FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13722-5E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90480/485 Series
MB90F481/F482/487/F488/V480/V485
s DESCRIPTION
The MB90480/485 series is a 16-bit general-purpose FUJITSU microcontroller designed for process control in consumer devices and other applications requiring high-speed real-time processing. The F2MC-16LX CPU core instruction set retains the AT architecture of the F2MC*1 family, with additional instructions for high-level languages, expanded addressing mode, enhanced multiply-drive instructions, and complete bit processing. In addition, a 32-bit accumulator is provided to enable long-word processing. The MB90480/485 series features embedded peripheral resources including 8/16-bit PPG, expanded I/O serial interface, UART, 10-bit A/D converter, 16-bit I/O timer, 8/16-bit up-counter, PWC timer, I2C*2 interface, DTP/external interrupt, chip select, and 16-bit reload timer. *1 : F2MC, an abbreviation for FUJITSU Flexible Microcontroller, is a registered trademark of FUJITSU, Ltd. *2 : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C stand a Specification as defined by Philips.
s PACKAGES
100-pin plastic QFP 100-pin plastic LQFP
(FPT-100P-M06)
(FPT-100P-M05)
MB90480/485 Series
s FEATURES
• Clock Minimum instruction execution time: 40.0 ns/6.25 MHz base frequency multiplied × 4 (25 MHz internal operating frequency/3.3 V ± 0.3 V) 62.5 ns/4 MHz base frequency multiplied × 4 (16 MHz internal operating frequency/3.0 V ± 0.3 V) PLL clock multiplier • Maximum memory space: 16 Mbyte • Instruction set optimized for controller applications Supported data types (bit, byte, word, or long word) Typical addressing modes (23 types) Enhanced signed multiplication/division instruction and RETI instruction functions 32-bit accumulator for enhanced high-precision calculation • Instruction set designed for high-level language (C) and multi-task operations System stack pointer adopted Instruction set compatibility and barrel shift instructions • Non-multiplex bus/multiplex bus compatible • Enhanced execution speed 4 byte instruction queue • Enhanced interrupt functions 8 levels setting with programmable priority, 8 external interrupts • Data transmission function (µDMA) Up to 16 channels • Embedded ROM Flash versions : 192 KB, 256 KB, MASK versions : 192 KB • Embedded RAM Flash versions : 4 KB, 6 KB, 10 KB, MASK versions : 10 KB • General purpose ports Up to 84 ports (Except MB90V480 : Includes 16 ports with input pull-up resistance, 16 ports with output open drain settings) • A/D converter 8-channel RC sequential comparison type (10-bit resolution, 3.68 µs conversion time (at 25 MHz) ) • I2C interface (MB90485 series only) : 1channel, P76/P77 Nch OD pin (without Pch) Do not apply high voltage in excess of recommended operating ranges to the Nch open drain pin (with Pch) in MB90V485. • µPG (MB90485 series only) : 1 channel • UART: 1 channel • I/O expanded serial interface (SIO) : 2 channels • 8/16-bit PPG: 3 channels (with 8-bit × 6 channel/16-bit × 3 channel mode switching function) • 8/16-bit up/down timer: 1 channel (with 8-bit × 2 channel/16-bit × 1-channel mode switching function) • PWC (MB90485 series only) : 3 channels (Capable of compare the inputs to two of the three) • 3 V/5 V I/F pin (MB90485 series only) P20 to P27, P30 to P37, P40 to P47, P70 to P77 • 16-bit reload timer: 1 channel • 16-bit I/O timer: 2-channel input capture, 6-channel output compare, 1-channel free run timer • On chip dual clock generator system • Low-power consumption mode With stop mode, sleep mode, CPU intermittent operation mode, watch mode, timebase timer mode • Packages: QFP 100/LQFP 100 • Process: CMOS technology • Power supply voltage: 3 V, single source (some ports can be operated by 5 V power supply at MB90485 series) 2
MB90480/485 Series
s PRODUCT LINEUP
• MB90480 series Part number Item ROM size RAM size MB90F481 FLASH 192 KB 4 KB Number of instructions Instruction bit length Instruction length Data bit length Minimum execution time MB90F482 FLASH 256 KB 6 KB MB90V480 16 KB
CPU function
: 351 : 8-bit, 16-bit : 1 byte to 7 bytes : 1-bit, 8-bits, 16-bits : 40 ns (25 MHz machine clock)
Ports UART 8/16-bit PPG timer 8/16-bit up/down counter/timer 16-bit free run timer 16-bit Output compare I/O timers (OCU) Input capture (ICU) DTP/external interrupt circuit Extended I/O serial interface Timebase timer
General-purpose I/O ports: up to 84 General-purpose I/O ports (CMOS output) General-purpose I/O ports (with pull-up resistance) General-purpose I/O ports (N-ch open drain) 1 channel, start-stop synchronized 8-bit × 6 channel/16-bit × 3 channel 6 event input pins, 8-bit up/down counters: 2 8-bit reload/compare registers: 2 Number of channels: 1 Overflow interrupt Number of channels: 6 Pin input factor: A match signal of compare register Number of channels: 2 Rewriting a register value upon a pin input (rising, falling, or both edges) Number of external interrupt channels: 8 (edge or level detection) 2 channels, embedded 18-bit counter Interrupt cycles: 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (at 4 MHz base oscillator) Conversion resolution: 8/10-bit, switchable One-shot conversion mode (converts selected channel 1 time only) Scan conversion mode (conversion of multiple consecutive channels, programmable up to 8 channels) Continuous conversion mode (repeated conversion of selected channels) Stop conversion mode (conversion of selected channels with repeated pause) Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (minimum value, at 4 MHz base oscillator) Sleep mode, stop mode, CPU intermittent mode, watch timer mode, timebase timer mode CMOS FLASH model Not included security function Evaluation model, user terminal, 3 V/5 V versions Included
A/D converter
Watchdog timer Low-power consumption (standby) modes Process Type Emulator power supply*
* : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply switching) about details. 3
MB90480/485 Series
• MB90485 series Part number Item ROM size RAM size MB90487*1 192 KB 10 KB Number of instructions Instruction bit length Instruction length Data bit length Minimum execution time MB90F488*2 FLASH 256 KB 10 KB MB90V485*1 16 KB
CPU function
: 351 : 8-bit, 16-bit : 1 byte to 7 bytes : 1-bit, 8-bits, 16-bits : 40 ns (25 MHz machine clock)
Ports
General-purpose I/O ports: up to 84 General-purpose I/O ports (CMOS output) General-purpose I/O ports (with pull-up resistance) General-purpose I/O ports (N-ch open drain) 1 channel, start-stop synchronized 8-bit × 6 channel/16-bit × 3 channel 6 event input pins, 8-bit up/down counters: 2 8-bit reload/compare registers: 2 Number of channels: 1 Overflow interrupt Number of channels: 6 Pin input factor: A match signal of compare register Number of channels: 2 Rewriting a register value upon a pin input (rising, falling, or both edges) Number of external interrupt channels: 8 (edge or level detection) 2 channels, embedded 1 ch 1 ch 3 ch 18-bit counter Interrupt cycles: 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (at 4 MHz base oscillator) Conversion resolution: 8/10-bit, switchable One-shot conversion mode (converts selected channel 1 time only) Scan conversion mode (conversion of multiple consecutive channels, programmable up to 8 channels) Continuous conversion mode (repeated conversion of selected channels) Stop conversion mode (conversion of selected channels with repeated pause) Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (minimum value, at 4 MHz base oscillator) Sleep mode, stop mode, CPU intermittent mode, watch timer mode, timebase timer mode CMOS
UART 8/16-bit PPG timer 8/16-bit up/down counter/timer 16-bit free run timer 16-bit Output compare I/O timers (OCU) Input capture (ICU) DTP/external interrupt circuit Extended I/O serial interface I C interface * µPG PWC Timebase timer
2 4
A/D converter
Watchdog timer Low-power consumption (standby) modes Process
(Continued)
4
MB90480/485 Series
(Continued)
Part number Item Type Emulator power supply*5 *1 : Under development *2 : Being planed *3 : 3 V/5 V I/F pin : All pins should be for 3 V power supply without P20 to P27, P30 to P37, P40 to P47, and P70 to P77. *4 : P76/P77 pins are Nch open drain pins (without Pch) at built-in I2C. However, MB90V485 uses the Nch open drain pin (with Pch) . *5 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details. Note : As for MB90V485, Input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/µPG/I2C become CMOS input. MB90487*1 MASK model 3 V/5 V power supply*3 MB90F488*2 FLASH model 3 V/5 V power supply*3 Included security function MB90V485*1 Evaluation model 3 V/5 V power supply*3 Included
5
MB90480/485 Series
s PIN ASSIGNMENT
(TOP VIEW)
P17/AD15/D15 P16/AD14/D14 P15/AD13/D13 P14/AD12/D12 P13/AD11/D11 P12/AD10/D10 P11/AD09/D09 P10/AD08/D08 P07/AD07/D07 P06/AD06/D06 P05/AD05/D05 P04/AD04/D04 P03/AD03/D03 P02/AD02/D02 P01/AD01/D01 P00/AD00/D00 VCC3 X1 X0 VSS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
* : These are the pins for MB90485 series. The pins for MB90480 series are P36/A06, P37/A07, P43/A11, P44/A12, P45/A13, P75, P76 and P77. Note : MB90485 series only • I2C pin P77 and P76 are Nch open drain pin (without Pch) . However, MB90V485 uses the Nch open drain pin (with Pch) . • P20 to P27, P30 to P37, P40 to P47 and P70 to P77 also used as 3 V/5 V I/F pin. • As for MB90V485, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/ µPG/I2C become CMOS input. 6
P74/TOT0 P75/PWC2* P76/SCL* P77/SDA* AVCC AVRH AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 Vss P64/AN4 P65/AN5 P66/AN6 P67/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P20/A16 P21/A17 P22/A18 P23/A19 P24/A20/PPG0 P25/A21/PPG1 P26/A22/PPG2 P27/A23/PPG3 P30/A00/AIN0 P31/A01/BIN0 VSS P32/A02/ZIN0 P33/A03/AIN1 P34/A04/BIN1 P35/A05/ZIN1 P36/A06/PWC0* P37/A07/PWC1* P40/A08/SIN2 P41/A09/SOT2 P42/A10/SCK2 P43/A11/MT00* P44/A12/MT01* VCC5 P45/A13/EXTC* P46/A14/OUT4 P47/A15/OUT5 P70/SIN0 P71/SOT0 P72/SCK0 P73/TIN0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
X0A X1A P57/CLK RST P56/RDY P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE PA3/OUT3 PA2/OUT2 PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/PPG5 P94/PPG4 P93/FRCK/ADTG/CS3 P92/SCK1/CS2 P91/SOT1/CS1 P90/SIN1/CS0 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3 P82/IRQ2 MD2
(FPT-100P-M06)
MB90480/485 Series
(TOP VIEW)
P22/A18 P23/A19 P24/A20/PPG0 P25/A21/PPG1 P26/A22/PPG2 P27/A23/PPG3 P30/A00/AIN0 P31/A01/BIN0 VSS P32/A02/ZIN0 P33/A03/AIN1 P34/A04/BIN1 P35/A05/ZIN1 P36/A06/PWC0* P37/A07/PWC1* P40/A08/SIN2 P41/A09/SOT2 P42/A10/SCK2 P43/A11/MT00* P44/A12/MT01* VCC5 P45/A13/EXTC* P46/A14/OUT4 P47/A15/OUT5 P70/SIN0
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
P21/A17 P20/A16 P17/AD15/D15 P16/AD14/D14 P15/AD13/D13 P14/AD12/D12 P13/AD11/D11 P12/AD10/D10 P11/AD09/D09 P10/AD08/D08 P07/AD07/D07 P06/AD06/D06 P05/AD05/D05 P04/AD04/D04 P03/AD03/D03 P02/AD02/D02 P01/AD01/D01 P00/AD00/D00 VCC3 X1 X0 VSS X0A X1A P57/CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
RST P56/RDY P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE PA3/OUT3 PA2/OUT2 PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/PPG5 P94/PPG4 P93/FRCK/ADTG/CS3 P92/SCK1/CS2 P91/SOT1/CS1 P90/SIN1/CS0 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3
* : These are the pins for MB90485 series. The pins for MB90480 series are P36/A06, P37/A07, P43/ A11, P44/A12, P45/A13, P75, P76 and P77. Note : MB90485 series only • I2C pin P77 and P76 are Nch open drain pin (without Pch) . However, MB90V485 uses the Nch open drain pin (with Pch) . • P20 to P27, P30 to P37, P40 to P47 and P70 to P77 also used as 3 V/5 V I/F pin. • As for MB90V485, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/ µPG/I2C become CMOS input.
P71/SOT0 P72/SCK0 P73/TIN0 P74/TOT0 P75/PWC2* P76/SCL* P77/SDA* AVCC AVRH AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1 MD2 P82/IRQ2
(FPT-100P-M05)
7
MB90480/485 Series
s PIN DESCRIPTIONS
Pin No. LQFP*1 QFP*2 80 81 78 77 75 82 83 80 79 77 Pin name X0 X1 X0A X1A RST P00 to P07 83 to 90 85 to 92 AD00 to AD07 D00 to D07 P10 to P17 91 to 98 93 to 100 AD08 to AD15 D08 to D15 P20 to P23 99, 100, 1,2 E C (CMOS) C (CMOS) Circuit type A A A A B Oscillator pin Oscillator pin 32 kHz oscillator pin 32 kHz oscillator pin Reset input pin This is a general purpose I/O port. A setting in the pull-up resistance setting register (RDR0) can be used to apply pull-up resistance (RD00RD07 = “1”) . (Disabled when pin is set for output.) In multiplex mode, these pins function as the external address/data bus low I/O pins. In non-multiplex mode, these pins function as the external data bus low output pins. This is a general purpose I/O port. A setting in the pull-up resistance setting resister (RDR1) can be used to apply pull-up resistance (RD10RD17 = “1”) . (Disabled when pin is set for output.) In multiplex mode, these pins function as the external address/data bus high I/O pins. In non-multiplex mode, these pins function as the external data bus high output pins. This is a general purpose I/O port. When the bits of external address output control register (HACR) are set to "1" in external bus mode, these pins function as general purpose I/O ports. When the bits of external address output control register (HACR) are set to "0" in multiplex mode, these pins function as address high output pins (CMOS/H) (A16-A19). When the bits of external address output control register (HACR) are set to "0" in non-multiplex mode, these pins function as address high output pins (A16-A19). This is a general purpose I/O port. When the bits of external address output control register (HACR) are set to "1" in external bus mode, these pins function as general purpose I/O ports. When the bits of external address output control register (HACR) are set to "0" in multiplex mode, these pins function as address high output pins (A20-A23). When the bits of external address output control register (HACR) are set to "0" in non-multiplex mode, these pins function as address high output pins (A20-A23). PPG timer output pins. This is a general purpose I/O port. E (CMOS/H)
In non-multiplex mode, this pin functions as an external address pin.
Function
1 to 4
A16 to A19
A16 to A19
P24 to P27
A20 to A23 3 to 6 5 to 8 A20 to A23
PPG0 to PPG3
E
(CMOS/H)
P30 7 9 A00 AIN0
8/16-bit up/down timer input pin (channel 0) .
(Continued)
8
MB90480/485 Series
Pin No. Pin name LQFP*1 QFP*2 P31 8 10 A01 BIN0 P32 A02 10 12 ZIN0 P33 A03 11 13 AIN1 P34 A04 12 14 BIN1 P35 A05 13 15 ZIN1 P36, P37 A06, A07 P36, P37 14 16 15 17*3 A06, A07 PWC0, PWC1 P40 A08 16 18 SIN2 P41 17 19 A09 SOT2 P42 A10 18 20 SCK2 P43, P44 A11, A12 P43, P44 19 21 20 22 A11, A12 MT00, MT01
Circuit type E
(CMOS/ H)
Function This is a general purpose I/O port. In non-multplex mode, this pin functions as an external address pin. 8/16-bit up/down counter input pin (channel 0) . This is a general purpose I/O port. In non-multiplex mode, this pin functions as an external address pin. 8/16-bit up/down counter input pin (channel 0) This is a general purpose I/O port. In non-multiplex mode, this pin functions as an external address pin. 8/16-bit up/down counter input pin (channel 1) . This is a general purpose I/O port. In non-multiplex mode, this pin functions as an external address pin. 8/16-bit up/down counter input pin (channel 1) . This is a general purpose I/O port. In non-multiplex mode, this pin functions as an external address pin. 8/16-bit up/down counter input pin (channel 1) MB90480 This is a general purpose I/O port. series In non-multiplex mode, this pin functions as an external address pin. This is a general purpose I/O port. MB90485 In non-multiplex mode, this pin functions as an external address pin.
series
E
(CMOS/ H)
E
(CMOS/ H)
E
(CMOS/ H)
E
(CMOS/ H)
D (CMOS) E (CMOS/ H) G
This is a PWC input pin. This is a general purpose I/O port.
(CMOS/ In non-multiplex mode, this pin functions as an external address pin. H) Simple serial I/O input pin.
This is a general purpose I/O port. F In non-multiplex mode, this pin functions as an external address pin. (CMOS) Simple serial I/O output pin. This is a general purpose I/O port. G (CMOS/ In non-multiplex mode, this pin functions as an external address pin. H) Simple serial I/O clock input/output pin. F MB90480 This is a general purpose I/O port. (CMOS) series In non-multiplex mode, this pin functions as an external address pin. This is a general purpose I/O port. MB90485 In non-multiplex mode, this pin functions as an external address pin. F (CMOS) series µPG output pin.
(Continued)
9
MB90480/485 Series
Pin No. LQFP* QFP*
1 2
Pin name P45 A13
Circuit type
Function
F MB90480 This is a general purpose I/O port. (CMOS) series In non-multiplex mode, this pin functions as an external address pin.
MB90485 (CMOS/ In non-multiplex mode, this pin functions as an external address pin. series H)
22
24
P45 A13 EXTC*3 P46, P47
G
This is a general purpose I/O port. µPG input pin (MB90485 series only) .
This is a general purpose I/O port. F In non-multiplex mode, this pin functions as an external address pin. (CMOS) Output compare event output pins. This is a general purpose I/O port. In external bus mode, this pin functions as the ALE pin. D (CMOS) In external bus mode, this pin functions as the address load enable (ALE) signal pin. D (CMOS) In external bus mode, this pin functions as the read strobe output (RD) signal pin. This is a general purpose I/O port. In external bus mode, when the WRE pin in the EPCR register is set to “1”, this pin functions as the WRL pin. This is a general purpose I/O port. In external bus mode, this pin functions as the RD pin.
23 24
25 26
A14, A15 OUT4/ OUT5 P50
68
70 ALE P51
69
71 RD P52
70
72 WRL
D (CMOS) In external bus mode, this pin functions as the lower data write strobe output (WRL) pin. When the WRE bit in the EPCR register is set to “0”, this pin functions as a general purpose I/O port. This is a general purpose I/O port. In external bus mode with 16-bit bus width, when the WRE bit in the EPCR register is set to “1”, this pin functions as the WRH pin.
P53 71 73 WRH
D (CMOS) In external bus mode with 16-bit bus width, this pin functions as the upper data write strobe output (WRH) pin. When the WRE bit in the EPCR register is set to “0”, this pin functions as a general purpose I/O port. This is a general purpose I/O port. In external bus mode, when the HDE bit in the EPCR register is set to “1”, this pin functions as the HRQ pin.
P54 72 74 HRQ P55 73 75 HAK
D (CMOS) In external bus mode, this pin functions as the hold request input (HRQ) pin. When the HDE bit in the EPCR register is set to “0”, this pin functions as a general purpose I/O port. This is a general purpose I/O port. In external bus mode, when the HDE bit in the EPCR register is set to “1”, this pin functions as the HAK pin.
D (CMOS) In external bus mode, this pin functions as the hold acknowledge (HAK) pin. When the HDE bit in the EPCR register is set to “0”, this pin functions as a general purpose I/O port.
(Continued)
10
MB90480/485 Series
Pin No. LQFP*
1
QFP*
2
Pin name P56
Circuit type
Function This is a general purpose I/O port. In external bus mode, when the RYE bit in the EPCR register is set to “1”, this pin functions as the RDY pin.
74
76 RDY P57
D (CMOS) In external bus mode, this pin functions as the external ready (RDY) input pin. When the RYE bit in the EPCR register is set to “0”, this pin functions as a general purpose I/O port. D (CMOS) In external bus mode, this pin functions as the machine cycle clock (CLK) output pin. When the CKE bit in the EPCR register is set to “0”, this pin functions as a general purpose I/O port. This is a general purpose I/O port. In external bus mode, when the CKE bit in the EPCR register is set to “1”, this pin functions as the CLK pin.
76
78 CLK
36 to 39 41 to 44 25 26 27
38 to 41 43 to 46 27 28 29
These are general purpose I/O ports. H (CMOS) These are the analog input pins. AN0 to AN3 These are general purpose I/O ports. H (CMOS) These are the analog input pins. AN4 to AN7 P70 SIN0 P71 SOT0 P72 SCK0 P73 G
(CMOS/ H)
P60 to P63
P64 to P67
This is a general purpose I/O port. This is the UART data input pin.
This is a general purpose I/O port. F (CMOS) This is the UART data output pin. G
(CMOS/ H)
This is a general purpose I/O port. This is the UART clock I/O pin. This is a general purpose I/O port. This is the 16-bit reload timer event input pin.
G
(CMOS/ H)
28 29
30 31
TIN0 P74 TOT0 P75
This is a general purpose I/O port. F (CMOS) This is the 16-bit reload timer output pin. F MB90480 series This is a general purpose I/O port. (CMOS) G (CMOS/ H)
MB90485 series This is a PWC input pin.
30
32
P75 PWC2*3 P76
This is a general purpose I/O port.
F (CMOS) MB90480 This is a general purpose I/O port. series I (NMOS/ H) MB90485 2 series Serves as the I C interface data I/O pin. During operation of the
31
33
P76 SCL*3 P77
This is a general purpose I/O port.
I2C interface, leave the port output in a high impedance state.
F (CMOS) MB90480 This is a general purpose I/O port. series I (NMOS/ H) MB90485 2 series Serves as the I C interface data I/O pin. During operation of the
32
34
P77 SDA*3
This is a general purpose I/O port.
I2C interface, leave the port output in a high impedance state.
45, 46
47, 48
P80, P81 IRQ0, IRQ1
E These are general purpose I/O ports. (CMOS/ External interrupt input pins. H)
(Continued)
11
MB90480/485 Series
(Continued) Pin No. LQFP*1 QFP*2
50 to 55 52 to 57
Pin name
Circuit type
Function
P82 to P87 These are general purpose I/O ports. E (CMOS/H) External interrupt input pins. IRQ2 to IRQ7 This is a general purpose I/O port. P90 E SIN1 Simple serial I/O data input pin. 56 58 (CMOS/H) CS0 Chip select 0. P91 This is a general purpose I/O port. D 57 59 SOT1 Simple serial I/O data output pin. (CMOS) CS1 Chip select 1. This is a general purpose I/O port. P92 E SCK1 Simple serial I/O data input/output pin. 58 60 (CMOS/H) CS2 Chip select 2. This is a general purpose I/O port. P93 When the free run timer is in use, this pin functions as the external FRCK clock input pin. E 59 61 (CMOS/H) When the A/D converter is in use, this pin functions as the external ADTG trigger input pin. CS3 Chip select 3. P94 This is a general purpose I/O port. D 60 62 (CMOS) PPG timer output pin. PPG4 P95 This is a general purpose I/O port. D 61 63 (CMOS) PPG timer output pin. PPG5 P96 This is a general purpose I/O port. E 62 64 (CMOS/H) Input capture channel 0 trigger input pin. IN0 This is a general purpose I/O port. P97 E 63 65 (CMOS/H) Input capture channel 1 trigger input pin. IN1 PA0 to PA3 These are general purpose I/O ports. D 64 to 67 66 to 69 (CMOS) Output compare event output pins. OUT0 to OUT3 A/D converter power supply pin. 33 35 AVCC 34 36 AVRH A/D converter external reference voltage supply pin. A/D converter power supply pin. 35 37 AVSS J (CMOS/ Operating mode selection input pins. 47 to 49 49 to 51 MD0 to MD2 H) 82 84 VCC3 3.3 V ± 0.3 V power supply pins (VCC3) . MB90480 3.3 V ± 0.3 V power supply pin. seriesv Usually, use VCC = VCC3 = VCC5 as a 3 V power supply. 3 V/5 V power supply pin. 21 23 VCC5 5 V power supply pin when P20 to P27, P30 to P37, MB90485 P40 to P47, P70 to P77 are used as 5 V I/F pins. series Usually, use VCC = VCC3 = VCC5 as a 3 V power supply (when the 3 V power supply is used alone) . 9 11 Power supply input pins (GND) . 40 42 VSS 79 81 *1 : LQFP : FPT-100P-M05 *2 : QFP : FPT-100P-M06 *3 : As for MB90V485, input pins become CMOS input. 12
MB90480/485 Series
s I/O CIRCUIT TYPES
Type
X1, X1A
Circuit
Remarks
X0, X0A
A Standby control signal
Oscillator feedback resistance X1, X0 : approx. 1 MΩ X1A, X0A : approx. 10 MΩ with standby control
B
Hysteresis input with pull-up resistance Resistance : approx. 50 kΩ
CTL
C
With input pull-up resistance control Resistance : approx. 50 kΩ CMOS level input/output
CMOS
D
CMOS
CMOS level input/output
E
CMOS
Hysteresis input CMOS level output
(Continued)
13
MB90480/485 Series
(Continued) Type
Circuit
Remarks
Open drain control signal F
CMOS level input/output with open drain control
CMOS
Open drain control signal G
CMOS level output Hysteresis input With open drain control
H
CMOS
CMOS level input/output Analog input
Analog input
Digital output I Hysteresis input Nch open drain output
FLASH model
Control signal J Mode input Diffusion resistance MASK model Hysteresis input
(FLASH model) CMOS level input with high voltage control for flash testing
(Mask model) Hysteresis input
14
MB90480/485 Series
s HANDLING DEVICES
1. Be careful never to exceed maximum rated voltages (preventing latchup)
In CMOS IC devices, a condition known as latchup may occur if voltages higher than VCC or loser than VSS are applied to input or output pins other than medium-or high-voltage pins, or if the voltage applied between VCC and VSS exceeds the rated voltage level. When latchup occurs, the power supply current increases rapidly causing the possibility of thermal damage to circuit elements. Therefore it is necessary to ensure that maximum ratings are not exceeded in circuit operation. Similarly, when turning the analog power supply on or off, it is necessary to ensure that the analog power supply voltages (AVCC and AVRH) and analog input voltages do not exceed the digital power supply (VCC) .
2. Treatment of unused pins
Leaving unused input pins unconnected can cause abnormal operation or latchup, leading to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/ output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins.
3. Notes on Using External Clock
Even when using an external clock signal, an oscilltion stabilization delay is applied after a power-on reset or when recovering from sub-clock or stop mode. When using an external clock, 25 MHz should be the upper frequency limit. The following figure shows a sample use of external clock signals.
X0
OPEN
X1
4. Treatment of Power Supply Pins (VCC/VSS)
When multiple VCC/VSS pins are present, device design considerations for prevention of latch-up and unwanted electromagnetic interference, abnormal storobe signal operation due to ground level rise, and conformity with total output current ratings require that all power supply pins must be externally connected to power supply or ground. Consideration should be given to connecting power supply sources to the VCC/VSS terminals of this device with as low impedane as possible. It is also recommended that a bypass capacitor of approximately 0.1 µF be placed between the VCC and VSS lines as close to this device as possible.
5. Crystal Oscillator Circuits
Noise around the X0/X1, or X0A/X1A pins may cause this device to operate abnormally. In the interest of stable operation it is strongly recommended that printed circuit artwork places ground bypass capacitors as close as possible to the X0/X1, X0A/X1A and crystal oscillator (or ceramic oscillator) and that oscillator lines do not cross the lines of other circuits.
15
MB90480/485 Series
6. Notes on during operation of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed.
7. Proper power-on/off sequence
The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be turned on after the digital power supply (VCC) is turned on. The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be shut off before the digital power supply (VCC) is shut off. Care should be taken that AVRH does not exceed AVCC. Even when pins used as analog input pins are doubled as input ports, be sure that the input voltage does not exceed AVCC.
8. Treatment of power supply pins on models with A/D converters
Even when the A/D converters are not in use, be sure to make the necessary connections AVCC = AVRH = VCC, and AVSS = VSS.
9. Precautions when turning the power supply on
In order to prevent abnormal operation in the chip’s internal step-down circuits, a voltage rise time during poweron of 50 µs (0.2 V to 2.7 V) or greater should be assured.
10. Supply Voltage Stabilization
Even within the operating range of VCC supply voltage, rapid voltage fluctuations may cause abnormal operation. As a standard for power supply voltage stability, it is recommended that the peak-to-peak VCC ripple voltage at commercial supply frequency (50 Hz to 60 Hz) be 10 % or less of VCC, and that the transient voltage fluctuation be no more than 0.1 V/ms or less when the power supply is turned on or off.
11. Notes on Using Power Supply
Only the MB90485 series usually uses a 3 V power supply. By setting VCC3 = 3 V power supply and VCC5 = 5 V power supply, P20 to P27, P30 to P37, P40 to P47 and P70 to P77 can be intefaced as 5 V power supplies separately from the main 3 V power supply. Note that the analog power supplies (such as AVCC and AVSS) for the A/D converter can be used only as 3 V power supplies. Programming into FLASH memory must be performed at an operating voltage (VCC) between 3.13 V and 3.6 V.
12. Treatment of N.C. pins
N.C. (internally connected) pins should always be left open.
13. When the MB90480/485 series microcontroller is used as a single system
When the MB90480/485 series microcontroller is used as a single system, use connections so the X0A = VSS, and X1A = Open.
14. Writing to FLASH memory
For serial writing to FLASH memory, always ensure that the operating voltage VCC is between 3.13 V and 3.6 V. For normal writing to FLASH memory, always ensure that the operating voltage VCC is between 3.0 V and 3.6 V.
16
MB90480/485 Series
s BLOCK DIAGRAM
X0, X1, RST X0A, X1A MD2, MD1, MD0 8
Clock control Circuit
RAM
CPU F2MC16LX series core
Interrupt controller
PPG0, PPG1 PPG2, PPG3 PPG4, PPG5 AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1
ROM
8/16 bit PPG
µDMA
8/16 bit U/D counter Communication prescaler
2
F2MC-16LX Bus
SIN0 SOT0 SCK0 SIN1, SIN2 SOT1, SOT 2 SCK1, SCK2
UART
µPG
EXTC MT00 MT01
I/O extended serial interface × 2ch
Chip select Input/output timer
CS0, CS1, CS2, CS3
AVCC AVRH AVSS ADTG AN0 to AN7
16 bit input capture × 2ch A/D converter ( 10 bit ) 16 bit output compare × 2ch 16 bit free-run timer 16 bit reload timer
IN0, IN1 OUT0, OUT1, OUT2, OUT3, OUT4, OUT5 TIN0 TOT0 SCL SDA 8
PWC0 PWC1 PWC2
PWC × 3ch
I2C interface
External interrupt
IRQ0 to IRQ7
I/O port
8 P00 8 P10 8 P20 8 P30 8 P40 8 P50 8 P60 8 P70 8 P80 8 P90 4 PA0
to
P07
to
P17
to
P27
to
P37
to
P47
to
P57
to
P67
to
P77
to
P87
to
P97
to
PA3
: Only MB90485 series
P00 to P07 (8 pins) P10 to P17 (8 pins) P40 to P47 (8 pins) P70 to P75 (6 pins)
: with an input pull-up resistance setting register. : with an input pull-up resistance setting register. : with an open drain setting register. : with an open drain setting register.
MB90485 series only • I2C pin P77 and P76 are Nch open drain pin (without Pch) . However, MB90V485 uses the Nch open drain pin (with Pch) . • P20 to P27, P30 to P37, P40 to P47 and P70 to P77 also used as 3 V/5 V I/F pin. • As for MB90V485, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/ µPG/I2C become CMOS input. Note : In the above diagram, I/O ports share internal function blocks and pins. However, when a set of pins is used with an internal module, it cannot also be used as an I/O port. 17
MB90480/485 Series
s MEMORY MAP
Single chip
FFFFFFH
Internal ROM external bus ROM area
External ROM external bus
ROM area
Address #1
010000H
Address #2
ROM area FF bank image
ROM area FF bank image *
Address #3
RAM 000100H 0000D0H
Register
RAM
Register
RAM
Register
Peripheral
000000H
Peripheral : External
Peripheral : Access inhibited
: internal
* : In models where address #3 overlaps with address #2, this external area does not exist. Model MB90F481 MB90F482 MB90487 MB90F488 MB90V480 MB90V485 Address #1 FC0000H * FC0000H FD0000H FC0000H (FC0000H) (FC0000H) 004000H or 008000H, selected by the MS bit in the ROMM register Address #2 Address #3 001100H 001900H 002900H 002900H 004000H 004000H
* : No memory cells from FC0000H to FC7FFFH and FE0000H to FE7FFFH. The upper part of the 00 bank is set up to mirror the image of FF bank ROM, to enable efficient use of small model C compilers. Because the lower 16-bit address of the FF bank and the lower 16-bit address of the 00 bank is the same, enabling reference to tables in ROM without the “far” pointer declaration. For example, in accessing address 00C000H it is actually the contents of ROM at FFC000H that are accessed. If the MS bit in the ROMM register is set to “0”, the ROM area in the FF bank will exceed 48 K bytes and it is not possible to reflect the entire area in the image in the 00 bank. Therefore the image from FF4000H to FFFFFFH is reflected in the 00 bank and the area from FF0000H to FF3FFFH can be seen in the FF bank only.
18
MB90480/485 Series
s F2MC-16L CPU PROGRAMMING MODEL
• Dedicated registers
AH AL USP SSP PS PC DPR PCB DTB USB SSB ADB 8 bit 16 bit 32 bit
Accumulator User stack pointer System stack pointer Processor status Program counter Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register
• General purpose registers
MSB 000180H + RP × 10H RW0 RL0 RW1 RW2 RL1 RW3 R1 R3 R5 R7 R0 R2 R4 R6 RW4 RL2 RW5 RW6 RL3 RW7 16 bit LSB
• Processor status
15 PS ILM 13 12 RP 87 CCR 0
19
MB90480/485 Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20 Register name Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register Up/down timer input enable register Interrupt/DTP enable register Interrupt/DTP source register Request level setting register Request level setting register Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Port A direction register Port 4 output pin register Port 0 input resistance register Port 1 input resistance register Port 7 output pin register Analog input enable register
Abbreviated Read/ register name Write
Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A U/D timer input control DTP/external interrupts Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port 4 (OD control) Port 0 (Pull-up) Port 1 (Pull-up) Port 7 (OD control) Port 5, A/D
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (MB90480 series) 11XXXXXXB (MB90485 series) XXXXXXXXB XXXXXXXXB - - - - XXXXB XX 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (MB90480 series) XX0 0 0 0 0 0B (MB90485 series) 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - - - 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (MB90480 series) XX0 0 0 0 0 0B (MB90485 series) 1 1 1 1 1 1 1 1B
PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA UDRE ENIR EIRR ELVR DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 DDRA ODR4 RDR0 RDR1 ODR7 ADER
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
(Continued)
MB90480/485 Series
Abbreviated register name
Address 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H
Register name Serial mode register Serial control register Serial input/output register Serial data register
Read/ Write R/W R/W R/W R/W
Resource name
Initial value 0 0 0 0 0 X 0 0B
SMR SCR SIDR/SODR SSR
UART
0 0 0 0 0 1 0 0B XXXXXXXXB 0 0 0 0 1 0 0 0B
(Reserved area) Communication prescaler control register Serial mode control status register Serial mode control status register Serial data register Communication prescaler control register Serial mode control status register Serial mode control status register Serial data register Communication prescaler control register Reload register L Reload register H Reload register L Reload resister H Reload register L Reload register H Reload register L Reload register H Reload register L Reload register H Reload register L Reload register H PPG0 operating mode control register PPG1 operating mode control register PPG2 operating mode control register PPG3 operating mode control register PPG4 operating mode control register PPG5 operating mode control register PPG0, 1 output control register PPG2, 3 output control register CDCR SMCS SMCS SDR0 SDCR0 SMCS SMCS SDR1 SDCR1 PPLL0 PPLH0 PPLL1 PPLH1 PPLL2 PPLH2 PPLL3 PPLH3 PPLL4 PPLH4 PPLL5 PPLH5 PPGC0 PPGC1 PPGC2 PPGC3 PPGC4 PPGC5 PPG01 PPG23 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8/16-bit PPG 8/16-bit PPG 8/16-bit PPG (ch0 to ch5) Communication prescaler (SCI2) SCI2 (ch1) Communication prescaler (SCI1) SCI1 (ch0) Communication prescaler (UART) 0 0 - - 0 0 0 0B - - - - 0 0 0 0B 0 0 0 0 0 0 1 0B XXXXXXXXB 0 - - - 0 0 0 0B - - - - 0 0 0 0B 0 0 0 0 0 0 1 0B XXXXXXXXB 0 - - - 0 0 0 0B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 X 0 0 0XX 1B 0 X 0 0 0 0 0 1B 0 X 0 0 0XX 1B 0 X 0 0 0 0 0 1B 0 X 0 0 0XX 1B 0 X 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
(Reserved area) (Reserved area)
(Continued)
21
MB90480/485 Series
Abbreviated Read/ register Write name
Address 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H
Register name PPG4, 5 output control register
Resource name 8/16-bit PPG
Initial value 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
PPG45 (Reserved area) ADCS1 ADCS2 ADCR1 ADCR2 OCCP0 OCCP1 OCCP2 OCCP3 OCCP4 OCCP5 OCS0 OCS1 OCS2 OCS3 OCS4 OCS5 IPCP0 IPCP1 ICS01 (Reserved area) TCDT TCDT TCCS TCCS CPCLR
R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W R/W R/W
Control status register Data register Output compare register (ch0) lower digits Output compare register (ch0) upper digits Output compare register (ch1) lower digits Output compare register (ch1) upper digits Output compare register (ch2) lower digits Output compare register (ch2) upper digits Output compare register (ch3) lower digits Output compare register (ch3) upper digits Output compare register (ch4) lower digits Output compare register (ch4) upper digits Output compare register (ch5) lower digits Output compare register (ch5) upper digits Output compare control register (ch0) Output compare control register (ch1) Output compare control register (ch2) Output compare control register (ch3) Output compare control register (ch4) Output compare control register (ch5) Input capture data register (ch0) lower digits Input capture data register (ch0) upper digits Input capture data register (ch1) lower digits Input capture data register (ch1) upper digits Input capture control register Timer counter data register lower digits Timer counter data register upper digits Timer control status register Timer control status register Compare clear register lower digits Compare clear register upper digits
A/Dconverter
0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 XXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
16-bit output timer 0 0 0 0 0 0 0 0B output compare 0 0 0 0 0 0 0 0B (ch0 to ch5) 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 - - 0 0B - - - 0 0 0 0 0B 0 0 0 0 - - 0 0B - - - 0 0 0 0 0B 0 0 0 0 - - 0 0B - - - 0 0 0 0 0B XXXXXXXXB 16-bit output timer input capture (ch0, ch1) XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 16-bit output timer 0 0 0 0 0 0 0 0B free run timer 0 - - 0 0 0 0 0B XXXXXXXXB XXXXXXXXB (Continued)
22
MB90480/485 Series
Address 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H* 77H* 78H* 79H* 7AH* 7BH* 7CH* 7DH* 7EH* 7FH* 80H* 81H* 82H* 83H 84H* 85H 86H* 87H 88H* 89H* 8AH* 8BH* 8CH* 8DH 8EH* 8FH to 9BH 9CH Register name Up/down count register ch0 Up/down count register ch1 Reload/compare register ch0 Reload/compare register ch1 Counter control register lower digits ch0 Counter control register upper digits ch0 ROM mirror function select register Counter control register lower digits ch1 Counter control register upper digits ch1 Counter status register ch0 Counter status register ch1
Abbreviated Read/ register name Write
Resource name
Initial value 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 X 0 0 X 0 0 0B 0 0 0 0 0 0 0 0B ------01B 0 X 0 0 X 0 0 0B - 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 XB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 XB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 XB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - - - - - 0 0B - - - - - - 0 0B - - - - - - 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - 0 X X X X XB - X X X X X X XB XXXXXXXXB 0 0 0 0 0 - - -B 0 0 0 0 0 0 0 0B (Continued) 23
UDCR0 R UDCR1 R RCR0 W 8/16-bit up/down timer counter RCR1 W CCRL0 R/W CCRH0 R/W (Reserved area) ROMM R/W ROM mirroring function CCRL1 R/W 8/16-bit up/down timer CCRH1 R/W counter CSR0 R/W (Reserved area) CSR1 R/W 8/16-bit UDC (Reserved area) PWCSR0 PWCR0 PWCSR1 PWCR1 PWCSR2 PWCR2 R/W PWC timer (ch0) R/W R/W PWC timer (ch 1) R/W R/W PWC timer (ch2) R/W PWC (ch0) PWC (ch1) PWC (ch2)
PWC control status register PWC data buffer register PWC control status register PWC data buffer register PWC control status register PWC data buffer register Dividing ratio control register Dividing ratio control register Dividing ratio control register Bus status register Bus control register Bus clock control register Bus address register Bus data register µPG control status register µDMA status register
DIVR0 R/W (Reserved area) DIVR1 R/W (Reserved area) DIVR2 R/W (Reserved area) IBSR R IBCR R/W ICCR R/W IADR R/W IDAR R/W (Reserved area) PGCSR R/W (Disabled) DSRL R/W
I2C
µPG µDMA
MB90480/485 Series
Abbreviated register name
Address 9DH 9EH 9FH A0H A1H A2H, A3H A4H A5H A6H A7H A8H A9H AAH ABH ACH ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H
Register name µDMA status register Program address detection control status resister Dilayed interrupt source general/ cancel register Low-power consumption mode control register Clock select register µDMA stop status register Automatic ready function select register External address output control register Bus control signal control register Watchdog timer control register Timebase timer control register Watch timer control register µDMA enable area µDMA enable area Flash memory control status register
Read/ Write R/W R/W R/W R/W R/W
Resource name µDMA
Initial value 0 0 0 0 0 0 0 0B
DSRH PACSR DIRR LPMCR CKSCR
Address match 0 0 0 0 0 0 0 0B detection function Delayed interruput generator module Low-power operation low-power operation µDMA External pins External pins External pins Watchdog timer Timebase timer Watch timer µDMA µDMA Flash memory interface Chip select function - - - - - - - 0B 0 0 0 1 1 0 0 0B 1 1 1 1 1 1 0 0B
(Reserved area) DSSR ARSR HACR EPCR WDTC TBTC WTC DERL DERH FMCR (Disabled) Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 interrupt control register 07 Interrput control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 Chip select area mask register ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 CMR0 W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W R/W X X X X 0 1 1 1B X X X X 0 1 1 1B X X X X 0 1 1 1B X X X X 0 1 1 1B X X X X 0 1 1 1B X X X X 0 1 1 1B X X X X 0 1 1 1B X X X X 0 1 1 1B X X X X 0 1 1 1B X X X X 0 1 1 1B X X X X 0 1 1 1B X X X X 0 1 1 1B X X X X 0 1 1 1B X X X X 0 1 1 1B X X X X 0 1 1 1B X X X X 0 1 1 1B 00001111B R/W W W W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0B 0 0 1 1 - - 0 0B * * * * * * * *B 1 0 0 0 * 1 0 -B XXXXX 1 1 1B 1 X X 0 0 1 0 0B 1 0 0 0 1 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 X 0 0 0 0B
(Reserved area)
(Continued)
24
MB90480/485 Series
(Continued)
Address C1H C2H C3H C4H C5H C6H C7H C8H C9H CAH CBH CCH CDH CEH CFH D0H to FFH 100H to #H 1FF0H 1FF1H 1FF2H 1FF3H 1FF4H 1FF5H Program address detection resister 0 (Low order address) Program address detection resister 0 (Middle order address) Program address detection resister 0 (High order address) Program address detection resister 1 (Low order address) Program address detection resister 1 (Middle order address) Program address detection resister 1 (High order address) PADR1 R/W Address match detection function XXXXXXXXB PADR0 R/W Address match detection function XXXXXXXXB PLL output control register Register name Chip select area register Chip select area mask register Chip select area register Chip select area mask register Chip select area register Chip select area mask register Chip select area register Chip select control register Chip select active level register Timer control status register 16-bit timer register/ 16-bit reload register
Abbreviated register name
Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Resource name
Initial value 1 1 1 1 1 1 1 1B 00001111B 1 1 1 1 1 1 1 1B 00001111B 1 1 1 1 1 1 1 1B 00001111B 1 1 1 1 1 1 1 1B - - - - 0 0 0 *B - - - - 0 0 0 0B 0 0 0 0 0 0 0 0B - - - - 0 0 0 0B XXXXXXXXB
CAR0 CMR1 CAR1 CMR2 CAR2 CMR3 CAR3 CSCR CALR TMCSR
TMR/TMRLR
16-bit reload timer R/W
(Reserved area) PLLOS (External area) (RAM area) W Low-power operation - - - - - - X 0B
* : These registers are only for MB90485 series. They are used as the reserved area on MB90480 series. Descriptions for read/write R/W : Readable and writable R : Read only W : Write only Descriptions for initial value 0 : The initila value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. : This bit is not used. * : The initial value of this bit is “1” or “0”. The value depends on the mode pin (MD2, MD1 and MD0) . 25
MB90480/485 Series
s INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
Interrupt source Reset INT9 instruction Exception INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 PWC1 (MB90485 series only) PWC2 (MB90485 series only) PWC0 (MB90485 series only) PPG0/PPG1 counter borrow PPG2/PPG3 counter borrow PPG4/PPG5 counter borrow 8/16-bit up/down counter timer compare/underflow/overflow/ inversion (ch0, 1) Input capture (ch0) load Input capture (ch1) load Output compare (ch0) match Output compare (ch1) match Output compare (ch2) match Output compare (ch3) match Output compare (ch4) match Output compare (ch5) match UART sending completed 16-bit free run timer overflow, 16-bit reload timer underflow UART receiving compleated SIO1 SIO2 µDMA cnannel number 0 × × × × × × × × × 1 2 3 4 × 5 6 8 9 10 × × × 11 12 7 13 14 Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H ICR13 0000BDH ICR08 ICR09 ICR10 ICR11 0000B8H 0000B9H 0000BAH 0000BBH Interrupt control register Number ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 Address 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H
ICR07
0000B7H
ICR12
0000BCH
(Continued)
26
MB90480/485 Series
(Continued)
Interrupt source I2C interface (MB90485 series only) A/D conversion FLASH write/erase, timebase timer,watch timer * Delay interrupt generator module µDMA channel number × 15 × × Interrupt vector Number #39 #40 #41 #42 Address FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt control register Number ICR14 Address 0000BEH
ICR15
0000BFH
×: Interrupt request flag not cleared by the interrupt clear signal. If there are two interrupt sources for the same interrupt number, the resource will clear both interrupt request flags at the DMAC interrupt clear signal. Therefore if either of the two sources uses the DMAC function, the other interrupt function cannot be used. The interrupt request enable bit for the corresponding resource should be set to “0” and interrupt requests from that resource should be handled by software polling. * : Caution : The FLASH write/erase, timebase timer, and watch timer cannot be used at the same time.
27
MB90480/485 Series
s PERIPHERAL RESOURCES
1. I/O Ports
The I/O ports perform the functions of either sending data from the CPU to the I/O pins, or loading information from the I/O into the CPU, according to the setting of the corresponding port register (PDR) . The input/output direction of each I/O pin can be set in individual bit units by the port direction register (DDR) for each port. The MB90480/485 series has 84 input/output pins. The I/O ports are port 0 through port A. (1) Port Data Registers PDR0 Address : 000000H PDR1 Address : 000001H PDR2 Address : 000002H PDR3 Address : 000003H PDR4 Address : 000004H PDR5 Address : 000005H PDR6 Address : 000006H PDR7 Address : 000007H PDR8 Address : 000008H PDR9 Address : 000009H PDRA Address : 00000AH Initial value Undefined Access R/W*1
7 P07
6 P06
5 P05
4 P04
3 P03
2 P02
1 P01
0 P00
7 P17 7 P27 7 P37 7 P47 7 P57 7 P67 7 P77 7 P87 7 P97 7
6 P16 6 P26 6 P36 6 P46 6 P56 6 P66 6 P76 6 P86 6 P96 6
5 P15 5 P25 5 P35 5 P45 5 P55 5 P65 5 P75 5 P85 5 P95 5
4 P14 4 P24 4 P34 4 P44 4 P54 4 P64 4 P74 4 P84 4 P94 4
3 P13 3 P23 3 P33 3 P43 3 P53 3 P63 3 P73 3 P83 3 P93 3 PA3
2 P12 2 P22 2 P32 2 P42 2 P52 2 P62 2 P72 2 P82 2 P92 2 PA2
1 P11 1 P21 1 P31 1 P41 1 P51 1 P61 1 P71 1 P81 1 P91 1 PA1
0 P10 0 P20 0 P30 0 P40 0 P50 0 P60 0 P70 0 P80 0 P90 0 PA0
Undefined
R/W*1
Undefined
R/W*1
Undefined
R/W*1
Undefined
R/W*1
Undefined
R/W*1
Undefined
R/W*1
Undefined*2 R/W*1
Undefined
R/W*1
Undefined
R/W*1
Undefined
R/W*1
*1 : The R/W indication for I/O ports is somewhat different than R/W access to memory, and involves the following operations. • Input mode Read : Reads the corresponding siganl pin level. Write : Writes to the output latch. • Output mode Read : Reads the value from the data register latch. Write : Outputs the value to the corresponding signal pin. *2 : The initial value of this bit is “11XXXXXXB” on MB90485 series.
28
MB90480/485 Series
(2) Port Direction Registers DDR0 7 Address : 000010H DDR1 Address : 000011H DDR2 Address : 000012H DDR3 Address : 000013H DDR4 Address : 000014H DDR5 Address : 000015H DDR6 Address : 000016H DDR7 Address : 000017H DDR8 Address : 000018H DDR9 Address : 000019H DDRA Address : 00001AH
D07 7 D17 7 D27 7 D37 7 D47 7 D57 7 D67 7 D77*1 7 D87 7 D97 7
6 D06 6 D16 6 D26 6 D36 6 D46 6 D56 6 D66 6 D76* 6 D86 6 D96 6
1
5 D05 5 D15 5 D25 5 D35 5 D45 5 D55 5 D65 5 D75 5 D85 5 D95 5
4 D04 4 D14 4 D24 4 D34 4 D44 4 D54 4 D64 4 D74 4 D84 4 D94 4
3 D03 3 D13 3 D23 3 D33 3 D43 3 D53 3 D63 3 D73 3 D83 3 D93 3 DA3
2 D02 2 D12 2 D22 2 D32 2 D42 2 D52 2 D62 2 D72 2 D82 2 D92 2 DA2
1 D01 1 D11 1 D21 1 D31 1 D41 1 D51 1 D61 1 D71 1 D81 1 D91 1 DA1
0 D 00 0 D10 0 D20 0 D30 0 D40 0 D50 0 D60 0 D70 0 D80 0 D90 0 DA0
Initial value 00000000B
Access R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B*2
R/W
00000000B
R/W
00000000B
R/W
- - - - 0000B
R/W
*1 : The value is set to “” on MB90485 series only. *2 : The initial value of this bit is “XX000000B” on MB90485 series only. • When a set of pins is functioning as a port, the corresponding signal pins are controlled as follows. 0 : Input mode 1 : Output mode Reset to “0”. Notes : • When any of these register are accessed using a read-modify-write type instruction (such as a bit set instruction) , the bit specified in the instruction will be set to the indicated value. However, the contents of output registers corresponding to any other bits having input settings will be rewritten to the input values of those pins at that time. For this reason, when changing any pin that has been used for input to output, first write the desired value to the PDR register before setting the DDR register for output. • P76, P77 (MB90485 series only) This port has no DDR. To use P77, P76 and I2C pins, set the PDR value to “1” so that port data remains enabled (to use P77 adn P76 for general purposes, disable I2C) . The port is an open drain output (with no Pch) . To use it as an input port, therefore, set the PDR to “1” to turn off the output trangistor and add a pull-up resistor to the external output. 29
MB90480/485 Series
(3) Port Input Resistance Registers RDR0 7 6 Address : 00001CH RDR1 Address : 00001DH
RD07 7 RD17 RD06 6 RD16
5 RD05 5 RD15
4 RD04 4 RD14
3 RD03 3 RD13
2 RD02 2 RD12
1 RD01 1 RD11
0 RD00 0 RD10
Initial value Access 00000000B R/W
00000000B
R/W
These registers control the use of pull-up resistance in input mode. 0 : No pull-up resistance in input mode. 1 : With pull-up resistance in input mode. In output mode, these registers have no significance (no pull-up resistance) . Input/output mode settings are controlled by the port direction (DDR) registers. In case of a stop (SPL = 1) , no pull-up resistance is applied (high impedance) . This function is prohibited when an external bus is used. Do not write to these registers. (4) Port Output Pin Registers ODR7 7 6 Address : 00001EH OD77*1 OD76*1 ODR4 Address : 00001BH
7 OD47 6 OD46
5 OD75 5 OD45
4 OD74 4 OD44
3 OD73 3 OD43
2 OD72 2 OD42
1 OD71 1 OD41
0 OD70 0 OD40
Initial value 00000000 *
B2
Access R/W
00000000B
R/W
*1 : The value is set to “” on MB90485 series only. *2 : The initial value of this bit is “XX000000B” on MB90485 series only. These registers control open drain settings in output mode. 0 : Standard output port functions in output mode. 1 : Open drain output port in output mode. In input mode these registers have no significance (Hi-Z output) . Input/output mode settings are controlled by direction (DDR) registers. This function is prohibited when an exteral bus is used. Do not write to these registers. (5) Analog Input Enable Register ADER 7 6 Address : 00001FH
ADE7 ADE6
5 ADE5
4 ADE4
3 ADE3
2 ADE2
1 ADE1
0 ADE0
Initial value Access 11111111B R/W
This resister controls the port 6 pins as follows. 0 : Port input/output mode. 1 : Analog input mode. The default value at reset is all “1”. (6) Up-down Timer Input Enable Register UDER 7 6 5 Address : 00000BH
UDE5
4 UDE4
3 UDE3
2 UDE2
1 UDE1
0 UDE0
Initial value Access XX000000B R/W
This register controls the port 3 pins as follows. 0 : Port input mode. 1 : Up/down timer input mode.The default value at reset is “0”. The MB90480/485 series uses the following setting values : UDE0 : P30/AIN0, UDE1 : P31/BIN0/UDE2 : P32/ ZIN0, UDE3 : P33/AIN1, UDE4 : P34/BIN1, UDE5 : P35/ ZIN1
30
MB90480/485 Series
2. UART
The UART is a serial I/O port for asynchronous (start-stop synchronized) communication as well as CLK synchronized communication. • Full duplex double buffer • Transfer modes : asynchronous (start-stop synchronized) , or CLK synchronized (no start bit or stop bit) . • Multi-processor mode supported. • Embedded proprietary baud rate generator Asynchronous : 76923/38461/19230/9615/500 K/250 Kbps CLK synchronized : 16 M/8 M/4 M/2 M/1 M/500 Kbps • External clock setting available, allows use of any desired baud rate. • Can use internal clock feed from PPG1. • Data length : 7-bit (asynchronous normal mode only) or 8-bit. • Master/slave type communication functions (in multi-processor mode) . • Error detection functions (parity, framing, overrun) • Transmission signals are NRZ encorded. • DMAC supported (for receiving/sending)
31
MB90480/485 Series
(1) Register List
15 CDCR SCR SSR 8 bit 87 SMR SIDR (R)/SODR (W) 8 bit 0
Serial mode register (SMR)
7 6 MD0 R/W 0 5 CS2 R/W 0 4 CS1 R/W 0 3 CS0 R/W 0 2
Reserved
1 SCKE R/W 0
0 SOE R/W 0
000020H
MD1 R/W 0
R/W X
Initial value
Serial control register (SCR)
15 14 P R/W 0 13 SBL R/W 0 12 CL R/W 0 11 A/D R/W 0 10 REC W 1 9 RXE R/W 0 8 TXE R/W 0
000021H
PEN R/W 0
Initial value
Serial I/O register (SIDR/SODR)
7 6 D6 R/W X 5 D5 R/W X 4 D4 R/W X 3 D3 R/W X 2 D2 R/W X 1 D1 R/W X 0 D0 R/W X
000022H
D7 R/W X
Initial value
Serial data register (SSR)
15 14 ORE R 0 13 FRE R 0 12 RDRF R 0 11 TDRE R 1 10 BDS R/W 0 9 RIE R/W 0 8 TIE R/W 0
000023H
PE R 0
Initial value
Communication prescaler control register (CDCR)
15 14 SRST R/W 0 13 12 11 DIV3 R/W 0 10 DIV2 R/W 0 9 DIV1 R/W 0 8 DIV0 R/W 0
000025H
MD R/W 0
Initial value
32
MB90480/485 Series
(2) Block Diagram Control signal Receiving interrupt (to CPU) Proprietary baud rate generator PPG1 (internal connection) External clock Receiving control circuit Start bit detect circuit Receive bit counter Receiving parity counter Sending control circuit Send start circuit Send bit counter Send parity counter Clock select circuit Sending clock
Receiving control circuit
SCK0
Sending interrupt (to CPU)
SIN0
SOT0
Receiving status decision circuit
Receiving shifter
Receiving control circuit
Sending shifter Sending start
SODR
DMAC receiving error generation circuit (to CPU)
SIDR
F2MC-16LX BUS
SMR register
MD1 MD0 CS2 CS1 CS0 SCKE SOE
SCR register
PEN P SBL CL A/D REC REX TXE
SSR register
PE ORE FRE RDRF TDRE BDS RIE TIE
Control signal
33
MB90480/485 Series
3. Expanded I/O Serial Interface
The expanded I/O serial interface is an 8-bit × 1-channel serial I/O interface for clock synchronized data transmission. A selection of LSB-first or MSB-first data transmission is provided. There are two serial I/O operation modes. • Internal shift clock mode : Data transmission is synchronized with the internal clock siganl. • External shift clock mode : Data transmission is synchronized with a clock signal input from the external clock signal pin (SCK) . In this mode the general-purpose port that shares the external clock signal pin (SCK) can be used for transmission according to CPU instructions. (1) Register List Serial mode control status register (SMCS) 000027H Address : 00002BH
15 SMD2 R/W 7 14 SMD1 R/W 6 13 SMD0 R/W 5 12 SIE R/W 4 11 SIR R/W 3 MODE R/W 10 BUSY R/W 2 BDS R/W 9 STOP R/W 1 SOE R/W 8 STRT R/W 0 SCOE R/W
Initial value 00000010B
000026H Address : 00002AH Serial data register (SDR) Address : 000028H 00002CH
----0000B
7 D7 R/W
6 D6 R/W
5 D5 R/W
4 D4 R/W
3 D3 R/W
2 D2 R/W
1 D1 R/W
0 D0 R/W
XXXXXXXXB
Communication prescaler control register (SDCR0, SDCR1) 000029H Address : 00002DH
15 MD R/W 14 13 12 11 DIV3 R/W 10 DIV2 R/W 9 DIV1 R/W 8 DIV0 R/W
0---0000B
34
MB90480/485 Series
(2) Block Diagram
Internal data bus (MSB first) D0 to D7
SIN1, SIN2
D7 to D0 (LSB first) Transfer direction selection Read Write
Initial value
SDR (Serial Data Register)
SOT1, SOT2
SCK1, SCK2
Control circuit
Shift clock counter
Internal clock
2
1
0 SIE SIR BUSY STOP STRT MODE BDS SOE SCOE
SMD2 SMD1 SMD0
Interrupt request Internal data bus
35
MB90480/485 Series
4. 8/10-bit A/D Converter
The A/D converter converts analog input voltage input voltages to digital values, and provides the following features. • Conversion time : minimum 3.68 µs per channel (92 machine cycles at 25 MHz machine clock, including sampling time) • Sampling time : minimum 1.92 µs per channel (48 machine cycles at 25 MHz machine clock) • RC sequential comparison conversion method, with sample & hold circuit. • 8-bit or 10-bit resolution • Analog input selection of 8 channels Single conversion mode : Conversion from one selected channel. Scan conversion mode : Conversion from multiple consecutive channels, programmable selection of up to 8 channels. Continuous conversion mode : Repeated conversion of specified channels. Stop conversion mode : Conversion from one channel followed by a pause until the next activation. • At the end of A/D conversion, an A/D conversion completed interrupt request can be generated. The interrupt can be used activate the µDMA in order to transfer the results of A/D conversion to memory for efficient continuous processing. • The starting factor conversion may be selected from software, external trigger (falling edge) , or timer (rising edge) . (1) Register List ADCS2, ADCS1 (Control status register) ADCS1 bit 7 6 5 Address : 000046H MD1 MD0 ANS2
0 R/W 0 R/W 14 INT 0 R/W 0 R/W 13 INTE 0 R/W
4 ANS1 0 R/W 12 PAUS 0 R/W
3 ANS0 0 R/W 11 STS1 0 R/W
2 ANE2 0 R/W 10 STS0 0 R/W
1 ANE1 0 R/W 9 STRT 0 W
0 ANE0 0 R/W 8
Reserved
←Initial value ←Bit attributes
ADCS2 bit Address : 000047H
15 BUSY 0 R/W
0 R/W
←Initial value ←Bit attributes
ADCR2, ADCR1 (Data register) ADCR1 bit 7 Address : 000048H D7
X R
6 D6 X R 14 ST1 0 W
5 D5 X R 13 ST0 0 W
4 D4 X R 12 CT1 0 W
3 D3 X R 11 CT0 0 W
2 D2 X R 10 X R
1 D1 X R 9 D9 X R
0 D0 X R 8 D8 X R
←Initial value ←Bit attributes
ADCR2 bit Address : 000049H
15 S10 0 R/W
←Initial value ←Bit attributes
36
MB90480/485 Series
(2) Block Diagram
AVCC AVRH AVSS
D/A converter
MP AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Input circuit Comparator
Sequential comparison register
Data bus
Sample & hold circuit
decoder
Data registers
ADCR1, ADCR2
A/D control register 1
ADTG
Trigger activation Timer activation
φ
A/D control register 2
ADCS1, ADCS2
Timer (PPG1 output)
Operation clock Prescaler
37
MB90480/485 Series
5. 8/16-bit PPG
The 8/16-bit PPG is an 8-bit reload timer module that produces a PPG output using a pulse from the timer operation. Hardware resources include 6 × 8-bit down counters, 12 × 8-bit reload timers, 3 × 16-bit control registers, 6 external bus output pins, and 6 interrupt outputs. Note that MB90480/485 series has six channels for 8-bit PPG use, which can also be combined as PPG0 + PPG1, PPG2 + PPG3, and PPG4 + PPG5 to operate as a three-channel 16-bit PPG. The following is a summary of functions. • 8-bit PPG output 6-channel independent mode : Provides PPG output operation on six independent channels. • 16-bit PPG output operation mode : Provides 16-bit PPG output on three channels. The six original channels are used in combination as PPG0 + PPG1, PPG2 + PPG3, and PPG4 + PPG5. • 8 + 8-bit PPG operation mode : Output from PPG0 (PPG2/PPG4) is used as clock input to PPG1 (PPG3/ PPG5) to provide to 8-bit PPG output at any desired period length. • PPG output operation : Produces pulse waves at any desired period and duty ratio. The PPG module can also be used with external cirsuits as a D/A converter. (1) Register List PPGC0/PPGC2/PPGC4 (PPG0/PPG2/PPG4 operation mode control register) 00003AH 00003CH 00003EH
7 PEN0 R/W 0 6 X 5 PE00 R/W 0 4 PIE0 R/W 0 3 PUF0 R/W 0 2 X 1 X 0
Reserved
1
Read/write Initial value
PPGC1/PPGC3/PPGC5 (PPG1/PPG3/PPG5 operation mode control register) 00003BH 00003DH 00003FH
15 PEN1 R/W 0 14 X 13 PE10 R/W 0 12 PIE1 R/W 0 11 PUF1 R/W 0 10 MD1 R/W 0 9 MD0 R/W 0 8
Reserved
1
Read/write Initial value
PPG01/PPG23/PPG45 (PPG0 to PPG5 output control register) 000040H 000042H 000044H
7 PCS2 R/W 0 6 PCS1 R/W 0 5 PCS0 R/W 0 4 PCM2 R/W 0 3 PCM1 R/W 0 2 1 0 PCM0 Reserved Reserved R/W 0 R/W 0 R/W 0
Read/write Initial value
PPLL0 to PPLL5 (Reload register L) 00002EH 7 6 5 000030H D07 D06 D05 000032H R/W R/W R/W 000034H X X X 000036H 000038H PPLH0 to PPLH5 (Reload register H) 00002FH 15 14 13 000031H D15 D14 D13 000033H R/W R/W R/W 000035H X X X 000037H 000039H
4 D04 R/W X
3 D03 R/W X
2 D02 R/W X
1 D01 R/W X
0 D00 R/W X
Read/write Initial value
12 D12 R/W X
11 D11 R/W X
10 D10 R/W X
9 D09 R/W X
8 D08 R/W X
Read/write Initial value
38
MB90480/485 Series
(2) Block Diagram • 8-bit PPG channel 0/2/4 block Diagram
Peripheral clock × 16 Peripheral clock × 8 Peripheral clock × 4 Peripheral clock × 2 Peripheral clock
PPG0/2/4 output enable
PPG0/2/4
A/D converter
PPG0/2/4 output latch
PEN0
PCNT (down counter) Count clock select L/H selector Timebase counter output main clock × 512 L/H select
PRLL PRLBH PUF0
S RQ
IRQ
ch1/3/5 borrow
PIE0
PPGC0 (operation mode control)
PRLL
L data bus H data bus
39
MB90480/485 Series
• 8-bit PPG ch1/3/5 Block Diagram
Peripheral clock × 16 Peripheral clock × 8 Peripheral clock × 4 Peripheral clock × 2 Peripheral clock
PPG1/3/5 output enable
PPG1/3/5 UART0
PPG1/3/5 output latch
PEN1
PCNT (down counter) Count clock select L/H selector Timebase counter output main clock × 512 L/H select
PRLL PRLBH PUF1
S RQ
IRQ
PIE1
PPGC1 (operation mode control)
PRLL
L data bus H data bus
40
MB90480/485 Series
6. 8/16-bit up/down Counter/Timer
8/16-bit up/down counter/timer consists of up/down counter/timer circuits including six event input pins, two 8bit up/down counters, two 8-bit reload/compare registers, as well as the related control circuits. (1) Principal Functions • 8-bit count register enables counting in the range 0 to 256. (In 16-bit × 1 mode, counting is enabled in the range 0 to 65535) • Count clock selection provides four count modes. Count modes Timer mode Up down count mode Phase differential count mode ( × 2) Phase differential count mode ( × 8) • In timer mode, there is a choice of two internal count clock signals. Count clock (at 16 MHz operation) Edge detection 125 ns (8 MHz : × 2) 0.5 µs (2 MHz : × 8) Falling edge detection Rising edge detection Both rising/falling edge detection Edge detection disabled • In phase differential count mode, to handle encoder counting for mortors, the encode A-phase, B-phase, and Z-phase are each input, enabling easy and highly accurate counting of angle of rotation, speed of rotation, etc. • The ZIN pin provides a selection of two functions ZIN pin Counter clear function Gate functions • A compare function and reload function are provided, each for use separately or in combination. Both functions can be activated together for up/down counting in any desired bandwidth. Compare/reload function Compare function (output interrupt at compare events) Compare function (output interrupt and clear counter at compare events) Reload function (output interrupt and reload at underflow events) Compare/reload function (output interrupt and clear counter at compare events, output interrupt and reload at underflow events) Compare/reload disabled • Individual control over interrupts at compare, reload (underflow) and overflow events. • Count direction flag enables identification of the last previous count direction. • Interrupt generated when count direction changes.
• In up/down count mode there is a choice of trigger edge detection for the input signal from external pins.
41
MB90480/485 Series
(2) Register List
15 UDCR1 RCR1 87 UDCR0 RCR0 CSR0 CCRL0 CSR1 CCRL1 8 bit 0
Reserved area
CCRH0
Reserved area
CCRH1 8 bit
CCRH0 (Counter Control Register High ch0)
15 14 CDCF R/W 13 CFIE R/W 12 CLKS R/W 11 CMS1 R/W 10 CMS0 R/W 9 CES1 R/W 8 CES0 R/W
Address : 00006DH
M16E R/W
Initial value 00000000B
CCRH1 (Counter Control Register High ch1)
15 14 CDCF R/W 13 CFIE R/W 12 CLKS R/W 11 CMS1 R/W 10 CMS0 R/W 9 CES1 R/W 8 CES0 R/W
Address : 000071H
Initial value -0000000B
CCRL0/1 (Counter Control Register Low ch0/ch1) Address : 00006CH Address : 000070H
7 UDMS R/W 6 CTUT W 5 UCRE R/W 4 RLDE R/W 3 UDCC W 2 CGSC R/W 1 CGE1 R/W 0 CGE0 R/W
Initial value 0X00X000B
CSR0/1 (Counter Status Register ch0/ch1) Address : 000072H Address : 000074H
7 CSTR R/W 6 CITE R/W 5 UDIE R/W 4 CMPF R/W 3 OVFF R/W 2 UDFF R/W 1 UDF1 R 0 UDF0 R
Initial value 00000000B
UDCR0/1 (Up Down Count Register ch0/ch1)
15 14 D16 R 6 D06 R 13 D15 R 5 D05 R 12 D14 R 4 D04 R 11 D13 R 3 D03 R 10 D12 R 2 D02 R 9 D11 R 1 D01 R 8 D10 R 0 D00 R
Address : 000069H
D17 R 7
Initial value 00000000B
Address : 000068H
D07 R
Initial value 00000000B
RCR0/1 (Reload/Compare Register ch0/ch1)
15 14 D16 W 6 D06 W 13 D15 W 5 D05 W 12 D14 W 4 D04 W 11 D13 W 3 D03 W 10 D12 W 2 D02 W 9 D11 W 1 D01 W 8 D10 W 0 D00 W
Address : 00006BH
D17 W 7
Initial value 00000000B
Address : 00006AH
D07 W
Initial value 00000000B
42
MB90480/485 Series
(3) Block Diagram
Data bus
8 bit CGE1 CGE0 CGSC ZIN0
Edge/level detection
RCR0 (Reload/ compare register 0)
CTUT
Reload control
UCRE
RLDE
UDCC
Counter clear
8 bit
UDCR0 (Up/down count register 0)
CES1 CES0 CMS1 CMS0 UDMS AIN0 BIN0 Carry UDFF OVFF CMPF
Up/down count clock selection Prescaler
CLKS
Count clock
UDF1 UDF0 CDCF CFIE
CITE
UDIE
CSTR
Interrupt output
43
MB90480/485 Series
7. DTP/External Interrupt
The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC16LX CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the requests to the F2MC-16LX CPU to activate the extended intelligent µDMA or interrupt processing. (1) Detailed Register Descriptions Interrupt/DTP Enable Register (ENIR : Enable Interrupt Request Register) ENIR 7 6 5 4 3 2 1 Address : 00000CH EN7 EN6 EN5 EN4 EN3 EN2 EN1
R/W R/W R/W R/W R/W R/W R/W
0 EN0 R/W
Initial value 00000000B
Interrupt/DTP Source Register (EIRR : External Interrupt Request Register) EIRR 15 14 13 12 11 10 9 Address : 00000DH ER7 ER6 ER5 ER4 ER3 ER2 ER1
R/W R/W R/W R/W R/W R/W R/W
8 ER0 R/W
Initial value XXXXXXXXB
Interrupt Level Setting Register (ELVR : External Level Register)
7 6 LA3 R/W 14 LA7 R/W 5 LB2 R/W 13 LB6 R/W 4 LA2 R/W 12 LA6 R/W 3 LB1 R/W 11 LB5 R/W 2 LA1 R/W 10 LA5 R/W 1 LB0 R/W 9 LB4 R/W 0 LA0 R/W 8 LA4 R/W
Address : 00000EH
LB3 R/W 15
Initial value 00000000B
Address : 00000FH
LB7 R/W
Initial value 00000000B
(2) Block Diagram F2MC-16 bus
4
Interrupt/DTP enable register Gate
Source F/F
Edge detection circuit
4
4
Request input
4
Interrupt/DTP source register Interrupt level setting register
8
44
MB90480/485 Series
8. 16-bit Input/Output Timer
The 16-bit input/output timer module is composed of one 16-bit free run timer, six output compare and two input capture modules. These functions can be used to output six independent waveforms based on the 16-bit free run timer, enabling input pilse width measurement and external clock frequency measurement. • Register List • 16-bit free run timer
15 0 CPCLR
000066/67H
Compare-clear register
000062/63H
TCDT
Timer counter data register Control status register
000064/65H
TCCS
• 16-bit output compare
15 0 OCCP0 to OCCP5
00004A, 4C, 4E, 50, 52, 54H 00004B, 4D, 4F, 51, 53, 55H 000056, 58, 5AH 000057, 59, 5BH
OCS1/3/5
Output compare register Output compare control registers
OCS0/2/4
• 16-bit input capture
15 0 IPCP0, IPCP1
00005C, 5EH 00005D, 5FH 000060H
Input capture data register
ICS
Input capture control register
45
MB90480/485 Series
• Block Diagram
Control logic Interrupt 16-bit free run timer 16-bit timer Clear Output compare 0 Bus Output compare 1 Output compare 2 Output compare 3 Output compare 4 Output compare 5 To each block
Compare register 0 Compare register 1
TQ
OUT0
TQ
OUT1
Compare register 2
TQ
OUT2
Compare register 3 Compare register 4
TQ
OUT3
TQ
OUT4
Compare register 5
TQ
OUT5
Input capture 0 Input Capture 1
Capture register 0
Edge selection
IN0
Capture register 1
Edge selection
IN1
46
MB90480/485 Series
(1) 16-bit Free Run Timer The 16-bit free run timer is composed of a 16-bit up-down counter and control status register. The counter value of this timer is used as the base timer for the input capture and output compare. • The counter operation provides a choice of eight clock types. • A counter overflow interrupt can be produced. • A mode setting is available to initialize the counter value whenever the output compare value matches the value in the compare clear register. • Register List Compare clear register (CPCLR)
15 14 CL14 R/W 13 CL13 R/W 12 CL12 R/W 11 CL11 R/W 10 CL10 R/W 9 CL09 R/W 8 CL08 R/W
000067H
CL15 R/W
Initial value XXXXXXXXB
7
6 CL06 R/W
5 CL05 R/W
4 CL04 R/W
3 CL03 R/W
2 CL02 R/W
1 CL01 R/W
0 CL00 R/W
000066H
CL07 R/W
Initial value XXXXXXXXB
Timer counter data register (TCDT)
15 14 T14 R/W 13 T13 R/W 12 T12 R/W 11 T11 R/W 10 T10 R/W 9 T09 R/W 8 T08 R/W
000063H
T15 R/W
Initial value 00000000B
7
6 T06 R/W
5 T05 R/W
4 T04 R/W
3 T03 R/W
2 T02 R/W
1 T01 R/W
0 T00 R/W
000062H
T07 R/W
Initial value 00000000B
Timer control status register (TCCS)
15 14 R/W 13 R/W 12 MSI2 R/W 11 MSI1 R/W 10 MSI0 R/W 9 ICLR R/W 8 ICRE R/W
000065H
ECKE R/W
Initial value 0--00000B
7
6 IVFE R/W
5 STOP R/W
4 MODE R/W
3 SCLR R/W
2 CLK2 R/W
1 CLK1 R/W
0 CLK0 R/W
000064H
IVF R/W
Initial value 00000000B
47
MB90480/485 Series
• Block Diagram
φ
Interrupt request
IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0
Multiplier
Clock Bus 16-bit free run timer 16-bit compare clear register
Compare circuit
MSI3 to MSI0
Count value output T15 to T00
ICLR
ICRE
Interrupt request A/D activation
48
MB90480/485 Series
(2) Output Compare The output compare module is composed of a 16-bit compare register, compare output pin group, and control register. When the value in the compare register in this module matches the 16-bit free run timer, the pin output levels can be inverted and an interrupt generated. • There are six compare registers in all, each operating independently. A setting is available to allow two compare registers to be used to control output. • Interrupts can be set in terms of compare match events. • Register List Output compare registers (OCCP0 to OCCP5)
15 14 C14 R/W 13 C13 R/W 12 C12 R/W 11 C11 R/W 10 C10 R/W 9 C09 R/W 8 C08 R/W
00004BH 00004DH 00004FH 000051H 000053H 000055H
C15 R/W
Initial value 00000000B
7
6 C06 R/W
5 C05 R/W
4 C04 R/W
3 C03 R/W
2 C02 R/W
1 C01 R/W
0 C00 R/W
00004AH 00004CH 00004EH 000050H 000052H 000054H
C07 R/W
Initial value 00000000B
Output control registers (OCS1/OCS3/OCS5)
15 14 13 12 CMOD R/W 11 OTE1 R/W 10 OTE0 R/W 9 OTD1 R/W 8 OTD0 R/W
000057H 000059H 00005BH
Initial value ---00000B
Output control registers (OCS0/OCS2/OCS4)
7 6 ICP0 R/W 5 ICE1 R/W 4 ICE0 R/W 3 2 1 CST1 R/W 0 CST0 R/W
000056H 000058H 00005AH
ICPIC R/W
Initial values 0000--00B
49
MB90480/485 Series
• Block Diagram
16-bit timer counter value (T15 to T00)
Compare control
Compare register 0 (2, 4)
TQ
OTE0
OUT0 (2) (4)
16-bit timer counter value (T15 to T00) Bus Compare control
Compare register 1 (3, 5)
ICP1 ICP0 ICE0 ICE0
CMOD
TQ
OTE1
OUT1 (3) (5)
Control unit
Individual control blocks
Compare 1 (3) (5) interrupt Compare 0 (2) (4) interrupt
50
MB90480/485 Series
(3) Input Capture The input capture module performs the functions of detecting the rising edge, falling edge, or both edges of signal input from external circuits, and saving the 16-bit free run timer value at that moment to a register. An interrupt can also be generated at the instant of edge detection. The input capture module consists of input capture registers and a control register. Each input capture module has its own external input pin. • Section of three types of valid edge for external input signals. Rising edge, falling edge, both edges. • An interrupt can be generated when a valid edge is detected in the external input signal. • Register List Input capture data register (IPCP0, IPCP1)
15 14 CP14 R 13 CP13 R 12 CP12 R 11 CP11 R 10 CP10 R 9 CP09 R 8 CP08 R
00005DH 00005FH
CP15 R
Initial value XXXXXXXXB
7
6 CP06 R
5 CP05 R
4 CP04 R
3 CP03 R
2 CP02 R
1 CP01 R
0 CP00 R
00005CH 00005EH
CP07 R
Initial value XXXXXXXXB
Input capture control register (ICS0, ICS1)
7 6 ICP0 R/W 5 ICE1 R/W 4 ICE0 R/W 3 EG11 R/W 2 EG10 R/W 1 EG01 R/W 0 EG00 R/W
000060H
ICP1 R/W
Initial value 00000000B
• Block Diagram Capture data register 0
Edge detection
IN0
Bus
16-bit timer counter value (T15 to T00)
EG11 EG10 EG01 EG00
Capture data register 1
Edge detection
IN1
ICP1
ICP0
ICE1
ICE0
Interrupt Interrupt
51
MB90480/485 Series
9. I2C Interface (MB90485 series only)
The I2C interface is a serial I/O port supporting the Inter IC BUS. Serves as a master/slave device on the I2C bus. The I2C interface has the following functions. • Master/slave transmit/receive • Arbitration function • Clock synchronization • Slave address/general call address detection function • Forwarding direction ditection function • Start condition repeated generation and detection • Bus error detection function (1) Register List Bus Status Register (IBSR) 000088H
7 BB R 6 RSC R 5 AL R 4 3 2 1 0
Initial value 0 0 0 0 0 0 0 0B
LRB TRX AAS GCA FBT R R R R R
Bus control register (IBCR) 000089H
15 14 13 12 11 10 9 8 INT R/W
Initial value 0 0 0 0 0 0 0 0B
BER BEIE SCC R/W R/W R/W
MSS ACK GCAA INTE R/W R/W R/W R/W
Clock control register (ICCR) 00008AH
7 6 5 EN R/W 4 3 2 CS2 R/W 1 CS1 R/W 0 CS0 R/W
Initial value - - 0 XXXXXB
CS4 CS3 R/W R/W
Address register (IADR) 00008BH
15 14 A6 R/W 13 A5 R/W 12 A4 R/W 11 A3 R/W 10 A2 R/W 9 A1 R/W 8 A0 R/W
Initial value - XXXXXXXB
Data register (IDAR) 00008CH
7 D7 R/W 6 D6 R/W 5 D5 R/W 4 D4 R/W 3 D3 R/W 2 D2 R/W 1 D1 R/W 0 D0 R/W
Initial value XXXXXXXXB
52
MB90480/485 Series
(2) Block Diagram
ICCR EN I2C enable Clock dividing 1 ICCR F2MC-16LX Bus CS4 CS3 CS2 CS1 CS0 Clock selection 2 Change timing of shift clock edge IBSR BB RSC LRB TRX FBT AL IBCR BER BEIE Interrupt request INTE INT IBCR SCC MSS ACK GCAA Start Master ACK enable
GC-ACK enable
Peripheral clock 8
5
6
7
Clock selection 1
Clock dividing 2 2 4 8 16 32 64 128 256 Sync Shift clock generation
Bus busy Repeat start Last Bit
Transmission/ Reception
Start/stop condition detection Error First Byte Arbitration lost detection
SCL
IRQ
SDA
End
Start/stop condition generatiion
IDAR IBCR AAS GCA Slave Global call Slave address comparison
IADR
53
MB90480/485 Series
10. 16-bit Reload Timer
The 16-bit reload timer provides a choice of functions, including internal clock signals that count down in synchronization with three types of internal clock, as well as an event count mode that counts down at specified edge detection events in pulse signals input from external pins. This timer defines an underflow as a change in count value from 0000H to FFFFH.Thus an underflow will occur when counting from the value “reload register setting value + 1”. The choice of counting operations includes reload mode, in which the count setting values is reload and counting continues following an underflow event, and one-shot mode, in which an underflow event causes counting to stop. An interrupt can be generated at counter underflow, and the timer is DTC compatible. (1) Register List • TMCSR (Timer control status register) Timer control status register (high) (TMCSR)
15 14 13 12 11 CSL1 R/W 0 10 CSL0 R/W 0 9 MOD2 R/W 0 8 MOD1 R/W 0
0000CBH
Read/Write Initial value
Timer control status register (low) (TMCSR)
7 6 OUTE R/W 0 5 OUTL R/W 0 4 RELD R/W 0 3 INTE R/W 0 2 UF R/W 0 1 CNTE R/W 0 0 TRG R/W 0
0000CAH
MOD0 R/W 0
Read/Write Initial value
• 16-bit timer register/16-bit reload register TMR/TMRLR (high)
15 14 D14 R/W X 13 D13 R/W X 12 D12 R/W X 11 D11 R/W X 10 D10 R/W X 9 D09 R/W X 8 D08 R/W X
0000CDH
D15 R/W X
Read/Write Initial value
TMR/TMRLR (low)
7 6 D06 R/W X 5 D05 R/W X 4 D04 R/W X 3 D03 R/W X 2 D02 R/W X 1 D01 R/W X 0 D00 R/W X
0000CCH
D07 R/W X
Read/Write Initial value
54
MB90480/485 Series
(2) Block Diagram
Internal data bus
TMRLR
16-bit reload register Reload signal
TMR
16-bit timer register (down counter)
CLK
UF
Reload control circuit
Count clock generator circuit machine clock φ Prescaler Clear
3
Gate input
Valid clock detection circuit
CLK
Wait signal
Output signal generation circuit
to A/D converter Pin (TOT0)
EN
Inverted Pin (TIN0)
Input control circuit
Clock selector External clock Select signal
2
Output signal generation circuit
OUTL
RELD
Function selection
3
Operation control circuit
OUTE
Timer control status register (TMCSR)
55
MB90480/485 Series
11. µPG Timer (MB90485 only)
The µPG timer performs pulse output in response to the external input. (1) Register List µPG control status register (PGCSR) Initial value 00008EH
7 PEN0 R/W 6 PE1 R/W 5 PE0 R/W 4 PMT1 R/W 3 PMT0 R/W 2 1 0
00000---B
(2) Block Diagram
MT00
MT01
MT00 Output latch
MT00 Output latch
Output enable
Control circuit
EXTC
56
MB90480/485 Series
12. PWC Timer (MB90485 only)
The PWC timer is a 16-bit multifunction up-count timer capable of measuring the pulse width of the input signal. A total of three channels are provided, each consisting of a 16-bit up-count timer, an input pulse divider & divide ratio control register, a measurement input pin, and a 16-bit control register. These components provide the following functions. Timer function : • Capable of generating an interrupt request at fixed intervals specified. • The internal clock used as the reference clock can be selected from among three types. Pulse width measurement function : • Measures the time between arbitrary events based on external pulse inputs. • The internal clock used as the reference clock can be selected from among three types. • Measurement modes - H pulse width (↑ to ↓) /L pulse width (↑ to ↓) - Rising cycle (↑ to ↑) /Falling cycle (↓ to ↓) - Measurement between edges (↑ or ↓ to ↓ or ↑) • The 8-bit input divider can be used for division measurement by dividing the input pulse by 22 ns (n = 1, 2, 3, 4) . • An interrupt can be generated upon completion of measurement. • One-time measurement or fast measurement can be selected.
57
MB90480/485 Series
(1) Register list PWC control status register (PWCSR0 to PWCSR2) 000077H 00007BH 00007FH
15 STRT R/W 14 STOP R/W 13 EDIR R 12 EDIE R/W 11 OVIR R/W 10 OVIE R/W 9 R 8
Initial value 0000000XB
ERR Reserved
PWC control status register (PWCSR0 to PWCSR2) 000076H 00007AH 00007EH
7 CKS1 R/W 6 CKS0 R/W 5 PIS1 R/W 4 PIS0 R/W 3 S/C R/W 2 R/W 1 R/W 0 R/W
Initial value 00000000B
MOD2 MOD1 MOD0
PWC data buffer register (PWCR0 to PWCR2) 000079H 00007DH 000081H
15 D15 R/W 14 D14 R/W 13 D13 R/W 12 D12 R/W 11 D11 R/W 10 D10 R/W 9 D9 R/W 8 D8 R/W
Initial value 00000000B
PWC data buffer register (PWCR0 to PWCR2) 000078H 00007CH 000080H
7 D7 R/W 6 D6 R/W 5 D5 R/W 4 D4 R/W 3 D3 R/W 2 D2 R/W 1 D1 R/W 0 D0 R/W
Initial value 00000000B
Dividing ratio control register (DIVR0 to DIVR2) 000082H 000084H 000086H
7 6 5 4 3 2 1 DIV1 R/W 0 DIV0 R/W
Initial value ------00B
58
MB90480/485 Series
(2) Block Diagram
PWCR read Error detection ERR Internal clock (machine clock/4)
PWCR
16 Reload Data transfer 16 Overflow Clock 16-bit up count timer 22 Clock divider 23 Timer clear F2MC-16 Bus CKS1/CKS0
Control circuit
Count enable
Control bit output
Flagset etc.
Start of measurement edge
Start edge selection Completion edge selection
Dividing ON/OFF Input waveform comparator PWC0 PWC1
Edge detection
Completion of measurement edge
Completion of measurement interrupt request Overflow interrupt request
PIS0/PIS1 CKS0/ CKS1 8-bit divider
ERR
PWCSR 15 2
Dividing ratio selection
DIVR
59
MB90480/485 Series
13. Watch Timer
The watch timer is a 15-bit timer using the sub clock. This circuit can generate interrupts at predetermined intervals. Also a setting is available to enable it to be used as the clock source for the watchdog timer. (1) Register List Watch timer control register (WTC)
7 6 SCE R 0 5 WTIE R/W 0 4 WTOF R/W 0 3 WTR R/W 1 2 WTC2 R/W 0 1 WTC1 R/W 0 0 WTC0 R/W 0
0000AAH
WDCS R/W 1
Read/write Initial value
(2) Block Diagram Watch timer control register (WTC)
WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0
Clear
28
Sub clock Watch counter
29 210 211 212 213 210 213 214 215 214
Interval sector
Interrupt generator circuit
Watch timer interrupt
To watchdog timer
60
MB90480/485 Series
14. Watchdog timer
The watchdog timer is a 2-bit counter that uses the output from the timebase timer or watch timer as acount clock signal, and will reset the CPU if not cleared within a predetermined time interval after it is activated. (1) Register List Watchdog timer control register (WDTC)
7 6
Reserved
5 WRST R X
4 ERST R X
3 SRST R X
2 WTE W 1
1 WT1 W 1
0 WT0 W 1
0000A8H
PONR R X
X
Read/write Initial value
(2) Block Diagram Watchdog timer control register (WDTC)
PONR served WRST ERST SRST WTE
Re-
WT1
WT0
Watch mode start Timebase timer mode start Sleep mode start Watchdog timer Hold status start Counter clear circuit Stop mode start
2
Watch timer control register (WTO) WDCS bit Clock select register (CKSCR) SCM bit
CLR
CLR and start Count clock selector
CLR
2-bit counter
Watchdog reset generator circuit
4
Internal reset generator circuit
Clear Time-base counter HCLK × 2
× 21 × 22
4
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
SCLK
× 21 × 2 2
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
HCLK : Oscillator clock SCLK : Sub clock
61
MB90480/485 Series
15. Timebase Timer
The timebase timer is an 18-bit free run counter (timebase counter) that counts up in synchronization with the internal count clock signal (base oscillator × 2) , and functions as an interval timer with a choice of four types of time intervals. Other functions provided by this module include timer output for the oscillator stabilization wait period, and operating clock signal feed for other timer circuits such as the watchdog timer. (1) Register List Timebase timer control register (TBTC) 0000A9H
15 RESV R/W 1 14 X 13 X 12 TBIE R/W 0 11 TBOF R/W 0 10 TBR W 1 9 TBC1 R/W 0 8 TBC0 R/W 0
Read/write Initial value
(2) Block Diagram
to PPG timer Timebase timer counter HCLK × 2
× 21 × 22
To watchdog timer
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 OF OF OF OF
Power-on reset Stop mode start
Hold status start CKSCR : MCS = 1→0*1 CKSCR : SCS = 0→1*2
Counter clear control circuit
Clock control module Oscillator stabilization wait To time selector
Interval timer selector TBOF clear
TBOF set
Timebase timer control register (TBTC) RESV Timebase timer interrupt signal OF HCLK *1 *2
TBIE TBOF TBR TBC1 TBC0
: Not used : Overflow : Oscillator clock : Switch machine clock from main clock or sub clock to PLL clock. : Switch machine clock from sub clock to main clock.
62
MB90480/485 Series
16. Clock
The clock generator module controls the operation of the internal clock circuits that serve as the operating clock for the CPU and peripheral devices. This internal clock is referred to as the machine clock, and one cycle os refferd to as a machine cycle. Also, the clock signals from the base oscillator are called the oscillator clock, and those from the PLL oscillator are called the PLL clock. (1) Register List Clock select register (CKSCR)
15 14 MCM R 1 13 WS1 R/W 1 12 WS0 R/W 1 11 SCS R/W 1 10 MCS R/W 1 9 CS1 R/W 0 8 CS0 R/W 0
0000A1H
SCM R 1
Read/write Initial value
PLL output select register (PLLOS)
15 14 13 12 11 10 9 W X 8 PLL2 W 0
0000CFH
Read/write Initial value
63
MB90480/485 Series
(2) Block Diagram Standby control circuit Low-power mode control register (LPMCR)
STP SLP SPL RST TMD CG1 CG0
Reserved
Pin high-impedance control circuit
Pin high-impedance control
RST
pin
CPU internal operation selector
Internal reset generator circuit
Internal reset
Intermittent cycle selection
CPU clock control circuit
CPU clock
Interrupt release
Standby control circuit
Stop, sleep signals Stop signal
Peripheral clock control circuit
Machine clock Clock generator module Clock selector × 4 SCLK
2
Peripheral clock
Oscillator stabilization wait release PLL output select register (PLLOS)
2 PLL2
Oscillator stabilization wait period selector
PLL multiplier circuit
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Sub clock generator circuit
X0A X1A
Clock select register (CKSCR)
System clock generator circuit
pin pin
×2
× 1024 Timebase timer
×2
×4
×4
×4
×2
HCLK X0
MCLK
pin
X1 pin
HCLK : Oscillator clock MCLK : Main clock SCLK : Sub clock
To watchdog timer
64
MB90480/485 Series
(3) Clock Feed Map
4
Peripheral functions Watchdog timer
4
Clock generator module Watch timer
X0A
8/16-bit PPG timer 0 8/16-bit PPG timer 1 8/16-bit PPG timer 2 16-bit reload timer 0
PPG0, PPG1
pins
PPG2, PPG3
pin
X1A
pin
Sub clock generator circuit
Timebase timer
1 2 3 4
pins
PPG4, PPG5
PLL multiplier circuit ×4
SCLK PCLK φ
pins
TIN0
pin
TOT0
X0
pin
X1
pin
System clock ×2 generator HCLK circuit MCLK
Clock selector
pin
SCK0, SIN0
pins
UART0 CPU, µDMAC SOT0
pin
SCK1, SCK2 SIN1, SIN2
I/O expanded serial interface, 2ch
pins
SOT1, SOT2
pins
AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1
8/16-bit U/D counter
pins
CS0, CS1, CS2, CS3
Chip select 16-bit output compare 16-bit free run timer 16-bit input capture 10-bit A/D converter HCLK MCLK SCLK PCLK φ : Oscillator clock : Main clock : Sub clock : PLL clock : Machine clock External interrupt Oscillator stabilization wait control
pins
OUT0, OUT1, OUT2, OUT3, OUT4, OUT5
pins
FRCK
pin
IN0, IN1
pins
AN0 to AN7, ADTG
pins
IRQ0 to IRQ7
pin
3
65
MB90480/485 Series
17. Low-power Consumption Mode
The MB90480/485 series uses operating clock selection and clock operation controls to provide the following CPU operating modes : • Clock modes (PLL clock mode, main clock mode, sub clock mode) • CPU intermittent operating modes (PLL clock intermittent mode, main clock intermittent mode, sub clock intermittent mode) • Standby modes (Sleep mode, timebase timer mode, stop mode, watch mode) (1) Register List Low-power mode control register (LPMCR)
7 6 SLP W 0 5 SPL R/W 0 4 RST W 1 3 TMD R/W 1 2 CG1 R/W 0 1 CG0 R/W 0 0
Reserved
0000A0H
STP W 0
R/W 0
Read/write Initial value
66
MB90480/485 Series
(2) Block Diagram Standby control circuit Low-power mode control register (LPMCR)
STP SLP SPL RST TMD CG1 CG0 served
Re-
Pin high-impedance control circuit
Internal reset generator circuit
Pin high-impedance control Internal reset
RST
pin
CPU intermittent operating selector
Intermittent cycle selection
CPU clock control circuit
CPU clock
Interrupt release
Standby control circuit
Stop, sleep signals Stop signal
Peripheral clock control circuit
Machine clock Clock generator Clock selector × 4 SCLK
2
Peripheral clock
Oscillator stabilization wait release PLL output select register (PLLOS)
2 PLL2
Oscillator stabilization wait period selector
PLL multiplier circuit
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Sub clock generator circuit
X0A X1A
Clock select register (CKSCR)
System clock generator circuit
pin pin
X0 X1
×2
× 1024 Timebase timer
×2
×4
×4
×4
×2
pin pin
HCLK
MCLK
To watchdog timer HCLK : Oscillator clock MCLK : Main clock SCLK : Sub clock
67
MB90480/485 Series
(3) Status Transition Chart
External reset, watchdog timer reset, software reset Power-on reset Reset
Power-on reset
SCS = 0 SCS = 1 MCS = 0 MCS = 1 SCS = 0 SCS = 1
Oscillator stabilization wait ends
Main clock mode
SLP = 1
PLL clock mode
SLP = 1
Sub clock mode
SLP = 1
Interrupt
Interrupt
Interrupt
Main sleep mode
TMD = 0
PLL sleep mode
TMD = 0
Sub sleep mode
TMD = 0
Interrupt
Interrupt
Interrupt
Timebase timer mode
STP = 1
Timebase timer mode
STP = 1
Watch mode
STP = 1
Main stop mode
Interrupt
Oscillator stabilization wait ends
PLL stop mode
Interrupt
Oscillator stabilization wait ends
Sub stop mode
Interrupt
Oscillator stabilization wait ends
Main clock oscillator
stabilization wait
Main clock oscillator
stabilization wait
Sub clock oscillator
stabilization wait
68
MB90480/485 Series
18. External Bus Pin Control Circuit
The external bus pin control circuit controls the external bus pins used to expand the CPU address/data bus connections to external circuits. (1) Register List • Auto ready function select register (ARSR) Address : 0000A5H
bit 15 IOR1 W bit 14 IOR0 W bit 13 HMR1 W bit 12 HMR0 W bit 11 bit 10 bit 9 LMR1 W bit 8 LMR0 W
Initial value 0011- - 00B
• External address output control register (HACR) Address : 0000A6H
bit 7 E23 W bit 6 E22 W bit 5 E21 W bit 4 E20 W bit 3 E19 W bit 2 E18 W bit 1 E17 W bit 0 E16 W
Initial value ********B
• Bus control signal select register (EPCR) Address : 0000A7H
bit 15 CKE W bit 14 RYE W bit 13 HDE W bit 12 IOBS W bit 11 HMBS W bit 10 WRE W bit 9 LMBS W bit 8
Initial value 1000*10 -B
W − *
: Write only : Not used : May be either “1” or “0”
(2) Block Diagram
P5 P2 P3 P4 P5
P0
P1
P0 data P0 direction
P0
RB
Data control
Address control
Access control
Access control
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MB90480/485 Series
19. Chip Select Function Description
The chip select module generators a chip select signals, which are used to facilitate connections to external memory devices. The MB90480/485 series has four chip select output pins, each having a chip select area register setting that specifies the corresponding hardware area and select signal that is output when access to the corresponding external address is detected. • Chip select function features The chip select function uses two 8-bit registers for each output pin. One of these registers (CARx) is able to detect memory areas in 64 Kbyte units by specifying the upper 8-bit of the address for match detection. The other register (CMRx) can be used to expand the detection area beyond 64 Kbytes by masking bits for match detection. Note that during external bus holds, the CS output is set to high impedance. (1) Register List
15 CAR0 CAR1 CAR2 CAR3 CALR 87 CMR0 CMR1 CMR2 CMR3 CSCR 0 R/W R/W R/W R/W R/W R/W
Chip select area mask register (CMRx) 0000C0H 0000C2H 0000C4H 0000C6H
7 M7 R/W 0 6 M6 R/W 0 5 M5 R/W 0 4 M4 R/W 0 3 M3 R/W 1 2 M2 R/W 1 1 M1 R/W 1 0 M0 R/W 1
Read/write initial value
Chip select area register (CARx) 0000C1H 0000C3H 0000C5H 0000C7H
15 A7 R/W 1 14 A6 R/W 1 13 A5 R/W 1 12 A4 R/W 1 11 A3 R/W 1 10 A2 R/W 1 9 A1 R/W 1 8 A0 R/W 1
Read/write initial value
Chip select control register (CSCR)
7 6 5 4 3 OPL3 R/W 0 2 OPL2 R/W 0 1 OPL1 R/W 0 0 OPL0 R/W *
0000C8H
Read/write initial value
Chip select active level register (CALR)
15 14 13 12 11 ACTL3 R/W 0 10 ACTL2 R/W 0 9 ACTL1 R/W 0 8 ACTL0 R/W 0
0000C9H
Read/write initial value
* : The initial value of this bit is “1” or “0”. The value depends on the mode pin (MD2, MD1 and MD0) . 70
MB90480/485 Series
(2) Block Diagram
F2MC-16LX Bus
CMRx
CARx
Chip select output pins
A23 to A16
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MB90480/485 Series
20. ROM Mirror Function Select Module
The ROM mirror function selection module sets the data in ROM assigned to FF bank so that the data is read by access to 00 bank. (1) Register List • ROM mirror function select register (ROMM) bit 15 14 Address : 00006FH
13
12
11
10
9 MS R/W
8 MI R/W
Initial value - - - - - -01B
- : Not used
(2) Block Diagram
F2MC-16LX bus ROM mirror function select
Address area 00 bank FF bank
ROM
Note : Do not access ROM mirror function selection register (ROMM) on using the area of address 004000H to 00FFFFH (008000H to 00FFFFH) .
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MB90480/485 Series
21. Interrupt Controller
The interrupt control register is built in interrupt control, and is supported for all I/O of interrupt function. This register set corresponding peripheral interrupt level. (1) Register List Interrupt control registers Address : ICR01 ICR03 ICR05 ICR07 ICR09 ICR11 ICR13 ICR15 0000B1H 0000B3H 0000B5H 0000B7H 0000B9H 0000BBH 0000BDH 0000BFH bit
15 14 13 12 11 10 IL2 IL1 9 IL0 8
Reserved
ICR01, 03, 05, 07, 09, 11, 13, 15
Read/write→ Initial value→
W X
W X
W X
W X
R/W 0
R/W 1
R/W 1
R/W 1
Interrupt control registers Address : ICR00 ICR02 ICR04 ICR06 ICR08 ICR10 ICR12 ICR14 0000B0H 0000B2H 0000B4H 0000B6H 0000B8H 0000BAH 0000BCH 0000BEH bit
7 6 5 4 3 IL2 2 IL1 1 IL0 0
Reserved
ICR00, 02, 04, 06, 08, 10, 12, 14
Read/write→ Initial value→
W X
W X
W X
W X
R/W 0
R/W 1
R/W 1
R/W 1
Note : The use of access involving read-modify-write instructions may lead to abnormal operation, and should be avoided.
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MB90480/485 Series
(2) Block Diagram
3
IL2
IL1
IL0
3
32
Interrupt requests (Peripheral resources)
F2MC-16LX Bus
Interrupt priority setting
3
(CPU) Interrupt level
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MB90480/485 Series
22. µDMAC
The µDMAC is a simplified DMA module with functions equivalent to EI2OS. The µDMA has 16 DMA data transfer channels, and provides the following functions. • Automatic data transfer between peripheral resources (I/O) and memory. • CPU program execution stops during DMA operation. • Incremental addressing for transfer source and destination can be turned on and off. • DMA transfer control from the DMA enable register, DMA stop status register, DMA status register, and descriptor. • Stop requests from resources can stop DMA transfer. • When DMA transfer is completed, the DMA status register sets a flag in the bit for the corresponding channel on which transfer was completed, and outputs a completion interrupt to the interrupt controller. (1) Register List µDMA enable register bit DERH : 0000ADH
15 EN15 R/W 14 EN14 R/W 13 EN13 R/W 12 EN12 R/W 11 EN11 R/W 10 EN10 R/W 9 EN9 R/W 8 EN8 R/W
Initial value 00000000B
µDMA enable register bit DERL : 0000ACH
7 EN7 R/W 6 EN6 R/W 5 EN5 R/W 4 EN4 R/W 3 EN3 R/W 2 EN2 R/W 1 EN1 R/W 0 EN0 R/W
Initial value 00000000B
µDMA stop status register bit DSSR : 0000A4H
7 STP7 R/W
6 STP6 R/W
5 STP5 R/W
4 STP4 R/W
3 STP3 R/W
2 STP2 R/W
1 STP1 R/W
0 STP0 R/W
Initial value 00000000B
µDMA status register bit DSRH : 00009DH
15 DE15 R/W 14 DE14 R/W 13 DE13 R/W 12 DE12 R/W 11 DE11 R/W 10 DE10 R/W 9 DE9 R/W 8 DE8 R/W
Initial value 00000000B
µDMA status register bit DSRL : 00009CH
7 DE7 R/W 6 DE6 R/W 5 DE5 R/W 4 DE4 R/W 3 DE3 R/W 2 DE2 R/W 1 DE1 R/W 0 DE0 R/W
Initial value 00000000B
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MB90480/485 Series
(2) Block Diagram
Memory space
by IOA
I/O register
I/O register If transfer not ended
Peripheral function (I/O)
F2MC-16LX Bus
DMA transfer request DMA controller If transfer is ended
DMA descriptor
Read by DER
by BAP
Transfer
Buffer
by DCT CPU
Interrupt controller
IOA BAP DER DCT
: I/O address pointer : Buffer address pointer : DMA enable register (ENx selection) : Data counter
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MB90480/485 Series
23. Address Match Detection Function
When the address is equal to a value set in the address detection register, the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code (01H). As a result, when the CPU executes a set instruction, the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program patching function to be implemented. Two address detection registers are supported. An interrupt enable bit is prepared for each register. If the value set in the address detection register matches an address and if the interrupt enable bit is set at “1”, the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code. (1) Register Configuration • Program address detection register 0 (PADR0)
Address PADR0 (Low order address): 001FF0H R/W Address PADR0 (Middle order address): 001FF1H R/W Address PADR0 (High order address): 001FF2H R/W Address PADR1 (Low order address): 001FF3H R/W Address PADR1 (Middle order address): 001FF4H R/W Address PADR1 (High order address): 001FF5H R/W Address 00009EH bit 7 RESV R/W R/W :Readable and writable X :Undefined RESV:Reserved bit R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 AD0E R/W R/W bit 0 RESV R/W Initial value 00000000 B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value XXXXXXXX B
• Program address detection register 1 (PADR1)
• Program address detection control status register (PACSR)
RESV RESV R/W R/W RESV AD1E RESV R/W R/W R/W
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MB90480/485 Series
(2) Block Diagram
Internal data bus
Address detection register
Compare
Address latch
INT9 instruction
Enable bit
F2MC-16LX CPU core
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MB90480/485 Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Symbol VCC3 Power supply voltage*1 VCC5 AVCC AVRH Input voltage*1 Output volatage*1 Maximum clamp current Total maximum clamp current “L” level maximum output current “L” level average output current “L” level maximum total output current “L” level total average output current “H” level maximum output current “H” level average output current “H” level maximum total output current “H” level total average output current Power consumption Operating temperature Storage temperature VI VO ICLAMP ΣICLAMP IOL IOLAV ΣIOL ΣIOLAV IOH IOHAV ΣIOH ΣIOHAV PD TA Tstg Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 −2.0 −40 −55 Max VSS + 4.0 VSS + 7.0 VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 7.0 VSS + 4.0 VSS + 7.0 +2.0 20 10 3 60 30 −10 −3 −60 −30 320 +85 +150 Unit V V V V V V V V mA mA mA mA mA mA mA mA mA mA mW °C °C *6 *6 *4 *5 *3 *3, *8, *9 *3 *3, *8, *9 *7 *7 *4 *5 *2 Remarks
*1 : This parameter is based on VSS = AVSS = 0.0 V. *2 : AVCC and AVRH must not exceed VCC. Also, AVRH must not exceed AVCC. *3 : V1 and V0 must not exceed VCC + 0.3 V. However, if the maximum current to/from and input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *4 : Maximum output current is defined as the peak value for one of the corresponding pins. *5 : Average output current is defined as the average current flow in a 100 ms interval at one of the corresponding pins. *6 : Average total output current is defined as the average current flow in a 100 ms interval at all corresponding pins. *7 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P46, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA3 • Use within recommended operating conditions. • Use at DC voltage (current) . • The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. 79
MB90480/485 Series
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. • Care must be taken not to leave the +B input pin open. • Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. • Sample recommended circuits: • Input/Output Equivalent circuits Protective diode Limiting resistance
VCC P-ch
+B input (0 V to 16 V)
N-ch
R
*8 : MB90485 series only P20 to P27, P30 to P37, P40 to P47, P70 to P77 pins can be used as 5 V I/F pin on applied 5 V to VCC5 pin. P76 and P77 is Nch open drain pin. *9 : As for P76 and P77 (Nch open drain pin) , even if using at 3 V simplicity (VCC3 = VCC5) , the ratings are applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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MB90480/485 Series
2. Recommended Operating Conditions
Value Min 2.7 1.8 2.7 1.8 0.7 VCC 0.7 VCC 0.8 VCC VCC − 0.3 0.8 VCC VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 −40 Max 3.6 3.6 5.5 5.5 VCC + 0.3 VSS + 5.8 VCC + 0.3 VCC + 0.3 VCC + 0.3 0.3 VCC 0.2 VCC VSS + 0.3 0.1 +85
(VSS = AVSS = 0.0 V) Unit V V V V V V V V V V V V V °C Remarks During normal operation To maintain RAM state in stop mode During normal operation* To maintain RAM state in stop mode* All pins other than VIH2, VIHS, VIHM and VIHX MB90485 series only P76, P77 pins (Nch open drain pins) Hysteresis input pins MD pin input X0A pin, X1A pin All pins other than VILS, VILM and VILX Hysteresis input pins MD pin input X0A pin, X1A pin
Parameter
Symbol VCC3
Supply voltage VCC5 VIH VIH2 “H” level input voltage VIHS VIHM VIHX VIL “L” level input voltage VILS VILM VILX Operating temperature TA
* : MB90485 series only P20 to P27, P30 to P37, P40 to P47, P70 to P77 pins can be used as 5 V I/F pin on applied 5 V to VCC5 pin. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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MB90480/485 Series
3. DC Characteristics
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Condition VCC = 2.7 V, IOH = −1.6 mA VCC = 4.5 V, IOH = −4.0 mA VCC = 2.7 V, IOL = 2.0 mA VCC = 4.5 V, IOH = 4.0 mA VCC = 3.3 V, VSS < VI < VCC VCC = 3.0 V, at TA = +25 °C At VCC = 3.3 V, internal 25 MHz operation, normal operation At VCC = 3.3 V, internal 25 MHz operation, FLASH programming At VCC = 3.3 V, internal 25 MHz operation, sleep mode At VCC = 3.3 V, external 32 kHz, internal 8 kHz operation, sub clock operation (TA = +25 °C) At VCC = 3.3 V, external 32 kHz, internal 8 kHz operation, watch mode (TA = +25 °C) TA = +25 °C, stop mode, At VCC = 3.3 V Min Value Typ 53 0.1 45 Max 0.4 0.4 +10 200 10 60 Unit V V V V µA kΩ µA mA At using 5 V power supply At using 5 V power supply
Remarks
“H” level output voltage
VOH
All output pins
VCC3 − 0.3 VCC5 − 0.5 −10 20
“L” level output voltage
VOL
All output pins
All input Input leakage IIL pins current Pull-up RPULL resistance P40 to P47, Open drain Ileak P70 to P77 output current
ICC
55
70
mA
ICCS Power supply current ICCL
17
35
mA
15
140
µA
ICCT
Other than AVCC, AVSS, VCC, VSS
1.8
40
µA µA pF
ICCH Input capacitance CIN
0.8 5
40 15
Notes : • Pins P40 to P47, and P70 to P77 are controlled N-ch open drain pins, and should always be used at CMOS levels. • MB90485 series only • P40 to P47 and P70 to P77 are Nch open drain pins with control, which are usually used as CMOS. • P76 and P77 are open drain pins without Pch. • For use as a single 3 V power supply products, set VCC = VCC3 = VCC5. • When the device is used with dual power supplies, P20 to P27, P30 to P37, P40 to P47 and P70 to P77 serve as 5 V pins while the other pins serve as 3 V I/O pins.
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MB90480/485 Series
4. AC Characteristics
(1) Clock Timing Standards Symbol Condition Clock frequency FCH X0, X1 FCL Clock cycle time tC tCL PWH PWL PWLH PWLL tcr tcf fCP fCPL tCP tCPL X0A, X1A X0, X1 X0A, X1A X0 X0A X0 Value Min 3 3 4 3 3 3 3 3 20 5 1.5 40.0 Typ 32.768 30.5 15.2 8.192 122.1 Max 25 50 25 12.5 6.66 6.25 4.16 3.12 333 5 25 666 kHz ns µs ns µs ns *2 With external clock *1 (VSS = 0.0 V, TA = −40 °C to +85 °C) Pinname Unit Remarks External crystal oscillator External clock input 1 multiplied PLL MHz 2 multiplied PLL 3 multiplied PLL 4 multiplied PLL 6 multiplied PLL 8 multiplied PLL
Parameter
Input clock pulse width
Input clock rise, fall time Internal operating clock frequency Internal operating clock cycle time
MHz *1 kHz ns µs *1
*1 : Be careful of the operating voltage. *2 : Duty raito should be 50 % ± 3 %.
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MB90480/485 Series
• X0, X1 clock timing
tC
X0
PWH tcf PWL tcr
0.8 VCC 0.2 VCC
• X0A, X1A clock timing
tCL
X0A
PWLH tcf PWLL tcr
0.8 VCC 0.1 V
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MB90480/485 Series
• Range of warranted PLL operation Internal operating clock frequency vs. Power supply voltage
3.6 Range of warranted PLL operation 3.0 2.7 Normal operating range
Supply voltage VCC (V)
1.5
4
16
25
Internal clock fCP (MHz) Notes: • For A/D operating frequency, refer to “5. A/D Converter Electrical Characteristics” • Only at 1 multiplied PLL, use with more than fcp = 4 MHz. Base oscillator frequency vs. Internal operating clock frequency
25 24
8 × *3 6 × *3 3 × *1 2 × *1,*2 4× *1,*2 1 × *1 No multiplied
Internal clock fCP (MHz)
20 18 16 12 9 8 6 4 1.5
3 4 5 6 8 10 12.5
16
20
25
32
40
50
Base oscillator clock FCH (MHz) *1 : In setting as 1, 2, 3 and 4 multiplied PLL, when the internal clock is used at 20 MHz < fcp ≤ 25 MHz, set the PLLOS register to “DIV2 bit = 1” and “PLL2 bit = 1”. [Example] When using the base oscillator frequency of 24 MHz at 1 multiplied PLL : CKSCR register : CS1 bit = “0”, CS0 bit = “0” PLLOS register : DIV2 bit = “1”, PLL2 bit = “1” [Example] When using the base oscillator frequency of 6 MHz at 3 multiplied PLL : CKSCR register : CS1 bit = “1”, CS0 bit = “0” PLLOS register : DIV2 bit = “1”, PLL2 bit = “1” *2 : In setting as 2 and 4 multiplied PLL, when the internal clock is used at 20 MHz < fcp ≤ 25 MHz, the following setting is also enabled. 2 multiplied PLL : CKSCR register : CS1 bit = “0”, CS0 bit = “0” PLLOS register : DIV2 bit = “0”, PLL2 bit = “1” 4 multiplied PLL : CKSCR register : CS1 bit = “0”, CS0 bit = “1” PLLOS register : DIV2 bit = “0”, PLL2 bit = “1” *3 : When using in setting as 6 and 8 multiplied PLL, set the PLLOS register to “DIV2 bit = 0” and “PLL2 bit = 1”. [Example] When using the base oscillator frequency of 4 MHz at 6 multiplied PLL : CKSCR register : CS1 bit = “1”, CS0 bit = “0” PLLOS register : DIV2 bit = “0”, PLL2 bit = “1” [Example] When using the base oscillator frequency of 3 MHz at 8 multiplied PLL : CKSCR register : CS1 bit = “1”, CS0 bit = “1” PLLOS register : DIV2 bit = “0”, PLL2 bit = “1” 85
MB90480/485 Series
AC standards are set at the following measurement voltage values. • Input signal waveform Hysteresis input pins
0.8 VCC 0.2 VCC
• Output signal waveform Output pins
2.4 V 0.8 V
• Pins other than hysteresis input/MD input
0.7 VCC 0.3 VCC
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MB90480/485 Series
(2) Clock Output Timing Value Min tCP* Max
(VSS = 0.0 V, TA = −40 °C to +85 °C) Conditions Unit ns ns ns ns at fcp = 25 MHz at fcp = 16 MHz at fcp = 5 MHz Remarks
Parameter Cycle time CLK↑→CLK↓
Symbol Pin name tCYC tCHCL CLK CLK
VCC = 3.0 V to 3.6 V tCP* / 2 − 15 tCP* / 2 + 15 VCC = 2.7 V to 3.3 V tCP* / 2 − 20 tCP* / 2 + 20 VCC = 2.7 V to 3.3 V tCP* / 2 − 64 tCP* / 2 + 64 * : For tCP see “ (1) Clock Timing Standards.”
tCYC tCHCL 2.4 V 2.4 V 0.8 V
CLK
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MB90480/485 Series
(3) Reset Input Standards Pin name Conditions
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Value Min 16 tCP Oscillator oscillation time* + 4 tCP Max Unit ns ms Remarks Normal operation Stop mode
Parameter
Symbol
Reset input time
tRSTL
RST
* : Oscillator oscillation time is the time to 90 % of amplitude. For a crystal oscillator this is on the order of several milliseconds to tens of milliseconds. For a FAR/ceramic oscillator, this is several hundred microseconds to several milliseconds. For an external clock signal the value is 0 ms. • In stop mode
tRSTL RST
0.2 Vcc 0.2 Vcc
X0
90 % of amplitude
Internal operating clock
Oscillator oscillation time
4 tcp Oscillator stabilization wait time
Instruction execution Internal reset
• Condition for measurement of AC standards Pin CL : Load capacitance applied during testing CLK, ALE : CL = 30 pF AD15 to AD00 (address data bus) , RD, WR, A23 to A00/D15 to D00 : CL = 30 pF
CL
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MB90480/485 Series
(4) Power-on Reset Standards
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Value Min 1 Max 30 Unit ms ms * In repeated operation Remarks
Parameter Power rise time Power down time
Symbol tR tOFF
Pin name Conditions VCC VCC
* : Power rise time requires VCC < 0.2 V. Notes: • The above standards are for the application of a power-on reset. • Within the device, the power-on reset should be applied by switching the power supply off and on again.
tR
VCC
2.7 V 0.2 V 0.2 V tOFF 0.2 V
Rapid fluctuations in power supply voltage may trigger a power-on reset in some cases. As shown below, when changing supply voltage during operation, it is recommended that voltage changes be suppressed and a smooth restart be applied.
Main power supply voltage VCC Sub power supply voltage VSS
RAM data maintenance
The slope of voltage increase should be kept within 50 mV/ms.
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MB90480/485 Series
(5) Bus Read Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C) Symbol Pin name Conditions Value Min tCP* / 2 − 15 tCP* / 2 − 20 tCP* / 2 − 35 tCP* / 2 − 17 tCP* / 2 − 40 tCP* / 2 − 15 tCP* − 25
3 tCP* / 2 − 25 3 tCP* / 2 − 20
Parameter
Max
5 tCP* / 2 − 55 5 tCP* / 2 − 80
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks at fcp = 25 MHz at fcp = 16 MHz at fcp = 8 MHz at fcp = 8 MHz
ALE pulse width Valid address→ ALE↓time ALE↓→ address valid time Valid address→ RD↓time Valid address→ valid data input RD pulse width RD↓→ valid data input RD↑→data hold time RD↑→ALE↑rise time RD↑→ address valid time Valid address→ CLK↑time RD↓→CLK↑time ALE↓→RD↓time
tLHLL
ALE
tAVLL tLLAX tAVRL tAVDV tRLRH tRLDV tRHDX tRHLH tRHAX tAVCH tRLCH tLLRL
Address, ALE ALE, Address RD, address Address, Data RD RD, Data RD, Data RD, ALE Address, RD Address, CLK RD, CLK RD, ALE
at fcp = 8 MHz at fcp = 25 MHz at fcp = 16 MHz at fcp = 8 MHz
3 tCP* / 2 − 55 3 tCP* / 2 − 80
0 tCP* / 2 − 15 tCP* / 2 − 10 tCP* / 2 − 17 tCP* / 2 − 17 tCP* / 2 − 15
* : tCP : See “ (1) Clock Timing Standards”.
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MB90480/485 Series
tAVCH 2.4 V
tRLCH 2.4 V
CLK
tRHLH
ALE
2.4 V tLHLL
2.4 V 0.8 V tRLRH
2.4 V
RD
2.4 V tAVLL tLLAX tLLRL 0.8 V
In multiplexed mode
A23 to A16
2.4 V 0.8 V
tAVRL
tRLDV
tRHAX 2.4 V 0.8 V
tAVDV 2.4 V 2.4 V 0.7 VCC
tRHDX 0.7 VCC
AD15 to AD00
0.8 V
Address
0.8 V 0.3 VCC
Read data
0.3 VCC tRHAX
In non-multiplexed mode
A23 to A00
2.4 V 0.8 V tRLDV tAVDV 0.7 VCC
2.4 V 0.8 V
tRHDX 0.7 VCC
D15 to D00
0.3 VCC
Read data
0.3 VCC
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MB90480/485 Series
(6) Bus Write Timing
Symbol
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C) Pin name Address, WR WRL, WRH Data, WR WR, Data WR, Address WR, ALE WR, CLK Condition Value Min tCP* − 15
3 tCP* / 2 − 25 3 tCP* / 2 − 20 3 tCP* / 2 − 15
Parameter Valid address→WR↓time WR pulse width
Max
Unit ns ns ns ns ns ns ns ns ns ns
Remarks
tAVWL tWLWH
at fcp = 25 MHz at fcp = 16 MHz at fcp = 25 MHz at fcp = 16 MHz at fcp = 8 MHz
Valid data output →WR↑time tDVWH WR↑→data hold time WR↑→address valid time WR↑→ALE↑time WR↓→CLK↑time tWHDX tWHAX tWHLH tWLCH
10 20 30 tCP* / 2 − 10 tCP* / 2 − 15 tCP* / 2 − 17
* : tCP : See “ (1) Clock Timing Standards”.
tWLCH 2.4 V
CLK
tWHLH
ALE
tWLWH 2.4 V
2.4 V
WR (WRL, WRH)
0.8 V
In multiplexed mode
A23 to A16
2.4 V 0.8 V
tAVWL
tWHAX 2.4 V 0.8 V tDVWH tWHDX 2.4 V
2.4 V
AD15 to AD00
0.8 V
Address
2.4 V 0.8 V
Write data
0.8 V tWHAX
In non-multiplexed mode
A23 to A00
2.4 V 0.8 V tDVWH 2.4 V 0.8 V
2.4 V 0.8 V tWHDX 2.4 V 0.8 V
D15 to D00
Write data
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MB90480/485 Series
(7) Ready Input Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C) Symbol tRYHS tRYHH Pin name Conditions RDY Value Min 35 70 0 Max Unit ns ns ns at fcp = 8 MHz Remarks
Parameter RDY setup time RDY hold time
Notes: • If the RDY setup time is insufficient, use the auto ready function. • Warning : For input from the RDY pin, if the AC ratings are not satisfied this device may unexpected operation.
2.4 V
2.4 V
CLK
ALE
RD/WR
tRYHS tRYHH
RDY wait not inserted RDY wait inserted (1 cycle)
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC tRYHS
93
MB90480/485 Series
(8) Hold Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C) Symbol tXHAL tHAHV Pin name HAK HAK Conditions Value Min 30 tCP Max tCP* 2 tCP* Unit ns ns Remarks
Parameter Pin floating→HAK↓time HAK↓→pin valid time
* : tCP : See “ (1) Clock Timing Standards”. Note : One or more cycles are required from the time the HRQ pin is read until the HAK signal changes.
HAK
0.8 V tXHAL 2.4 V 0.8 V
2.4 V tHAHV
Pins
High-Z
2.4 V 0.8 V
(9) UART Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin External shift clock mode output pins : CL*1 = 80 pF + 1 TTL Internal shift clock mode output pins : CL*1 = 80 pF + 1 TTL Conditions Value Min 8 tCP*2 −80 −120 100 200 t*
CP 2
Parameter Serial clock cycle time SCK↓→SOT delay time Valid SIN→SCK↑ SCK↑→valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK↓→SOT delay time Valid SIN→SCK↑ SCK↑→valid SIN hold time
Max +80 +120 150 200
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks
fcp = 8 MHz fcp = 8 MHz
4 tCP*2 4 tCP*2 60 120 60 120
fcp = 8 MHz fcp = 8 MHz fcp = 8 MHz
*1 : CL is the load capacitance applied to pins for testing. *2 : tCP : See “ (1) Clock Timing Standards”. Note : AC ratings are for CLK synchronized mode.
94
MB90480/485 Series
• Internal shift clock mode
tSCYC
SCK
0.8 V tSLOV 2.4 V
2.4 V 0.8 V
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
• External shift clock mode
tSLSH tSHSL 0.8 VCC 0.2 VCC tSLOV 2.4 V 0.2 VCC 0.8 VCC
SCK
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
95
MB90480/485 Series
(10) I/O Expanded Serial Interface Timing Pin name External shift clock mode output pins : CL*1 = 80 pF + 1 TTL Internal shift clock mode output pins : CL*1 = 80 pF + 1 TTL
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Conditions Value Min 8 tCP*2 −80 −120 100 200 tCP*2 4t * 4t * 60 120 60 120
CP 2 CP 2
Parameter Serial clock cycle time SCK↓→SOT delay time Valid SIN→SCK↑ SCK↑→valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK↓→SOT delay time Valid SIN→SCK↑ SCK↑→valid SIN hold time
Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX
Max + 80 + 120 150 200
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks
fcp = 8 MHz fcp = 8 MHz
fcp = 8 MHz fcp = 8 MHz fcp = 8 MHz
*1 : CL is the load capacitance applied to pins for testing. *2 : tCP : See “ (1) Clock Timing Standards”. Notes : • AC ratings are for CLK synchronized mode. • Values on this table are target values.
96
MB90480/485 Series
• Internal shift clock mode
tSCYC
SCK
0.8 V tSLOV 2.4 V
2.4 V 0.8 V
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
• External shift clock mode
tSLSH tSHSL 0.8 VCC 0.2 VCC tSLOV 2.4 V 0.2 VCC 0.8 VCC
SCK
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
97
MB90480/485 Series
(11) Timer Input Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Pin name TIN0, IN0, IN1, PWC0 to PWC3 Conditions Value Min 4 tCP* Max Unit Remarks
Parameter
Symbol tTIWH tTIWL
Input pulse width
ns
* : tCP : See “ (1) Clock Timing Standards”.
TIN0 IN0, IN1
0.8 VCC
0.8 VCC 0.2 VCC tTIWH tTIWL 0.2 VCC
(12) Timer Output Timing Symbol tTO
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Pin name TOT0, PPG0 to PPG5, OUT0 to OUT5 Conditions Load conditions 80 pF Value Min 30 Max Unit Remarks
Parameter CLK↑→Tout change time PPG0 to PPG5 change time OUT0 to OUT5 change time
ns
CLK
0.7 VCC
TOUT PPG0 to PPG5 OUT0 to OUT5
0.7 VCC 0.3 VCC
tTO
98
MB90480/485 Series
(13) I2C Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol fSCL tHDSTA tLOW tHIGH tSUSTA tHDDAT When power supply voltage of external pull-up resistance is 5.5 V fcp*1 ≤ 20 MHz, R = 1.3 kΩ, C = 50 pF*2 When power supply voltage of external pull-up resistance is 3.6 V fcp*1 ≤ 20 MHz, R = 1.6 kΩ, C = 50 pF*2 When power supply voltage of external pull-up resistance is 5.5 V fcp*1 > 20 MHz, R = 1.3 kΩ, C = 50 pF*2 When power supply voltage of external pull-up resistance is 3.6 V fcp*1 > 20 MHz, R = 1.6 kΩ, C = 50 pF*2 When power supply voltage of external pull-up resistance is 5.5 V R = 1.3 kΩ, C = 50 pF*2 When power supply voltage of external pull-up resistance is 3.6 V R = 1.6 kΩ, C = 50 pF*2 When power supply voltage of external pull-up resistance is 5.5 V R = 1.3 kΩ, C = 50 pF*2 When power supply voltage of external pull-up resistance is 3.6 V R = 1.6 kΩ, C = 50 pF*2 Condition Standard-mode Min 0 4.0 4.7 4.0 4.7 0 Max 100 3.45*3 Unit kHz µs µs µs µs µs
Parameter SCL clock frequency Hold time (repeated) START condition SDA↓→SCL↓ “L” width of the SCL clock “H” width of the SCL clock Set-up time (repeated) START condition SCL↑→SDA↓ Data hold time SCL↓→SDA↓↑
250
ns
Data set-up time SDA↓↑→SCL↑
tSUDAT
200
ns
Set-up time for STOP condition SCL↑→SDA↑ Bus free time between a STOP and START condition
tSUSTO
4.0
µs
tBUS
4.7
µs
*1 : fcp is internal operation clock frequency. Refer to “ (1) Clock Timing Standards”. *2 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines. *3 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal. Note : VCC = VCC3 = VCC5
SDA tLOW SCL tHIGH tHDSTA tHDDAT tSUSTA tSUSTO tSUDAT tHDSTA tBUS
99
MB90480/485 Series
(14) Trigger Input Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Pin name ADTG, IRQ0 to IRQ7 Conditions Value Min 5 tCP* 1 Max Unit ns µs Remarks Normal operation Stop mode
Parameter Input pulse width
Symbol tTRGH tTRGL
* : tCP : See “ (1) Clock Timing Standards”.
IRQ0 to IRQ7 ADTG
0.8 VCC
0.8 VCC 0.2 VCC tTRGH tTRGL 0.2 VCC
(15) Up-down Counter Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Pin name Conditions Value Min 8 tCP* 8 tCP* 8 tCP* 8 tCP* 4 tCP* AIN0, AIN1, BIN0, BIN1 4 tCP* Load conditions 80 pF 4 tCP* 4 tCP* 4 tCP* 4 tCP* 4 tCP* 4 tCP* ZIN0, ZIN1 4 tCP* 4 tCP* Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks
Parameter AIN input “H” pulse width AIN input “L” pulse width BIN input “H” pulse width BIN input “L” pulse width AIN↑→BIN↑ rise time BIN↑→AIN↓ fall time AIN↓→BIN↑ rise time BIN↓→AIN↑ rise tome BIN↑→AIN↑ rise time AIN↑→BIN↓ fall time BIN↓→AIN↑ rise time AIN↓→BIN↑ rise time ZIN input “H” pulse width ZIN input “L” pulse width
Symbol tAHL tALL tBHL tBLL tAUBU tBUAD tADBD tBDAU tBUAU tAUBD tBDAD tADBU tZHL tZLL
* : tCP : See “ (1) Clock Timing Standards”.
100
MB90480/485 Series
tAHL 0.8 VCC 0.8 VCC 0.2 VCC
tALL
AIN
0.2 VCC
tAUBU
tBUAD
tADBD
tBDAU
0.8 VCC
0.8 VCC 0.2 VCC tBHL tBLL 0.2 VCC
BIN
0.8 VCC
0.8 VCC 0.2 VCC 0.2 VCC
BIN
tBUAU
tAUBD
tBDAD
tADBU
0.8 VCC
AIN
0.2 VCC
0.8 VCC
0.8 VCC
ZIN
tZHL tZLL
0.2 VCC
0.2 VCC
101
MB90480/485 Series
(16) Chip Select Output Timing Symbol tSVRL tSVWL tRHSV tWHSV
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Pin name CS0 to CS3, RD CS0 to CS3, WRH, WRL RD, CS0 to CS3 WRH, WRL, CS0 to CS3 Conditions Value Min tCP* / 2 − 7 tCP* / 2 − 7 tCP* / 2 − 17 tCP* / 2 − 17 Max Unit ns ns ns ns Remarks
Parameter Chip select output valid time →RD↓ Chip select output valid time→WR↓ RD↑→chip select output valid time WR↑→chip select output valid time
* : tCP : See “ (1) Clock Timing Standards”.
tSVRL 2.4 V
RD
0.8 V tRHSV 2.4 V 0.8 V
A23 to A16 CS0 to CS3
D15 to D00
2.4 V
Read data
0.8 V tSVWL tWHSV 2.4 V 0.8 V
WRH, WRL
D15 to D00 Undefined
Write data
Note : Due to the configuration of the internal bus, changes in the chip select output signal are clock synchronous and therefore may causes bus conflict conditions. AC cannot be warranted between the ALE output signal and the chip select output signal.
102
MB90480/485 Series
5. A/D Converter Electrical Characteristics
(VCC = AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, 2.7 V ≤ AVRH, TA = −40 °C to +85 °C) Value Min AVSS − 1.5 LSB AVRH − 3.5 LSB 3.68 *1 AVSS AVSS + 2.2 Typ AVSS + 0.5 LSB AVRH − 1.5 LSB 0.1 1.4 94 Max 10 ±3.0 ±2.5 ±1.9 AVSS + 2.5 LSB AVRH + 0.5 LSB 10 AVRH AVCC 3.5 5 *2 150 5* 4
2
Parameter Resolution Total error Non-linear error Differential linearity error Zero transition voltage Full scale transition voltage Conversion time Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Offset between channels
Symbol Pin name VOT VFST IAIN VAIN IA IAH IR IRH AN0 to AN7 AN0 to AN7 AN0 to AN7 AN0 to AN7 AVRH AVCC AVCC AVRH AVRH AN0 to AN7
Unit bit LSB LSB LSB mV mV µs µA V V mA µA µA µA LSB
Remarks
*1 : At machine clock frequency of 25 MHz. *2 : CPU stop mode current when A/D converter is not operating (at VCC = AVCC = AVRH = 3.0 V) .
(Continued)
103
MB90480/485 Series
(Continued)
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. • Analog input circuit model
R
Analog input During sampling : ON
C
Comparator
Note: The values are reference values.
MB90487 MB90F481/F482 MB90F488
R 2.5 kΩ (Max) 1.9 kΩ (Max) 1.9 kΩ (Max)
C 31.0 pF (Max) 25.0 pF (Max) 25.0 pF (Max)
• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. External impedance = 0 kΩ to 100 kΩ
MB90F481/F482 MB90F488 MB90487
20
External impedance = 0 kΩ to 100 kΩ
MB90F481/F482 MB90F488 MB90487
100
→ External impedance [kΩ]
→ External impedance [kΩ]
0 5 10 15 20 25 30 35
90 80 70 60 50 40 30 20 10 0
18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8
→ Minimum sampling time [µs]
→ Minimum sampling time [µs]
The relationship between external impedance and minimum sampling time • If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. As |AVRH − AVSS| becomes smaller, values of relative errorsgrow larger. Note : Concerning sampling time, and compare time When 3.6 V ≥ AVCC ≥ 2.7 V, then Sampling time : 1.92 µs, compare time : 1.1 µs Settings should ensure that actual values do not go below these values due to operating frequency changes.
104
MB90480/485 Series
• Flash Memory Program/Erase Characteristics Parameter Sector erase time Chip erase time Word (16-bit) programming time Program/Erase cycle Data hold time TA = + 25 °C, VCC = 3.0 V Conditions Value Min 10,000 100,000 Typ 1 7 16 Max 15 3,600 Unit s s µs cycle h Remarks Excludes 00H programming prior erasure Excludes 00H programming prior erasure Excludes system-level overhead
• Use of the X0/X1, X0A/X1A pins When used with a crystal oscillator
Pull-up resistance 1 Damping resistance 1
X1
X0
X0A
X1A
Internal damping resistance 0
Damping resistance 2
C1 C3 C4
C2
In normal use : Internal damping resistance 1 : Typ 600 Ω Consult with the oscillator manufacturer. Pull-up resistance 1, Damping resistance 1, 2, C1 to C4
• Sample use with external clock input
X0
MB90480/485 series
OPEN
X1
105
MB90480/485 Series
s EXAMPLE CHARACTERISTICS
VOH − IOH TA = + 25 °C
1800 VCC = 3.9 V VCC = 3.6 V VCC = 3.3 V 1600 1400 1200
VOL − IOL
TA = + 25 °C
VCC = 2.4 V
4.0 3.5 3.0 2.5
VOL (mV)
VOH (V)
VCC = 3.0 V VCC = 2.7 V
1000 800 600
2.0 1.5 1.0 0.5 0.0 −1 −2 −3 −4 −5
VCC = 2.4 V
400 200 0 1 2 3 4 5
VCC = 2.7 V VCC = 3.0 V VCC = 3.3 V VCC = 3.6 V VCC = 3.9 V
IOH (mA)
IOL (mA)
CMOS input characteristics TA = + 25 °C
2.4 2.2 2.0 VIH 2.4 2.2 2.0
Hysteresis input characteristics TA = + 25 °C
VIHS
Hysteresis input (V)
1.8
1.8 1.6 1.4 1.2 1.0 VILS 0.8 0.6 0.4
CMOS input (V)
1.6 1.4 VIL 1.2 1.0 0.8 0.6 0.4 2.4 2.7 3.0 3.3 3.6
2.4
2.7
3.0
3.3
3.6
VCC (V)
VCC (V)
(Continued)
106
MB90480/485 Series
ICC − VCC 60 f = 25 MHz 50 f = 20 MHz 40 f = 16 MHz
ICC (mA)
30 f = 10 MHz 20 f = 4 MHz f = 2 MHz f = 1 MHz 2.7 3.0 VCC (V) 3.3 3.6 3.9
10
0 2.4
ICCH − VCC 1.4 1.2 1.0 ICCH (µA) 0.8 0.6 0.4 0.2 0.0 2.4 2.7 3.0 VCC (V) 3.3 3.6 3.9
ICCT − VCC 2.0 1.8 1.6 1.4 ICCT (µA) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.4 2.7 3.0 VCC (V) 3.3 3.6 3.9
(Continued)
107
MB90480/485 Series
IA − VCC 2.0 1.8 1.6 1.4 IA (mA) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.4 2.7 3.0 VCC (V) 3.3 3.6 3.9
R − VCC 1000
R (kΩ)
100
10 2.4 2.7 3.0 VCC (V) 3.3 3.6 3.9
(Continued)
108
MB90480/485 Series
(Continued)
ICCS − VCC 20 18 16 14 f = 20 MHz f = 16 MHz 10 8 6 4 2 0 2.4 2.7 3.0 VCC (V) 3.3 3.6 f = 4 MHz f = 2 MHz f = 1 MHz 3.9 f = 10 MHz f = 25 MHz
ICCS (mA)
12
ICCL − VCC 20 18 16 14 ICCL (µA) 12 10 8 6 4 2 0 2.4 2.7 3.0 VCC (V) 3.3 3.6 3.9
IR − VCC 250
200
150 IR (µA) 100 50 0 2.4 2.7 3.0 VCC (V) 3.3 3.6 3.9
109
MB90480/485 Series
s ORDERING INFORMATION
Model MB90F481PF MB90F482PF MB90487PF MB90F488PF MB90F481PFV MB90F482PFV MB90487PFV MB90F488PFV Package 100-pin plastic QFP (FPT-100P-M06) Remarks
100-pin plastic LQFP (FPT-100P-M05)
110
MB90480/485 Series
s PACKAGE DIMENSIONS
100-pin plastic QFP (FPT-100P-M06) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80 51
81
50
0.10(.004) 17.90±0.40 (.705±.016)
*14.00±0.20 (.551±.008)
INDEX Details of "A" part
100 31
1
30
0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8˚ 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.25±0.20 (.010±.008) (Stand off)
0.65(.026)
0.32±0.05 (.013±.002)
0.13(.005)
M
"A"
C
2002 FUJITSU LIMITED F100008S-c-5-5
Dimensions in mm (inches) Note : The values in parentheses are reference values.
(Continued)
111
MB90480/485 Series
(Continued) 100-pin plastic LQFP (FPT-100P-M05)
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
75 51
76
50
0.08(.003) Details of "A" part
INDEX
1.50 –0.10 .059 –.004 (Mounting height)
26
+0.20
+.008
100
0.10±0.10 (.004±.004) (Stand off) 0.25(.010)
0˚~8˚ "A" 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006)
1
25
0.50(.020)
0.20±0.05 (.008±.002)
0.08(.003)
M
0.145±0.055 (.0057±.0022)
C
2003 FUJITSU LIMITED F100007S-c-4-6
Dimensions in mm (inches) Note : The values in parentheses are reference values.
112
MB90480/485 Series
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0407 © 2004 FUJITSU LIMITED Printed in Japan
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