MB90F583CA

FUJITSU MICROELECTRONICS DATA SHEET DS07-13710-7E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90580C Series MB90583C/583CA/F583C/F583CA/F584C/F584CA/ MB90587C/587CA/V580B ■ DESCRIPTION The MB90580C series is a line of general-purpose, Fujitsu Microelectronics 16-bit microcontrollers designed for process control applications which require high-speed real-time processing, such as consumer products. While inheriting the AT architecture of the F2MC*1 family, the instruction set for the F2MC-16LX CPU core of the MB90580C series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, the MB90580C has an on-chip 32-bit accumulator which enables processing of long-word data. The peripheral resources integrated in the MB90580C series include: an 8/10-bit A/D converter, an 8-bit D/A converter, UARTs (SCI) 0 to 4, an 8/16-bit PPG timer, 16-bit I/O timers (16-bit free-run timer, input capture units (ICUs) 0 to 3, output compare units (OCUs) 0 and 1), and an IEBusTM controller *2. *1: F2MC is the abbreviation of FUJITSU Flexible Microcontroller. *2: IEBusTM is a trademark of NEC Corporation. ■ FEATURES • Minimum execution time: 62.5 ns/4 MHz oscillation (Uses PLL clock multiplication) maximum multiplier = 4 • Maximum memory space 16 Mbyte Linear/bank access (Continued) For the information for microcontroller supports, see the following web site. This web site includes the "Customer Design Review Supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development. http://edevice.fujitsu.com/micom/en-support/ Copyright©2001-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2009.5 MB90580C Series • Instruction set optimized for controller applications Supported data types: bit, byte, word, and long-word types Standard addressing modes: 23 types 32-bit accumulator enhancing high-precision operations Signed multiplication/division and extended RETI instructions • Enhanced high level language (C) and multitasking support instructions Use of a system stack pointer Symmetrical instruction set and barrel shift instructions • Program patch function (for two address pointers) • Enhanced execution speed: 4 byte instruction queue • Enhanced interrupt function Up to eight priority levels programmable External interrupt inputs: 8 lines • Automatic data transmission function independent of CPU operation Up to 16 channels for the extended intelligent I/O service DTP request inputs: 8 lines • Internal ROM FLASH: 128 Kbyte (MB90F583C/CA), 256Kbyte (MB90F584C/CA) MASKROM: 128 Kbyte (MB90583C/CA) , 64 Kbyte (MB90587C/CA) • Internal RAM FLASH: 6 Kbyte (MB90F583C/CA, MB90F584C/CA) MASKROM: 6 Kbyte (MB90583C/CA) , 4 Kbyte (MB90587C/CA) • General-purpose ports Up to 77 channels (Input pull-up resistor settable for: 22 channels. Output open drain settable for: 8 channels) • IEBusTM controller* Three different data transfer rates selectable Mode 0: 3.9 Kbps (16 bytes/frame) Mode 1: 17.0 Kbps (32 bytes/frame) Mode 2: 26.0 Kbps (128 bytes/frame) *: IEBusTM is a trademark of NEC Corporation. • A/D Converter (RC) : 8 ch 8/10-bit resolution Conversion time: 34.7 μs (Min) , 12 MHz operation • D/A Converter: 2 ch 8-bit resolutions Setup time: 12.5 μs • UART : 5 ch • 8/16 bit PPG : 1 ch 8 bits × 2 channels: 16 bits × 1 channel: Mode switching function provided • 16 bit reload timer: 3 ch • 16-bit PWC timer: 1 channel Noise filter provided. Available to pulse width counter • 16 bit I/O timer Input capture : 4 ch Output compare : 2 ch Free run timer: 1 ch • Internal clock generator • Time-base counter/watchdog timer: 18-bit (Continued) 2 DS07-13710-7E MB90580C Series (Continued) • Clock monitor function integrated • Low-power consumption mode Sleep mode Stop mode Hardware standby mode CPU intermittent operation mode • Package: LQFP-100 / QFP-100 • CMOS technology DS07-13710-7E 3 MB90580C Series ■ PRODUCT LINEUP Part number Item Classification ROM size RAM size Clock*1 Emulator-specific power supply *2 MB90587C/CA MB90583C/CA MB90F583C/CA MB90F584C/CA MB90V580B Development/ evaluation product None 6 Kbytes Two clocks system None Mass-produced products (MASK ROM) 64 Kbytes 4 Kbytes 128 Kbytes 6 Kbytes Mass-produced products (Flash ROM) 128 Kbytes 6 Kbytes 256 Kbytes 6 Kbytes Two clocks / Two clocks / Two clocks / Two clocks / one clock system one clock system one clock system one clock system ⎯ ⎯ ⎯ ⎯ CPU functions The number of instructions: 340 Instruction bit length: 8 bits, 16 bits Instruction length: 1 byte to 7 bytes Data bit length: 1 bit, 8 bits, 16 bits Minimum execution time: 62.5 ns (at machine clock of 16 MHz) Interrupt processing time: 1.5 μs (at machine clock of 16 MHz, minimum value) General-purpose I/O ports (CMOS output) General-purpose I/O port (Can be set as open-drain) General-purpose I/O ports (Input pull-up resistors available) Total: : 45 :8 : 22 : 77 Ports IEBusTM controller None Communication mode: Half-duplex, asynchronous communication Multi-master system Access control: CDMA/CD Three modes selectable for different transmission speeds Transmit buffer: 8-byte FIFO buffer Receive buffer: 8-byte FIFO buffer Timebase timer Watchdog timer Watch timer 18-bit counter Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms (At oscillation of 4 MHz) Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 MHz, minimum value) 15-bit counter Interrupt interval: 1 s, 0.5 s, 0.25 s, 31.25 ms (At oscillation of 32.768 kHz) Number of channels: 1 (8-bit × 2 channels) PPG operation of 8-bit or 16-bit A pulse wave of given intervals and given duty ratios can be output. Pulse interval: 62.5 ns to 1 ms (at oscillation of 4 MHz, machine clock of 16 MHz) Number of channels: 3 Event count provided Interval: 125 ns to 131 ms (at oscillation of 4 MHz, machine clock of 16 MHz) Number of channels: 1 Timer function (select the counter timer from three internal clocks.) Pulse width measuring function (select the counter timer from three internal clocks.) (Continued) 8/16-bit PPG timer 16-bit reload timer PWC timer 4 DS07-13710-7E MB90580C Series (Continued) Part number Item 16-bit free run timer Output 16-bit compare I/O timer (OCU) Input capture (ICU) DTP/external interrupt circuit Delayed interrupt generation module UART0, 1, 2, 3, 4 MB90587C/CA MB90583C/CA MB90F583C/CA MB90F584C/CA MB90V580B Number of channels: 1 Overflow interrupts Number of channels: 2 Pin input factor: A match signal of compare register Number of channels: 4 Rewriting a register value upon a pin input (rising, falling, or both edges) Number of inputs: 8 Started by a rising edge, a falling edge, an “H” level input, or an “L” level input. External interrupt circuit or extended intelligent I/O service (EI2OS) can be used. An interrupt generation module for switching tasks used in real time operating systems. Clock synchronized transmission (62.5 Kbps to 1 Mbps) Clock asynchronized transmission (1202 bps to 9615 bps) Transmission can be performed by bi-directional serial transmission or by master/slave connection. Resolution: 8/10-bit changeable Number of inputs: 8 One-shot conversion mode (converts selected channel only once) Scan conversion mode (converts two or more successive channels and can program up to 8 channels.) Continuous conversion mode (converts selected channel repeatedly) Stop conversion mode (converts selected channel and stop operation repeatedly) 8-bit resolution Number of channels: 2 channels Based on the R-2R system Sleep/stop/CPU intermittent operation/watch/hardware standby CMOS 4.5 V to 5.5 V*3 A/D converter D/A converter Low-power consumption (standby) mode Process Power supply voltage for operation *1: Connect the oscillator to both terminals XA0 and XA1 for MB90F587C / 583C / F583C / F584C. *2: It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used. Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details. *3: Varies with conditions such as the operating frequency (See section “■ ELECTRICAL CHARACTERISTICS”). Assurance for the MB90V580B is given only for operation with a tool at a power supply voltage of 4.5 V to 5.5 V, an operating temperature of 0 to +25 °C, and an operating frequency of 1 MHz to 16 MHz. ■ PACKAGE AND CORRESPONDING PRODUCTS Package FPT-100P-M20 FPT-100P-M06 : Available ×: Not available Note: : For more information about each package, see section “■ PACKAGE DIMENSIONS”. DS07-13710-7E 5 MB90583C/CA MB90587C/CA MB90F584C/CA MB90F583C/CA MB90580C Series ■ DIFFERENCES AMONG PRODUCTS Memory Size In evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. The following items must be taken into consideration. • The MB90V580B does not have an internal ROM, however, operations equivalent to chips with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the development tool. • In the MB90V580B, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to mapped to bank FE and FF only. (This setting can be changed by configuring the development tool.) • In the MB90583C/583CA/587C/587CA/F583C/F583CA/F584C/F584CA, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH to bank FF only. IEBusTM Controller • MB90587C/CA does not have an IEBusTM Controller. 6 DS07-13710-7E MB90580C Series ■ PIN ASSIGNMENT (TOP VIEW) 100 P21/A17 99 P20/A16 98 P17/AD15 97 P16/AD14 96 P15/AD13 95 P14/AD12 94 P13/AD11 93 P12/AD10 92 P11/AD09 91 P10/AD08 90 P07/AD07 89 P06/AD06 88 P05/AD05 87 P04/AD04 86 P03/AD03 85 P02/AD02 84 P01/AD01 83 P00/AD00 82 VCC 81 X1 80 X0 79 VSS 78 X0A 77 X1A 76 PA2 P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SIN0 P41/SOT0 P42/SCK0 P43/SIN1 P44/SOT1 VCC P45/SCK1 P46/ADTG P47 C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 RST PA1 PA0 P97/POT P96/PWC P95/TOT2/OUT1 P94/TOT1/OUT0 P93/TOT0/IN3 P92/TIN2/IN2 P91/TIN1/IN1 P90/TIN0/IN0 RX* TX* P65/CKOT P64/PPG0 P63/PPG1 P62/SCK2 P61/SOT2 P60/SIN2 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3 P82/IRQ2 DS07-13710-7E P71 P72 DVRH DVSS P73/DA00 P74/DA01 AVCC AVRH AVRL AVSS P50/AN0/SIN3 P51/AN1/SOT3 P52/AN2/SCK3 P53/AN3 VSS P54/AN4/SIN4 P55/AN5/SOT4 P56/AN6/SCK4 P57/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1 MD2 HST 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 * : N.C. pin on the MB90587C/CA (FPT-100P-M20) 7 MB90580C Series (TOP VIEW) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P17/AD15 P16/AD14 P15/AD13 P14/AD12 P13/AD11 P12/AD10 P11/AD09 P10/AD08 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VCC X1 X0 VSS P20/A16 P21/A17 P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SIN0 P41/SOT0 P42/SCK0 P43/SIN1 P44/SOT1 VCC P45/SCK1 P46/ADTG P47 C P71 P72 DVRH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 X0A X1A PA2 RST PA1 PA0 P97/POT P96/PWC P95/TOT2/OUT1 P94/TOT1/OUT0 P93/TOT0/IN3 P92/TIN2/IN2 P91/TIN1/IN1 P90/TIN0/IN0 RX* TX* P65/CKOT P64/PPG0 P63/PPG1 P62/SCK2 P61/SOT2 P60/SIN2 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3 P82/IRQ2 HST MD2 8 DVSS P73/DA00 P74/DA01 AVCC AVRH AVRL AVSS P50/AN0/SIN3 P51/AN1/SOT3 P52/AN2/SCK3 P53/AN3 VSS P54/AN4/SIN4 P55/AN5/SOT4 P56/AN6/SCK4 P57/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 * : N.C. pin on the MB90587C/CA (FPT-100P-M06) DS07-13710-7E MB90580C Series ■ PIN DESCRIPTION Pin no. QFP*1 82 83 52 77 LQFP*2 80 81 50 75 Pin name X0 X1 HST RST P00 to P07 AD00 to AD07 P10 to P17 AD08 to AD15 P20 to P27 A16 to A23 P30 9 7 ALE P31 RD P32 12 10 WRL P33 13 11 WRH *1: FPT-100P-M06 *2: FPT-100P-M20 (Continued) DS07-13710-7E 9 Circuit type A A C B Oscillator pin Oscillator pin Hardware standby input pin Reset input pin Function 85 to 92 83 to 90 General-purpose I/O ports. A pull-up resistor can be assigned (RD07 to RD00=“1”) by the pullup resistor setting register (RDR0). [These pins are disabled with D (CMOS/H) the output setting (DDR0 register: D07 to D00=“1”).] In external bus mode, the pins function as the lower data I/O or lower address outputs (AD00 to AD07). General-purpose I/O ports. A pull-up resistor can be assigned (RD17 to RD10=“1”) by the pullup resistor setting register (RDR1). [These pins are disabled with D (CMOS/H) the output setting (DDR1 register: D17 to D10 =“1”).] In 16-bit external bus mode, the pins function as the upper data I/O or middle address outputs (AD08 to AD15). General-purpose I/O ports In external bus mode, pins for which the corresponding bit in the HACR register is “1” function as the A16 to A23 pins. 93 to 100 91 to 98 1 to 8 99,100, 1 to 6 F (CMOS/H) In external bus mode, pins for which the corresponding bit in the HACR register is “1” function as the upper address output pins (A16 to A23). General-purpose I/O port Functions as the ALE pin in external bus mode. F (CMOS/H) Functions as the address latch enable signal pin (ALE) in external bus mode. General-purpose I/O port F Functions as the RD pin in external bus mode. (CMOS/H) Functions as the read strobe output pin (RD) in external bus mode. General-purpose I/O port Functions as the WRL pin in external bus mode if the WRE bit is “1”. Functions as the lower data write strobe output pin (WRL) in external bus mode. General-purpose I/O port Functions as the WRH pin in 16-bit external bus mode if the WRE bit in the EPCR register is “1” Functions as the upper data write strobe output pin (WRH) in external bus mode. 10 8 F (CMOS/H) F (CMOS/H) MB90580C Series Pin no. QFP*1 LQFP*2 Pin name Circuit type Function 14 12 P34 HRQ P35 General-purpose I/O port Functions as the HRQ pin in external bus mode if the HDE bit in the F (CMOS/H) EPCR register is “1”. Functions as the hold request input pin (HRQ) in external bus mode. General-purpose I/O port Functions as the HAK pin in external bus mode if the HDE bit in the EPCR register is “1”. Functions as the hold acknowledge output pin (HAK) in external bus mode. 15 13 HAK F (CMOS/H) 16 14 P36 RDY P37 General-purpose I/O port Functions as the RDY pin in external bus mode if the RYE bit in the F (CMOS/H) EPCR register is “1”. Functions as the external ready input pin (RDY) in external bus mode. General-purpose I/O port Functions as the CLK pin in external bus mode if the CKE bit in the EPCR register is “1”. Functions as the machine cycle clock output pin (CLK) in external bus mode. General-purpose I/O port. This pin serves as an open-drain output port with OD40 in the opendrain control setting register (ODR4) set to “1”. [The pin is disabled with the input setting (DDR4 register: D40=“0”).] 17 15 CLK F (CMOS/H) P40 18 16 SIN0 E (CMOS/H) UART0 serial data input (SIN0) pin. When UART0 is operating for input, this input is used as required and thus the output from any other function to the pin must be off unless used intentionally. P41 19 17 SOT0 General-purpose I/O port. This pin serves as an open-drain output port with OD41 in the opendrain control setting register (ODR4) set to “1”. [The pin is disabled E (CMOS/H) with the input setting (DDR4 register: D41=“0”).] UART0 serial data output pin (SOT0). This pin is enabled with the UART0 serial data output enabled. General-purpose I/O port. This pin serves as an open-drain output port with OD42 in the opendrain control setting register (ODR4) set to “1”. [The pin is disabled E (CMOS/H) with the input setting (DDR4 register: D42=“0”).] UART0 serial clock I/O pin (SCK0). This pin is enabled with the UART0 clock output enabled. P42 20 18 SCK0 *1: FPT-100P-M06 *2: FPT-100P-M20 (Continued) 10 DS07-13710-7E MB90580C Series Pin no. QFP*1 LQFP*2 Pin name Circuit type Function General-purpose I/O port. This pin serves as an open-drain output port with OD43 in the opendrain control setting register (ODR4) set to “1”. [The pin is disabled with the input setting (DDR4 register: D43=“0”).] P43 21 19 SIN1 E (CMOS/H) UART1 serial data input (SIN1) pin. When UART1 is operating for input, this input is used as required and thus the output from any other function to the pin must be off unless used intentionally. P44 22 20 SOT1 General-purpose I/O port. This pin serves as an open-drain output port with OD44 in the opendrain control setting register (ODR4) set to “1”. [The pin is disabled E (CMOS/H) with the input setting (DDR4 register: D44=“0”).] UART1 serial data output pin (SOT1). This pin is enabled with the UART1 serial data output enabled. General-purpose I/O port. This pin serves as an open-drain output port with OD45 in the opendrain control setting register (ODR4) set to “1”. [The pin is disabled E (CMOS/H) with the input setting (DDR4 register: D45=“0”).] UART1 serial clock I/O pin (SCK1). This pin is enabled with the UART1 clock output enabled. General-purpose I/O port. This pin serves as an open-drain output port with OD46 in the openE drain control setting register (ODR4) set to “1”. [The pin is disabled (CMOS/H) with the input setting (DDR4 register: D46=“0”).] External trigger input pin (ADTG) for the A/D converter. General-purpose I/O port. E This pin serves as an open-drain output port with OD47 in the open(CMOS/H) drain control setting register (ODR4) set to “1”. [The pin is disabled with the input setting (DDR4 register: D47=“0”).] General-purpose I/O port. Analog input pin (AN0) for use during A/D converter operation. G UART3 serial data input pin (SIN3). (CMOS/H) When UART3 is operating for input, this input is used as required and thus the output from any other function to the pin must be off unless used intentionally. General-purpose I/O port. G Analog input pin (AN1) for use during A/D converter operation. (CMOS/H) UART3 serial data output pin (SOT3). This pin is enabled with the UART3 serial data output enabled. P45 24 22 SCK1 25 23 P46 ADTG 26 24 P47 P50 AN0 38 36 SIN3 P51 39 37 AN1 SOT3 *1: FPT-100P-M06 *2: FPT-100P-M20 (Continued) DS07-13710-7E 11 MB90580C Series Pin no. QFP*1 LQFP*2 Pin name Circuit type P52 General-purpose I/O port. G (CMOS/H) Function 40 38 AN2 SCK3 Analog input pin (AN2) for use during A/D converter operation. UART3 serial clock I/O pin (SCK3). This pin is enabled with the UART3 clock output enabled. General-purpose I/O port. Analog input pin (AN3) for use during A/D converter operation. General-purpose I/O port. Analog input pin (AN4) for use during A/D converter operation. 41 39 P53 AN3 P54 AN4 G (CMOS/H) 43 41 SIN4 G (CMOS/H) UART4 serial data input pin (SIN4). When UART4 is operating for input, this input is used as required and thus the output from any other function to the pin must be off unless used intentionally. General-purpose I/O port. Analog input pin (AN5) for use during A/D converter operation. UART4 serial data output pin (SOT4). This pin is enabled with the UART4 serial data output enabled. General-purpose I/O port. Analog input pin (AN6) for use during A/D converter operation. UART4 serial clock output pin (SCK4). This pin is enabled with the UART4 clock output enabled. General-purpose I/O port. Analog input pin (AN7) for use during A/D converter operation. 0.1 μF capacitor coupling pin for regulating the power supply. General-purpose I/O port. General-purpose I/O port. This pin serves as a D/A output pin (DA00) when the DAE0 bit in the D/A control register (DACR) is “1”. D/A converter output 0 (DA00) pin. General-purpose I/O port. This pin serves as a D/A output pin (DA01) when the DAE1 bit in the D/A control register (DACR) is “1”. D/A converter output 1 pin (DA01). General-purpose I/O port. Functions as external interrupt request input 0 pin (IRQ0). P55 44 42 AN5 SOT4 P56 45 43 AN6 SCK4 46 27 28 29 44 25 26 27 P57 AN7 C P71 P72 P73 DA00 P74 DA01 47 45 P80 IRQ0 F (CMOS/H) H (CMOS/H) G (CMOS/H) ⎯ F (CMOS/H) G (CMOS/H) G (CMOS/H) F (CMOS/H) General-purpose I/O port. H (CMOS/H) 32 30 33 31 *1: FPT-100P-M06 *2: FPT-100P-M20 (Continued) 12 DS07-13710-7E MB90580C Series Pin no. QFP*1 48 53 54 55 56 57 58 LQFP*2 46 51 52 53 54 55 56 Pin name Circuit type P81 IRQ1 P82 IRQ2 P83 IRQ3 P84 IRQ4 P85 IRQ5 P86 IRQ6 P87 IRQ7 Function General-purpose I/O port. F (CMOS/H) Functions as external interrupt request input 1 pin (IRQ1). General-purpose I/O port. F (CMOS/H) Functions as external interrupt request input 2 pin (IRQ2). General-purpose I/O port. F (CMOS/H) Functions as external interrupt request input 3 pin (IRQ3). General-purpose I/O port. F (CMOS/H) Functions as external interrupt request input 4 pin (IRQ4). General-purpose I/O port. F (CMOS/H) Functions as external interrupt request input 5 pin (IRQ5). General-purpose I/O port. F (CMOS/H) Functions as external interrupt request input 6 pin (IRQ6). General-purpose I/O port. F (CMOS/H) Functions as external interrupt request input 7 pin (IRQ7). General-purpose I/O port. A pull-up resistor can be assigned (RD60=“1”) by the pull-up resistor setting register (RDR6). [This pin is disabled with the output setting (DDR6 register: D60=“1”).] P60 59 57 SIN2 D (CMOS/H) UART2 serial data input pin (SIN2). When UART2 is operating for input, this input is used as required and thus the output from any other function to the pin must be off unless used intentionally. P61 60 58 SOT2 General-purpose I/O port. A pull-up resistor can be assigned (RD61=“1”) by the pull-up resistor setting register (RDR6). [This pin is disabled with the output setting D (CMOS/H) (DDR6 register: D61=“1”).] UART2 serial data output pin (SOT2). This pin is enabled with the UART2 serial data output enabled. General-purpose I/O port. A pull-up resistor can be assigned (RD62=“1”) by the pull-up resistor setting register (RDR6). [This pin is disabled with the output setting D (CMOS/H) (DDR6 register: D62=“1”).] UART2 serial clock I/O pin (SCK2). This pin is enabled with the UART2 clock output enabled. P62 61 59 SCK2 *1: FPT-100P-M06 *2: FPT-100P-M20 (Continued) DS07-13710-7E 13 MB90580C Series Pin no. QFP*1 LQFP*2 Pin name Circuit type Function General-purpose I/O port. A pull-up resistor can be assigned (RD63=“1”) by the pull-up resistor setting register (RDR6). [This pin is disabled with the output setting (DDR6 register: D63=“1”).] The pin serves as the PPG1 output when PPGs are enabled. General-purpose I/O port. A pull-up resistor can be assigned (RD64=“1”) by the pull-up resistor setting register (RDR6). [This pin is disabled with the output setting (DDR6 register: D64=“1”).] The pin serves as the PPG0 output when PPGs are enabled. General-purpose I/O port. A pull-up resistor can be assigned (RD65=“1”) by the pull-up resistor setting register (RDR6). [This pin is disabled with the output setting (DDR6 register: D65=“1”).] This pin serves as the CKOT output during CKOT operation. This pin serves as the IEBusTM output. This pin serves as the IEBusTM input. General-purpose I/O port. 62 60 P63 D (CMOS/H) PPG1 63 61 P64 D (CMOS/H) PPG0 64 62 P65 D (CMOS/H) CKOT 65 66 63 64 TX* 3 I J (CMOS) RX*3 P90 to P92 67 to 69 65 to 67 TIN0 to TIN2 IN0 to IN2 P93 F (CMOS/H) Event input pins for reload timers 0, 1, and 2. During reload timer input, these inputs are used continuously and thus the output from any other function to the pins must be avoided unless used intentionally. Trigger inputs for input capture channels 0 to 2 General-purpose I/O port. 70 68 TOT0 IN3 P94, P95 TOT1, TOT2 OUT0, OUT1 F (CMOS/H) Reload timer output pin. This function is applied when the output for reload timer 0 is enabled. Trigger inputs for input capture channel 3. General-purpose I/O port. Reload timer output pins. This function is applied when the output for reload timer 1 and 2 are enabled. Event output for channel 0 and 1 of the output compare General-purpose I/O port. This pin serves as the PWC input with the PWC timer enabled. 71, 72 69, 70 F (CMOS/H) 73 71 P96 PWC F (CMOS/H) *1: FPT-100P-M06 *2: FPT-100P-M20 *3: N.C. pin on the MB90587C/CA. (Continued) 14 DS07-13710-7E MB90580C Series (Continued) Pin no. QFP*1 74 75, 76 78 79 80 34 37 35 36 30 31 LQFP*2 72 73, 74 76 77 78 32 35 33 34 28 29 Pin name Circuit type P97 POT PA2 X1A X0A AVCC AVSS AVRH AVRL DVRH DVSS MD0 to MD2 VCC VSS F (CMOS/H) General-purpose I/O port. Function This pin serves as the PWC output with the PWC timer enabled. PA0, PA1 F (CMOS/H) General-purpose I/O port. F (CMOS/H) General-purpose I/O port. A A ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ C ⎯ ⎯ Oscillation pin. Leave the terminal open for the one clock system parts. Oscillation pin. Pull-down the terminal externally for the one clock system parts. A/D converter power supply pin. A/D converter power supply pin. A/D converter external reference power supply pin. A/D converter external reference power supply pin. D/A converter external reference power supply pin. D/A converter power supply pin. Input pin for specifying the operation mode. Connect these pins directly to Vcc or Vss. Power supply (5 V) input pin. Power supply (0 V) input pin. 49 to 51 47 to 49 23, 84 11, 42, 81 21, 82 9, 40, 79 *1: FPT-100P-M06 *2: FPT-100P-M20 DS07-13710-7E 15 MB90580C Series ■ I/O CIRCUIT TYPE Type A X1, X1A Circuit Remarks • High-speed oscillation feedback resistance : Approx. 1 MΩ • Low-speed oscillation feedback resistance : Approx. 10 MΩ Clock input X0, X0A HARD,SOFT STANDBY CONTROL B • Hysteresis input with pull-up resistance : Approx. 50 kΩ C • Hysteresis input D Pull-up resistor control • Incorporates pull-up resistor control (for input) • CMOS level output • Hysteresis input with standby control resistance : Approx. 50 kΩ Standby control signal (Continued) 16 DS07-13710-7E MB90580C Series Type E Circuit Remarks • CMOS level output • Hysteresis input with standby control • Incorporates open-drain control • Open-drain control signal Standby control signal F • CMOS level output • Hysteresis input with standby control Standby control signal G • CMOS level output • Hysteresis input with standby control • Analog input Analog input Standby control signal (Continued) DS07-13710-7E 17 MB90580C Series (Continued) Type H Circuit Remarks • CMOS level output • Hysteresis input with standby control • DA output DA output Standby control signal I • CMOS level output J • CMOS input with standby control Standby control signal 18 DS07-13710-7E MB90580C Series ■ HANDLING DEVICES 1. Preventing Latch-up CMOS ICs may cause Latch-up in the following situations: • When a voltage higher than Vcc or lower than Vss is applied to input or output pins. • When a voltage exceeding the rating is applied between Vcc and Vss. • When AVcc power is supplied prior to the Vcc voltage. If Latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Use meticulous care not to let it occur. For the same reason, also be careful not to let the analog power-supply voltage exceed the digital power-supply voltage. 2. Handling unused input pins Unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage. Unused input pins should be pulled up or pulled down through at least 2 kΩ resistance. Unused input/output pins may be left open in output state, but if such pins are in input state they should be handled in the same way as input pins. 3. Treatment of the TX and RX pins with the IEBusTM unused When the IEBus is not used, connect a pull-down resistor to the TX pin and a pull-down/pull-up resistor to the RX pin. 4. Use of the external clock When the device uses an external clock, drive only the X0 pin while leaving the X1 pin open (See the illustration below). MB90580C series X0 Open X1 5. Power Supply Pins (VCC/VSS) In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VCC and VSS pins via lowest impedance to power lines. DS07-13710-7E 19 MB90580C Series It is recommended to provide a bypass capacitor of around 0.1 μF between VCC and VSS pin near the device. VCC VSS VCC VSS VCC VSS MB90580C Series VCC VCC VSS VSS 6. Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand area for stabilizing the operation. 7. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply (AVCC, AVSS, AVRH, AVRL) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage of AVRH dose not exceed AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable). 8. Connection of Unused Pins of A/D Converter Connect unused pin of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS. 9. Connection of Unused Pins of D/A Converter Connect unused pin of D/A converter to DVRH = VSS, DVSS = VSS. 10. N.C. Pin The N.C. (internally connected) pin must be opened for use. 11. Notes on Energization To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 μs or more (0.2 V to 2.7 V). 12. Use of the sub-clock Use the one clock system parts when the sub-clock is not used. Connected the oscillator under 32 kHz to the both terminals XA0 and X1A for the two clocks system parts. Pull-down the terminal X0A and leave the terminal X0A open for the one clock system parts. 20 DS07-13710-7E MB90580C Series 13. Indeterminate outputs from ports 0 and 1 The outputs from ports 0 and 1 become indeterminate during a power-on reset after the power is turned on. Pay attention to the port output timing shown as follow. Oscillation settling time*2 Power-on reset*1 VCC (Power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operation clock A) signal KB (internal operation clock B) signal PORT (port output) signal Period of indeterminate *1: Power-on reset time: Period of “clock frequency x 217” (Clock frequency of 16 MHz: 8.192 ms) *2: Oscillation settling time: Period of “clock frequency x 218” (Clock frequency of 16 MHz: 16.384 ms) 14. Initialization In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers turning on the power again. 15. Return from standby state If the power-supply voltage goes below the standby RAM holding voltage in the standby state, the device may fail to return from the standby state. In this case, reset the device via the external reset pin to return to the normal state. 16. Precautions for Use of ’DIV A, Ri,’ and ’DIVW A, RWi’ Instructions The signed multiplication-division instructions ’DIV A, Ri,’ and ’DIVW A, RWi’ should be used when the corresponding bank registers (DTB, ADB, USB, SSB) are set to value ’00h.’ If the corresponding bank registers (DTB, ADB, USB, SSB) are set to a value other than ’00h,’ then the remainder obtained after the execution of the instruction will not be placed in the instruction operand register. 17. Precautions for Use of REALOS Extended intelligent I/O service (EI2OS) cannot be used, when REALOS is used. DS07-13710-7E 21 MB90580C Series 18. Caution on PLL Clock Mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. 22 DS07-13710-7E MB90580C Series ■ BLOCK DIAGRAM X0, X1 X0A, X1A RST HST 6 Clock control circuit RAM ROM CPU Core of F2MC-16LX family Interrupt controller CMOS I/O port A I/O timer 16 bit ICU × 4 ch 16 bit OCU × 2 ch 16 bit free run timer 16 bit reload timer × 3 ch F2MC-16LX bus 3 3 PA0 to PA2 P90 to P92/ TIN0 to TIN2/ IN0 to IN2 P93/ TOT0/ IN3 2 P94, P95/ TOT1, TOT2/ OUT0, OUT1 P96/PWC P97/POT P00 to P07/ AD00 to AD07 P10 to P17/ AD08 to AD15 P20 to P27/ A16 to A23 P30/ALE P31/RD P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P47 8 8 8 CMOS I/O port 0 CMOS I/O port 1 CMOS I/O port 2 CMOS I/O port 3 Noise filter PWC timer 16 bit × 1 ch CMOS I/O port 9 Prescaler × 1 ch Prescaler × 2 ch CMOS I/O port 4 SIN0, SOT0, SCK0/ P40 to P42 SIN1, SOT1, SCK1/ P43 to P45 3 3 UART × 2 ch UART × 1 ch 8 / 16 PPG × 1 ch 2 2 P63, P64/ PPG1, PPG0 P65/CKOT 3 SIN2, SOT2, SCK2/ P60 to P62 P80 to P87/ IRQ0 to IRQ7 P71, P72 Clock monitor 8 ADTG / P46 AVCC AVRH, AVRL AVSS SIN3, SOT3, SCK3/ P50 to P52/ AN0 to AN2 3 A/D converter (8/10 bit) 8 CMOS I/O port 6 External interrupt CMOS I/O port 8 8 2 Prescaler × 2 ch CMOS I/O port 7 D/A converter (8 bit) × 2 ch 2 P73, P74 /DA00, DA01 DVRH DVSS P53/AN3, P57/AN7 SIN4, SOT4, SCK4/ P54 to P56/ AN4 to AN6 TX RX 2 3 UART × 2 ch CMOS I/O port 5 * IEBusTM controller Evaluation device (MB90V580B) This chip has no internal ROM. Internal RAM is 6 Kbytes. Internal resources are common. The package is PGA-256C-A02. Other pins MD2 to MD0 C,VCC,VSS P00 to 07 (8 channels): Provided with a register available as an input pull-up resistor. P10 to 17(8 channels): Provided with a register available as an input pull-up resistor. P60 to 65(6 channels): Provided with a register available as an input pull-up resistor. P40 to 47 (8 channels): Provided with a register available as an open drain. *: The MB90587C/CA has no IEBusTM controller. The TX and RX pins are N.C. pins. 23 DS07-13710-7E MB90580C Series ■ MEMORY MAP FFFFFFH ROM area Address#1 FC0000H ROM area 010000 H Address#2 ROM area (image of bank FF) ROM area (image of bank FF) 004000 H 002000 H : Internal : External RAM Register Address#3 RAM Register RAM Register : Inhibited area 000100 H 0000C0H 000000 H Peripheral Single chip mode A mirror function is supported Peripheral Internal ROM external bus mode A mirror function is supported Peripheral External ROM external bus mode Parts No. MB90583C/CA MB90F583C/CA MB90F584C/CA MB90587C/CA MB90V580B Address#1 FE0000H FE0000H FC0000H FF0000H (FE0000H) Address#2 004000H 004000H 004000H 004000H 004000H Address#3 001900H 001900H 001900H 001100H 001900H Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit is assigned to the same address, enabling reference of the table on the ROM without stating “far”. For example, if an attempt has been made to access 00C000H, the contents of the ROM at FFC000H are accessed actually. Since the ROM area of the FF bank exceeds 48 Kbytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image for 00400H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H to FFFFFFH. 24 DS07-13710-7E MB90580C Series ■ F2MC-16LX CPU PROGRAMMING MODEL • Dedicated registers AH AL USP : Accumulator (A) Dual 16-bit register used for storing results of calculation etc. The two 16-bit registers can be combined to be used as a 32-bit register. : User stack pointer (USP) The 16-bit pointer indicating a user stack address. : System stack pointer (SSP) The 16-bit pointer indicating the status of the system stack address. : Processor status (PS) The 16-bit register indicating the system status. : Program counter (PC) The 16-bit register indicating storing location of the current instruction code. : Direct page register (DPR) The 8-bit register indicating bit 8 through 15 of the operand address in the short direct addressing mode. : Program bank register (PCB) The 8-bit register indicating the program space. : Data bank register (DTB) The 8-bit register indicating the data space. : User stack bank register (USB) The 8-bit register indicating the user stack space. : System stack bank register (SSB) The 8-bit register indicating the system stack space. : Additional data bank register (ADB) The 8-bit register indicating the additional data space. SSP PS PC DPR PCB DTB USB SSB ADB 8 bit 16 bit 32 bit DS07-13710-7E 25 MB90580C Series • General-purpose registers Maximum of 32 banks R7 R5 R3 R1 RW3 R6 R4 R2 R0 RW7 RL3 RW6 RW5 RL2 RW4 RL1 RW2 RW1 RL0 000180H + (RP × 10H) RW0 16 bit • Processor status (PS) ILM RP CCR bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PS ILM2 ILM1 ILM0 0 0 0 B4 0 B3 0 B2 0 B1 0 B0 0 ⎯ ⎯ I 0 S 1 T X N X Z X V X C X Initial value ⎯ : Unused X : Undefined 26 DS07-13710-7E MB90580C Series ■ I/O MAP Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH to 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH to 1FH 20H 21H 22H 23H Serial mode register 0 Serial control register 0 Serial input data register 0/ serial output data register 0 Serial status register 0 SMR0 SCR0 SIDR0/ SODR0 SSR0 Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Port A direction register Port 4 output pin register Port 5 analog input enable register DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 DDRA ODR4 ADER Register name Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register Abbreviated register Read/write name PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (Disabled) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (Disabled) R/W R/W R/W R/W UART0 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B XXXXXXXXB 0 0 0 0 1 − 0 0B (Continued) Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port 4 Port 4, A/D 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B − − 0 0 0 0 0 0 0B − − −0000− B Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 1 1 1 1 1 1 1 1B − − XXXXXXB − − − XXXX −B XXXXXXXXB XXXXXXXXB − − − − − XXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B − − − − − 0 0 0B 0 0 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B DS07-13710-7E 27 MB90580C Series Address 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Register name Serial mode register 1 Serial control register 1 Serial input data register 1/ serial output data register 1 Serial status register 1 Serial mode register 2 Serial control register 2 Serial input data register 2/ serial output data register 2 Serial status register 2 Clock division control register 0 Abbreviated register name SMR1 SCR1 SIDR1/ SODR1 SSR1 SMR2 SCR2 SIDR2/ SODR2 SSR2 CDCR0 Read/ write R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Initial value 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B UART1 XXXXXXXXB 0 0 0 0 1 − 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B UART2 XXXXXXXXB 0 0 0 0 1 − 0 0B Communications prescaler 0 Communications prescaler 1 0 − − − 1 1 1 1B (Disabled) Clock division control register 1 CDCR1 R/W 0 − − − 1 1 1 1B (Disabled) DTP/interrupt enable register DTP/interrupt factor register Request level setting register lower Request level setting register upper Clock division control register 2 ENIR EIRR R/W R/W DTP/external interrupt ELVR R/W 0 0 0 0 0 0 0 0B CDCR2 R/W Communications prescaler 2 0 − − − 1 1 1 1B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B (Disabled) Control status register lower Control status register upper Data register lower Data register upper D/A converter data register 0 D/A converter data register 1 D/A control register 0 D/A control register 1 Clock output enable register ADCS1 ADCS2 ADCR1 ADCR2 DAT0 DAT1 DACR0 DACR1 CLKR R/W R/W R R or W R/W R/W R/W R/W R/W (Disabled) (Continued) Clock monitor function D/A converter A/D converter 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 1 − XXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B − − − − − − − 0B − − − − − − − 0B − − − − 0 0 0 0B 28 DS07-13710-7E MB90580C Series Address 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H Register name Reload register L (ch.0) Reload register H (ch.0) Reload register L (ch.1) Reload register H (ch.1) PPG0 operating mode control register PPG1 operating mode control register PPG0 and 1 operating output control registers Timer control status register lower Timer control status register upper 16 bit timer register lower/ 16 bit reload register lower 16 bit timer register upper/ 16 bit reload register upper Timer control status register lower Timer control status register upper 16bit timer register lower/ 16 bit reload register lower 16 bit timer register upper/ 16 bit reload register upper Timer control status register lower Timer control status register upper 16 bit timer register lower/ 16 bit reload register lower 16 bit timer register upper/ 16 bit reload register upper PWC control status register lower PWC control status register upper PWC data buffer register lower PWC data buffer register upper Divide ratio control register Abbreviated Read/ register write name PRLL0 PRLH0 PRLL1 PRLH1 PPGC0 PPGC1 PPGOE R/W R/W R/W R/W R/W R/W R/W Resource name Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 8/16 bit PPG0/1 0 X 0 0 0 X X 1B 0 X 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B (Disabled) TMCSR0 R/W 16 bit reload timer 0 R/W XXXXXXXXB R/W 16 bit reload timer 1 R/W XXXXXXXXB R/W 16 bit reload timer 2 R/W XXXXXXXXB R/W or R R/W R/W 16 bit PWC timer 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB XXXXXXXXB − − − − − − 0 0B 0 0 0 0 0 0 0 0B − − − − 0 0 0 0B TMR0/ TMRLR0 XXXXXXXXB TMCSR1 0 0 0 0 0 0 0 0B − − − − 0 0 0 0B TMR1/ TMRLR1 XXXXXXXXB TMCSR2 0 0 0 0 0 0 0 0B − − − − 0 0 0 0B TMR2/ TMRLR2 XXXXXXXXB PWCSR PWCR DIVR (Disabled) (Continued) DS07-13710-7E 29 MB90580C Series Address 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H Register name Compare register lower Compare register upper Compare register lower Compare register upper Compare control status register 0 Compare control status register 1 Input capture register lower Input capture register upper Input capture register lower Input capture register upper Input capture register lower Input capture register upper Input capture register lower Input capture register upper Input capture control status register 01 Input capture control status register 23 Timer data register lower Timer data register upper Timer control status register ROM mirroring function selection register Local-office address setting register L Local-office address setting register H Slave address setting register L Slave address setting register H Message length bit setting register Broadcast control bit setting register Abbreviated register Read/write name OCCP0 OCCP1 OCS0 OCS1 IPCP0 IPCP1 IPCP2 IPCP3 ICS01 R/W R/W R/W R/W R R R R R/W Resource name Output compare (ch.0) Output compare (ch.1) Output compare (ch.0) Output compare (ch.1) Input capture (ch.0) Input capture (ch.1) Input capture (ch.2) Input capture (ch.3) Input capture (ch.0, ch.1) Input capture (ch.2, ch.3) Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 − − 0 0B − − − 0 0 0 0 0B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B (Disabled) ICS23 R/W 0 0 0 0 0 0 0 0B (Disabled) TCDTL TCDTH TCCS ROMM MAWL MAWH SAWL SAWH DEWR DCWR R/W R/W R/W W R/W R/W R/W R/W R/W R/W IEBusTM controller Free-run timer 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B ROM mirror function − − − − − − − 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (Continued) 30 DS07-13710-7E MB90580C Series Address 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH 90H to 9DH Register name Command register L Command register H Status register L Status register H Lock read register L Lock read register H Master address read register L Master address read register H Message length bit read register Broadcast control bit read register Write data buffer Read data buffer Serial mode register 3 Serial control register 3 Serial input register 3/ serial output register 3 Serial status register 3 PWC noise filter register Clock division control register 3 Serial mode register 4 Serial control register 4 Serial input register 4/ serial output register 4 Serial status register 4 Port 0 input pull-up resistor setup register Port 1 input pull-up resistor setup register Port 6 input pull-up resistor setup register Clock division control register 4 Abbreviated register Read/write name CMRL CMRH STRL STRH LRRL LRRH MARL MARH DERR DCRR WDB RDB SMR3 SCR3 SIDR3/ SODR3 SSR3 RNCR CDCR3 SMR4 SCR4 SIDR4/ SODR4 SSR4 RDR0 RDR1 RDR6 CDCR4 R/W R/W R R/W or R R R/W or R R R R R W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Initial value 1 1 0 0 0 0 0 0B 0 0 0 0 0 0 0 XB 0 0 1 1 XXXXB 0 0 XX 0 0 0 0B XXXXXXXXB 1 1 1 0 XXXXB XXXXXXXXB 1 1 1 1 XXXXB XXXXXXXXB 0 0 0 XXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B IEBusTM controller UART3 XXXXXXXXB 0 0 0 0 1 − 0 0B PWC noise filter Communications prescaler 3 − − − − − 0 0 0B 0 − − − 1 1 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B UART4 XXXXXXXXB 0 0 0 0 1 − 0 0B Port 0 Port 1 Port 6 Communications prescaler 4 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B − − 0 0 0 0 0 0B 0 − − − 1 1 1 1B (Disabled) (Continued) DS07-13710-7E 31 MB90580C Series Address Register name Program address detection control/ status register Delayed interrupt generation/release register Low-power consumption mode control register Clock selection register Abbreviated register name PACSR DIRR LPMCR CKSCR Read/ write R/W R/W R/W or W R/W or R Resource name Address match detection function Delayed interrupt generation module Low-power consumption mode Initial value 9EH 9FH A0H A1H A2H to A4H A5H A6H A7H A8H A9H AAH ABH to ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH 0 0 0 0 0 0 0 0B − − − − − − − 0B 0 0 0 1 1 0 0 −B 1 1 1 1 1 1 0 0B (Disabled) Auto-ready function selection register External address output control register Bus control signal selection register Watch dog timer control register Time-base timer control register Watch timer control register ARSR HACR ECSR WDTC TBTC WTC W W W R or W R/W, W R/W or R Watch dog timer Timebase timer Watch timer External bus pin control circuit 0 0 1 1 − − 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 −B XXXXX 1 1 1B 1 − − 0 0 1 0 0B 1 X 0 0 0 0 0 0B (Disabled) Flash memory control status register FMCS R/W or R or W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt controller Flash interface 0 0 0 X 0 0 0 0B (Disabled) Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B (Continued) 32 DS07-13710-7E MB90580C Series (Continued) Address C0H to FFH 100H to #H # H to 1FEFH 1FF0H 1FF1H 1FF2H 1FF3H 1FF4H 1FF5H 1FF6H to 1FFFH Program address detection register 0 (lower) Program address detection register 0 (middle) Program address detection register 0 (upper) Program address detection register 1 (lower) Program address detection register 1 (middle) Program address detection register 1 (upper) PADR1 PADR0 Register name Abbreviated register Read/write name (External area) (RAM area) (Reserved area) R/W R/W R/W R/W R/W R/W (Reserved area) Address match detection function XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Resource name Initial value • Explanation of initial values→“0” : initial value“0” / “1” : initial value“1” / “X” : undefined / “−” : undefined (not used) • The addresses following 00FFH are reserved. No external bus access signal is generated. • Boundary #H between the RAM area and the reserved area varies with the product model. Note: For bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an initial value. Note that the values are different from reading results. For LPMCR/CKSCR/WDTC, there are cases where initialization is performed or not performed, depending on the types of the reset. However initial value for resets that initializes the value are listed. DS07-13710-7E 33 MB90580C Series ■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER Interrupt source Reset INT9 instruction Exception A/D converter Timebase timer DTP0 (external interrupt #0) /UART3 reception complete DTP1 (external interrupt #1) /UART4 reception complete DTP2 (external interrupt #2) /UART3 transmission complete DTP3 (external interrupt #3) /UART4 transmission complete DTP4 to 7 (external interrupt #4 to #7) Output compare (ch.1) match (I/O timer) UART2 reception complete UART1 reception complete Input capture (ch.3) include (I/O timer) Input capture (ch.2) include (I/O timer) Input capture (ch.1) include (I/O timer) Input capture (ch.0) include (I/O timer) 8/16 bit PPG0 counter borrow 16 bit reload timer 2 to 0 Watch prescaler Output compare (ch.0) match (I/O timer) UART2 transmission complete EI2OS support × × × × Interrupt vector No. #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H Interrupt control register ICR ⎯ ⎯ ⎯ ICR00 Address ⎯ ⎯ ⎯ 0000B0H Priority High ICR01 FFFFC4H FFFFC0H ICR02 FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF68H FFFF60H FFFF58H FFFF54H ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH Low × × #25 #26 #27 #28 #29 #30 #31 #32 #33 PWC timer measurement complete / over flow UART1 transmission complete 16-bit free run timer (I/O timer) over flow UART0 transmission complete 8/16 bit PPG1 counter borrow IEBus reception complete IEBus transmission start UART0 reception complete Flash memory status Delayed interrupt × #34 #35 #37 #39 × × #41 #42 : Indicates that the interrupt request flag is cleared by the EI2OS interrupt clear signal (stop request present). : Indicates that the interrupt request flag is cleared by the EI2OS interrupt clear signal. × : Indicates that the interrupt request flag is not cleared by the EI2OS interrupt clear signal. 34 DS07-13710-7E MB90580C Series ■ PERIPHERAL RESOURCES 1. I/O Ports When a data register serving for control output is read, the data output from it as a control output is read regardless of the value in the direction register. Note that, if a read modify write instruction (such as a bit set instruction) is used to preset output data in the data register when changing its setting from input to output, the data read is not the data register latched value but the input data from the pin. Ports 0 to 4 and 6 to A are input/output ports which serve as inputs when the direction register value is “0” or as outputs when the value is “1”. On the MB90580C series, ports 0 to 3 also serve as external bus pins. When the device is used in external bus mode, therefore, these ports are restricted on use. Ports 2 and 3 can be used as ports even in external bus mode depending on the setting of the corresponding function select bit. (2) Register configuration • Port 0 data register (PDR0) (1) Outline of I/O ports bit 15 ………… 8 (PDR1) 7 P07 6 P06 5 P05 4 P04 3 P03 2 P02 1 P01 0 P00 Address : 000000H Access Initial value (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • Port 1 data register (PDR1) bit Address : 000001H 15 P17 14 P16 13 P15 12 P14 11 P13 10 P12 9 P11 8 P10 7 ………… 0 (PDR0) Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) Initial value • Port 2 data register (PDR2) bit 15 ………… 8 (PDR3) 7 P27 6 P26 5 P25 4 P24 3 P23 2 P22 1 P21 0 P20 Address : 000002H Access Initial value (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • Port 3 data register (PDR3) bit Address : 000003H Access Initial value • Port 4 data register (PDR4) 15 P37 14 P36 13 P35 12 P34 11 P33 10 P32 9 P31 8 P30 7 ………… 0 (PDR2) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) bit 15 ………… 8 (PDR5) 7 P47 6 P46 5 P45 4 P44 3 P43 2 P42 1 P41 0 P40 Address : 000004H Access Initial value (R/W) (RW) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) (Continued) DS07-13710-7E 35 MB90580C Series • Port 5 data register (PDR5) bit Address : 000005H Access Initial value • Port 6 data register (PDR6) 15 P57 14 P56 13 P55 12 P54 11 P53 10 P52 9 P51 8 P50 7 ………… 0 (PDR4) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (1) (1) (1) (1) (1) (1) (1) (1) bit 15 ………… 8 (PDR7) 7 ⎯ (⎯) (⎯) 6 ⎯ (⎯) (⎯) 5 P65 4 P64 3 P63 2 P62 1 P61 0 P60 Address : 000006H Access Initial value (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) • Port 7 data register (PDR7) bit Address : 000007H Access Initial value • Port 8 data register (PDR8) 15 ⎯ (⎯) (⎯) 14 ⎯ (⎯) (⎯) 13 ⎯ 12 P74 11 P73 10 P72 9 P71 8 ⎯ 7 ………… 0 (PDR6) (⎯) (R/W) (R/W) (R/W) (R/W) (⎯) (⎯) (X) (X) (X) (X) (⎯) bit 15 ………… 8 (PDR9) 7 P87 6 P86 5 P85 4 P84 3 P83 2 P82 1 P81 0 P80 Address : 000008H Access Initial value (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • Port 9 data register (PDR9) bit Address : 000009H Access Initial value • Port A data register (PDRA) 15 P97 14 P96 13 P95 12 P94 11 P93 10 P92 9 P91 8 P90 7 ………… 0 (PDR8) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) bit 15 ………… 8 (Disabled) 7 ⎯ (⎯) (⎯) 6 ⎯ (⎯) (⎯) 5 ⎯ (⎯) (⎯) 4 ⎯ (⎯) (⎯) 3 ⎯ (⎯) (⎯) 2 PA2 1 PA1 0 PA0 Address : 00000AH Access Initial value (R/W) (R/W) (R/W) (X) (X) (X) • Port 0 direction register (DDR0) bit 15 ………… 8 Address : 000010H Access Initial value (DDR1) 7 D07 6 D06 5 D05 4 D04 3 D03 2 D02 1 D01 0 D00 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) (Continued) 36 DS07-13710-7E MB90580C Series • Port 1 direction register (DDR1) bit Address : 000011H Access Initial value • Port 2 direction register (DDR2) 15 D17 14 D16 13 D15 12 D14 11 D13 10 D12 9 D11 8 D10 7 ………… 0 (DDR0) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) bit 15 ………… 8 (DDR3) 7 D27 6 D26 5 D25 4 D24 3 D23 2 D22 1 D21 0 D20 Address : 000012H Access Initial value (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • Port 3 direction register (DDR3) bit Address : 000013H Access Initial value • Port 4 direction register (DDR4) 15 D37 14 P36 13 P35 12 P34 11 P33 10 P32 9 P31 8 P30 7 ………… 0 (DDR2) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) bit 15 ………… 8 (DDR5) 7 D47 6 D46 5 D45 4 D44 3 D43 2 D42 1 D41 0 D40 Address : 000014H Access Initial value (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • Port 5 direction register (DDR5) bit Address : 000015H Access Initial value • Port 6 direction register (DDR6) 15 D57 14 D56 13 D55 12 D54 11 D53 10 D52 9 D51 8 D50 7 ………… 0 (DDR4) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) bit 15 ………… 8 (DDR7) 7 ⎯ (⎯) (⎯) 6 ⎯ (⎯) (⎯) 5 D65 4 D64 3 D63 2 D62 1 D61 0 D60 Address : 000016H Access Initial value (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) • Port 7 direction register (DDR7) bit Address : 000017H Access Initial value 15 ⎯ (⎯) (⎯) 14 ⎯ (⎯) (⎯) 13 ⎯ 12 D74 11 D73 10 D72 9 D71 8 ⎯ 7 ………… 0 (DDR6) (⎯) (R/W) (R/W) (R/W) (R/W) (⎯) (⎯) (0) (0) (0) (0) (⎯) (Continued) DS07-13710-7E 37 MB90580C Series • Port 8 direction register (DDR8) bit 15 ………… 8 (DDR9) 7 D87 6 D86 5 D85 4 D84 3 D83 2 D82 1 D81 0 D80 Address : 000018H Access Initial value (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • Port 9 direction register (DDR9) ………… 8 14 bit 15 15 13 7 12 6 11 5 10 4 9 3 8 2 ………… 0 71 0 Address : 000019H Access Initial value D97 D96 RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00 D95 D94 D93 D92 D91 D90 (DDR8) (RDR1) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) • Port A direction register (DDRA) bit 15 ………… 8 (ODR4) 7 ⎯ (⎯) (⎯) 6 ⎯ (⎯) (⎯) 5 ⎯ (⎯) (⎯) 4 ⎯ (⎯) (⎯) 3 ⎯ (⎯) (⎯) 2 DA2 1 DA1 0 DA0 Address : 00001AH Access Initial value (R/W) (R/W) (R/W) (0) (0) (0) • Port 4 output pin register (ODR4) bit Address : 00001BH Access Initial value 15 14 13 12 11 10 9 8 7 ………… 0 (DDRA) OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • Port 5 analog input enable register (ADER) bit 15 ………… 8 7 6 5 4 3 2 1 0 Address : 00001CH Access Initial value ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (1) (1) (1) (1) (1) (1) (1) (1) • Port 0 input pull-up resistor setup register (RDR0) bit 15 ………… 8 7 6 5 4 3 2 1 0 Address : 00008CH Access Initial value (RDR1) RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • Port 1 input pull-up resistor setup register (RDR1) 15 14 13 bit 12 11 10 9 8 7 ………… 0 (RDR0) Address : 00008DH Access Initial value RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) (Continued) 38 DS07-13710-7E MB90580C Series (Continued) • Port 6 input pull-up resistor setup register (RDR6) bit 15 ………… 8 7 6 ⎯ (⎯) (⎯) 5 4 3 2 1 0 Address : 00008EH Access Initial value (CDCR4) ⎯ (⎯) (⎯) RD65 RD64 RD63 RD62 RD61 RD60 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) DS07-13710-7E 39 MB90580C Series (3) Block Diagram • Input/output port Internal data bus Data register read Data register Data register write Direction register Direction register write Pin Direction register read • Input pull-up resistor setup register Pull-up resistor (About 50 kΩ) Data register Port I/O Direction register Input pull-up resistor setup register Bus 40 DS07-13710-7E MB90580C Series • Output pin register Data register Port I/O Direction register Pin register Bus DS07-13710-7E 41 MB90580C Series 2. Timebase Timer The time-base timer consists of a 18-bit timer and an interval interrupt control circuit. Note that the time-base timer uses the oscillation clock regardless of the setting of the MCS bit in the CKSCR. (1) Register configuration • Timebase timer control register bit Address : 0000A9H Access Initial value (2) Block Diagram 15 Reserved 14 ⎯ (⎯) (⎯) 13 ⎯ (⎯) (⎯) 12 11 10 (W) (1) 9 8 TBTC TBIE TBOF TBR (R/W) (R/W) (0) (0) TBC1 TBC0 (R/W) (R/W) (0) (0) (R/W) (1) Main clock TBTC TBC1 TBC0 TBR TBIE TBOF AND Q S R Selector 212 214 216 219 TBTRES Clock input Time-base timer 211 213 215 218 Time-base interrupt WDTC WT1 WT0 Selector 2-bit counter CLR OF Watchdog reset generator CLR F2MC-16LX bus WTE WTC WDCS SCE WTC2 WTC1 WTC0 WTR WTIE WTOF AND Q S R AND S R To WDGRST internal reset generator Q Selector 29 210 211 212 213 214 215 WTRES 210 213 214 215 Watch timer Clock input Sub clock Clock interrupt WDTC PONR STBR WRST ERST SRST From power-on reset generator From hardware standby control circuit From RST pin From RST bit in STBYC register 42 DS07-13710-7E MB90580C Series 3. Watchdog Timer The watchdog timer consists of a 2-bit watchdog counter using carry signals from the 18-bit time-base timer as the clock source, a control register, and a watchdog reset control section. (1) Register configuration • Watchdog timer control register bit Address : 0000A8H Access Initial value (2) Block Diagram 7 (R) (X) 6 (R) (X) 5 (R) (X) 4 (R) (X) 3 (R) (X) 2 (W) (1) 1 (W) (1) 0 WDTC (W) (1) PONR STBR WRST ERST SRST WTE WT1 WT0 Main clock TBTC TBC1 TBC0 TBR TBIE TBOF AND Q S R Selector 212 214 216 219 TBTRES Clock input Time-base timer 211 213 215 218 Time-base interrupt WDTC WT1 WT0 WTE WTC Selector 2-bit counter CLR OF Watchdog reset generator CLR To WDGRST internal reset generator F2MC-16LX bus WDCS SCE WTC2 WTC1 WTC0 WTR WTIE WTOF AND S R Q Selector 29 210 211 212 213 214 215 WTRES 210 213 214 215 Watch timer Clock input Sub clock AND Q S R Watch interrupt WDTC PONR STBR WRST ERST SRST From power-on reset generator From hardware standby control circuit From RST pin From RST bit in STBYC register 43 DS07-13710-7E MB90580C Series 4. Watch timer The watch timer has the functions of a watchdog timer clock source, a sub clock oscillation settling time wait timer, and of a periodically interrupt generating interval timer. (1) Register configuration • Watch timer control register bit Address : 0000AAH Access Initial value (2) Block Diagram 7 (R/W) (1) 6 (R) (X) 5 4 3 2 1 0 WTC WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) Main clock TBTC TBC1 TBC0 TBR TBIE TBOF AND Q S R Selector 212 214 216 219 TBTRES Clock input Time-base timer 211 213 215 218 Time-base interrupt WDTC WT1 WT0 WTE WTC Selector 2-bit counter CLR OF Watchdog reset generator CLR To WDGRST internal reset generator F2MC-16LX bus WDCS SCE WTC2 WTC1 WTC0 WTR WTIE WTOF AND S R Q Selector 29 210 211 212 213 214 215 WTRES 210 213 214 215 Watch timer Clock input Sub clock AND Q S R Watch interrupt WDTC PONR STBR WRST ERST SRST From power-on reset generator From hardware standby control circuit From RST pin From RST bit in STBYC register DS07-13710-7E 44 MB90580C Series 5. External Memory Access (External Bus Pin Control Circuit) The external bus pin control circuit controls external bus pins used to expand the address/data buses of the CPU outside. (1) Register configuration • Automatic ready function selection register 15 bit 14 13 12 11 ⎯ (⎯) (⎯) 10 ⎯ (⎯) (⎯) 9 8 ARSR Address : 0000A5H Access Initial value IOR1 IOR0 HMR1 HMR0 (W) (0) (W) (0) (W) (1) (W) (1) LMR1 LMR0 (W) (0) (W) (0) • External address output control register bit Address : 0000A6H Access Initial value • Bus control signal selection register 7 E23 (W) (0) 6 E22 (W) (0) 5 E21 (W) (0) 4 E20 (W) (0) 3 E19 (W) (0) 2 E18 (W) (0) 1 E17 (W) (0) 0 E16 (W) (0) HACR bit Address : 0000A7H Access Initial value (2) Block Diagram 15 CKE (W) (0) 14 RYE (W) (0) 13 12 11 10 9 8 ⎯ (⎯) (⎯) ECSR HDE IOBS HMBS WRE LMBS (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) P0 P0 data P0 direction P1 P2 P3 P3 P0 RB Data control Address control Access control Access control DS07-13710-7E 45 MB90580C Series 6. PWC Timer The PWC (pulse width count) timer is a 16-bit multifunction up-counter with reload timer functions and inputsignal pulse-width count functions as well. The PWC timer consists of a 16-bit counter, a input pulse divider, a divide ratio control register, a count input pin, a pulse output pin, and a 16-bit control register. (1) Features of the PWC timer The PWC timer has the following features: • Timer functions Generates an interrupt request at set time intervals. Outputs pulse signals synchronized with the timer cycle. Selects the counter clock from among three internal clocks. • Pulse-width count functions Counts the time between external pulse input events. Selects the counter clock from among three internal clocks. Count mode •H pulse width (rising edge to falling edge)/L pulse width (falling edge to rising edge) •Rising-edge cycle (rising edge to falling edge)/Falling-edge cycle (falling edge to rising edge) •Count between edges (rising or falling edge to falling or rising edge) Capable of counting cycles by dividing input pulses by 22, 24, 26, 28 using an 8-bit input divider. Generates an interrupt request upon the completion of count operation. Selects single or consecutive count operation. 46 DS07-13710-7E MB90580C Series (2) Register configuration • PWC control status register Upper bit Address : 000055H Access Initial value • PWC control status register Lower 15 14 13 (R) (0) 12 EDIE 11 OVIR 10 OVIE 9 (R) (0) 8 (R/W) (0) STRT STOP EDIR (R/W) (R/W) (0) (0) ERR POUT PWCSR upper (R/W) (R/W) (R/W) (0) (0) (0) bit Address : 000054H Access Initial value • PWC data buffer register Upper 7 6 5 4 3 S/C 2 1 0 CKS1 CKS0 ReservedReserved MOD2 MOD1 MOD0 PWCSR lower (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) bit Address : 000057H Access Initial value • PWC data buffer register Lower 15 14 13 12 11 10 9 8 PWCR upper (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) bit Address : 000056H Access Initial value • Divide ratio control register 7 6 5 4 3 2 1 0 PWCR lower (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) bit Address : 000058H Access Initial value • PWC noise filter register 7 ⎯ (⎯) (⎯) 6 ⎯ (⎯) (⎯) 5 ⎯ (⎯) (⎯) 4 ⎯ (⎯) (⎯) 3 ⎯ (⎯) (⎯) 2 ⎯ (⎯) (⎯) 1 DIV1 0 DIV0 DIVR (R/W) (R/W) (0) (0) bit Address : 000086H Access Initial value 7 ⎯ (⎯) (⎯) 6 ⎯ (⎯) (⎯) 5 ⎯ (⎯) (⎯) 4 ⎯ (⎯) (⎯) 3 ⎯ (⎯) (⎯) 2 SW1 1 SW0 0 EN RNCR (R/W) (R/W) (R/W) (0) (0) (0) DS07-13710-7E 47 MB90580C Series (3) Block Diagram PWCR read 16 Error detection ERR PWCR 16 16 Write enable Reload Data transfer Overflow Internal clock (Machine clock/4) 16 Clock 16-bit up-count timer Timer clear Count enable 22 23 CKS1, CKS0 F2MC-16LX bus Clock divider Control circuit Control bit output Start edge End edge selection selection Count end edge Edge detection Count start edge Divider clear SW1 SW0 Noise Canceller PWC Divider ON/OFF Flag set Count end interrupt request Overflow interrupt request ERR CKS1 CKS0 8-bit divider Divide ratio selection DIVR EN 15 PWCSR 2 Overflow F.F. POT 48 DS07-13710-7E MB90580C Series 7. 16-bit I/O timer The 16-bit I/O timer module consists of one 16-bit free run timer, four input capture circuits, and two output comparators. This module allows two independent waveforms to be output on the basis of the 16-bit free run timer. Input pulse width and external clock periods can, therefore, be measured. (1) 16-bit free-run timer (1 channel) The 16-bit free run timer consists of a 16-bit up-counter, a control register, and a prescaler. The value output from this timer/counter is used as the base time for the input capture and output compare modules. • Counter operation clock (Selectable from among the following four) Four internal clock cycles: φ/4, φ/16, φ/64, φ/256 φ: Machine clock • Interrupts An interrupt can be generated when the 16-bit free-run timer causes a counter overflow or by compare/match operation with compare register 0. (The compare/match operation requires the mode setting). • Counter value An interrupt can be generated when the 16-bit free-run timer causes a counter overflow or when a match with compare register 0 occurs (The compare/match function can be used by the appropriate mode setting). • Initialization The counter value can be initialized to “0000H” at a reset, soft clear operation, or a match with compare register 0. (2) Output compare module (2 channels) The output compare module consists of two 16-bit compare registers, compare output latches, and control registers. When the 16-bit free-run timer value matches the compare register value, this module generates an interrupt while inverting the output level. • Two compare registers can operate independently. Output pin and interrupt flag for each compare register • A pair of compare registers can be used to control the output pin. Two compare registers can be used to invert the output pin polarity. • The initial value for each output pin can be set. • An interrupt can be generated by compare/match operation. (3) Input capture module (4 channels) The input capture module consists of capture registers and control registers respectively associated with four independent external input pins. This module can hold the 16-bit free run timer value in the capture register. In addition, it can detect an arbitrary edge of the signal input from each external input pin to generate an interrupt. • The external input signal edge to be detected can be selected. One or both of the rising and falling edges can be selected. • Four input capture channels can operate independently. • An interrupt can be generated at a valid edge of the external input signal. The extended intelligent I/O service can be activated by the interrupt by the input capture module. DS07-13710-7E 49 MB90580C Series (4) Register configuration • Timer data register (upper) bit Address : 00006DH Access Initial value • Timer data register (lower) 15 T15 14 T14 13 T13 12 T12 11 T11 10 T10 9 T09 8 T08 TCDTH (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) bit Address : 00006CH Access Initial value • Timer control status register 7 T07 6 T06 5 T05 4 T04 3 T03 2 T02 1 T01 0 T00 TCDTL (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) bit Address : 00006EH Access Initial value • Compare register (upper) 7 Reserved 6 5 4 3 2 1 0 TCCS IVF IVFE STOP MODE CLR CLK1 CLK0 (⎯) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) bit Address : ch0 00005BH : ch1 00005DH Access Initial value 15 C15 14 C14 13 12 11 10 C09 9 C08 8 OCCP0 OCCP1 C13 C12 C11 C10 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • Compare register (lower) bit Address : ch0 00005AH : ch1 00005CH Access Initial value 7 C07 6 C06 5 C05 4 C04 3 C03 2 1 0 C00 OCCP0 OCCP1 C02 C01 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • Compare control status register 1 bit Address : ch1 00005FH Access Initial value • Compare control status register 0 15 ⎯ (⎯) (⎯) 14 ⎯ (⎯) (⎯) 13 ⎯ (⎯) (⎯) 12 11 10 9 8 OCS1 CMOD OTE1 OTE0 OTD1 OTD0 (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) bit Address : ch0 00005EH Access Initial value 7 6 5 4 3 ⎯ (⎯) (⎯) 2 ⎯ 1 0 OCS0 ICP1 ICP0 ICE1 ICE0 (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) CST1 CST0 (⎯) (R/W) (R/W) (⎯) (0) (0) (Continued) 50 DS07-13710-7E MB90580C Series (Continued) • Input capture register (upper) Address bit : ch0 000061H : ch1 000063H : ch2 000065H : ch3 000067H Access Initial value 15 14 13 12 11 10 9 8 IPCP0 upper IPCP1 upper IPCP2 upper IPCP3 upper CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) • Input capture register (lower) Address bit : ch0 000060H : ch1 000062H : ch2 000064H : ch3 000066H Access Initial value 7 6 5 4 3 2 1 0 IPCP0 lower IPCP1 lower IPCP2 lower IPCP3 lower CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) • Input capture control status register 01 bit Address : 000068H Access Initial value • Input capture control status register 23 7 6 5 4 3 2 1 0 ICS01 ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) bit Address : 00006AH Access Initial value 7 6 5 4 3 2 1 0 ICS23 ICP3 ICP2 ICE3 ICE2 EG31 EG30 EG21 EG20 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) DS07-13710-7E 51 MB90580C Series (5) Block Diagram Interrupt request IVF IVFE STOP MODE CLR CLK1 CLK0 φ Frequency divider Comparator 0 16-bit up-counter Output count value (T15 to T00) Compare control Compare register ch.0 CMOD OUT0 Clock F2MC-16LX bus T Q OTE0 Compare control Compare register ch.1 ICP1 ICP0 ICE1 T Q OTE1 OUT1 ICE0 Compare interrupt 0 Control block Each control block Input capture data register ch.0, ch.2 Edge detection IN0, IN2 Compare interrupt 1 EG11 EG10 EG01 EG00 Input capture data register ch.1, ch.3 Edge detection ICP0 ICE1 ICE0 IN1, IN3 ICP1 Capture interrupt 1/3 Capture interrupt 0/2 52 DS07-13710-7E MB90580C Series 8. 16-bit Reload Timer The 16-bit reload timer has three channels, each of which consists of a 16-bit down counter, a 16-bit reload register, an input pin (TIN), an output pin (TOT), and a control register. The input clock can be selected from among three internal clocks and one external clock. (1) Register configuration • Timer control status register (upper) Address bit : ch0 000049H : ch1 00004DH : ch2 000051H Access Initial value 15 ⎯ (⎯) (⎯) 7 ⎯ 14 ⎯ 13 ⎯ 12 11 10 9 8 TMCSR0 upper TMCSR1 upper TMCSR2 upper CSL1 CSL0 MOD2 MOD1 (⎯) (⎯) 6 (⎯) (⎯) 5 (⎯) (R/W) (R/W) (R/W) (R/W) (⎯) (0) (0) (0) (0) 4 3 2 1 0 TMCSR0 lower TMCSR1 lower TMCSR2 lower • Timer control status register (lower) Address bit : ch0 000048H : ch1 00004CH : ch2 000050H Access Initial value MOD0 OUTE OUTL RELD INTE UF CNTE TRG (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) (read) TMR0 upper TMR1 upper TMR2 upper (write) TMRLR0 upper TMRLR1 upper TMRLR2 upper (read) TMR0 lower TMR1 lower TMR2 lower (write) TMRLR0 lower TMRLR1 lower TMRLR2 lower • 16-bit timer register (upper) /16 bit reload register (upper) Address bit : ch0 00004BH : ch1 00004FH : ch2 000053H Access Initial value 15 14 13 12 11 10 9 8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • 16-bit timer register (lower) /16 bit reload register (lower) Address bit : ch0 00004AH : ch1 00004EH : ch2 000052H Access Initial value 7 6 5 4 3 2 1 0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) DS07-13710-7E 53 MB90580C Series (2) Block Diagram 16 16-bit reload register 8 Reload RELD 16-bit down-counter UF 16 2 OUTE OUTL F2MC-16LX bus GATE CSL1 OUT CTL. INTE UF IRQ Clock selector CSL0 CNTE Retrigger 2 IN EXCK φφφ ——— 21 23 25 CTL 3 MOD2 MOD1 TRG Clear EI2OSCLR Port (TIN) Port (TOT) Output enable Prescaler clear Machine clock 3 Serial baud rate (channel n) MOD0 Note: Reload timer channels and UART channels are connected as follows •Reload timer channel 0 : UART0, UART3 •Reload timer channel 1 : UART1, UART4 •Reload timer channel 2 : UART2 54 DS07-13710-7E MB90580C Series 9. 8/16-bit PPG 8/16-bit PPG is an 8/16-bit reload timer module. The block performs PPG output in which the pulse output is controlled by the operation of the timer. The hardware consists of two 8-bit down-counters, four 8-bit reload registers, one 16-bit control register, two external pulse output pins, and two interrupt outputs. The PPG has the following functions. • 8-bit PPG output in two channels independent operation mode: Two independent PPG output channels are available. • 16-bit PPG output operation mode : One 16-bit PPG output channel is available. • 8 + 8-bit PPG output operation mode : Variable-period 8-bit PPG output operation is available by using the output of channel 0 as the clock input to channel 1. • PPG output operation : Outputs pulse waveforms with variable period and duty ratio. Can be used as a D/A converter in conjunction with an external circuit. (1) Register configuration • PPG0 operating mode control register bit Address : ch0 0000044H Access Initial value • PPG1 operating mode control register 7 PEN0 6 ⎯ 5 4 3 2 ⎯ 1 ⎯ 0 Reserved POE0 PIE0 PUF0 PPGC0 (R/W) (⎯) (R/W) (R/W) (R/W) (⎯) (0) (X) (0) (0) (0) (X) (⎯) (R/W) (X) (1) bit Address : ch1 0000045H Access Initial value • PPG0 and 1 output control registers 15 PEN1 14 ⎯ 13 12 11 10 9 8 Reserved POE1 PIE1 PUF1 MD1 MD0 PPGC1 (R/W) (⎯) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (X) (0) (0) (0) (0) (0) (1) bit Address : ch0, 1 0000046H Access Initial value • Reload register H 7 6 5 4 3 2 1 0 PPGOE PCS2 PCS1 PCS0 PCM2PCM1PCM0 ReReserved served (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) bit Address : ch0 000041H : ch1 000043H Access Initial value 15 14 13 12 11 10 9 8 PRLH0 PRLH1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • Reload register L bit Address : ch0 000040H : ch1 000042H Access Initial value 7 6 5 4 3 2 1 0 PRLL0 PRLL1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 55 DS07-13710-7E MB90580C Series (2) Block Diagram • Block diagram (8 bit PPG (ch.0) ) PPG0 output enable Machine clock divided by 16 Machine clock divided by 8 Machine clock divided by 4 Machine clock divided by 2 Machine clock PPG0 PPG0 output latch Invert Clear PEN0 PCNT (Down-counter) Count clock selection S RQ IRQ Reload Timebase counter output oscillation clock divided by 512 ch.1 borrow L/H Selector L/H select PRLL0 PRLBH0 PIE0 PRLH0 PUF0 L-side data bus H-side data bus PPGC0 (Operation mode control) 56 DS07-13710-7E MB90580C Series • Block Diagram (8/16 bit PPG (ch.1) ) PPG1 output enable Machine clock divided by 16 Machine clock divided by 8 Machine clock divided by 4 Machine clock divided by 2 Machine clock PPG1 A/D converter PPG1 output latch Invert Clear PEN1 Count clock selection ch0 borrow Timebase counter output oscillation clock divided by 512 L/H select PCNT (Down-counter) Reload S RQ IRQ L/H Selector PRLL1 PRLBH1 PIE PRLH1 PUF L-side data bus H-side data bus PPGC1 (Operation mode control) DS07-13710-7E 57 MB90580C Series 10. DTP/External Interrupts The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16LX CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the requests to the F2MC-16LX CPU to activate the intelligent I/O service or interrupt processing. Two request levels (“H” and “L”) are provided for the intelligent I/O service. For external interrupt requests, generation of interrupts on a rising or falling edge as well as on “H” and “L” levels can be selected, giving a total of four types. (1) Register configuration • Interrupt/DTP enable register bit Address : 0000030H Access Initial value • Interrupt/DTP source register 7 6 5 4 3 2 1 0 ENIR EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) bit Address : 0000031H Access Initial value • Request level setting register (lower) 15 14 13 12 11 10 9 8 EIRR ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) bit Address : 0000032H Access Initial value • Request level setting register (upper) 7 LB3 6 LA3 5 LB2 4 LA2 3 LB1 2 LA1 1 LB0 0 LA0 ELVR lower (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) bit Address : 0000033H Access Initial value (2) Block Diagram F2MC-16LX bus 8 15 LB7 14 LA7 13 LB6 12 LA6 11 LB5 10 LA5 9 LB4 8 LA4 ELVR upper (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Interrupt/DTP enable register Gate Source F/F Edge detect circuit 8 8 Request input 8 Interrupt/DTP source register 8 Request level setting register 58 DS07-13710-7E MB90580C Series 11. Delayed Interrupt Generation Module The delayed interrupt generation module is used to generate the task switching interrupt. Interrupt requests to the F2MC-16LX CPU can be generated and cleared by software using this module. (1) Register configuration The DIRR register controls generation and clearing of delayed interrupt requests. Writing “1” to the register generates a delayed interrupt request. Writing “0” to the register clears the delayed interrupt request. The register is set to the interrupt cleared state by a reset. Either “0” or “1” can be written to the reserved bits. However, considering possible future extensions, it is recommended that the set bit and clear bit instructions are used for register access. • Delayed interrupt generation/release register bit Address : 00009FH Access Initial value 15 ⎯ (⎯) (⎯) 14 ⎯ (⎯) (⎯) 13 ⎯ (⎯) (⎯) 12 ⎯ (⎯) (⎯) 11 ⎯ (⎯) (⎯) 10 ⎯ (⎯) (⎯) 9 ⎯ 8 R0 DIRR (⎯) (R/W) (⎯) (0) (2) Block Diagram F2MC-16LX bus Delayed interrupt generation/ release decode Interrupt latch DS07-13710-7E 59 MB90580C Series 12. A/D Converter The A/D converter converts analog input voltages to digital values. The A/D converter has the following features. • Conversion time: Minimum of 34.7 μs per channel (for a 12 MHz machine clock) • Uses RC-type successive approximation conversion with a sample and hold circuit. • 8/10-bit resolution • Eight program-selectable analog input channels Single conversion mode: Selectively convert one channel. Scan conversion mode: Continuously convert multiple channels. Maximum of 8 program selectable channels. Continuous conversion mode : Repeatedly convert specified channels. Stop conversion mode:Convert one channel then halt until the next activation. (Enables synchronization of the conversion start timing.) • An A/D conversion completion interrupt request. An A/D conversion completion interrupt request to the CPU can be generated on the completion of A/D conversion. This interrupt can activate EI2OS to transfer the result of A/D conversion to memory and is suitable for continuous operation. • Activation by software, external trigger (falling edge), or timer (rising edge) can be selected. (1) Register configuration • Control status register (upper) bit Address : 000037H Access Initial value • Control status register (lower) 15 14 13 12 11 10 9 8 Reserved BUSY INT INTE PAUS STS1 STS0 STRT ADCS2 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (⎯) (0) (0) (0) (0) (0) (0) (0) (0) bit Address : 000036H Access Initial value • Data register (upper) 7 6 5 4 3 2 1 0 ADCS1 MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) bit Address : 000039H Access Initial value • Data register (lower) 15 (W) (0) 14 (W) (0) 13 (W) (0) 12 (W) (0) 11 (W) (1) 10 ⎯ (⎯) ( ⎯) 9 D9 (R) (X) 8 D8 (R) (X) ADCR2 SELB ST1 ST0 CT1 CT0 bit Address : 000038H Access Initial value 7 D7 (R) (X) 6 D6 (R) (X) 5 D5 (R) (X) 4 D4 (R) (X) 3 D3 (R) (X) 2 D2 (R) (X) 1 D1 (R) (X) 0 D0 (R) (X) ADCR1 60 DS07-13710-7E MB90580C Series (2) Block Diagram AVCC AVRH,AVRL AVSS D/A converter MPX AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Input circuit Successive approximation register Comparator Sample and hold circuit Decoder Data register ADCR1, 2 F2 M C 1 6 L X b u s Control status register upper Control status register lower Trigger activation ADTG Timer activation PPG1 output ADCS1, 2 Operating clock Prescaler φ DS07-13710-7E 61 MB90580C Series 13. D/A Converter D/A converter is an R-2R type D/A converter with 8-bit resolution. The device contains two D/A converters. The D/A control register controls the output of the two D/A converters independently. (1) Register configuration • D/A converter data register 1 bit Address : 00003BH 15 14 13 12 11 10 9 8 DAT1 DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10 Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) • D/A converter data register 0 bit Address : 00003AH 7 6 5 4 3 2 1 0 DAT0 DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00 Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) • D/A control register 1 bit Address : 00003DH Access Initial value • D/A control register 0 15 ⎯ (⎯) (⎯) 14 ⎯ (⎯) (⎯) 13 ⎯ (⎯) (⎯) 12 ⎯ (⎯) (⎯) 11 ⎯ (⎯) (⎯) 10 ⎯ (⎯) (⎯) 9 ⎯ 8 DAE1 DACR1 (⎯) (R/W) (⎯) (0) bit Address : 00003CH Access Initial value 7 ⎯ (⎯) (⎯) 6 ⎯ (⎯) (⎯) 5 ⎯ (⎯) (⎯) 4 ⎯ (⎯) (⎯) 3 ⎯ (⎯) (⎯) 2 ⎯ (⎯) (⎯) 1 ⎯ 0 DAE0 DACR0 (⎯) (R/W) (⎯) (0) 62 DS07-13710-7E MB90580C Series (2) Block Diagram F2MC-16LX - BUS DA DA DA DA DA DA DA DA 17 16 15 14 13 12 11 10 DA DA DA DA DA DA DA DA 07 06 05 04 03 02 01 00 DVR DA17 2R DA16 2R DA15 R DA07 DVR 2R DA06 2R DA05 R R R DA11 2R DA10 R DA01 2R DA00 R 2R 2R DAE1 DAE0 2R 2R Standby control Standby control DA output channel 1 DA output channel 0 DS07-13710-7E 63 MB90580C Series 14. Communication Prescaler The register (clock division control register) of the communication prescaler controls division of the machine clock frequency. It is designed to provide a fixed baud rate for a variety of machine clock frequencies depending on the user setting. The output from the communication prescaler is used by the UARTs. (1) Register configuration • Clock division control registers 0 to 4 bit Address : 00002CH 00002EH Access 000034H Initial value 000087H 00008FH 15 MD 14 ⎯ 13 ⎯ (⎯) (⎯) 12 ⎯ 11 10 9 8 CDCR0 CDCR1 CDCR2 CDCR3 CDCR4 DIV3 DIV2 DIV1 DIV0 (R/W) (⎯) (0) (⎯) (⎯) (R/W) (R/W) (R/W) (R/W) (⎯) (1) (1) (1) (1) 64 DS07-13710-7E MB90580C Series 15. UART The UART is a serial I/O port for asynchronous (start-stop) communication or clock-synchronous communication. The UART has the following features: • Full-duplex double buffering • Capable of asynchronous (start-stop) and CLK-synchronous communications • Support for the multiprocessor mode • Dedicated baud rate generator integrated Baud rate Operation Baud rate Asynchronous 31250/9615/4808/2404/1202 bps CLK synchronous 2 M/1 M/500 k/250 k/125 k/62.5 kbps * : Assuming internal machine clock frequencies of 6, 8, 10, 12, and 16 MHz • Capable of setting an arbitrary baud rate using an external clock • Error detection functions (parity, framing, overrun) • HRz sign transfer signal (1) Register configuration • Serial mode register 0 to 4 Address : 0000020H bit 0000024H 0000028H Access 0000082H 0000088H Initial value • Serial control register 0 to 4 7 6 5 4 3 2 Reserved 1 0 MD1 MD0 CS2 CS1 CS0 SCKE SOE (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) SMR0 SMR1 SMR2 SMR3 SMR4 Address : 0000021H bit 0000025H 0000029H Access 0000083H 0000089H Initial value 15 PEN 14 P 13 SBL 12 CL 11 10 9 8 A/D REC RXE TXE (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (1) (0) (0) SCR0 SCR1 SCR2 SCR3 SCR4 • Serial input register 0 to 4/serial output register 0 to 4 bit 0000022H Address : 0000026H Access 000002AH Initial value 0000084H 000008AH • Serial status register 0 to 4 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) (read) (write) SIDR0 SODR0 SIDR1 SODR1 SIDR2 SODR2 SIDR3 SODR3 SIDR4 SODR4 Address : 0000023H bit 0000027H 000002BH Access 0000085H 000008BH Initial value 15 PE 14 13 12 11 10 9 RIE 8 TIE ORE FRE RDRFTDRE ⎯ (R/W) (R/W) (R/W) (R/W) (R/W) (⎯) (R/W) (R/W) (0) (0) (0) (0) (1) (⎯) (0) (0) SSR0 SSR1 SSR2 SSR3 SSR4 DS07-13710-7E 65 MB90580C Series (2) Block Diagram Control signals Receive interrupt signal (to CPU) Dedicated baud rate generator 16 bit reload timer channel 0 to 2 External clock Clock select circuit Receive clock SCK0 to SCK4 Transmit clock Transmit interrupt signal (to CPU) Receive control circuit Start bit detection circuit Receive bit counter Receive parity counter Transmit control circuit Transmit start circuit Transmit bit counter Transmit parity counter SOT0 to SOT4 SIN0 ∼ SIN4 Receive condition decision circuit Shift register for reception Reception complete Shift register for transmission Start transmission Reception error generation signal for EI2OS (to CPU) SIDR0 to SIDR4 SODR0 to SODR4 F2MC-16LX bus SMR0 to SMR4 register MD1 MD0 CS2 CS1 CS0 SCKE SOE SCR0 to SCR4 register PEN P SBL CL A/D REC RXE TXE SSR0 to SSR4 register PE ORE FRE RDRF TDRE RIE TIE Control signal 66 DS07-13710-7E MB90580C Series 16. IEBusTM Controller The IEBusTM (Inter-Equipment Bus) is a small-scale, two-wire serial bus interface designed for data transfer between pieces of equipment. This interface is applicable, for example, as a bus interface for controlling vehicle-mounted devices. IEBusTM has the following features: • Multitasking Any of the units connected to the IEBusTM can transmit data to another one. • Broadcast function (Communication from one unit to multiple units) Group broadcast : Broadcast to a group of units All-unit broadcast : Broadcast to all units • Three modes can be selected for different transmission speeds. IEBusTM internal frequency 6 MHz Mode 0 Mode 1 Mode 2 About 3.9 kbps About 17 kbps About 26 kbps 6.29 MHz About 4.1 kbps About 18 kbps About 27 kbps • Data buffer for transmission 8-byte FIFO buffer • Data buffer for reception 8-byte FIFO buffer • CPU internal operating frequency (12 MHz, 12.58 MHz) • Frequency tolerance In mode 0 or 1 : ±1.5% In mode 2 : ±0.5% (1) Register configuration • Local-office address setting register H bit Address : 000071H Access Initial value 15 14 13 12 11 10 9 8 MAWH Reserved Reserved Reserved Reserved MA11 MA10 MA09 MA08 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • Local-office address setting register L bit Address : 000070H Access Initial value • Slave address setting register H 7 6 5 4 3 2 1 0 MAWL MA07 MA06 MA05 MA04 MA03 MA02 MA01 MA00 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) bit Address : 000073H Access Initial value 15 14 13 12 11 10 9 8 SAWH Reserved Reserved Reserved Reserved SA11 SA10 SA09 SA08 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) (Continued) DS07-13710-7E 67 MB90580C Series • Slave address setting register L bit Address : 000072H 7 6 5 4 3 2 1 0 SAWL SA07 SA06 SA05 SA04 SA03 SA02 SA01 SA00 Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (X) (X) (X) (X) (X) (X) (X) (X) • Broadcast control bit setting register bit Address : 000075H 15 14 13 12 11 C3 10 C2 9 C1 8 C0 DCWR DO3 DO2 DO1 DO0 Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) • Broadcast control bit read register bit Address : 00007FH Access Initial value • Message length bit setting register 15 (R) (0) 14 (R) (0) 13 (R) (0) 12 (R) (X) 11 C3 (R) (X) 10 C2 (R) (X) 9 C1 (R) (X) 8 C0 (R) (X) DCRR DO3 DO2 DO1 DO0 bit Address : 000074H 7 DE7 6 DE6 5 DE5 4 DE4 3 DE3 2 DE2 1 DE1 0 DE0 DEWR Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) • Message length bit read register bit Address : 00007EH Access Initial value • Command register H 7 DE7 (R) (X) 6 DE6 (R) (X) 5 DE5 (R) (X) 4 DE4 (R) (X) 3 DE3 (R) (X) 2 DE2 (R) (X) 1 DE1 (R) (X) 0 DE0 (R) (X) DERR bit Address : 000077H 15 14 13 12 11 10 9 8 CMRH MD1 MD0 PCOM RIE TIE GOTMGOTS Reserved Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (X) • Command register L bit Address : 000076H 7 RXS 6 TXS 5 4 3 CS1 2 1 0 CMRL TIT1 TIT0 CS0 RDBC WDBC Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (1) (1) (0) (0) (0) (0) (0) (0) • Status register H bit Address : 000079H Access Initial value 15 COM 14 TE 13 PEF (R) (X) 12 ACK 11 RIF 10 TIF 9 TSL (R) (0) 8 EOD (R) (0) (Continued) STRH (R) (R/W) (0) (0) (R) (R/W) (R/W) (X) (0) (0) 68 DS07-13710-7E MB90580C Series (Continued) • Status register L bit Address : 000078H Access Initial value 7 (R) (0) 6 (R) (0) 5 (R) (1) 4 (R) (1) 3 ST3 (R) (X) 2 ST2 (R) (X) 1 ST1 (R) (X) 0 ST0 (R) (X) STRL WDBF RDBF WDBE RDBE • Lock read register H bit Address : 00007BH Access Initial value • Lock read register L 15 (R) (1) 14 (R) (1) 13 (R) (1) 12 LOC (R/W) (0) 11 (R) (X) 10 (R) (X) 9 (R) (X) 8 LRRH (R) (X) Reserved Reserved Reserved LD11 LD10 LD09 LD08 bit Address : 00007AH Access Initial value • Master address read register H 7 LD07 (R) (X) 6 LD06 (R) (X) 5 LD05 (R) (X) 4 (R) (X) 3 (R) (X) 2 (R) (X) 1 (R) (X) 0 LRRL (R) (X) LD04 LD03 LD02 LD01 LD00 bit Address : 00007DH Access Initial value • Master address read register L 15 (R) (1) 14 (R) (1) 13 (R) (1) 12 (R) (1) 11 (R) (X) 10 (R) (X) 9 (R) (X) 8 MARH (R) (X) Reserved Reserved Reserved Reserved MA11 MA10 MA09 MA08 bit Address : 00007CH Access Initial value • Read data buffer 7 (R) (X) 6 (R) (X) 5 (R) (X) 4 (R) (X) 3 (R) (X) 2 (R) (X) 1 (R) (X) 0 MARL (R) (X) MA07 MA06 MA05 MA04 MA03 MA02 MA01 MA00 bit Address : 000081H Access Initial value • Write data buffer 15 RD7 (R) (X) 14 RD6 (R) (X) 13 RD5 (R) (X) 12 RD4 (R) (X) 11 RD3 (R) (X) 10 RD2 (R) (X) 9 RD1 (R) (X) 8 RD0 (R) (X) RDB bit Address : 000080H Access Initial value 7 WD7 (W) (X) 6 WD6 (W) (X) 5 WD5 (W) (X) 4 WD4 (W) (X) 3 (W) (X) 2 (W) (X) 1 (W) (X) 0 WDB (W) (X) WD3 WD2 WD1 WD0 DS07-13710-7E 69 MB90580C Series (2) Block Diagram Local-office address setting register Slave address setting register F2MC-16LX internal bus Broadcast control bit setting register Message length bit setting register 8-byte FIFO, write data buffer Master address read register Broadcast control bit read register Message length bit read register Lock read register 8-byte FIFO, read data buffer Command register Status register Interrupt request signal (transmission/reception) Internal clock 12 MHz/12.58 MHz Control circuit IEBusTM protocol controller TX RX 2 Prescaler 6 MHz/6.29 MHz IEBusTM controller The control circuit in the IEBusTM controller executes the following control functions: • Controls the number of bytes in data to be transmitted and received. • Controls the maximum number of bytes transmitted. • Detects the results of arbitration. • Evaluates the return of acknowledgment of each field. • Generates interrupt signals. 70 DS07-13710-7E MB90580C Series 17. Clock Monitor Function The clock monitor function outputs the frequency-divided machine clock signal (for monitoring purposes) from the CKOT pin. (1) Register configuration • Clock output enable register bit Address : 00003EH Access Initial value 7 ⎯ (⎯) (⎯) 6 ⎯ (⎯) (⎯) 5 ⎯ (⎯) (⎯) 4 3 2 1 0 CLKR ⎯ CKEN FRQ2 FRQ1 FRQ0 (⎯) (R/W) (R/W) (R/W) (R/W) (⎯) (0) (0) (0) (0) (2) Block Diagram F2MC-16LX bus CKEN FRQ2 FRQ1 FRQ0 Divider circuit Machine clock φ P65/CKOT DS07-13710-7E 71 MB90580C Series 18. Address Match Detection Function When an address matches the value set in the address detection register, the instruction code to be loaded into the CPU is forced to be replaced with the INT9 instruction code (01H). When executing a set instruction, the CPU executes the INT9 instruction. The address match detection function is implemented by processing using the INT9 interrupt routine. The device contains two address detection registers, each provided with a compare enable bit. When the value set in the address detection register matches an address and the interrupt enable bit is “1”, the instruction code to be loaded into the CPU is forced to be replaced with the INT9 instruction code. (1) Register configuration • Program address detection register 0 to 2 (PADR0) 7 bit 6 5 4 3 2 1 0 PADR0 (lower) Address : 001FF0H Access Initial value bit (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 17 16 15 14 13 12 11 10 PADR0 (middle) Address : 001FF1H Access Initial value bit (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0 PADR0 (upper) Address : 001FF2H Access Initial value (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • Program address detection register 3 to 5 (PADR1) 17 bit 16 15 14 13 12 11 10 PADR1 (lower) Address : 001FF3H Access Initial value bit (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0 PADR1 (middle) Address : 001FF4H Access Initial value bit (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 17 16 15 14 13 12 11 10 PADR1 (upper) Address : 001FF5H Access Initial value (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • Program address detection control/status register (PACSR) 7 6 5 4 3 2 1 0 bit ReReReReReReAD1E AD0E : 00009EH Address served served served served served served (−) (−) (−) (−) (R/W) (−) (R/W) (−) Access (0) (0) (0) (0) (0) (0) (0) (0) Initial value 72 DS07-13710-7E MB90580C Series (2) Block Diagram Address detection register Compare Address latch Enable bit INT9 Instruction F2MC-16LX CPU core F2MC-16LX bus DS07-13710-7E 73 MB90580C Series 19. ROM Mirroring Function Selection Module The ROM mirroring function selection module can select what the FF bank allocated the ROM sees through the 00 bank according to register settings. (1) Register configuration • ROM mirroring function selection register bit Address : 00006FH Access 15 ⎯ (⎯) 14 ⎯ (⎯) 13 ⎯ (⎯) 12 ⎯ (⎯) 11 ⎯ (⎯) 10 ⎯ (⎯) 9 ⎯ (⎯) 8 MI (W) ROMM (2) Block Diagram F2MC-16LX bus ROM mirroring function selection register Address area Address FF bank 00 bank Data ROM 74 DS07-13710-7E MB90580C Series 20. One-Megabit Flash Memory The 1Mbit flash memory is allocated in the FEH to FFH banks on the CPU memory map. Like masked ROM, flash memory is read-accessible and program-accessible to the CPU using the flash memory interface circuit. The flash memory can be programmed/erased by the instruction from the CPU via the flash memory interface circuit. The flash memory can therefore be reprogrammed (updated) while still on the circuit board under integrated CPU control, allowing program code and data to be improved efficiently. Note that sector operations such as “enable sector protect” cannot be used. Features of 1Mbit flash memory • 128K words x 8 bits or 64K words x 16 bits (16K + 8K x 2 + 32K + 64K) sector configuration • Automatic program algorithm (Embedded Algorithm: Same as the MBM29F400TA) • Erasure suspend/resume function integrated • Detection of programming/erasure completion using the data polling or toggle bit • Detection of programming/erasure completion using CPU interrupts • Compatible with JEDEC standard commands • Capable of erasing data sector by sector (arbitrary combination of sectors) • Minimum number of times of programming/erasure: 10,000 (1) Register configuration • Flash memory control status register bit Address : 0000AEH Access Initial value 7 INTE (R/W) (0) 6 RDYINT (R/W) (0) 5 WE (R/W) (0) 4 RDY (R) (X) 3 Reserved 2 LPM1 (R/W) (0) 1 Reserved 0 LPM0 (R/W) (0) FMCS (W) (0) (W) (0) DS07-13710-7E 75 MB90580C Series (2) Sector configuration of 1Mbit flash memory The 1Mbit flash memory has the sector configuration illustrated below. The addresses in the illustration are the upper and lower addresses of each sector. When accessed from the CPU, SA0 and SA1 to SA4 are allocated in the FE and FF bank registers, respectively. Flash memory SA4 (16 Kbytes) CPU address FFFFFFH FFC000H FFBFFFH Programmer address * 7FFFFH 7C000H 7BFFFH 7A000H 79FFFH 78000H 77FFFH 70000H 6FFFFH 60000H SA3 (8 Kbytes) FFA000H FF9FFFH SA2 (8 Kbytes) FF8000H FF7FFFH SA1 (32 Kbytes) FF0000H FEFFFFH SA0 (64 Kbytes) FE0000H * : Programmer addresses correspond to CPU addresses when data is programmed in flash memory by a parallel programmer. Programmer addresses are used to program/erase data using a general-purpose programmer. 76 DS07-13710-7E MB90580C Series 21. Low-Power Consumption Control Circuit The operation modes of the MB90580C series are the PLL clock, PLL sleep, watch, main clock, main sleep, stop, and hardware standby modes. The operation modes excluding the PLL clock mode are classified as lowpower consumption modes. The low power consumption circuit has the following functions. • Main clock mode/Main sleep mode In either mode, the microcontroller operates only with the main clock (OSC oscillation clock), using the main clock as the operating clock while suspending the PLL clock (VCO oscillation clock). • PLL sleep mode/Main sleep mode These modes stop only the operation clock of the CPU, leaving the other clocks active. • Watch mode The watch mode allows only the time-base timer to operate. • Stop mode/Hardware standby mode These modes stop oscillation while retaining data at the lowest power consumption. The CPU intermittent operation function causes the clock supplied to the CPU to operate intermittently when the CPU accesses a register, internal memory, internal resource, or external bus. This function saves power consumption by decreasing the execution speed of the CPU while providing high-speed clock signals to the internal resources. The PLL clock multiplication factor can be selected from among 1, 2, 3, and 4 using the CS1 and CS0 bits in the clock selection register. The WS1 and WS0 bits can be used to set the oscillation settling time for the main clock, which is taken to wake up from the stop or hardware standby mode. (1) Register configuration • Low-power consumption mode control register bit Address : 0000A0H Access Initial value • Clock selection register 7 (W) (0) 6 5 4 3 2 1 0 ⎯ LPMCR STP SLP SPL RST TMD CG1 CG0 (W) (R/W) (W) (0) (0) (1) (⎯) (R/W) (R/W) (⎯) (1) (0) (0) (⎯) bit Address : 0000A1H Access Initial value 15 (R) (1) 14 13 12 11 10 9 8 CKSCR SCM MCM WS1 WS0 SCS MCS CS1 CS0 (R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (1) (1) (1) (1) (1) (0) (0) DS07-13710-7E 77 MB90580C Series (2) Block Diagram CKSCR SCM SCS CKSCR MCM MCS CKSCR Sub clock switching controller Sub clock (OSC oscillation) PLL multiplication circuit 1 2 3 4 Main clock (OSC oscillation) CPU clock generation 1/2 S F2MC-16LX bus CPU clock CS1 CS0 LPMCR CG1 CG0 CPU clock selector 0/9/17/33 intermittent cycle selection CPU intermittent operation cycle selector Peripheral clock generation SLEEP Peripheral clock LPMCR SLP STP TMD SCM Standby control circuit RST MSTP STOP Main OSC stop Sub OSC stop Cancel HST Start HST pin Interrupt request or RST CKSCR WS1 WS0 LPMCR SPL Oscillation stability waiting time selector 210 213 215 218 Clock input Timebase timer 212 214 216 219 Pin hi-impedance control circuit Internal reset generation signal circuit Pin Hi-Z LPMCR RST RST pin Internal RST To watchdog timer WDGRST 78 DS07-13710-7E MB90580C Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = AVSS = 0.0 V) Parameter Symbol VCC Power supply voltage AVCC AVRH, AVRL DVCC Input voltage Output voltage Maximum clamp current Total maximum clamp current “L” level maximum output current “L” level average output current “L” level total maximum output current “L” level total average output current “H” level maximum output current “H” level average output current “H” level total maximum output current “H” level total average output current Power consumption Operating temperature Storage temperature VI VO ICLAMP Σ | ICLAMP | IOL IOLAV ΣIOL ΣIOLAV IOH IOHAV ΣIOH ΣIOHAV PD TA Tstg Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 − 2.0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ −40 −55 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 + 2.0 20 15 4 100 50 −15 −4 −100 −50 300 +85 +150 Unit V V V V V V mA mA mA mA mA mA mA mA mA mA mW °C °C Average output current = operating current × operating efficiency Average output current = operating current × operating efficiency *3 Average output current = operating current × operating efficiency VCC ≥ AVCC *1 AVCC ≥ AVRH/L, AVRH ≥ AVRL VCC ≥ DVCC *2 *2 *4 *4 *3 Average output current = operating current × operating efficiency Remarks *1 : Care must be taken that AVCC, AVRH, AVRL, DVCC do not exceed VCC. Also, care must be taken that AVRH, AVRL do not exceed AVCC, and AVRL does not exceed AVRH. *2 : VI and VO shall never exceed VCC + 0.3 V. *3 : The maximum output current is a peak value for a corresponding pin. *4 : • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P60 to P65, P71, P72, P80 to P87, P90 to P97, PA0 to PA2, RX • Use within recommended operating conditions. • Use at DC voltage (current) • The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller. (Continued) DS07-13710-7E 79 MB90580C Series (Continued) • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pins does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. • Care must be taken not to leave the +B input pin open. • Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. • Sample recommended circuits • Input/Output equivalent circuits Protective diode VCC Limiting resistance +B input (0 V to 16 V) P-ch N-ch R WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 80 DS07-13710-7E MB90580C Series 2. Recommended Operating Conditions (VSS = AVSS = 0.0 V) Parameter Symbol Value Min 3.0 Power supply voltage VCC 4.5 VCC VIH “H” level input voltage VIHS VIHM VIL “L” level input voltage VILS VILM Smoothing capacitor Operating temperature 3.0 0.7 VCC 0.8 VCC VCC − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 0.1 5.5 5.5 VCC+0.3 VCC+0.3 VCC+0.3 0.3 VCC 0.2 VCC VSS+0.3 1.0 V V V V V V V V μF Max 5.5 Unit V Remarks Normal operation (MB90583C/CA, MB90587C/CA, MB90V580B) Normal operation (MB90F583C/CA, MB90F584C/CA) Retains status at the time of operation stop CMOS input pin CMOS hysteresis input pin MD pin input CMOS input pin CMOS hysteresis input pin MD pin input Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be connected to the VCC pin must have a capacitance value higher than CS. CS TA −40 +85 °C • C pin connection circuit C CS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. DS07-13710-7E 81 MB90580C Series 3. DC Characteristics Parameter “H” level output voltage “L” level output voltage Input leakage current Symbol VOH VOL IIL Pin name (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Condition Unit Remarks Min Typ Max VCC − 0.5 ⎯ −5 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 27 40 22 35 ⎯ 0.4 5 33 50 26 45 V V μA mA mA MB90583C/CA, MB90587C/CA MB90F583C/CA, MB90F584C/CA All output VCC = 4.5 V, pins IOH = −2.0 mA All output VCC = 4.5 V, pins IOL = 2.0 mA All input pins VCC = 5.5 V, VSS < VI< VCC VCC = 5.0 V, Internal operation at 16 MHz, Normal operation VCC = 5.0 V, Internal operation at 12.58 MHz, Normal operation mA MB90583C/CA mA MB90F583C/CA, MB90F584C/CA ICC VCC = 5.0 V, Internal operation at 16 MHz, When data written in flash mode programming of erasing VCC = 5.0 V, Internal operation at 12.58 MHz, When data written in flash mode programming of erasing VCC = 5.0 V, Internal operation at 16 MHz, In sleep mode ⎯ 45 60 mA MB90F583C/CA, MB90F584C/CA Power supply current* VCC ⎯ 40 50 mA ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 7 15 6 12 12 20 10 18 mA MB90587C/CA MB90583C/CA, mA MB90F583C/CA, MB90F584C/CA mA MB90587C/CA MB90583C/CA, mA MB90F583C/CA, MB90F584C/CA mA MB90583C, MB90587C ICCS VCC = 5.0 V Internal operation at 12.58 MHz, In sleep mode VCC = 5.0 V, Internal operation at 8 kHz, Subsystem operation, TA = 25 °C 0.1 4 1.0 7 ICCL mA MB90F583C/F584C (Continued) 82 DS07-13710-7E MB90580C Series (Continued) Parameter Symbol Pin name (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Condition Unit Remarks Min Typ Max VCC = 5.0 V, Internal operation at 8 kHz, In subsleep mode, TA = 25 °C VCC VCC = 5.0 V, Internal operation at 8 kHz, In clock mode, TA = 25 °C In stop mode, TA = 25 °C Except AVCC, AVSS, C, VCC and VSS P40 to P47 P00 to P07 P10 to P17 P60 to P65 RST MD2 MB90583C, MB90587C, MB90F583C/F584C ICCLS ⎯ 30 50 μA Power supply current* ICCT ⎯ 15 30 μA MB90583C, MB90587C, MB90F583C/F584C MB90583C/CA MB90587C/CA, MB90F583C/CA, MB90F584C/CA ICCH ⎯ 5 20 μA Input capacitance Open-drain output leakage current Pull-up resistance Pull-down resistance CIN ⎯ ⎯ 10 80 pF Ileak ⎯ ⎯ 0.1 5 μA Open-drain output setting RUP ⎯ 25 50 100 kΩ RDOWN ⎯ 25 50 100 kΩ *: The current value is preliminary value and may be subject to change for enhanced characteristics without previous notice. The power supply current is measured with an external clock. DS07-13710-7E 83 MB90580C Series 4. AC Characteristics (1) Clock Timings Parameter (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value CondiSymbol Pin name Unit Remarks tion Min Typ Max Not multiplied, 3 ⎯ 16 when using oscillation circuit. PLL multiplied 1, 8 ⎯ 16 when using oscillation circuit. PLL multiplied 2, X0, X1 4 ⎯ 8 MHz when using oscillation fC circuit. PLL multiplied 3, 3 ⎯ 5.3 when using oscillation circuit. PLL multiplied 4, 3 ⎯ 4 when using oscillation ⎯ circuit. X0A, X1A ⎯ 32.768 ⎯ kHz fCL tHCYL X0, X1 62.5 ⎯ 333 ns tLCYL X0A, X1A ⎯ 30.5 ⎯ μs PWH X0 10 ⎯ ⎯ ns PWL Recommended duty ratio of 30% to 70% PWLH X0A ⎯ 15.2 ⎯ μs PWLL External clock tCR X0 ⎯ ⎯ 5 ns operation tCF fCP ⎯ 1.0 ⎯ 16 MHz Main clock operation fLCP ⎯ ⎯ 8.192 ⎯ kHz Sub clock operation tCP ⎯ 62.5 — 666 ns Main clock operation tLCP ⎯ ⎯ 122.1 ⎯ μs Sub clock operation Clock frequency Clock cycle time Input clock pulse width Input clock rise/fall time Internal operating clock frequency Internal operating clock cycle time • X0, X1 clock timing tHCYL X0 PWH tCF PWL tCR 0.8 VCC 0.2 VCC • X0A, X1A clock timing tLCYL 0.8 VCC 0.2 VCC PWLH tCF PWLL tCR X0A 84 DS07-13710-7E MB90580C Series • PLL operation guarantee range Relationship between internal operating clock frequency and power supply voltage Power supply voltage VCC (V) Operation guarantee range of MB90F583C/CA, MB90F584C/CA 5.5 4.5 3.3 3.0 Operation guarantee range of MB90583C/CA, MB90587C/CA, MB90V580B 1.5 3 8 12 Operation guarantee range of PLL 16 Internal clock fCP (MHz) Relationship between oscillating frequency and internal operating clock frequency Multiplied- Multiplied- Multipliedby-3 by-4 by-2 Multipliedby-1 16 Internal clock fCP (MHz) 12 9 8 Not multiplied 4 3 4 8 16 Oscillation clock fC (MHz) The AC ratings are measured for the following measurement reference voltages • Input signal waveform • Output signal waveform Hystheresis input pin 0.8 VCC 0.2 VCC Output pin 2.4 V 0.8 V Pins other than hystheresis input/MD input 0.7 VCC 0.3 VCC DS07-13710-7E 85 MB90580C Series (2) Clock Output Timings (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Condition Unit Remarks Min Max VCC = 5 V ± 10% 62.5 20 ⎯ ⎯ ns ns Parameter Clock cycle time CLK↑ → CLK↓ Symbol tCYC tCHCL Pin name CLK tCYC tCHCL 2.4 V 2.4 V 0.8 V CLK (3) Reset, Hardware Standby Input Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin name Condition Unit Remarks Min Max RST HST ⎯ 4 tCP 4 tCP ⎯ ⎯ ns ns Parameter Reset input time Hardware standby input time Symbol tRSTL tHSTL tRSTL, tHSTL RST HST 0.2 VCC 0.2 VCC 86 DS07-13710-7E MB90580C Series (4) Power-on Reset (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Symbol Pin name Condition Unit Remarks Min Max tR tOFF VCC VCC ⎯ 0.05 4 30 ⎯ ms ms Wait time until power-on Parameter Power supply rising time Power supply cut-off time * : VCC must be kept lower than 0.2 V before power-on. Note: The above values are used for causing a power-on reset. If HST = “L”, be sure to turn the power supply on using the above values to cause a power-on reset whether or not the power-on reset is required. Some registers in the device are initialized only upon a power-on reset. To initialize these registers, turn the power supply using the above values. tR VCC 2.7 V 0.2 V 0.2 V tOFF 0.2 V Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 V or fewer per second, however, you can use the PLL clock. VCC 3.0 V VSS RAM data hold It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower. DS07-13710-7E 87 MB90580C Series (5) Bus Timing (Read) (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin name Condition Unit Remarks Min Max ALE ALE, A23 to A16, AD15 to AD00 ALE, AD15 to AD00 A23 to A16, AD15 to AD00, RD A23 to A16, AD15 to AD00 RD RD, AD15 to AD00 RD, AD15 to AD00 RD, ALE ALE, A23 to A16 A23 to A16, AD15 to AD00, CLK RD, CLK ALE, RD ⎯ tCP/2 − 20 tCP/2 − 20 tCP/2 − 15 tCP − 15 ⎯ 3 tCP/2 − 20 ⎯ 0 tCP/2 − 15 tCP/2 − 10 tCP/2 − 20 tCP/2 − 20 tCP/2 − 15 ⎯ ⎯ ⎯ ⎯ 5 tCP/2 − 60 ⎯ 3 tCP/2 − 60 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter ALE pulse width Effective address → ALE ↓ time ALE ↓ → address effective time Effective address → RD ↓ time Effective address → valid data input RD pulse width RD ↓ → valid data input RD ↑ → data hold time RD ↑ → ALE ↑ time RD ↑ → address effective time Effective address → CLK ↑ time RD ↓ → CLK ↑ time ALE ↓ → RD ↓ time Symbol tLHLL tAVLL tLLAX tAVRL tAVDV tRLRH tRLDV tRHDX tRHLH tRHAX tAVCH tRLCH tLLRL 88 DS07-13710-7E MB90580C Series • Bus Timing (Read) tAVCH 2.4 V tRLCH 2.4 V CLK tRHLH 2.4 V 2.4 V tLHLL 0.8 V tRLRH 2.4 V ALE RD 2.4 V tAVLL tLLAX tLLRL tAVRL 2.4 V tRLDV tRHAX 2.4 V 0.8 V tAVDV tRHDX 0.8 VCC 0.8 VCC 0.8 V A23 to A16 0.8 V AD15 to AD00 2.4 V 2.4 V Address 0.8 V 0.8 V 0.2 VCC Read data 0.2 VCC DS07-13710-7E 89 MB90580C Series (6) Bus Timing (Write) (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin name Condition Unit Remarks Min Max A23 to A16, AD15 to AD00, WRH, WRL WRH, WRL AD15 to AD00, WRH, WRL WRH, WRL, AD15 to AD00 WRH, WRL, A23 to A16 ⎯ tCP − 15 3 tCP/2 − 20 3 tCP/2 − 20 20 tCP/2 − 10 tCP/2 − 15 tCP/2 − 20 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ns Parameter Effective address → WRH, WRL↓ time WRH, WRL pulse width Effective data output → WRH, WRL ↑ time WRH, WRL ↑ → data hold time WRH, WRL ↑ → address effective time WRH, WRL ↑ → ALE ↑ time WRH, WRL ↓ → CLK ↑ time Symbol tAVWL tWLWH ns tDVWH ns tWHDX ns tWHAX ns tWHLH tWLCH WRH, WRL, ALE WRH, WRL, CLK ns ns • Bus Timing (Write) tWLCH 2.4 V CLK tWHLH 2.4 V ALE tWLWH WRH, WRL 0.8 V 2.4 V tAVWL 2.4 V tWHAX 2.4 V 0.8 V tDVWH tWHDX 2.4 V A23 to A16 0.8 V AD15 to AD00 2.4 V 2.4 V Address 0.8 V 0.8 V Write data 0.8 V 90 DS07-13710-7E MB90580C Series (7) Ready Input Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin name Condition Unit Remarks Min Max RDY ⎯ ⎯ 45 0 ⎯ ⎯ ns ns Parameter RDY setup time RDY hold time Symbol tRYHS tRYHH Note: Use the automatic ready function when the setup time for the rising edge of the RDY signal is not sufficient. 2.4 V 2.4 V CLK ALE RD/ WRH/ WRL tRYHS tRYHS RDY (wait inserted) RDY (wait not inserted) 0.2 VCC 0.2 VCC 0.8 VCC 0.8 VCC tRYHH DS07-13710-7E 91 MB90580C Series (8) Hold Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin name Condition Unit Remarks Min Max HAK HAK ⎯ 30 tCP tCP 2 tCP ns ns Parameter Pins in floating status → HAK ↓ time HAK ↑ → pin valid time Symbol tXHAL tHAHV Note: More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched. HAK 0.8 V tXHAL 2.4 V tHAHV 2.4 V Pins 2.4 V 0.8 V High impedance 0.8 V 92 DS07-13710-7E MB90580C Series (9) UART0 to UART4 (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin name Condition Unit Remarks Min Max SCK0 to SCK4 SCK0 to SCK4, SOT0 to SOT4 CL = 80 pF + 1 TTL for an output pin of SCK0 to SCK4, internal shift clock SIN0 to SIN4 mode SCK0 to SCK4, SIN0 to SIN4 SCK0 to SCK4 SCK0 to SCK4 SCK0 to SCK4, CL = 80 pF + 1 TTL SOT0 to SOT4 for an output pin of external shift clock SCK0 to SCK4, mode SIN0 to SIN4 SCK0 to SCK4, SIN0 to SIN4 8 tCP −80 100 60 4 tCP 4 tCP ⎯ 60 60 ⎯ 80 ⎯ ⎯ ⎯ ⎯ 150 ⎯ ⎯ ns ns ns ns ns ns ns ns ns Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Notes : • These are AC ratings in the CLK synchronous mode. • CL is the load capacitance value connected to pins while testing. • tCP is machine cycle time (unit: ns). DS07-13710-7E 93 MB90580C Series • Internal shift clock mode tSCYC 2.4 V 0.8 V tSLOV 2.4 V 0.8 V SCK SOT 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC SIN 0.2 VCC • External shift clock mode SCK 0.2 VCC tSLOV tSLSH 0.2 VCC tSHSL 0.8 VCC 0.8 VCC 2.4 V SOT 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC SIN 0.2 VCC 94 DS07-13710-7E MB90580C Series (10)Timer Input Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin name Condition Unit Remarks Min Max IN0 to IN3, TIN0 to TIN2 ⎯ 4 tCP ⎯ ns Parameter Input pulse width Symbol tTIWH tTIWL 0.8 VCC 0.8 VCC 0.2 VCC tTIWH tTIWL 0.2 VCC (11) Timer Output Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin name Condition Unit Remarks Min Max OUT0, OUT1, PPG0, PPG1, TOT0 to TOT2 ⎯ 30 ⎯ ns Parameter Symbol CLK↑→TOUT transition time tTO CLK 2.4 V tTO 2.4 V TOUT 0.8 V DS07-13710-7E 95 MB90580C Series (12) Trigger Input Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin name Condition Unit Remarks Min Max IRQ0 to IRQ7, ADTG ⎯ 5 tCP ⎯ ns Parameter Input pulse width Symbol tTRGH tTRGL 0.8 VCC 0.8 VCC 0.2 VCC tTRGH tTRGL 0.2 VCC 96 DS07-13710-7E MB90580C Series (13) IEBusTM Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin name Condition Unit Remarks Min Max TX, RX TX, RX ⎯ 0 0 1000 1000 ns ns Parameter TX → RX delay time (rise) TX → RX delay time (fall) Symbol tDLY1 tDLY2 TX 0.7 VCC 0.3 VCC tDLY1 RX 0.7 VCC 0.3 VCC tDLY2 MB90580C series TX RX Driver/ receiver TX RX BUS+ BUS− IEBusTM DS07-13710-7E 97 MB90580C Series 5. A/D Converter Electrical Characteristics (3.0 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Symbol Pin name Unit Remarks Parameter Min Typ Max Resolution Total error Non-linear error Differential linearity error Zero transition voltage Full-scale transition voltage Compare time Sampling period Analog port input current Analog input voltage Reference voltage ⎯ ⎯ ⎯ ⎯ VOT VFST ⎯ ⎯ IAIN VAIN ⎯ ⎯ Power supply current Reference voltage supply current Offset between channels IA IAH IR IRH — ⎯ ⎯ ⎯ ⎯ AN0 to AN7 AN0 to AN7 ⎯ ⎯ AN0 to AN7 AN0 to AN7 AVRH AVRL AVCC AVCC AVRH AVRH AN0 to AN7 ⎯ ⎯ ⎯ ⎯ AVRL − 3.5 LSB AVRH − 6.5 LSB 352 tCP 64 tCP ⎯ AVRL AVRL + 3.0 0 ⎯ ⎯ ⎯ ⎯ ⎯ 10 ⎯ ⎯ ⎯ AVRL + 0.5 LSB AVRH − 1.5 LSB ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 5 ⎯ 400 ⎯ ⎯ ⎯ ±5.0 ±2.5 ±1.9 AVRL + 4.5 LSB AVRH + 1.5 LSB ⎯ ⎯ 10 AVRH AVCC AVRH − 3.0 ⎯ 5 ⎯ 5 4 bit LSB LSB LSB V V ns ns μA V V V mA μA μA μA LSB * * 1 LSB = (AVRH - AVRL)/ 1024 At machine clock = 16 MHZ At machine clock = 16 MHZ * : The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVRH = 5.0 V) Note: • The error increases proportionally as |AVRH - AVRL| decreases. •The output impedance of the external circuits connected to the analog inputs should be in the following range. •The output impedance of the external circuit : 15.5 kΩ (Max) (Sampling time = 4.0 μs) •If the output impedance of the external circuit is too high, the sampling time might be insufficient. C0 Comparator Analog input C1 98 DS07-13710-7E MB90580C Series 6. A/D Converter Glossary Resolution: Analog changes that are identifiable with the A/D converter Linearity error: The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error: The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error. Total error 3FF 3FE 3FD Actual conversion value 0.5 LSB Digital output {1 LSB × (N − 1) + 0.5 LSB} 004 003 002 001 AVRL (Measured value) Actual conversion value Theoretical characteristics 0.5 LSB AVRH VNT Analog input VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB AVRH − AVRL [V] 1024 Total error for digital output N = 1 LSB = (Theoretical value) [LSB] VOT(Theoretical value) = AVRL + 0.5 LSB [V] VFST(Theoretical value) = AVRH − 1.5 LSB [V] VNT : Voltage at a transition of digital output from (N - 1) to N (Continued) DS07-13710-7E 99 MB90580C Series (Continued) Linearity error 3FF 3FE 3FD Differential linearity error Theoretical characteristics N+1 VFST (Measured value) Actual conversion value {1 LSB × (N − 1) + VOT } Actual conversion value Digital output Digital output N 004 003 002 001 AVRL (measured value) Actual conversion value VNT V(N + 1)T N−1 VNT (Measured value) (Measured value) Actual conversion value AVRH Theoretical characteristics (Measured value) VOT AVRH N−2 AVRL Analog input Linearity error of = digital output N Analog input VNT − {1 LSB × (N − 1) + VOT} 1 LSB − 1 LSB[LSB] [V] [LSB] Differential linearity error V (N + 1) T − VNT = 1 LSB of digital output N 1 LSB = VFST − VOT 1022 VOT : Voltage at transition of digital output from “000H” to “001H” VFST : Voltage at transition of digital output from “3FEH” to “3FFH” 100 DS07-13710-7E MB90580C Series 7. Notes on Using A/D Converter Select the output impedance value for the external circuit of analog input according to the following conditions. Output impedance values of the external circuit of 15.5 kΩ or lower are recommended. When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient (sampling period = 4.00 μs @machine clock of 16 MHz) • Equipment of analog input circuit model Analog input C0 Comparator C1 MB90587C/CA, MB90V580B R ≅ 1.5 kΩ, C ≅ 30 pF MB90F583C/CA, MB90F584C/CA R ≅ 3.0 kΩ, C ≅ 65 pF MB90583C/CA R ≅ 2.2 kΩ, C ≅ 45 pF Note: Listed values must be considered as standards. • Error The smaller the | AVRH - AVRL |, the greater the error would become relatively. 8. D/A Converter Electrical Characteristics (VCC = AVCC = 5.0 V±10%, VSS = AVSS = DVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Resolution Differential linearity error Absolute accuracy Linearity error Conversion time Analog reference voltage Reference voltage supply current Analog output impedance *1 : Load capacitance: 20 pF *2 : In sleep mode Symbol Pin name ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ IDVR IDVRS ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DVRH DVRH ⎯ Value Min ⎯ ⎯ ⎯ ⎯ ⎯ VSS + 3.0 ⎯ ⎯ ⎯ Typ 8 ⎯ ⎯ ⎯ 10 ⎯ 120 ⎯ 20 Max ⎯ ±0.9 ±1.2 ±1.5 20 AVCC 300 10 ⎯ Unit bit LSB % LSB μs V μA μA kΩ *2 *1 Remarks DS07-13710-7E 101 MB90580C Series 9. Flash Memory Program/Erase Characteristics Parameter Sector erase time Chip erase time Word (16 bit width) programming time Erase/Program cycle ⎯ TA = + 25 °C VCC = 3.0 V Condition Value Min ⎯ ⎯ ⎯ 10,000 Typ 1 7 16 ⎯ Max 15 ⎯ 3,600 Unit s s μs cycle Remarks Excludes 00H programming prior erasure Excludes 00H programming prior erasure Excludes system-level overhead 102 DS07-13710-7E MB90580C Series ■ EXAMPLE CHARACTERISTICS • Power Suppy Current of MB90F583C/CA ICC vs. VCC TA = 25 °C, external clock input 45 40 35 ICCS (mA) 20 ICCS vs. VCC TA = 25 °C, external clock input f = 16 MHz 15 f = 16 MHz f = 12 MHz 10 f = 10 MHz f = 8 MHz 5 f = 4 MHz f = 2 MHz 0 2 3 4 VCC (V) 5 6 30 ICC (mA) f = 12 MHz f = 10 MHz f = 8 MHz 25 20 15 f = 4 MHz 10 f = 2 MHz 5 0 2 3 4 VCC (V) 5 6 ICCL vs. VCC TA = 25 °C, external clock input (MB90F583C only) ICCLS vs. VCC TA = 25 °C, external clock input (MB90F583C only) 500 450 400 350 ICCL (μA) 300 250 200 150 100 50 0 2 3 4 VCC (V) 5 6 f = 8 kHz ICCLS (μA) 50 45 40 35 30 25 20 15 10 5 0 2 3 4 VCC (V) 5 6 f = 8 kHz (Continued) DS07-13710-7E 103 MB90580C Series (Continued) ICCT vs. VCC TA = 25 °C, external clock input (MB90F583C only) 30 28 26 24 22 20 28 16 14 12 10 8 6 4 2 0 2 3 4 VCC (V) 5 f = 8 kHz ICCT (μA) 6 VOH vs. IOH TA = 25 °C, VCC = 4.5 V 1000 900 800 700 VCC - VOH (mV) 600 500 400 300 200 100 0 0 1 2 34 5 6 7 8 9 10 11 12 VOL (V) 1000 900 800 700 600 500 400 300 200 100 0 0 VOL vs. IOL TA = 25 °C, VCC = 4.5 V 12 34 5 6 78 9 10 11 12 IOH (mA) IOL (mA) 104 DS07-13710-7E MB90580C Series Power Supply Current of MB90583C/CA ICC vs. VCC TA = 25 °C, external clock input 30 f = 16 MHz 20 ICCS vs. VCC TA = 25 °C, external clock input 25 f = 12 MHz 20 ICC (mA) ICCS (mA) f = 10 MHz f = 8 MHz 15 f = 16 MHz f = 12 MHz 10 f = 10 MHz f = 8 MHz 5 f = 4 MHz 5 f = 2 MHz 0 2 0 2 3 4 VCC (V) 5 6 3 4 VCC (V) 5 6 f = 4 MHz f = 2 MHz 15 10 ICCL vs. VCC TA = 25 °C, external clock input (MB90583C only) 70 60 50 40 30 20 10 0 ICCLS (μA) ICCL (μA) f = 8 kHz 50 45 40 35 30 25 20 15 10 5 0 2 2 3 4 VCC (V) 5 6 ICCLS vs. VCC TA = 25 °C, external clock input (MB90583C only) f = 8 kHz 3 4 VCC (V) 5 6 (Continued) DS07-13710-7E 105 MB90580C Series (Continued) ICCT vs. VCC TA = 25 °C, external clock input (MB90583C only) 30 28 26 24 22 20 28 16 14 12 10 8 6 4 2 0 2 3 4 VCC (V) 5 f = 8 kHz ICCT (μA) 6 VOH vs. IOH TA = 25 °C, VCC = 4.5 V 1000 900 800 700 VOL (V) 600 VCC - VOH (mV) 500 400 300 200 100 0 0 1 2 34 56 7 8 9 10 11 12 1000 900 800 700 600 500 400 300 200 100 0 0 1 VOL vs. IOL TA = 25 °C, VCC = 4.5 V 2 3 4 5 6 7 8 9 10 11 12 IOH (mA) IOL (mA) 106 DS07-13710-7E MB90580C Series ■ ORDERING INFORMATION Part number MB90F583CPMC MB90F583CAPMC MB90583CPMC MB90583CAPMC MB90F584CPMC MB90F584CAPMC MB90587CPMC MB90587CAPMC MB90F583CPF MB90F583CAPF MB90583CPF MB90583CAPF MB90F584CPF MB90F584CAPF MB90587CPF MB90587CAPF Package Remarks 100-pin Plastic LQFP (FPT-100P-M20) 100-pin Plastic QFP (FPT-100P-M06) DS07-13710-7E 107 MB90580C Series ■ PACKAGE DIMENSIONS 100-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.50 mm 14.0 mm × 14.0 mm Gullwing Plastic mold 1.70 mm Max 0.65 g P-LFQFP100-14×14-0.50 (FPT-100P-M20) Code (Reference) 100-pin plastic LQFP (FPT-100P-M20) 16.00±0.20(.630±.008)SQ Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. * 14.00±0.10(.551±.004)SQ 75 51 76 50 0.08(.003) Details of "A" part INDEX 1.50 –0.10 .059 –.004 (Mounting height) 26 +0.20 +.008 100 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) 0˚~8˚ "A" (0.50(.020)) 0.60±0.15 (.024±.006) 1 25 0.50(.020) 0.20±0.05 (.008±.002) 0.08(.003) M 0.145±0.055 (.0057±.0022) ©2005-2008 FUJITSU MICROELECTRONICS LIMITED F100031S-c-2-2 C 2005 FUJITSU LIMITED F100031S-c-2-1 Dimensions in mm (inches). Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 108 DS07-13710-7E MB90580C Series (Continued) 100-pin plastic QFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Code (Reference) 0.65 mm 14.00 × 20.00 mm Gullwing Plastic mold 3.35 mm MAX P-QFP100-14×20-0.65 (FPT-100P-M06) 100-pin plastic QFP (FPT-100P-M06) 23.90±0.40(.941±.016) * 20.00±0.20(.787±.008) 80 51 Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 81 50 0.10(.004) 17.90±0.40 (.705±.016) *14.00±0.20 (.551±.008) INDEX Details of "A" part 100 31 1 30 0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8˚ 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.25±0.20 (.010±.008) (Stand off) 0.65(.026) 0.32±0.05 (.013±.002) 0.13(.005) M "A" ©2002-2008 FUJITSU MICROELECTRONICS LIMITED F100008S-c-5-6 C 2002 FUJITSU LIMITED F100008S-c-5-5 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ DS07-13710-7E 109 MB90580C Series ■ MAIN CHANGES IN THIS EDITION Page 79 Section ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings ■ ELECTRICAL CHARACTERISTICS 4. AC Characteristics→ (1) Clock Timings Change Results Corrected the *4. P71 to P74 → P71, P72 Changed the row of “Clock frequency”. Deleted the row of “Frequency fluctuation rate locked*”. Corrected the minimum value of “Internal operating clock frequency”. 1.5 → 1.0 Deleted “*: The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied PLL signal is locked.” and the figure. ■ ELECTRICAL CHARACTERISTICS 4. AC Characteristics (1) Clock Timings • PLL operation guarantee range ■ ELECTRICAL CHARACTERISTICS 4. AC Characteristics (4) Power-on Reset Corrected the figure of “Relationship between internal operating clock frequency and power supply voltage”. 84 85 87 Corrected the Remarks column of “Power supply cut-off time”. Due to repeated operations → Wait time until power-on The vertical lines marked in the left side of the page show the changes. 110 DS07-13710-7E MB90580C Series MEMO DS07-13710-7E 111 MB90580C Series FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. 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Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department