MB90F867E

FUJITSU SEMICONDUCTOR DATA SHEET DS07-13748-1E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90860E Series MB90867E(S), MB90F867E(S), MB90V340E-101/102 ■ DESCRIPTION MB90860E-series with Flash ROM is especially designed for automotive and other industrial applications. With the new 0.35 µm CMOS technology, Fujitsu now offers on-chip Flash ROM program memory up to 512 Kbytes. The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates a major advantage in terms of EMI and power consumption. The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external 4 MHz clock. The unit features an 8 channel Output Compare Unit and 8 channel Input Capture Unit with 2 separate 16-bit free running timers. 4 UARTs constitute additional functionality for communication purposes. Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller. Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development. Copyright©2006 FUJITSU LIMITED All rights reserved MB90860E Series ■ FEATURES • CPU • Instruction system best suited to controller • Wide choice of data types (bit, byte, word, and long word) • Wide choice of addressing modes(23 types) • Enhanced multiply-divide instructions and RETI instructions • Enhanced high-precision computing with 32-bit accumulator • Instruction system compatible with high-level language (C language) and multitask • Employing system stack pointer • Enhanced various pointer indirect instructions • Barrel shift instructions • Increased processing speed • 4-byte instruction queue • Serial interface • UART (LIN/SCI) : up to 4 channels • Equipped with full-duplex double buffer • Clock-asynchronous or clock-synchronous serial transmission is available • I2C interface* : up to 2 channels • Up to 400 Kbits/s transfer rate • Interrupt controller • Powerful interrupt function • Powerful 8-level, 34-condition interrupt feature • Up to 16 external interrupts are supported • Automatic data transfer function independent of CPU • Expanded intelligent I/O service function (EI2OS) : up to 16 channels • I/O port • General-purpose input/output port (CMOS output) - 80 ports (devices without S-suffix) - 82 ports (devices with S-suffix) • 8/10-bit A/D converter • 8/10-bit A/D converter : 24 channels • Resolution is selectable between 8-bit and 10-bit. • Activation by external trigger input is allowed. • Conversion time : 3 µs (at 24-MHz machine clock, including sampling time) • Program patch function • Timer • Time-base timer, clock timer, watchdog timer : 1 channel • 8/16-bit PPG timer : 8-bit × 16 channels, or 16-bit × 8 channels • 16-bit reload timer : 4 channels • 16-bit input/output timer - 16-bit free run timer : 2 channel (FRT0 : ICU 0/1/2/3, OCU 0/1/2/3, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7) - 16-bit input capture: (ICU) : 8 channels - 16-bit output compare : (OCU) : 8 channels 2 MB90860E Series • Variety of mode • Low power consumption (standby) mode • Sleep mode (a mode that halts CPU operating clock) • Main timer mode (time-base timer mode that is transferred from main clock mode) • PLL timer mode (time-base timer mode that is transferred from PLL clock mode) • Watch mode (a mode that operates sub clock and clock timer only) • Stop mode (a mode that stops oscillation clock and sub clock) • CPU blocking operation mode • Technology • 0.35 µm CMOS technology * : I2C license : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. 3 MB90860E Series ■ PRODUCT LINEUP Part Number MB90867E(S) Parameter CPU Type System clock ROM RAM Emulator-specific power supply*1 MASK ROM product F2MC-16LX CPU Flash memory product Evaluation product On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops) Minimum instruction execution time : 42 ns (4 MHz osc. PLL × 6) MASK ROM 128 Kbytes 6 Kbytes ⎯ Flash memory 128 Kbytes 6 Kbytes External 30 Kbytes Yes MB90F867E(S) MB90V340E-101/102 Technology 0.35 µm CMOS with on-chip 0.35 µm CMOS with on-chip voltage regulator for internal 0.35 µm CMOS with on-chip voltage regulator for internal power supply + Flash memory voltage regulator for internal power supply with on-chip charge pump for power supply programming voltage 3.5 V to 5.5 V : at normal operating (not using A/D converter) 4.0 V to 5.5 V : at using A/D converter/Flash programming 4.5 V to 5.5 V : at using external bus −40 °C to +105 °C QFP-100, LQFP-100 4 channels 5 V ± 10% ⎯ PGA-299 5 channels Operating voltage range Temperature range Package UART Wide range of baud rate settings using a dedicated reload timer Special synchronous options for adapting to different synchronous serial protocols LIN functionality working either as master or slave LIN device 2 channels 24 channels 10-bit or 8-bit resolution Conversion time : Min 3 µs include sample time (per one channel) Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency) Supports External Event Count function Signals an interrupt when overflowing Supports Timer Clear when a match with Output Compare (ch.0, ch.4) Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27 (fsys = Machine clock freq.) I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1/2/3, OCU 0/1/2/3 I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7 Signals an interrupt when 16-bit I/O Timer match output compare registers. A pair of compare registers can be used to generate an output signal. Rising edge, falling edge or rising & falling edge sensitive Signals an interrupt upon external event (Continued) I2C (400 kbps) 8/10-bit A/D converter 16-bit reload timer (4 channels) 16-bit I/O timer (2 channels) 16-bit output compare (8 channels) 16-bit input capture (8 channels) 4 MB90860E Series (Continued) Part Number MB90867E(S) Parameter Supports 8-bit and 16-bit operation modes Sixteen 8-bit reload counters 8/16-bit Sixteen 8-bit reload registers for L pulse width programmable pulse Sixteen 8-bit reload registers for H pulse width generator A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as (8 channels) 8-bit prescaler plus 8-bit reload counter Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz (fsys = Machine clock frequency, fosc = Oscillation clock frequency) CAN interface External interrupt (16 channels) D/A converter Up to 100 kHz sub clock for low power operation Devices without ‘S’-suffix ⎯ 3 channels Can be used rising edge, falling edge, starting up by H/L level input, external interrupt, expanded intelligent I/O services (EI2OS) and DMA ⎯ 2 channels Only for MB90V340E102 MB90F867E(S) MB90V340E-101/102 I/O ports Virtually all external pins can be used as general purpose I/O port All push-pull outputs Bit-wise settable as input/output or peripheral signal Settable in pin-wise of 8 as CMOS schmitt trigger/automotive inputs (default) TTL input level settable for external bus (32-pin only for external bus) Supports automatic programming, Embedded AlgorithmTM*2 Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of erase cycles : 10,000 times Data retention time : 20 years Boot block configuration Erase can be performed on each block Block protection with external programming voltage Flash Security Feature for protecting the content of the Flash Flash memory ⎯ *1 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the Emulator hardware manual about details. *2 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc. 5 MB90860E Series ■ PIN ASSIGNMENTS • MB90V340E-101/102 (TOP VIEW) P04/AD04/INT12 P05/AD05/INT13 P06/AD06/INT14 P07/AD07/INT15 P10/AD08/TIN1 P11/AD09/TOT1 P12/AD10/SIN3/INT11R P13/AD11/SOT3 P14/AD12/SCK3 Vcc Vss X1 X0 P15/AD13/SIN4 P16/AD14/SOT4 P17/AD15/SCK4 P20/A16/PPG9(8) P21/A17/PPGB(A) P22/A18/PPGD(C) P23/A19/PPGF(E) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 82 49 83 48 84 47 85 46 86 45 87 44 88 43 89 42 90 41 QFP - 100 91 40 92 39 93 38 94 37 95 36 96 35 97 34 98 33 99 32 100 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P24/A20/IN0 P25/A21/IN1 P26/A22/IN2 P27/A23/IN3 P30/ALE/IN4 P31/RD/IN5 P32/WRL/WR/RX2/INT10R P33/WRH/TX2 P34/HRQ/OUT4 P35/HAK/OUT5 P36/RDY/OUT6 P37/CLK/OUT7 P40/X0A* P41/X1A* Vcc Vss C P42/IN6/RX1/INT9R P43/IN7/TX1 P44/SDA0/FRCK0 P45/SCL0/FRCK1 P46/SDA1 P47/SCL1 P50/AN8/SIN2 P51/AN9/SOT2 P52/AN10/SCK2 P53/AN11/TIN3 P54/AN12/TOT3 P55/AN13 P56/AN14/DA00 P03/AD03/INT11 P02/AD02/INT10 P01/AD01/INT9 P00/AD00/INT8 PA1/TX0 PA0/RX0/INT8R P97/OUT3 P96/OUT2 P95/OUT1 P94/OUT0 P93/PPG7(6) P92/PPG5(4) P91/PPG3(2) P90/PPG1(0) Vss Vcc P87/SCK1 P86/SOT1 P85/SIN1 P84/SCK0/INT15R P83/SOT0/TOT2 P82/SIN0/TIN2/INT14R P81/TOT0/CKOT/INT13R P80/TIN0/ADTG/INT12R P77/AN23/INT7 P76/AN22/INT6 RST MD0 MD1 MD2 P75/AN21/INT5 P74/AN20/INT4 P73/AN19/INT3 P72/AN18/INT2 P71/AN17/INT1 P70/AN16/INT0 Vss P67/AN7/PPGE(F) P66/AN6/PPGC(D) P65/AN5/PPGA(B) P64/AN4/PPG8(9) P63/AN3/PPG6(7) P62/AN2/PPG4(5) P61/AN1/PPG2(3) P60/AN0/PPG0(1) AVss AVRL AVRH AVcc P57/AN15/DA01 (FPT-100P-M06) * : X0A, X1A : MB90V340E-102 P40, P41 : MB90V340E-101 (Continued) 6 MB90860E Series (Continued) (TOP VIEW) P81/TOT0/CKOT/INT13R P80/TIN0/ADTG/INT12R P77/AN23/INT7 P76/AN22/INT6 P00/AD00/INT8 PA1/TX0 PA0/RX0/INT8R P97/OUT3 P96/OUT2 P95/OUT1 P94/OUT0 P93/PPG7(6) P92/PPG5(4) P91/PPG3(2) P90/PPG1(0) Vss Vcc P87/SCK1 P86/SOT1 P85/SIN1 P84/SCK0/INT15R P83/SOT0/TOT2 P82/SIN0/TIN2/INT14R P01/AD01/INT9 P02/AD02/INT10 P03/AD03/INT11 P04/AD04/INT12 P05/AD05/INT13 P06/AD06/INT14 P07/AD07/INT15 P10/AD08/TIN1 P11/AD09/TOT1 P12/AD10/SIN3/INT11R P13/AD11/SOT3 P14/AD12/SCK3 Vcc Vss X1 X0 P15/AD13/SIN4 P16/AD14/SOT4 P17/AD15/SCK4 P20/A16/PPG9(8) P21/A17/PPGB(A) P22/A18/PPGD(C) P23/A19/PPGF(E) P24/A20/IN0 P25/A21/IN1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 50 77 49 78 48 47 79 46 80 45 81 44 82 43 83 42 84 41 85 40 86 39 87 38 88 LQFP - 100 37 89 36 90 35 91 34 92 33 93 32 94 31 95 30 96 29 97 98 28 99 27 100 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P36/RDY/OUT6 P37/CLK/OUT7 P40/X0A* P41/X1A* P26/A22/IN2 P27/A23/IN3 P30/ALE/IN4 P31/RD/IN5 P32/WRL/WR/RX2/INT10R P33/WRH/TX2 P34/HRQ/OUT4 P42/IN6/RX1/INT9R P43/IN7/TX1 P44/SDA0/FRCK0 P45/SCL0/FRCK1 P46/SDA1 P47/SCL1 P50/AN8/SIN2 P51/AN9/SOT2 P52/AN10/SCK2 P53/AN11/TIN3 P35/HAK/OUT5 Vcc Vss C RST MD0 MD1 MD2 P75/AN21/INT5 P74/AN20/INT4 P73/AN19/INT3 P72/AN18/INT2 P71/AN17/INT1 P70/AN16/INT0 Vss P67/AN7/PPGE(F) P66/AN6/PPGC(D) P65/AN5/PPGA(B) P64/AN4/PPG8(9) P63/AN3/PPG6(7) P62/AN2/PPG4(5) P61/AN1/PPG2(3) P60/AN0/PPG0(1) AVss AVRL AVRH AVcc P57/AN15/DA01 P56/AN14/DA00 P55/AN13 P54/AN12/TOT3 (FPT-100P-M05) * : X0A, X1A : MB90V340E-102 P40, P41 : MB90V340E-101 7 MB90860E Series • MB90867E(S)/MB90F867E(S) (TOP VIEW) P03/AD03/INT11 P02/AD02/INT10 P01/AD01/INT9 P00/AD00/INT8 PA1 PA0/INT8R P97/OUT3 P96/OUT2 P95/OUT1 P94/OUT0 P93/PPG7(6) P92/PPG5(4) P91/PPG3(2) P90/PPG1(0) Vss Vcc P87/SCK1 P86/SOT1 P85/SIN1 P84/SCK0/INT15R P83/SOT0/TOT2 P82/SIN0/TIN2/INT14R P81/TOT0/CKOT/INT13R P80/TIN0/ADTG/INT12R P77/AN23/INT7 P76/AN22/INT6 MD0 MD1 P04/AD04/INT12 P05/AD05/INT13 P06/AD06/INT14 P07/AD07/INT15 P10/AD08/TIN1 P11/AD09/TOT1 P12/AD10/SIN3/INT11R P13/AD11/SOT3 P14/AD12/SCK3 Vcc Vss X1 X0 P15/AD13 P16/AD14 P17/AD15 P20/A16/PPG9(8) P21/A17/PPGB(A) P22/A18/PPGD(C) P23/A19/PPGF(E) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 82 49 83 48 84 47 85 46 86 45 87 44 88 43 89 42 QFP - 100 90 41 91 40 92 39 93 38 94 37 95 36 96 35 97 34 98 33 99 32 100 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P31/RD/IN5 P32/WRL/WR/INT10R P33/WRH P34/HRQ/OUT4 P35/HAK/OUT5 P36/RDY/OUT6 P37/CLK/OUT7 P40/X0A* P41/X1A* Vcc Vss C P42/IN6/INT9R P43/IN7 P44/SDA0/FRCK0 P45/SCL0/FRCK1 P46/SDA1 P47/SCL1 P50/AN8/SIN2 P51/AN9/SOT2 P52/AN10/SCK2 P53/AN11/TIN3 P54/AN12/TOT3 P55/AN13 P56/AN14 P24/A20/IN0 P25/A21/IN1 P26/A22/IN2 P27/A23/IN3 P30/ALE/IN4 MD2 RST P75/AN21/INT5 P74/AN20/INT4 P73/AN19/INT3 P72/AN18/INT2 P71/AN17/INT1 P70/AN16/INT0 Vss P67/AN7/PPGE(F) P66/AN6/PPGC(D) P65/AN5/PPGA(B) P64/AN4/PPG8(9) P63/AN3/PPG6(7) P62/AN2/PPG4(5) P61/AN1/PPG2(3) P60/AN0/PPG0(1) AVss AVRL AVRH AVcc P57/AN15 (FPT-100P-M06) * : X0A, X1A : MB90867E, MB90F867E P40, P41 : MB90867ES/MB90F867ES (Continued) 8 MB90860E Series (Continued) (TOP VIEW) P81/TOT0/CKOT/INT13R P80/TIN0/ADTG/INT12R P77/AN23/INT7 P76/AN22/INT6 P00/AD00/INT8 PA1 PA0/INT8R P97/OUT3 P96/OUT2 P95/OUT1 P94/OUT0 P93/PPG7(6) P92/PPG5(4) P91/PPG3(2) P90/PPG1(0) Vss Vcc P87/SCK1 P86/SOT1 P85/SIN1 P84/SCK0/INT15R P83/SOT0/TOT2 P82/SIN0/TIN2/INT14R P01/AD01/INT9 P02/AD02/INT10 P03/AD03/INT11 P04/AD04/INT12 P05/AD05/INT13 P06/AD06/INT14 P07/AD07/INT15 P10/AD08/TIN1 P11/AD09/TOT1 P12/AD10/SIN3/INT11R P13/AD11/SOT3 P14/AD12/SCK3 Vcc Vss X1 X0 P15/AD13 P16/AD14 P17/AD15 P20/A16/PPG9(8) P21/A17/PPGB(A) P22/A18/PPGD(C) P23/A19/PPGF(E) P24/A20/IN0 P25/A21/IN1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 50 77 49 48 78 47 79 46 80 45 81 44 82 43 83 42 84 41 85 40 86 39 87 LQFP - 100 38 88 37 89 36 90 35 91 34 92 33 93 32 94 31 95 30 96 29 97 98 28 99 27 100 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P31/RD/IN5 P32/WRL/WR/INT10R P33/WRH P34/HRQ/OUT4 P35/HAK/OUT5 P36/RDY/OUT6 P37/CLK/OUT7 P40/X0A* P41/X1A* Vcc Vss C P42/IN6/INT9R P43/IN7 P44/SDA0/FRCK0 P45/SCL0/FRCK1 P46/SDA1 P47/SCL1 P50/AN8/SIN2 P51/AN9/SOT2 P52/AN10/SCK2 P53/AN11/TIN3 P26/A22/IN2 P27/A23/IN3 P30/ALE/IN4 MD0 RST MD1 MD2 P75/AN21/INT5 P74/AN20/INT4 P73/AN19/INT3 P72/AN18/INT2 P71/AN17/INT1 P70/AN16/INT0 Vss P67/AN7/PPGE(F) P66/AN6/PPGC(D) P65/AN5/PPGA(B) P64/AN4/PPG8(9) P63/AN3/PPG6(7) P62/AN2/PPG4(5) P61/AN1/PPG2(3) P60/AN0/PPG0(1) AVss AVRL AVRH AVcc P57/AN15 P56/AN14 P55/AN13 P54/AN12/TOT3 (FPT-100P-M05) * : X0A, X1A : P40, P41 : MB90867E, MB90F867E MB90867ES, MB90F867ES 9 MB90860E Series ■ PIN DESCRIPTION Pin No. QFP100*1 LQFP100*2 Pin name I/O Circuit type*3 Function General purpose I/O pins. The register can be set to select whether to use a pull-up resistor.In external bus mode, the pin is enabled as a general-purpose I/O port when the corresponding bit in the external address output control register (HACR) is 1. G A20 to A23 IN0 to IN3 P30 5 3 ALE IN4 P31 6 4 RD IN5 P32 G G Output pins of the external address bus. When the corresponding bit in the external address output control register (HACR) is 0, the pins are enabled as high address output pins (A20 to A23). Trigger input pins for input captures 0 to 3. General purpose I/O pin.The register can be set to select whether to use a pull-up resistor.This function is enabled in single-chip mode. Address latch enable output pin. This function is enabled when the external bus is enabled. Trigger input pin for input capture 4. General purpose I/O pin.The register can be set to select whether to use a pull-up resistor.This function is enabled in single-chip mode. External read strobe output pin. This function is enabled when the external bus is enabled. Trigger input pin for input capture 5. General purpose I/O pin. The register can be set to select whether to use a pull-up resistor. This function is enabled either in singlechip mode or with the WR/WRL pin output disabled. G WR / WRL Write strobe output pin for the external data bus. This function is enabled when both the external bus and the WR/WRL pin output are enabled. WRL is used to write-strobe 8 lower bits of the data bus in 16-bit access while WR is used to write-strobe 8 bits of the data bus in 8-bit access. External interrupt request input pin (sub) . General purpose I/O pin. The register can be set to select whether to use a pull-up resistor.This function is enabled either in singlechip mode or with the WRH pin output disabled. G WRH Write strobe output pin for the 8 higher bits of the external data bus. This function is enabled when the external bus is enabled, when the external bus 16-bit mode is selected, and when the WRH output pin is enabled. (Continued) P24 to P27 1 to 4 99 to 2 7 5 INT10R P33 8 6 10 MB90860E Series Pin No. QFP100*1 LQFP100*2 Pin name I/O Circuit type*3 Function General purpose I/O pin. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the hold function disabled. P34 9 7 HRQ OUT4 P35 10 8 HAK OUT5 P36 11 9 RDY OUT6 P37 12 10 CLK OUT7 P40, P41 13, 14 11, 12 X0A , X1A 15 16 17 13 14 15 VCC VSS C P42 18 16 IN6 INT9R F B ⎯ ⎯ K F G G G G Hold request input pin. This function is enabled when both the external bus and the hold function are enabled. Waveform output pin for output compare 4. General purpose I/O pin. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the hold function disabled. Hold acknowledge output pin. This function is enabled when both the external bus and the hold function are enabled. Waveform output pin for output compare 5. General purpose I/O pin. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the external ready function disabled. External ready input pin. This function is enabled when both the external bus and the external ready function are enabled. Waveform output pin for output compare 6. General purpose I/O pin. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the clock output disabled. Clock output pin. This function is enabled when both the external bus and clock output are enabled. Waveform output pin for output compare 7. General purpose I/O pins. (devices with S-suffix) Input pins for sub-clock (devices without S-suffix) Power (3.5 V to 5.5 V) input pin GND pin This is the power supply stabilization capacitor pin. It should be connected to a higher than or equal to 0.1 µF ceramic capacitor. General purpose I/O pin. Trigger input pin for input capture 6. External interrupt request input pin (sub) (Continued) 11 MB90860E Series Pin No. QFP100*1 LQFP100*2 19 17 Pin name P43 IN7 P44 20 18 SDA0 FRCK0 P45 21 19 SCL0 FRCK1 22 23 20 21 P46 SDA1 P47 SCL1 P50 24 22 AN8 SIN2 P51 25 23 AN9 SOT2 P52 26 24 AN10 SCK2 P53 27 25 AN11 TIN3 P54 28 26 AN12 TOT3 29 30, 31 32 27 28, 29 30 P55 AN13 P56, P57 AN14, AN15 AVCC I/O Circuit type*3 F General purpose I/O pin. Function Trigger input pin for input capture 7. General purpose I/O pin. Serial data I/O pin for I2C 0 Input pin for the 16-bit I/O Timer 0 General purpose I/O pin. H H Serial clock I/O pin for I2C 0 Input pin for the 16-bit I/O Timer General purpose I/O pin. Serial data I/O pin for I2C 1 General purpose I/O pin. Serial clock I/O pin for I2C 1 General purpose I/O pin. Analog input pin for the A/D converter Serial data input pin for UART2 General purpose I/O pin. H H O I Analog input pin for the A/D converter Serial data output pin for UART2 General purpose I/O pin. I Analog input pin for the A/D converter Clock I/O pin for UART2 General purpose I/O pin. I Analog input pin for the A/D converter Event input pin for the reload timer 3 General purpose I/O pin. I Analog input pin for the A/D converter Output pin for the reload timer 3 General purpose I/O pin. Analog input pin for the A/D converter General purpose I/O pins. Analog input pin for the A/D converter Power input pin for the A/D Converter analog (Continued) I J K 12 MB90860E Series Pin No. QFP100*1 LQFP100*2 33 34 35 31 32 33 Pin name I/O Circuit type*3 L K K Function Reference voltage input pin for the A/D Converter. This power supply must be turned on or off while a voltage higher than or equal to AVRH is applied to AVCC. Lower reference voltage input pin for the A/D Converter GND pin for the A/D Converter analog General purpose I/O pins. Analog input pins for the A/D converter Output pins for PPGs AVRH AVRL AVSS P60 to P67 AN0 to AN7 PPG0, 2, 4, 6, 8, A, C, E 36 to 43 34 to 41 I 44 45 to 50 51 52, 53 54 55, 56 42 43 to 48 49 50, 51 52 53, 54 VSS P70 to P75 AN16 to AN21 INT0 to INT5 MD2 MD1, MD0 RST P76, P77 AN22, AN23 INT6, INT7 P80 TIN0 ADTG INT12R P81 TOT0 CKOT INT13R P82 SIN0 TIN2 INT14R P83 ⎯ I D C E I GND pin General purpose I/O pins. Analog input pins for the A/D converter External interrupt request input pins Input pin for specifying the operating mode. Input pins for specifying the operating mode. Reset input General purpose I/O pins. Analog input pins for the A/D converter External interrupt request input pins General purpose I/O pin. Event input pin for the reload timer 0 Trigger input pin for the A/D converter External interrupt request input pin (sub) General purpose I/O pin. Output pin for the reload timer 0 Output pin for the clock monitor External interrupt request input pin (sub) General purpose I/O pin. Serial data input pin for UART0 Event input pin for the reload timer 2 External interrupt request input pin (sub) General purpose I/O pin. 57 55 F 58 56 F 59 57 M 60 58 SOT0 TOT2 P84 F Serial data output pin for UART0 Output pin for the reload timer 2 General purpose I/O pin. 61 59 SCK0 INT15R F Clock I/O pin for UART0 External interrupt request input pin (sub) (Continued) 13 MB90860E Series Pin No. QFP100*1 LQFP100*2 62 63 64 65 66 67 to 70 60 61 62 63 64 65 to 68 Pin name P85 SIN1 P86 SOT1 P87 SCK1 VCC VSS P90 to P93 PPG1, 3, 5, 7 P94 to P97 71 to 74 69 to 72 OUT0 to OUT3 PA0 INT8R PA1 P00 to P07 77 to 84 75 to 82 AD00 to AD07 INT8 to INT15 P10 85 83 AD08 TIN1 P11 86 84 AD09 TOT1 I/O Circuit type*3 M F F ⎯ ⎯ F General purpose I/O pin. Function Serial data input pin for UART1 General purpose I/O pin. Serial data output pin for UART1 General purpose I/O pin. Clock I/O pin for UART1 Power (3.5 V to 5.5 V) input pins GND pins General purpose I/O pin Output pins for PPGs General purpose I/O pin Waveform output pins for output compares 0 to 3. This function is enabled when the OCU enables waveform output. General purpose I/O pin. External interrupt request input pin (sub) General purpose I/O pin. General purpose I/O pins. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. F 75 76 73 74 F F G I/O pins for 8 lower bits of the external address/data bus. This function is enabled when the external bus is enabled. External interrupt request input pins. General purpose I/O pin. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. G I/O pin for the external address/data bus. This function is enabled when the external bus is enabled. Event input pin for the reload timer 1 General purpose I/O pin. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. G I/O pin for the external address/data bus. This function is enabled when the external bus is enabled. Output pin for the reload timer 1 (Continued) 14 MB90860E Series Pin No. QFP100*1 LQFP100*2 Pin name I/O Circuit type*3 Function General purpose I/O pin. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. P12 87 85 N AD10 SIN3 INT11R P13 I/O pin for the external address/data bus. This function is enabled when the external bus is enabled. Serial data input pin for UART3 External interrupt request input pin (sub) General purpose I/O pin. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. 88 86 AD11 SOT3 P14 G I/O pin for the external address/data bus. This function is enabled when the external bus is enabled. Serial data output pin for UART3 General purpose I/O pin. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. 89 87 AD12 SCK3 G I/O pin for the external address/data bus. This function is enabled when the external bus is enabled. Clock I/O pin for UART3 Power (3.5 V to 5.5 V) input pin GND pin Main clock output pin Main clock input pin General purpose I/O pin. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. I/O pin for the external address/data bus. This function is enabled when the external bus is enabled. General purpose I/O pin. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. I/O pin for the external address/data bus. This function is enabled when the external bus is enabled. General purpose I/O pin. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. I/O pin for the external address/data bus. This function is enabled when the external bus is enabled. (Continued) 90 91 92 93 88 89 90 91 VCC VSS X1 X0 P15 ⎯ ⎯ A 94 92 AD13 G P16 95 93 AD14 G P17 96 94 AD15 G 15 MB90860E Series (Continued) Pin No. QFP100*1 LQFP100*2 Pin name I/O Circuit type*3 Function General purpose I/O pins. The register can be set to select whether to use a pull-up resistor.In external bus mode, the pin is enabled as a general-purpose I/O port when the corresponding bit in the external address output control register (HACR) is 1. P20 to P23 97 to 100 95 to 98 A16 to A19 G Output pins of the external address bus. When the corresponding bit in the external address output control register (HACR) is 0, the pins are enabled as high address output pins (A16 to A19). Output pins for PPGs PPG9,PPGB, PPGD,PPGF *1 : FPT-100P-M06 *2 : FPT-100P-M05 *3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”. 16 MB90860E Series ■ I/O CIRCUIT TYPE Type Circuit Remarks • Oscillation circuit High-speed oscillation feedback resistor = approx. 1 MΩ X1 Xout A X0 Standby control signal X1A Xout • Oscillation circuit Low-speed oscillation feedback resistor = approx. 10 MΩ B X0A Standby control signal R C Hysteresis inputs • Mask ROM and evaluation device: CMOS Hysteresis input pin • Flash device: CMOS input pin • Mask ROM and evaluation device: CMOS Hysteresis input pin Pull-down resistor value: approx. 50 kΩ • Flash memory device: CMOS input pin No Pull-down R Hysteresis inputs D Pull-down Resistor CMOS Hysteresis input pin Pull-up resistor value: approx. 50 kΩ E Pull-up Resistor R Hysteresis inputs (Continued) 17 MB90860E Series Type Circuit Remarks • CMOS level output (IOL = 4 mA, IOH = −4 mA) • CMOS hysteresis inputs (With the standbytime input shutdown function) • Automotive input (With the standby-time input shutdown function) P-ch Pout N-ch Nout F R Hysteresis inputs Automotive inputs Standby control for input shutdown Pull-up control P-ch P-ch Pout N-ch Nout G R Hysteresis inputs • CMOS level output (IOL = 4 mA, IOH = −4 mA) • CMOS hysteresis inputs (With the standbytime input shutdown function) • Automotive input (With the standby-time input shutdown function) • TTL input (With the standby-time input shutdown function) • Programmable pull-up resistor: 50 kΩ approx. Automotive inputs TTL input Standby control for input shutdown P-ch Pout N-ch Nout • CMOS level output (IOL = 3 mA, IOH = −3 mA) • CMOS hysteresis inputs (With the standbytime input shutdown function) • Automotive input (With the standby-time input shutdown function) H R Hysteresis inputs Automotive inputs Standby control for input shutdown (Continued) 18 MB90860E Series Type Circuit Remarks • CMOS level output (IOL = 4 mA, IOH = −4 mA) • CMOS hysteresis inputs (With the standbytime input shutdown function) • Automotive input (With the standby-time input shutdown function) • A/D converter analog input P-ch Pout N-ch R Nout I Hysteresis inputs Automotive inputs Standby control for input shutdown Analog input P-ch Pout N-ch R Nout • CMOS level output (IOL = 4 mA, IOH = −4 mA) • D/A analog output • CMOS hysteresis inputs (With the standbytime input shutdown function) • Automotive input (With the standby-time input shutdown function) • A/D converter analog input J Hysteresis inputs Automotive inputs Standby control for input shutdown Analog input Analog output Power supply input protection circuit P-ch K N-ch P-ch ANE AVR L N-ch • A/D converter reference voltage power supply input pin, with the protection circuit • Flash devices do not have a protection circuit against VCC for pin AVRH ANE (Continued) 19 MB90860E Series (Continued) Type Circuit Remarks • CMOS level output (IOL = 4 mA, IOH = −4 mA) • CMOS inputs (With the standby-time input shutdown function) • Automotive input (With the standby-time input shutdown function) P-ch Pout N-ch Nout M R CMOS inputs Automotive inputs Standby control for input shutdown Pull-up control P-ch P-ch Pout N-ch Nout N R CMOS inputs • CMOS level output (IOL = 4 mA, IOH = −4 mA) • CMOS inputs (With the standby-time input shutdown function) • Automotive input (With the standby-time input shutdown function) • TTL input (With the standby-time input shutdown function) Programmable pull-up registor:50 kΩ approx Automotive inputs TTL input Standby control for input shutdown P-ch Pout N-ch R Nout • CMOS level output(IOL = 4 mA, IOH = −4 mA) • CMOS inputs (With the standby-time input shutdown function) • Automotive input (With the standby-time input shutdown function) • A/D converter analog input O CMOS inputs Automotive inputs Standby control for input shutdown Analog input 20 MB90860E Series ■ HANDLING DEVICES 1. Preventing latch-up CMOS IC may suffer latch-up under the following conditions : • A voltage higher than VCC or lower than VSS is applied to an input or output pin. • A voltage higher than the rated voltage is applied between VCC and VSS pins. • The AVCC power supply is applied before the VCC voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage. 2. Handling unused pins Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 kΩ . Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. 3. Power supply pins (VCC/VSS) • If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected the inside of the device to prevent such malfunctioning as latch up. To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally. • Connect VCC and VSS to the device from the current supply source at a low impedance. • As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between VCC and VSS in the vicinity of VCC and VSS pins of the device Vcc Vss Vcc Vss Vcc Vss MB90860E Series Vcc Vss Vss Vcc 4. Mode Pin (MD0 to MD2) Connect the mode pin directly to VCC or VSS pins. To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the mode pins to VCC or VSS pins and to provide a low-impedance connection. 21 MB90860E Series 5. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN23) after turning-on the digital power supply (VCC) . Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable) . 6. Connection of Unused Pins of A/D Converter if A/D Converter is used Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS. 7. Crystal Oscillator Circuit X0, X1 pins and X0A, X1A pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic oscillator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area for stabilizing the operation. 8. Pull-up/down resistors The MB90860E Series does not support internal pull-up/down resistors (Port 0 to Port 3: built-in pull-up resistors). Use external components where needed. 9. Using external clock To use external clock, drive the X0 pin and leave X1 pin open. MB90860E Series X0 Open X1 10. Precautions for when not using a sub clock signal If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the X1A pin open. 11. Notes on during operation of PLL clock mode If the PLL clock mode is selected, the MB90860 series attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. 12. Notes on Energization To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 or more µs (0.2 V to 2.7 V) 22 MB90860E Series 13. Stabilization of power supply voltage A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply voltage operating range. Therefore, the VCC supply voltage should be stabilized. For the reference, stabilize the supply voltage by setting the following value. • VCC ripple variations (peak-to-peak value) at commercial frequencies (50 Hz/60 Hz) fall below 10% of the standard VCC supply voltage • The coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching. 14. Initialization In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers, turn on the power again. 15. Port 0 to port 3 output during Power-on (External-bus mode) As shown below, when power is turned on in External-Bus mode, in spite of reset input, there is a possibility that output signal of Port 0 to Port 3 might be unstable. 1/2VCC VCC Port 0 to Port 3 Port 0 to Port 3 outputs might be unstable Port 0 to Port 3 outputs = Hi-Z 16. Flash security Function The security bit is located in the area of the flash memory. If protection code 01H is written in the security bit, the flash memory is in the protected state by security. Therefore please do not write 01H in this address if you do not use the security function. Please refer to following table for the address of the security bit. Flash memory size MB90F867E(S) Embedded 1 Mbit Flash Memory Address for security bit FE0001H 23 MB90860E Series ■ BLOCK DIAGRAMS • MB90V340E-101/102 X0,X1 X0A,X1A* RST Clock Controller 16LX CPU RAM 30 Kbytes I/O Timer 0 Input Capture 8 channels Output Compare 8 channels FRCK0 IN7 to IN0 OUT7 to OUT0 Prescaler 5 channels SOT4 to SOT0 SCK4 to SCK0 SIN4 to SIN0 AVCC AVSS AN23 to AN0 AVRH AVRL ADTG I/O Timer 1 FRCK1 UART 5 channels CAN Controller 3 channels RX2 to RX0 TX2 to TX0 8/10-bit ADC 24 channels F2MC-16 Bus 16-bit Reload Timer 4 channels TIN3 to TIN0 TOT3 to TOT0 AD15 to AD00 A23 to A16 ALE RD External Bus Interface WR/WRL WRH HRQ HAK RDY CLK External Interrupt 16 channels Clock Monitor INT15 to INT8 (INT15R to INT8R) INT7 to INT0 DA01, DA00 10-bit DAC 2 channels 8/16-bit PPG 16 channels I2C Interface 2 channels PPGF to PPG0 SDA1, SDA0 SCL1, SCL0 DMAC CKOT * : Only for MB90V340E-102 24 MB90860E Series • MB90867E(S), MB90F867E(S) X0,X1 X0A,X1A* RST Clock Controller 16LX CPU RAM 6 Kbytes I/O Timer 0 Input Capture 8 channels FRCK0 IN7 to IN0 ROM/Flash 128 Kbytes Prescaler 4 channels Output Compare 8 channels I/O Timer 1 OUT7 to OUT0 FRCK1 SOT3 to SOT0 SCK3 to SCK0 SIN3 to SIN0 AVCC AVSS AN15 to AN0 AN23 to AN16 AVRH AVRL ADTG UART 4 channels 8/10-bit ADC 24 channels F2MC-16 Bus 16-bit Reload Timer 4 channels TIN3 to TIN0 TOT3 to TOT0 AD15 to AD00 A23 to A16 ALE RD External Bus Interface WR/WRL WRH HRQ HAK RDY CLK External Interrupt 16 channels Clock Monitor INT15 to INT8 (INT15R to INT8R) INT7 to INT0 PPGF to PPG0 8/16-bit PPG 16 channels I2C Interface 2 channels SDA1, SDA0 SCL1, SCL0 DMAC CKOT * : Only for devices without ‘S’ Suffix 25 MB90860E Series ■ MEMORY MAP MB90867E(S) MB90F867E(S) 000000H 0000EFH 000100H Peripheral External access area MB90V340E-101/102 000000H 0000EFH 000100H Peripheral External access area RAM 6 Kbytes 003FFFH RAM 30 Kbytes 0078FFH 007900H Peripheral 007FFFH 008000H 00FFFFH F80000H F8FFFFH F90000H F9FFFFH FA0000H FAFFFFH FB0000H ROM (FB bank) FBFFFFH FC0000H FCFFFFH FD0000H FDFFFFH FE0000H ROM (FE bank) FEFFFFH FF0000H ROM (FF bank) FFFFFFH ROM (FC bank) ROM (FD bank) ROM (FA bank) ROM (F8 bank) ROM (F9 bank) ROM (image of FF bank) External access area 007900H Peripheral 007FFFH 008000H 00FFFFH ROM (image of FF bank) External access area FE0000H FEFFFFH FF0000H FFFFFFH ROM (FE bank) ROM (FF bank) : No access Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without using the far specification in the pointer declaration. For example, an attempt to access 00C000H accesses the value at FFC000H in ROM. The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00. The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF7FFFH is visible only in bank FF. 26 MB90860E Series ■ I/O MAP Address Register Abbreviation PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA ADER5 ADER6 ADER7 ILSR0 ILSR1 DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 DDRA Reserved PUCR0 PUCR1 PUCR2 PUCR3 R/W R/W R/W W, R/W Port 0 Port 1 Port 2 Port 3 00000000B 00000000B 00000000B 00000000B (Continued) Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port 5, A/D Port 6, A/D Port 7, A/D Ports Ports Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 11111111B 11111111B 11111111B XXXXXXXXB XXXX0XXXB 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000100B 000000H Port 0 Data Register 000001H Port 1 Data Register 000002H Port 2 Data Register 000003H Port 3 Data Register 000004H Port 4 Data Register 000005H Port 5 Data Register 000006H Port 6 Data Register 000007H Port 7 Data Register 000008H Port 8 Data Register 000009H Port 9 Data Register 00000AH Port A Data Register 00000BH Port 5 Analog Input Enable Register 00000CH Port 6 Analog Input Enable Register 00000DH Port 7 Analog Input Enable Register 00000EH Input Level Select Register 0 00000FH Input Level Select Register 1 000010H Port 0 Direction Register 000011H Port 1 Direction Register 000012H Port 2 Direction Register 000013H Port 3 Direction Register 000014H Port 4 Direction Register 000015H Port 5 Direction Register 000016H Port 6 Direction Register 000017H Port 7 Direction Register 000018H Port 8 Direction Register 000019H Port 9 Direction Register 00001AH Port A Direction Register 00001BH 00001CH Port 0 Pull-up Control Register 00001DH Port 1 Pull-up Control Register 00001EH Port 2 Pull-up Control Register 00001FH Port 3 Pull-up Control Register 27 MB90860E Series Address Register Abbreviation SMR0 SCR0 RDR0/ TDR0 SSR0 ECCR0 ESCR0 BGR00 BGR01 SMR1 SCR1 RDR1/ TDR1 SSR1 ECCR1 ESCR1 BGR10 BGR11 PPGC0 PPGC1 PPG01 Reserved PPGC2 PPGC3 PPG23 Reserved PPGC4 PPGC5 PPG45 PACSR1 PPGC6 PPGC7 PPG67 Reserved Access W,R/W W,R/W R/W R,R/W R,W, R/W R/W R/W R/W W,R/W W,R/W R/W R,R/W R,W, R/W R/W R/W R/W W,R/W W,R/W R/W W,R/W W,R/W R/W W,R/W W,R/W R/W R/W W,R/W W,R/W R/W Resource name Initial value 00000000B 00000000B 00000000B UART0 00001000B 000000XXB 00000100B 00000000B 00000000B 00000000B 00000000B 00000000B UART1 00001000B 000000XXB 00000100B 00000000B 00000000B 0X000XX1B 16-bit PPG 0/1 0X000001B 000000X0B 0X000XX1B 16-bit PPG 2/3 0X000001B 000000X0B 0X000XX1B 16-bit PPG 4/5 Address Match Detection 1 16-bit PPG 6/7 0X000001B 000000X0B 00000000B 0X000XX1B 0X000001B 000000X0B (Continued) 000020H Serial Mode Register 0 000021H Serial Control Register 0 000022H Reception/Transmission Data Register 0 000023H Serial Status Register 0 000024H Extended Communication Control Register 0 000025H Extended Status/Control Register 0 000026H Baud Rate Generator Register 00 000027H Baud Rate Generator Register 01 000028H Serial Mode Register 1 000029H Serial Control Register 1 00002AH Reception/Transmission Data Register 1 00002BH Serial Status Register 1 00002CH Extended Communication Control Register 1 00002DH Extended Status/Control Register 1 00002EH Baud Rate Generator Register 10 00002FH Baud Rate Generator Register 11 000030H PPG 0 Operation Mode Control Register 000031H PPG 1 Operation Mode Control Register 000032H PPG 0/PPG 1 Count Clock Select Register 000033H 000034H PPG 2 Operation Mode Control Register 000035H PPG 3 Operation Mode Control Register 000036H PPG 2/PPG 3 Count Clock Select Register 000037H 000038H PPG 4 Operation Mode Control Register 000039H PPG 5 Operation Mode Control Register 00003AH PPG 4/PPG 5 Clock Select Register 00003BH Address Detect Control Register 1 00003CH PPG 6 Operation Mode Control Register 00003DH PPG 7 Operation Mode Control Register 00003EH PPG 6/PPG 7 Count Clock Control Register 00003FH 28 MB90860E Series Address Register Abbreviation PPGC8 PPGC9 PPG89 Reserved PPGCA PPGCB PPGAB Reserved PPGCC PPGCD PPGCD Reserved PPGCE PPGCF PPGEF Reserved ICS01 ICE01 ICS23 ICE23 ICS45 ICE45 ICS67 ICE67 OCS0 OCS1 OCS2 OCS3 OCS4 OCS5 OCS6 OCS7 Access W,R/W W,R/W R/W Resource name Initial value 0X000XX1B 000040H PPG 8 Operation Mode Control Register 000041H PPG 9 Operation Mode Control Register 000042H 000043H 000044H PPG A Operation Mode Control Register 000045H PPG B Operation Mode Control Register 000046H 000047H 000048H PPG C Operation Mode Control Register 000049H PPG D Operation Mode Control Register 00004AH 00004BH 00004CH PPG E Operation Mode Control Register 00004DH PPG F Operation Mode Control Register 00004EH 00004FH 000050H Input Capture Control Status 0/1 000051H Input Capture Edge 0/1 000052H Input Capture Control Status 2/3 000053H Input Capture Edge 2/3 000054H Input Capture Control Status 4/5 000055H Input Capture Edge 4/5 000056H Input Capture Control Status 6/7 000057H Input Capture Edge 6/7 000058H Output Compare Control Status 0 000059H Output Compare Control Status 1 00005AH Output Compare Control Status 2 00005BH Output Compare Control Status 3 00005CH Output Compare Control Status 4 00005DH Output Compare Control Status 5 00005EH Output Compare Control Status 6 00005FH Output Compare Control Status 7 PPG E/PPG F Count Clock Select Register PPG C/PPG D Count Clock Select Register PPG A/PPG B Count Clock Select Register PPG 8/PPG 9 Count Clock Control Register 16-bit PPG 8/9 0X000001B 000000X0B W,R/W W,R/W R/W 16-bit PPG A/B 0X000XX1B 0X000001B 000000X0B W,R/W W,R/W R/W 16-bit PPG C/D 0X000XX1B 0X000001B 000000X0B W,R/W W,R/W R/W 16-bit PPG E/F 0X000XX1B 0X000001B 000000X0B R/W R/W, R R/W R R/W R R/W R/W, R R/W R/W R/W R/W R/W R/W R/W R/W Input Capture 0/1 Input Capture 2/3 Input Capture 4/5 Input Capture 6/7 Output Compare 0/1 Output Compare 2/3 Output Compare 4/5 Output Compare 6/7 00000000B XXX0X0XXB 00000000B XXXXXXXXB 00000000B XXXXXXXXB 00000000B XXX000XXB 0000XX00B 0XX00000B 0000XX00B 0XX00000B 0000XX00B 0XX00000B 0000XX00B 0XX00000B (Continued) 29 MB90860E Series Address Register Abbreviation TMCSR0 TMCSR0 TMCSR1 TMCSR1 TMCSR2 TMCSR2 TMCSR3 TMCSR3 ADCS0 ADCS1 ADCR0 ADCR1 ADSR0 ADSR1 Reserved ROMM Reserved Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W W Resource name 16-bit Reload Timer 0 16-bit Reload Timer 1 16-bit Reload Timer 2 16-bit Reload Timer 3 Initial value 00000000B XXXX0000B 00000000B XXXX0000B 00000000B XXXX0000B 00000000B XXXX0000B 000XXXX0B 0000000XB 00000000B XXXXXX00B 00000000B 00000000B 000060H Timer Control Status 0 000061H Timer Control Status 0 000062H Timer Control Status 1 000063H Timer Control Status 1 000064H Timer Control Status 2 000065H Timer Control Status 2 000066H Timer Control Status 3 000067H Timer Control Status 3 000068H A/D Control Status 0 000069H A/D Control Status 1 00006AH A/D Data 0 00006BH A/D Data 1 00006CH ADC Setting 0 00006DH ADC Setting 1 00006EH 00006FH ROM Mirror Function Select 000070H to 00009AH 00009BH DMA Descriptor Channel Specified Register A/D Converter ROM Mirror XXXXXXX1B DCSR DSRL DSRH PACSR0 DIRR LPMCR CKSCR Reserved DSSR ARSR HACR ECSR WDTC R/W R/W R/W R/W R/W W,R/W R,R/W Address Match Detection 0 Low Power Control Circuit Low Power Control Circuit DMA 00000000B 00000000B 00000000B 00000000B 00009CH DMA Status L Register 00009DH DMA Status H Register 00009EH Address Detect Control Register 0 00009FH Delayed Interrupt/release 0000A0H Low-power Mode Control Register 0000A1H Clock Selection Register 0000A2H, 0000A3H 0000A4H DMA Stop Status Register 0000A5H Automatic Ready Function Select Register 0000A6H External Address Output Control Register 0000A7H Bus Control Signal Selection Register 0000A8H Watchdog Control Register Delayed Interrupt XXXXXXX0B 00011000B 11111100B R/W W W W R,W DMA External Memory Access Watchdog Timer 00000000B 0011XX00B 00000000B 0000000XB XXXXX111B (Continued) 30 MB90860E Series Address Register Abbreviation TBTC WTC Access W,R/W R,R/W R/W R/W R,R/W Resource name Time Base Timer Watch Timer Initial value 1XX00100B 1X001000B 00000000B 00000000B 000X0000B 0000A9H Time Base Timer Control Register 0000AAH Watch Timer Control Register 0000ABH 0000ACH DMA Enable L Register 0000ADH DMA Enable H Register 0000AEH 0000AFH 0000B0H Interrupt Control Register 00 0000B1H Interrupt Control Register 01 0000B2H Interrupt Control Register 02 0000B3H Interrupt Control Register 03 0000B4H Interrupt Control Register 04 0000B5H Interrupt Control Register 05 0000B6H Interrupt Control Register 06 0000B7H Interrupt Control Register 07 0000B8H Interrupt Control Register 08 0000B9H Interrupt Control Register 09 0000BAH Interrupt Control Register 10 0000BBH Interrupt Control Register 11 0000BCH Interrupt Control Register 12 0000BDH Interrupt Control Register 13 0000BEH Interrupt Control Register 14 0000BFH Interrupt Control Register 15 0000C0H D/A Converter Data 0 Register 0000C1H D/A Converter Data 1 Register 0000C2H D/A Control 0 Register 0000C3H D/A Control 1 Register 0000C4H, 0000C5H 0000C6H External Interrupt Enable 0 0000C7H External Interrupt Source 0 0000C8H External Interrupt Level Setting 0 0000C9H External Interrupt Level Setting 0 Flash Control Status Register (Flash Devices only. Otherwise reserved) Reserved DERL DERH FMCS Reserved ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 DAT0 DAT1 DACR0 DACR1 Reserved ENIR0 EIRR0 ELVR0 ELVR0 R/W R/W R/W R/W External Interrupt 0 00000000B XXXXXXXXB 00000000B 00000000B (Continued) W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W R/W R/W R/W R/W D/A Converter Interrupt Control 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B XXXXXXXXB XXXXXXXXB XXXXXXX0B XXXXXXX0B DMA Flash Memory 31 MB90860E Series Address Register Abbreviation ENIR1 EIRR1 ELVR1 ELVR1 EISSR PSCCR BAPL BAPM BAPH DMACS IOAL IOAH DCTL DCTH SMR2 SCR2 RDR2/ TDR2 SSR2 ECCR2 ESCR2 BGR20 BGR21 Access R/W R/W R/W R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W W,R/W W,R/W R/W R,R/W R,W, R/W R/W R/W R/W Resource name Initial value 00000000B XXXXXXXXB 0000CAH External Interrupt Enable 1 0000CBH External Interrupt Source 1 0000CCH External Interrupt Level Setting 1 0000CDH External Interrupt Level Setting 1 0000CEH External Interrupt Source Select 0000CFH PLL/Sub Clock Control Register 0000D0H DMA Buffer Address Pointer L Register 0000D1H DMA Buffer Address Pointer M Register 0000D2H DMA Buffer Address Pointer H Register 0000D3H DMA Control Register 0000D4H 0000D5H I/O Register Address Pointer L Register I/O Register Address Pointer H Register External Interrupt 1 00000000B 00000000B 00000000B PLL XXXX0000B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB DMA XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B 00000000B 00000000B 0000D6H Data Counter L Register 0000D7H Data Counter H Register 0000D8H Serial Mode Register 2 0000D9H Serial Control Register 2 0000DAH Reception/Transmission Data Register 2 Extended Communication Control Register 2 0000DBH Serial Status Register 2 0000DCH UART2 00001000B 000000XXB 00000100B 00000000B 00000000B 0000DDH Extended Status Control Register 2 0000DEH Baud Rate Generator Register 20 0000DFH Baud Rate Generator Register 21 0000E0H to 0000FFH 007900H 007901H 007902H 007903H 007904H 007905H 007906H 007907H 32 Reload Register L0 Reload Register H0 Reload Register L1 Reload Register H1 Reload Register L2 Reload Register H2 Reload Register L3 Reload Register H3 External area PRLL0 PRLH0 PRLL1 PRLH1 PRLL2 PRLH2 PRLL3 PRLH3 R/W R/W R/W R/W R/W R/W R/W R/W 16-bit PPG 2/3 16-bit PPG 0/1 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued) MB90860E Series Address Register Abbreviation PRLL4 PRLH4 PRLL5 PRLH5 PRLL6 PRLH6 PRLL7 PRLH7 PRLL8 PRLH8 PRLL9 PRLH9 PRLLA PRLHA PRLLB PRLHB PRLLC PRLHC PRLLD PRLHD PRLLE PRLHE PRLLF PRLHF IPCP0 IPCP0 IPCP1 IPCP1 IPCP2 IPCP2 IPCP3 IPCP3 IPCP4 IPCP4 IPCP5 IPCP5 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R Resource name Initial value XXXXXXXXB 007908H Reload Register L4 007909H Reload Register H4 00790AH Reload Register L5 00790BH Reload Register H5 00790CH Reload Register L6 00790DH Reload Register H6 00790EH Reload Register L7 00790FH Reload Register H7 007910H Reload Register L8 007911H Reload Register H8 007912H Reload Register L9 007913H Reload Register H9 007914H Reload Register LA 007915H Reload Register HA 007916H Reload Register LB 007917H Reload Register HB 007918H Reload Register LC 007919H Reload Register HC 00791AH Reload Register LD 00791BH Reload Register HD 00791CH Reload Register LE 00791DH Reload Register HE 00791EH Reload Register LF 00791FH Reload Register HF 007920H Input Capture 0 007921H Input Capture 0 007922H Input Capture 1 007923H Input Capture 1 007924H Input Capture 2 007925H Input Capture 2 007926H Input Capture 3 007927H Input Capture 3 007928H Input Capture 4 007929H Input Capture 4 00792AH Input Capture 5 00792BH Input Capture 5 16-bit PPG 4/5 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued) 33 16-bit PPG 6/7 16-bit PPG 8/9 16-bit PPG A/B 16-bit PPG C/D 16-bit PPG E/F Input Capture 0/1 Input Capture 2/3 Input Capture 4/5 MB90860E Series Address Register Abbreviation IPCP6 IPCP6 IPCP7 IPCP7 OCCP0 OCCP0 OCCP1 OCCP1 OCCP2 OCCP2 OCCP3 OCCP3 OCCP4 OCCP4 OCCP5 OCCP5 OCCP6 OCCP6 OCCP7 OCCP7 TCDT0 TCDT0 TCCSL0 TCCSH0 TCDT1 TCDT1 TCCSL1 TCCSH1 TMR0/ TMRLR0 TMR1/ TMRLR1 TMR2/ TMRLR2 TMR3/ TMRLR3 Access R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Initial value XXXXXXXXB 00792CH Input Capture 6 00792DH Input Capture 6 00792EH Input Capture 7 00792FH Input Capture 7 007930H Output Compare 0 007931H Output Compare 0 007932H Output Compare 1 007933H Output Compare 1 007934H Output Compare 2 007935H Output Compare 2 007936H Output Compare 3 007937H Output Compare 3 007938H Output Compare 4 007939H Output Compare 4 00793AH Output Compare 5 00793BH Output Compare 5 00793CH Output Compare 6 00793DH Output Compare 6 00793EH Output Compare 7 00793FH Output Compare 7 007940H Timer Data 0 007941H Timer Data 0 007942H Timer Control Status 0 007943H Timer Control Status 0 007944H Timer Data 1 007945H Timer Data 1 007946H Timer Control Status 1 007947H Timer Control Status 1 007948H 007949H 00794AH 00794BH 00794CH 00794DH 00794EH 00794FH Timer 0/Reload 0 Timer 1/Reload 1 Timer 2/Reload 2 Timer 3/Reload 3 Input Capture 6/7 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B 00000000B 00000000B 0XXXXXXXB 00000000B 00000000B 00000000B 0XXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued) Output Compare 0/1 Output Compare 2/3 Output Compare 4/5 Output Compare 6/7 I/O Timer 0 I/O Timer 1 16-bit Reload Timer 0 16-bit Reload Timer 1 16-bit Reload Timer 2 16-bit Reload Timer 3 34 MB90860E Series Address Register Abbreviation SMR3 SCR3 RDR3/ TDR3 SSR3 ECCR3 ESCR3 BGR30 BGR31 SMR4 SCR4 RDR4/ TDR4 SSR4 ECCR4 ESCR4 BGR40 BGR41 Access W,R/W W,R/W R/W R,R/W R,W, R/W R/W R/W R/W W,R/W W,R/W R/W R,R/W R,W, R/W R/W R/W R/W Resource name Initial value 00000000B 00000000B 00000000B 007950H Serial Mode Register 3 007951H Serial Control Register 3 007952H Reception/Transmission Data Register 3 Extended Communication Control Register 3 007953H Serial Status Register 3 007954H UART3 00001000B 000000XXB 00000100B 00000000B 00000000B 00000000B 00000000B 00000000B 007955H Extended Status Control Register 007956H Baud Rate Generator Register 30 007957H Baud Rate Generator Register 31 007958H Serial Mode Register 4 007959H Serial Control Register 4 00795AH Reception/Transmission Data Register 4 Extended Communication Control Register 4 00795BH Serial Status Register 4 00795CH UART4 00001000B 000000XXB 00000100B 00000000B 00000000B 00795DH Extended Status Control Register 00795EH Baud Rate Generator Register 40 00795FH Baud Rate generator Register 41 007960H to 00796BH 00796CH Clock Output Enable Register 00796DH to 00796FH 007970H I2C Bus Status Register 0 007971H I2C bus Control Register 0 007972H 007973H I2C 10-bit Slave Address Register 0 Reserved CLKR Reserved IBSR0 IBCR0 ITBAL0 ITBAH0 ITMKL0 ITMKH0 ISBA0 ISMK0 IDAR0 Reserved (Continued) 35 R W,R/W R/W R/W R/W R/W R/W R/W R/W I C Interface 0 2 R/W Clock Monitor XXXX0000B 00000000B 00000000B 00000000B 00000000B 11111111B 00111111B 00000000B 01111111B 00000000B 007974H I2C 10-bit Slave Address Mask 007975H Register 0 007976H I C 7-bit Slave Address Register 0 007977H I C 7-bit Slave Address Mask Register 0 007978H I2C Data Register 0 007979H, 00797AH 2 2 MB90860E Series Address Register Abbreviation ICCR0 Access R/W Resource name I2C Interface 0 Initial value 00011111B 00797BH I2C Clock Control Register 0 00797CH to 00797FH 007980H I2C Bus Status Register 1 007981H I2C Bus Control Register 1 007982H 007983H I2C 10-bit Slave Address Register 1 2 Reserved IBSR1 IBCR1 ITBAL1 ITBAH1 ITMKL1 ITMKH1 ISBA1 ISMK1 IDAR1 Reserved ICCR1 Reserved Clock modulator control register (setting prohibited) Clock modulator (using prohibited) R/W I2C Interface 1 00011111B R W,R/W R/W R/W R/W R/W R/W R/W R/W I C Interface 1 2 00000000B 00000000B 00000000B 00000000B 11111111B 00111111B 00000000B 01111111B 00000000B 007984H I C 10-bit Slave Address Mask 007985H Register 1 007986H I C 7-bit Slave Address Register 1 007987H I C 7-bit Slave Address Mask Register 1 007988H I C Data Register 1 007989H, 00798AH 00798BH I2C Clock Control Register 1 00798CH to 0079C1H 0079C2H 0079C3H to 0079DFH 0079E0H Detect Address Setting 0 0079E1H Detect Address Setting 0 0079E2H Detect Address Setting 0 0079E3H Detect Address Setting 1 0079E4H Detect Address Setting 1 0079E5H Detect Address Setting 1 0079E6H Detect Address Setting 2 0079E7H Detect Address Setting 2 0079E8H Detect Address Setting 2 0079E9H to 0079EFH 2 2 2 CMCR R, R/W 0001X000B Reserved PADR0 PADR0 PADR0 PADR1 PADR1 PADR1 PADR2 PADR2 PADR2 Reserved (Continued) R/W R/W R/W R/W R/W R/W R/W R/W R/W Address Match Detection 0 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 36 MB90860E Series (Continued) Address Register Abbreviation PADR3 PADR3 PADR3 PADR4 PADR4 PADR4 PADR5 PADR5 PADR5 Reserved Access R/W R/W R/W R/W R/W R/W R/W R/W R/W Address Match Detection 1 Resource name Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0079F0H Detect Address Setting 3 0079F1H Detect Address Setting 3 0079F2H Detect Address Setting 3 0079F3H Detect Address Setting 4 0079F4H Detect Address Setting 4 0079F5H Detect Address Setting 4 0079F6H Detect Address Setting 5 0079F7H Detect Address Setting 5 0079F8H Detect Address Setting 5 0079F9H to 007FFFH Notes : • Initial value of “X” represents unknown value. • Any write access to reserved addresses in I/O map should not be performed. A read access to reserved addresses results in reading “X”. 37 MB90860E Series ■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER Interrupt cause Reset INT9 instruction Exception (Reserved) (Reserved) Input Capture 6 Input Capture 7 I2C0 (Reserved) 16-bit Reload Timer 0 16-bit Reload Timer 1 16-bit Reload Timer 2 16-bit Reload Timer 3 PPG 0/1/4/5 PPG 2/3/6/7 PPG 8/9/C/D PPG A/B/E/F Time Base Timer External Interrupt 0 to 3, 8 to 11 Watch Timer External Interrupt 4 to 7, 12 to 15 8/10-bit A/D Converter I/O Timer 0, I/O Timer 1 Input Capture 4/5, I2C1 Output Compare 0/1/4/5 Input Capture 0 to 3 Output Compare 2/3/6/7 UART 0 Reception UART 0 Transmission UART 1 Reception / UART 3 Reception UART 1 Transmission / UART 3 Transmission EI2OS clear N N N N N Y1 Y1 N N Y1 Y1 Y1 Y1 N N N N N Y1 N Y1 Y1 N Y1 Y1 Y1 Y1 Y2 Y1 Y2 Y1 DMA ch number ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0 1 2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 3 ⎯ 4 5 ⎯ 6 7 8 9 10 11 12 13 Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H ICR13 FFFF64H (Continued) 0000BDH Interrupt control register Number ⎯ ⎯ ⎯ ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 Address ⎯ ⎯ ⎯ 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 38 MB90860E Series (Continued) Interrupt cause UART 2 Reception / UART 4 Reception UART 2 Transmission / UART 4 Transmission Flash Memory Delayed interrupt Y1 : Usable Y2 : Usable, with EI2OS stop function N : Unusable Notes : • The peripheral resources sharing the ICR register have the same interrupt level. • When two peripheral resources share the ICR register, only one can use Extended Intelligent I/O Service at a time. • When either of the two peripheral resources sharing the ICR register specifies Extended Intelligent I/O Service, the other one cannot use interrupts. EI2OS clear Y2 Y1 N N DMA ch number 14 15 ⎯ ⎯ Interrupt vector Number #39 #40 #41 #42 Address FFFF60H ICR14 FFFF5CH FFFF58H FFFF54H ICR15 0000BFH 0000BEH Interrupt control register Number Address 39 MB90860E Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol VCC Power supply voltage*1 AVCC AVRH, AVRL Input voltage*1 Output voltage*1 Maximum Clamp Current Total Maximum Clamp Current “L” level maximum output current “L” level average output current “L” level maximum overall output current “L” level average overall output current “H” level maximum output current “H” level average output current “H” level maximum overall output current “H” level average overall output current Power consumption Operating temperature Storage temperature VI VO ICLAMP Σ|ICLAMP| IOL IOLAV ΣIOL ΣIOLAV IOH IOHAV ΣIOH ΣIOHAV PD TA TSTG Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 −4.0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ −40 −55 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 +4.0 40 15 4 100 50 −15 −4 −100 −50 340 +105 +150 Unit V V V V V mA mA mA mA mA mA mA mA mA mA mW °C °C VCC = AVCC*2 AVCC ≥ AVRH, AVCC ≥ AVRL, AVRH ≥ AVRL *3 *3 *5 *5 *4 *4 *4 *4 *4 *4 *4 *4 Remarks *1 : This parameter is based on VSS = AVSS = 0 V. *2 : Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on. *3 : VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *4 : Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA1 (Continued) 40 MB90860E Series (Continued) *5 : • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57 (evaluation device : P50 to P55) , P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA1 • Use within recommended operating conditions. • Use at DC voltage (current) • The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. • Care must be taken not to leave the +B input pin open. • Sample recommended circuits: • Input/output equivalent circuits Protective diode VCC Limiting resistance +B input (0 V to 16 V) P-ch N-ch R WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 41 MB90860E Series 2. Recommended Conditions (VSS = AVSS = 0 V) Parameter Symbol Value Min 4.0 VCC, AVCC 3.5 4.5 3.0 Typ 5.0 5.0 5.0 ⎯ ⎯ ⎯ Max 5.5 5.5 5.5 5.5 Unit V V V V µF °C Remarks Under normal operation Under normal operation, when not using the A/D converter and not Flash programming. When External bus is used. Maintains RAM data in stop mode Use a ceramic capacitor or capacitor of better AC characteristics. Capacitor at the VCC should be greater than this capacitor. Power supply voltage Smooth capacitor CS 0.1 −40 1.0 +105 Operating temperature TA C CS C Pin Connection Diagram WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 42 MB90860E Series 3. DC Characteristics (TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Parameter Symbol Pin Condition Value Min Typ Max Unit Remarks Port inputs if CMOS hysteresis input levels are selected (except P12, P44, P45, P46, P47, P50, P82, P83) Port inputs if Automotive input levels are selected Port inputs if TTL input levels are selected P12, P50, P82, P85 inputs if CMOS input levels are selected P44, P45, P46, P47 inputs if CMOS hysteresis input levels are selected RST input pin (CMOS hysteresis) MD input pin Port inputs if CMOS hysteresis input levels are selected (except P12, P44, P45, P46, P47, P50, P82, P83) Port inputs if Automotive input levels are selected Port inputs if TTL input levels are selected P12, P50, P82, P85 inputs if CMOS input levels are selected P44, P45, P46, P47 inputs if CMOS hysteresis input levels are selected RST input pin (CMOS hysteresis) MD input pin VIHS ⎯ ⎯ 0.8 VCC ⎯ VCC + 0.3 V VIHA Input H voltage (At VCC = 5 V ± 10%) VIHT VIHS ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.8 VCC 2.0 0.7 VCC ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 V V V VIHI VIHR VIHM 0.7 VCC 0.8 VCC VCC − 0.3 VSS − 0.3 V V V VILS 0.2 VCC V VILA Input L voltage (At VCC = 5 V ± 10%) VILT VILS ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Normal outputs ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.5 VCC 0.8 0.3 VCC V V V VILI VILR VILM Output H voltage Output H voltage Output L voltage Output L voltage VOH VOHI VOL VOLI 0.3 VCC 0.2 VCC VSS + 0.3 ⎯ ⎯ 0.4 0.4 V V V V V V V VCC = 4.5 V, VCC − 0.5 IOH = −4.0 mA I2C current VCC = 4.5 V, VCC − 0.5 outputs IOH = −3.0 mA Normal outputs VCC = 4.5 V, IOL = 4.0 mA ⎯ ⎯ I2C current VCC = 4.5 V, outputs IOL = 3.0 mA (Continued) 43 MB90860E Series (Continued) Parameter Input leak current Pull-up resistance Symbol IIL (TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Pin ⎯ P00 to P07, P10 to P17, P20 to P27, P30 to P37, RST MD2 Condition VCC = 5.5 V, VSS < VI < VCC ⎯ Value Min −1 Typ ⎯ Max +1 Unit Remarks µA kΩ RUP 25 50 100 Pull-down resistance RDOWN ⎯ VCC = 5.0 V, Internal frequency : 24 MHz, At normal operation. 25 50 100 Except kΩ Flash devices mA Flash devices Flash devices ⎯ ⎯ ⎯ ⎯ ⎯ 55 70 ICC VCC = 5.0 V, Internal frequency : 24 MHz, At writing FLASH memory. VCC = 5.0 V, Internal frequency : 24 MHz, At erasing FLASH memory. 70 85 mA 75 90 mA ICCS VCC = 5.0 V, Internal frequency : 24 MHz, At Sleep mode. VCC = 5.0 V, Internal frequency : 2 MHz, At Main Timer mode VCC VCC = 5.0 V, Internal frequency : 24 MHz, At PLL Timer mode, external frequency = 4 MHz VCC = 5.0 V Internal frequency : 8 kHz, At sub operation TA = +25°C VCC = 5.0 V Internal frequency : 8 kHz, At sub sleep TA = +25°C VCC = 5.0 V Internal frequency : 8 kHz, At watch mode TA = +25°C VCC = 5.0 V, At Stop mode, TA = +25°C Other than C, AVCC, AVSS, AVRH, AVRL, VCC, VSS, ⎯ 25 35 mA ICTS 0.3 0.8 mA Power supply current* ICTSPLL6 ⎯ 4 7 mA ICCL ⎯ 70 140 µA ICCLS ⎯ 20 50 µA ICCT ⎯ 10 35 µA ICCH ⎯ 7 25 µA Input capacity CIN ⎯ 5 15 pF * : The power supply current is measured with an external clock. 44 MB90860E Series 4. AC Characteristics (1) Clock Timing (TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Parameter Symbol Pin X0, X1 Clock frequency fC X0, X1 fCL X0A, X1A X0, X1 Clock cycle time tCYL X0, X1 tCYLL Input clock pulse width Input clock rise and fall time Internal operating clock frequency (machine clock) Internal operating clock cycle time (machine clock) PWH, PWL PWHL, PWLL tCR, tCF fCP fCPL tCP tCPL X0A, X1A X0 X0A X0 ⎯ ⎯ ⎯ ⎯ 41.67 10 10 5 ⎯ 1.5 ⎯ 41.67 20 ⎯ 30.5 ⎯ 15.2 ⎯ ⎯ 8.192 ⎯ 122.1 333 — ⎯ ⎯ 5 24 50 666 ⎯ ns µs ns µs ns MHz kHz ns µs Duty ratio is about 30% to 70%. When using external clock When using main clock When using sub clock When using main clock When using sub clock 3 — 62.5 ⎯ 32.768 ⎯ 24 100 333 MHz kHz ns When using an oscillation circuit When using an external clock Value Min 3 Typ ⎯ Max 16 Unit MHz Remarks When using an oscillation circuit When using an external clock* * : When selecting the PLL clock, the range of clock frequency is limited. Use this product within range as mentioned in “Relation among external clock frequency and machine clock frequency”. tCYL X0 PWH tCF PWL tCR 0.8 VCC 0.2 VCC tCYLL X0A PWHL tCF PWLL tCR 0.8 VCC 0.2 VCC Clock Timing 45 MB90860E Series • Guaranteed PLL operation range Guaranteed operation range 5.5 4.0 3.5 Guaranteed PLL operation range Guaranteed A/D Converter operation range Power supply voltage VCC (V) 1.5 4 Machine clock fCP (MHz) 24 Guaranteed operation range of MB90860E series Guaranteed oscillation frequency range ×6 ×4 ×3 ×2 ×1 24 Internal clock fCP (MHz) 16 12 8 4.0 1.5 3 4 8 12 16 24 External clock fC (MHz) * × 1/2 (PLL off) * : When using crystal oscillator or ceramic oscillator, the maximum oscillation clock frequency is 16 MHz 46 MB90860E Series (2) Reset Standby Input (TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0.0 V) Parameter Symbol Pin Value Min 500 Reset input time tRSTL RST Oscillation time of oscillator* + 100 µs 100 Max ⎯ ⎯ ⎯ Unit ns ns µs Remarks Under normal operation In Stop mode, Sub Clock mode, Sub Sleep mode and Watch mode In Time Timer mode * : Oscillation time of oscillator is the time that the amplitude reaches 90%. In the crystal oscillator, the oscillation time is between several ms and to tens of ms. In ceramic oscillators, the oscillation time is between hundreds of µs to several ms. With an external clock, the oscillation time is 0 ms. Under normal operation: tRSTL RST 0.2 VCC 0.2 VCC In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode, Power-on: tRSTL RST 0.2 VCC 90% of amplitude 0.2 VCC X0 Internal operation clock Oscillation time of oscillator 100 µs Oscillation stabilization waiting time Instruction execution Internal reset 47 MB90860E Series (3) Power On Reset (TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0.0 V) Parameter Power on rise time Power off time Symbol tR tOFF Pin VCC VCC Condition ⎯ Value Min 0.05 1 Max 30 ⎯ Unit ms ms Due to repetitive operation Remarks tR 2.7 V 0.2 V 0.2 V tOFF If you change the power supply voltage too rapidly, a power on reset may occur. We recommend that you startup smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within 1 V/s, you can operate 0.2 V VCC VCC 3V VSS Holds RAM data We recommend a rise of 50 mV/ms maximum. (4) Clock Output Timing (TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, fCP ≤ 24 MHz) Parameter Cycle time CLK ↑ → CLK ↓ Symbol tCYC tCHCL Pin CLK CLK Condition ⎯ ⎯ Value Min 62.5 41.76 20 13 Max ⎯ ⎯ ⎯ ⎯ Unit ns ns ns ns Remarks fCP = 16 MHz fCP = 24 MHz fCP = 16 MHz fCP = 24 MHz tCYC tCHCL CLK 2.4 V 0.8 V 2.4 V 48 MB90860E Series (5) Bus Timing (Read) Parameter ALE pulse width Valid address → ALE ↓ time ALE ↓ → Address valid time Valid address → RD ↓ time Valid address → Valid data input RD pulse width RD ↓ → Valid data input RD ↑ → Data hold time RD ↓ → ALE ↑ time RD ↑ → Address valid time Valid address → CLK ↑ time RD ↓ → CLK ↑ time ALE ↓ → RD ↓ time Symbol tLHLL tAVLL tLLAX tAVRL tAVDV tRLRH tRLDV tRHLH tRHAX tAVCH tRLCH tLLRL (TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, fCP ≤ 24 MHz) Value Pin Condition Unit Min Max ALE ALE, A23 to A16, AD15 to AD00 ALE, AD15 to AD00 A23 to A16, AD15 to AD00, RD A23 to A16, AD15 to AD00 RD RD, AD15 to AD00 RD, ALE RD, A23 to A16 A23 to A16, AD15 to AD00, CLK RD, CLK ALE, RD tAVCH CLK 2.4 V tRLCH 2.4 V tCP/2 − 10 tCP/2 − 20 tCP/2 − 15 tCP − 15 ⎯ ⎯ 3 tCP/2 − 20 ⎯ 0 tCP/2 − 15 tCP/2 − 10 tCP/2 − 16 tCP/2 − 15 tCP/2 − 15 ⎯ ⎯ ⎯ ⎯ 5 tCP/2 − 60 ⎯ 3 tCP/2 − 50 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ns ns ns ns ns ns ns ns ns ns ns ns ns tRHDX RD, AD15 to AD00 tAVLL ALE 2.4 V tLHLL tAVRL RD tLLAX 2.4 V 0.8 V tRLRH 2.4 V 0.8 V tLLRL tRHLH 2.4 V tRHAX A23 to A16 2.4 V 0.8 V tRLDV tAVDV AD15 to AD00 2.4 V 0.8 V 2.4 V Address 0.8 V VIH VIL Read data 2.4 V 0.8 V tRHDX VIH VIL 49 MB90860E Series (6) Bus Timing (Write) (TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, fCP ≤ 24 MHz) Value Symbol Pin Condition Unit Min Max tAVWL tWLWH tDVWH tWHDX tWHAX tWHLH tWLCH A23 to A16, AD15 to AD00, WR WR AD15 to AD00, WR AD15 to AD00, WR A23 to A16, WR WR, ALE WR, CLK ⎯ tCP−15 3 tCP/2 − 20 3 tCP/2 − 20 15 tCP/2 − 10 tCP/2 − 15 tCP/2 − 15 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ns ns ns ns ns ns ns Parameter Valid address → WR ↓ time WR pulse width Valid data output → WR ↑ time WR ↑ → Data hold time WR ↑ → Address valid time WR ↑ → ALE ↑ time WR ↓ → CLK ↑ time tWLCH 2.4 V CLK tWHLH ALE 2.4 V tAVWL WR (WRL, WRH) 0.8 V tWLWH 2.4 V tWHAX A23 to A16 2.4 V 0.8 V tDVWH AD15 to AD00 2.4 V 0.8 V 2.4 V Address 0.8 V Write data 2.4 V 0.8 V tWHDX 2.4 V 0.8 V 50 MB90860E Series (7) Ready Input Timing Symbol tRYHS tRYHH (TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, fCP ≤ 24 MHz) Rated Value Test Pin Units Remarks Condition Min Max RDY RDY 45 ⎯ 32 0 ⎯ ⎯ ⎯ ns ns ns fCP = 16 MHz fCP = 24 MHz Parameter RDY setup time RDY hold time Note : If the RDY setup time is insufficient, use the auto-ready function. CLK 2.4 V ALE RD/WR tRYHS RDY When WAIT is not used. VIH tRYHH VIH RDY When WAIT is used. VIL 51 MB90860E Series (8) Hold Timing (TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, fCP ≤ 24 MHz) Value Symbol Pin Condition Units Min Max tXHAL tHAHV HAK HAK ⎯ 30 tCP tCP 2 tCP ns ns Parameter Pin floating → HAK ↓ time HAK ↑ time → Pin valid time Note : There is more than 1 cycle from when HRQ reads in until the HAK is changed. HAK 0.8 V tXHAL Each pin 2.4 V 0.8 V High-Z 2.4 V tHAHV 2.4 V 0.8 V 52 MB90860E Series (9) UART0/1/2/3/4 (TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, fCP ≤ 24 MHz) Value Symbol Pin Condition Unit Min Max tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX SCK0 to SCK4 SCK0 to SCK4, SOT0 to SOT4 SCK0 to SCK4, SIN0 to SIN4 SCK0 to SCK4, SIN0 to SIN4 SCK0 to SCK4 SCK0 to SCK4 SCK0 to SCK4, SOT0 to SOT4 SCK0 to SCK4, SIN0 to SIN4 SCK0 to SCK4, SIN0 to SIN4 External clock operation output pins are CL = 80 pF + 1 TTL. Internal clock operation output pins are CL = 80 pF + 1 TTL. 8 tCP −80 100 60 4 tCP 4 tCP ⎯ 60 60 ⎯ +80 ⎯ ⎯ ⎯ ⎯ 150 ⎯ ⎯ ns ns ns ns ns ns ns ns ns Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → Valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → Valid SIN hold time Notes : • AC characteristic in CLK synchronized mode. • CL is load capacity value of pins when testing. tSCYC SCK 2.4 V 0.8 V tSLOV SOT 2.4 V 0.8 V tIVSH SIN VIH VIL tSHIX VIH VIL 0.8 V Internal Shift Clock Mode 53 MB90860E Series tSLSH SCK VIL tSLOV SOT 2.4 V 0.8 V tIVSH SIN VIH VIL VIL VIH tSHSL VIH tSHIX VIH VIL External Shift Clock Mode (10) Trigger Input Timing (TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0.0 V) Value Pin Condition Unit Min Max INT0 to INT15, INT0R to INT15R, ADTG ⎯ 5 tCP ⎯ ns Parameter Symbol tTRGH tTRGL Input pulse width VIH VIH VIL tTRGH tTRGL VIL INT0 to INT15, INT0R to INT15R, ADTG 54 MB90860E Series (11) Timer Related Resource Input Timing (TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V) Value Parameter Symbol Pin Condition Unit Min Max Input pulse width tTIWH tTIWL TIN0 to TIN3, IN0 to IN7 ⎯ 4 tCP ⎯ ns VIH VIH VIL tTIWH tTIWL VIL TIN0 to TIN3, IN0 to IN7 (12) Timer Related Resource Output Timing (TA = –40°C to +105°C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0.0 V) Value Parameter Symbol Pin Condition Unit Min Max CLK ↑ → TOUT change time tTO TOT0 to TOT3, PPG0 to PPGF ⎯ 30 ⎯ ns CLK 2.4 V TOT0 to TOT3, PPG0 to PPGF tTO 2.4 V 0.8 V 55 MB90860E Series (13) I2C Timing (TA = –40°C to +105°C, VCC = 5.0 V ± 10%, VSS = 0.0 V) Standard-mode Fast-mode*1 Condition Unit Min Max Min Max 0 4.0 4.7 4.0 4.7 R = 1.7 kΩ, C = 50 pF*2 0 250 4.0 4.7 100 ⎯ ⎯ ⎯ ⎯ 3.45*3 ⎯ ⎯ ⎯ 0 0.6 1.3 0.6 0.6 0 100 0.6 1.3 400 ⎯ ⎯ ⎯ ⎯ 0.9*4 ⎯ ⎯ ⎯ kHz µs µs µs µs µs ns µs µs Parameter SCL clock frequency Hold time (repeated) START condition SDA ↓ → SCL ↓ “L” width of the SCL clock “H” width of the SCL clock Set-up time for a repeated START condition SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓ ↑ Data set-up time SDA ↓ ↑ → SCL ↑ Set-up time for STOP condition SCL ↑ → SDA ↑ Bus free time between a STOP and START condition Symbol fSCL tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tSUSTO tBUS *1 : For use at over 100 kHz, set the machine clock to at least 6 MHz. *2 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines. *3 : The maximum tHDDAT have only to be met if the device does not stretch the “L” width (tLOW) of the SCL signal. *4 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSUDAT ≥ 250 ns must then be met. SDA tBUS tLOW SCL tSUDAT tHDSTA tHDSTA tHDDAT tHIGH tSUSTA tSUSTO 56 MB90860E Series 5. A/D Converter (TA = −40 °C to +105 °C, 3.0 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Parameter Resolution Total error Nonlinearity error Differential nonlinearity error Zero reading voltage Full scale reading voltage Compare time Sampling time Analog port input current Analog input voltage range Reference voltage range Power supply current Reference voltage current Offset between input channels Symbol ⎯ ⎯ ⎯ ⎯ VOT VFST ⎯ ⎯ IAIN VAIN ⎯ ⎯ IA IAH IR IRH ⎯ Pin ⎯ ⎯ ⎯ ⎯ Value Min ⎯ ⎯ ⎯ ⎯ Typ ⎯ ⎯ ⎯ ⎯ Max 10 ±3.0 ±2.5 ±1.9 Unit bit LSB LSB LSB Remarks AN0 to AN23 AVRL − 1.5 AVRL + 0.5 AVRL + 2.5 LSB AN0 to AN23 AVRH − 3.5 AVRH − 1.5 AVRH + 0.5 LSB ⎯ ⎯ AN0 to AN23 AN0 to AN23 AVRH AVRL AVCC AVCC AVRH AVRH AN0 to AN23 1.0 2.0 0.5 1.2 −0.3 AVRL AVRL + 2.7 0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 3.5 ⎯ 600 ⎯ ⎯ 16500 µs µs µA V V V mA µA µA µA LSB * * 4.5 V ≤ AVCC ≤ 5.5 V 4.0 V ≤ AVCC < 4.5 V 4.5 V ≤ AVCC ≤ 5.5 V 4.0 V ≤ AVCC < 4.5 V ∞ +0.3 AVRH AVCC AVRH − 2.7 7.5 5 900 5 4 * : IF A/D convertor is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVRH = 5.0 V) . Note : The accuracy gets worse as AVRH − AVRL becomes smaller. 57 MB90860E Series 6. Definition of A/D Converter Terms Resolution Non linearity error Differential linearity error Total error Zero reading voltage Full scale reading voltage : Analog variation that is recognized by an A/D converter. : Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” ) and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion characteristics. : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. : Difference between an actual value and an ideal value. A total error includes zero transition error, full-scale transition error, and linear error. : Input voltage which results in the minimum conversion value. : Input voltage which results in the maximum conversion value. Total error 3FFH 3FEH 3FDH Digital output {1 LSB × (N − 1) + 0.5 LSB} Actual conversion characteristics 1.5 LSB 004H 003H 002H 001H 0.5 LSB AVRL Analog input VNT (Actually-measured value) Actual conversion characteristics Ideal characteristics AVRH Total error of digital output “N” = VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB AVRH − AVRL 1 LSB (Ideal value) = [V] 1024 VOT (Ideal value) = AVRL + 0.5 LSB [V] VFST (Ideal value) = AVRH − 1.5 LSB [V] [LSB] VNT : A voltage at which digital output transitions from (N − 1) to N. (Continued) 58 MB90860E Series (Continued) Non linearity error 3FFH 3FEH 3FDH Digital output Actual conversion characteristics {1 LSB × (N − 1) + VOT } N + 1H VFST (actual measurement value) VNT (actual measurement value) Actual conversion characteristics Actual conversion characteristics Differential linearity error Ideal characteristics Digital output NH 004H 003H 002H N − 1H V (N + 1) T (actual measurement value) VNT (actual measurement value) Actual conversion characteristics AVRH Analog input Ideal characteristics 001H VOT (actual measurement value) AVRL Analog input AVRH N − 2H AVRL Non linearity error of digital output N = Differential linearity error of digital output N = 1 LSB = VNT − {1 LSB × (N − 1) + VOT} 1 LSB V (N+1) T − VNT 1 LSB VFST − VOT 1022 −1 LSB [LSB] [V] [LSB] VOT : Voltage at which digital output transits from “000H” to “001H.” VFST : Voltage at which digital output transits from “3FEH” to “3FFH.” 59 MB90860E Series 7. Notes on A/D Converter Section Use the device with external circuits of the following output impedance for analog inputs : Recommended output impedance of external circuits are : Approx. 1.5 kΩ or lower (4.0 V ≤ AVCC ≤ 5.5 V, sampling period ≤ 0.5 µs) If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors and on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high as internal capacitor. If output impedance of an external circuit is too high, a sampling period for an analog voltage may be insufficient. • Analog input circuit model Analog input R Comparator C 4.5 V ≤ AVCC ≤ 5.5 V : R = 2.52 kΩ, C = 10.7 pF : : 4.0 V ≤ AVCC < 4.5 V : R = 13.6 kΩ, C = 10.7 pF : : Note : Use the values in the figure only as a guideline. 8. Flash Memory Program/Erase Characteristics Parameter Sector erase time Chip erase time Word (16-bit width) programming time Programs/Erase cycle Flash Data Retention Time ⎯ Average TA = +85 °C TA = +25 °C VCC = 5.0 V Conditions Value Min ⎯ ⎯ ⎯ 10000 20 Typ 1 9 16 ⎯ ⎯ Max 15 ⎯ 3600 ⎯ ⎯ Unit s s µs cycle Year * Remarks Excludes programming prior to erasure Excludes programming prior to erasure Except for the over head time of the system * : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at +85 °C) . 60 MB90860E Series ■ EXAMPLE CHARACTERISTICS • MB90F867E, MB90F867ES ICC − VCC TA = +25 °C, at external clock operating f = Internal operation frequency 70 60 50 f = 24 MHz f = 20 MHz f = 16 MHz f = 12 MHz f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz 2.5 3.5 4.5 5.5 6.5 100 90 80 70 60 50 40 30 20 10 0 ICCL − VCC TA = +25 °C, at external clock operating f = Internal operation frequency ICC (mA) 40 30 20 10 0 ICCL ( A) f = 8 kHz 2.5 3.5 4.5 5.5 6.5 VCC (V) VCC (V) ICCS − VCC TA = +25 °C, at external clock operating f = Internal operation frequency 35 30 f = 24 MHz f = 20 MHz f = 16 MHz f = 12 MHz f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz 2.5 3.5 4.5 5.5 6.5 50 45 40 35 30 25 20 15 10 5 0 ICCLS − VCC TA = +25 °C, at external clock operating f = Internal operation frequency ICCS (mA) 20 15 10 5 0 ICCLS ( A) 25 f = 8 kHz 2.5 3.5 4.5 5.5 6.5 VCC (V) VCC (V) ICTS − VCC TA = +25 °C, at external clock operating f = Internal operation frequency 400 350 300 250 200 150 100 50 0 2.5 3.5 4.5 5.5 6.5 20 18 16 14 12 10 8 6 4 2 0 ICCT − VCC TA = +25 °C, at external clock operating f = Internal operation frequency ICCT ( A) ICTS ( A) f = 2 MHz f = 8 kHz 2.5 3.5 4.5 5.5 6.5 VCC (V) VCC (V) ICTSPLL6 − VCC TA = +25 °C, at external clock operating f = Internal operation frequency 10 9 8 7 6 5 4 3 2 1 0 10 9 8 7 6 5 4 3 2 1 0 ICCH − VCC TA = +25 °C, at stop ICTSPLL6 (mA) f = 24 MHz 2.5 3.5 4.5 5.5 6.5 ICCH ( A) 2.5 3.5 4.5 5.5 6.5 VCC (V) VCC (V) 61 MB90860E Series • MB90867E, MB90867ES ICC − VCC TA = +25 °C, at external clock operating f = Internal operation frequency 70 60 f = 24 MHz 50 100 90 80 70 60 50 40 30 20 10 0 ICCL − VCC TA = +25 °C, at external clock operating f = Internal operation frequency ICC (mA) 40 30 20 10 0 2.5 3.5 4.5 5.5 ICCL (µA) f = 20 MHz f = 16 MHz f = 12 MHz f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz 6.5 f = 8 kHz 2.5 3.5 4.5 5.5 6.5 VCC (V) VCC (V) ICCS − VCC TA = +25 °C, at external clock operating f = Internal operation frequency 35 30 f = 24 MHz f = 20 MHz f = 12 MHz f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz 2.5 3.5 4.5 5.5 6.5 f = 16 MHz 50 45 40 35 30 25 20 15 10 5 0 ICCLS − VCC TA = +25 °C, at external clock operating f = Internal operation frequency ICCS (mA) 25 20 15 10 5 0 ICCLS (µA) f = 8 kHz 2.5 3.5 4.5 5.5 6.5 VCC (V) VCC (V) ICTS − VCC TA = +25 °C, at external clock operating f = Internal operation frequency 400 350 300 20 18 16 14 12 10 8 6 4 2 0 ICCT − VCC TA = +25 °C, at external clock operating f = Internal operation frequency ICTS (µA) 250 200 150 100 50 0 2.5 3.5 4.5 5.5 ICCT (µA) f = 2 MHz f = 8 kHz 6.5 2.5 3.5 4.5 5.5 6.5 VCC (V) VCC (V) ICTSPLL6 − VCC TA = +25 °C, at external clock operating f = Internal operation frequency 10 9 8 7 6 5 4 3 2 1 0 10 9 8 7 6 5 4 3 2 1 0 ICCH − VCC TA = +25 °C, at stop ICTSPLL6 (mA) f = 24 MHz 2.5 3.5 4.5 5.5 6.5 ICCH (µA) 2.5 3.5 4.5 5.5 6.5 VCC (V) VCC (V) 62 MB90860E Series • I/O characteristics (VCC−VOH) − IOH TA = +25 °C, VCC = 4.5 V 800 700 1000 900 800 700 600 500 400 300 200 100 0 VOL − IOL TA = +25 °C, VCC = 4.5 V VCC VOH (mV) 600 500 400 300 200 100 0 0 1 2 3 4 5 6 7 8 9 10 VOL (mV) 0 1 2 3 4 5 6 7 8 9 10 IOH (mA) IOL (mA) Automotive VIN − VCC TA = +25 °C 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 CMOS VIN − VCC UART-SIN pin, other than I2C pin TA = +25 °C VIHA VILA VIN (V) VIHS VIN (V) VILS 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 VCC (V) VCC (V) TTL VIN − VCC TA = +25 °C 2.5 2.3 2.0 1.8 1.5 1.3 1.0 0.8 0.5 0.3 0.0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.5 3.0 CMOS VIN − VCC UART-SIN pin, I2C pin TA = +25 °C VIHS VIN (V) VIHT VILT VIN (V) VILS 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 VCC (V) VCC (V) 63 MB90860E Series ■ ORDERING INFORMATION Part number MB90F867EPF MB90F867ESPF MB90F867EPFV MB90F867ESPFV MB90867EPF MB90867ESPF MB90867EPFV MB90867ESPFV MB90V340E-101 MB90V340E-102 Package 100-pin Plastic QFP (FPT-100P-M06) Flash memory product 100-pin Plastic LQFP (FPT-100P-M05) 100-pin Plastic QFP (FPT-100P-M06) MASK ROM product 100-pin Plastic LQFP (FPT-100P-M05) 299-pin Ceramic PGA (PGA-299C-A01) Evaluation product Remarks 64 MB90860E Series ■ PACKAGE DIMENSIONS 100-pin plastic QFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Code (Reference) 0.65 mm 14.00 × 20.00 mm Gullwing Plastic mold 3.35 mm MAX P-QFP100-14×20-0.65 (FPT-100P-M06) 100-pin plastic QFP (FPT-100P-M06) 23.90±0.40(.941±.016) * 20.00±0.20(.787±.008) 80 51 Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 81 50 0.10(.004) 17.90±0.40 (.705±.016) *14.00±0.20 (.551±.008) INDEX Details of "A" part 100 31 1 30 0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8˚ 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.25±0.20 (.010±.008) (Stand off) 0.65(.026) 0.32±0.05 (.013±.002) 0.13(.005) M "A" C 2002 FUJITSU LIMITED F100008S-c-5-5 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html (Continued) 65 MB90860E Series (Continued) 100-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.50 mm 14.0 × 14.0 mm Gullwing Plastic mold 1.70 mm MAX 0.65g P-LFQFP100-14×14-0.50 (FPT-100P-M05) Code (Reference) 100-pin plastic LQFP (FPT-100P-M05) 16.00±0.20(.630±.008)SQ * 14.00±0.10(.551±.004)SQ 75 51 Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 76 50 0.08(.003) Details of "A" part INDEX 1.50 –0.10 .059 –.004 (Mounting height) 26 +0.20 +.008 100 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) 0˚~8˚ "A" 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 1 25 0.50(.020) 0.20±0.05 (.008±.002) 0.08(.003) M 0.145±0.055 (.0057±.0022) C 2003 FUJITSU LIMITED F100007S-c-4-6 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 66 MB90860E Series The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Edited Business Promotion Dept. F0610