MB90F897PMT

FUJITSU MICROELECTRONICS DATA SHEET DS07-13731-5E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90895 Series MB90F897/F897S/F897Y*1/F897YS*1/ MB90V495G ■ DESCRIPTION MB90895 series devices are 16-bit general-purpose microcontrollers designed for applications which need highspeed real-time processing. The devices of this series are high-performance 16-bit CPU microcontrollers employing of the dual operation flash memory and CAN controller on LQFP-48 small package. The system, inheriting the architecture of F2MC*2 family, employs additional instruction ready for high-level languages, expanded addressing mode, enhanced multiply-divide instructions, and enriched bit-processing instructions. Furthermore, employment of 32-bit accumulator achieves processing of long-word data (32 bits). The peripheral resources of MB90895 series include the following: 8/10-bit A/D converter, UART0/UART1 (SCI), 8/16-bit PPG timer, 16-bit input-output timer (16-bit free-run timer, input capture 0, 1, 2, 3 (ICU)), and CAN controller. *1 : These devices are under development. This datasheet provides preliminary information for the devices under development. *2 : “F2MC” is the abbreviation of FUJITSU Flexible Microcontroller. ■ FEATURES • Models that support +125°C (MB90F897/S) • Models that support +150°C (MB90F897Y/YS) • Clock • Built-in PLL clock frequency multiplication circuit • Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and multiplication of 1 to 4 times of oscillation clock (for 4-MHz oscillation clock, 4 MHz to 16 MHz). • Operation by sub-clock (8.192 kHz) is allowed. (MB90F897/Y) • Minimum execution time of instruction: 62.5 ns (when operating with 4-MHz oscillation clock, and 4-time multiplied PLL clock). • 16 Mbyte CPU memory space • 24-bit internal addressing (Continued) For the information for microcontroller supports, see the following web site. This web site includes the "Customer Design Review Supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development. http://edevice.fujitsu.com/micom/en-support/ Copyright©2004-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2009.8 MB90895 Series (Continued) • Instruction system best suited to controller • Wide choice of data types (bit, byte, word, and long word) • Wide choice of addressing modes (23 types) • Enhanced multiply-divide instructions and RETI instructions • Enhanced high-precision computing with 32-bit accumulator • Instruction system compatible with high-level language (C language) and multitask • Employing system stack pointer • Enhanced various pointer indirect instructions • Barrel shift instructions • Increased processing speed • 4-byte instruction queue • Powerful interrupt function with 8 levels and 34 factors • Automatic data transfer function independent of CPU • Extended intelligent I/O service function (EI2OS): Maximum of 16 channels • Low power consumption (standby) mode • Sleep mode (a mode that halts CPU operating clock) • Time-base timer mode (a mode that operates oscillation clock, sub clock, time-base timer and watch timer only) • Watch mode (a mode that operates sub clock and watch timer only) • Stop mode (a mode that stops oscillation clock and sub clock) • CPU intermittent operation mode • Process • CMOS technology • I/O port • General-purpose input/output port (CMOS output) : MB90F897/Y : 34 ports (including 4 high-current output ports) MB90F897S/YS : 36 ports (including 4 high-current output ports) • Timer • Time-base timer, watch timer, watchdog timer: 1 channel • 8/16-bit PPG timer: 8-bit x 4 channels, or 16-bit x 2 channels • 16-bit reload timer: 2 channels • 16-bit input/output timer - 16-bit free run timer: 1 channel - 16-bit input capture: (ICU): 4 channels Interrupt request is issued upon latching a count value of 16-bit free run timer by detection of an edge on pin input. • CAN controller: 1 channel • Complied with Ver 2.0A and Ver 2.0B CAN specifications • 8 built-in message buffers • Transmission rate of 10 kbps to 1 Mbps (by 16 MHz machine clock) • CAN wake-up • UART0 (SCI), UART1(SCI): 2 channels • Equipped with full-duplex double buffer • Clock-asynchronous or clock-synchronous serial transmission is available. • DTP/External interrupt: 4 channels, CAN wake-up: 1channel • Module for activation of extended intelligent I/O service (EI2OS), and generation of external interrupt. • Delay interrupt generator module • Generates interrupt request for task switching. • 8/10-bit A/D converter: 8 channels • Resolution is selectable between 8-bit and 10-bit. • Activation by external trigger input is allowed. • Conversion time: 6.125 μs (at 16-MHz machine clock, including sampling time) • Program patch function • Address matching detection for 2 address pointers. 2 DS07-13731-5E MB90895 Series ■ PRODUCT LINEUP Part number MB90F897 MB90F897S MB90F897Y (Under development) MB90F897YS (Under development) Flash ROM 64 Kbytes 2 Kbytes CMOS LQFP-48 (pin pitch 0.50 mm) 3.5 V to 5.5 V ⎯ Number of basic instructions : 351 instructions Instruction length : 1 byte to 7 bytes Data bit length : 1 bit, 8 bits, 16 bits Minimum instruction execution time : 62.5 ns (at 16-MHz machine clock) Interrupt processing time : 1.5 μs at minimum (at 16-MHz machine clock) Low power consumption (standby) mode I/O port Sleep mode/Watch mode/Time-base timer mode/ Stop mode/CPU intermittent General-purpose input/output ports (CMOS output) : 34 ports (36 ports*2) including 4 high-current output ports (P14 to P17) 18-bit free-run counter Interrupt cycle : 1.024 ms, 4.096 ms, 16.834 ms, 131.072 ms (with oscillation clock frequency at 4 MHz) Reset generation cycle: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (with oscillation clock frequency at 4 MHz) 16-bit free-run timer Input capture Number of channels: 1 Interrupt upon occurrence of overflow Number of channels: 4 Retaining free-run timer value set by pin input (rising edge, falling edge, and both edges) Number of channels: 2 16-bit reload timer operation Count clock cycle: 0.25 μs, 0.5 μs, 2.0 μs (at 16-MHz machine clock frequency) External event count is allowed. 15-bit free-run counter Interrupt cycle: 31.25 ms, 62.5 ms, 12 ms, 250 ms, 500 ms, 1.0 s, 2.0 s (with 8.192 kHz sub clock) Number of channels: 2 (four 8-bit channels are available also.) PPG operation is allowed with four 8-bit channels or one 16-bit channel. Outputting pulse wave of arbitrary cycle or arbitrary duty is allowed. Count clock: 62.5 ns to 1 μs (with 16 MHz machine clock) Interrupt generator module for task switching. Used for real-time OS. (Continued) PGA256 4.5 V to 5.5 V None MB90V495G Parameter Classification ROM capacity RAM capacity Process Package Operating power supply voltage Special power supply for emulator*1 Evaluation product ⎯ 6 Kbytes CPU functions Time-base timer Watchdog timer 16-bit input/output timer 16-bit reload timer Watch timer 8/16-bit PPG timer Delay interrupt generator module DS07-13731-5E 3 MB90895 Series (Continued) Part number MB90F897 MB90F897S MB90F897Y (Under development) MB90F897YS (Under development) MB90V495G Parameter DTP/External interrupt Number of inputs: 4 Activated by rising edge, falling edge, “H” level or “L” level input. External interrupt or extended intelligent I/O service (EI2OS) is available. Number of channels: 8 Resolution: Selectable 10-bit or 8-bit. Conversion time: 6.125 μs (at 16-MHz machine clock, including sampling time) Sequential conversion of two or more successive channels is allowed. (Setting a maximum of 8 channels is allowed.) Single conversion mode : Selected channel is converted only once. Sequential conversion mode: Selected channel is converted repetitively. Halt conversion mode : Conversion of selected channel is stopped and activated alternately. Number of channels: 1 Clock-synchronous transfer: 62.5 kbps to 2 Mbps Clock-asynchronous transfer: 1,202 bps to 62,500 bps Communication is allowed by bi-directional serial communication function and master/slave type connection. Number of channels: 1 Clock-synchronous transfer: 62.5 kbps to 2 Mbps Clock-asynchronous transfer: 9,615 bps to 500 kbps Communication is allowed by bi-directional serial communication function and master/slave type connection. Complied with Ver 2.0A and Ver 2.0B CAN specifications. 8 built-in message buffers. Transmission rate of 10 kbps to 1 Mbps (by 16 MHz machine clock) CAN wake-up 8/10-bit A/D converter UART0 (SCI) UART1 (SCI) CAN *1 : Settings of DIP switch S2 for using emulation pod MB2145-507. For details, see MB2145-507 Hardware Manual (2.7 Power Pin solely for Emulator). *2 : MB90F897S/YS ■ PACKAGES AND PRODUCT MODELS Package FPT-48P-M26 : Yes, × : No Note : Refer to “ PACKAGE DIMENSION” for details of the package. MB90F897/S/Y/YS 4 DS07-13731-5E MB90895 Series ■ PRODUCT COMPARISON Memory space When testing with test product for evaluation, check the differences between the product and a product to be used actually. Pay attention to the following points: • The MB90V495G has no built-in ROM. However, a special-purpose development tool allows the operations as those of one with built-in ROM. ROM capacity depends on settings on a development tool. • On MB90V495G, an image from FF4000H to FFFFFFH is viewed on 00 bank and an image of FE0000H to FF3FFFH is viewed only on FE bank and FF bank. (Modified on settings of a development tool.) • On MB90F897/S/Y/YS, an image from FF4000H to FFFFFFH is viewed on 00 bank and an image of FF0000H to FF3FFFH is viewed only on FF bank. DS07-13731-5E 5 MB90895 Series ■ PIN ASSIGNMENT (TOP VIEW) AVSS X1A/P36* X0A/P35* P33 P32/SIN0 P31SCK0 P30/SOT0 P44/RX P43/TX P42/SOT1 P41/SCK1 P40/SIN1 48 47 46 45 44 43 42 41 40 39 38 37 *: MB90F897/Y : X1A, X0A MB90F897S/YS : P36, P35 6 P21/TOT0 P22/TIN1 P23/TOT1 P24/INT4 P25/INT5 P26/INT6 P27/INT7 MD2 MD1 MD0 RST VCC 13 14 15 16 17 18 19 20 21 22 23 24 AVCC AVR P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 P37/ADTG P20/TIN0 1 2 3 4 5 6 7 8 9 10 11 12 LQFP-48 36 35 34 33 32 31 30 29 28 27 26 25 P17/PPG3 P16/PPG2 P15/PPG1 P14/PPG0 P13/IN3 P12/IN2 P11/IN1 P10/IN0 X1 X0 C VSS (FPT-48P-M26) DS07-13731-5E MB90895 Series ■ PIN DESCRIPTION Pin No. 1 2 3 to 10 Pin name AVcc AVR P50 to P57 AN0 to AN7 P37 11 ADTG P20 12 TIN0 P21 13 TOT0 P22 14 TIN1 P23 15 TOT1 P24 to P27 INT4 to INT7 MD2 MD1 MD0 RST Vcc Vss C X0 X1 P10 to P13 29 to 32 IN0 to IN3 D D D D D D E Circuit type ⎯ ⎯ Function Vcc power input pin for A/D converter. Power (Vref+) input pin for A/D converter. Use as input for Vcc or lower. General-purpose input/output ports. Functions as analog input pin for A/D converter. Valid when analog input setting is “enabled.” General-purpose input/output ports. Function as an external trigger input pin for A/D converter. Use the pin by setting as input port. General-purpose input/output ports. Function as an event input pin for reload timer 0. Use the pin by setting as input port. General-purpose input/output ports. Function as an event output pin for reload timer 0. Valid only when output setting is “enabled.” General-purpose input/output ports. Function as an event input pin for reload timer 1. Use the pin by setting as input port. General-purpose input/output ports. Function as an event output pin for reload timer 1. Valid only when output setting is “enabled.” General-purpose input/output ports. Functions as external interrupt input pin. Use the pin by setting as input port. 16 to 19 20 21 22 23 24 25 26 27 28 D F C C B ⎯ ⎯ ⎯ A A Input pin for specifying operation mode. Connect directly to Vss. Input pin for specifying operation mode. Connect directly to Vcc. Input pin for specifying operation mode. Connect directly to Vcc. External reset input pin. Power supply (5 V) input pin. Power supply (0 V) input pin. Capacitor pin for stabilizing power supply. Connect a ceramic capacitor of approximately 0.1 μF. Pin for high-rate oscillation. Pin for high-rate oscillation. General-purpose input/output ports. Functions as trigger input pins of input capture channels 0 to 3. Use the pins by setting as input ports. (Continued) DS07-13731-5E 7 MB90895 Series (Continued) Pin No. Pin name P14 to P17 33 to 36 PPG0 to PPG3 P40 SIN1 P41 38 SCK1 P42 39 SOT1 P43 40 TX P44 RX P30 42 SOT0 P31 43 SCK0 P32 SIN0 P33 X0A* P35* X1A* P36* AVss D D D D D G Circuit type Function General-purpose input/output ports. High-current output ports. Functions as output pin of PPG timers 01 and 23. Valid when output setting is “enabled.” General-purpose input/output port. Serial data input pin for UART1. Use the pin by setting as input port. General-purpose input/output port. Serial clock input/output pin for UART1. Valid only when serial clock input/ output setting on UART1 is “enabled.” General-purpose input/output port. Serial data output pin for UART1. Valid only when serial data output setting on UART1 is “enabled.” General-purpose input/output port. Transmission output pin for CAN. Valid only when output setting is “enabled.” General-purpose input/output port. Receive input pin for CAN. Use the pin by setting as input port. General-purpose input/output port. Serial data output pin for UART0. Valid only when serial data output setting on UART0 is “enabled.” General-purpose input/output port. Serial clock input/output pin for UART0. Valid only when serial clock input/ output setting on UART0 is “enabled.” General-purpose input/output port. Serial data input/output pin for UART0. Use the pin by setting as input port. General-purpose input/output port. Pin for low-rate oscillation. General-purpose input/output port. Pin for low-rate oscillation. General-purpose input/output port. Vss power supply input pin for A/D converter. 37 D 41 D 44 45 46 47 48 H D A A ⎯ * : MB90F897/Y : X1A, X0A MB90F897S/YS : P36, P35 8 DS07-13731-5E MB90895 Series ■ I/O CIRCUIT TYPE Type A X1 X1A X0 X0A Circuit Remarks • High-rate oscillation feedback resistor, approx. 1 MΩ • Low-rate oscillation feedback resistor, approx. 10 MΩ Clock input Standby control signal B Vcc R R • Hysteresis input with pull-up resistor. • Pull-up resistor, approx. 50 kΩ Hysteresis input C R Hysteresis input Hysteresis input D Vcc P-ch Digital output Digital output Hysteresis input • • • • CMOS hysteresis input CMOS level output Standby control provided Automotive input R N-ch Vss Standby control R Automotive input • • • • • CMOS hysteresis input CMOS level output Shared for analog input pin Standby control provided Automotive input E Vcc P-ch Digital output Digital output Hysteresis input R N-ch Vss Standby control R Automotive input Analog input (Continued) DS07-13731-5E 9 MB90895 Series (Continued) Type F R Circuit Remarks • Hysteresis input with pull-down resistor • Pull-down resistor, approx. 50 kΩ • FLASH product is not provided with pull-down resistor. Hysteresis input R Vss G Vcc P-ch High-current output High-current output • CMOS hysteresis input • CMOS level output (high-current output) • Standby control provided • Automotive input R N-ch Vss Hysteresis input Standby control R Automotive input • • • • • CMOS hysteresis input CMOS level output Standby control provided CMOS input Automotive input H Vcc P-ch Digital output Digital output R R Vss Hysteresis input Automotive input R CMOS input Standby control 10 DS07-13731-5E MB90895 Series ■ HANDLING DEVICES • Do Not Exceed Maximum Rating (preventing “latch up”) • Latch-up may occur in a CMOS IC if a voltage higher than VCC or less than VSS is applied to an input or output pin or if a voltage exceeding the rated value is applied between VCC pin and VSS pins. • Latch-up causes drastic increase of power current, which may lead to destruction of elements by heat. Extreme caution must be taken not to exceed maximum rating. • When turning on and off analog power supply, take extra care not to apply an analog power voltages (AVcc and AVR) and analog input voltage that are higher than digital power voltage (Vcc). • Handling Unused Pins • Leaving unused input pins open may cause permanent destruction by malfunction or latch-up. Apply pull-up or pull-down process to the unused pins using resistors of 2 kΩ or higher. Leave unused I/O pins open under output status, or process as input pins if they are under input status. • Using External Clock • When using an external clock, drive only X0 pin and leave X1 pin open. An example of using an external clock is shown below. • Using external clock X0 Open X1 MB90895 series • Notes When Using No Sub Clock on MB90F897/Y • If an oscillator is not connected to X0A and X1A pins, apply pull-down resistor to the X0A pin and leave the X1A pin open. • About Power Supply Pins • If two or more Vcc and Vss exist, the pins that should be at the same potential are connected to each other inside the device. For reducing unwanted emissions and preventing malfunction of strobe signals caused by increase of ground level, however, be sure to connect the Vcc and Vss pins to the power supply and the ground externally. • Pay attention to connect a power supply to Vcc and Vss pins of MB90895 series device in a lowest-possible impedance. • Near pins of MB90895 series device, connecting a bypass capacitor is recommended at 0.1 μF across Vcc and Vss pins. • Crystal Oscillator Circuit • Noises around X0 and X1 pins cause malfunctions on a MB90895 series device. Design a print circuit so that X0 and X1 pins, an crystal oscillator (or a ceramic oscillator), and bypass capacitor to the ground become as close as possible to each other. Furthermore, avoid wires to X0 and X1 pins crossing each other as much as possible. • Print circuit designing that surrounds X0 and X1 pins with grounding wires, which ensures stable operation, is strongly recommended. DS07-13731-5E 11 MB90895 Series • Caution on Operations during PLL Clock Mode • If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. • Sequence of Turning on Power of A/D Converter and Applying Analog Input • Be sure to turn on digital power (Vcc) before applying signals to the A/D converter and applying analog input signals (AN0 to AN7 pins). • Be sure to turn off the power of A/D converter and analog input before turning off the digital power supply. • Be sure not to apply AVR exceeding AVcc when turning on and off. (No problems occur if analog and digital power is turned on and off simultaneously.) • Handling Pins When A/D Converter is Not Used • If the A/D converter is not used, connect the pins under the following conditions: “AVcc=AVR=Vcc,” and “AVss=Vss”. • Note on Turning on Power • For preventing malfunctions on built-in step-down circuit, maintain a minimum of 50 μs of voltage rising time (between 0.2 V and 2.7 V) when turning on the power. • Stabilization of supply voltage • A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply voltage operating range. Therefore, the VCC supply voltage should be stabilized. For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak values) at commercial frequencies (50 / 60Hz) fall below 10% of the standard VCC supply voltage and the coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching. • Support for +125°C / +150°C • Users considering application exceeding TA = +105°C are advised to contact their representatives beforehand for reliability limitations. 12 DS07-13731-5E MB90895 Series ■ BLOCK DIAGRAM X0,X1 RST X0A,X1A Clock control circuit Watch timer Time-base timer CPU F2MC-16LX core 16-bit free-run timer Input capture (4ch) IN0 to IN3 RAM FLASH 16-bit PPG timer (2ch) Internal data bus PPG0 to PPG3 Prescaler SOT1 SCK1 SIN1 CAN RX TX UART1 Prescaler SOT0 SCK0 SIN0 AVcc AVss AN0 to AN7 AVR ADTG DTP/External interrupt INT4 to INT7 UART0 16-bit reload timer (2ch) TIN0,TIN1 TOT0,TOT1 8/10-bit A/D converter (8ch) DS07-13731-5E 13 MB90895 Series ■ MEMORY MAP 1. Memory allocation of MB90895 MB90895 series model outputs 24-bit wide internal address bus and up to 24-bit of external address bus. A maximum of 16 Mbyte memory space of external access memory is accessible. 2. Memory map (with ROM mirroring function enabled) Peripheral RAM area Register 000000H 0000C0H 000100H Address #1 003900H 004000H Extension IO area ROM area (FF bank image) 010000H FE0000H FF0000H FFFFFFH ROM area* ROM area Model MB90V495G MB90F897/S/Y/YS Address #1 001900H 000900H : Internal access memory : Access disallowed * : On MB90F897/S/Y/YS, to read “FE0000H” to “FEFFFFH” is to read out “FF0000H” to “FFFFFFH”. Note : When internal ROM is operating, F2MC-16LX allows viewing ROM data image on FF bank at upper-level of 00 bank. This function is called “mirroring ROM,” which allows effective use of C compiler small model. F2MC-16LX assigns the same low order 16-bit address to FF bank and 00 bank, which allows referencing table in ROM without specifying “far” using pointer. For example, when accessing to “00C000H”, ROM data at “FFC000H” is accessed actually. However, because ROM area of FF bank exceeds 48 Kbytes, viewing all areas is not possible on 00 bank image. Because ROM data of “FF4000H” to “FFFFFFH” is viewed on “004000H” to “00FFFFH” image, store a ROM data table in area “FF4000H” to “FFFFFFH.” 14 DS07-13731-5E MB90895 Series ■ I/O MAP Register Address abbreviation Register Read/ Write (Reserved area) * R/W R/W R/W R/W R/W (Reserved area) * Resource Initial value 000000H 000001H 000002H 000003H 000004H 000005H 000006H to 000010H 000011H 000012H 000013H 000014H 000015H 000016H to 00001AH 00001BH 00001CH to 00001FH 000020H 000021H 000022H 000023H 000024H 000025H 000026H 000027H 000028H 000029H 00002AH 00002BH CDCR1 SMR0 SCR0 SIDR0/ SODR0 SSR0 CDCR0 SES0 SMR1 SCR1 SIDR1/ SODR1 SSR1 Serial mode register 0 Serial control register 0 Serial input data register 0/ Serial output data register 0 Serial status register 0 ADER DDR1 DDR2 DDR3 DDR4 DDR5 PDR1 PDR2 PDR3 PDR4 PDR5 Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 1 Port 2 Port 3 Port 4 Port 5 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Port 1 direction data register Port 2 direction data register Port 3 direction data register Port 4 direction data register Port 5 direction data register R/W R/W R/W R/W R/W Port 1 Port 2 Port 3 Port 4 Port 5 00000000B 00000000B 000X0000B XXX00000B 00000000B (Reserved area) * 8/10-bit A/D converter Analog input permission register R/W 11111111B (Reserved area) * R/W R/W, W R, W R, R/W R/W R/W R/W R/W, W R, W R, R/W (Reserved area) * Communication prescaler control register 1 R/W UART1 0XXX0000B (Continued) UART1 UART0 00000000B 00000100B XXXXXXXXB 00001X00B 0XXX1111B XXXXXXX0B 00000000B 00000100B XXXXXXXXB 00001000B Communication prescaler control register 0 Serial edge selection register 0 Serial mode register 1 Serial control register 1 Serial input data register 1/ Serial output data register 1 Serial status data register 1 DS07-13731-5E 15 MB90895 Series Register Address abbreviation Register Read/ Write (Reserved area) * Resource Initial value 00002CH to 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H 000038H to 00003EH 00003FH 000040H 000041H 000042H 000043H 000044H 000045H 000046H 000047H to 00004FH PPGC2 PPGC3 PPG23 PSCCR PPGC0 PPGC1 PPG01 ENIR EIRR ELVR ADCS ADCR DTP/External interrupt permission register DTP/External interrupt source register Detection level setting register A/D control status register A/D data register R/W R/W R/W R/W R/W R/W, W W, R R 8/10-bit A/D converter DTP/External interrupt 00000000B XXXXXXXXB 00000000B 00000000B 00000000B 00000000B XXXXXXXXB 00101XXXB (Reserved area) * PLL/Subclock control register PPG0 operation mode control register PPG1 operation mode control register PPG0/1 count clock selection register PPG2 operation mode control register PPG3 operation mode control register PPG2/3 count clock selection register R/W, W R/W, W R/W, W R/W 8/16-bit PPG timer 0/1 Clock XXXX0000B 0X000XX1B 0X000001B 000000XXB (Reserved area) * R/W, W R/W, W R/W 8/16-bit PPG timer 2/3 0X000XX1B 0X000001B 000000XXB (Reserved area) * (Continued) 16 DS07-13731-5E MB90895 Series Register Address abbreviation Register Input capture data register 0 Input capture data register 1 Input capture control status register Timer counter data register Timer counter control status register Read/ Write R R R/W R/W R/W (Reserved area) * Resource Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000058H 000059H 00005AH 00005BH 00005CH 00005DH 00005EH to 000065H 000066H 000067H 000068H 000069H 00006AH to 00006EH 00006FH 000070H to 00007FH 000080H 000081H 000082H 000083H 000084H 000085H 000086H IPCP0 IPCP1 ICS01 ICS23 TCDT TCCS 16-bit input/output timer 00000000B 00000000B 00000000B 00000000B 00000000B IPCP2 IPCP3 Input capture data register 2 Input capture data register 3 R 16-bit input/output timer R XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Reserved area) * R/W Timer control status register TMCSR1 R/W R/W R/W (Reserved area) * ROM mirroring function selection module 00000000B XXXX0000B 00000000B XXXX0000B TMCSR0 16-bit reload timer 0 16-bit reload timer 1 ROMM ROM mirroring function selection register W XXXXXXX1B (Reserved area) * BVALR TREQR TCANR TCR Message buffer enabling register Send request register Send cancel register Send completion register R/W R/W (Reserved area) * W (Reserved area) * R/W CAN controller 00000000B (Continued) CAN controller 00000000B CAN controller CAN controller 00000000B 00000000B (Reserved area) * DS07-13731-5E 17 MB90895 Series Register Address abbreviation Register Read/ Write (Reserved area) * R/W (Reserved area) * R/W (Reserved area) * R/W (Reserved area) * Resource Initial value 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH to 00009DH 00009EH 00009FH 0000A0H 0000A1H 0000A2H 0000A3H to 0000A7H 0000A8H 0000A9H 0000AAH 0000ABH to 0000ADH 0000AEH 0000AFH FMCS WDTC TBTC WTC PACSR DIRR LPMCR CKSCR PILR RIER ROVRR Receive overrun register RRTRR Receive RTR register RCR Receive completion register CAN controller CAN controller CAN controller 00000000B 00000000B 00000000B Receive completion interrupt permission register R/W CAN controller 00000000B (Reserved area) * Address matching detection function Delay interrupt generation module Lower power consumption mode Clock I/O Address detection control register Delay interrupt request generation/ release register Lower power consumption mode control register Clock selection register Port input level selection register R/W R/W W,R/W R,R/W R/W 00000000B XXXXXXX0B 00011000B 11111100B 0000000XB (Reserved area) * Watchdog timer control register Time-base timer control register Watch timer control register R,W R/W,W R,R/W (Reserved area) * Flash memory control status register 512K-bit flash memory Watchdog timer Time-base timer Watch timer XXXXX111B 1XX00100B 1X001000B R,W,R/W 000X0000B (Reserved area) * (Continued) 18 DS07-13731-5E MB90895 Series Register Address abbreviation Register Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 Read/ Write Resource Initial value 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H to 0000FFH 001FF0H 001FF1H 001FF2H 001FF3H 001FF4H 001FF5H 003900H 003901H 003902H 003903H 003904H to 003909H ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 R/W Interrupt controller (Reserved area) * Detection address setting register 0 (low-order) PADR0 Detection address setting register 0 (middle-order) Detection address setting register 0 (high-order) Detection address setting register 1 (low-order) PADR1 Detection address setting register 1 (middle-order) Detection address setting register 1 (high-order) TMR0/ TMRLR0 TMR1/ TMRLR1 16-bit timer register 0/16-bit reload register 0 16-bit timer register 1/16-bit reload register 1 R,W R,W 16-bit reload timer 0 16-bit reload timer 1 R/W R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Address matching detection function (Reserved area) * (Continued) DS07-13731-5E 19 MB90895 Series Register Address abbreviation Register FLASH programing control register 0 FLASH programing control register 1 Sector conversion set register Read/ Write R/W R/W R/W Resource Dual operation FLASH Initial value 00000000B 00000000B 00XXXXX0B 00390AH 00390BH 00390CH 00390DH to 00390FH 003910H 003911H 003912H 003913H 003914H 003915H 003916H 003917H 003918H to 00392FH 003930H to 003BFFH 003C00H to 003C0FH 003C10H to 003C13H 003C14H to 003C17H 003C18H to 003C1BH 003C1CH to 003C1FH 003C20H to 003C23H 003C24H to 003C27H 003C28H to 003C2BH FWR0 FWR1 SSR0 (Reserved area) * PRLL0 PRLH0 PRLL1 PRLH1 PRLL2 PRLH2 PRLL3 PRLH3 PPG0 reload register L PPG0 reload register H PPG1 reload register L PPG1 reload register H PPG2 reload register L PPG2 reload register H PPG3 reload register L PPG3 reload register H R/W R/W R/W R/W R/W R/W R/W R/W (Reserved area) * 8/16-bit PPG timer XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Reserved area) * RAM (General-purpose RAM) XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB (Continued) DS07-13731-5E IDR0 ID register 0 R/W IDR1 ID register 1 R/W IDR2 ID register 2 R/W IDR3 ID register 3 R/W CAN controller IDR4 ID register 4 R/W IDR5 ID register 5 R/W IDR6 ID register 6 R/W 20 MB90895 Series Address 003C2CH to 003C2FH 003C30H 003C31H 003C32H 003C33H 003C34H 003C35H 003C36H 003C37H 003C38H 003C39H 003C3AH 003C3BH 003C3CH 003C3DH 003C3EH 003C3FH 003C40H to 003C47H 003C48H to 003C4FH 003C50H to 003C57H 003C58H to 003C5FH 003C60H to 003C67H 003C68H to 003C6FH 003C70H to 003C77H 003C78H to 003C7FH Register abbreviation Register ID register 7 DLC register 0 DLC register 1 DLC register 2 DLC register 3 DLC register 4 DLC register 5 DLC register 6 DLC register 7 Data register 0 Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource Initial value XXXXXXXXB to XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB (Continued) IDR7 DLCR0 DLCR1 DLCR2 DLCR3 DLCR4 DLCR5 DLCR6 DLCR7 DTR0 CAN controller DTR1 Data register 1 R/W DTR2 Data register 2 R/W DTR3 Data register 3 R/W DTR4 Data register 4 R/W DTR5 Data register 5 R/W DTR6 Data register 6 R/W DTR7 Data register 7 R/W DS07-13731-5E 21 MB90895 Series (Continued) Register Address abbreviation Register Read/ Write (Reserved area) * Resource Initial value 003C80H to 003CFFH 003D00H 003D01H 003D02H 003D03H 003D04H 003D05H 003D06H 003D07H 003D08H 003D09H 003D0AH 003D0BH 003D0CH 003D0DH 003D0EH 003D0FH 003D10H 003D11H 003D12H 003D13H 003D14H to 003D17H 003D18H to 003D1BH 003D1CH to 003DFFH 003E00H to 003EFFH 003FF0H to 003FFFH CSR LEIR Control status register Last event display register R/W, R R/W (Reserved area) * CAN controller 0XXXX001B 00XXX000B 000XX000B 00000000B 00000000B 11111111B X1111111B XXXXXXXXB 00000000B RTEC BTR IDER TRTRR RFWTR Send/receive error counter Bit timing register IDE register Send RTR register Remote frame receive wait register Send completion interrupt permission register R R/W R/W (Reserved area) * R/W (Reserved area) * R/W CAN controller CAN controller XXXXXXXXB (Reserved area) * TIER R/W (Reserved area) * AMSR Acceptance mask selection register R/W CAN controller XXXXXXXXB XXXXXXXXB CAN controller 00000000B (Reserved area) * AMR0 Acceptance mask register 0 R/W CAN controller AMR1 Acceptance mask register 1 R/W XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB (Reserved area) * (Reserved area) * (Reserved area) * Initial values : 0 : Initial value of this bit is “0.” 1 : Initial value of this bit is “1.” X : Initial value of this bit is undefined. * : “Reserved area” should not be written anything. Result of reading from “Reserved area” is undefined. 22 DS07-13731-5E MB90895 Series ■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS Interrupt source Reset INT 9 instruction Exceptional treatment CAN controller reception completed (RX) CAN controller transmission completed (TX) / Node status transition (NS) Reserved Reserved CAN wakeup Time-base timer 16-bit reload timer 0 8/10-bit A/D converter 16-bit free-run timer overflow Reserved Reserved PPG timer ch.0, ch.1 underflow Input capture 0-input External interrupt (INT4/INT5) Input capture 1-input PPG timer ch.2, ch.3 underflow External interrupt (INT6/INT7) Watch timer Reserved Input capture 2-input Input capture 3-input Reserved Reserved Reserved Reserved Reserved 16-bit reload timer 1 EI2OS readiness Interrupt vector Number #08 #09 #10 #11 08H 09H 0AH 0BH Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H Interrupt control register ICR ⎯ ⎯ ⎯ Address ⎯ ⎯ ⎯ Priority*3 High ↑ × × × × × × × Δ × Δ Δ Δ × × × Δ Δ Δ × Δ Δ × × × × × × × ICR00 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH ICR09 0000B0H*1 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 0000B1H 0000B2H*1 0000B3H*1 0000B4H*1 0000B5H*1 0000B6H*1 0000B7H*2 0000B8H*1 0000B9H*1 ICR10 ICR11 ICR12 0000BAH*1 0000BBH*1 0000BCH*1 ↓ Low (Continued) DS07-13731-5E 23 MB90895 Series (Continued) Interrupt source UART1 reception completed UART1 transmission completed UART0 reception completed UART0 transmission completed Flash memory Delay interrupt generation module : Available × : Unavailable : Available, El2OS stop function is provided. Δ : Available when a cause of interrupt sharing a same ICR is not used. *1 : • Peripheral functions sharing an ICR register have the same interrupt level. • If peripheral functions share an ICR register, only one function is available when using extended intelligent I/O service. • If peripheral functions share an ICR register, a function using extended intelligent I/O service does not allow interrupt by another function. *2 : Only input capture 1 is ready for EI2OS. Because PPG is not ready for EI2OS, disable PPG interrupt when using EI2OS with Input capture 1. *3 : Priority when two or more interrupts of a same level occur simultaneously. Δ × × Δ EI2OS readiness Interrupt vector Number #37 #38 #39 #40 #41 #42 25H 26H 27H 28H 29H 2AH Address FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt control register ICR ICR13 ICR14 Address 0000BDH*1 0000BEH*1 Priority*3 High ↑ ICR15 0000BFH*1 ↓ Low 24 DS07-13731-5E MB90895 Series ■ FLASH MEMORY CONFIGURATION • Sector configuration of 512 Kbit flash memory Flash memory SA0 (4 Kbytes) FF0FFF H FF1000H 70FFFH 71000H CPU address FF0000H Writer address* 70000H FF1FFF H FF2000H 71FFFH 72000H SA2 (4 Kbytes) FF2FFF H FF3000H 72FFFH 73000H SA3 (4 Kbytes) FF3FFF H FF4000H 73FFFH 74000H SA4 (16 Kbytes) FF7FFF H FF8000H 77FFFH 78000H SA5 (16 Kbytes) FFBFFF H FFC000 H 7BFFF H 7C000H FFCFFF H FFD000 H 7CFFF H 7D000H SA7 (4 Kbytes) FFDFFF H FFE000H 7DFFF H 7E000H SA8 (4 Kbytes) FFEFFF H FFF000H 7EFFF H 7F000H SA9 (4 Kbytes) FFFFFF H 7FFFFH * : “Writer address” is an address equivalent to CPU address, which is used when data is written on flash memory, using parallel writer. When writing/ deleting data with general-purpose writer, the writer address is used for writing and deleting. DS07-13731-5E Upper Bank SA6 (4 Kbytes) Lower Bank SA1 (4 Kbytes) 25 MB90895 Series ■ ELECTRIC CHARACTERISTICS 1. Absolute Maximum Rating Parameter Symbol VCC Power supply voltage* Input voltage*1 Output voltage*1 Maximum clamp current Total maximum clamp current “L” level maximum output current “L” level average output current “L” level maximum total output current “L” level average total output current “H” level maximum output current “H” level average output current “H” level maximum total output current “H” level average total output current Power consumption 1 Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 − 2.0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ −40 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 + 2.0 20 15 40 4 30 125 160 40 40 −15 −40 −4 −30 −125 −160 −40 −40 297 +105 +125 +150 +150 Unit V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mW °C °C °C °C Remarks AVCC AVR VI VO ICLAMP Σ| ICLAMP | IOL1 IOL2 IOLAV1 IOLAV2 ΣIOL1 ΣIOL2 ΣIOLAV1 ΣIOLAV2 IOH1 IOH2 IOHAV1 IOHAV2 ΣIOH1 ΣIOH2 ΣIOHAV1 ΣIOHAV2 PD VCC = AVCC*2 AVCC ≥ AVR*2 *3 *3 *7 *7 Normal output*4 High-current output*4 Normal output*5 High-current output*5 Normal output High-current output Normal output*6 High-current output*6 Normal output*4 High-current output*4 Normal output*5 High-current output*5 Normal output High-current output Normal output*6 High-current output*6 Other than MB90F897Y/YS *8 Other than MB90F897Y/YS *8, *9 MB90F897Y/YS Operating temperature TA −40 −40 Storage temperature Tstg −55 *1: The parameter is based on VSS = AVSS = 0.0 V. *2 : AVcc and AVR should not exceed Vcc. (Continued) 26 DS07-13731-5E MB90895 Series (Continued) *3 : VI and VO should not exceed Vcc + 0.3 V. However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *4 : A peak value of an applicable one pin is specified as a maximum output current. *5 : An average current value of an applicable one pin within 100 ms is specified as an average output current. (Average value is found by multiplying operating current by operating rate.) *6 : An average current value of all pins within 100 ms is specified as an average total output current. (Average value is found by multiplying operating current by operating rate.) *7 : • Applicable to pins: P10 to P17, P20 to P27, P30 to P33, P35, P36, P37, P40 to P44, P50 to P57 Note: P35 and P36 are MB90F897S/YS only. • Use within recommended operating conditions. • Use at DC voltage (current) . • The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. • Care must be taken not to leave the +B input pin open. • Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. • Sample recommended circuits: • Input/Output Equivalent circuits Protective diode VCC Limiting resistance +B input (0 V to 16 V) P-ch N-ch R *8 : Users considering application exceeding TA = +105°C are advised to contact their FUJITSU MICROELECTRONICS representatives beforehand for reliability limitations. *9 : Use the PB circuit board which has 4 or more layers. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. DS07-13731-5E 27 MB90895 Series 2. Recommended Operating Conditions (VSS = AVSS = 0.0 V) Parameter Symbol Value Min 3.5 Power supply voltage VCC 3.0 4.0 Smoothing capacitor CS 0.1 −40 Operating temperature TA −40 −40 Typ 5.0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Max 5.5 5.5 5.5 1.0 +105 +125 +150 Unit V V V μF Remarks Under normal operation Retain status of stop operation Accuracy guarantee voltage of A/D converter *1 *2 Other than MB90F897Y/YS *2, *3 MB90F897Y/YS °C Other than MB90F897Y/YS °C °C *1 : Use a ceramic capacitor, or a capacitor of similar frequency characteristics. On the Vcc pin, use a bypass capacitor that has a larger capacity than that of Cs. Refer to the following figure for connection of smoothing capacitor Cs. *2: Users considering application exceeding TA = +105°C are advised to contact their FUJITSU MICROELECTRONICS representatives beforehand for reliability limitations. *3 : Use the PB circuit board which has 4 or more layers. • C pin connection diagram C CS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. 28 DS07-13731-5E MB90895 Series 3. DC Characteristics • MB90F897/S (Models that support + 125 °C) Parame- Sym ter bol Pin name (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +125 °C) Value Remarks Conditions Unit Min Typ Max — 0.8 VCC — VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 0.2 VCC V When selected CMOS hysteresis When selected Automotive When selected CMOS When selected CMOS hysteresis When selected Automotive When selected CMOS CMOS VIHS hysteresis input pin “H” level input voltage VIHA VIHC Automotive input pin CMOS input pin (P32, P40) — — — — 0.8 VCC 0.7 VCC VCC − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VCC – 0.5 VCC – 0.5 — — — — — — V V V V VIHM MD input pin CMOS VILS hysteresis input pin “L” level input voltage VILA VILC Automotive input pin CMOS input pin (P32, P40) — — — — — — — — — — 0.5 VCC 0.3 VCC VSS + 0.3 — — 0.4 0.4 +5 V V V V V V V μA VILM MD input pin “H” level output voltage “L” level output voltage Input leak current VOH1 Pins other than VCC = 4.5 V, P14 to P17 IOH = −4.0 mA VCC = 4.5 V, IOH = −14.0 mA VOH2 P14 to P17 VOL1 Pins other than VCC = 4.5 V, P14 to P17 IOL = 4.0 mA VCC = 4.5 V, IOL = 20.0 mA VCC = 5.5 V, VSS < VI < VCC VCC = 5.0 V, Internally operating at 16 MHz, normal operation. VOL2 P14 to P17 IIL All input pins –5 — — 25 30 mA Power supply current* ICC VCC VCC = 5.0 V, Internally operating at 16 MHz, writing on flash memory. VCC = 5.0 V, Internally operating at 16 MHz, deleting on flash memory. — 45 50 mA MB90F897/S — 45 50 mA MB90F897/S * : Test conditions of power supply current are based on a device using external clock. (Continued) DS07-13731-5E 29 MB90895 Series (Continued) Parameter Symbol ICCS Pin name (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +125 °C) Value Conditions Unit Remarks Min Typ Max VCC = 5.0 V, Internally operating at 16 MHz, sleeping. VCC = 5.0 V, Internally operating at 2 MHz, transition from main clock mode, in time-base timer mode. VCC = 5.0 V, Internally operating at 16 MHz, transition from PLL clock mode, in time-base timer mode. VCC ICCL VCC = 5.0 V, Internally operating at 8 kHz, subclock operation, TA = + 25°C VCC = 5.0 V, Internally operating at 8 kHz, subclock, sleep mode, TA = + 25°C VCC = 5.0 V, Internally operating at 8 kHz, watch mode, TA = + 25°C Stopping, TA = + 25°C Other than AVCC, AVSS, AVR, C, VCC, VSS RST ⎯ — 8 12 mA ICTS — 0.2 0.35 mA ICTSPII — 3 5 mA Power supply current* — 40 100 μA ICCLS — 10 50 μA ICCT — 8 30 μA ICCH — 5 25 μA Input capacity Pull-up resistor Pull-down resistor CIN — 5 15 pF RUP ⎯ ⎯ 25 50 100 kΩ kΩ FLASH product is not provided with pull-down resistor. RDOWN MD2 25 50 100 * : Test conditions of power supply current are based on a device using external clock. 30 DS07-13731-5E MB90895 Series • • MB90F897Y/YS (Models that support + 150 °C) (Under development) (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +150 °C) Value Sym Remarks Parameter Pin name Conditions Unit bol Min Typ Max CMOS VIHS hysteresis input pin “H” level input voltage VIHA VIHC Automotive input pin CMOS input pin (P32, P40) — — — — — — — — 0.8 VCC 0.8 VCC 0.7 VCC VCC − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VCC – 0.5 VCC – 0.5 — — –5 — — — — — — — — — — — — — VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 0.2 VCC 0.5 VCC 0.3 VCC VSS + 0.3 — — 0.4 0.4 +5 V V V V V V V V V V V V μA When selected CMOS hysteresis When selected Automotive When selected CMOS When selected CMOS hysteresis When selected Automotive When selected CMOS VIHM MD input pin CMOS VILS hysteresis input pin “L” level input voltage VILA VILC Automotive input pin CMOS input pin (P32, P40) VILM MD input pin “H” level output voltage “L” level output voltage Input leak current VOH1 Pins other than VCC = 4.5 V, P14 to P17 IOH = −3.0 mA VCC = 4.5 V, IOH = −12.0 mA VOH2 P14 to P17 VOL1 Pins other than VCC = 4.5 V, P14 to P17 IOL = 3.0 mA VCC = 4.5 V, IOL = 16 mA VCC = 5.5 V, VSS < VI < VCC VCC = 5.0 V, Internally operating at 16 MHz, normal operation. VOL2 P14 to P17 IIL All input pins — 25 32 mA Power supply current* ICC VCC VCC = 5.0 V, Internally operating at 16 MHz, writing on flash memory. TA = −40 °C to +125 °C VCC = 5.0 V, Internally operating at 16 MHz, deleting on flash memory. TA = −40 °C to +125 °C — 45 50 mA Up to + 125 °C — 45 50 mA Up to + 125 °C * : Test conditions of power supply current are based on a device using external clock. (Continued) DS07-13731-5E 31 MB90895 Series (Continued) Parameter Symbol ICCS Pin name (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +150 °C) Value Conditions Unit Remarks Min Typ Max VCC = 5.0 V, Internally operating at — 8 14 mA 16 MHz, sleeping. VCC = 5.0 V, Internally operating at 2 MHz, transition from — 0.2 0.35 mA Up to + 125 °C main clock mode, in time-base timer mode. TA = −40 °C to +125 °C VCC = 5.0 V, Internally operating at 2 MHz, transition from main clock mode, in — 0.2 T.B.D mA time-base timer mode. TA = +125 °C to +150 °C VCC = 5.0 V, Internally operating at 16 MHz, transition — 3 7 mA from PLL clock mode, in time-base timer mode. VCC = 5.0 V, Internally operating at — 40 100 μA 8 kHz, subclock operation, TA = + 25°C VCC = 5.0 V, Internally operating at 8 kHz, subclock, — 10 50 μA sleep mode, TA = + 25°C VCC = 5.0 V, Internally operating at — 8 30 μA 8 kHz, watch mode, TA = + 25°C Stopping, — 5 25 μA TA = + 25°C ⎯ ⎯ ⎯ — 5 15 pF ICTS Power supply current* ICTSPII VCC ICCL ICCLS ICCT ICCH Input capacity Pull-up resistor Pull-down resistor Other than AVCC, AVSS, AVR, C, VCC, VSS RST CIN RUP 25 25 50 50 100 100 kΩ kΩ FLASH product is not provided with pull-down resistor. RDOWN MD2 * : Test conditions of power supply current are based on a device using external clock. 32 DS07-13731-5E MB90895 Series 4. AC Characteristics (1) Clock timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +125 °C/+150 °C (only MB90F897Y/YS)) Value Parameter Symbol Pin name Unit Remarks Min Typ Max 3 3 Clock frequency fC X0, X1 4 4 4 4 fCL Clock cycle time tHCYL tLCYL PWH, PWL PWLH,PWLL Input clock rise time and fall time Internal operation clock frequency Internal operation clock cycle time tCR, tCF fCP fLCP tCP tLCP X0A, X1A X0, X1 X0A, X1A X0 X0A X0 — — — — — 125 — 10 — — 1.5 — 62.5 — — — — — — — 32.768 — 30.5 — 15.2 — — 8.192 — 122.1 8 16 16 8 5.33 4 — 333 — — — 5 16 — 666 — MHz When crystal or ceramic resonator is used MHz External clock MHz PLL multiplied by 1 MHz PLL multiplied by 2 MHz PLL multiplied by 3 MHz PLL multiplied by 4 kHz ns μs ns μs ns MB90F897/Y only Set duty factor at 30% to 70% as a guideline. MB90F897/Y only When external clock is used MB90F897/Y only Input clock pulse width MHz When main clock is used kHz ns μs When sub clock is used, MB90F897/Y only When main clock is used When sub clock is used, MB90F897/Y only • Clock timing tHCYL X0 PWH tCF tLCYL X0A PWLH tCF PWLL tCR 0.8 VCC 0.2 VCC PWL tCR 0.8 VCC 0.2 VCC DS07-13731-5E 33 MB90895 Series • PLL operation guarantee range Relation between internal operation clock frequency and power supply voltage Operation guarantee range of MB90F897/S/Y/YS 5.5 Power voltage VCC (V) 4.0 3.5 3.0 A/D converter accuracy guarantee range PLL operation guarantee range 1.5 34 8 12 16 Internal clock fCP (MHz) Relation among external clock frequency and internal clock frequency 4x 16 3x 2x 1x Internal clock fCP (MHz) 12 9 8 4 1.5 3 4 8 16 1/2 x (no multiplication) External clock fC (MHz)* * : fc is 8 MHz at maximum when crystal or ceramic resonator circuit is used. 34 DS07-13731-5E MB90895 Series Rating values of alternating current is defined by the measurement reference voltage values shown below: • Input signal waveform • Output signal waveform Hysteresis input pin VIH VIL Output pin 2.4 V 0.8 V (2) Reset input timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +125 °C/+150 °C (only MB90F897Y/YS)) Value Pin CondiParameter Symbol Unit Remarks name tions Min Max 16 tCP*3 Reset input time tRSTL RST ⎯ Oscillation time of oscillator*1 + 100 μs + 16 tCP*3 100 ⎯ ⎯ ⎯ ns ⎯ μs Normal operation In sub clock*2, sub sleep*2, watch*2 and stop mode In timebase timer *1 : Oscillation time of oscillator is time that the amplitude reached the 90%. In the crystal oscillator, the oscillation time is between several ms to tens of ms. In ceramic oscillator, the oscillation time is between hundreds of μs to several ms. In the external clock, the oscillation time is 0 ms. *2 : Except for MB90F897S/YS. *3 : Refer to “(1) Clock timing” ratings for tCP (internal operation clock cycle time). • In sub clock, sub sleep, watch and stop mode tRSTL RST 0.2 VCC 0.2 VCC 90% of amplitude X0 Internal operation clock Oscillation time of oscillator Internal reset 100 s + 16 tCP Wait time for stabilizing oscillation Execute instruction DS07-13731-5E 35 MB90895 Series (3) Power-on reset (VSS = AVSS = 0.0 V, TA = −40 °C to +125 °C/+150 °C (only MB90F897Y/YS)) Value Symbol Pin name Conditions Unit Remarks Min Max tR tOFF VCC VCC ⎯ 0.05 1 30 ⎯ ms ms Repeated operation Parameter Power supply rise time Power supply shutdown time tR VCC 2.7 V 0.2 V 0.2 V tOFF 0.2 V Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power supply voltages during operation, raise the power smoothly by suppressing variation of voltages as shown below. When raising the power, do not use PLL clock. However, if voltage drop is 1V/s or less, use of PLL clock is allowed during operation. VCC 3.0 V VSS Limiting the slope of rising within 50 mV/ms is recommended. RAM data hold period 36 DS07-13731-5E MB90895 Series (4) UART0/UART1 timing (VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +125 °C/+150 °C (only MB90F897Y/YS)) Value Parameter Symbol Pin name Conditions Unit Remarks Min Max Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ →valid SIN hold time tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX SCK0/SCK1 SCK0/SCK1, SOT0/SOT1 Internal shift clock SCK0/SCK1, mode output pin is : SIN0/SIN1 CL = 80 pF+1TTL SCK0/SCK1, SIN0/SIN1 SCK0/SCK1 SCK0/SCK1 SCK0/SCK1, External shift clock SOT0/SOT1 mode output pin is : SCK0/SCK1, CL = 80 pF+1TTL SIN0/SIN1 SCK0/SCK1, SIN0/SIN1 8 tCP * −80 100 60 4 tCP * 4 tCP * ⎯ 60 60 ⎯ +80 ⎯ ⎯ ⎯ ⎯ 150 ⎯ ⎯ ns ns ns ns ns ns ns ns ns * : Refer to "(1) Clock timing" ratings for tCP (internal operation clock cycle time). Notes: • AC rating in CLK synchronous mode. • CL is a load capacitance value on pins for testing. DS07-13731-5E 37 MB90895 Series • Internal shift clock mode SCK 0.8 V tSLOV 2.4 V tSCYC 2.4 V 0.8 V SOT 0.8 V tIVSH VIH tSHIX VIH VIL SIN VIL • External shift clock mode tSLSH VIH VIL tSLOV 2.4 V VIL tSHSL VIH SCK SOT 0.8 V tIVSH VIH tSHIX VIH VIL SIN VIL 38 DS07-13731-5E MB90895 Series (5) Timer input timing (VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +125 °C/+150 °C (only MB90F897Y/YS)) Value Parameter Symbol Pin name Conditions Unit Remarks Min Max Input pulse width tTIWH tTIWL TIN0, TIN1 IN0 to IN3 ⎯ 4 tCP * ⎯ ns * : Refer to "(1) Clock timing" ratings for tCP (internal operation clock cycle time). • Timer input timing TIN0, TIN1, IN0 to IN3 VIH VIH VIL tTIWH tTIWL VIL (6) Trigger input timing (VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +125 °C/+150 °C (only MB90F897Y/YS)) Value Parameter Symbol Pin name Conditions Unit Remarks Min Max Input pulse width tTRGH tTRGL INT4 to INT7, ADTG ⎯ 3 tCP * ⎯ ns * : Refer to "(1) Clock timing" ratings for tCP (internal operation clock cycle time). • Trigger input timing INT4 to INT7, ADTG VIH VIH VIL tTRGH tTRGL VIL DS07-13731-5E 39 MB90895 Series 5. A/D converter (VCC = AVCC = 5.0 V ± 10 %, 3.0 V ≤ AVR − AVSS, VSS = AVSS = 0.0 V, TA = −40 °C to +125 °C/+150 °C (only MB90F897Y/YS)) Value Unit Remarks Min Typ Max ⎯ ⎯ ⎯ ⎯ AVSS − 1.5 LSB AVR − 3.5 LSB 66 tCP *1 Compare time ⎯ ⎯ 88 tCP *1 ⎯ ⎯ ns ⎯ ⎯ ⎯ ⎯ AVSS + 0.5 LSB AVR − 1.5 LSB ⎯ 10 ± 3.0 ± 2.5 ± 1.9 AVSS + 2.5 LSB AVR + 0.5 LSB ⎯ bit LSB LSB LSB V V 1 LSB = (AVR − AVSS) /1024 With 16 MHz machine clock 5.5 V ≥ AVCC ≥ 4.5 V With 16 MHz machine clock 4.5 V > AVCC ≥ 4.0 V With 16 MHz machine clock 5.5 V ≥ AVCC ≥ 4.5 V With 16 MHz machine clock 4.5 V > AVCC ≥ 4.0 V Parameter Resolution Total error Nonlinear error Differential linear error Zero transition voltage Full-scale transition voltage Symbol ⎯ ⎯ ⎯ ⎯ VOT VFST Pin name ⎯ ⎯ ⎯ ⎯ AN0 to AN7 AN0 to AN7 ns 32 tCP *1 Sampling time ⎯ ⎯ 128 tCP *1 Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supplying current Variation among channels AN0 to AN7 AN0 to AN7 AVR AVCC AVCC AVR AVR AN0 to AN7 ⎯ AVSS AVSS + 2.7 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ns ⎯ ⎯ ⎯ ⎯ 3.5 ⎯ 165 ⎯ ⎯ ⎯ 10 AVR AVCC 7.5 5 250 5 4 ns μA V V mA μA μA μA LSB IAIN VAIN ⎯ IA IAH IR IRH ⎯ *2 *2 *1 : Refer to "(1) Clock timing" ratings for tCP (internal operation clock cycle time). *2 : If A/D converter is not operating, a current when CPU is stopped is applicable (Vcc=AVcc=AVR=5.0 V). 40 DS07-13731-5E MB90895 Series 6. Definition of A/D Converter Terms Resolution Linear error : Analog variation that is recognized by an A/D converter. : Deviation between a line across zero-transition line (“00 0000 0000” ←→“00 0000 0001”) and full-scale transition line (“11 1111 1110” ←→ “11 1111 1111”) and actual conversion characteristics. : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. : Difference between an actual value and an ideal value. A total error includes zero transition error, full-scale transition error, and linear error. Total error 3FFH 3FEH 3FDH Differential linear error Total error Actual conversion characteristics 1.5 LSB Digital output {1 LSB × (N − 1) + 0.5 LSB} 004H 003H 002H 001H 0.5 LSB AVss VNT (Actually-measured value) Actual conversion characteristics Ideal characteristics Analog input AVR Total error of digital output “N” = VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB AVR − AVSS 1024 [LSB] 1 LSB = (Ideal value) [V] VOT (Ideal value) = AVSS + 0.5 LSB [V] VFST (Ideal value) = AVR − 1.5 LSB [V] VNT : A voltage at which digital output transits from (N-1) to N. (Continued) DS07-13731-5E 41 MB90895 Series (Continued) Linear error 3FFH 3FEH 3FDH Actual conversion characteristics {1 LSB × (N − 1) + VOT } N+1 Differential linear error Ideal characteristics Actual conversion characteristics Digital output Digital output VFST (actual measurement value) VNT (actual measurement value) Actual conversion characteristics N 004H 003H 002H N−1 V (N + 1) T (actual measurement value) VNT (actual measurement value) Ideal characteristics 001H VOT (actual measurement value) AVss AVR N−2 Actual conversion characteristics AVR AVss Analog input VNT − {1 LSB × (N − 1) + VOT} 1 LSB V (N + 1) T − VNT 1 LSB VFST − VOT 1022 −1LSB [LSB] Analog input Linear error of digital output N = Differential linear error of digital output N = 1 LSB = [LSB] [V] VOT : Voltage at which digital output transits from “000H” to “001H.” VFST : Voltage at which digital output transits from “3FEH” to “3FFH.” 42 DS07-13731-5E MB90895 Series 7. Notes on A/D Converter Section • A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. Analog input circuit model R Analog input Comparator C During sampling : ON MB90F897/S MB90F897Y/YS 4.5 V ≤ AVCC ≤ 5.5 V 4.0 V ≤ AVCC < 4.5 V R 2.4 kΩ (Max) 16.4 kΩ (Max) C 36.4 pF (Max) 36.4 pF (Max) Note : The values are reference values. (Continued) DS07-13731-5E 43 MB90895 Series (Continued) • To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. (At 4.5 V ≤ AVCC ≤ 5.5 V) [External impedance = 0 kΩ to 100 kΩ] [External impedance = 0 kΩ to 20 kΩ] → External impedance [kΩ] 0 → External impedance [kΩ] 100 90 80 70 60 50 40 30 20 10 0 5 10 15 20 MB90F897/S/ MB90F897Y/YS 20 18 16 14 12 10 8 6 4 2 0 MB90F897/S/ MB90F897Y/YS 25 30 35 0 1 2 3 4 5 6 7 8 → Minimum sampling time [μs] (At 4.0 V ≤ AVCC < 4.5 V) [External impedance = 0 kΩ to 100 kΩ] → Minimum sampling time [μs] [External impedance = 0 kΩ to 20 kΩ] 100 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 MB90F897/S/ MB90F897Y/YS 20 18 16 14 12 10 8 6 4 2 0 → External impedance [kΩ] → External impedance [kΩ] MB90F897/S/ MB90F897Y/YS 25 30 35 0 1 2 3 4 5 6 7 8 → Minimum sampling time [μs] → Minimum sampling time [μs] The relationship between the external impedance and minimum sampling time • If the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin. • As ⏐AVR − AVss⏐ become smaller, values of relative errors grow larger. 44 DS07-13731-5E MB90895 Series 8. Flash Memory Program/Erase Characteristics*1 Parameter Sector erase time (4 KB sector) Sector erase time (16 KB sector) Chip erase time Word (16 bit width) programming time Program/Erase cycle Flash Data Retention Time ⎯ Average TA = + 85 °C TA = + 25 °C, VCC = 5.0 V Conditions Value Min ⎯ ⎯ ⎯ ⎯ 10,000 20 Typ 0.2 0.5 2.6 16 ⎯ ⎯ Max 0.5 7.5 ⎯ 3,600 ⎯ ⎯ Unit s s s μs cycle Years *2 Remarks Excludes 00H programming prior to erasure Excludes 00H programming prior to erasure Excludes 00H programming prior to erasure Except for the over head time of the system *1 : For MB90F897Y/YS, it is prohibited to write or erase data in the range of TA = + 125 °C to + 150 °C. *2 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 85 °C) . DS07-13731-5E 45 MB90895 Series ■ EXAMPLE CHARACTERISTICS • MB90F897 ICC − VCC TA = +25 °C, In external clock operation f = Internal operating frequency 30 25 20 f = 16 MHz ICC (mA) 15 10 5 0 2.5 f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz 3.5 4.5 VCC (V) 5.5 6.5 ICCS − VCC TA = +25 °C, In external clock operation f = Internal operating frequency 10 8 f = 16 MHz ICCS (mA) 6 f = 10 MHz 4 2 0 2.5 f = 8 MHz f = 4 MHz f = 2 MHz 3.5 4.5 VCC (V) 5.5 6.5 ICCL − VCC TA = +25 °C, In external clock operation f = Internal operating frequency 350 300 250 ICCL (µA) 200 150 100 50 0 f = 8 kHz 3 4 5 VCC (V) 6 7 (Continued) 46 DS07-13731-5E MB90895 Series ICCLS − VCC TA = +25 °C, In external clock operation f = Internal operating frequency 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICCLS (µA) f = 8 kHz 3 4 5 VCC (V) 6 7 ICCT − VCC TA = +25 °C, In external clock operation f = Internal operating frequency 10 9 8 7 ICCT (µA) 6 5 4 3 2 1 0 f = 8 kHz 3 4 5 VCC (V) 6 7 ICCH − VCC 30 25 Stopping, TA = +25 °C ICCH (µA) 20 15 10 5 0 2 3 4 VCC (V) 5 6 7 (Continued) DS07-13731-5E 47 MB90895 Series (Continued) (VCC - VOH) − IOH 1000 900 800 TA = +25 °C, VCC = 4.5 V VCC - VOH (mV) 700 600 500 400 300 200 100 0 0 1 2 3 4 5 IOH (mA) 6 7 8 9 10 VOL − IOL 1000 900 800 700 VOL (mV) 600 500 400 300 200 100 0 0 2 4 IOL (mA) 6 TA = +25 °C, VCC = 4.5 V 8 10 “H” level input voltage/ “L” level input voltage VIN − VCC TA = +25 °C 5 4 VIH VIN (V) 3 VIL 2 1 0 2.5 3 3.5 4 4.5 VCC (V) 5 5.5 6 48 DS07-13731-5E MB90895 Series ■ ORDERING INFORMATION Part number MB90F897PMT MB90F897SPMT MB90F897YPMT MB90F897YSPMT Package 48-pin plastic LQFP (FPT-48P-M26) Remarks DS07-13731-5E 49 MB90895 Series ■ PACKAGE DIMENTION 48-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.50 mm 7 × 7 mm Gullwing Plastic mold 1.70 mm MAX 0.17 g P-LFQFP48-7×7-0.50 (FPT-48P-M26) Code (Reference) 48-pin plastic LQFP (FPT-48P-M26) Note 1) * : These dimensions include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 9.00±0.20(.354±.008)SQ * 7.00 –0.10 .276 –.004 SQ 36 25 +0.40 +.016 0.145±0.055 (.006±.002) 37 24 0.08(.003) INDEX Details of "A" part 1.50 –0.10 .059 –.004 +0.20 +.008 (Mounting height) 48 13 "A" 0˚~8˚ LEAD No. 0.50(.020) 1 12 0.10±0.10 (.004±.004) (Stand off) 0.20±0.05 (.008±.002) 0.08(.003) M 0.25(.010) 0.60±0.15 (.024±.006) ©20033 FUJITFUJITSU MICROELECTRONICS LIMITED F48040S-c-2-3 C 200-2008 SU LIMITED F48040S-c-2-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ 50 DS07-13731-5E MB90895 Series ■ MAIN CHANGES IN THIS EDITION Page ⎯ 1 8 11 12 ■ BLOCK DIAGRAM 13 ■ FEATURES ■ PIN DESCRIPTION ■ HANDLING DEVICES Section ⎯ Change Results Added the following part numbers under development. MB90F897Y, MB90F897YS Added as follows. • Models that support + 150 °C (MB90F897Y/YS) Corrected the function of pin SCK0 on pin number 43. UART1 → UART0 Corrected the description for “• Handling Unused Pins”. unused input pins → unused I/O pins “• Support for + 125 °C” → “• Support for + 125 °C / + 150 °C” Corrected the arrow for “pin X0 and X1” in the clock control circuit. “input → ”→ “input/output←→” Corrected the arrow for “pin TIN0 and pin TIN1” in 16-bit reload timer (2ch). “output →” →“ input←” ■ INTERRUPT SOURCES, INTERRUPT Corrected footnotes in the address column for ICR05 and VECTORS, AND INTERRUPT CONTROL ICR07 of the interrupt control register. REGISTERS 0000B5H*2 → 0000B5H*1 10000B7H*1 → 0000B7H*2 Corrected the description for footnote *2. 16-bit reload timer → Input capture 1 ■ PERIPHERAL RESOURCES Deleted the section Refer to the hardware manual, for details of peripheral resources. Changed the item name from “PERIPHERAL RESOURCES” to “FLASH MEMORY CONFIGURATION”. Item: Added the rating value for MB90F897Y/YS to the operating temperature. Min: − 40 °C, Max: + 150 °C Added footnote*9. 2. Recommended Operating Conditions 28 Item: Added the rating value for MB90F897Y/YS to the operating temperature. Min: − 40 °C,Max: + 150 °C Added footnote *3. 31, 32 3. DC Characteristics 4. AC Characteristics 33 to 40 5. A/D converter ■ ORDERING INFORMATION Added DC characteristics for “MB90F897Y/YS”. Changed the condition description in the upper right of the table. TA = − 40 °C to +125 °C → TA = − 40 °C to +125 °C/ + 150 °C (Only MB90F897Y/YS) Added the following part numbers. MB90F897YPMT, MB90F897YSPMT 23 24 ⎯ 25 26 27 ■ FLASH MEMORY CONFIGURATION ■ ELECTRIC CHARACTERISTICS 1. Absolute Maximum Rating 49 The vertical lines marked in the left side of the page show the changes. DS07-13731-5E 51 MB90895 Series FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. 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Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department