MB90F927

FUJITSU SEMICONDUCTOR DATA SHEET DS07-13745-1E 16-bit Microcontroller CMOS F2MC-16LX MB90925 Series MB90F927/F927S/V925-101/V925-102 ■ DESCRIPTION MB90925 series is a 16-bit general-purpose high-capacity microcontroller designed for vehicle meter control applications etc. The instruction set retains the same AT architecture as F2MC-8L and F2MC-16L series, with further refinements including high-level language instructions, expanded addressing mode, enhanced signed multiplication and division computation and bit processing. In addition, a 32-bit accumulator is built in to enable long word processing. Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller. ■ FEATURES • Clock Built-in PLL clock frequency multiplication circuit. Selection of machine clocks (PLL clocks) is allowed among frequency division by 2 on oscillation clock and multiplication of 1 to 4 times of oscillation clock(for 4 MHz oscillation clock, 4 MHz to 16 MHz). Operation by sub clock(up to 50 kHz : 100 kHz oscillation clock divided by 2). (Continued) Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development. Copyright©2007 FUJITSU LIMITED All rights reserved MB90925 Series • 16-bit input capture (4 channels) Detects rising, falling, or both edges. 16-bit capture register × 4 Pin input edge detection latches the 16-bit free-run timer counter value, and generates an interrupt request. • 16-bit reload timer (2 channels) 16-bit reload timer operation (select toggle output or one-shot output) Event count function selection provided • Real Time watch timer (main clock) Operates directly from oscillator clock. Interrupt can be generated by second/minute/hour/date counter overflow. • 16-bit PPG (3 channels) Output pins (3 channels) , external trigger input pin (1 channel) Output clock frequencies : fCP, fCP/22, fCP/24, fCP/26 • Delay interrupt Generates interrupt for task switching. Interrupts to CPU can be generated/deleted by software setting. • External interrupts (8 channels) 8-channel independent operation Interrupt source setting available : “L” to “H” edge/ “H” to “L” edge/ “L” level/ “H” level. • A/D converter 10-bit or 8-bit resolution × 8 channels (input multiplexed) Conversion time : 2.6µs (at fCP = 16 MHz) External trigger startup available (P50/INT0/ADTG) Internal timer startup available (16-bit reload timer 1) • UART(LIN/SCI) (2 channels) Equipped with full duplex double buffer Clock-asynchronous or clock-synchronous serial transfer is available • SIO (1 channel) Clock synchronized data transmission. LSB-first or MSB-first data transfer selection is available. • CAN interface Conforms to CAN specifications version 2.0 Part A and B. Automatic resend in case of error. Automatic transfer in response to remote frame. 16 prioritized message buffers for data and ID Multiple message support Receiving filter has flexible configuration : Full bit compare/full bit mask/two partial bit masks Supports up to 1 Mbps CAN WAKEUP function (connects RX internally to INT0) • LCD controller/driver (32 segment x 4 common) Segment driver and command driver with direct LCD panel (display) drive capability • Low voltage/Program looping detect reset Automatic reset when low voltage is detected Program looping detection function (Continued) 2 MB90925 Series (Continued) • Stepping motor controller (4 channels) High current output for each channel × 4 Synchronized 8/10-bit PWM for each channel × 2 • Sound generator 8-bit PWM signal mixed with tone frequency from 8-bit reload counter. PWM frequencies : 62.5 kHz, 31.2 kHz, 15.6 kHz, 7.8 kHz (at fCP = 16 MHz) Tone frequencies : 1/2 PWM frequency, divided by (reload frequency +1) • Input/output ports General-purpose input/output port (CMOS output) - 70 ports (dual clock system) - 72 ports (single clock system) • Input level select function for port Automotive/CMOS-Schmitt (initial level is Automotive in single chip mode) • Flash memory security function Protect the content of Flash memory (Flash memory product only) 3 MB90925 Series ■ PRODUCT LINEUP Part number MB90F927 MB90F927S MB90V925-101 MB90V925-102 Parameter Type CPU System clock Sub clock pin (X0A, X1A) ROM RAM I/O port SIO LCD segment UART CAN interface 16-bit input capture 16-bit reload timer 16-bit free-run timer Real time watch timer 16-bit PPG External interrupt 8/10-bit A/D converter LVD/CPU loop reset Stepping motor controller Sound generator Flash memory security Operation voltage Packages Yes 3.7 V to 5.5 V QFP-100, LQFP-100 Yes 4 channels 1 channel No 4.5 V to 5.5 V PGA-299 70 ports Flash memory product F2MC-16LX CPU PLL clock multiplier circuit ( × 1, × 2, × 3, × 4, 1/2 when PLL stopped) Minimum instruction execution time 62.5 ns (with 4 MHz oscillation clock × 4) Yes Flash memory 64 Kbytes 4 Kbytes 72 ports 1 channel 32 UART(LIN/SCI) 2 channels 1 channel 4 channels 2 channels 1 channel 1 channel 3 channels 8 channels 8 channels No No External 13.5 Kbytes 70 ports Yes Evaluation product 4 MB90925 Series ■ PIN ASSIGNMENTS (TOP VIEW) COM1 COM0 P15/IN0 P14/IN1 P13/IN2 P12/TIN0/IN3 P11/TOT0 P10/PPG2 P07/PPG1/TIN1/SEG31 P06/PPG0/TOT1/SEG30 P05/SCK1/TRG/SEG29 P04/SOT1/SEG28 P03/SIN1/INT7/SEG27 P02/SCK0/INT6/SEG26 P01/SOT0/INT5/SEG25 P00/SIN0/INT4/SEG24 VCC X1 X0 VSS COM2 COM3 P22/SEG0 P23/SEG1 P24/SEG2 P25/SEG3 P26/SEG4 P27/SEG5 P30/SEG6 P31/SEG7 VSS P32/SEG8 P33/SEG9 P34/SEG10 P35/SEG11 P36/SEG12 P37/SEG13 P40/SEG14 P41/SEG15 P42/SEG16 P43/SEG17 P44/SEG18 VCC P45/SEG19 P46/SEG20 P47/SEG21 C P90/SEG22 P91/SEG23 V0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P92/X0A P93/X1A P57/SGA RST P56/SGO/FRCK P55/RX0 P54/TX0 DVSS P87/PWM2M3 P86/PWM2P3 P85/PWM1M3 P84/PWM1P3 DVCC P83/PWM2M2 P82/PWM2P2 P81/PWM1M2 P80/PWM1P2 DVSS P77/PWM2M1 P76/PWM2P1 P75/PWM1M1 P74/PWM1P1 DVCC P73/PWM2M0 P72/PWM2P0 P71/PWM1M0 P70/PWM1P0 DVSS P53/INT3/SCK MD2 V1 V2 V3 AVCC AVRH P50/INT0/ADTG AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P51/INT1/SI P52/INT2/SO MD0 MD1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (FPT-100P-M06) 5 MB90925 Series (TOP VIEW) COM3 COM2 COM1 COM0 P15/IN0 P14/IN1 P13/IN2 P12/TIN0/IN3 P11/TOT0 P10/PPG2 P07/PPG1/TIN1/SEG31 P06/PPG0/TOT1/SEG30 P05/SCK1/TRG/SEG29 P04/SOT1/SEG28 P03/SIN1/INT7/SEG27 P02/SCK0/INT6/SEG26 P01/SOT0/INT5/SEG25 P00/SIN0/INT4/SEG24 VCC X1 X0 VSS P92/X0A P93/X1A P57/SGA 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P22/SEG0 P23/SEG1 P24/SEG2 P25/SEG3 P26/SEG4 P27/SEG5 P30/SEG6 P31/SEG7 VSS P32/SEG8 P33/SEG9 P34/SEG10 P35/SEG11 P36/SEG12 P37/SEG13 P40/SEG14 P41/SEG15 P42/SEG16 P43/SEG17 P44/SEG18 VCC P45/SEG19 P46/SEG20 P47/SEG21 C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 RST P56/SGO/FRCK P55/RX0 P54/TX0 DVSS P87/PWM2M3 P86/PWM2P3 P85/PWM1M3 P84/PWM1P3 DVCC P83/PWM2M2 P82/PWM2P2 P81/PWM1M2 P80/PWM1P2 DVSS P77/PWM2M1 P76/PWM2P1 P75/PWM1M1 P74/PWM1P1 DVCC P73/PWM2M0 P72/PWM2P0 P71/PWM1M0 P70/PWM1P0 DVSS 6 P90/SEG22 P91/SEG23 V0 V1 V2 V3 AVCC AVRH P50/INT0/ADTG AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P51/INT1/SI P52/INT2/SO MD0 MD1 MD2 P53/INT3/SCK 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (FPT-100P-M05) MB90925 Series ■ PIN DESCRIPTIONS Pin no. LQFP*1 80 81 78 QFP*2 82 83 80 Pin name X0 X1 P92 X0A P93 77 75 79 77 X1A RST P00 83 85 SIN0 INT4 SEG24 P01 84 86 SOT0 INT5 SEG25 P02 85 87 SCK0 INT6 SEG26 P03 86 88 SIN1 INT7 SEG27 P04 87 89 SOT1 SEG28 P05 88 90 SCK1 TRG SEG29 E E J E E J I/O circuit type*3 A G A G A B Function High speed oscillator input pin High speed oscillator output pin General-purpose I/O port Low speed oscillator input pin. If no oscillator is connected, apply pull-down processing. General-purpose I/O port Low speed oscillator output pin. If no oscillator is connected, leave open. Reset input pin General-purpose input/output port UART ch.0 serial data input pin INT4 external interrupt input pin LCD controller/driver segment output General-purpose input/output port UART ch.0 serial data output pin INT5 external interrupt input pin LCD controller/driver segment output General-purpose input/output port UART ch.0 serial clock input/output pin INT6 external interrupt input pin LCD controller/driver segment output General-purpose input/output port UART ch.1 serial data input pin INT7 external interrupt input pin LCD controller/driver segment output General-purpose input/output port UART ch.1 serial data output pin LCD controller/driver segment output General-purpose input/output port UART ch.1 serial clock input/output pin 16-bit PPG ch.0 to ch.2 external trigger input pin LCD controller/driver segment output (Continued) 7 MB90925 Series Pin no. LQFP*1 QFP*2 Pin name P06 89 91 PPG0 TOT1 SEG30 P07 90 92 PPG1 TIN1 SEG31 91 92 93 94 P10 PPG2 P11 TOT0 P12 93 95 TIN0 IN3 94 to 96 97 to 100 96 to 98 99, 100, 1, 2 3 to 8 P13 to P15 IN2 to IN0 COM0 to COM3 P22 to P27 1 to 6 SEG0 to SEG5 P30 to P37 SEG6 to SEG13 P40 to P47 SEG14 to SEG21 P90, P91 26, 27 28, 29 SEG22, SEG23 P50 34 36 INT0 ADTG I/O circuit type*3 16-bit PPG ch.0 output pin Function General-purpose input/output port E 16-bit reload timer ch.1 TOT output pin LCD controller/driver segment output General-purpose input/output port 16-bit PPG ch.1 output pin 16-bit reload timer ch.1 TIN output pin LCD controller/driver segment output General-purpose input/output port 16-bit PPG ch.2 output pin General-purpose input/output port 16-bit reload timer ch.0 TOT output pin General-purpose input/output port 16-bit reload timer ch.0 TIN output pin Input capture ch.3 trigger input pin General-purpose input/output port Input capture ch.2 to ch.0 trigger input pins LCD controller/driver common output pins General-purpose input/output ports E G G G G I E LCD controller/driver segment output pins General-purpose input/output port 7, 8, 10 to 15 16 to 20, 22 to 24 9, 10, 12 to 17 18 to 22, 24 to 26 E LCD controller/driver segment output pins General-purpose input/output port E LCD controller/driver segment output pins General-purpose input/output port E LCD controller/driver segment output pins General-purpose input/output port G INT0 external interrupt input pin A/D converter external trigger input pin (Continued) 8 MB90925 Series Pin no. LQFP*1 36 to 39, 41 to 44 QFP*2 38 to 41, 43 to 46 Pin name P60 to P67 AN0 to AN7 P51 45 47 INT1 SI P52 46 48 INT2 SO P53 50 52 INT3 SCK P70 to P73 52 to 55 54 to 57 PWM1P0, PWM1M0, PWM2P0, PWM2M0 P74 to P77 57 to 60 59 to 62 PWM1P1, PWM1M1, PWM2P1, PWM2M1 P80 to P83 62 to 65 64 to 67 PWM1P2, PWM1M2, PWM2P2, PWM2M2 P84 to P87 67 to 70 69 to 72 PWM1P3, PWM1M3, PWM2P3, PWM2M3 P54 TX0 P55 RX0 I/O circuit type*3 F Function General-purpose input/output port A/D converter input pins General-purpose input/output port K INT1 external interrupt input pin SIO data input pin General-purpose input/output port G INT2 external interrupt input pin SIO data output pin General-purpose input/output port G INT3 external interrupt input pin SIO clock input/output pin General-purpose input/output port H Stepping motor controller ch.0 output pins General-purpose input/output port H Stepping motor controller ch.1 output pins General-purpose input/output port H Stepping motor controller ch.2 output pins General-purpose input/output port H Stepping motor controller ch.3 output pins 72 73 74 75 G G General-purpose input/output port CAN interface 0 TX output pin General-purpose output port CAN interface 0 RX input pin (Continued) 9 MB90925 Series (Continued) Pin no. LQFP*1 QFP*2 Pin name P56 74 76 SGO FRCK 76 28 to 31 56, 66 78 30 to 33 58, 68 P57 SGA V0 to V3 DVCC DVSS AVCC AVSS AVRH MD0, MD1 MD2 C VCC VSS G ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ C C/D*4 ⎯ ⎯ ⎯ G I/O circuit type*3 Function General-purpose input/output port Sound generator SGO output pin Free-run timer clock input pin General-purpose input/output port Sound generator SGA output pin LCD controller /driver reference power supply pins Power supply input pins dedicated for high current output buffer (pin numbers 54 to 57, 59 to 62, 64 to 67, 69 to 72) . Power supply GND pins dedicated for high current output buffer (pin numbers 54 to 57, 59 to 62, 64 to 67, 69 to 72) . A/D converter dedicated power supply input pin A/D converter dedicated power supply GND pin A/D converter Vref + input pin Test mode input pins. Connect to VCC. Test mode input pin. Connect to VSS. External capacitor pin. Connect an 0.1 µF capacitor between this pin and VSS. Power supply input pins Power supply GND pins 51, 61, 71 53, 63, 73 32 35 33 47, 48 49 25 21, 82 34 37 35 49, 50 51 27 23, 84 9, 40, 79 11, 42, 81 *1: FPT-100P-M05 *2: FPT-100P-M06 *3: For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE” *4: Type C in MB90F927 and MB90F927S, type D in MB90V925-101 and MB90V925-102. 10 MB90925 Series ■ I/O CIRCUIT TYPE Type X1 Xout Circuit Remarks • High-speed oscillation pin Oscillation feedback resistance : approx. 1 MΩ (X0, X1 : MAIN) • Low-speed oscillation pin Oscillation feedback resistance : approx. 10 MΩ (X0A, X1A : SUB) A X0 Standby control signal Input dedicated pin (with pull-up resistance) • Pull-up resistance attached : approx. 50 kΩ • Hysteresis input (VIH/VIL = 0.8VCC/0.2VCC) Input dedicated pin Hysteresis input (VIH/VIL = 0.8VCC/0.2VCC) Input dedicated pin (with pull-down resistance) • Pull-down resistance attached : approx. 50 kΩ • Hysteresis input (VIH/VIL = 0.8VCC/0.2VCC) LCDC output common generalpurpose port • CMOS output (IOH/IOL = ± 4 mA) • Hysteresis input (VIH/VIL = 0.8VCC/0.2VCC) • Automotive input (VIH/VIL = 0.8VCC/0.5VCC) B Hysteresis input C Hysteresis input Hysteresis input D P-ch Pout Nout LCDC output Hysteresis input Standby control signal or LCDC output switching signal N-ch E Automotive input Standby control signal or LCDC output switching signal (Continued) 11 MB90925 Series Type Circuit Remarks A/D converter input common generalpurpose port • CMOS output (IOH/IOL = ± 4 mA) • Hysteresis input (VIH/VIL = 0.8VCC/0.2VCC) • Automotive input (VIH/VIL = 0.8VCC/0.5VCC) P-ch N-ch Pout Nout Analog input Hysteresis input Standby control signal or Analog input enable signal Automotive input Standby control signal or Analog input enable signal F P-ch Pout Nout Hysteresis input Standby control signal Automotive input Standby control signal N-ch G General-purpose port • CMOS output (IOH/IOL = ± 4 mA) • Hysteresis input (VIH/VIL = 0.8VCC/0.2VCC) • Automotive input (VIH/VIL = 0.8VCC/0.5VCC) P-ch Pout high current output Nout high current output N-ch H Hysteresis input Standby control signal Automotive input Standby control signal High current output common generalpurpose port • CMOS output (IOH/IOL = ± 30 mA) • Hysteresis input (VIH/VIL = 0.8VCC/0.2VCC) • Automotive input (VIH/VIL = 0.8VCC/0.5VCC) (Continued) 12 MB90925 Series (Continued) Type Circuit Remarks LCDC output pin (COM pin) P-ch I N-ch LCDC output P-ch Pout Nout LCDC output N-ch J Hysteresis input Standby control signal or LCDC output enable signal Automotive input Standby control signal or LCDC output enable signal CMOS input (SIN) Standby control signal or LCDC output enable signal LCDC output common generalpurpose port (serial input) • CMOS output (IOH/IOL = ± 4 mA) • Hysteresis input (VIH/VIL = 0.8VCC/0.2VCC) • CMOS input (SIN) (VIH/VIL = 0.7VCC/0.3VCC) • Automotive input (VIH/VIL = 0.8VCC/0.5VCC) P-ch Pout Nout Hysteresis input Standby control signal Automotive input Standby control signal CMOS input (SIN) Standby control signal N-ch K General-purpose port (serial input) • CMOS output (IOH/IOL = ± 4 mA) • Hysteresis input (VIH/VIL = 0.8VCC/0.2VCC) • CMOS input (SIN) (VIH/VIL = 0.7VCC/0.3VCC) • Automotive input (VIH/VIL = 0.8VCC/0.5VCC) 13 MB90925 Series ■ HANDLING DEVICES • Strictly observe maximum rated voltages (preventing latch-up) In CMOS IC devices, a condition known as latch-up may occur if voltages higher than VCC or lower than VSS are applied to input or output pins other than medium-or high-voltage pins, or if the voltage applied between VCC and VSS exceeds the rated voltage level. In a latch-up condition, the power supply current can increase dramatically and may destroy semiconductor elements. In using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings. Also care must be taken when the analog system power supply is switched on or off to ensure that the analog power supply (AVCC, AVRH) , the analog input voltages and the power supply voltage for the high current output buffer pins (DVCC) do not exceed the digital power supply voltage (VCC) . Once the digital power supply voltage (VCC) has been disconnected, the analog power supply (AVCC, AVRH) and the power supply voltage for the high current output buffer pins (DVCC) may be turned on in any sequence. • Stable supply voltage Even within the warranted operating range of VCC power supply voltage, rapid fluctuations in the power supply voltage can cause malfunctions. The recommended stability for ripple fluctuations (P-P value) at commercial frequencies (50 Hz/60 Hz) should be within 10% of the standard VCC value, and voltage fluctuations that occur during switching of power supplies etc. should be limited to transient fluctuation rates of 0.1 V/ms or less. • Notes on energization Power-on procedures In order to prevent the built-in step-down circuits from malfunctioning, the voltage rising time (0.2 V to 2.7 V) during power-on should be attained within 50 µs. • Treatment of unused pins If unused input pins are left open, they may cause malfunctions or latch-up which may lead to permanent damage to the semiconductor. Unused input pins should therefore be pulled up or pulled down through a resistor of at least 2 kΩ. Any unused input/output pins should be left open in output status, or if found set to input status, they should be treated in the same way as input pins. • Treatment of A/D converter power supply pins Even if the A/D converter is not used, pins should be connected so that AVCC = VCC, and AVSS = AVRH = VSS. • Notes on Using an external clock Even when an external clock is used, an oscillation stabilization wait time is required following power-on reset or release from sub clock mode or stop mode. Also, when an external clock is used, it should drive only the X0 pin and the X1 pin should be left open, as shown below. X0 OPEN X1 MB90925 Series Sample external clock connection 14 MB90925 Series • Power supply pins Devices are designed to prevent problems such as latch-up when multiple VCC and VSS pins are used, by providing internal connections between pins having the same potential. However, in order to reduce unwanted radiation, to prevent abnormal operation of strobe signals due to rise in ground level, and to maintain total output current ratings, all VCC and VSS pins should always be connected externally to power supplies and ground respectively. As shown in the figure below, all VCC pins must have the same potential and all VSS pins must be at the same potential. If there are multiple VCC or VSS systems, the device will not operate properly even within the warranted operating range. VCC VSS VCC VSS VCC VSS VCC VSS VSS VCC Power supply input pins (VCC/VSS) In addition, care must be given to connecting the VCC and VSS pins of this device to the current supply source with as low impedance as possible. It is recommended that a 1.0 µF bypass capacitor be connected between the VCC and VSS pins as close to the pins as possible. • Turning-on sequence of power supply to A/D converter and analog inputs The A/D converter power supply (AVCC, AVRH) and analog inputs (AN0 to AN7) must be applied after the digital power supply (VCC) is switched on. When power is shut off, the A/D converter power supply and analog inputs must be cut off before the digital power supply is switched off (VCC) . In both power-on and power-off, care should be taken that AVRH does not exceed AVCC. Even when pins which double as analog input pins are used as input ports, be sure that the input voltage does not exceed AVCC. • Handling the power supply for high-current output buffer pins (DVCC, DVSS) Always apply power supply to high-current output buffer pins (DVCC, DVSS) after the digital power supply (VCC) is turned on. Also when switching the power off, always shut off the power supply to the high-current output buffer pins (DVCC, DVSS) before switching off the digital power supply (VCC) . There is no problem if the high-current output buffer pins and digital power supplies are turned off and on at the same time. Even when the high-current output buffer pins are used as general-purpose ports, the power supply for high current output buffer pins (DVCC, DVSS) should be applied to these pins. • Pull-up/pull-down resistor MB90925 series does not support internal pull-up/pull-down resistor. If necessary, use external components. 15 MB90925 Series • Precautions for when not using a sub clock signal If the X0A and X1A pins are not connected to an oscillator, apply pull-down treatment to the X0A pin and leave the X1A pin open. • Notes on operation when external clock is stopped When there is no external oscillator or external clock input is stopped, performance of the operation by MB90925 series the internal oscillation circuit cannot be guaranteed. 16 MB90925 Series ■ BLOCK DIAGRAM X0, X1 P92/X0A P93/X1A RST Clock control circuit CPU F2MC-16LX core RAM 4 Kbytes* Interrupt controller ROM 64 Kbytes* Low voltage/ CPU operation detection reset F2MC-16LX BUS Sound generator CAN controller P57/SGA P56/SGO/FRCK P55/RX0 P54/TX0 P53/INT3/SCK P52/INT2/SO P51/INT1/SI P50/INT0/ADTG External interrupt (8 channels) P00/SIN0/INT4/SEG24 P01/SOT0/INT5/SEG25 P02/SCK0/INT6/SEG26 P03/SIN1/INT7/SEG27 P04/SOT1/SEG28 P05/SCK1/TRG/SEG29 P06/PPG0/TOT1/SEG30 P07/PPG1/TIN1/SEG31 Prescaler 0/1 UART0/1 Port 5 Prescaler (SIO) SIO P87/PWM2M3 Port 8 P86/PWM2P3 P85/PWM1M3 P84/PWM1P3 P83/PWM2M2 P82/PWM2P2 Stepping motor controller 0/1/2/3 P81/PWM1M2 P80/PWM1P2 P77/PWM2M1 P76/PWM2P1 P75/PWM1M1 P74/PWM1P1 P73/PWM2M0 P72/PWM2P0 Port 7 P71/PWM1M0 P70/PWM1P0 Port 6 Port 0 P67 to P60/ PPG0/1/2 P10/PPG2 P11/TOT0 P12/TIN0/IN3 P13/IN2 P14/IN1 P15/IN0 Real-time watch timer Port 3 ICU0/1/2/3 Port 2 Free-run timer Reload timer 0/1 Port 4 P47 to P40/ SEG21 to SEG14 P37 to P30/ SEG13 to SEG6 P27 to P22/ SEG5 to SEG0 Port F Port 9 A/D converter (8 channels) AN7 to AN0 AVCC/AVSS AVRH P91, P90/ SEG23, SEG22 * : Evaluation device (MB90V925-101/102) No built-in ROM Built-in RAM is 6 Kbytes. LCD controller/ driver COM3 to COM0 V3 to V0 17 MB90925 Series ■ MEMORY MAP Single chip mode (with ROM mirror function) 000000H Peripheral area 0000D0H 000100H Register RAM area Address #2 003900H Peripheral area 004000H ROM area (FF bank image) 010000H Address #1 ROM area FFFFFFH : Internal access memory : Access prohibited Part number MB90F927/MB90F927S MB90V925-101/MB90V925-102 Address #1 FF0000H F80000H Address #2 001100H 003700H Note : To select models without the ROM mirror function, refer to the “ROM Mirror Function Selection Module” in Hardware Manual. The image of the ROM data in the FF bank appears at the top of the 00 bank, in order to enable efficient use of small C compiler models. The lower 16-bit address for the FF bank will be assigned to the same address, so that tables in ROM can be referenced without declaring a “far” indication with the pointer. For example when accessing the address 00C000H, the actual access is to address FFC000H in ROM. Here the FF bank ROM area exceeds 48 Kbytes, so that it is not possible to see the entire area in the 00 bank image. Therefore because the ROM data from FF4000H to FFFFFFH will appear in the image from 004000H to 00FFFFH, it is recommended that the ROM data table be stored in the area from FF4000H to FFFFFFH. 18 MB90925 Series ■ I/O MAP • Other than CAN Interface Address Register name 000000H Port 0 data register 000001H Port 1 data register 000002H Port 2 data register 000003H Port 3 data register 000004H Port 4 data register 000005H Port 5 data register 000006H Port 6 data register 000007H Port 7 data register 000008H Port 8 data register 000009H Port 9 data register 00000AH to 00000FH 000010H Port 0 direction register 000011H Port 1 direction register 000012H Port 2 direction register 000013H Port 3 direction register 000014H Port 4 direction register 000015H Port 5 direction register 000016H Port 6 direction register 000017H Port 7 direction register 000018H Port 8 direction register 000019H Port 9 direction register 00001AH Analog input enable 00001BH to 00001FH 000020H A/D control status register lower 000021H A/D control status register higher 000022H A/D data register lower 000023H A/D data register higher 000024H 000025H 000026H 000027H Compare clear register Timer data register DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 ADER Symbol Read/write PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (Disabled) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (Disabled) ADCS0 ADCS1 ADCR0 ADCR1 CPCLR TCDT TCCSL TCCSH R/W R/W R R R/W R/W R/W R/W R/W R/W 16-bit free-run timer 8/10-bit A/D converter 0 0 0 - - - - 0B 0 0 0 0 0 0 0 -B 0 0 0 0 0 0 0 0B - - - - - - 0 0B XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 1 - 0 0 0 0 0B (Continued) 19 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 6, A/D 0 0 0 0 0 0 0 0B - - 0 0 0 0 0 0B 0 0 0 0 0 0 - -B * 0 0 0 0 0 0 0 0B * 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - - - 0 0 0 0B 1 1 1 1 1 1 1 1B Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Initial value XXXXXXXXB - - XX X XX X B X X X X X X - -B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB - - - -XXXXB 000028H Timer control status register lower 000029H Timer control status register higher MB90925 Series Address Register name Symbol PCNTL0 PCNTH0 PCNTL1 PCNTH1 PCNTL2 PCNTH2 ENIR EIRR ELVRL ELVRH SMR0 SCR0 RDR0/ TDR0 SSR0 ECCR0 ESCR0 BGR00 BGR01 Read/write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name 16-bit PPG0 16-bit PPG1 16-bit PPG2 Initial value 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 00002AH PPG0 control status register lower 00002BH PPG0 control status register higher 00002CH PPG1 control status register lower 00002DH PPG1 control status register higher 00002EH PPG2 control status register lower 00002FH PPG2 control status register higher 000030H External interrupt enable 000031H External interrupt request 000032H External interrupt level lower 000033H External interrupt level higher 000034H Serial mode register 0 000035H Serial control register 0 000036H Reception/transmission data register 0 Extended communication control register 0 External interrupt 000037H Serial status register 0 000038H UART(LIN/SCI) 0 0 0 0 0 1 0 0 0B 0 0 0 0 0 0 XXB 0 0 0 0 0 1 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 000039H Extended status control register 00003AH Baud rate generator register 00 00003BH Baud rate generator register 01 00003CH, 00003DH 00003EH CAN wake-up control register 00003FH 000040H to 00004FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H Timer control status register 0 lower Timer control status register 0 higher Timer register 0/reload register 0 Timer control status register 1 lower Timer control status register 1 higher Timer register 1/reload register 1 (Disabled) CWUCR R/W CAN - - - - - - - 0B (Disabled) Area reserved for CAN interface 0 TMCSR0L TMCSR0H TMR0/ TMRLR0 TMCSR1L TMCSR1H TMR1/ TMRLR1 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0B 16-bit reload timer 0 - - 1 0 0 0 0 0B XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B 16-bit reload timer 1 - - 1 0 0 0 0 0B XXXXXXXXB XXXXXXXXB (Continued) 20 MB90925 Series Address Register name Symbol Read/write LOCR1 LOCR2 SGCRL SGCRH SGFR SGAR SGDR SGTR IPCP0 IPCP1 IPCP2 IPCP3 ICS01 ICE01 ICS23 ICE23 LCRL LCRH LVRC ROMM R/W R/W R/W R/W R/W R/W R/W R/W R Resource name LCD Initial value 1 1 1 1 1 1 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 - - - - 1 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B XXX0X0XXB 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 1 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 1 1 1 0 0 0B X X X X X X X 1B 000058H LCD output control register 1 000059H LCD output control register 2 00005AH Sound control register lower 00005BH Sound control register higher 00005CH Frequency data register 00005DH Amplitude data register 00005EH Decrement grade register 00005FH Tone count register 000060H 000061H 000062H 000063H 000064H 000065H 000066H 000067H Input capture register 0 Input capture register 1 Input capture register 2 Input capture register 3 Sound generator Input capture 0/1 R R Input capture 2/3 R R/W R/W R/W R/W R/W R/W R/W W (Disabled) PWC0 R/W (Disabled) PWC1 R/W (Disabled) PWC2 R/W (Disabled) PWC3 R/W Stepping motor controller 3 Stepping motor controller 2 Stepping motor controller 1 Stepping motor controller 0 Input capture 0/1 Input capture 0/1 Input capture 2/3 Input capture 2/3 LCD controller/ driver Low voltage/CPU operation detection reset ROM mirror 000068H Input capture control status 0/1 000069H Input capture edge register 0/1 00006AH Input capture control status 2/3 00006BH Input capture edge register 2/3 00006CH LCD control register lower 00006DH LCD control register higher 00006EH Low voltage/CPU operation detection reset control register 00006FH ROM mirror 000070H to 00007FH 000080H PWM control register 0 000081H 000082H PWM control register 1 000083H 000084H PWM control register 2 000085H 000086H PWM control register 3 0 0 0 0 0 - - 0B 0 0 0 0 0 - - 0B 0 0 0 0 0 - - 0B 0 0 0 0 0 - - 0B (Continued) 21 MB90925 Series Address 000087H to 000089H Register name Symbol Read/write (Disabled) ADSR0 ADSR1 PIL0 PIL1 R/W R/W R/W R/W (Disabled) R/W R/W R/W R/W (Disabled) WDTC TBTC WTC R/W R/W R/W (Disabled) FMCS ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 R/W (Disabled) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Initial value 00008AH A/D setting register 0 00008BH A/D setting register 1 00008CH Port input level select 0 00008DH Port input level select 1 00008EH to 00009DH A/D Port Input Level Select 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - - 0 0 0 0 0B 00009EH ROM correction control register PACSR 00009FH Delay interrupt/release 0000A0H Power saving mode 0000A1H Clock select 0000A2H to 0000A7H 0000A8H Watchdog control 0000A9H Time-base timer control register DIRR LPMCR CKSCR Address match detection function Delay interrupt Power saving control circuit - - - - - 0 - 0B - - - - - - - 0B 0 0 0 1 1 0 0 0B 1 1 1 1 1 1 0 0B Watchdog timer Time-base timer Watch timer (sub clock) X X X X X 1 1 1B 1 - - 0 0 1 0 0B 1 X 0 0 0 0 0 0B 0000AAH Watch timer control register 0000ABH to 0000ADH 0000AEH Flash control register 0000AFH 0000B0H Interrupt control register 00 0000B1H Interrupt control register 01 0000B2H Interrupt control register 02 0000B3H Interrupt control register 03 0000B4H Interrupt control register 04 0000B5H Interrupt control register 05 0000B6H Interrupt control register 06 0000B7H Interrupt control register 07 0000B8H Interrupt control register 08 0000B9H Interrupt control register 09 0000BAH Interrupt control register 10 0000BBH Interrupt control register 11 0000BCH Interrupt control register 12 22 Flash memory interface 0 0 0 X 0 XX 0B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B Interrupt controller 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B (Continued) Interrupt controller MB90925 Series Address Register name Symbol ICR13 ICR14 ICR15 SMCSL SMCSH SDR SDCR SMR1 SCR1 RDR1/ TDR1 SSR1 ECCR1 ESCR1 BGR10 BGR11 WTCRL WTCRM WTCRH SCCR Read/write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W Resource name Interrupt controller Initial value 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B - - - - 0 0 0 0B 0000BDH Interrupt control register 13 0000BEH Interrupt control register 14 0000BFH Interrupt control register 15 0000C0H Serial mode control register (lower) 0000C1H Serial mode control register (higher) 0000C2H Serial data register 0000C3H Communication prescaler control register SIO Communication prescaler (SIO) 0 0 0 0 0 0 1 0B XXXXXXXXB 0 - - - 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0000C4H Serial mode register 1 0000C5H Serial control register 1 0000C6H Reception/transmission data register 1 Extended communication control register 1 0000C7H Serial status register 1 0000C8H UART(LIN/SCI) 1 0 0 0 0 1 0 0 0B 0 0 0 0 0 0 XXB 0 0 0 0 0 1 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 - - 0 0 0B 0000C9H Extended status control register 1 0000CAH Baud rate generator register 10 0000CBH Baud rate generator register 11 0000CCH Watch timer control register lower 0000CDH Watch timer control register middle 0000CEH Watch timer control register higher 0000CFH Sub clock control register 0000D0H to 0000FFH 001FF0H ROM correction address 0 001FF1H ROM correction address 1 001FF2H ROM correction address 2 001FF3H ROM correction address 3 001FF4H ROM correction address 4 001FF5H ROM correction address 5 003900H to 00391FH 003920H 003921H 003922H 003923H 003924H 003925H PPG0 down counter register PPG0 cycle setting register PPG0 duty setting register Real-time watch timer Sub clock 0 0 0 0 0 0 0 0B - - - - 0 0 0 0B - - - - 0 0 0 0B (Disabled) PADR0 PADR0 PADR0 PADR1 PADR1 PADR1 R/W R/W R/W R/W R/W R/W Address match detection function Address match detection function XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Disabled) 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B 16-bit PPG 0 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued) 23 PDCR0 PCSR0 PDUT0 R W W MB90925 Series Address 003926H, 003927H 003928H 003929H 00392AH 00392BH 00392CH 00392DH 00392EH, 00392FH 003930H 003931H 003932H 003933H 003934H 003935H 003936H to 003957H 003958H Register name Symbol Read/write Resource name Initial value (Disabled) PPG1 down counter register PPG1 cycle setting register PPG1 duty setting register PDCR1 PCSR1 PDUT1 R W W 16-bit PPG 1 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Disabled) PPG2 down counter register PPG2 cycle setting register PPG2 duty setting register PDCR2 PCSR2 PDUT2 R W W 16-bit PPG 2 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Disabled) XXXXXXXXB WTBR WTSR WTMR WTHR WTDR R/W R/W R/W R/W R/W Real time watch timer XXXXXXXXB - - - XXXXXB - - 0 0 0 0 0 0B - - 0 0 0 0 0 0B - - - 0 0 0 0 0B 0 0 - 0 0 0 0 1B 003959H Sub second data register 00395AH 00395BH Second data register 00395CH Minute data register 00395DH Hour data register 00395EH Day data register 00395FH 003960H to LCD display RAM 00396FH 003970H to 00397FH 003980H 003981H 003982H 003983H PWM1 compare register 0 PWM2 compare register 0 (Disabled) VRAM R/W LCD controller/ driver XXXXXXXXB (Disabled) XXXXXXXXB - - - - - - XXB Stepping motor controller 0 XXXXXXXXB - - - - - - XXB - - 0 0 0 0 0 0B - 0 0 0 0 0 0 0B (Continued) PWC10 PWC20 PWS10 PWS20 R/W R/W R/W R/W 003984H PWM1 select register 0 003985H PWM2 select register 0 24 MB90925 Series Address 003986H, 003987H 003988H 003989H 00398AH 00398BH Register name Symbol Read/write Resource name Initial value (Disabled) PWM1 compare register 1 PWM2 compare register 1 PWC11 PWC21 PWS11 PWS21 R/W R/W R/W R/W Stepping motor controller 1 XXXXXXXXB - - - - - - XXB XXXXXXXXB - - - - - - XXB - - 0 0 0 0 0 0B - 0 0 0 0 0 0 0B 00398CH PWM1 select register 1 00398DH PWM2 select register 1 00398EH, 00398FH 003990H 003991H 003992H 003993H PWM1 compare register 2 PWM2 compare register 2 (Disabled) PWC12 PWC22 PWS12 PWS22 R/W R/W R/W R/W Stepping motor controller 2 XXXXXXXXB - - - - - - XXB XXXXXXXXB - - - - - - XXB - - 0 0 0 0 0 0B - 0 0 0 0 0 0 0B 003994H PWM1 select register 2 003995H PWM2 select register 2 003996H, 003997H 003998H 003999H 00399AH 00399BH PWM1 compare register 3 PWM2 compare register 3 (Disabled) PWC13 PWC23 PWS13 PWS23 R/W R/W R/W R/W Stepping motor controller 3 XXXXXXXXB - - - - - - XXB XXXXXXXXB - - - - - - XXB - - 0 0 0 0 0 0B - 0 0 0 0 0 0 0B 00399CH PWM1 select register 3 00399DH PWM2 select register 3 00399EH to 0039FFH 003A00H to 003AFFH 003B00H to 003BFFH 003C00H to 003CFFH 003D00H to 003EFFH (Disabled) Area reserved for CAN interface 0 (Disabled) Area reserved for CAN interface 0 (Disabled) (Continued) 25 MB90925 Series (Continued) • Initial value symbols : “0” : initial value 0 “1” : initial value 1 “X” : initial value undetermined “-” : initial value undetermined (none) • Write/read symbols : “R/W” : read/write enabled “R” : read only “W” : write only • Addresses in the area 0000H to 00FFH are reserved for the principal functions of the MCU. Read access attempts to reserved areas will result in an “X” value. Also, write access to reserved areas is prohibited. * : P22/SEG0 to P27/SEG5 and P30/SEG6 to P35/SEG11 initially will be LCD segment output as LCD output control register LOCR1 (58H) is “11111111B” initially. To use port 2 and port 3 as the general-purpose input/ output ports, set LOCR1 to “00000000B” to disable the LCD segment output first. 26 MB90925 Series • CAN Interface Address 000040H 000041H 000042H 000043H 000044H 000045H 000046H 000047H 000048H 000049H 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH 003C00H 003C01H 003C02H 003C03H 003C04H 003C05H 003C06H 003C07H 003C08H 003C09H 003C0AH 003C0BH 003C0CH 003C0DH 003C0EH 003C0FH Register name Message buffer valid area Transmission request register Transmission cancel register Transmission completed register Receiving completed register Remote request receiving register Receiving overrun register Receiving interrupt enable register Control status register Last event indicator register RX/TX error counter Bit timing register IDE register Transmission RTR register Remote frame receiving wait register Transmission interrupt enable register Symbol BVALR TREQR TCANR TCR RCR RRTRR ROVRR RIER CSR LEIR RTEC BTR IDER TRTRR RFWTR TIER Read/ write R/W R/W W R/W R/W R/W R/W R/W R/W, R R/W R R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 - - - 0 0 0B 0 - - - - 0 - 1B - - - - - - - -B 0 0 0 - 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (Continued) 27 MB90925 Series Address 003C10H 003C11H 003C12H 003C13H 003C14H 003C15H 003C16H 003C17H 003C18H 003C19H 003C1AH 003C1BH Register name Symbol Read/ write Initial value XXXXXXXXB Acceptance mask select register AMSR R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXX- - -B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXX- - -B XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXX- - -B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXX- - -B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXX- - -B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXX- - -B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXX- - -B XXXXXXXXB (Continued) Acceptance mask register 0 AMR0 R/W Acceptance mask register 1 AMR1 R/W 003A00H to General-purpose RAM 003A1FH 003A20H 003A21H 003A22H 003A23H 003A24H 003A25H 003A26H 003A27H 003A28H 003A29H 003A2AH 003A2BH 003A2CH 003A2DH 003A2EH 003A2FH 003A30H 003A31H 003A32H 003A33H ID register 4 ID register 3 ID register 2 ID register 1 ID register 0 ⎯ R/W IDR0 R/W IDR1 R/W IDR2 R/W IDR3 R/W IDR4 R/W 28 MB90925 Series Address 003A34H 003A35H 003A36H 003A37H 003A38H 003A39H 003A3AH 003A3BH 003A3CH 003A3DH 003A3EH 003A3FH 003A40H 003A41H 003A42H 003A43H 003A44H 003A45H 003A46H 003A47H 003A48H 003A49H 003A4AH 003A4BH 003A4CH 003A4DH 003A4EH 003A4FH 003A50H 003A51H 003A52H 003A53H ID register 12 ID register 11 ID register 10 ID register 9 ID register 8 ID register 7 ID register 6 ID register 5 Register name Symbol Read/ write Initial value XXXXXXXXB IDR5 R/W XXXXXXXXB XXXXX- - -B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXX- - -B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXX- - -B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXX- - -B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXX- - -B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXX- - -B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXX- - -B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXX- - -B XXXXXXXXB (Continued) IDR6 R/W IDR7 R/W IDR8 R/W IDR9 R/W IDR10 R/W IDR11 R/W IDR12 R/W 29 MB90925 Series Address 003A54H 003A55H 003A56H 003A57H 003A58H 003A59H 003A5AH 003A5BH 003A5CH 003A5DH 003A5EH 003A5FH 003A60H 003A61H 003A62H 003A63H 003A64H 003A65H 003A66H 003A67H 003A68H 003A69H 003A6AH 003A6BH 003A6CH 003A6DH 003A6EH 003A6FH 003A70H 003A71H 003A72H 003A73H 003A74H 003A75H DLC register 0 DLC register 1 DLC register 2 DLC register 3 DLC register 4 DLC register 5 DLC register 6 DLC register 7 DLC register 8 DLC register 9 DLC register 10 ID register 15 ID register 14 ID register 13 Register name Symbol Read/ write Initial value XXXXXXXXB IDR13 R/W XXXXXXXXB XXXXX- - -B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXX- - -B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXX- - -B XXXXXXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB (Continued) IDR14 R/W IDR15 R/W DLCR0 DLCR1 DLCR2 DLCR3 DLCR4 DLCR5 DLCR6 DLCR7 DLCR8 DLCR9 DLCR10 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 30 MB90925 Series Address 003A76H 003A77H 003A78H 003A79H 003A7AH 003A7BH 003A7CH 003A7DH 003A7EH 003A7FH DLC register 11 DLC register 12 DLC register 13 DLC register 14 DLC register 15 Register name Symbol DLCR11 DLCR12 DLCR13 DLCR14 DLCR15 Read/ write R/W R/W R/W R/W R/W Initial value - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB - - - -XXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB (Continued) 003A80H to Data register 0 (8 bytes) 003A87H 003A88H to Data register 1 (8 bytes) 003A8FH 003A90H to Data register 2 (8 bytes) 003A97H 003A98H to Data register 3 (8 bytes) 003A9FH 003AA0H to Data register 4 (8 bytes) 003AA7H 003AA8H to Data register 5 (8 bytes) 003AAFH 003AB0H to Data register 6 (8 bytes) 003AB7H 003AB8H to Data register 7 (8 bytes) 003ABFH 003AC0H to Data register 8 (8 bytes) 003AC7H 003AC8H to Data register 9 (8 bytes) 003ACFH DTR0 R/W DTR1 R/W DTR2 R/W DTR3 R/W DTR4 R/W DTR5 R/W DTR6 R/W DTR7 R/W DTR8 R/W DTR9 R/W 31 MB90925 Series (Continued) Address Register name Symbol Read/ write R/W Initial value XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB 003AD0H to Data register 10 (8 bytes) 003AD7H 003AD8H to Data register 11 (8 bytes) 003ADFH 003AE0H to Data register 12 (8 bytes) 003AE7H 003AE8H to Data register 13 (8 bytes) 003AEFH 003AF0H to Data register 14 (8 bytes) 003AF7H 003AF8H to Data register 15 (8 bytes) 003AFFH DTR10 DTR11 R/W DTR12 R/W DTR13 R/W DTR14 R/W DTR15 R/W 32 MB90925 Series ■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS Interrupt source Reset INT9 instruction Exception processing CAN0 RX CAN0 TX/NS ( Reserved) *3 SIO *3 EI2OS corresponding × × × × × × Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 Address Interrupt control register ICR ⎯ ⎯ ⎯ ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 Address ⎯ ⎯ ⎯ 0000B0H *1 0000B1H *1 0000B2H *1 0000B3H *1 0000B4H *1 0000B5H *1 Priority *2 High 08H FFFFDCH 09H FFFFD8H 0AH FFFFD4H 0BH FFFFD0H 0CH FFFFCCH 0DH FFFFC8H 0EH FFFFC4H 0FH FFFFC0H 10H FFFFBCH 11H 12H 13H 15H 16H 17H FFFFB8H FFFFB4H FFFFB0H FFFFA8H FFFFA4H FFFFA0H Input capture 0 DTP/external interrupt - ch.0 detected Reload timer 0 DTP/external interrupt - ch.1 detected Input capture 1 DTP/external interrupt - ch.2 detected Input capture 2 DTP/external interrupt - ch.3 detected Input capture 3 DTP/external interrupt - ch.4/ch.5 detected PPG timer 0 DTP/external interrupt - ch.6/ch.7 detected PPG timer 1 Reload timer 1 PPG timer 2 Real time watch timer Free-run timer overflow A/D converter conversion end Free-run timer clear Sound generator Time-base timer Watchdog (sub clock) UART 1 RX UART 1 TX UART 0 RX UART 0 TX Flash memory status Delay interrupt generator module × × × × × × × × 14H FFFFACH 18H FFFF9CH 19H 1AH 1BH FFFF98H FFFF94H FFFF90H ICR06 0000B6H *1 ICR07 0000B7H *1 1CH FFFF8CH 1DH FFFF88H 1EH 1FH 21H 22H 23H 25H 26H 27H 29H 2AH FFFF84H FFFF80H FFFF78H FFFF74H FFFF70H FFFF68H FFFF64H FFFF60H FFFF58H FFFF54H ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 0000B8H *1 0000B9H *1 0000BAH *1 0000BBH *1 0000BCH *1 0000BDH *1 0000BEH *1 0000BFH *1 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 20H FFFF7CH 24H FFFF6CH 28H FFFF5CH Low 33 (Continued) MB90925 Series (Continued) : Usable, with EI2OS stop function : Usable : Usable when interrupt sources sharing ICR are not in use × : Unusable *1 : • Peripheral functions sharing the ICR register have the same interrupt level. • If peripheral functions sharing the ICR register are using expanded intelligent I/O services, one or the other cannot be used. • When peripheral functions are sharing the ICR register and one specifies expanded intelligent I/O services, the interrupt from the other function cannot be used. *2 : Priority applies when interrupts of the same level are generated. *3 : SIO and CAN1 TX/NX will share IRQ3 in evaluation chip (MB90V925-101/102) . 34 MB90925 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol VCC Power supply voltage*1 AVCC AVRH DVCC Input voltage*1 Output voltage* 1 Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 − 400 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VCC + 0.3 VCC + 0.3 + 400 4 15 40 4 30 100 330 50 250 −15 −40 −4 −30 −100 −330 −50 −250 500 +105 +150 Unit V V V V V V µA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mW °C °C *7 *7 AVCC = VCC*2 Remarks AVCC ≥ AVRH*2 DVCC = VCC*2 *3 VI VO ICLAMP IOL1 IOL2 IOLAV1 IOLAV2 ΣIOL1 ΣIOL2 ΣIOLAV1 ΣIOLAV2 I I I I OH1 4 Maximum clamp current “L” level maximum output current*4 “L” level average output current*5 “L” level maximum total output current “L” level average total output current “H” level maximum output current “H” level average output current “H” level maximum total output current “H” level average total output current Power consumption Operating temperature Storage temperature Total maximum clamp current Σ| ICLAMP | Other than P70 to P77 and P80 to P87 P70 to 77 and P80 to87 Other than P70 to P77 and P80 to P87 P70 to 77 and P80 to 87 Other than P70 to P77 and P80 to P87 P70 to 77 and P80 to 87 Other than P70 to P77 and P80 to P87 P70 to 77 and P80 to 87 Other than P70 to P77 and P80 to P87 P70 to 77 and P80 to 87 Other than P70 to P77 and P80 to P87 P70 to 77 and P80 to 87 Other than P70 to P77 and P80 to P87 P70 to 77 and P80 to 87 Other than P70 to P77 and P80 to P87 P70 to 77 and P80 to 87 * * OH2 4 OHAV1 5 * * OHAV2 5 ΣIOH1 ΣIOH2 ΣI ΣI OHAV1 6 * * ⎯ ⎯ ⎯ −40 −55 OHAV2 6 PD TA TSTG *1 : The parameter is based on VSS = AVSS = DVSS = 0.0 V. *2 : AVCC, AVRH and DVCC shall never exceed VCC. Also, AVRH shall never exceed AVCC. *3 : The maximum current to/from and input are limited by some means with external components, the ICLAMP rating supersedes the VI rating. *4 : Maximum output current is defined as the peak value of the current of any one of the corresponding pins. *5 : Average output current is defined as the value of the average current flowing over 100 ms at any one of the corresponding pins. The “average value” can be calculated from the formula of “operating current” times “operating factor”. (Continued) 35 MB90925 Series (Continued) *6 : Average total output current is defined as the value of the average current flowing over 100 ms at all of the corresponding pins. The “average value” can be calculated from the formula of “operating current” times “ operating factor”. *7 : • Applicable to pins : P10 to P15, P50 to P57, P70 to P77, P80 to P87 • Use within recommended operating conditions. • Use at DC voltage (current) . • The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the +B signal is applied, the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. • Care must be taken not to leave the +B input pin open. • Note that analog system input/output pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. • Sample recommended circuits : • Input/Output equivalent circuits Protective diode VCC Limiting resistance +B input (0 V to 16 V) P-ch N-ch R WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 36 MB90925 Series 2. Recommended Operating Conditions (VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Value Min 3.7 Max 5.5 Unit Remarks (MB90F927/MB90F927S) Low voltage detection reset starts to work when power supply voltage is 4.0 V ± 0.3 V. Holding stop operation status (MB90F927/MB90F927S) Use a ceramic capacitor or other capacitor of equivalent frequency characteristics. A bypass capacitor on the VCC pin should have a capacitance greater than Cs. Power supply voltage VCC AVCC DVCC V 4.3 5.5 V µF °C Smoothing capacitor* Operating temperature CS 0.1 − 40 1.0 + 105 TA * : For smoothing capacitor Cs connections, refer to the illustration below. • C pin connection diagram C CS VSS DVSS AVSS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 37 MB90925 Series 3. DC Characteristics (VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Parameter Symbol Pin name ⎯ Conditions ⎯ Value Min 0.8 VCC Typ ⎯ Max VCC + 0.3 Unit Remarks Pin inputs if Automotive input levels are selected*1 Pin inputs if CMOS hysteresis input levels are selected*1 (0.8Vcc/0.2Vcc CMOS hysteresis is selected for P00, P03 and P51) Pin inputs if 0.7Vcc/ 0.3Vcc CMOS hysteresis input levels is selected for P00, P03 and P51. RST input pin (CMOS hysteresis) MD pin*2 Pin inputs if Automotive input levels are selected*1 Pin inputs if CMOS hysteresis input levels are selected*1 (0.8Vcc/0.2Vcc CMOS hysteresis is selected for P00, P03 and P51) Pin inputs if 0.7Vcc/ 0.3Vcc CMOS hysteresis input levels is selected for P00, P03 and P51. RST input pin (CMOS hysteresis) MD pin*2 (Continued) VIHA V VIHS2 “H” level input voltage ⎯ ⎯ 0.8 VCC ⎯ VCC + 0.3 V VIHS1 ⎯ ⎯ 0.7 VCC ⎯ VCC + 0.3 V VIHR VIHM VILA ⎯ ⎯ ⎯ ⎯ 0.8 VCC VCC − 0.3 VSS − 0.3 ⎯ ⎯ ⎯ VCC + 0.3 VCC + 0.3 V V V ⎯ ⎯ 0.5 VCC VILS2 “L” level input voltage ⎯ ⎯ VSS − 0.3 ⎯ 0.2 VCC V VILS1 ⎯ ⎯ VSS − 0.3 ⎯ 0.3 VCC V VILR VILM ⎯ ⎯ ⎯ ⎯ VSS − 0.3 VSS − 0.3 ⎯ ⎯ 0.2 VCC VSS + 0.3 V V 38 MB90925 Series (VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Parameter Symbol Pin name Conditions Operating frequency FCP = 16 MHz, normal operation ICC Operating frequency FCP = 16 MHz, writing Flash memory Operating frequency FCP = 16 MHz, erasing Flash memory ICCS Operating frequency FCP = 16 MHz, sleep mode Operating frequency FCP = 2 MHz, time-base timer mode VCC ICTSPLL Operating frequency FCP = 16 MHz, PLL timer mode, External frequency = 4MHz Operating frequency FCP = 8 kHz, TA = + 25 °C, sub clock operation Operating frequency FCP = 8 kHz, TA = + 25 °C, sub sleep operation Operating frequency FCP = 8 kHz, TA = + 25 °C, watch mode TA = + 25 °C, stop mode All input pins Other than VCC, VSS, DVCC, DVSS, AVCC, AVSS, C, P70 to P77, P80 to P87 VCC = DVCC = AVCC = 5.5 V VSS < VI < VCC Value Min ⎯ Typ 35 Max 45 Unit Remarks mA ⎯ 50 60 mA Flash mA memory product mA ⎯ 50 60 ⎯ 12 20 ICTS Power supply current*3 ⎯ 0.4 1.0 mA ⎯ 4 7 mA ICCL ⎯ 90 200 µA ICCLS ⎯ 60 150 µA ICCT ICCH Input leakage current IIL ⎯ ⎯ −5 60 50 ⎯ 130 130 +5 µA µA µA Input capacitance 1 CIN1 ⎯ ⎯ 5 15 pF (Continued) 39 MB90925 Series (Continued) (VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Symbol CIN2 RUP RDOWN Pin name P70 to P77, P80 to P87 RST MD2 Other than P70 to P77, P80 to P87 P70 to P77, P80 to P87 Other than P70 to P77, P80 to P87 P70 to P77, P80 to P87 PWM1Pn, PWM1Mn, PWM2Pn, PWM2Mn, (n = 0 to 3) PWM1Pn, PWM1Mn, PWM2Pn, PWM2Mn, (n = 0 to 3) V0 to V3 COMn (n = 0 to 3) SEGn (n = 0 to 31) V0 to V3 COMm (m = 0 to 3) SEGn (n = 0 to 31) Conditions ⎯ ⎯ ⎯ VCC = 4.5 V IOH = −4.0 mA Value Min ⎯ 25 25 VCC − 0.5 Typ 15 50 50 ⎯ ⎯ ⎯ ⎯ Max 45 100 100 ⎯ ⎯ 0.4 Unit pF kΩ kΩ V Except Flash memory product Remarks Parameter Input capacitance 2 Pull-up resistance Pull-down resistance Output “H” voltage 1 Output “H” voltage 2 Output “L” voltage 1 Output “L” voltage 2 Large current output drive capacity variation 1 VOH1 VOH2 VCC = 4.5 V VCC − IOH = −30.0 mA 0.5 VCC = 4.5 V IOL = 4.0 mA VCC = 4.5 V IOL = 30.0 mA VCC = 4.5 V IOH = 30.0 mA VOH2 maximum variation VCC = 4.5 V IOH = 30.0 mA VOL2 maximum variation ⎯ ⎯ ⎯ ⎯ ⎯ V VOL1 V VOL2 0.55 V ∆VOH2 0 ⎯ 90 mV *4 Large current output drive capacity variation 2 LCD internal divider resistance COM0 to COM3 output impedance SEG0 to SEG31 output impedance ∆VOL2 0 ⎯ 90 mV *4 RLCD RVCOM RVSEG 50 ⎯ ⎯ 100 ⎯ ⎯ 200 2.5 15 kΩ kΩ kΩ LCD leakage current ILCDC ⎯ −5.0 ⎯ +5.0 µA *1 : All input pins except X0, X0A, MD0, MD1, and MD2. *2 : MD0, MD1, and MD2 pins. *3 : Power supply current values assume external clock feed from the X1 pin and X1A pin. Users must be aware that power supply current levels differ depending on whether an external clock or oscillator is used. *4 : Defined as maximum variation in VOH2/VOL2 with all ch.0 PWM1P0/PWM1M0/PWM2P0/PWM2M0 simultaneously ON. Similarly for other channels. 40 MB90925 Series 4. AC Characteristics (1) Clock timing (VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Parameter Symbol Pin name Conditions Value Min 4 4 Base oscillation clock frequency FC X0, X1 4 4 4 FLC Base oscillation clock cycle time Input clock pulse width Input clock rise and fall time Internal operating clock frequency Internal operating clock cycle time tCYL tLCYL PWH, PWL PWLH, PWLL tcr, tcf FCP FLCP tCP tLCP X0A, X1A X0, X1 X0A, X1A X0 X0A X0, X0A ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 10 ⎯ ⎯ 2 ⎯ 62.5 ⎯ Typ ⎯ ⎯ ⎯ ⎯ ⎯ 32.768 250 30.5 ⎯ 15.2 ⎯ ⎯ 8.192 — 122.1 Max 12 12 8 5.33 4 ⎯ ⎯ ⎯ ⎯ ⎯ 5 16 ⎯ 500 ⎯ Unit Remarks MHz 1/2 (when PLL stops) MHz PLL x 1 MHz PLL x 2 MHz PLL x 3 MHz PLL x 4 kHz ns µs ns µs ns MHz external clock signal Using main clock (PLL clock) Using main clock (PLL clock) Using sub clock Use duty ratio of 40 to 60% as a guideline kHz Using sub clock ns µs • X0 clock timing tCYL X0 PWH tcf PWL tcr 0.8 VCC 0.2 VCC • X0A clock timing tLCYL X0A PWLH tcf PWLL tcr 0.8 VCC 0.2 VCC 41 MB90925 Series • Range of guaranteed operation Relation between internal operating clock frequency and power supply voltage guaranteed operation range Power supply voltage VCC (V) 5.5 4.0 3.7 Guaranteed A/D converter operation range Guaranteed PLL operation range 2 4 Internal operating clock frequency FCP (MHz) 16 Note : The MB90F927/ MB90F927S enters reset mode at power supply voltage below 4 V ± 0.3 V. Guaranteed oscillation frequency range 16 Internal clock fcp (MHz) x4 x3 x2 12 8 4 2 4 8 External clock Fc (MHz) x1 x 1/2 (PLL off) 12 16 42 MB90925 Series (2) Reset input (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Parameter Symbol Pin name Value Min 500 Reset input time tRSTL RST Oscillator oscillation time* + 100 µs 100 Max ⎯ ⎯ ⎯ Unit ns ms µs Remarks At normal operation At stop mode, sub clock mode, sub sleep mode, and watch mode At time-base timer mode *: Oscillator’s oscillation time is the time that the amplitude reaches 90%. The oscillation time of a crystal oscillator is between several ms and tens of ms. The oscillation time of a ceramic oscillator is between hundreds of µs and several ms. The oscillation time of an external clock is 0 ms. • At normal operation tRSTL RST 0.2 VCC 0.2 VCC • At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on tRSTL RST 0.2 Vcc 90 % of amplitude 0.2 Vcc X0 Internal operation clock Oscillator oscillation time 100 µs Oscillation stabilization wait time Execution of the instruction Internal reset 43 MB90925 Series (3) Power-on reset (VSS = 0.0 V, TA = −40 °C to +105 °C) Parameter Power supply rise time Power supply start voltage Power supply attained voltage Power supply cutoff time Symbol Pin Conditions name Value Min 0.05 ⎯ Max 30 0.2 ⎯ ⎯ Unit ms V V ms Remarks tR VOFF VON tOFF VCC ⎯ 2.7 50 Waiting time until power-on tR VCC 2.7 V 0.2 V 0.2 V tOFF 0.2 V Note : Extreme variations in power supply voltage may activate a power-on reset. As the illustration below shows, when varying power supply voltage during operation, the use of a smooth voltage rise with suppressed fluctuation is recommended. Also in this situation, the PLL clock on the device should not be used, however it is permissible to use the PLL clock during a voltage drop of 1V/s or less. VCC 5.0 V 3.0 V 0V A rise slope of 50 mV/ms or less is recommended VSS RAM data hold 44 MB90925 Series (4) SIO timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Parameter Serial clock cycle time SCK ↓ → SO delay time Valid SI → SCK ↑ SCK ↑ → valid SI hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SO delay time Valid SI → SCK ↑ SCK ↑ → valid SI hold time Symbol Pin name SCK SCK, SO SCK, SI SCK SCK, SO SCK, SI Conditions Value Min 8 tCP −80 100 60 4 tCP 4 tCP ⎯ 60 60 Max ⎯ + 80 ⎯ ⎯ ⎯ ⎯ 150 ⎯ ⎯ Unit ns ns ns ns ns ns ns ns ns tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Internal shift clock mode output pin CL = 80 pF + 1TTL External shift clock mode output pin CL = 80 pF + 1TTL Notes : • AC ratings are for CLK synchronous mode. • CL is load capacitance connected to pin during testing. • tCP is internal operating clock cycle time. Refer to “ (1) Clock timing”. • Internal shift clock mode SCK 0.8 V tSLOV 2.4 V tSCYC 2.4 V 0.8 V SO 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.5 VCC SI 0.5 VCC • External shift clock mode SCK 0.5 VCC tSLOV 2.4 V tSLSH 0.8 VCC 0.5 VCC tSHSL 0.8 VCC SO 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.5 VCC SI 0.5 VCC 45 MB90925 Series (5) UART0/1 (LIN/SCI) • Bit setting: ESCR0/1:SCES=0, ECCR0/1:SCDE=0 (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time Serial clock “L” pulse width Serial clock “H” pulse width SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time SCK fall time SCK rise time Symbol tSCYC tSLOVI tIVSHI tSHIXI tSLSH tSHSL tSLOVE tIVSHE tSHIXE tF tR Pin name SCK0, SCK1 SCK0, SCK1, SOT0, SOT1 SCK0, SCK1, SIN0, SIN1 SCK0, SCK1 SCK0, SCK1, SOT0, SOT1 SCK0, SCK1, SIN0, SIN1 SCK0, SCK1 Internal shift clock mode output pins are CL = 80 pF + 1TTL Conditions Value Min 5 tCP − 50 tCP + 80 0 tCP + 10 3 tCP − tR Max ⎯ + 50 ⎯ ⎯ ⎯ ⎯ 2 tCP + 60 ⎯ ⎯ 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns External shift clock mode output pins are CL = 80 pF + 1TTL ⎯ 30 tCP + 30 ⎯ ⎯ Notes : • AC characteristic in CLK synchronized mode. • CL is load capacity value of pins when testing. • tCP is internal operating clock cycle time (machine clock). Refer to “ (1) Clock timing”. 46 MB90925 Series • Internal shift clock mode SCK tSLSH VIH VIL tF tSLOVE 2.4 V VIL tR VIH tSHSL VIH SOT 0.8 V tIVSHE tSHIXE VIH VIH VIL SIN VIL • External shift clock mode SCK tSLSH VIH VIL tF tSLOVE 2.4 V VIL tR VIH tSHSL VIH SOT 0.8 V tIVSHE tSHIXE VIH VIH VIL SIN VIL 47 MB90925 Series • Bit setting: ESCR0/1:SCES=1, ECCR0/1:SCDE=0 (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Parameter Serial clock cycle time SCK ↑ → SOT delay time Valid SIN → SCK ↓ SCK ↓ → valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↑ → SOT delay time Valid SIN → SCK ↓ SCK ↓ → valid SIN hold time SCK fall time SCK rise time Symbol tSCYC tSLOVI tIVSHI tSHIXI tSHSL tSLSH tSLOVE tIVSHE tSHIX tF tR Pin name SCK0, SCK1 SCK0, SCK1, SOT0, SOT1 SCK0, SCK1, SIN0, SIN1 SCK0, SCK1 SCK0, SCK1, SOT0, SOT1 SCK0, SCK1, SIN0, SIN1 SCK0, SCK1 Internal shift clock mode output pins are CL = 80 pF + 1TTL Conditions Value Min 5 tCP − 50 tCP + 80 0 3 tCP − tR tCP + 10 Max ⎯ + 50 ⎯ ⎯ ⎯ ⎯ 2 tCP + 60 ⎯ ⎯ 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns External shift clock mode output pins are CL = 80 pF + 1TTL ⎯ 30 tCP + 30 ⎯ ⎯ 48 MB90925 Series • Internal shift clock mode SCK tSCYC 2.4 V 0.8 V tSHOVI 2.4 V 2.4 V SOT 0.8 V tIVSLI tSLIXI VIH VIH VIL SIN VIL • External shift clock mode SCK VIL tR tSHOVE 2.4 V tSHSL VIH VIH VIL tF VIL tSLSH SOT 0.8 V tIVSLE tSLIXE VIH VIH VIL SIN VIL 49 MB90925 Series • Bit setting: ESCR0/1:SCES=0, ECCR0/1:SCDE=1 (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Parameter Serial clock cycle time SCK ↑ → SOT delay time Valid SIN → SCK ↓ SCK ↓ → valid SIN hold time SOT → SCK ↓ delay time Symbol tSCYC tSHOVI tIVSLI tSLIXI tSOVLI Pin name SCK0, SCK1 SCK0, SCK1, SOT0, SOT1 SCK0, SCK1, SIN0, SIN1 SCK0, SCK1, SOT0, SOT1 Internal clock operation output pins are CL = 80 pF + 1TTL Conditions Value Min 5 tCP − 50 tCP + 80 0 3 tCP − 70 Max ⎯ + 50 ⎯ ⎯ ⎯ Unit ns ns ns ns ns Notes : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing”rating for tCP. SCK 0.8 V tSOVLI 2.4 V tSCYC 2.4 V 0.8 V tSHOVI 2.4 V 0.8 V tIVSLI tSLIXI VIH VIL SOT 0.8 V VIH SIN VIL 50 MB90925 Series • Bit setting: ESCR0/1:SCES=1, ECCR0/1:SCDE=1 (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time SOT → SCK ↑ delay time Symbol tSCYC tSLOVI tIVSHI tSHIXI tSOVHI Pin name SCK0, SCK1 SCK0, SCK1, SOT0, SOT1 SCK0, SCK1, SIN0, SIN1 SCK0, SCK1, SOT0, SOT1 Internal clock operation output pins are CL = 80 pF + 1TTL Conditions Value Min 5 tCP − 50 tCP + 80 0 3 tCP − 70 Max ⎯ + 50 ⎯ ⎯ ⎯ Unit ns ns ns ns ns Notes : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing”rating for tCP. SCK tSCYC 2.4 V 0.8 V tSOVHI 2.4 V tSLOVI 2.4 V 0.8 V tIVSHI tSHIXI VIH VIL 2.4 V SOT 0.8 V VIH SIN VIL 51 MB90925 Series (6) Timer input timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Parameter Input pulse width Symbol tTIWH tTIWL Pin name TIN0, TIN1, IN0 to IN3 Conditions ⎯ Value Min 4 tCP Max ⎯ Unit ns Note : tCP is internal operating clock cycle time. Refer to “ (1) Clock timing”. • Timer input timing tTIWH tTIWL VIH VIL VIL TIN0 , TIN1 IN0 to IN3 VIH 52 MB90925 Series (7) Trigger input timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Parameter Input pulse width Symbol tTRGH, tTRGL Pin name INT0 to INT7 ADTG Conditions ⎯ ⎯ Value Min 200 tCP + 200 Max ⎯ ⎯ Unit ns ns Note : tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock timing”. • Trigger input timing VIH VIH VIL tTRGH tTRGL VIL INT0 to INT7 53 MB90925 Series (8) Low voltage detection (VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Parameter Detection voltage Hysteresis width Power supply voltage fluctuation ratio Detection delay time Symbol Pin name Conditions Value Min 3.7 0.1 −0.1 ⎯ Typ 4.0 ⎯ ⎯ ⎯ Max 4.3 ⎯ +0.02 35 Unit V V V/µs µs Remarks During voltage drop During voltage rise VDL VHYS dV/dt td VCC VCC VCC ⎯ ⎯ ⎯ ⎯ ⎯ Internal reset VCC dV dt Vni VHYS td td 54 MB90925 Series 5. A/D Converter (1) Electrical Characteristics (VCC = AVCC = 5.0 V±10%, 3.0V ≤ AVRH-AVss, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Parameter Resolution Total error Non-linear error Differential linear error Zero transition voltage Full scale transition voltage Sampling time Compare time Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Inter-channel variation Symbol ⎯ ⎯ ⎯ ⎯ VOT VFST tSMP tCMP IAIN VAIN AVRH IA IAH IR IRH — Pin name ⎯ ⎯ ⎯ ⎯ AN0 to AN7 AN0 to AN7 ⎯ ⎯ AN0 to AN7 AN0 to AN7 AVRH AVCC AVRH AVRH AN0 to AN7 Value Min ⎯ ⎯ ⎯ ⎯ AVSS − 1.5 LSB AVRH − 3.5 LSB 1.4 2.0 0.5 1.2 − 0.3 AVss AVss+2.7 ⎯ ⎯ ⎯ ⎯ ⎯ Typ ⎯ ⎯ ⎯ ⎯ AVSS + 0.5 LSB AVRH − 1.5 LSB ⎯ ⎯ ⎯ ⎯ ⎯ 3.5 ⎯ 600 ⎯ ⎯ Max 10 ±3.0 ±2.5 ±1.9 AVSS + 2.5 LSB AVRH + 0.5 LSB 16500 ⎯ +0.3 AVRH AVCC 7.5 5 900 5 4 Unit bit LSB LSB LSB V V µs µs µA V V mA µA µA µA LSB * VAVRH = 5.0 V * 1 LSB = (AVRH − AVSS) / 1024 4.5 V ≤ AVcc ≤ 5.5 V 4.0 V ≤ AVcc ≤ 4.5 V 4.5 V ≤ AVcc ≤ 5.5 V 4.0 V ≤ AVcc ≤ 4.5 V Remarks * : Defined as supply current (when VCC = AVCC = AVRH = 5.0 V) with A/D converter not operating, and CPU in stop mode. 55 MB90925 Series • Notes of the external impedance of the analog input and its sampling time A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. • Analog input equivalent circuit R Analog input Comparator C During sampling : ON MB90F927/MB90F927S R 4.5 V ≤ AVcc ≤ 5.5 V : 2.0 kΩ (Max) 4.0 V ≤ AVcc ≤ 4.5 V : 8.2 kΩ (Max) MB90V925-101/102 4.5 V ≤ AVcc ≤ 5.5 V : 2.0 kΩ (Max) 4.0 V ≤ AVcc ≤ 4.5 V : 8.2 kΩ (Max) Note : The values are reference values. C 16.0 pF (Max) 16.0 pF (Max) 14.4 pF (Max) 14.4 pF (Max) 56 MB90925 Series • The relationship between the external impedance and minimum sampling time • At 4.5 V ≤ AVcc ≤ 5.5 V (External impedance = 0 kΩ to 100 kΩ) 100 90 80 70 60 50 40 30 20 10 0 0 MB90V925-101/102 MB90F927/F927S (External impedance = 0 kΩ to 20 kΩ) 20 18 16 14 12 10 8 6 4 2 0 0 MB90V925-101/102 MB90F927/F927S External impedance [kΩ] 5 10 15 20 25 30 35 External impedance [kΩ] 1 2 3 4 5 6 7 8 Minimum sampling time [µs] • At 4.0 V ≤ AVcc ≤ 4.5 V (External impedance = 0 kΩ to 100 kΩ) 100 90 80 70 60 50 40 30 20 10 0 0 MB90V925-101/102 Minimum sampling time [µs] (External impedance = 0 kΩ to 20 kΩ) 20 18 16 14 12 10 8 6 4 2 0 0 1 MB90V925-101/102 MB90F927/F927S External impedance [kΩ] MB90F927/F927S External impedance [kΩ] 5 10 15 20 25 30 35 2 3 4 5 6 7 8 Minimum sampling time [µs] Minimum sampling time [µs] • About errors As |AVRH - AVSS| becomes smaller, values of relative errors grow larger. 57 MB90925 Series (2) Definition of terms Resolution : Analog changes that are identifiable with the A/D converter. Non-Linear error : The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics. Differential linear error : The deviation of input voltage needed to change the output code by 1 LSB from the ideal value. Total error : The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linear error. Total error 3FFH 3FEH 3FDH Digital output Actual conversion value 1.5 LSB {1 LSB x (N - 1) + 0.5 LSB} 004H 003H 002H 001H 0.5 LSB AVSS Analog input Actual conversion value Ideal characteristics (Measured value) VNT AVRH Total error for digital output N = 1 LSB(Ideal) = VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB AVRH − AVSS [V] 1024 [LSB] N : A/D converter digital output value VOT (Ideal) = AVss + 0.5 LSB [V] VFST (Ideal) = AVRH − 1.5 LSB [V] VNT : Voltage at a transition of digital output from (N - 1)H to NH (Continued) 58 MB90925 Series (Continued) Non-Linear error 3FFH 3FEH 3FDH Digital output Actual conversion value {1 LSB x (N -1) + VOT} Differential linear error Ideal characteristics N + 1H Actual conversion value Digital output VFST (Measured value) NH V(N + 1)T N - 1H 004H 003H 002H 001H AVss (Measured value) Actual conversion value Ideal characteristics VOT (Measured value) VNT VNT N - 2H (Measured value) (Measured value) Actual conversion value AVRH Analog input Non-Linear error of digital output N = AVss Analog input AVRH VNT − {1 LSB × (N − 1) + VOT} 1 LSB − 1 [LSB] [V] [LSB] Differential linear error V (N + 1) T − VNT = 1 LSB of digital output N 1 LSB = VFST − VOT 1022 N : A/D converter digital output value VOT : Voltage at transition of digital output from “000H” to “001H” VFST : Voltage at transition of digital output from “3FEH” to “3FFH” 6. Flash Memory Program/Erase Characteristics Parameter Chip erase time Byte (8-bit width) programming time Erase/program cycle Flash memory data retention time Conditions Value Min ⎯ ⎯ 10000 20 Typ 1 32 ⎯ ⎯ Max 15 3600 ⎯ ⎯ Unit s µs cycle year * Remarks Excludes pre-programming before erase Excludes system-level overhead TA = + 25 °C VCC = 5.0 V ⎯ Average TA = + 85 °C * : This value comes from the technology qualification. (using Arrhenius equation to translate high temperature measurements into normalized value at + 85 °C) 59 MB90925 Series ■ ORDERING INFORMATION Part number MB90F927PF-GE1 MB90F927SPF-GE1 MB90F927PFV-GE1 MB90F927SPFV-GE1 MB90V925-101 MB90V925-102 Package 100-pin plastic QFP (FPT-100P-M06) 100-pin plastic LQFP (FPT-100P-M05) 299-pin ceramic PGA (PGA-299C-A01) For evaluation Remarks 60 MB90925 Series ■ PACKAGE DIMENSIONS 100-pin plastic QFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Code (Reference) 0.65 mm 14.00 × 20.00 mm Gullwing Plastic mold 3.35 mm MAX P-QFP100-14×20-0.65 (FPT-100P-M06) 100-pin plastic QFP (FPT-100P-M06) 23.90±0.40(.941±.016) * 20.00±0.20(.787±.008) 80 51 Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 81 50 0.10(.004) 17.90±0.40 (.705±.016) *14.00±0.20 (.551±.008) INDEX Details of "A" part 100 31 1 30 0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8˚ 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.25±0.20 (.010±.008) (Stand off) 0.65(.026) 0.32±0.05 (.013±.002) 0.13(.005) M "A" C 2002 FUJITSU LIMITED F100008S-c-5-5 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html (Continued) 61 MB90925 Series (Continued) 100-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.50 mm 14.0 × 14.0 mm Gullwing Plastic mold 1.70 mm MAX 0.65g P-LFQFP100-14×14-0.50 (FPT-100P-M05) Code (Reference) 100-pin plastic LQFP (FPT-100P-M05) 16.00±0.20(.630±.008)SQ * 14.00±0.10(.551±.004)SQ 75 51 Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 76 50 0.08(.003) Details of "A" part INDEX 1.50 –0.10 .059 –.004 (Mounting height) 26 +0.20 +.008 100 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) 0˚~8˚ "A" 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 1 25 0.50(.020) 0.20±0.05 (.008±.002) 0.08(.003) M 0.145±0.055 (.0057±.0022) C 2003 FUJITSU LIMITED F100007S-c-4-6 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 62 MB90925 Series The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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