MB90F947

FUJITSU SEMICONDUCTOR DATA SHEET DS07-13741-2E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90945 Series MB90F946A/947A/F947/F947A/F949/F949A/ V390HA/V390HB ■ DESCRIPTION The MB90945 series with one FULL-CAN* interface and FLASH ROM is especially designed for automotive HVAC applications. Its main feature is the on board CAN* Interface, which conform to V2.0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal FULL-CAN* approach. With the new 0.35 µm CMOS technology, Fujitsu now offers on-chip FLASH-ROM program memory up to 384 K bytes. An internal voltage booster removes the necessity for a second programming voltage. An on board voltage regulator provides 3 V to the internal MCU core. This creates a major advantage in terms of EMI and power consumption. The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external 4 MHz clock. The unit features a 4-channel Output Compare Unit and a 6-channel Input Capture Unit with two separate 16-bit free running timers. Up to 3 UARTs, one Serial I/O and one I2C constitute additional functionality for communication purposes. * : Controller Area Network (CAN) - License of Robert Bosch GmbH ■ PACKAGE 100-pin Plastic QFP (FPT-100P-M06) MB90945 Series ■ FEATURES • • • • • • • • • • • • • • • • • • • • • • • • 16-bit core CPU; 4 MHz external clock (24 MHz internal, 42 ns instr. cycle time) New 0.35 µm CMOS Process Technology Internal voltage regulator supports 3 V MCU core, offering low EMI and low power consumption figures One FULL-CAN interface; conforming to Version 2.0 Part A and Part B, flexible message buffering (mailbox and FIFO buffering can be mixed) Powerful interrupt functions (8 progr. priority levels; 8 external interrupts) EI2OS - Automatic transfer function independant of CPU; 16 channels of intelligent I/O Services 18-bit Time-base counter Watchdog Timer 1 full duplex UART; support 10.4 KBaud (USA standard) up to 2 full duplex UARTs (LIN/SCI/SPI) 1 Serial I/O (SPI) 1 I2C interface A/D Converter : 15 channels analog inputs (Resolution 10-bit or 8-bit) 16-bit reload timer × 1channel ICU (Input capture) 16-bit × 6 channels OCU (Output compare) 16-bit × 4 channels 16-bit free running timer × 2 channels (FRT0 : ICU 0/1, OCU 0/1/2/3, FRT1 : ICU 2/3/4/5) 8/16-bit Programmable Pulse Generator 6 channels × 8/16-bit Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety of pointers) 4-byte instruction execution queue signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available Program Patch Function (3 address match registers) Fast Interrupt processing Low Power Consumption mode Sleep mode Timebase timer mode Stop mode CPU intermittent mode Automotive input levels Package : 100-pin plastic QFP • • 2 MB90945 Series ■ PRODUCT LINEUP Part Number MB90947A Parameter CPU System clock MB90F946A MB90F947, MB90F947A MB90F949, MB90F949A MB90V390HA MB90V390HB F2MC-16LX CPU On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops) Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL clock multiplied by 6) Boot-block Flash memory 256 Kbytes: MB90F949 MB90F949A 128 Kbytes: MB90F947 MB90F947A 12 Kbytes: MB90F949 MB90F949A 6 Kbytes: MB90F947 MB90F947A ROM ROM memory 128 Kbytes Boot-block Flash memory 384 Kbytes External RAM 6 Kbytes 16 Kbytes 30 Kbytes Emulator-specific power supply*1 0.35 µm CMOS with on-chip voltage regulator for internal power supply ⎯ 0.35 µm CMOS with on-chip voltage regulator for internal power supply + Flash memory with on-chip charge pump for programming voltage Yes 0.35 µm CMOS with on-chip voltage regulator for internal power supply 5 V ± 10% ⎯ PGA-299C 2 channels Technology Operating voltage range Temperature range Package 3.5 V to 5.5 V : other than conditions listed below 4.0 V to 5.5 V : when writing to Flash 4.5 V to 5.5 V : if A/D Converter is used −40 °C to +105 °C QFP-100P 1 channel UART Full duplex double buffer Supports asynchronous/synchronous (with start/stop bit) transfer Baud rate : 4808/9615/10417/19230/38460/62500/500000 bps (asynchronous) 500 K/1 M/2 Mbps (synchronous) at System clock = 20 MHz 1 channel 2 channels 1 channel 2 channels UART (LIN/SCI/SPI) Serial I/O 1 channel Transfer can be started from MSB or LSB Supports internal clock synchronized transfer and external clock synchronized transfer Supports positive-edge and negative-edge clock synchronization Baud rate : 31.25 K/62.5 K/125 K/500 K/1 Mbps at System clock = 20 MHz 1 channel (Continued) I2C (400 Kbps) 3 MB90945 Series Part Number MB90947A Parameter MB90F946A MB90F947, MB90F947A MB90F949, MB90F949A MB90V390HA MB90V390HB 10-bit or 8-bit resolution A/D Converter Conversion time : Min 4.9 µs includes sample time (per one channel, only at certain (15 input channels) machine clock frequencies) 1 channel 2 channels 16-bit Reload Timer Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = System clock frequency) Supports External Event Count function Signals an interrupt when overflowing Supports Timer Clear when a match with Output Compare (ch0) Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27 (fsys = System clock freq.) I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1, OCU 0/1/2/3 I/O Timer 1 (clock input FRCK1) corresponds to ICU 2/3/4/5 Rising edge, falling edge or rising & falling edge sensitive Six 16-bit Capture registers Signals an interrupt upon external event ⎯ 4 channels Signals an interrupt when a match with 16-bit I/O Timer Eight 16-bit compare registers. A pair of compare registers can be used to generate an output signal. ⎯ ICU 3/5 inputs are shared with OCU 6/7 outputs ICU 3/5 inputs are shared with OCU 6/7 outputs 8 channels 16-bit I/O Timer (2 channels) 16-bit Input Capture (6 channels) 16-bit Output Compare 8/16-bit Programmable Pulse Generator (6 channels) Supports 8-bit and 16-bit operation modes Twelve 8-bit reload counters Twelve 8-bit reload registers for L pulse width Twelve 8-bit reload registers for H pulse width A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 102.4 µs (fosc = 5 MHz) (fsys = System clock frequency, fosc = Oscillation clock frequency) 1 channel 5 channels Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame Prioritized 16 message buffers for data and ID’s Supports multiple messages Flexible configuration of acceptance filtering : Full-bit compare/Full-bit mask/Two partial bit masks Supports up to 1 Mbps MB90F947/F949/V390HA: Do not use clock modulation and CAN at the same time (Continued) CAN Interface 4 MB90945 Series Part Number MB90947A Parameter External Interrupt (8 channels) Stepping motor controller Watch Timer Sound generator Machine clock output Program patch function MB90F946A MB90F947, MB90F947A MB90F949, MB90F949A MB90V390HA MB90V390HB Can be programmed edge sensitive or level sensitive ⎯ ⎯ ⎯ ⎯ 3 address match registers Virtually all external pins can be used as general purpose I/O All push-pull outputs Bit-wise programmable as input/output or peripheral signal 2 channels 1 channel 1 channel 2 channels (non-inverted and inverted) 5 address match registers I/O Ports Port-wise programAutomotive input level (P21/RX1, P42/SDA, P43/SCL have CMOS mable as Automotive Schmitt input level) (default) or CMOS Schmitt input level All ports except P42, P43 All ports except P80, P81, PA0 to PA7, P42, P43 P42, P43 P80, P81, PA0 to PA7 Frequency and phase modulation mode I/O Ports with 4 mA CMOS output I/O Ports with 3 mA CMOS output I/O Ports with 30 mA CMOS output with slewrate control P42, P43 ⎯ Phase modulation mode Clock Modulator Phase modulation mode MB90F947/F949/V390HA: Do not use clock modulation and CAN at the same time Reduces EMI by modulating the PLL clock 218 oscillation cycles (65.536 ms at 4 MHz 3 × 216 oscillation cycles (49.152 ms at 4 MHz oscillation) + oscillaoscillation) + tion time of oscillator*2 oscillation time of oscillator*2 (Continued) Start-up time at power-on reset 5 MB90945 Series (Continued) Part Number MB90947A Parameter MB90F946A MB90F947, MB90F947A MB90F949, MB90F949A MB90V390HA MB90V390HB Flash Memory ⎯ Supports automatic programming, Embedded AlgorithmTM*3 Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of erase cycles : 10,000 times Data retention time : 20 years*4 Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory (address FFA000H, mode data 00H) Boot block configuration Erase can be performed on each block Block protection with external programming voltage Write and erase at Fmax = 20 MHz ⎯ *1 : It is setting of Jumper switch SI when Emulation Pod (MB2147) is used. Please refer to the Emulator hardware manual about details. *2 : Oscillation time of the oscillator is the time that the amplitude reaches 90%. *3 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc. *4 : Data is based on reliability tests during process qualification (the value for TA = + 85 °C is calculated via the Arrenhius formula from data of accelerated measurements at elevated temperature) . 6 MB90945 Series ■ PIN ASSIGNMENTS • MB90947A/F946A/F947/F947A/F949/F949A (TOP VIEW) P23/INT3 P22/INT2 P21/RX1 P20/TX1 P17 P16 P15/TOT0 X0 X1 Vss Vcc P14/TIN0 P13 P12 P11/OUT3 P10/OUT2 P07/OUT1 P06/OUT0 P05/IN5 P04/IN4 P24/INT4 P25/INT5 P26/INT6 P27/INT7 P30 P31 P32 P33 P34/SOT0 P35/SCK0 P36/SIN0 P37 P44 P45/ADTG Vcc Vss C P40 P41 P42/SDA P43/SCL P46/INT0 P47/INT1 P50/PPG10 PB0/PPG02/AN8 PB1/PPG03/AN9 PB2/PPG04/AN10 PB3/PPG05/AN11 PB4/SIN4/AN12 PB5/SCK4/AN13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB6/SOT4/AN14 AVcc AVRH AVRL AVss P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 Vss P51/PPG11 P52/PPG12 P53/PPG13 P54/PPG14 PB7/FRCK0 P97/FRCK1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P03/IN3 P02/IN2 P01/IN1 P00/IN0 P81 P80 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Vss Vcc P96 P92 P91 P94/SCK3 P95/SOT3 P93/SIN3 P90 P57/PPG01 P56/PPG00 P55/PPG15 RST MD0 MD1 MD2 (FPT-100P-M06) 7 MB90945 Series • MB90V390HA/V390HB (TOP VIEW) P23/INT3 P22/INT2 P21/RX1 P20/TX1 P17/SGA P16/SGO P15/TOT0 X0 X1 Vss Vcc P14/TIN0 P13/OUT5 P12/OUT4 P11/OUT3 P10/OUT2 P07/OUT1 P06/OUT0 P05/IN5/OUT7 P04/IN4 P24/INT4 P25/INT5 P26/INT6 P27/INT7 P30/RX0 P31/TX0 P32/TIN1 P33/TOT1 P34/SOT0 P35/SCK0 P36/SIN0 P37/SIN1 P44 P45/ADTG Vcc Vss C P40/SCK1 P41/SOT1 P42/SDA P43/SCL P46/INT0 P47/INT1 P50/PPG10 PB0/PPG02/TX3/AN8 PB1/PPG03/RX3/AN9 PB2/PPG04/TX4/AN10 PB3/PPG05/RX4/AN11 PB4/SIN4/AN12 PB5/SCK4/AN13 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 8 PB6/SOT4/AN14 AVcc AVRH AVRL AVss P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 Vss P51/PPG11 P52/PPG12 P53/PPG13 P54/PPG14 PB7/FRCK0/HCLK P97/FRCK1/HCLKX 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P03/IN3/OUT6 P02/IN2 P01/IN1 P00/IN0 P81 P80 PA7/PWM2M5 PA6/PWM2P5 PA5/PWM1M5 PA4PWM1P5 PA3/PWM2M4 PA2/PWM2P4 PA1/PWM1M4 PA0/PWM1P4 DVss DVcc P96/WOT P92/SOT2 P91/SCK2 P94/SCK3 P95/SOT3 P93/SIN3 P90/SIN2 P57/PPG01/TX2 P56/PPG00/RX2 P55/PPG15 RST MD0 MD1 MD2 (FPT-100P-M06) As seen with QFP100 probe cable MB90945 Series ■ PIN DESCRIPTION Pin no. 92 93 54 77 to 82 Pin name X1 X0 RST P00 to P05 IN0 to IN5 P06, P07 P10, P11 OUT0 to OUT3 87, 88 89 94 95, 96 97 98 99, 100 1 to 4 5 to 8 9 10 11 12 13 14 18, 19 20 P12, P13 P14 TIN0 P15 TOT0 P16, P17 P20 TX1 P21 RX1 P22 to P27 INT2 to INT7 P30 to P33 P34 SOT0 P35 SCK0 P36 SIN0 P37 P44 P45 ADTG P40, P41 P42 SDA D D D D D F D D D D D D D D D F Circuit type A B D Pin for oscillation Pin for oscillation Reset input General purpose I/O Inputs for the Input Captures 0-5 General purpose I/O Outputs for the Output Compares General purpose I/O General purpose I/O TIN0 input for the 16-bit Reload Timer 0 General purpose I/O TOT0 output for the 16-bit Reload Timer 0 General purpose I/O General purpose I/O TX output for CAN Interface 1 General purpose I/O RX input for CAN Interface 1 General purpose I/O External interrupt inputs for INT2 to INT7 General purpose I/O General purpose I/O SOT output for UART0 General purpose I/O SCK input/output for UART0 General purpose I/O SIN input for UART0 General purpose I/O General purpose I/O General purpose I/O External trigger input of the A/D Converter General purpose I/O General purpose I/O Serial data for I2C interface (Continued) Function 83 to 86 D 9 MB90945 Series Pin no. 21 22, 23 24 Pin name P43 SCL P46, P47 INT0, INT1 P50 PPG10 PB0 to PB3 PPG02 to PPG05 AN8 to AN11 PB4 Circuit type F D D General purpose I/O Function Serial clock for I2C interface General purpose I/O External interrupt inputs for INT0, INT1 General purpose I/O Output for the PPG1 General purpose I/O Outputs for the PPG4, 6, 8, A Inputs for the A/D Converter General purpose I/O 25 to 28 E 29 SIN4 AN12 PB5 E SIN input for Serial I/O Input for the A/D Converter General purpose I/O 30 SCK4 AN13 PB6 E SCK input/output for Serial I/O Input for the A/D Converter General purpose I/O 31 SOT4 AN14 P60 to P67 AN0 to AN7 P51 to P54 PPG11 to PPG14 PB7 FRCK0 P97 FRCK1 P55 PPG15 P56, P57 PPG00, PPG01 P90 E SOT output for Serial I/O Input for the A/D Converter General purpose I/O Inputs for the A/D Converter General purpose I/O Outputs for the PPG3, 5, 7, 9 General purpose I/O FRCK0 input for the 16-bit I/O Timer 0 General purpose I/O FRCK1 input for the 16-bit I/O Timer 1 General purpose I/O Outputs for the PPGB General purpose I/O Outputs for the PPG0, PPG2 General purpose I/O SIN input for UART 2 (LIN/SCI/SPI) (only MB90V390HA, MB90V390HB and MB90F946A) General purpose I/O SIN input for UART3 (LIN/SCI/SPI) (Continued) 36 to 43 45 to 48 49 50 55 56, 57 E D D D D D 58 SIN2 P93 SIN3 D 59 D 10 MB90945 Series (Continued) Pin no. 60 61 Pin name P95 SOT3 P94 SCK3 P91 Circuit type D D General purpose I/O Function SOT output for UART3 (LIN/SCI/SPI) General purpose I/O SCK input/output for UART3 (LIN/SCI/SPI) General purpose I/O SCK input/output for UART 2 (LIN/SCI/SPI) (only MB90V390HA, MB90V390HB and MB90F946A) General purpose I/O SOT output for UART 2 (LIN/SCI/SPI) (only MB90V390HA, MB90V390HB and MB90F946A) General purpose I/O General purpose I/O. For the EVA device, these pins are high current outputs. General purpose I/O. For the EVA device, these pins are high current outputs. Dedicated power supply pin (5 V) for the A/D converter Dedicated pos. reference voltage pin for the A/D converter Dedicated neg. reference voltage pin for the A/D converter Dedicated power supply pin (0 V) for the A/D converter These are input pins used to designate the operating mode. They should be connected directly to VCC or VSS. This is an input pin used to designate the operating mode. It should be connected directly to VCC or VSS. These are power supply (5 V) input pins. For the EVA device, pin 65 is the DVCC supply pin for the high current outputs. 62 SCK2 P92 D 63 64 67 to 74 75, 76 32 33 34 35 52, 53 51 15 65 90 16 44 66 91 17 SOT2 P96 PA0 to PA7 P80, P81 AVCC AVRH AVRL AVss MD1, MD0 MD2 D D H H ⎯ ⎯ ⎯ ⎯ C G ⎯ Vcc Vss ⎯ These are power supply (0 V) input pins. For the EVA device, pin 66 is the DVSS supply pin for the high current outputs. This is the power supply stabilization capacitor pin. It should be connected to higher than or equal to 0.1 µF ceramic capacitor. C ⎯ 11 MB90945 Series ■ I/O CIRCUIT TYPE Type X1 Clock input Pch Nch Circuit Remarks • Oscillation feedback resistor : 1 MΩ approx. X0 A Standby control signal VCC B R (pull-up) R CMOS Hysteresis • CMOS Hysteresis input with pull-up resistor : 50 kΩ approx. C R CMOS Hysteresis • EVA/ROM device : CMOS Hysteresis input • Flash device : CMOS input. • CMOS output (4 mA) • Automotive Hysteresis input VCC Pch D Nch Automotive Hysteresis R (Continued) 12 MB90945 Series (Continued) Type VCC Pch Circuit Remarks • CMOS output (4 mA) • Automotive Hysteresis input • Analog input Nch E Pch Analog input Nch R Automotive Hysteresis VCC Pch • CMOS output P42, P43 : 3mA P21 : 4 mA • CMOS Hysteresis input F Nch CMOS Hysteresis R R CMOS Hysteresis G R (pull-down) • EVA/ROM device : CMOS Hysteresis input with pulldown resistor : 50 kΩ approx. • Flash device : CMOS input without pull-down. VCC Pch H Nch Automotive Hysteresis • EVA/ROM device : CMOS high current output (30 mA) with slewrate control • Flash device : CMOS output (4 mA) • Automotive Hysteresis input R 13 MB90945 Series ■ HANDLING DEVICES Special care is required for the following when handling the device : • Preventing latch-up • Stabilization of supply voltage • Treatment of unused pins • Using external clock • Power supply pins (VCC/VSS) • Pull-up/pull-down resistors • Crystal Oscillator Circuit • Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs • Connection of Unused Pins of A/D Converter if A/D Converter is unused. • Caution on Operations during PLL Clock Mode 1. Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions : • A voltage higher than VCC or lower than VSS is applied to an input or output pin. • A voltage higher than the rated voltage is applied between VCC and VSS. • The AVCC power supply is applied before the VCC voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. In using the devices, take sufficient care to avoid exceeding maximum ratings. For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage. 2. Stabilization of supply voltage A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply voltage operation range. Therefore, the VCC supply voltage should be stabilized. For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak values) at commercial frequencies (50 Hz to 60 Hz) fall below 10 % of the standard VCC supply voltage and the coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching. 3. Treatment of unused pins Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 kΩ . Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. 4. Using external clock To use external clock, drive the X0 pin and leave X1 pin open. MB90945 Series X0 X1 14 MB90945 Series 5. Power supply pins (VCC/VSS) • If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected the inside of the device to prevent such malfunctioning as latch up. To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally. • Connect VCC and VSS to the device from the current supply source at a low impedance. • As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between VCC and VSS in the vicinity of VCC and VSS pins of the device. VCC VSS VCC VSS VCC MB90945 Series VSS VCC VSS VSS VCC 6. Pull-up/pull-down resistors The MB90945 series does not support internal pull-up/pull-down resistors option. Use external components where needed. 7. Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic oscillator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits while you design a printed circuit. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground area for stabilizing the operation. 8. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN14) after turning-on the digital power supply (VCC) . Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable) . 9. Connection of Unused Pins of A/D Converter if A/D Converter is unused Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS. 10. Notes on During Operation of PLL Clock Mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. 15 MB90945 Series ■ BLOCK DIAGRAMS • MB90F946A X0, X1 RST Clock Controller with Phase Modulator F2MC-16LX CPU IO Timer 0 FRCK0 RAM 16 K bytes Input Capture 6 channels Output Compare 4 channels IN5 to IN0 Flash 384 K bytes OUT3 to OUT0 Prescaler IO Timer 1 FRCK1 SOT0 SCK0 SIN0 UART0 8/16-bit PPG 6 channels PPG15 to PPG10 PPG05 to PPG00 Internal data bus Prescaler x2 CAN Interface 1 RX1 TX1 SOT2/3 SCK2/3 SIN2/3 UART2/3 (LIN/SCI/ SPI) External Interrupt INT7 to INT0 Prescaler SOT4 SCK4 SIN4 Serial I/O I2 C Interface SDA SCL AVCC AVSS AN [14:0] AVRH AVRL ADTG 10-bit A/D Converter 15 input channel 16-bit Reload Timer 1 channel TIN0 TOT0 16 MB90945 Series • MB90947A X0, X1 RST Clock Controller with Phase Modulator F2MC-16LX CPU IO Timer 0 FRCK0 RAM 6 K bytes Input Capture 6 channels Output Compare 4 channels IN5 to IN0 ROM 128 K bytes OUT3 to OUT0 Prescaler IO Timer 1 FRCK1 SOT0 SCK0 SIN0 UART0 8/16-bit PPG 6 channels PPG15 to PPG10 PPG05 to PPG00 Internal data bus Prescaler CAN Interface 1 RX1 TX1 SOT3 SCK3 SIN3 UART3 (LIN/SCI/ SPI) External Interrupt INT7 to INT0 Prescaler SOT4 SCK4 SIN4 Serial I/O I2 C Interface SDA SCL AVCC AVSS AN [14:0] AVRH AVRL ADTG 10-bit A/D Converter 15 input channel 16-bit Reload Timer 1 channel TIN0 TOT0 17 MB90945 Series • MB90F947, MB90F947A X0, X1 RST Clock Controller with Phase Modulator F2MC-16LX CPU IO Timer 0 FRCK0 RAM 6 K bytes Input Capture 6 channels Output Compare 4 channels IN5 to IN0 Flash 128 K bytes OUT3 to OUT0 Prescaler IO Timer 1 FRCK1 SOT0 SCK0 SIN0 UART0 8/16-bit PPG 6 channels PPG15 to PPG10 PPG05 to PPG00 Internal data bus Prescaler CAN Interface 1 RX1 TX1 SOT3 SCK3 SIN3 UART3 (LIN/SCI/ SPI) External Interrupt INT7 to INT0 Prescaler SOT4 SCK4 SIN4 Serial I/O I2 C Interface SDA SCL AVCC AVSS AN14 to AN0 AVRH AVRL ADTG 10-bit A/D Converter 15 input channel 16-bit Reload Timer 1 channel TIN0 TOT0 18 MB90945 Series • MB90F949, MB90F949A X0, X1 RST Clock Controller with Phase Modulator F2MC-16LX CPU IO Timer 0 FRCK0 RAM 12 K bytes Input Capture 6 channels Output Compare 4 channels IN5 to IN0 Flash 256 K bytes OUT3 to OUT0 Prescaler IO Timer 1 FRCK1 SOT0 SCK0 SIN0 UART0 8/16-bit PPG 6 channels PPG15 to PPG10 PPG05 to PPG00 Internal data bus Prescaler CAN Interface 1 RX1 TX1 SOT3 SCK3 SIN3 UART3 (LIN/SCI/ SPI) External Interrupt INT7 to INT0 Prescaler SOT4 SCK4 SIN4 Serial I/O I2C Interface SDA SCL AVCC AVSS AN14 to AN0 AVRH AVRL ADTG 10-bit A/D Converter 15 input channel 16-bit Reload Timer 1 channel TIN0 TOT0 19 MB90945 Series ■ MEMORY MAP MB90947A MB90F947 MB90F947A FFFFFFH ROM (FF bank) ROM (FE bank) ROM (FD bank) FF0000H FEFFFFH FE0000H ROM (FF bank) ROM (FE bank) FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H ROM (FB bank) ROM (FA bank) ROM (F9 bank) ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) MB90F946A FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H MB90F949 MB90F949A FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H 8017FFH 800000H MB90V390HA MB90V390HB ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) ROM (FB bank) ROM (FA bank) ROM (F9 bank) RAM 6 Kbytes 00FFFFH 008000H ROM (Image of FF bank) 00FFFFH ROM (Image of FF bank) 004000H/ 008000H 00FFFFH ROM (Image of FF bank) 004000H/ 008000H 00FFFFH 008000H 0070FFH ROM (Image of FF bank) 0050FFH 004100H 003FFFH RAM 12 Kbytes RAM 4 Kbytes 003FFFH Peripheral 003500H Peripheral 003500H 0030FFH RAM 12 Kbytes RAM 6 Kbytes Peripheral 000100H 0000BFH 000000H Peripheral 000100H 0000BFH 000000H Peripheral 003FFFH Peripheral 003500H 0030FFH RAM 12 Kbytes 004100H 003FFFH Peripheral 003500H 0030FFH RAM 12 Kbytes 000100H 0000BFH 000000H Peripheral 0018FFH 000100H 0000BFH 000000H : No access Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without using the far specification in the pointer declaration. For example, an attempt to access 00C000H accesses the value at FFC000H in ROM. The ROM area in bank FF exceeds 32/48 K bytes, and its entire image cannot be shown in bank 00. The image between FF4000H/FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF3FFFH/FF7FFFH is visible only in bank FF. 20 MB90945 Series ■ I/O MAP Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH to 1FH Port 8 direction register Port 9 direction register Port A direction register Port B direction register Port 8 data register Port 9 data register Port A data register Port B data register Analog Input Enable 0 Analog Input Enable 1/ ADC Select Input Level Select Register (MB90V390HA/MB90V390HB only) Input Level Select Register (MB90V390HA/MB90V390HB only) Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Register Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register AbbreviaAccess tion PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 Reserved PDR8 PDR9 PDRA PDRB ADER0 ADER1 ILSR ILSR DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 Reserved DDR8 DDR9 DDRA DDRB Reserved (Continued) R/W R/W R/W R/W Port 8 Port 9 Port A Port B XXXXXX00 00000000 00000000 00000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port 8 Port 9 Port A Port B Port 6, A/D Port B, A/D Ports Ports Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 11111111 01111111 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 R/W R/W R/W R/W R/W R/W R/W Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 21 MB90945 Series Address 20H 21H 22H 23H 24H to 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H Register Serial Mode Control 0 Status 0 Input/Output Data 0 Rate and Data 0 Serial Mode Control 4 Serial Mode Control 4 Serial Data 4 Serial I/O Prescaler/Edge Selector 4 External Interrupt Enable External Interrupt Request External Interrupt Level External Interrupt Level A/D Control Status 0 A/D Control Status 1 A/D Data 0 A/D Data 1 PPG0 operation mode control register PPG1 operation mode control register PPG0 and PPG1 clock select register PPG2 operation mode control register PPG3 operation mode control register PPG2 and PPG3 clock select register PPG4 operation mode control register PPG5 operation mode control register PPG4 and PPG5 clock select register PPG6 operation mode control register PPG7 operation mode control register PPG6 and PPG7 clock select register AbbreviaAccess tion UMC0 USR0 UIDR0/ UODR0 URD0 Reserved SMCS4 SMCS4 SDR4 CDCR4 ENIR EIRR ELVR ELVR ADCS0 ADCS1 ADCR0 ADCR1 PPGC0 PPGC1 PPG01 Reserved PPGC2 PPGC3 PPG23 Reserved PPGC4 PPGC5 PPG45 Reserved PPGC6 PPGC7 PPG67 Reserved R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W Resource name Initial value 00000100 00010000 UART0 XXXXXXXX 0000000X XXXX0000 Serial I/O Interface 00000010 XXXXXXXX 0 X 0 X 0000 00000000 XXXXXXXX 00000000 00000000 00000000 00000000 XXXXXXXX 000000XX 0X000XX1 0X000001 000000XX 0X000XX1 0X000001 000000XX 0X000XX1 0X000001 000000XX 0X000XX1 0X000001 000000XX (Continued) External Interrupt A/D Converter 16-bit Programable Pulse Generator 0/1 16-bit Programable Pulse Generator 2/3 16-bit Programable Pulse Generator 4/5 16-bit Programable Pulse Generator 6/7 22 MB90945 Series Address 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H to 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH to 6EH 6FH 70H to 7FH 90H to 9DH 9EH 9FH A0H A1H A2H to A7H A8H A9H AAH to ADH ROM Mirror Register PPG8 operation mode control register PPG9 operation mode control register PPG8 and PPG9 clock select register PPGA operation mode control register PPGB operation mode control register PPGA and PPGB clock select register Timer Control Status 0 Timer Control Status 0 Input Capture Control Status 0/1 Input Capture Control Status 2/3 Input Capture Control Status 4/5 Output Compare Control Status 0 Output Compare Control Status 1 Output Compare Control Status 2 Output Compare Control Status 3 AbbreviaAccess tion PPGC8 PPGC9 PPG89 Reserved PPGCA PPGCB PPGAB Reserved TMCSR0 TMCSR0 Reserved ICS01 ICS23 ICS45 Reserved OCS0 OCS1 OCS2 OCS3 Reserved ROMM Reserved Reserved W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name 16-bit Programable Pulse Generator 8/9 Initial value 0X000XX1 0X000001 000000XX 0X000XX1 0X000001 000000XX 00000000 XXXX0000 00000000 00000000 00000000 0000XX00 0XX00000 0000XX00 0XX00000 16-bit Programable Pulse Generator A/B 16-bit Reload Timer 0 Input Capture 0/1 Input Capture 2/3 Input Capture 4/5 Output Compare 0/1 Output Compare 2/3 ROM Mirror XXXXXXX1 80H to 8FH Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLER” ROM Correction Control Status 0 Delayed Interrupt/release Low-power Mode Clock Selector PACSR0 DIRR LPMCR CKSCR Reserved Watchdog Control Timebase timer Control WDTC TBTC Reserved (Continued) 23 R/W R/W Watchdog Timer Timebase timer XXXXX111 1XX00100 R/W R/W R/W R/W ROM Correction 0 Delayed Interrupt Low Power Controller Low Power Controller 00000000 XXXXXXX0 00011000 11111100 MB90945 Series AbbreviaAccess tion FMCS Reserved Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Reserved (Continued) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt controller 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 R/W Address AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H to FFH Register Flash Control Status (Flash devices only. Otherwise reserved) Resource name Flash memory Initial value 000X0000 24 MB90945 Series Address 3500H 3501H 3502H 3503H 3504H 3505H 3506H 3507H 3508H 3509H 350AH 350BH 350CH 350DH 350EH 350FH 3510H 3511H 3512H 3513H 3514H 3515H 3516H 3517H 3518H 3519H 351AH 351BH 351CH 351DH 351EH 351FH Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Register AbbreviaAccess tion PRLL0 PRLH0 PRLL1 PRLH1 PRLL2 PRLH2 PRLL3 PRLH3 PRLL4 PRLH4 PRLL5 PRLH5 PRLL6 PRLH6 PRLL7 PRLH7 PRLL8 PRLH8 PRLL9 PRLH9 PRLLA PRLHA PRLLB PRLHB SMR3 SCR3 RDR3/ TDR3 SSR3 ECCR3 ESCR3 BGR03 BGR13 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Initial value XXXXXXXX 16-bit Programable Pulse Generator 0/1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 16-bit Programable Pulse Generator 2/3 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 16-bit Programable Pulse Generator 4/5 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 16-bit Programable Pulse Generator 6/7 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 16-bit Programable Pulse Generator 8/9 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 16-bit Programable Pulse Generator A/B XXXXXXXX XXXXXXXX XXXXXXXX 00000000 00000000 00000000 Serial Mode Register Serial Control Register Reception/Transmission Data Register Serial Status Register Extended Communication Control Reg. Extended Status/Control Register Baud Rate Register 0 Baud Rate Register 1 UART3 00001000 000000XX 00000100 00000000 00000000 (Continued) 25 MB90945 Series Address 3520H 3521H 3522H 3523H 3524H 3525H 3526H 3527H 3528H 3529H 352AH 352BH 352CH 352DH 352EH 352FH 3530H 3531H 3532H 3533H 3534H 3535H 3536H 3537H 3538H to 353BH 353CH 353DH 353EH 353FH 3540H 3541H 3542H to 356DH Timer Data 1 Timer Data 1 Timer Control 1 Timer Control 1 Input Capture 0 Input Capture 0 Input Capture 1 Input Capture 1 Input Capture 2 Input Capture 2 Input Capture 3 Input Capture 3 Input Capture 4 Input Capture 4 Input Capture 5 Input Capture 5 Timer Data 0 Timer Data 0 Timer Control 0 Timer Control 0 Register AbbreviaAccess tion IPCP0 IPCP0 IPCP1 IPCP1 IPCP2 IPCP2 IPCP3 IPCP3 IPCP4 IPCP4 IPCP5 IPCP5 TCDT0 TCDT0 TCCS0 TCCS0 OCCP0 OCCP0 OCCP1 OCCP1 OCCP2 OCCP2 OCCP3 OCCP3 Reserved TCDT1 TCDT1 TCCS1 TCCS1 TMR0/ TMRLR0 TMR0/ TMRLR0 Reserved R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Initial value XXXXXXXX Input Capture 0/1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000000 00000000 00000000 0XXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Input Capture 2/3 Input Capture 4/5 I/O Timer 0 Output Compare 0 Output Compare 0 Output Compare 1 Output Compare 1 Output Compare 2 Output Compare 2 Output Compare 3 Output Compare 3 Output Compare 0/1 Output Compare 2/3 00000000 I/O Timer 1 00000000 00000000 0XXXXXXX 16-bit Reload Timer 0 XXXXXXXX XXXXXXXX Timer 0/Reload 0 Timer 0/Reload 0 (Continued) 26 MB90945 Series Address 356EH 356FH to 359FH 35A0H 35A1H 35A2H 35A3H 35A4H 35A5H 35A6H 35A7H 35A8H 35A9H to 35AAH 35ABH 35ACH to 35C8H 35C9H 35CAH 35CBH 35CCH to 35CEH 35CFH 35D0H to 35D7H 35D8H 35D9H 35DAH 35DBH 35DCH 35DDH 35DEH Register CAN Direct Mode Register AbbreviaAccess tion CDMR Reserved R/W Resource name CAN clock sync Initial value XXXXXXX0 I2C bus status register I2C bus control register I2C ten bit slave address register I2C ten bit address mask register I C seven bit slave address register I C seven bit address mask register I2C data register 2 2 IBSR IBCR ITBAL ITBAH ITMKL ITMKH ISBA ISMK IDAR Reserved R R/W R/W R/W R/W R/W R/W R/W R/W I2C Interface 00000000 00000000 00000000 00000000 11111111 00111111 00000000 01111111 00000000 I2C clock control register ICCR Reserved R/W I2C Interface 00011111 Input Capture Edge 0/1 Input Capture Edge 2/3 Input Capture Edge 4/5 ICE01 ICE23 ICE45 Reserved R/W R R/W Input Capture 0/1 Input Capture 2/3 Input Capture 4/5 XXXXX0XX XXXXXXXX XXXXX0XX PLL and Special Configuration Control Register PSCCR Reserved W PLL XXXX0000 Serial Mode Register Serial Control Register Reception/Transmission Data Register Serial Status Register Extended Communication Control Reg. Extended Status/Control Register Baud Rate Register 0 SMR2 SCR2 RDR2/ TDR2 SSR2 ECCR2 ESCR2 BGR02 R/W R/W R/W R/W R/W R/W R/W UART2 (MB90V390HA, MB90V390HB and MB90F946A only) UART2 (MB90V390HA, MB90V390HB and MB90F946A only) 00000000 00000000 00000000 00001000 000000XX 00000100 00000000 35DFH Baud Rate Register 1 BGR12 R/W 00000000 27 MB90945 Series Address 35E0H 35E1H 35E2H 35E3H 35E4H 35E5H (Continued) Address 35E6H 35E7H 35E8H 35E9H to 37FFH 3800H to 38FFH 3900H to 39FFH 3A00H to 3FFFH _ : Unused bit X : Unknown value Note : Any write access to reserved addresses in I/O map should not be performed. A read access to reserved address results in reading “X”. Register ROM Correction Address 2 ROM Correction Address 2 ROM Correction Address 2 AbbreviaAccess tion PADR2 PADR2 PADR2 Reserved Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLER” Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLER” Reserved R/W R/W R/W Resource name Initial value Register ROM Correction Address 0 ROM Correction Address 0 ROM Correction Address 0 ROM Correction Address 1 ROM Correction Address 1 ROM Correction Address 1 AbbreviaAccess tion PADR0 PADR0 PADR0 PADR1 PADR1 PADR1 R/W R/W R/W R/W R/W R/W Resource name Initial value XXXXXXXX XXXXXXXX Address Matching XXXXXXXX Detection Function 0 XXXXXXXX XXXXXXXX XXXXXXXX (Continued) XXXXXXXX Address Matching XXXXXXXX Detection Function 0 XXXXXXXX 28 MB90945 Series ■ CAN CONTROLLER The CAN controller has the following features : • Conforms to CAN Specification Version 2.0 Part A and B - Supports transmission/reception in standard frame and extended frame formats • Supports transmitting of data frames by receiving remote frames • 16 transmitting/receiving message buffers - 29-bit ID and 8-byte data - Multi-level message buffer configuration • Provides full-bit comparison, full-bit mask, acceptance mask register 0/acceptance mask register 1 for each message buffer as ID acceptance mask - Two acceptance mask registers in either standard frame format or extended frame formats • Bit rate programmable from 10 Kbps to 2 Mbps (when input clock is at 16 MHz) List of Control Registers (1) Address CAN1 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH Register Message buffer valid register Transmit request register Transmit cancel register Transmit complete register Receive complete register Remote request receiving register Receive overrun register Receive interrupt enable register Abbreviation BVALR TREQR TCANR TCR RCR RRTRR ROVRR RIER Access R/W R/W W R/W R/W R/W R/W R/W Initial Value 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 29 MB90945 Series List of Control Registers (2) Address CAN1 003900H 003901H 003902H 003903H 003904H 003905H 003906H 003907H 003908H 003909H 00390AH 00390BH 00390CH 00390DH 00390EH 00390FH 003910H 003911H 003912H 003913H 003914H 003915H 003916H 003917H 003918H 003919H 00391AH 00391BH Acceptance mask register 1 AMR1 R/W XXXXXXXX XXXXXXXX Acceptance mask register 0 AMR0 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Acceptance mask select register AMSR R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Register Control status register Last event indicator register Receive/transmit error counter Bit timing register IDE register Transmit RTR register Remote frame receive waiting register Transmit interrupt enable register Abbreviation CSR LEIR RTEC BTR IDER TRTRR Access R/W, R R/W R R/W R/W R/W Initial Value 00XXX000 0XXXX0X1 XXXXXXXX 000X0000 00000000 00000000 X1111111 11111111 XXXXXXXX XXXXXXXX 00000000 00000000 XXXXXXXX XXXXXXXX 00000000 00000000 XXXXXXXX XXXXXXXX RFWTR R/W TIER R/W 30 MB90945 Series List of Message Buffers (ID Registers) (1) Address CAN1 003800H to 00381FH 003820H 003821H 003822H 003823H 003824H 003825H 003826H 003827H 003828H 003829H 00382AH 00382BH 00382CH 00382DH 00382EH 00382FH 003830H 003831H 003832H 003833H 003834H 003835H 003836H 003837H 003838H 003839H 00383AH 00383BH 00383CH 00383DH 00383EH 00383FH ID register 7 IDR7 R/W XXXXXXXX XXXXXXXX 31 ID register 6 IDR6 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 5 IDR5 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 4 IDR4 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 3 IDR3 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 2 IDR2 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 1 IDR1 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 0 IDR0 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Register Generalpurpose RAM Abbreviation Access Initial Value XXXXXXXX to XXXXXXXX XXXXXXXX XXXXXXXX ⎯ R/W MB90945 Series List of Message Buffers (ID Registers) (2) Address CAN1 003840H 003841H 003842H 003843H 003844H 003845H 003846H 003847H 003848H 003849H 00384AH 00384BH 00384CH 00384DH 00384EH 00384FH 003850H 003851H 003852H 003853H 003854H 003855H 003856H 003857H 003858H 003859H 00385AH 00385BH 00385CH 00385DH 00385EH 00385FH ID register 15 IDR15 R/W XXXXXXXX XXXXXXXX ID register 14 IDR14 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 13 IDR13 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 12 IDR12 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 11 IDR11 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 10 IDR10 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 9 IDR9 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 8 IDR8 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Register Abbreviation Access Initial Value XXXXXXXX XXXXXXXX 32 MB90945 Series List of Message Buffers (DLC Registers and Data Registers) (1) Address CAN1 003860H 003861H 003862H 003863H 003864H 003865H 003866H 003867H 003868H 003869H 00386AH 00386BH 00386CH 00386DH 00386EH 00386FH 003870H 003871H 003872H 003873H 003874H 003875H 003876H 003877H 003878H 003879H 00387AH 00387BH 00387CH 00387DH 00387EH 00387FH Register DLC register 0 DLC register 1 DLC register 2 DLC register 3 DLC register 4 DLC register 5 DLC register 6 DLC register 7 DLC register 8 DLC register 9 DLC register 10 DLC register 11 DLC register 12 DLC register 13 DLC register 14 DLC register 15 Abbreviation DLCR0 DLCR1 DLCR2 DLCR3 DLCR4 DLCR5 DLCR6 DLCR7 DLCR8 DLCR9 DLCR10 DLCR11 DLCR12 DLCR13 DLCR14 DLCR15 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 33 MB90945 Series List of Message Buffers (DLC Registers and Data Registers) (2) Address CAN1 003880H to 003887H 003888H to 00388FH 003890H to 003897H 003898H to 00389FH 0038A0H to 0038A7H 0038A8H to 0038AFH 0038B0H to 0038B7H 0038B8H to 0038BFH 0038C0H to 0038C7H 0038C8H to 0038CFH 0038D0H to 0038D7H 0038D8H to 0038DFH 0038E0H to 0038E7H 0038E8H to 0038EFH Register Abbreviation Access Initial Value XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX Data register 0 (8 bytes) DTR0 R/W Data register 1 (8 bytes) DTR1 R/W Data register 2 (8 bytes) DTR2 R/W Data register 3 (8 bytes) DTR3 R/W Data register 4 (8 bytes) DTR4 R/W Data register 5 (8 bytes) DTR5 R/W Data register 6 (8 bytes) DTR6 R/W Data register 7 (8 bytes) DTR7 R/W Data register 8 (8 bytes) DTR8 R/W Data register 9 (8 bytes) DTR9 R/W Data register 10 (8 bytes) DTR10 R/W Data register 11 (8 bytes) DTR11 R/W Data register 12 (8 bytes) DTR12 R/W Data register 13 (8 bytes) DTR13 R/W 34 MB90945 Series List of Message Buffers (DLC Registers and Data Registers) (3) Address CAN1 0038F0H to 0038F7H 0038F8H to 0038FFH Register Abbreviation Access Initial Value XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX Data register 14 (8 bytes) DTR14 R/W Data register 15 (8 bytes) DTR15 R/W 35 MB90945 Series ■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER Interrupt cause Reset INT9 instruction Exception Timebase timer External Interrupt INT0 to INT7 Reserved Reserved CAN 1 RX CAN 1 TX/NS PPG 0/1 PPG 2/3 PPG 4/5 PPG 6/7 PPG 8/9 PPG A/B 16-bit Reload Timer 0 Reserved Input Capture 0/1 Output compare 0/1 Input Capture 2/3 Output Compare 2/3 Input Capture 4/5 IC A/D Converter I/O Timer 0 / I/O Timer 1 Serial I/O Reserved UART 0 RX UART 0 TX Reserved Reserved N/A 2 EI2OS clear N/A N/A N/A N/A Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H Interrupt control register Number ⎯ ⎯ ⎯ ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 Address ⎯ ⎯ ⎯ 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH (Continued) N/A N/A N/A N/A N/A N/A N/A N/A #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 36 MB90945 Series (Continued) Interrupt cause UART 2 RX / UART 3 RX UART 2 TX / UART 3 TX Flash memory Delayed interrupt N/A N/A EI2OS clear Interrupt vector Number #39 #40 #41 #42 Address FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt control register Number ICR14 ICR15 Address 0000BEH 0000BFH : The interrupt request flag is cleared by the EI2OS interrupt clear signal. : The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available. : Unavailable N/A : The interrupt request flag is not cleared by the EI2OS interrupt clear signal. Notes : • For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags are cleared by the EI2OS interrupt clear signal. • At the end of EI2OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same interrupt number. If one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by hardware event, the later event is lost because the flag is cleared by the EI2OS clear signal caused by the first event. So it is recommended not to use the EI2OS for this interrupt number. • If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control register (ICR) is asserted. This means that different interrupt sources share the same EI2OS Descriptor which should be unique for each interrupt source. For this reason, when one interrupt source uses the EI2OS, the other interrupt should be disabled. 37 MB90945 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol VCC Power supply voltage*1 AVCC AVRH, AVRL Input voltage*1 Output voltage* 1 Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 −4.0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 +4.0 40 15 4 100 50 −15 −4 −100 −50 500 525 +105 +150 Unit V V V V V mA mA mA mA mA mA mA mA mA mA Remarks VCC = AVCC *2 AVCC ≥ AVRH, AVCC ≥ AVRL, AVRH ≥ AVRL *3 *3 *5 *5 *4 *4 *4 *4 *4 *4 *4 *4 VI VO ICLAMP Σ|ICLAMP| IOL1 IOLAV1 ΣIOL1 ΣIOLAV1 IOH1 IOHAV1 ΣIOH1 ΣIOHAV PD TA TSTG Maximum Clamp Current Total Maximum Clamp Current “L” level maximum output current “L” level average output current “L” level maximum overall output current “L” level average overall output current “H” level maximum output current “H” level average output current “H” level maximum overall output current “H” level average overall output current Power consumption Operating temperature Storage temperature MB90947A/F947/F947A/F949/ mW F949A MB90F946A °C °C −40 −55 *1 : This parameter is based on VSS = AVSS = 0 V. *2 : Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on. *3 : VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximum current to/from a input is limited by some means with external components, the ICLAMP rating supercedes the VI rating. *4 : Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P80, P81, P90 to P97, PA0 to PA7, PB0 to PB7 *5 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P80, P81, P90 to P97, PA0 to PA7, PB0 to PB7 • Use within recommended operating conditions. • Use at DC voltage (current) • The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. 38 MB90945 Series • Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. • Care must be taken not to leave the +B input pin open. • Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. • Sample recommended circuits : • Input/output equivalent circuits Protective diode Limiting resistance +B input (0 V to 16 V) Nch VCC Pch R WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 39 MB90945 Series 2. Recommended Conditions (VSS = AVSS = 0 V) Parameter Symbol Value Min 3.5 Power supply voltage VCC, AVCC 4.0 4.5 2.0 Smoothing capacitor Operating temperature CS TA 0.1 −40 Typ 5.0 5.0 5.0 ⎯ ⎯ ⎯ Max 5.5 5.5 5.5 5.5 1.0 +105 Unit Remarks Other than when writing to Flash memory and when using the A/D converter When writing to Flash memory When using the A/D converter Retain RAM data in stop mode * V V V V µF °C * : Use a ceramic capacitor, or a capacitor of similar frequency characteristics. On the VCC pin, use a bypass capacitor that has a larger capacity than that of CS. Refer to the following figure for connection of smoothing capacitor CS. • C Pin Connection Diagram C CS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 40 MB90945 Series 3. DC Characteristics (TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V) Parameter Symbol VIHA Pin ⎯ Condition ⎯ Value Min 0.8 VCC Typ ⎯ Max VCC + 0.3 Unit Remarks Port inputs except ports P21/RX1, P42/SDA, P43/SCL Port inputs P21/ RX1, P42/SDA, P43/SCL RST input pin (CMOS Hysteresis) MD input pin Port inputs except ports P21/RX1, P42/SDA, P43/SCL Port inputs P21/ RX1, P42/SDA, P43/SCL RST input pin (CMOS Hysteresis) MD input pin V Input “H” voltage VIHS VIHR VIHM VILA ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.7 VCC 0.8 VCC VCC − 0.3 VSS − 0.3 ⎯ ⎯ ⎯ ⎯ VCC + 0.3 VCC + 0.3 VCC + 0.3 0.5 VCC V V V V Input “L” voltage VILS VILR VILM ⎯ ⎯ ⎯ Normal outputs I2C outputs Normal outputs I2C outputs ⎯ ⎯ ⎯ ⎯ VCC = 4.5 V, IOH1 = −4.0 mA VCC = 4.5 V, IOH1 = −3.0 mA VCC = 4.5 V, IOL1 = 4.0 mA VCC = 4.5 V, IOL1 = 3.0 mA VCC = 5.5 V, VSS < VI < VCC VSS − 0.3 VSS − 0.3 VSS − 0.3 VCC − 0.5 VCC − 0.5 ⎯ ⎯ −1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.3 VCC 0.2 VCC VSS + 0.3 ⎯ ⎯ 0.4 0.4 1 V V V V V V V µA Output “H” voltage Output “H” voltage Output “L” voltage Output “L” voltage Input leak current VOH VOHI VOL VOLI IIL (Continued) 41 MB90945 Series (Continued) Symbol RDOWN (TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V) Pin MD2 Condition ⎯ VCC = 5.0 V, Internal frequency : 24 MHz, At normal operation. VCC = 5.0 V, Internal frequency : 20 MHz, At normal operation. VCC = 5.0 V, Internal frequency : 20 MHz, At writing FLASH memory. VCC = 5.0 V, Internal frequency : 20 MHz, At erasing FLASH memory. VCC ICCS VCC = 5.0 V, Internal frequency : 24 MHz, At Sleep mode. VCC = 5.0 V, Internal frequency : 2 MHz, At Main Timebase timer mode VCC = 5.0 V, Internal frequency : 24 MHz, At PLL Timebase timer mode, external frequency = 4 MHz Parameter Pull-down resistance Value Min 25 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Typ 50 Max 100 Unit kOhm Remarks only ROM devices MB90947A MB90F947/A MB90F949/A MB90F946A MB90947A MB90F947/A MB90F949/A MB90F946A MB90F947/A MB90F949/A MB90F946A MB90F947/A MB90F949/A MB90F946A MB90947A MB90F947/A MB90F949/A MB90F946A MB90947A MB90F946A MB90F947/A MB90F949/A MB90947A MB90F946A MB90F947/A MB90F949/A MB90947A MB90F946A MB90F947/A MB90F949/A 60 65 50 55 65 70 70 75 25 28 75 85 65 75 80 90 85 95 35 40 mA mA mA mA mA mA mA mA mA mA ICC Power supply current* ICTS 0.3 0.6 mA ICTSPLL6 ⎯ 5 7 mA ICCH VCC = 5.0 V, At Stop mode, TA = +25°C Other than C, AVCC, AVSS, AVRH, AVRL, VCC, VSS ⎯ 5 100 µA Input capacity CIN ⎯ ⎯ 5 15 pF * : The power supply current is measured with an external clock. 42 MB90945 Series 4. AC Characteristics (1) Clock Timing Value Parameter Symbol Pin Min 3 4 X0, X1 4 4 4 Clock frequency fC 4 3 4 X0 4 4 4 4 Clock cycle time Input clock pulse width Input clock rise and fall time Machine clock frequency Machine clock cycle time tCYL PWH, PWL tCR, tCF X0, X1 125 Typ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Max CS2 = 0 CS2 = 1 8 8 8 6.67 5 ⎯ 12 12 10 6.67 5 ⎯ 333 333 ⎯ 5 24 20 666 666 8 ⎯ 8 ⎯ 6 4 12 ⎯ 12 ⎯ 6 4 MHz × 1/2 (When PLL stops) When using an oscillation circuit Unit Remarks (TA = −40 °C to +105 °C, VCC = 3.5V to 5.5 V, VSS = AVSS = 0 V) MHz PLL × 1 When using an oscillation circuit MHz PLL × 2 When using an oscillation circuit MHz PLL × 3 When using an oscillation circuit MHz PLL × 4 When using an oscillation circuit MHz PLL × 6 When using an oscillation circuit MHz × 1/2 (When PLL stops) When using an external circuit MHz PLL × 1 When using an external circuit MHz PLL × 2 When using an external circuit MHz PLL × 3 When using an external circuit MHz PLL × 4 When using an external circuit MHz PLL × 6 When using an external circuit ns ns ns ns When using an oscillation circuit When using an external clock Duty ratio is about 30% to 70%. When using external clock X0, X1 83.33 ⎯ X0 X0 ⎯ 20 ⎯ 1.5 1.5 MHz Except programming or erasing Flash memory. When programming or erasing Flash memory. MHz Be sure that the maximum momentary frequency Fmax does not exceed 20MHz. ns ns Except programming or erasing Flash memory. When programming or erasing Flash memory. fCP ⎯ ⎯ ⎯ tCP 41.67 ⎯ 50 ⎯ • Clock Timing tCYL X0 PWH tCF PWL tCR 0.8 VCC 0.2 VCC 43 MB90945 Series • Guaranteed PLL operation range Guaranteed operation range Guaranteed PLL operation range (CS2=1) 5.5 Power supply voltage VCC (V) 4.5 3.5 Guaranteed PLL operation range (CS2=0) Guaranteed A/D converter operation range 1.5 4 8 Machine clock fCP (MHz) 20 24 Guaranteed operation range of MB90F947/MB90F949 • CS2 (bit 0 in PSCCR register) = 0 Guaranteed oscilation frequency range Machine clock fCP (MHz) 20 16 12 8 6 4 1.5 3 4 6 8 10 ×1*1 (CS=000) ×4 (CS=011) ×3 (CS=010) ×2 (CS=001) ×1/2 (PLL off) 12 External clock fC (MHz)*2 • CS2 (bit 0 in PSCCR register) = 1 Guaranteed oscilation frequency range ×6 (CS=110) ×4 (CS=101) 24 Machine clock fCP (MHz) ×2 (CS=100) 16 8 6 1.5 3 4 6 8 10 ×1/2 (PLL off) 12 External clock fC (MHz)*2 *1 : PLL × 1 guaranteed operation range is from 4.0 MHz to 12 MHz. *2 : When using a crystal oscillator or a ceramic oscillator, the maximum oscillation clock frequency is 8 MHz External clock frequency and Machine clock frequency 44 MB90945 Series (2) Reset Standby Input (TA = −40 °C to +105 °C, VCC = 3.5V to 5.5 V, VSS = AVSS = 0.0 V) Parameter Symbol Pin Value Min 16 tCP*1 Reset input time tRSTL RST Oscillation time of oscillator*2 + 100 + 16 tCP*1 100 Max ⎯ ⎯ ⎯ Unit ns µs µs Remarks Under normal operation In Stop mode In Timebase timer mode *1 : “tCP” represents one cycle time of the machine clock. No reset can fully initialize the Flash memory if it is performing the automatic algorithm. *2 : Oscillation time of oscillator is the time that the amplitude reaches 90%. In the crystal oscillator, the oscillation time is between several ms and to tens of ms. In FAR / ceramic oscillators, the oscillation time is between hundreds of µs to several ms. With an external clock, the oscillation time is 0 ms. Under normal operation : tRSTL RST 0.2 VCC 0.2 VCC In Stop mode : tRSTL RST 0.2 VCC 90% of amplitude 0.2 VCC X0 Internal operation clock Oscillation time of oscillator +100 µs 16 tCP Oscillation stabilization waiting time Instruction execution Internal reset 45 MB90945 Series (3) Power On Reset (TA = −40 °C to +105 °C, VCC = 3.5V to 5.5 V, VSS = AVSS = 0.0 V) Parameter Power on rise time Power off time Symbol tR tOFF Pin VCC VCC Condition ⎯ Value Min 0.05 1 Max 30 ⎯ Unit ms ms Due to repetitive operation Remarks tR 2.7 V 0.2 V 0.2 V tOFF If you change the power supply voltage too rapidly, a power on reset may occur. We recommend that you startup smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within 1 V/s, you can operate while using the PLL clock. 0.2 V VCC VCC 3V VSS Holds RAM data We recommend a rise of 50 mV/ms maximum. 46 MB90945 Series (4) UART0, SIO Timing (TA = −40 °C to +105 °C, VCC = 3.5V to 5.5 V, VSS = AVSS = 0.0 V) Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → Valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → Valid SIN hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin SCK0, SCK4 SCK0, SCK4, SOT0, SOT4 SCK0, SCK4, SIN0, SIN4 SCK0, SCK4, SIN0, SIN4 SCK0, SCK4 SCK0, SCK4 SCK0, SCK4, SOT0, SOT4 SCK0, SCK4, SIN0, SIN4 SCK0, SCK4, SIN0, SIN4 External clock operation output pins are CL = 80 pF + 1 TTL. Internal clock operation output pins are CL = 80 pF + 1 TTL. Condition Value Min 8 tCP −80 100 60 4 tCP 4 tCP ⎯ 60 60 Max ⎯ +80 ⎯ ⎯ ⎯ ⎯ 150 ⎯ ⎯ Unit ns ns ns ns ns ns ns ns ns Remarks Notes : • AC characteristics in CLK synchronized mode. • CL is load capacity value of pins when testing. • tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for tCP . 47 MB90945 Series • Internal Shift Clock Mode tSCYC SCK 2.4 V 0.8 V tSLOV 0.8 V SOT 2.4 V 0.8 V tIVSH tSHIX VIH VIL SIN VIH VIL • External Shift Clock Mode tSLSH tSHSL VIH VIL tSLOV VIL VIH SCK SOT 2.4 V 0.8 V tIVSH tSHIX VIH VIL SIN VIH VIL 48 MB90945 Series (5) UART2/3 Timing • Bit setting : ESCR : SCES = 0, ECCR : SCDE = 0 (TA = −40 °C to +105 °C, VCC = 3.5V to 5.5 V, VSS = AVSS = 0V) Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → Valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → Valid SIN hold time SCK fall time SCK rise time Symbol tSCYC tSLOVI tIVSHI tSHIXI tSHSL tSLSH tSLOVE tIVSHE tSHIXE tF tR Pin SCK2,SCK3 Condition Value Min 5 tCP Max ⎯ +50 ⎯ ⎯ ⎯ ⎯ 2 tCP + 60 ⎯ ⎯ 10 10 Unit Remarks ns ns ns ns ns ns ns ns ns ns ns SCK2,SCK3 −50 SOT2,SOT3 Internal clock operation output SCK2,SCK3 pins are tCP + 80 SIN2,SIN3 CL = 80 pF + 1 TTL. SCK2,SCK3 0 SIN2,SIN3 SCK2,SCK3 SCK2,SCK3 SCK2,SCK3 SOT2,SOT3 External clock SCK2,SCK3 operation output SIN2,SIN3 pins are SCK2,SCK3 CL = 80 pF + 1 TTL. SIN2,SIN3 SCK2,SCK3 SCK2,SCK3 tCP + 10 3 tCP − tR ⎯ 30 tCP + 30 ⎯ ⎯ . Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for tCP • Internal Shift Clock Mode tSCYC SCK 2.4 V 0.8 V tSLOVI 0.8 V SOT 2.4 V 0.8 V tIVSHI tSHIXI VIH VIL SIN VIH VIL 49 MB90945 Series • External Shift Clock Mode tSLSH tSHSL VIH VIL tF tSLOVE 2.4 V 0.8 V tIVSHE tSHIXE VIH VIL VIL tR VIH SCK SOT SIN VIH VIL • Bit setting : ESCR : SCES = 1, ECCR : SCDE = 0 (TA = −40 °C to +105 °C, VCC = 3.5V to 5.5V, VSS = AVSS = 0V) Parameter Serial clock cycle time SCK ↑ → SOT delay time Valid SIN → SCK ↓ SCK ↓ → Valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↑ → SOT delay time Valid SIN → SCK ↓ SCK ↓ → Valid SIN hold time SCK fall time SCK rise time Symbol tSCYC tSHOVI tIVSLI tSLIXI tSHSL tSLSH tSHOVE tIVSLE tSLIXE tF tR Pin SCK2,SCK3 Condition Value Min 5 tCP Max ⎯ +50 ⎯ ⎯ ⎯ ⎯ Unit Remarks ns ns ns ns ns ns ns ns ns ns ns SCK2,SCK3 −50 SOT2,SOT3 Internal clock operation output SCK2,SCK3 pins are tCP + 80 SIN2,SIN3 CL = 80 pF + 1 TTL. SCK2,SCK3 0 SIN2,SIN3 SCK2,SCK3 SCK2,SCK3 SCK2,SCK3 SOT2,SOT3 3 tCP − tR tCP + 10 ⎯ 2 tCP + 60 External clock SCK2,SCK3 operation output 30 ⎯ SIN2,SIN3 pins are C SCK2,SCK3 L = 80 pF + 1 TTL. tCP + 30 ⎯ SIN2,SIN3 SCK2,SCK3 SCK2,SCK3 ⎯ ⎯ 10 10 Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for tCP . 50 MB90945 Series • Internal Shift Clock Mode tSCYC SCK 2.4 V 0.8 V tSHOVI SOT 2.4 V 0.8 V tIVSLI tSLIXI VIH VIL SIN VIH VIL • External Shift Clock Mode tSHSL tSLSH VIH VIL tR tSHOVE 2.4 V 0.8 V tIVSLE tSLIXE VIH VIL tF VIL SCK VIH SOT SIN VIH VIL 51 MB90945 Series • Bit setting : ESCR : SCES = 0, ECCR : SCDE = 1 (TA = −40 °C to +105 °C, VCC = 3.5V to 5.5V, VSS = AVSS = 0V) Parameter Serial clock cycle time SCK ↑ → SOT delay time Valid SIN → SCK ↓ SCK ↓ → Valid SIN hold time SOT → SCK ↓ delay time Symbol tSCYC tSHOVI tIVSLI tSLIXI tSOVLI Pin SCK2,SCK3 SCK2,SCK3 SOT2,SOT3 Condition Value Min 5 tCP −50 Max ⎯ +50 ⎯ ⎯ ⎯ Unit ns ns ns ns ns Remarks Internal clock SCK2,SCK3 tCP + 80 operation output SIN2,SIN3 pins are SCK2,SCK3 CL = 80 pF + 1 TTL. 0 SIN2,SIN3 SCK2,SCK3 SOT2,SOT3 3 tCP − 70 . Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for tCP tSCYC SCK tSOVLI 2.4 V 0.8 V tSHOVI 2.4 V 0.8 V tIVSLI tSLIXI VIH VIL 0.8 V SOT 2.4 V 0.8 V SIN VIH VIL 52 MB90945 Series • Bit setting : ESCR : SCES = 1, ECCR : SCDE = 1 (TA = −40 °C to +105 °C, VCC = 3.5V to 5.5V, VSS = AVSS = 0V) Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → Valid SIN hold time SOT → SCK ↑ delay time Symbol tSCYC tSLOVI tIVSHI tSHIXI tSOVHI Pin SCK2,SCK3 SCK2,SCK3 SOT2,SOT3 Condition Value Min 5 tCP −50 Max ⎯ +50 ⎯ ⎯ ⎯ Unit ns ns ns ns ns Remarks Internal clock SCK2,SCK3 tCP + 80 operation output SIN2,SIN3 pins are SCK2,SCK3 CL = 80 pF + 1 TTL. 0 SIN2,SIN3 SCK2,SCK3 SOT2,SOT3 3 tCP − 70 . Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for tCP tSCYC SCK tSOVHI 2.4 V 0.8 V tSLOVI 2.4 V SOT 2.4 V 0.8 V tIVSHI tSHIXI 2.4 V 0.8 V SIN VIH VIL VIH VIL 53 MB90945 Series (6) Trigger Input Timing (TA = −40 °C to +105 °C, VCC = 3.5V to 5.5V, VSS = AVSS = 0.0 V) Parameter Input pulse width Symbol tTRGH tTRGL Pin INT0 to INT7 ADTG Condition ⎯ Value Min 200 tCP + 200 Max ⎯ ⎯ Unit ns ns Remarks Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for tCP . • Trigger Input Timing VIH VIH VIL tTRGH tTRGL VIL (7) Timer Related Resource Input Timing (TA = −40 °C to +105 °C, VCC = 3.5V to 5.5V, VSS = AVSS = 0.0 V) Parameter Input pulse width Symbol tTIWH tTIWL Pin TIN0, IN0 to IN5 Condition ⎯ Value Min 4 tCP Max ⎯ Unit ns Remarks Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for tCP . • Timer Input Timing VIH VIH VIL tTIWH tTIWL VIL 54 MB90945 Series (8) I2C Timing (TA = −40 °C to +105 °C, VCC = 3.5V to 5.5V, VSS = AVSS = 0.0 V) Standard-mode Fast-mode*4 Unit Symbol Condition Min Max Min Max fSCL tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tSUSTO tBUS R = 1.3 kΩ, C = 50 pF*1 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 100 ⎯ ⎯ ⎯ ⎯ 3.45*2 ⎯ ⎯ ⎯ 0 0.6 1.3 0.6 0.6 0 100 0.6 1.3 400 ⎯ ⎯ ⎯ ⎯ 0.9*3 ⎯ ⎯ ⎯ kHz µs µs µs µs µs ns µs µs Parameter SCL clock frequency Hold time (repeated) START condition SDA ↓ → SCL ↓ “L” width of SCL clock “H” width of SCL clock Set-up time for a repeated START condition SCL ↑ → SDA ↓ Data hold time SCL ↑ → SDA ↓↑ Data set-up time SDA ↓↑ → SCL ↑ Set-up time for STOP condition SCL ↑ → SDA ↑ Bus free time between STOP and START condition *1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : The maximum tHDDAT only has to be met if the devie does not stretch the “L” width (tLOW) of the SCL signal. *3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSUDAT ≥ 250 ns must then be met. *4 : For use at over 100 kHz, set the machine clock to at least 6 MHz. • I2C Timing SDA tBUS tLOW tSUDAT tHDSTA SCL tHDSTA tHDDAT tHIGH tSUSTA tSUSTO 55 MB90945 Series 5. A/D Converter (TA = −40 °C to +105 °C, 3.0 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V ± 10%, VSS = AVSS = 0 V) Parameter Resolution Total error Nonlinearity error Differential nonlinearity error Zero reading voltage Full scale reading voltage Compare time Sampling time Analog port input current Analog input voltage range Reference voltage range Power supply current Reference voltage current Offset between input channels Symbol ⎯ ⎯ ⎯ ⎯ VOT VFST ⎯ ⎯ IAIN VAIN ⎯ IA IAH IR IRH ⎯ Pin ⎯ ⎯ ⎯ ⎯ Value Min ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Typ Max 10 ±3.0 ±2.5 ±1.9 Unit bit LSB LSB LSB Remarks AN0 to AN14 AVRL − 1.5 AVRL + 0.5 AVRL + 2.5 LSB AN0 to AN14 AVRH − 3.5 AVRH − 1.5 AVRH + 0.5 LSB ⎯ ⎯ AN0 to AN14 AN0 to AN14 AVRH AVRL AVCC AVCC AVRH AVRH AN0 to AN14 3.3 1.6 −0.3 AVRL AVRL + 2.7 0 ⎯ ⎯ ⎯ ⎯ ⎯ 66 tCP 32 tCP ⎯ ⎯ ⎯ ⎯ 3.5 ⎯ 165 ⎯ ⎯ 16500 ∞ +0.3 AVRH AVCC AVRH − 2.7 7.5 5 250 5 4 µs µs µA V V V mA µA * µA µA * LSB * : When not operating A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) . Terminology Conversion error : Absolute maximum conversion deviation with respect to the theoretical conversion line. Nonlinearity : Relative maximum conversion deviation with respect to the theoretical conversion line conncecting to the device unigque zero reading voltage and full scale reading voltage. Differential nonlinearity : Max conversion deviation in any two adjacent reading voltages with respect to the theoretical LSB conversion step. Zero reading voltage : Input voltage which results in the minimum conversion value. Full scale reading voltage : Input voltage which results in the maximum conversion value. Notes : • tCP is the machine clock cycle time (Unit : ns) . Refer to “4. AC Characteristics (1) Clock timing” rating . for tCP • The accuracy gets worse as |AVRH − AVRL| becomes smaller. 56 MB90945 Series 6. Definition of A/D Converter Terms Resolution Linear error : Analog variation that is recognized by an A/D converter. : Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” ) and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion characteristics. : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. : Difference between an actual value and an ideal value. A total error includes zero transition error, full-scale transition error, and linear error. Differential linear error Total error Total error 3FFH 3FEH 3FDH Digital output {1 LSB × (N − 1) + 0.5 LSB} Actual conversion characteristics 1.5 LSB 004H 003H 002H 001H 0.5 LSB AVRL Analog input VNT (Actually-measured value) Actual conversion characteristics Ideal characteristics AVRH VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB AVRH − AVRL 1 LSB (Ideal value) = [V] 1024 VOT (Ideal value) = AVRL + 0.5 LSB [V] Total error of digital output “N” = VFST (Ideal value) = AVRH − 1.5 LSB [V] VNT : A voltage at which digital output transitions from (N − 1) to N. [LSB] (Continued) 57 MB90945 Series (Continued) Linear error 3FFH 3FEH 3FDH Digital output Actual conversion characteristics {1 LSB × (N − 1) + VOT } N+1 VFST (actual measurement value) VNT (actual measurement value) Actual conversion characteristics Actual conversion characteristics Differential linear error Ideal characteristics Digital output N 004H 003H 002H N−1 V (N + 1) T (actual measurement value) VNT (actual measurement value) Actual conversion characteristics AVRH Analog input Ideal characteristics 001H VOT (actual measurement value) AVRL Analog input AVRH N−2 AVRL Linear error of digital output N = Differential linear error of digital output N = 1 LSB = VNT − {1 LSB × (N − 1) + VOT} 1 LSB V (N+1) T − VNT 1 LSB VFST − VOT 1022 −1 LSB [LSB] [V] [LSB] VOT : Voltage at which digital output transits from “000H” to “001H.” VFST : Voltage at which digital output transits from “3FEH” to “3FFH.” 58 MB90945 Series 7. Notes on A/D Converter Section • About the external impedance of the analog input and its sampling time • A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. • Analog input circuit model R Analog input C Comparator During sampling : ON R C Note : The values are reference values. MB90F946A/947A/ F947/F947A/F949/ F949A 2.4 kΩ (Max) 36.4 pF (Max) • To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. • The relationship between the external impedance and minimum sampling time (External impedance = 0 kΩ to 100 kΩ) MB90F947 MB90F949 (External impedance = 0 kΩ to 20 kΩ) MB90F947 MB90F949 100 20 External impedance [kΩ] 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 External impedance [kΩ] 90 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 Minimum sampling time [µs] Minimum sampling time [µs] • If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. • About the error The accuracy gets worse as |AVRH − AVRL| becomes smaller. 59 MB90945 Series 8. Flash Memory Program/Erase Characteristics Parameter Sector erase time Conditions Value Min ⎯ TA = +25 °C VCC = 5.0 V ⎯ ⎯ ⎯ ⎯ Average TA = +85 °C 10,000 20 Typ 1 5 7 16 ⎯ ⎯ Max 15 ⎯ ⎯ 3,600 ⎯ ⎯ Unit s s s µs cycle Year * Remarks Excludes programming prior to erasure MB90F947, Excludes programming prior to erasure MB90F949, Excludes programming prior to erasure Except for the overhead time of the system Chip erase time Word (16-bit width) programming time Program/Erase cycle Flash Data Retention Time * : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at +85 °C) . 60 MB90945 Series ■ EXAMPLE CHARACTERISTICS •MB90F947 ICC - VCC TA = +25 ˚C, at external clock operating f = Internal operation frequency 60 30 ICCS - VCC TA = +25 ˚C, at external clock operating f = Internal operation frequency 50 f = 24 MHz f = 20 MHz ICCS [mA] f = 16 MHz 25 40 ICC [mA] 20 f = 24 MHz 15 f = 20 MHz f = 16 MHz 10 f = 12 MHz f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz 2.0 3.0 4.0 5.0 VCC [V] 6.0 7.0 30 f = 12 MHz 20 f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz 0 2.0 3.0 4.0 5.0 VCC [V] ICTS - VCC TA = +25 ˚C, at external clock operating f = Internal operation frequency 500 450 400 350 6.0 7.0 10 5 0 ICTSPLL6 - VCC TA = +25 ˚C, at external clock operating f = Internal operation frequency 10 9 8 7 ICTSPLL6 [mA] 6 5 4 3 2 1 0 f = 24 MHz ICTS [µA] 300 250 200 150 100 50 0 2.0 3.0 4.0 5.0 VCC [V] 6.0 7.0 f = 2 MHz 2.0 3.0 4.0 5.0 VCC [V] 6.0 7.0 (Continued) 61 MB90945 Series (Continued) ICCH - VCC TA = +25 ˚C, at stop 10 9 8 7 ICCH [µA] 6 5 4 3 2 1 0 2.0 3.0 4.0 5.0 VCC [V] 6.0 7.0 62 MB90945 Series •MB90F949 ICC - VCC TA = +25 ˚C, at external clock operating f = Internal operation frequency 60 f = 24 MHz f = 20 MHz 20 f = 16 MHz 30 f = 12 MHz 20 f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz 0 2.0 3.0 4.0 5.0 VCC [V] 6.0 7.0 0 2.0 3.0 ICCS [mA] 30 ICCS - VCC TA = +25 ˚C, at external clock operating f = Internal operation frequency 50 25 40 ICC [mA] f = 24 MHz f = 20 MHz f = 16 MHz 15 10 10 5 f = 12 MHz f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz 4.0 5.0 VCC [V] 6.0 7.0 ICTS - VCC TA = +25 ˚C, at external clock operating f = Internal operation frequency 500 450 400 350 ICTSPLL6 [mA] ICTS [µA] 300 250 200 150 100 50 0 2.0 3.0 4.0 5.0 VCC [V] 6.0 7.0 f = 2 MHz 10 9 8 7 6 5 4 3 2 1 0 2.0 3.0 ICTSPLL6 - VCC TA = +25 ˚C, at external clock operating f = Internal operation frequency f = 24 MHz 4.0 5.0 VCC [V] 6.0 7.0 (Continued) 63 MB90945 Series (Continued) ICCH - VCC TA = +25 ˚C, at stop 10 9 8 7 ICCH [µA] 6 5 4 3 2 1 0 2.0 3.0 4.0 5.0 VCC [V] 6.0 7.0 64 MB90945 Series •I/O Characteristic (VCC−VOH) − IOH TA = +25 °C, VCC = 4.5 V 900 800 VCC-VOH (mV) 700 600 500 400 300 200 100 0 0 1 2 3 4 5 6 IOH (mA) 7 VOL − IOL TA = +25 °C, VCC = 4.5 V 1000 900 800 700 600 500 400 300 200 100 0 0 1 2 3 4 5 IOL (mA) 6 7 8 9 10 8 9 10 Automotive VIN − VCC TA = +25 °C 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.5 3.0 VOL (mV) CMOS VIN − VCC CAN RX pin, I2C pin TA = +25 °C VIHA VILA VIN (V) VIHS VIN (V) VILS 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 VCC (V) VCC (V) 65 MB90945 Series ■ ORDERING INFORMATION Part number MB90F946APF MB90947APF Package 100-pin Plastic QFP (FPT-100P-M06) 100-pin Plastic QFP (FPT-100P-M06) 100-pin Plastic QFP (FPT-100P-M06) 100-pin Plastic QFP (FPT-100P-M06) 100-pin Plastic QFP (FPT-100P-M06) 100-pin Plastic QFP (FPT-100P-M06) 299-pin Ceramic PGA (PGA-299C-A01) 299-pin Ceramic PGA (PGA-299C-A01) For evaluation It is recommended to use MB90V390HB For evaluation It is recommended to use MB90F949A, because MB90F949 does not support clock modulation and CAN at the same time It is recommended to use MB90F947A, because MB90F947 does not support clock modulation and CAN at the same time Remarks MB90F947PF MB90F947APF MB90F949PF MB90F949APF MB90V390HACR MB90V390HBCR 66 MB90945 Series ■ PACKAGE DIMENSIONS 100-pin Plastic QFP (FPT-100P-M06) 23.90±0.40(.941±.016) * 20.00±0.20(.787±.008) 80 51 Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 81 50 0.10(.004) 17.90±0.40 (.705±.016) *14.00±0.20 (.551±.008) INDEX Details of "A" part 100 31 1 30 0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8˚ 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.25±0.20 (.010±.008) (Stand off) 0.65(.026) 0.32±0.05 (.013±.002) 0.13(.005) M "A" C 2002 FUJITSU LIMITED F100008S-c-5-5 Dimensions in mm (inches) . Note : The values in parentheses are reference values. 67 MB90945 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0507 © 2005 FUJITSU LIMITED Printed in Japan