MB90F962SPMT

FUJITSU SEMICONDUCTOR DATA SHEET DS07-13749-1E 16-bit Microcontroller CMOS F2MC-16LX MB90960 Series MB90F962(S)/V340E-101/V340E-102 ■ DESCRIPTION The MB90960-series is a 16-bit general-purpose microcontroller. Fujitsu now offers on-chip Flash-ROM program memory up to 64 Kbytes. The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates a major advantage in terms of EMI and power consumption. The unit features a 4 channel input capture unit, 1 channel 16-bit free-run timer, 2-channel LIN-UART, and 16channel 8/10-bit A/D converter as the peripheral resource. Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller. ■ FEATURES • Clock • Built-in PLL clock frequency multiplying circuit • Machine clock (PLL clock) selectable from frequency division by 2 of oscillation clock or 1 to 6-multiplied oscillation clock (4 MHz to 24 MHz when oscillation clock is 4 MHz) . • Sub clock operation : Up to 50 kHz (devices without S-suffix only) • Minimum instruction execution time : 42 ns (4 MHz oscillation clock and 6-multiplied PLL clock) . (Continued) Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development. Copyright©2007 FUJITSU LIMITED All rights reserved MB90960 Series • Instruction system optimized controllers • 16 Mbytes CPU memory space : Internal 24-bit addressing • Various data types (bit, byte, word, and long word) • Various addressing modes (23 types) • Enhanced signed instructions of multiplication/division and RETI • Enhanced high-accuracy operations by 32-bit accumulator • Instruction system for high-level language (C language) / multitask • System stack pointer • Enhanced pointer indirect instructions • Barrel shift instructions • Higher execution speed • 4-byte instruction queue • Powerful interrupt function • Powerful interrupt function with 8 levels and 34 factors • Corresponds to 8-channel external interrupt • CPU-independent automatic data transfer function • Expanded intelligent I/O service function (EI2OS) : Maximum 16 channels • Low-power consumption mode • Clock mode PLL clock mode (a PLL clock that is a multiple of the oscillation clock is used to operate the CPU and peripheral functions.) Main clock mode (the main clock, with the oscillation clock frequency divided by 2 is used to operate the CPU and peripheral functions.) Sub clock mode (the sub clock is used to operate the CPU and peripheral functions.) • Standby mode Sleep mode (stops the operation clock to the CPU.) Watch mode (operates the sub clock and watch timer only.) Time-base timer mode (operates the oscillation clock, sub clock, time-base timer and watch timer only.) Stop mode (stops the operates the oscillation clock and sub clock.) • CPU intermittent operation mode • I/O port • General-purpose input/output ports (CMOS output) - 34 ports (products without S-suffix) - 36 ports (products with S-suffix) • Sub clock pin (X0A, X1A) • Yes : (external oscillator used), products without S-suffix • No : products with S-suffix • Timer • Time-base timer, watch timer (products without S-suffix), watchdog timer : 1 channel • 8/16-bit PPG timer : 8-bit × 4 channels or 16-bit × 2 channels • 16-bit reload timer : 2 channels • 16- bit input/output timer - 16-bit free-run timer : 1 channel - 16- bit input capture (ICU) : 4 channels (Continued) 2 MB90960 Series (Continued) • LIN-UART (LIN/SCI) : Maximum 2 channels • Full-duplex double buffer • Clock-asynchronous or clock-synchronous serial transfer • DTP/External interrupt : 8 channels • Module for activation of expanded intelligent I/O service (EI2OS) and generation of external interrupt by external input. • Delayed interrupt generator module • Generates interrupt request for task switching. • 8/10-bit A/D converter : 16 channels • 8-bit and 10-bit resolution. • Start by external trigger input. • Conversion time : 3 µs (frequency, including sampling time at 24 MHz machine clock) • Program patch function • Detects address match for 6 address pointers. • Changeable port input voltage level • Automotive input level/CMOS Schmitt input level (initial value in single-chip mode is Automotive level). 3 MB90960 Series ■ PRODUCT LINEUP Part number MB90F962 Parameter Type CPU System clock ROM RAM capacitance Power supply for emulator*1 Sub clock pin (X0A, X1A) Operating voltage range Operating temperature range Package Yes 3.5 V to 5.5 V : at normal operation (not using A/D converter and not doing flash programming) 4.0 V to 5.5 V : at normal operation − 40 °C to + 125°C *2 LQFP-48P 2 channels LIN-UART Flash memory product F2MC-16LX CPU PLL clock multiplier ( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops) Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL × 6) Flash memory 64 Kbytes (60 Kbytes + 4 Kbytes Sectors) 3 Kbytes ⎯ No External 30 Kbytes Yes Yes Evaluation product MB90F962S MB90V340E-101 MB90V340E-102 5 V ± 10% ⎯ PGA-299C 5 channels Wide range of baud rate settings using a dedicated reload timer Special synchronous options for adapting to different synchronous serial protocols LIN functionality working either as master or slave LIN device 16 channels 24 channels 10-bit or 8-bit resolution Conversion time: Min. 3 µs includes sample time (per one channel) 2 channels 4 channels 1 3 5 8/10-bit A/D Converter 16-bit Reload Timer Operation clock frequency: fsys/2 , fsys/2 , fsys/2 (fsys = Machine clock frequency) Supports External Event Count function 1 channel 4 channels Signals an interrupt when overflowing. Operating clock frequency: fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27 (fsys = Machine clock frequency) 4 channels 6 channels Maintains I/O timer value by pin input (rising edge, falling edge, or both edge), and generates interrupt (Continued) 16-bit I/O Timer 16-bit Input Capture 4 MB90960 Series (Continued) Part number Parameter MB90F962 MB90F962S MB90V340E-101 MB90V340E-102 8/16-bit PPG timer 2 channels (16-bit) / 4 channels (8-bit) 8-bit reload counters × 4 8-bit reload registers for “L” pulse width × 4 8-bit reload registers for “H” pulse width × 4 8 channels (16-bit) / 16 channels (8-bit) 8-bit reload counters × 16 8-bit reload registers for “L” pulse width × 16 8-bit reload registers for “H” pulse width × 16 Supports 8-bit and 16-bit operation modes. A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler + 8-bit reload counter. Operating clock frequency: fsys, fsys/21, fsys/22, fsys/23, fsys/24, or 128 µs @ fosc = 4 MHz (fsys = Machine clock frequency, fosc = Oscillation clock frequency) 8 channels Can be used rising edge, falling edge, starting up by “H”/“L” level input, external input,extended intelligent I/O services (EI2OS) and DMA. MB90V340E-102 MB90V340E-101 ⎯ External Interrupts Corresponding evaluation product *1 : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the Emulator hardware manual for the details. *2 : If used exceeding TA = +105°C, be sure to contact Fujitsu for reliability limitations. 5 MB90960 Series ■ PIN ASSIGNMENT • MB90F962(S) (TOP VIEW) (LQFP-48P) P82/SIN0/INT14R/TIN2 P84/SCK0/INT15R P44/FRCK0 P83/SOT0/TOT2 P42/INT9R X0A/P40 * X1A/P41 * P87/SCK1 38 P86/SOT1 AVss 48 47 46 45 44 43 42 41 40 39 37 P85/SIN1 P43 AVcc AVR P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6/PPGC(D) P67/AN7/PPGE(F) P80/ADTG/INT12R P50/AN8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 P20 P21 P22/PPGD(C) P23/PPGF(E) P24/IN0 P25/IN1 P26/IN2 P27/IN3 X1 X0 C Vss P52/AN10 P55/AN13/INT10 P54/AN12/TOT3/INT8 P56/AN14/INT11 P53/AN11/TIN3 P57/AN15/INT13 MD2 MD1 P51/AN9 MD0 RST (FPT-48P-M26) * : MB90F962: X0A, X1A MB90F962S: P40, P41 6 Vcc MB90960 Series ■ PIN DESCRIPTION Pin No. LQFP-48P* 1 2 3 to 8 Pin name AVCC AVR P60 to P65 AN0 to AN5 P66, P67 9, 10 AN6, AN7 PPGC (D) , PPGE (F) P80 11 ADTG INT12R 12 to 14 P50 to P52 AN8 to AN10 P53 15 AN11 TIN3 P54 16 AN12 TOT3 INT8 P55 to P57 17 to 19 AN13 to AN15 INT10, INT11, INT13 20 21, 22 23 24 25 26 27 28 MD2 MD1, MD0 RST VCC VSS C X0 X1 D C E ⎯ ⎯ I A H H H H F H Circuit type I ⎯ H Function VCC power input pin for analog circuit. Power (Vref+) input pin for A/D converter. AVR should not exceed VCC. General-purpose I/O ports. Analog input pins for A/D converter. General-purpose I/O ports. Analog input pins for A/D converter. Output pins for PPG. General-purpose I/O port. Trigger input pin for A/D converter. External interrupt request input pin for INT12R. General-purpose I/O ports (I/O circuit type of P50 is different from that of MB90V340E) . Analog input pins for A/D converter. General-purpose I/O port. Analog input pin for A/D converter. Event input pin for reload timer 3. General-purpose I/O port. Analog input pin for A/D converter. Output pin for reload timer 3. External interrupt request input pin for INT8. General-purpose I/O ports. Analog input pins for A/D converter. External interrupt request input pins for INT10, INT11, INT13. Input pin for selecting operation mode. Input pins for selecting operation mode. Reset input. Power input pin (3.5 V to 5.5 V) . Power input pin (0 V) . Capacity pin for stabilizing power supply. It should be connected to a higher than or equal to 0.1 µF ceramic capacitor. Oscillation input pin. Oscillation output pin. (Continued) 7 MB90960 Series Pin No. LQFP-48P* Pin name Circuit type Function General-purpose I/O ports. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. Event input pins for input capture 0 to 3. General-purpose I/O ports. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. Output pins for PPG. General-purpose I/O ports. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. General-purpose I/O port. Serial data input pin for LIN-UART1. General-purpose I/O port. Clock I/O pin for LIN-UART1. General-purpose I/O port. Serial data output pin for LIN-UART1. General-purpose I/O port. General-purpose I/O port. External interrupt request input pin for INT9R. General-purpose I/O port. Serial data output pin for LIN-UART0. Output pin for reload timer 2 General-purpose I/O port. 29 to 32 P27 to P24 IN3 to IN0 P23, P22 G 33, 34 PPGF (E) , PPGD (C) 35, 36 P21, P20 P85 SIN1 P87 SCK1 P86 SOT1 P43 P42 INT9R P83 42 SOT0 TOT2 P84 43 SCK0 INT15R P82 44 SIN0 INT14R TIN2 45 P44 FRCK0 G G 37 38 39 40 41 K F F F F F F Clock I/O pin for LIN-UART0. External interrupt request input pin for INT15R. General-purpose I/O port. Serial data input pin for LIN-UART0. External interrupt request input pin for INT14R. Event input pin for reload timer 2. General-purpose I/O port (I/O circuit type of P44 is different from that of MB90V340E) . Free-run timer 0 clock input pin. (Continued) K F 8 MB90960 Series (Continued) Pin No. Pin name LQFP-48P* P40, P41 46, 47 X0A, X1A 48 * : FPT-48P-M26 AVSS B I F General-purpose I/O ports. (products with S-suffix and MB90V340E-101) X0A: Oscillation input pin for sub clock X1A: Oscillation output pin for sub clock (products without S-suffix and MB90V340E-102) VSS power input pin for analog circuit. Circuit type Function 9 MB90960 Series ■ I/O CIRCUIT TYPE Type X1 Circuit Remarks Oscillation circuit High-speed oscillation feedback resistor = approx. 1 MΩ Xout A X0 Standby control signal X1A Xout Oscillation circuit Low-speed oscillation feedback resistor = approx. 10 MΩ B X0A Standby control signal CMOS input C R CMOS Hysteresis inputs R CMOS Hysteresis inputs • CMOS input • No Pull-down D Pull-down resistor CMOS hysteresis input Pull-up resistor value : approx. 50 kΩ Pull-up resistor R CMOS Hysteresis inputs E (Continued) 10 MB90960 Series Type Circuit Remarks • CMOS level output (IOL = 4 mA, IOH = − 4 mA) • CMOS hysteresis input (With the standby-time input shutdown function) • Automotive input (With the standbytime input shutdown function) P-ch Pout N-ch Nout F R CMOS hysteresis input Automotive input Standby control for input shutdown Pull-up control Pull-up resistor P-ch P-ch Pout N-ch Nout G R CMOS hysteresis input • CMOS level output (IOL = 4 mA, IOH = − 4 mA) • CMOS hysteresis input (With the standby-time input shutdown function) • Automotive input (With the standbytime input shutdown function) • Programmable pull-up resistor : approx. 50 kΩ Automotive input Standby control for input shutdown P-ch Pout N-ch R Nout H CMOS hysteresis input • CMOS level output (IOL = 4 mA, IOH = − 4 mA) • CMOS hysteresis input (With the standby-time input shutdown function) • Automotive input (With the standbytime input shutdown function) • A/D analog input Automotive input Standby control for input shutdown A/D analog input (Continued) 11 MB90960 Series (Continued) Type Circuit Remarks Power supply input protection circuit P-ch I N-ch P-ch Pout N-ch Nout • CMOS level output (IOL = 4 mA, IOH = − 4 mA) • CMOS input (With standby-time input shutdown function) • Automotive input (With the standbytime input shutdown function) K R CMOS input Automotive input Standby control for input shutdown 12 MB90960 Series ■ HANDLING DEVICES Special care is required for the following when handling the device : • Preventing latch-up • Treatment of unused pins • Using external clock • Notes on during operation of PLL clock mode • Power supply pins (VCC/VSS) • Pull-up/down resistors • Crystal oscillator circuit • Turning-on sequence of power supply to A/D converter and analog inputs • Connection of unused pins of A/D converter • Notes on energization • Stabilization of power supply voltage • Initialization • Correspondence with +105 °C or more 1. Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions : • A voltage higher than VCC or lower than VSS is applied to an input or output pin. • A voltage higher than the rated voltage is applied between VCC and VSS. • The AVCC power supply is applied before the VCC voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. When used, note that maximum rated voltage is not exceeded. For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVR) exceed the digital power-supply voltage. 2. Treatment of unused pins Leaving unused input pins open may result in misbehavior or latch-up and possible permanent damage of the device. Therefore, they must be pulled up or pulled down through resistors. In this case, those resistors should be more than 2 kΩ . Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. 3. Using external clock To use external clock, drive the X0 (X0A) pin and leave X1 (X1A) pin open. MB90960 Series X0 (X0A) Open X1 (X1A) 13 MB90960 Series 4. Notes on during operation of PLL clock mode On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs. 5. Power supply pins (VCC/VSS) • If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected the inside of the device to prevent such malfunctioning as latch-up. To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and to keep the recommended DC characteristics specified as the total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally. • Connect VCC and VSS to the device from the power supply source with lowest possible impedance. • It is recommended to connect a capacitor of about 0.1 µF as a bypass capacitor between VCC and VSS in the vicinity of VCC and VSS pins of the device. VCC VSS VCC VSS VCC MB90960 Series VSS VCC VSS VSS VCC 6. Pull-up/down resistors The MB90960 series does not support internal pull-up/down resistors (except Port 2 : programmable pull-up resistors) . Use pull-up/down handling where needed. 7. Crystal oscillator circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits. It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground area for stabilizing the operation. 8. Turning-on sequence of power supply to A/D converter and analog inputs Make sure to turn on the A/D converter power supply (AVCC, AVR) and analog inputs (AN0 to AN15) after turningon the digital power supply (VCC) . Turn-off the digital power supply after turning off the A/D converter power supply and analog inputs. In this case, make sure that the voltage does not exceed AVR or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable) . 9. Connection of unused pins of A/D converter if A/D converter is not used Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVR = VSS. 14 MB90960 Series 10. Notes on energization To prevent malfunction of the internal voltage regulator , supply voltage profile while turning on the power supply should be slower than 50 µs (0.2 V to 2.7 V) . 11. Stabilization of power supply voltage If the power supply voltage varies acutely even within the operation assurance range of the VCC power supply voltage, a malfunction may occur. The VCC power supply voltage must therefore be stabilized. As stabilization guide lines, stabilize the power supply voltage so that VCC ripple fluctuations (peak to peak value) in the commercial frequencies (50 Hz/60 Hz) fall within 10% of the standard VCC power supply voltage and the transient fluctuation rate becomes 0.1 V/ms or less in instantaneous fluctuation for power supply switching. 12. Initialization In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers, turn on the power again. 13. Correspondence with +105 °C or more If used exceeding TA = +105 °C, please contact Fujitsu for reliability limitations. 15 MB90960 Series ■ BLOCK DIAGRAMS • MB90V340E-101/V340E-102 X0 X1 RST X0A* X1A* Clock controller F2MC-16LX core 16-bit I/O timer 0 Input capture 8 channels FRCK0 IN7 to IN0 RAM 30 Kbytes Prescaler (5 channels) SOT4 to SOT0 SCK4 to SCK0 SIN4 to SIN0 AVCC AVSS AN23 to AN0 AVRH AVRL ADTG Output compare 8 channels 16-bit I/O timer 1 CAN controller 3 channels Internal data bus 16-bit reload Timer 4 channels OUT7 to OUT0 FRCK1 LIN-UART 5 channels RX2 to RX0 TX2 to TX0 8/10-bit A/D converter 24 channels TIN3 to TIN0 TOT3 to TOT0 AD15 to AD00 A23 to A16 ALE RD WRL WRH HRQ HAK RDY CLK DA01, DA00 10-bit D/A converter 2 channels 8/16-bit PPG timer 16/8 channels I2C interface 2 channels DMA External bus PPGF to PPG0 SDA1, SDA0 SCL1, SCL0 DTP/ External interrupt Clock monitor INT15 to INT8 (INT15R to INT8R) INT7 to INT0 CKOT * : Only for MB90V340E-102 16 MB90960 Series • MB90F962(S) X0 X1 RST X0A* X1A* Clock controller F2MC-16LX core Input capture 4 channels 16-bit I/O timer 0 RAM 3 Kbytes IN0 to IN3 FRCK0 ROM 64 Kbytes Internal data bus Prescaler (2 channels) SOT0, SOT1 SCK0, SCK1 SIN0, SIN1 AVCC AVSS AN15 to AN0 AVR ADTG 16-bit reload timer 2 channels TIN2, TIN3 TOT2, TOT3 LIN-UART 2 channels 8/10-bit A/D converter 16 channels PPGF(E), PPGD(C), PPGC(D), PPGE(F) 8/16-bit PPG timer 4/2 channels DTP/ External interrupt INT8, INT9R INT10, INT11 INT12R, INT13 INT14R, INT15R * : Only for MB90F962 17 MB90960 Series ■ MEMORY MAP MB90V340E-101 MB90V340E-102 MB90F962(S) FFFFFFH ROM (FF bank) FF0000H FEFFFFH ROM (FE bank) FE0000H FDFFFFH ROM (FD bank) FD0000H FCFFFFH ROM (FC bank) FC0000H FBFFFFH ROM (FB bank) FB0000H FAFFFFH ROM (FA bank) FA0000H F9FFFFH ROM (F9 bank) F90000H F8FFFFH ROM (F8 bank) F80000H 00FFFFH 008000H 007FFFH 007900H 0078FFH FFFFFFH FF0000H FEFFFFH ROM (FF bank) 010000H 00FFFFH ROM (image of FF bank) Peripheral 008000H 007FFFH 007900H ROM (image of FF bank) Peripheral RAM 30 Kbytes 000100H 0000EFH 000000H Peripheral 000CFFH 000100H 0000FFH 0000F0H 0000EFH 000000H RAM 3 Kbytes Peripheral : Access prohibited Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referred without using the far specification in the pointer declaration. For example, an attempt to access 00C000H accesses the value at FFC000H in ROM. The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00. The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF7FFFH is visible only in bank FF. 18 MB90960 Series ■ I/O MAP Address 000000H, 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H, 00000AH 00000BH Port 5 Analog Input Enable Register 00000CH Port 6 Analog Input Enable Register 00000DH 00000EH Input Level Select Register 0 00000FH Input Level Select Register 1 0000010H, 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 000019H 00001AH Port A Direction Register 00001BH to 00001DH 00001EH Port 2 Pull-up Control Register 00001FH Port 8 Direction Register Port 4 Direction Register Port 5 Direction Register Port 6 Direction Register Port 2 Direction Register Port 8 Data Register Port 4 Data Register Port 5 Data Register Port 6 Data Register Port 2 Data Register Register Abbreviation Reserved PDR2 Reserved PDR4 PDR5 PDR6 Reserved PDR8 Reserved ADER5 ADER6 Reserved ILSR0 ILSR1 Reserved DDR2 Reserved DDR4 DDR5 DDR6 Reserved DDR8 Reserved DDRA Reserved PUCR2 Reserved (Continued) R/W Port 2 00000000B W Port A XXX00XXXB R/W Port 8 000000X0B R/W R/W R/W Port 4 Port 5 Port 6 XXX00000B 00000000B 00000000B R/W Port 2 00000000B R/W R/W Port 2, 4, 5, 6 Port 8 X000X0XXB XXXXXXX0B R/W R/W Port 5, A/D Port 6, A/D 11111111B 11111111B R/W Port 8 XXXXXXXXB R/W R/W R/W Port 4 Port 5 Port 6 XXXXXXXXB XXXXXXXXB XXXXXXXXB R/W Port 2 XXXXXXXXB Access Resource name Initial value 19 MB90960 Series Address Register Abbreviation SMR0 SCR0 RDR0/TDR0 SSR0 ECCR0 ESCR0 BGR00 BGR01 SMR1 SCR1 RDR1/TDR1 SSR1 ECCR1 ESCR1 BGR10 BGR11 Reserved Access W, R/W W, R/W R/W R, R/W R, W, R/W R/W R/W, R R/W, R W, R/W W, R/W R/W R, R/W R, W, R/W R/W R/W, R R/W, R Resource name Initial value 00000000B 00000000B 00000000B 00001000B LIN-UART0 000000XXB 00000100B 00000000B 00000000B 00000000B 00000000B 00000000B 00001000B LIN-UART1 000000XXB 00000100B 00000000B 00000000B 000020H Serial Mode Register 0 000021H Serial Control Register 0 000022H Reception/Transmission Data Register 0 000023H Serial Status Register 0 000024H Extended Communication Control Register 0 000025H Extended Status Control Register 0 000026H Baud Rate Generator Register 00 000027H Baud Rate Generator Register 01 000028H Serial Mode Register 1 000029H Serial Control Register 1 00002AH Reception/Transmission Data Register 1 00002BH Serial Status Register 1 00002CH Extended Communication Control Register 1 00002DH Extended Status Control Register 1 00002EH Baud Rate Generator Register 10 00002FH Baud Rate Generator Register 11 000030H to 00003AH 00003BH Address Detect Control Register 1 00003CH to 000047H 000048H PPGC Operation Mode Control Register 000049H PPGD Operation Mode Control Register 00004AH 00004BH 00004CH PPGE Operation Mode Control Register 00004DH PPGF Operation Mode Control Register 00004EH 00004FH PPGE/PPGF Count Clock Select Register PPGC/PPGD Count Clock Select Register PACSR1 R/W Address Match Detection 1 00000000B Reserved PPGCC PPGCD PPGCD Reserved PPGCE PPGCF PPGEF Reserved (Continued) W, R/W W, R/W R/W 16-bit PPG E/F 0X000XX1B 0X000001B 000000X0B W, R/W W, R/W R/W 16-bit PPG C/D 0X000XX1B 0X000001B 000000X0B 20 MB90960 Series Address Register Abbreviation ICS01 ICE01 ICS23 ICE23 Access R/W R/W, R R/W R Resource name Input Capture 0/1 Input Capture 2/3 Initial value 00000000B XXX0X0XXB 00000000B XXXXXXXXB 000050H Input Capture Control Status 0/1 000051H Input Capture Edge 0/1 000052H Input Capture Control Status 2/3 000053H Input Capture Edge 2/3 000054H to 000063H 000064H Timer Control Status 2 000065H Timer Control Status 2 000066H Timer Control Status 3 000067H Timer Control Status 3 000068H A/D Control Status 0 000069H A/D Control Status 1 00006AH A/D Data Register 0 00006BH A/D Data Register 1 00006CH A/D Converter Setting 0 00006DH A/D Converter Setting 1 00006EH 00006FH ROM Mirror Function Select 000070H to 00009DH 00009EH Address Detect Control Register 0 00009FH Delayed Interrupt/Release Register Low-power Consumption Mode Control Register Reserved TMCSR2 TMCSR2 TMCSR3 TMCSR3 ADCS0 ADCS1 ADCR0 ADCR1 ADSR0 ADSR1 Reserved ROMM Reserved Address Match Detection 0 Delayed Interrupt generation module Low-Power consumption Control Circuit Low-Power consumption Control Circuit W ROM Mirror XXXXXXX1B R/W R/W R/W R/W R/W R/W, W R R R/W R/W A/D Converter 00000000B XXXX0000B 00000000B XXXX0000B 000XXXX0B 0000000XB 00000000B XXXXXX00B 00000000B 00000000B 16-bit Reload Timer 2 16-bit Reload Timer 3 PACSR0 DIRR R/W R/W 00000000B XXXXXXX0B 0000A0H LPMCR W, R/W 00011000B 0000A1H Clock Selection Register 0000A2H to 0000A7H 0000A8H Watchdog Timer Control Register 0000A9H Time-base Timer Control Register CKSCR R, R/W 11111100B Reserved WDTC TBTC R, W W, R/W Watchdog Timer Time-base Timer XXXXX111B 1XX00100B (Continued) 21 MB90960 Series Address 0000ABH to 0000ADH Register Abbreviation WTC Access R, R/W Resource name Watch Timer Initial value 1X001000B 0000AAH Watch Timer Control Register Reserved FMCS ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 R, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W Interrupt Control Flash Memory 000X0000B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 0000AEH Flash Control Status 0000AFH 0000B0H Interrupt Control Register 00 0000B1H Interrupt Control Register 01 0000B2H Interrupt Control Register 02 0000B3H Interrupt Control Register 03 0000B4H Interrupt Control Register 04 0000B5H Interrupt Control Register 05 0000B6H Interrupt Control Register 06 0000B7H Interrupt Control Register 07 0000B8H Interrupt Control Register 08 0000B9H Interrupt Control Register 09 0000BAH Interrupt Control Register 10 0000BBH Interrupt Control Register 11 0000BCH Interrupt Control Register 12 0000BDH Interrupt Control Register 13 0000BEH Interrupt Control Register 14 0000BFH Interrupt Control Register 15 0000C0H to 0000C9H 0000CAH DTP/External Interrupt Enable 1 0000CBH DTP/External Interrupt Source 1 0000CCH Detection Level Setting 1 0000CDH Detection Level Setting 1 0000CEH External Interrupt factor Select 0000CFH PLL/Sub clock Control Register 0000D0H to 0000FFH Reserved Reserved ENIR1 EIRR1 ELVR1 ELVR1 EISSR PSCCR Reserved (Continued) R/W R/W R/W R/W R/W W PLL External Interrupt 1 00000000B XXXXXXXXB 00000000B 00000000B 00000000B XXXX0000B 22 MB90960 Series Address 007900H to 007917H Register Abbreviation Access Resource name Initial value Reserved PRLLC PRLHC PRLLD PRLHD PRLLE PRLHE PRLLF PRLHF IPCP0 IPCP0 IPCP1 IPCP1 IPCP2 IPCP2 IPCP3 IPCP3 Reserved TCDT0 TCDT0 TCCSL0 TCCSH0 Reserved R/W R/W R/W R/W 16-bit Reload Timer 2 16-bit Reload Timer 3 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB R/W R/W R/W R/W I/O Timer 0 00000000B 00000000B 00000000B 0XXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R Input Capture 2/3 Input Capture 0/1 16-bit PPG E/F 16-bit PPG C/D XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 007918H Reload Register LC 007919H Reload Register HC 00791AH Reload Register LD 00791BH Reload Register HD 00791CH Reload Register LE 00791DH Reload Register HE 00791EH Reload Register LF 00791FH Reload Register HF 007920H Input Capture 0 007921H Input Capture 0 007922H Input Capture 1 007923H Input Capture 1 007924H Input Capture 2 007925H Input Capture 2 007926H Input Capture 3 007927H Input Capture 3 007928H to 00793FH 007940H Timer Data 0 007941H Timer Data 0 007942H Timer Control Status 0 007943H Timer Control Status 0 007944H to 00794BH 00794CH 00794DH 00794EH 00794FH 007950H to 0079DFH Timer 2/Reload 2 Timer 3/Reload 3 TMR2/TMRLR2 TMR3/TMRLR3 Reserved (Continued) 23 MB90960 Series (Continued) Address Register Abbreviation PADR0 PADR0 PADR0 PADR1 PADR1 PADR1 PADR2 PADR2 PADR2 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0079E0H Detect Address Setting 0 0079E1H Detect Address Setting 0 0079E2H Detect Address Setting 0 0079E3H Detect Address Setting 1 0079E4H Detect Address Setting 1 0079E5H Detect Address Setting 1 0079E6H Detect Address Setting 2 0079E7H Detect Address Setting 2 0079E8H Detect Address Setting 2 0079E9H to 0079EFH 0079F0H Detect Address Setting 3 0079F1H Detect Address Setting 3 0079F2H Detect Address Setting 3 0079F3H Detect Address Setting 4 0079F4H Detect Address Setting 4 0079F5H Detect Address Setting 4 0079F6H Detect Address Setting 5 0079F7H Detect Address Setting 5 0079F8H Detect Address Setting 5 0079F9H to 007FFFH Address Match Detection 0 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Reserved PADR3 PADR3 PADR3 PADR4 PADR4 PADR4 PADR5 PADR5 PADR5 Reserved R/W R/W R/W R/W R/W R/W R/W R/W R/W Address Match Detection 1 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Notes : • Initial value of “X” represents unknown value. • Any write access to reserved addresses in I/O map should not be performed. A read access to reserved addresses results in reading “X”. 24 MB90960 Series ■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER Interrupt cause Reset INT9 instruction Exception processing Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 16-bit reload timer 2 16-bit reload timer 3 Reserved Reserved PPG C/D PPG E/F Time-base timer External interrupt 8 to 11 Watch Timer External interrupt 12 to 15 A/D converter I/O timer 0 Reserved Reserved Input capture 0 to 3 Reserved LIN-UART 0 reception LIN-UART 0 transmission LIN-UART 1 reception LIN-UART 1 transmission EI2OS corresponding N N N N N N N N N N N Y1 Y1 N N N N N Y1 N Y1 Y1 N N N Y1 N Y2 Y1 Y2 Y1 Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H Interrupt control register Number ⎯ ⎯ ⎯ ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 Address ⎯ ⎯ ⎯ 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH (Continued) 25 MB90960 Series (Continued) Interrupt cause Reserved Reserved Flash memory Delayed interrupt generation module Y1 : Usable Y2 : Usable, with EI2OS stop function N : Unusable Notes : • The peripheral resources sharing the ICR register have the same interrupt level. • When 2 peripheral resources share the ICR register, only one can use extended intelligent I/O service at a time. • When either of the 2 peripheral resources sharing the ICR register specifies extended intelligent I/O service, the other one cannot use interrupts. EI2OS corresponding N N N N Interrupt vector Number #39 #40 #41 #42 Address FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt control register Number ICR14 ICR15 Address 0000BEH 0000BFH 26 MB90960 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol VCC Power supply voltage*1 Input voltage*1 Output voltage*1 Maximum clamp current Total Maximum clamp current “L” level maximum output current “L” level average output current “L” level maximum overall output current “L” level average overall output current “H” level maximum output current “H” level average output current “H” level maximum overall output current “H” level average overall output current Power consumption Operating temperature Storage temperature AVCC AVR VI VO ICLAMP Σ|ICLAMP| IOL IOLAV ΣIOL ΣIOLAV IOH IOHAV ΣIOH ΣIOHAV PD TA TSTG Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 −2.0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ −40 −40 −55 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 +2.0 40 15 4 125 40 −15 −4 −125 −40 300 +105 +125 +150 Unit V V V V V mA mA mA mA mA mA mA mA mA mA mW °C °C °C (Continued) *5 VCC = AVCC*2 AVCC ≥ AVR*2 *3 *3 *4 *4 *4 *4 *4 *4 *4 *4 *4 *4 Remarks 27 MB90960 Series (Continued) *1 : This parameter is based on VSS = AVSS = 0 V. *2 : Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on. *3 : VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *4 : Applicable to pins : P20 to P27, P40 to P44, P50 to P57, P60 to P67, P80, P82 to P87 *5 : If used exceeding TA = +105°C, be sure to contact Fujitsu for reliability limitations. • Use within recommended operating conditions. • Use at DC voltage (current) . • The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a +B signal is inputted when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. • Care must be taken not to leave the +B input pin open. • Sample recommended circuits : • Input/output equivalent circuits Protective diode Limiting resistance +B input (0 V to 16 V) N-ch VCC P-ch R WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 28 MB90960 Series 2. Recommended Conditions (VSS = AVSS = 0 V) Parameter Symbol Value Min 4.0 Power supply voltage VCC, AVCC 3.5 3.0 Typ 5.0 5.0 ⎯ ⎯ ⎯ ⎯ Max 5.5 5.5 5.5 Unit V V V µF °C °C * Remarks Under normal operation Under normal operation when not using the A/D converter and not Flash programming. Maintains RAM data in stop mode Use a ceramic capacitor or capacitor of better AC characteristics for the C pin. Bypass capacitor at the VCC pin should be greater than this capacitor. Smooth capacitor CS 0.1 −40 −40 1.0 +105 +125 Operating temperature TA * : If used exceeding TA = +105 °C, please contact Fujitsu for reliability limitations. • C Pin Connection Diagram C CS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 29 MB90960 Series 3. DC Characteristics (TA = −40 °C to +125 °C*1, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Parameter Symbol Pin Condition Value Min Typ ⎯ Max VCC + 0.3 Unit Remarks Pin inputs if CMOS hysteresis levels are selected (except P82, P85) P82, P85 inputs if CMOS input levels are selected Pin inputs if Automotive input levels are selected RST input pin (CMOS hysteresis) MD input pin Pin inputs if CMOS hysteresis input levels are selected (except P82, P85) P82, P85 inputs if CMOS input levels are selected Pin inputs if Automotive input levels are selected RST input pin (CMOS hysteresis) MD input pin ⎯ VIHS ⎯ Input “H” voltage VIHA ⎯ ⎯ ⎯ ⎯ VILS ⎯ Input “L” voltage VILA ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ P20 to P27, RST MD2 ⎯ 0.8 VCC V ⎯ 0.7 VCC ⎯ VCC + 0.3 V ⎯ ⎯ ⎯ ⎯ 0.8 VCC ⎯ ⎯ ⎯ ⎯ VCC + 0.3 VCC + 0.3 VCC + 0.3 0.2 VCC V VIHR VIHM 0.8 VCC VCC − 0.3 VSS − 0.3 V V V ⎯ VSS − 0.3 ⎯ 0.3 VCC V ⎯ ⎯ ⎯ VCC = 4.5 V, IOH = −4.0 mA VCC = 4.5 V, IOL = 4.0 mA VCC = 5.5 V, VSS < VI < VCC ⎯ ⎯ VSS − 0.3 VSS − 0.3 VSS − 0.3 VCC − 0.5 ⎯ −1 25 25 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 50 50 0.5 VCC V VILR VILM Output “H” voltage Output “L” voltage Input leak current Pull-up resistance Pull-down resistance VOH VOL IIL RUP RDOWN 0.2 VCC VSS + 0.3 ⎯ 0.4 +1 100 100 V V V V µA kΩ kΩ Except Flash memory devices (Continued) 30 MB90960 Series (Continued) Symbol (TA = −40 °C to +125 °C*1, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Pin Condition VCC = 5.0 V, Internal frequency : 24 MHz, At normal operation. ICC VCC = 5.0 V, Internal frequency : 24 MHz, At writing Flash memory. VCC = 5.0 V, Internal frequency : 24 MHz, At erasing Flash memory. ICCS VCC = 5.0 V, Internal frequency : 24 MHz, At sleep mode. VCC = 5.0 V, Internal frequency : 2 MHz, At main timer mode VCC VCC = 5.0 V, Internal frequency : 24 MHz, At PLL timer mode, External frequency = 4 MHz VCC = 5.0 V, Internal frequency : 8 kHz, At sub clock operation mode, TA = + 25°C VCC = 5.0 V, Internal frequency : 8 kHz, At sub clock sleep mode, TA = + 25°C VCC = 5.0 V, Internal frequency : 8 kHz, At watch mode, TA = + 25°C VCC = 5.0 V, At stop mode, TA = + 25°C Other than AVCC, AVSS, AVR, VCC, VSS, C Value Min Typ Max ⎯ 35 45 Unit Remarks Parameter mA MB90F962(S) ⎯ 50 60 mA MB90F962(S) ⎯ 50 60 mA MB90F962(S) ⎯ 12 20 mA MB90F962(S) ICTS Power supply current*2 ⎯ 0.3 0.8 mA MB90F962(S) ICTSPLL6 ⎯ 4 7 mA MB90F962(S) ICCL ⎯ 40 100 µA MB90F962 ICCLS ⎯ 10 50 µA MB90F962 ICCT ⎯ 8 30 µA MB90F962 ICCH ⎯ 5 25 µA MB90F962(S) Input capacity CIN ⎯ ⎯ 5 15 pF *1 : If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations. *2 : The power supply current is measured with an external clock. 31 MB90960 Series 4. AC Characteristics (1) Clock Timing (TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Parameter Symbol Pin Value Min 3 4 4 X0, X1 4 4 4 Clock frequency fC 3 4 4 X0, X1 4 4 4 fCL Clock cycle time tCYL tCYLL Input clock pulse width Input clock rise and fall time Internal operating clock frequency (machine clock) Internal operating clock cycle time (machine clock) PWH, PWL PWHL, PWLL tCR, tCF fCP fCPL tCP tCPL X0A, X1A X0, X1 X0, X1 X0A, X1A X0 X0A X0 ⎯ ⎯ ⎯ ⎯ ⎯ 62.5 41.67 10 10 5 ⎯ 1.5 ⎯ 41.67 20 32.768 ⎯ ⎯ 30.5 ⎯ 15.2 ⎯ ⎯ 8.192 ⎯ 122.1 ⎯ 8 6 4 100 333 333 ⎯ ⎯ ⎯ 5 24 50 666 ⎯ kHz ns ns µs ns µs ns When using an oscillation circuit When using an external clock When using sub clock Duty ratio is about 30% to 70%. When using external clock 24 20 12 MHz ⎯ 8 6 4 Typ Max 16 16 12 MHz Unit Remarks 1/2 when PLL stops, When using an oscillation circuit PLL × 1, When using an oscillation circuit PLL × 2, When using an oscillation circuit PLL × 3, When using an oscillation circuit PLL × 4, When using an oscillation circuit PLL × 6, When using an oscillation circuit 1/2 when PLL stops, When using an external clock PLL × 1, When using an external clock PLL × 2, When using an external clock PLL × 3, When using an external clock PLL × 4, When using an external clock PLL × 6, When using an external clock MHz When using main clock kHz ns µs When using sub clock When using main clock When using sub clock *: If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations. 32 MB90960 Series • Clock Timing tCYL X0 PWH tCF PWL tCR 0.8 VCC 0.2 VCC tCYLL X0A PWHL tCF PWLL tCR 0.8 VCC 0.2 VCC 33 MB90960 Series • Guaranteed PLL Operation Range Guaranteed operation range Guaranteed PLL operation range (CS2=1) 5.5 Power supply voltage VCC (V) 4.5 3.5 Guaranteed PLL operation range (CS2=0) Guaranteed A/D converter operation range 1.5 4 8 Machine clock fCP (MHz) 20 24 Guaranteed operation range of MB90960 series • CS2 (bit 0 in PSCCR register) = 0 x4 (CS=011) x3 (CS=010) x2 (CS=001) Guaranteed oscillation frequency range x1 (CS=000) Machine clock fCP (MHz) 20 16 12 8 6 4 1.5 34 x1/2 (PLL off) 6 8 10 12 16 20 24 External clock fC (MHz)* • CS2 (bit 0 in PSCCR register) = 1 x6 (CS=110) x4 (CS=101) x2 (CS=100) 24 Machine clock fCP (MHz) Guaranteed oscillation frequency range 16 12 8 4 1.5 34 6 8 10 12 16 20 24 External clock fC (MHz)* x1/2 (PLL off) * : When using a crystal oscillator or a ceramic oscillator, the maximum oscillation clock frequency is 16 MHz. External clock frequency and Machine clock frequency 34 MB90960 Series (2) Reset Standby Input (TA = −40 °C to +125 °C*1, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Parameter Symbol Pin Value Min 500 Reset input time tRSTL RST Oscillation time of oscillator*2 + 100 µs 100 Max ⎯ ⎯ ⎯ Unit ns ns µs Remarks Under normal operation In stop mode In time-base timer mode *1: If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations. *2 : Oscillation time of oscillator is the time that the amplitude reaches 90%. In the crystal oscillator, the oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of µs and several ms. With an external clock, the oscillation time is 0 ms. • Under normal operation : tRSTL RST 0.2 VCC 0.2 VCC • In stop mode : tRSTL RST 0.2 VCC 90% of amplitude 0.2 VCC X0 Internal operation clock Oscillation time of oscillator 100 µs Oscillation stabilization waiting time Instruction execution Internal reset 35 MB90960 Series (3) Power-on Reset (TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Parameter Power on rise time Power off time Symbol tR tOFF Pin VCC VCC Condition ⎯ Value Min 0.05 1 Max 30 ⎯ Unit ms ms Due to repetitive operation Remarks *: If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations. tR 2.7 V 0.2 V 0.2 V tOFF 0.2 V VCC Note : If you change the power supply voltage too rapidly, a power-on reset may occur. We recommend that you start up smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within 1 V/s, you can operate while using the PLL clock. VCC 3V VSS Holds RAM data We recommend a rise of 50 mV/ms maximum. 36 MB90960 Series (4) LIN-UART0/1 • Bit setting: ESCR0/1:SCES = 0, ECCR0/1:SCDE = 0 (TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V) Value Parameter Symbol Pin Condition Unit Min Max Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → Valid SIN hold time Serial clock “L” pulse width Serial clock “H” pulse width SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → Valid SIN hold time SCK fall time SCK rise time tSCYC tSLOVI tIVSHI tSHIXI tSHSL tSLSH tSLOVE tIVSHE tSHIXE tF tR SCK0, SCK1 SCK0, SCK1, SOT0, SOT1 SCK0, SCK1, SIN0, SIN1 SCK0, SCK1, SIN0, SIN1 SCK0, SCK1 SCK0, SCK1 SCK0, SCK1, SOT0, SOT1 SCK0, SCK1, SIN0, SIN1 SCK0, SCK1, SIN0, SIN1 SCK0, SCK1 SCK0, SCK1 External shift clock mode output pins are CL = 80 pF + 1 TTL. Internal shift clock mode output pins are CL = 80 pF + 1 TTL. 5 tCP −50 tCP + 80 0 3 tCP - tR tCP + 10 ⎯ 30 tCP + 30 ⎯ ⎯ ⎯ +50 ⎯ ⎯ ⎯ ⎯ 2 tCP + 60 ⎯ ⎯ 10 10 ns ns ns ns ns ns ns ns ns ns ns *: If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations. Notes : • AC characteristic in CLK synchronized mode. • CL is load capacity value of pins when testing. • tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”. • Internal Shift Clock Mode tSCYC SCK 2.4 V 0.8 V tSLOVI 0.8 V SOT 2.4 V 0.8 V tIVSHI tSHIXI VIH VIL SIN VIH VIL 37 MB90960 Series • External Shift Clock Mode tSLSH tSHSL VIH VIL tF tSLOVE 2.4 V 0.8 V tIVSHE tSHIXE VIH VIL VIL tR VIH SCK SOT SIN VIH VIL • Bit setting: ESCR0/1:SCES = 1, ECCR0/1:SCDE = 0 (TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V) Value Parameter Symbol Pin Condition Unit Min Max Serial clock cycle time SCK ↑ → SOT delay time Valid SIN → SCK ↓ SCK ↓ → Valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↑ → SOT delay time Valid SIN → SCK ↓ SCK ↓ → Valid SIN hold time SCK fall time SCK rise time tSCYC tSHOVI tIVSLI tSLIXI tSHSL tSLSH tSHOVE tIVSLE tSLIXE tF tR SCK0, SCK1 SCK0, SCK1, SOT0, SOT1 SCK0, SCK1, SIN0, SIN1 SCK0, SCK1, SIN0, SIN1 SCK0, SCK1 SCK0, SCK1 SCK0, SCK1, SOT0, SOT1 SCK0, SCK1, SIN0, SIN1 SCK0, SCK1, SIN0, SIN1 SCK0, SCK1 SCK0, SCK1 External shift clock mode output pins are CL = 80 pF + 1 TTL. Internal shift clock mode output pins are CL = 80 pF + 1 TTL. 5 tCP −50 tCP + 80 0 3 tCP - tR tCP + 10 ⎯ 30 tCP + 30 ⎯ ⎯ ⎯ +50 ⎯ ⎯ ⎯ ⎯ 2 tCP + 60 ⎯ ⎯ 10 10 ns ns ns ns ns ns ns ns ns ns ns * : If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations. 38 MB90960 Series • Internal Shift Clock Mode tSCYC SCK 2.4 V 0.8 V tSHOVI SOT 2.4 V 0.8 V tIVSLI tSLIXI VIH VIL SIN VIH VIL • External Shift Clock Mode tSHSL tSLSH VIH VIL tR tSHOVE 2.4 V 0.8 V tIVSLE tSLIXE VIH VIL tF VIL SCK VIH SOT SIN VIH VIL 39 MB90960 Series • Bit setting: ESCR0/1:SCES = 0, ECCR0/1:SCDE = 1 (TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V) Parameter Serial clock cycle time SCK ↑ → SOT delay time Valid SIN → SCK ↓ SCK ↓ → Valid SIN hold time SOT → SCK ↓ delay time Symbol tSCYC tSHOVI tIVSLI tSLIXI tSOVLI Pin SCK0,SCK1 SCK0,SCK1 SOT0,SOT1 SCK0,SCK1 Internal clock operation SIN0,SIN1 output pins are SCK0,SCK1 CL = 80 pF + 1 TTL. SIN0,SIN1 SCK0,SCK1 SOT0,SOT1 Condition Value Min 5 tCP −50 tCP + 80 0 3 tCP − 70 Max ⎯ +50 ⎯ ⎯ ⎯ Unit ns ns ns ns ns * : If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations. Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock Timing” rating for tCP. tSCYC SCK tSOVLI 2.4 V 0.8 V tSHOVI 2.4 V 0.8 V tIVSLI tSLIXI VIH VIL 0.8 V SOT 2.4 V 0.8 V SIN VIH VIL • Bit setting: ESCR0/1:SCES = 1, ECCR0/1:SCDE = 1 (TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V) Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → Valid SIN hold time SOT → SCK ↑ delay time Symbol tSCYC tSLOVI tIVSHI tSHIXI tSOVHI Pin SCK0,SCK1 SCK0,SCK1 SOT0,SOT1 SCK0,SCK1 Internal clock operation SIN0,SIN1 output pins are SCK0,SCK1 CL = 80 pF + 1 TTL. SIN0,SIN1 SCK0,SCK1 SOT0,SOT1 Condition Value Min 5 tCP −50 tCP + 80 0 3 tCP − 70 Max ⎯ +50 ⎯ ⎯ ⎯ Unit ns ns ns ns ns * : If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations. 40 MB90960 Series Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock Timing” rating for tCP. tSCYC SCK tSOVHI 2.4 V 0.8 V tSLOVI 2.4 V SOT 2.4 V 0.8 V tIVSHI tSHIXI 2.4 V 0.8 V SIN VIH VIL VIH VIL (5) Trigger Input Timing (TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V) Value Pin Condition Unit Min Max INT8, INT9R INT10, INT11 INT12R, INT13 INT14R, INT15R ADTG ⎯ ⎯ ⎯ ⎯ Parameter Symbol Input pulse width tTRGH tTRGL 200 ns tCP + 200 ns * : If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations. Note : tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”. INT8, INT9R INT10, INT11 INT12R, INT13 INT14R, INT15R ADTG VIH VIH VIL tTRGH tTRGL VIL 41 MB90960 Series (6) Timer Related Resource Input Timing (TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V) Value Parameter Symbol Pin Condition Unit Min Max Input pulse width tTIWH tTIWL TIN2, TIN3 IN0 to IN3 ⎯ 4 tCP ⎯ ns * : If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations. Note : tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”. VIH VIH VIL tTIWH tTIWL VIL TIN2, TIN3 IN0 to IN3 (7) Timer Related Resource Output Timing (TA = –40°C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V) Value Parameter Symbol Pin Condition Unit Min Max CLK ↑ → TOUT change time tTO TOT2, TOT3 PPGC to PPGF ⎯ 30 ⎯ ns * : If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations. CLK 2.4 V TOT2, TOT3 PPGC to PPGF 2.4 V 0.8 V tTO 42 MB90960 Series 5. A/D Converter (TA = −40 °C to +125 °C*1, 3.0 V ≤ AVR − AVSS, VCC = AVCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Parameter Resolution Total error Nonlinearity error Differential nonlinearity error Zero reading voltage Full scale reading voltage Compare time Sampling time Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Offset between input channels Symbol ⎯ ⎯ ⎯ ⎯ VOT VFST ⎯ ⎯ IAIN VAIN ⎯ IA IAH IR IRH ⎯ Pin ⎯ ⎯ ⎯ ⎯ Value Min ⎯ ⎯ ⎯ ⎯ Typ ⎯ ⎯ ⎯ ⎯ Max 10 ±3.0 ±2.5 ±1.9 Unit bit LSB LSB LSB Remarks AN0 to AN15 AVSS − 1.5 AVSS + 0.5 AVSS + 2.5 LSB AN0 to AN15 AVR − 3.5 AVR − 1.5 AVR + 0.5 LSB ⎯ ⎯ AN0 to AN15 AN0 to AN15 AVR AVCC AVCC AVR AVR AN0 to AN15 1.0 2.0 0.5 1.2 −0.3 AVSS AVSS + 2.7 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 3.5 ⎯ 600 ⎯ ⎯ 16500 µs µs µA V V mA µA µA µA LSB *2 *2 4.5 V ≤ AVCC ≤ 5.5 V 4.0 V ≤ AVCC < 4.5 V 4.5 V ≤ AVCC ≤ 5.5 V 4.0 V ≤ AVCC < 4.5 V ∞ +0.3 AVR AVCC 7.5 5 900 5 4 *1 : If used exceeding TA = + 105 °C, please contact Fujitsu for reliability limitations. *2 : If A/D converter is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVR = 5.0 V) . (Continued) 43 MB90960 Series • About the external impedance of analog input and its sampling time • A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage changed to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. • Analog input circuit model R Analog input C Comparator During sampling : ON Part number MB90F962(S) MB90V340E-101/V340-102 Analog input 4.5 V ≤ AVCC ≤ 5.5 V 4.0 V ≤ AVCC < 4.5 V 4.5 V ≤ AVCC ≤ 5.5 V 4.0 V ≤ AVCC < 4.5 V R 2.0 kΩ (Max) 8.2 kΩ (Max) 2.0 kΩ (Max) 8.2 kΩ (Max) C 16.0 pF (Max) 16.0 pF (Max) 14.4 pF (Max) 14.4 pF (Max) Note : The values are reference values. Use the device with external circuits of the following output impedance for analog inputs: • Recommended output impedance of external circuits are : Approx. 1.5 kΩ or lower (4.0 V ≤ AVCC ≤ 5.5 V, sampling period = 0.5 µs) • If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors an on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high as internal capacitor. • If the output impedance of an external circuit is too high, the sampling period for the analog voltage may be insufficient. • If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. • To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. (Continued) 44 MB90960 Series (Continued) • The relationship between external impedance and minimum sampling time • At 4.5 V ≤ AVCC ≤ 5.5 V (External impedance = 0 kΩ to 100 kΩ) 100 MB90V340E-101/V340-102 (External impedance = 0 kΩ to 20 kΩ) 20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 MB90V340E-101/V340-102 External impedance [kΩ] External impedance [kΩ] 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 MB90F962(S) MB90F962(S) Minimum sampling time [µs] • At 4.0 V ≤ AVCC < 4.5 V (External impedance = 0 kΩ to 100 kΩ) 100 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 MB90V340E-101/V340-102 Minimum sampling time [µs] (External impedance = 0 kΩ to 20 kΩ) 20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 MB90V340E-101/V340-102 External impedance [kΩ] External impedance [kΩ] MB90F962(S) MB90F962(S) Minimum sampling time [µs] Minimum sampling time [µs] • About errors As | AVR − AVSS | becomes smaller, values of relative errors grow larger. 45 MB90960 Series 6. Definition of A/D Converter Terms Resolution Non linearity error Differential linearity error Total error : Analog variation that is recognized by an A/D converter. : Deviation between a line across zero-transition line ( “00 0000 0000B” ← → “00 0000 0001B” ) and full-scale transition line ( “11 1111 1110B” ← → “11 1111 1111B” ) and actual conversion characteristics. : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. : Difference between an actual value and an theoretical value. A total error includes zero transition error, full-scale transition error, and linear error. Total error 3FFH 3FEH 3FDH Digital output {1 LSB × (N − 1) + 0.5 LSB} Actual conversion characteristics 1.5 LSB 004H 003H 002H 001H 0.5 LSB AVSS Analog input VNT (Actually-measured value) Actual conversion characteristics Ideal characteristics AVR Total error of digital output “N” = VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB AVR − AVSS 1 LSB (Ideal value) = [V] 1024 VOT (Ideal value) = AVSS + 0.5 LSB [V] VFST (Ideal value) = AVR − 1.5 LSB [V] [LSB] VNT : A voltage at which digital output transits from (N − 1) H to NH. (Continued) 46 MB90960 Series (Continued) Non linearity error 3FFH 3FEH 3FDH Digital output Actual conversion characteristics {1 LSB × (N − 1) + VOT } (N + 1)H VFST (actual measurement value) VNT (actual measurement value) Actual conversion characteristics Actual conversion characteristics Differential linearity error Ideal characteristics Digital output NH 004H 003H 002H (N − 1)H V (N + 1) T (actual measurement value) VNT (actual measurement value) Actual conversion characteristics AVR Analog input Ideal characteristics 001H VOT (actual measurement value) AVSS Analog input AVR (N − 2)H AVSS Non linearity error of digital output N = Differential linearity error of digital output N = 1 LSB = VNT − {1 LSB × (N − 1) + VOT} 1 LSB V (N+1) T − VNT 1 LSB VFST − VOT 1022 −1 LSB [LSB] [V] [LSB] VOT : Voltage at which digital output transits from “000H” to “001H.” VFST : Voltage at which digital output transits from “3FEH” to “3FFH.” 47 MB90960 Series 7. Flash Memory Program/Erase Characteristics Parameter Sector erase time (60 Kbytes) Sector erase time (4 Kbytes) Byte programming time Machine clock frequency fCP at Flash programming/erasing Program/Erase cycle Flash memory data retention time VCC = 5.0 V ⎯ Average TA = +85 °C TA = +25 °C VCC = 5.0 V Conditions Value Min ⎯ ⎯ ⎯ ⎯ 10000 20 Typ 1 0.2 21 ⎯ ⎯ ⎯ Max 15 0.5 6100 24 ⎯ ⎯ Unit s s μs MHz cycle year * Remarks Excludes programming prior to erasure Excludes programming prior to erasure Except for the overhead time of the system level * : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at +85 °C) . 48 MB90960 Series ■ ORDERING INFORMATION Part number MB90F962PMT MB90F962SPMT MB90V340E-101 MB90V340E-102 Package 48-pin plastic LQFP FPT-48P-M26 7 mm ❑, 0.50 mm pitch 299-pin ceramic PGA PGA-299C-A01 Remarks Flash Memory Product (64Kbytes) Evaluation product 49 MB90960 Series ■ PACKAGE DIMENSION 48-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.50 mm 7 × 7 mm Gullwing Plastic mold 1.70 mm MAX 0.17 g P-LFQFP48-7×7-0.50 (FPT-48P-M26) Code (Reference) 48-pin plastic LQFP (FPT-48P-M26) Note 1) * : These dimensions include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 9.00±0.20(.354±.008)SQ * 7.00 –0.10 .276 –.004 SQ 36 25 +0.40 +.016 0.145±0.055 (.006±.002) 37 24 0.08(.003) INDEX Details of "A" part 1.50 –0.10 .059 –.004 +0.20 +.008 (Mounting height) 48 13 "A" 0˚~8˚ LEAD No. 0.50(.020) 1 12 0.10±0.10 (.004±.004) (Stand off) 0.20±0.05 (.008±.002) 0.08(.003) M 0.25(.010) 0.60±0.15 (.024±.006) C 2003 FUJITSU LIMITED F48040S-c-2-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 50 MB90960 Series The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. 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Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept. F0703