FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16305-3E
32-bit RISC Microcontroller
CMOS
FR30 Series
MB91107/108
s DESCRIPTION
The MB91107 is a standard single-chip microcontroller constructed around the 32-bit RISC CPU (FR* family) core with abundant I/O resources and bus control functions optimized for high-performance/high-speed CPU processing for embedded controller applications. To support the vast memory space accessed by the 32-bit CPU, the MB91107 normally operates in the external bus access mode and executes instructions on the internal 1 Kbyte cache memory and RAM (MB91107: 128 Kbytes, MB91108: 160 Kbytes) for enhanced performance. The MB91107 is optimized for applications requiring high-performance CPU processing such as navigation systems, high-performance FAXs and printer controllers. *: FR Family stands for FUJITSU RISC controller.
s FEATURES
FR CPU • • • • • 32-bit RISC, load/store architecture, 5-stage pipeline Operating clock frequency: Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz) General purpose registers: 32 bits × 16 16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle Memory to memory transfer, bit processing, barrel shifter processing: Optimized for embedded applications (Continued) 120-pin Plastic LQFP
s PACKAGE
(FPT-120P-M21)
MB91107/108
• Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems supporting high level languages • Register interlock functions, efficient assembly language coding • Branch instructions with delay slots: Reduced overhead time in branch executions • Internal multiplier/supported at instruction level Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles • Interrupt (push PC and PS): 6 cycles, 16 priority levels Bus interface • • • • • • Clock doubler: Internal 50 MHz, external bus 25 MHz operation 25-bit address bus (32 Mbytes memory space) 8/16-bit data bus Basic external bus cycle: 2 clock cycles Chip select outputs for setting down to a minimum memory block size of 64 Kbytes: 8 Interface supported for various memory technologies DRAM interface (area 4 and 5) • Automatic wait cycle insertion: Flexible setting, from 0 to 7 for each area • Unused data/address pins can be configured us input/output ports • Little endian mode supported (Select 1 area from area 1 to 5) DRAM interface • • • • • 2 banks independent control (area 4 and 5) Double CAS DRAM (normal DRAM I/F) / Single CAS DRAM / Hyper DRAM Basic bus cycle: Normally 5 cycles, 2-cycle access possible in high-speed page mode Programmable waveform: Automatic 1-cycle wait insertion to RAS and CAS cycles DRAM refresh CBR refresh (interval time configurable by 6-bit timer) Self-refresh mode • Supports 8/9/10/12-bit column address width • 2CAS/1WE, 2WE/1CAS selective Cache memory • • • • • • • • • • • • • • • • • 1-Kbyte instruction cache memory 2 way set associative 32 block/way, 4 entry(4 word)/block Lock function: For specific program code to be resident in cache memory 8 channels Transfer incident/external pins/internal resource interrupt requests Transfer sequence: Step transfer/block transfer/burst transfer/continuous transfer Transfer data length: 8 bits/16 bits/32 bits selective NMI/interrupt request enables temporary stop operation 3 independent channels Full-duplex double buffer Data length: 7 bits to 9 bits (non-parity), 6 bits to 8 bits (parity) Asynchronous (start-stop system), CLK-synchronized communication selective Multi-processor mode Internal 16-bit timer (U-TIMER) operating as a proprietary baud rate generator: Generates any given baud rate Use external clock can be used as a transfer clock Error detection: Parity, frame, overrun (Continued)
DMAC (DMA controller)
UART
2
MB91107/108
(Continued)
10-bit A/D converter (successive approximation conversion type) • • • • • 10-bit resolution, 4 channels Successive approximation type: Conversion time of 5.6 µs at 25 MHz Internal sample and hold circuit Conversion mode: Single conversion/scanning conversion/repeated conversion selective Start: Software/external trigger/internal timer selective
16-bit reload timer • 16-bit timer: 3 channels • Internal clock: 2 clock cycle resolution, divide by 2/8/32 selective Other interval timers • 16-bit timer: 3 channels (U-TIMER) • PWM timer: 4 channels • Watchdog timer: 1 channel Bit search module First bit transition “1” or “0” from MSB can be detected in 1 cycle Interrupt controller • External interrupt input: Non-maskable interrupt (NMI), normal interrupt 8 (INT0 to INT7) • Internal interrupt incident:UART, DMA controller (DMAC), A/D converter, U-TIMER and delayed interrupt module • Priority levels of interrupts are programmable except for non-maskable interrupt (in 16 levels) Others • Reset cause: Power-on reset/hardware standby/watchdog timer/software reset/external reset • Low-power consumption mode: Sleep mode/stop mode • Clock control Gear function:Operating clocks for CPU and peripherals are independently selective Gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16) However, operating frequency for peripherals is less than 25 MHz. • Packages: LQFP-120 • CMOS technology (0.35 µm): MB91V108 (0.25 µm) ••••• Development model MB91107 (0.25 µm) ••••• Production model MB91108 (0.25 µm) ••••• Production model • Power supply voltage: 3.3 V ± 0.3 V (internal regulator)
3
MB91107/108
s PIN ASSIGNMENT
(TOP VIEW)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
RAS1/PB4 DW0/PB3 CS0H/PB2 CS0L/PB1 RAS0/PB0 VCC X0 X1 VSS PI1/EOP2/ATG PI0/DACK2 PE7/DREQ2 PE6/EOP1 PE5/DACK1 PE4/DREQ1 PE3/EOP0 PE2/DACK0 PE1/DREQ0 PE0/SC2 PF7/SO2 PF6/SI2 PF5/SC1 PF4/SO1 PF3/SI1 PF2/SC0 PF1/SO0 VSS PF0/SI0 PG7/INT7 PG6/INT6
4
P26/D22 P27/D23 D24 D25 D26 D27 D28 D29 D30 D31 VSS A00 A01 A02 A03 A04 A05 A06 A07 VCC A08 A09 A10 A11 A12 A13 A14 A15 VSS P60/A16
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
PB5/CS1L PB6/CS1H PB7/DW1 C CS0 PA1/CS1 PA2/CS2 PA3/CS3 PA4/CS4 PA5/CS5 PA6/CLK NMI HST RST VSS MD0 MD1 MD2 P80/RDY P81/BGRNT P82/BRQ RD WR0 P85/WR1 P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
PG5/INT5 PG4/INT4 PG3/INT3 PG2/INT2 PG1/INT1 PG0/INT0 VCC PH7/OCPA3 PH6/OCPA2 PH5/OCPA1 PH4/OCPA0 PH3/TRG3/CS7 PH2/TRG2/CS6 PH1/TRG1 PH0/TRG0 AN3 AN2 AN1 AN0 AVSS/AVRL AVRH AVCC A24/P70 A23/P67 A22/P66 A21/P65 A20/P64 A19/P63 A18/P62 A17/P61
(FPT-120P-M21)
MB91107/108
s PIN DESCRIPTION
Pin no. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 102 103 104 105 106 107 108 109 111 112 113 114 115 116 117 118 120 1 2 3 4 5 6 7 8 Pin name D16/P20 D17/P21 D18/P22 D19/P23 D20/P24 D21/P25 D22/P26 D23/P27 D24 D25 D26 D27 D28 D29 D30 D31 A00 A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16/P60 A17/P61 A18/P62 A19/P63 A20/P64 A21/P65 A22/P66 A23/P67 A24/P70 Circuit type Function
C
Bit 16 to bit 23 of external data bus. Can be configured as ports (P20 to P27) when external data bus width is set to 8-bit.
C
Bit 24 to bit 31 of external data bus.
F
Bit 00 to bit 15 of external address bus.
F
Bit 16 to bit 23 of external address bus. Can be configured as ports(P60 to P67) when not used as address bus.
F
Bit 24 of external address bus. Can be configured as a port(P70) when not used as address bus. External ready input. Inputs “0” when bus cycle is being executed and not completed. Can be configured as a port when this pin is not used.
79
RDY/P80
C
(Continued)
5
MB91107/108
Pin no.
Pin name
Circuit type F
Function External bus release acknowledge output. Outputs “L” level when external bus is released. Can be configured as a port when this pin is not used. External bus release request input. Inputs “1” when release of external bus is required. Can be configured as a port when this pin is not used. Read strobe output pin for external bus. Write strobe output pin for external bus. Relation between control signals and effective byte locations is as follows: 16-bit bus width D31 to D24 WR0 WR1 8-bit bus width WR0 (I/O port enabled)
80
BGRNT/P81
81 82
BRQ/P82 RD
P M
83
WR0
M
84
WR1/P85
F
D23 to D16
Note: WR1 is Hi-Z during resetting. Attach an external pull-up resister when using at 16-bit bus width. 65 66 67 68 69 70 CS0 CS1/PA1 CS2/PA2 CS3/PA3 CS4/PA4 CS5/PA5 M Chip select 0 output (“L” active). Chip select 1 output (“L” active). Chip select 2 output (“L” active). Chip select 3 output (“L” active). Chip select 4 output (“L” active). Chip select 5 output (“L” active). Can be configured as ports when PA1 to PA5 are not used. System clock output. Outputs clock signal of external bus operating frequency. Can be configured as a port when PA6 is not used. RAS output for DRAM bank 0. CASL output for DRAM bank 0. CASH output for DRAM bank 0. Refer to the WE output for DRAM bank 0 (“L” active). DRAM interface RAS output for DRAM bank 1. for details. CASL output for DRAM bank 1. CASH output for DRAM bank 1. WE output for DRAM bank 1 (“L” active) Can be configured as a port when PB0 to PB7 are not used. Mode pins 0 to 2. MCU basic operation mode is set by these pins. Directly connect these pins with VCC or VSS for use. Clock (oscillator) output. Clock (oscillator) input. External reset input. Hardware standby input (“L” active).
F
71
CLK/PA6
F
56 57 58 59 60 61 62 63 76 77 78 53 54 74 73
RAS0/PB0 CS0L/PB1 CS0H/PB2 DW0/PB3 RAS1/PB4 CS1L/PB5 CS1H/PB6 DW1/PB7 MD0 MD1 MD2 X1 X0 RST HST
F
G
A B H
(Continued)
6
MB91107/108
Pin no. 72
Pin name NMI
Circuit type H
Function NMI (non-maskable interrupt pin) input (“L” active). (SC2) Clock I/O pin for UART2. Clock output is available when clock output of UART2 is enabled. (PE0) General purpose I/O port. This function is available when UART2 clock output is disabled. (DREQ0) External transfer request input pins for DMA. This pin is used for input when external trigger is selected to cause DMAC operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. (PE1) General purpose I/O port. (DACK0) External transfer request acknowledge output pin for DMAC (ch. 0). This function is available when transfer request output for DMAC is enabled. (PE2) General purpose I/O port. This function is available when transfer request acknowledge output for DMAC or DACK0 output is disabled. (EOP0) Can be configured as DMAC EOP OUTPUT (ch.0) when DMAC EOP output is enable. (PE3) General purpose I/O port. (DREQ1) External transfer request input pins for DMA. This pin is used for input when external trigger is selected to cause DMAC operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. (PE4) General purpose I/O port. (DACK1) External transfer request acknowledge output pin for DMAC (ch. 1). This function is available when transfer request output for DMAC is enabled. (PE5) General purpose I/O port. This function is available when transfer request acknowledge output for DMAC or DACK1 output is disabled. (EOP1) Can be configured as DMAC EOP OUTPUT (ch.1) when DMAC EOP output is enable. (PE6) General purpose I/O port. (DREQ2) External transfer request input pins for DMA. This pin is used for input when external trigger is selected to cause DMAC operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. (PE7) General purpose I/O port.
42
SC2/PE0
F
43
DREQ0/PE1
F
44
DACK0/PE2
F
45
EOP0/PE3
F
46
DREQ1/PE4
F
47
DACK1/PE5
F
48
EOP1/PE6
F
49
DREQ2/PE7
F
(Continued)
7
MB91107/108
Circuit type
Pin no.
Pin name
Function (SI0) UART0 data input pin. This pin is used for input during UART0 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. (PF0) General purpose I/O port. (SO0) UART0 data output pin. This function is available when UART0 data output is enabled. (PF1) General purpose I/O port. This function is available when UART0 data output is disabled. (SC0) UART0 clock I/O pin. Clock output is available when UART0 clock output is enabled. (PF2) General purpose I/O port. This function is available when UART0 clock output is disabled. (SI1) UART1 data input pin. This pin is used for input during UART1 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. (PF3) General purpose I/O port. (SO1) UART1 data output pin. This function is available when UART1 data output is enabled. (PF4) General purpose I/O port. This function is available when UART1 data output is disabled. (SC1) Clock I/O pin for UART1. Clock output is available when clock output of UART1 is enabled. (PF5) General purpose I/O port. This function is available when UART1 clock output is disabled. (SI2) UART2 data input pin. This pin is used for input during UART2 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. (PF6) General purpose I/O port. (SO2) UART2 data output pin. This function is available when UART2 data output is enabled. (PF7) General purpose I/O port. This function is available when UART2 data output is disabled. (Continued)
33
SI0/PF0
F
35
SO0/PF1
F
36
SC0/PF2
F
37
SI1/PF3
F
38
SO1/PF4
F
39
SC1/PF5
F
40
SI2/PF6
F
41
SO2/PF7
F
8
MB91107/108
Pin no. 25 26 27 28 29 30 31 32 16 17
Pin name INT0/PG0 INT1/PG1 INT2/PG2 INT3/PG3 INT4/PG4 INT5/PG5 INT6/PG6 INT7/PG7 TRG0/PH0 TRG1/PH1
Circuit type
Function (INT0 to INT7) External interrupt request input pin. This pin is used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. (PG0 and PG7) General purpose I/O port. (TRG0 and TRG1) PWM timer external trigger input pin. This function is available when PH0 and PH1 data outputs are disabled. (PH0 and PH1) General purpose I/O port. (TRG2 and TRG3) PWM timer external trigger input pin. This function is available when PH2 and PH3 data outputs are disabled.
I
F
18 19
TRG2/PH2/ CS6 TRG3/PH3/ CS7 OCPA0/PH4 OCPA1/PH5 OCPA2/PH6 OCPA3/PH7
F
(PH2 and PH3) Can be configured as a I/O port when TRG2, TRG3, CS6 and CS7 are not used. Chip select 6 output (“L” active). Chip select 7 output (“L” active). (OCPA0 to OCPA3) PWM timer output pin. This function is available when PWM timer output is enabled. (PH4 to PH7) General purpose I/O port. (DACK2) External transfer request acknowledge output pin for DMAC (ch. 2). This function is available when transfer request output for DMAC is enabled. (PI0) General purpose I/O port. This function is available when transfer request acknowledge output for DMAC or DACK2 output is disabled. (EOP2) EOP output pin for DMAC (ch.1). This function is available when EOP output for DMAC is enabled. (PI1) General purpose I/O port. This function is available when transfer complete acknowledge output for DMAC output is disabled. (ATG)External trigger input pin for A/D converter. This pin is used for input when external trigger is selected to cause A/D converter operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally.
20 21 22 23
F
50
DACK2/PI0
F
51
EOP2/PI1/ ATG
F
12 to 15 9 10
AN0 to AN3 AVCC AVRH
N
(AN0 to AN3) Analog input pins of A/D converter. This function is available when AIC register is set to specify analog input mode. Power supply pin (VCC) for A/D converter. Reference voltage input (high) for A/D converter. Make sure to turn on and off this pin with potential of AVRH or more applied to VCC.
(Continued)
9
MB91107/108
(Continued)
Pin no. 11 24, 55, 110 64 34, 52, 75, 101, 119 Pin name AVSS/ AVRL VCC C VSS Circuit type Function Power supply pin (VSS) for A/D converter and reference voltage input pin (low). Power supply pin (VCC) for digital circuit. Always three pins must be connected to the power supply Bypass capacitor pin for internal capacitor. Refer to the HANDLING DEVICES. Earth level (VSS) for digital circuit.
Note : In most of the above pins, I/O port and resource I/O are multiplexed e.g. xxx/Pxxx. In case of conflict between output of I/O port and resource I/O, priority is always given to the output of resource I/O.
s DRAM CONTROL REGISTER
Pin name RAS0 RAS1 CS0L CS0H CS1L CS1H DW0 DW1 Data bus 16-bit mode 2CAS/1WR mode 1CAS/2WR mode Area 4 RAS Area 5 RAS Area 4 CASL Area 4 CASH Area 5 CASL Area 5 CASH Area 4 WE Area 5 WE Area 4 RAS Area 5 RAS Area 4 CAS Area 4 WEL Area 5 CAS Area 5 WEL Area 4 WEL Area 5 WEL Data bus 8-bit mode Area 4 RAS Area 5 RAS Area 4 CAS Area 4 CAS Area 5 CAS Area 5 CAS Area 4 WE Area 5 WE Remarks Correspondence of “L” “H” to lower address 1 bit (A0) in data bus 16-bit mode. “L”: “0” “H”: “1” CASL : CAS which A0 corresponds to “0” area CASH : CAS which A0 corresponds to “1” area WEL : WE which A0 corresponds to “0” area WEH : WE which A0 corresponds to “1”
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MB91107/108
s I/O CIRCUIT TYPE
Type
X1
Circuit
Remarks • Oscillation feedback resistance: 1 MΩ approx. Clock input
X0
A
STANDBY CONTROL
VCC
P-channel type Tr. B Diffused resistor
VSS
• CMOS level Hysteresis input Without standby control • With pull-up resistance
N-channel type Tr.
Digital input • CMOS level I/O With standby control
Digital output Digital output C Digital input
STANDBY CONTROL
• Analog input
N Analog input
(Continued)
11
MB91107/108
Type
Circuit
Remarks • CMOS level output • CMOS level Hysteresis input With standby control
Digital output Digital output F Digital input
STANDBY CONTROL
• CMOS level input Without standby control
G
Digital input • CMOS level Hysteresis input Without standby control H
Digital input • CMOS level output • CMOS level Hysteresis input Without standby control
Digital output I Digital output Digital input
(Continued)
12
MB91107/108
(Continued)
Type Circuit Remarks • CMOS level output Digital output M Digital output
Digital output Digital output P Pull-down resistor control Digital input
STANDBY CONTROL
• CMOS level output • CMOS level input With standby control • With pull-down resistance
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MB91107/108
s HANDLING DEVICES
1. Preventing Latchup
In CMOS ICs, applying voltage higher than VCC or lower than VSS to input/output pin or applying voltage over rating across VCC and VSS may cause latchup. This phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the device. Make sure to prevent the voltage from exceeding the maximum rating.
2. Treatment of Pins
•Treatment of unused pins Unused pins left open may cause malfunctions. Make sure to connect them to pull-up or pull-down resistors. •Handling the output pins Connecting an output pin to the power supply, to another output pin, or to a large-capacitance load may cause a large current to flow. Since letting it flow for an extended period of time degrades the device, be careful in using the device not to exceed the maximum rating. •Power supply pins When there are several VCC and VSS pins, each of them is equipotentially connected to its counterpart inside of the device, minimizing the risk of malfunctions such as latch up. To further reduce the risk of malfunctions, to prevent EMI radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and to observe the total output current standard, connect all VCC and VSS pins to the power supply or GND. It is preferred to connect VCC and VSS of MB91107 to power supply with minimal impedance possible. It is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1 µF between VCC and VSS at a position as close as possible to MB91107. •Mode setting pins (MD0 to MD2) Connect mode setting pins (MD0 to MD2) directly to VCC or VSS. Arrange each mode setting pin and VCC or VSS patterns on the printed circuit board as close as possible and make the impedance between them minimal to prevent mistaken entrance to the test mode caused by noises. •Crystal oscillator circuit Noises around X0 and X1 pins may cause malfunctions of MB91101. In designing the PC board, layout X0, X1 and crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as close as possible. It is strongly recommended to design PC board so that X1 and X0 pins are surrounded by grounding area for stable operation.
3. Notes on Use
•External reset input The RST pin requires "L" level input for at least five machine cycles before the the internal circuitry can be completely reset. •External clock To use an external clock, in principle, supply the X0 and X1 pins with a clock signal opposite in phase to the X0. To use the STOP mode (oscillation stop mode) along with the external clock, in which the X1 pin stops with "H" output, you should insert an external resistor of about 1 kilohm to prevent a collision between outputs. Given the next page is an example of using an external clock.
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MB91107/108
•Using an external clock (for normal use)
X0 X1
MB91108 MB91107
Note: To use the STOP mode (oscillation stop mode), insert a resistor to the X1 pin.
4. Notes on Internal DC-DC Regulator
• Since this product contains a regulator, be sure to supply current at 3.3 V to the VCC pin and insert a bypass capacitor of about 0.1 µF to the C pin for the regulator. • The A/D converter requires a 3.3-V power supply separately.
•Connecting to power supply
3.3 V VCC AVCC AVRH AVSS GND VSS C
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MB91107/108
• Notes on using the STOP mode The regulator built in this product stops in the STOP mode. If the regulator stops due to a malfunction caused by noise or a fault in the power supply during normal operation, the internal 2.5-V power supply may go below the lower limit of the guaranteed operating voltage range. When using the STOP mode with the internal regulator, therefore, be sure to supply an auxiliary external power to prevent the 3.3-V power supply from coming down. Even in that case, the internal regulator can be restarted by input of a reset signal (To restart the regulator, keep the reset pin at the L level for at least the oscillation settling time).
•Using STOP mode with 3.3 V power supply
3.3 V
VCC C 0.1 µF VSS
2.4 kΩ
7.6 kΩ
5. Turning on the Power Supply
•RST pin When turning on the power supply, never fail to start from setting the RST pin to “L” level. And after the power supply voltage goes to VCC level, at least after ensuring the time for 5 machine cycles, then set to “H” level. •Pin Condition at Turning on the Power Supply The pin condition at turning on the power supply is unstable. The circuit starts being initialized after turning on the power supply and then starting oscillation and then the operation of the internal regulator becomes stable. So it takes about 42 ms for the pin to be initialized from the oscillation starting at the source oscillation 12.5 MHz. Take care that the pin condition may be output condition at initial unstable condition. (With the MB91107, however, initalization can be achieved in less than about 42 ms after turning on the internal power supply by maintaining the RST pin at "L" level.) •Source Oscillation Input at Turning on the Power Supply At turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing waiting. •Hardware Stand-by at Turning on the Power Supply When turning on the power supply with the HST pin being set to “L” level, the hardware doesn’t stand by. However the HST pin becomes available after the reset cancellation, the HST pin must once be back to “H” level. •Power on Reset Make sure to make power on reset at turning on the power supply or returning on the power supply when the power supply voltage is below the warranty range for normal operation.
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MB91107/108
s BLOCK DIAGRAM
FR CPU
I-bus
Instruction Cache 1 KB
Bit Search Module
(16 bit)
Harvard Princeton
D-bus (32 bit) DMAC (8 ch) DREQ0 DREQ1 DREQ2 DACK0 DACK1 DACK2 EOP0 EOP1 EOP2
Bus Converter
Bus Controller 32 bit 16 bit Bus Converter C-bus RAM 128 KB (MB91107) RAM 160 KB (MB91108)
D31 ∼ D16 A24 ∼ A00 RD WR0 ∼ WR1 RDY CLK CS0 ∼ CS7 BRQ BGRNT
X0 X1 RST HST
Clock Control Unit (Watch Dog Timer)
DRAM Controller INT0 ∼ INT7 NMI Interrupt Control Unit (32 bit) AN0 ∼ AN3 AVCC AVRH AVSS AVRL ATG 10 bit A/D Converter (4 ch) Port 0 ∼ Port B
RAS0 CS0L CS0H DW0
RAS1 CS1L CS1H DW1
Reload Timer (3 ch)
R-bus (16 bit)
UART (3 ch) with Baud Rate Timer
SI0 SI1 SI2 SO0 SO1 SO2 SC0 SC1 SC2
Port
PWM Timer (4 ch)
OCPA0 ∼ OCPA3 TRG0 ∼ TRG3
Note: Pins are display for functions (Actually some pins are multiplexer). When using REALOS, time control should be done by using external interrupt or inner timer.
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MB91107/108
s CPU CORE
1. Memory Space
The FR family has a logical address space of 4 Gbytes (232 bytes) and the CPU linearly accesses the memory space.
External ROM/external bus mode
0000 0000H I/O 0000 0400H I/O 0000 0800H
Internal ROM/external bus mode
I/O
Direct addressing area*1 See “s I/O MAP”
I/O
Access inhibited
0001 0000H
Access inhibited External area Internal RAM ←Internal 128 KB-RAM
External area
000C 0000H 000E 0000H 000E 8000H 0010 0000H
External area
Internal RAM ←Internal 32KB-RAM *2 (MB91108 only) Access inhibited
External area
External area
FFFF FFFFH
*1: The following areas on the memory space are assigned to direct addressing area for
I/O. In these areas, an address can be specified in a direct operand of a code. Direct areas consists of the following areas dependent on accessible data sizes. → byte data access 0-0FFH → half word data access 0-1FFH → word data access 0-3FFH
*2: Access inhibited of MB91107
Note : Only the above mode exist in this product.
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MB91107/108
2. Registers
The FR family has two types of registers; dedicated registers embedded on the CPU and general-purpose registers on memory. •Dedicated registers Program counter (PC) Program status (PS) : 32-bit length, indicates the location of the instruction to be executed. : 32-bit length, register for storing register pointer or condition codes. : Holds top address of vector table used in EIT (Exceptional/Interrupt/ Table base register (TBR) Trap processing. Return pointer (RP) : Holds address to resume operation after returning from a subroutine. System stack pointer (SSP) : Indicates system stack space. User's stack pointer (USP) : Indicates user’s stack space. Multiplication/division result : 32-bit length, register for multiplication/division. register (MDH/MDL)
32 bit Program counter Program status Table base register Return pointer System stack pointer User’s stack pointer Multiplication/division result register PC PS TBR RP SSP USP MDH MDL ILM
32 bit
Initial value XXXX XXXX Indeterminate
SCR CCR 0 0 0F FC 0 0 XXXX XXXX Indeterminate 0000 0000 XXXX XXXX Indeterminate XXXX XXXX Indeterminate XXXX XXXX Indeterminate
•Program status (PS) The PS register is for holding program status and consists of a condition code register (CCR), a system condition code register (SCR) and a interrupt level mask register (ILM).
31 PS
20
19
18
17
16
10
9
8 T
7
6
5 S
4 I
3 N
2 Z
1 V
0 C
ILM4 to ILM0
D1 D0
ILM
SCR
CCR
19
MB91107/108
•Condition code register (CCR) S-flag : Specifies a stack pointer used as R15. I-flag : Controls user interrupt request enable/disable. N-flag : Indicates sign bit when division result is assumed to be in the 2’s complement format. Z-flag : Indicates whether or not the result of division was “0”. : Assumes the operand used in calculation in the 2’s complement format and indicates whether or V-flag not overflow has occurred. C-flag : Indicates if a carry or borrow from the MSB has occurred. •System condition code register (SCR) T-flag : Specifies whether or not to enable step trace trap. •Interrupt level mask register (ILM) ILM4 to ILM0 : Register for holding interrupt level mask value. The value held by this register is used as a level mask. When an interrupt request issued to the CPU is higher than the level held by ILM, the interrupt request is accepted. ILM4 0 0 1 ILM3 0 1 1 ILM2 0 1 1 ILM1 0 1 1 ILM0 0 1 1 Interrupt level 0 15 31 Low High-low High
20
MB91107/108
s GENERAL-PURPOSE REGISTERS
R0 to R15 are general-purpose registers embedded on the CPU. These registers functions as an accumulator and a memory access pointer.
32 bit R0 R1 : R12 R13 R14 R15 :
AC FP SP
Initial value XXXX XXXXH : : : : : : XXXX XXXXH 00 0 0 0 0 0 0 H
Of the above 16 registers, following registers have special functions. To support the special functions, part of the instruction set has been sophisticated to have enhanced functions. R13: Virtual accumulator (AC) R14: Frame pointer (FP) R15: Stack pointer (SP) Upon reset, values in R0 to R14 are not fixed. Value in R15 is initialized to be 0000 0000H (SSP value).
21
MB91107/108
s SETTING MODE
1. Pin
•Mode setting pins and modes Mode setting pins MD2 0 0 0 0 1 MD1 0 0 1 1 — MD0 0 1 0 1 — Mode name External vector mode 0 External vector mode 1 — Internal vector mode — Reset vector access area External External — Internal — External data bus width 8 bits 16 bits — (Mode register) — Bus mode
External ROM/external bus mode Inhibited Inhibited Inhibited
2. Registers
•Mode data
MODR Address : 0000 07FFH M1 M0
Initial value
Access W
∗
∗
∗
∗
∗
∗
XXXX XXXXB
Always write “0” except for M1 and M0.
•Bus mode setting bits and functions M1 0 0 1 1 M0 0 1 0 1 Single-chip mode Internal ROM/external bus mode External ROM/external bus mode — Inhibited Inhibited Functions Note
Note : MB91107 places 128-KB internal RAM in the internal ROM area. To use the 128-KB internal RAM, be sure to set ’01’.
Bus mode setting bit
22
MB91107/108
s I/O MAP
The remainder of this section contains a list of the registers for peripheral resources in memory space. Address 000001H 000004H 000005H 000008H 000009H 00000BH 000012H 000013H 000014H 000015H 000016H 00001CH 00001DH 00001EH 00001FH 000020H 000021H 000022H 000023H 000024H 000025H 000026H 000027H 000028H 000029H 00002AH 00002BH 00002EH 00002FH Register name PDR2 PDR7 PDR6 PDRB PDRA PDR8 PDRE PDRF PDRG PDRH PDRI SSR0 SIDR0/ SODR0 SCR0 SMR0 SSR1 SIDR1/ SODR1 SCR1 SMR1 SSR2 SIDR2/ SODR2 SCR2 SMR2 TMRLR0 TMR0 TMCSR0 Register name Port 2 data registe Port 7 data registe Port 6 data registe Port B data registe Port A data registe Port 8 data registe Port E data registe Port F data registe Port G data registe Port H data registe Port I data registe Serial status register 0 Serial input data register 0/ Serial output data register Serial control register 0 Serial mode register 0 Serial status register 1 Serial input data register 1/ Serial output data register Serial control register 1 Serial mode register 1 Serial status register 2 Serial input data register 2/ Serial output data register Serial control register 2 Serial mode register 2 16-bit reload register 0 16-bit timer register 0 16-bit reload timer control status register 0 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R R/W Reload Timer 0 UART2 UART1 UART0 Port Data Register Resource name Initial value XXXXXXXXB − − − − − − −XB XXXXXXXXB XXXXXXXXB −XXXXXX−B − −X− −XXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXX0B − − − − − −XXB 0 0 0 0 1 − 0 0B XXXXXXXXB 0 0 0 0 0 1 0 0B 0 0 − − 0 − 0 0B 0 0 0 0 1 − 0 0B XXXXXXXXB 0 0 0 0 0 1 0 0B 0 0 − − 0 − 0 0B 0 0 0 0 1 − 0 0B XXXXXXXXB 0 0 0 0 0 1 0 0B 0 0 − − 0 − 0 0B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB − − − − 0 0 0 0B 0 0 0 0 0 0 0 0B
Note : Do not execute an RMW-type instruction for any register containing a write-only bit.
(Continued)
23
MB91107/108
Register name TMRLR1 TMR1 TMCSR1 ADCR ADCS TMRLR2 TMR2 TMCSR2 ASR6 AMR6 ASR7 AMR7 CS67 UTIM0/ UTIMR0 UTIMC0
Address 000030H 000031H 000032H 000033H 000036H 000037H 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH 00003FH 000042H 000043H 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000059H 000078H 000079H 00007BH
Register name 16-bit reload register 1 16-bit timer register 1 16-bit reload timer control status register 1 A/D converter data register A/D converte control status register 16-bit reload register 2 16-bit timer register 2 16-bit reload timer control status register 2 Area select register 6 Area mask register 6 Area select register 7 Area mask register 7 Output enable U-TIMER register ch.0 U-TIMER reload register ch.0 U-TIMER control register ch.0
Access
W
Resource name
Initial value
XXXXXXXXB XXXXXXXXB
R
Reload Timer 1
XXXXXXXXB
XXXXXXXXB − − − − 0 0 0 0B 0 0 0 0 0 0 0 0B − − − − − − XXB
R/W R R/W W R R/W W W W W R/W R/W R/W U-TIMER 0 Reload Timer 2
A/D Converter (Successive approximation type)
XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB − − − − 0 0 0 0B 0 0 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
External Bus Interface 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B − − − − 0 0 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 − − 0 0 0 0 1B
Note : Do not execute an RMW-type instruction for any register containing a write-only bit.
(Continued)
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MB91107/108
Register name UTIM1/ UTIMR1 UTIMC1 UTIM2/ UTIMR2 UTIMC2 EIRR ENIR ELVR DDRE DDRF DDRG DDRH DDRI GCN1 GCN2 PTMR0 PCSR0 PDUT0 PCNH0 PCNL0 PTMR1 PCSR PDUT PCNH PCNL
Address 00007CH 00007DH 00007FH 000080H 000081H 000083H 000094H 000095H 000098H 000099H 0000D2H 0000D3H 0000D4H 0000D5H 0000D6H 0000DCH 0000DDH 0000DFH 0000E0H 0000E1H 0000E2H 0000E3H 0000E4H 0000E5H 0000E6H 0000E7H 0000E8H 0000E9H 0000EAH 0000EBH 0000ECH 0000EDH 0000EEH 0000EFH
Register name U-TIMER register ch.1 U-TIMER reload register ch.1 U-TIMER control register ch.1 U-TIMER register ch.2 U-TIMER reload register ch.2 U-TIMER control register ch.2 External interrup request register Interrupt enabble register External interrup request level setup register Port E data direction register Port F data direction register Port G data direction register Port H data direction register Port I data direction register General control register 1 General control register 2 PWM timer register 0 PWM cycle setting register 0 PWM duty setting register 0 Control status register H 0 Control status register L 0 PWM timer register 1 PWM cycle setting register 1 PWM duty setting register 1 Control status register H 1 Control status register L 1
Access R/W R/W R/W R/W R/W R/W R/W W W W W W R/W R/W R W W R/W R/W R W W R/W R/W
Resource name
Initial value 0 0 0 0 0 0 0 0B
U-TIMER 1
0 0 0 0 0 0 0 0B 0 − − 0 0 0 0 1B 0 0 0 0 0 0 0 0B
U-TIMER 2
0 0 0 0 0 0 0 0B 0 − − 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
External Interrupt/NMI
Port E-I Data Direction Register
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 1B − − − − − − 0 0B 0 0 1 1 0 0 1 0B 0 0 0 1 0 0 0 0B 0 0 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
PWM
0 0 0 0 0 0 0 −B 0 0 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 −B 0 0 0 0 0 0 0 0B
Note : Do not execute an RMW-type instruction for any register containing a write-only bit.
(Continued)
25
MB91107/108
Register name PTMR2 PCSR2 PDUT2 PCNH2 PCNL2 PTMR3 PCSR3 PDUT3 PCNH3 PCNL3
Address 0000F0H 0000F1H 0000F2H 0000F3H 0000F4H 0000F5H 0000F6H 0000F7H 0000F8H 0000F9H 0000FAH 0000FBH 0000FCH 0000FDH 0000FEH 0000FFH 000200H 000201H 000202H 000203H 000204H 000205H 000206H 000207H 000208H 000209H 00020AH 00020BH 0003E4H 0003E5H 0003E6H 0003E7H
Register name PWM timer register 2 PWM cycle setting register 2 PWM duty setting register 2 Control status register H 2 Control status register L 2 PWM timer register 3 PWM cycle setting register 3 PWM duty setting register 3 Control status register H 3 Control status register L 3
Access R W W R/W R/W R W W R/W R/W
Resource name
Initial value 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 −B 0 0 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 −B 0 0 0 0 0 0 0 0B XXXXXXXXB XXXXXXXXB XXXXXXXXB X 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB XX 0 0 0 0 0 0B XX 0 0 0 0 0 0B XX 0 0 0 0 0 0B − − − − − − − −B − − − − − − − −B − − − − − − − −B − − 0 0 0 0 0 0B
PWM
DPDP
DMAC parameter descriptor point
R/W
DACSR
DMAC control status register
R/W
DMAC
DATCR
DMAC pin control register
R/W
ICHCR
Instruction cache
R/W
Instruction Cache
Note : Do not execute an RMW-type instruction for any register containing a write-only bit.
(Continued)
26
MB91107/108
Register name
Address 0003F0H 0003F1H 0003F2H 0003F3H 0003F4H 0003F5H 0003F6H 0003F7H 0003F8H 0003F9H 0003FAH 0003FBH 0003FCH 0003FDH 0003FEH 0003FFH 000400H 000401H 000402H 000403H 000404H 000405H 000406H 000407H 000408H 000409H 00040AH 00040BH 00040CH 00040DH 00040EH 00040FH 000410H
Register name
Access
Resource name
Initial value XXXXXXXXB
BSD0
Bit search module zero-detection data register
W
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Bit Search Module XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B
BSD1
Bit search module single-detection data register
R/W
BSDC
Bit search module transition-detection data register
W
BSRR
Bit search module result register
R
ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16
Interrupt control register 0 Interrupt control register 1 Interrupt control register 2 Interrupt control register 3 Interrupt control register 4 Interrupt control register 5 Interrupt control register 6 Interrupt control register 7 Interrupt control register 8 Interrupt control register 9 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 Interrupt control register 16 R/W Interrupt Controller
− − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B
Note : Do not execute an RMW-type instruction for any register containing a write-only bit.
(Continued)
27
MB91107/108
Register name ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 DICR HRCL
Address 000411H 000412H 000413H 000414H 000415H 000416H 000417H 000418H 000419H 00041AH 00041BH 00041CH 00041DH 00041EH 00041FH 000420H 000421H 000422H 000423H 000424H 000425H 000426H 000427H 000428H 000429H 00042AH 00042BH 00042CH 00042DH 00042EH 00042FH 000430H 000431H
Register name Interrupt control register17 Interrupt control register 18 Interrupt control register 19 Interrupt control register 20 Interrupt control register 21 Interrupt control register 22 Interrupt control register 23 Interrupt control register 24 Interrupt control register 25 Interrupt control register 26 Interrupt control register 27 Interrupt control register 28 Interrupt control register 29 Interrupt control register 30 Interrupt control register 31 Interrupt control register 32 Interrupt control register 33 Interrupt control register 34 Interrupt control register 35 Interrupt control register 36 Interrupt control register 37 Interrupt control register 38 Interrupt control register 39 Interrupt control register 40 Interrupt control register 41 Interrupt control register 42 Interrupt control register 43 Interrupt control register 44 Interrupt control register 45 Interrupt control register 46 Interrupt control register 47 Delayed interrupt Holding request withdrawal request level set register
Access
Resource name
Initial value − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B
R/W
Interrupt Controller
− − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B − − − 1 1 1 1 1B
R/W R/W
Delayed Interrupt Controller Register
− − − − − − − 0B − − − 1 1 1 1 1B
Note : Do not execute an RMW-type instruction for any register containing a write-only bit.
(Continued)
28
MB91107/108
Register name RSRR/ WTCR STCR PDRR CTBR GCR WPR PCTR DDR2 DDR7 DDR6 DDRB DDRA DDR8 ASR1 AMR1 ASR2 AMR2 ASR3 AMR3 ASR4 AMR4 ASR5
Address 000480H 000481H 000482H 000483H 000484H 000485H 000488H 000601H 000604H 000605H 000608H 000609H 00060BH 00060CH 00060DH 00060EH 00060FH 000610H 000611H 000612H 000613H 000614H 000615H 000616H 000617H 000618H 000619H 00061AH 00061BH 00061CH 00061DH
Register name Reset cause register/watchdog cycle control register Stand-by controller register DMA controller request prohibit resister Timebase timer clear register Gear controller register Watchdog reset generation postpone register PLL controller register Port 2 data direction register Port 7 data direction register Port 6 data direction register Port B data direction register Port A data direction register Port 8 data direction register Area selection register 1 Area mask register 1 Area selection register 2 Area mask register 2 Area selection register 3 Area mask register 3 Area selection register 4 Area mask register 4 Area selection register 5
Access R/W R/W R/W W R/W W W W W W W W W W W W W W W W W W
Resource name
Initial value 1 XXXX − 0 0B 0 0 0 1 1 1 − −B
Clock Controller
− − − − 0 0 0 0B XXXXXXXXB 1 1 0 0 1 1 − 1B XXXXXXXXB
PLL Controller
0 0 − − 0 − − −B 0 0 0 0 0 0 0 0B − − − − − − − 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B − 0 0 0 0 0 0 −B − −0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 1 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 11B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 1B
Port Direction Register
External Bus Interface
Note : Do not execute an RMW-type instruction for any register containing a write-only bit.
(Continued)
29
MB91107/108
(Continued)
Address 00061EH 00061FH 000620H 000621H 000622H 000623H 000624H 000625H 000626H 000627H 000628H 000629H 00062AH 00062BH 00062CH 00062DH 00062EH 00062FH 0007FEH 0007FFH Register name AMR5 AMD0 AMD1 AMD32 AMD4 AMD5 DSCR RFCR EPCR0 EPCR1 DMCR4 DMCR5 LER MODR Register name Area mask register 5 Area mode register 0 Area mode register 1 Area mode register 32 Area mode register 4 Area mode register 5 DRAM signal control register Refresh control register External pin control register 0 External pin control register 1 DRAM control register 4 DRAM control register 5 Little endian register Mode register Access W R/W R/W R/W R/W R/W W R/W W W R/W R/W W W Little Endian Registor Mode Register External Bus Interface Resource name Initial value 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B − − − 0 0 1 1 1B 0 − − 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 − − 0 0 0 0 0B 0 − − 0 0 0 0 0B 0 0 0 0 0 0 0 0B − − XXXXXXB 0 0 − − − 0 0 0B − − − − 1 1 0 0B − 1 1 1 1 1 1 1B − − − − − − − 1B 1 1 1 1 1 1 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 −B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 −B − − − − − 0 0 0B XXXXXXXXB
Note: Do not execute an RMW-type instruction for any register containing a write-only bit. Note : RMW-type instructions (RMW: Read modify write) AND Rj, @Ri OR Rj, @Ri ANDH Rj, @Ri ORH Rj, @Ri ANDB Rj, @Ri ORB Rj, @Ri BANDL #u4, @Ri BORL #u4, @Ri BANDH #u4, @Ri BORH #u4, @Ri EOR EORH EORB BEORL BEORH Rj, @Ri Rj, @Ri Rj, @Ri #u4, @Ri #u4, @Ri
30
MB91107/108
s INTERRUPT CAUSES, INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTER ALLOCATIONS
Interrupt causes Reset Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Exception for undefined instruction NMI request External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 UART0 receive complete UART1 receive complete UART2 receive complete UART0 transmit complete UART1 transmit complete UART2 transmit complete DMAC0 (complete, error) DMAC1 (complete, error) DMAC2 (complete, error) DMAC3 (complete, error) DMAC4 (complete, error) DMAC5 (complete, error) DMAC6 (complete, error) DMAC7 (complete, error) Interrupt number Decimal Hexadecimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 Interrupt level Register FH fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H 37CH 378H TBR default address 0FFFFCH 0FFFF8H 0FFFF4H 0FFFF0H 0FFFECH 0FFFE8H 0FFFE4H 0FFFE0H 0FFFDCH 0FFFD8H 0FFFD4H 0FFFD0H 0FFFCCH 0FFFC8H 0FFFC4H 0FFFC0H 0FFFBCH 0FFFB8H 0FFFB4H 0FFFB0H 0FFFACH 0FFFA8H 0FFFA4H 0FFFA0H 0FFF9CH 0FFF98H 0FFF94H 0FFF90H 0FFF8CH 0FFF88H 0FFF84H 0FFF80H 0FFF7CH 0FFF78H
(Continued)
31
MB91107/108
(Continued)
Interrupt causes A/D converter (successive approximation conversion type) Reload timer 0 Reload timer 1 Reload timer 2 PWM0 PWM1 PWM2 PWM3 U-TIMER0 U-TIMER1 U-TIMER2 Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Delayed interrupt cause bit Reserved for system (used in REALOS*) Reserved for system (used in REALOS*) Used in INT instructions Interrupt number Decimal Hexadecimal 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 to 255 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 to FF Interrupt level Register ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 Offset 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H 2F4H to 000H TBR default address 0FFF74H 0FFF70H 0FFF6CH 0FFF68H 0FFF64H 0FFF60H 0FFF5CH 0FFF58H 0FFF54H 0FFF50H 0FFF4CH 0FFF48H 0FFF44H 0FFF40H 0FFF3CH 0FFF38H 0FFF34H 0FFF30H 0FFF2CH 0FFF28H 0FFF24H 0FFF20H 0FFF1CH 0FFF18H 0FFF14H 0FFF10H 0FFF0CH 0FFF08H 0FFF04H 0FFF00H 0FFEFCH 0FFEF8H 0FFEF4H to 0FFC00H
*: When using in REALOS/FR, interrupt 0x40, 0x41 for system code. 32
MB91107/108
s PERIPHERAL RESOURCES
1. I/O Ports
There are 2 types of I/O port register structure; PDR (port data register) and DDR (data direction register) . • For input (DDR = “0”) setting; PDR reading operation: reads level of corresponding external pin. PDR writing operation: writes set value to PDR. • For output (DDR = “1”) setting; PDR reading operation: reads PDR value. PDR writing operation: outputs PDR value to corresponding external pin. (1) Register configuration
•Port Data Register (PDR)
Address 000001H 000005H 000004H 00000BH 000009H 000008H 000012H 000013H 000014H 000015H 000016H
bit 7 PDR2 PDR6 PDR7 PDR8 PDRA PDRB PDRE PDRF PDRG PDRH PDRI
bit 0
Initial value XXXXXXXXB XXXXXXXXB - - - - - - - XB - - X - - XXXB - XXXXXX -B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXX0B - - - - - - XXB
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Readable and writable : Unused X : Indeterminate
33
MB91107/108
•Data Direction Register (DDR)
Address 000601H 000605H 000604H 00060BH 000609H 000608H 0000D2H 0000D3H 0000D4H 0000D5H 0000D6H
bit 7 DDR2 DDR6 DDR7 DDR8 DDRA DDRB DDRE DDRF DDRG DDRH DDRI W : Write only : Unused
bit 0
Initial value 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - - - - - - 0B - - 0 - - 0 0 0B - 0 0 0 0 0 0 -B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 1B - - - - - - 0 0B
Access W W W W W W W W W W W
34
MB91107/108
(2) Block diagram
Data Bus
Resource input
0
1 PDR read
0 PDR
pin
Resource output
1
Resource output enable
DDR
PDR : Port Data Register DDR : Data Direction Register
35
MB91107/108
2. DMA Controller (DMAC)
The DMA controller is a module embedded in FR family devices, and performs DMA (direct memory access) transfer. DMA transfer performed by the DMA controller transfers data without intervention of CPU, contributing to enhanced performance of the system. • 8 channels • Mode: single/block transfer, burst transfer and continuous transfer: 3 kinds of transfer • Transfer all through the area • Max. 65536 of transfer cycles • Interrupt function right after the transfer • Selectable for address transfer increase/decrease by the software • External transfer request input pin, external transfer request accept output pin, external transfer complete output pin three pins for each (1) Register configuration DMAC (DMAC internal registers) Address 000200H DMAC control status register 000204H DMAC pin control register 000208H DATCR DATCR DACSR DACSR bit 31 DPDP bit 0 DPDP
DMAC parameter descriptor point
RAM (DMA descriptor) bit 31 DPDP + 0H bit 0 DMA ch-0 descriptor DPDP + 0CH DMA ch-1 descriptor : : DPDP + 54H DMA ch-7 descriptor
36
MB91107/108
(2) Block diagram
3 DREQ0 ∼DREQ2 3
Edge/level detection circuit
3
DACK0 ∼ DACK2 EOP0 ∼ EOP2
3
Sequencer Inner resource Transfer request
5
8
Interrupt request
Data buffer
Switcher Data bus
DPDP
DACSR
DATCR
Mode
BLK DEC BLK
DMACT
INC / DEC
SADR
DADR
37
MB91107/108
3. UART
The UART is a serial I/O port for supporting asynchronous (start-stop system) communication or CLK synchronous communication, and it has the following features. The MB91107 consists of 3 channels of UART. • Full double double buffer • Both a synchronous (start-stop system) communication and CLK synchronous communication are available. • Supporting multi-processor mode • Perfect programmable baud rate Any baud rate can be set by internal timer (refer to section “4. U-TIMER”). • Any baud rate can be set by external clock. • Error checking function (parity, framing and overrun) • Transfer signal: NRZ code • Enable DMA transfer/start by interrupt. (1) Register configuration
•Serial control register
Address SCR0 : 00001EH SCR1 : 000022H SCR2 : 000026H
•Serial mode register
bit 15 bit 8 bit 7 SCR0 to SCR2
bit 0 (SMR)
Initial value 0 0 0 0 010 0B
Access R/W
Address SMR0 : 00001FH SMR1 : 000023H SMR2 : 000027H
•Serial status register
bit 15 (SCR)
bit 8 bit 7 bit 0 SMR0 to SMR2
Initial value Access 0 0 - - 0 - 0 0B R/W
Address SSR0 : 00001CH SSR1 : 000020H SSR2 : 000024H
•Serial input data register
bit 15 bit 8 bit 7 bit 0 SSR0 to SSR2 (SIDR/SODR)
Initial value Access 0 0 0 01 - 0 0 B R/W
Address SIDR0 : 00001DH SIDR1 : 000021H SIDR2 : 000025H
•Serial output data register
bit 15 (SSR)
bit 8 bit 7 bit 0 (SIDR/SODR)
Initial value Access XXXXXXXXB R
Address SIDR0 : 00001DH SIDR1 : 000021H SIDR2 : 000025H
bit 15 (SSR)
bit 8 bit 7 bit 0 (SIDR/SODR)
Initial value Access XXXXXXXXB R
R/W : Readable and writable R : Read only W : Write only
X
: Unused : Indeterminate
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(2) Block diagram
Control signal Receive interrupt ( to CPU) SC (clock) From U-TIMER From external clock
SC
Clock select circuit
Transmit clock Receive clock Receive control circuit Start bit detect circuit Receive bit counter Receive parity counter
Transmit interrupt ( to CPU)
Transmit control circuit Transmit bit counter Transmit start circuit Transmit parity counter SO (Transmit data)
SI
(Receive data)
Receive status judge circuit
Receive shifter
Receive complete
Transmit shifter Transmit start
SODR
Receive error generate signal for DMA ( to DMAC)
SIDR
R - BUS
MD1 MD0
SMR
Register
CS0 SCKE SOE
SCR
Register
PEN P SBL CL A/D REC RXE TXE
SSR
Register
PE ORE FRE RDRF TDRE RIE TIE
Control signals
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4. U-TIMER (16-bit Timer for UART Baud Rate Generation)
The U-TIMER is a 16-bit timer for generating UART baud rate. Combination of chip operating frequency and reload value of U-TIMER allows flexible setting of baud rate. The U-TIMER operates as an interval timer by using interrupt issued on counter underflow. The MB91107 has 3 channel U-TIMER embedded on the chip. An interval of up to 216 × φ can be counted. (1) Register configuration • U-TIMER register ch 0 to ch 2 Address bit 15 UTIM0 : 000078H UTIM1 : 00007CH UTIM2 : 000080H
bit 0 UTIM0 to UTIM2
Initial value Access 0 0 0 0 0 0 0 0B R 0 0 0 0 0 0 0 0B
• U-TIMER reload register ch 0 to ch 2 Address bit 15 UTIM0 : 000078H UTIM0 to UTIM2 UTIM1 : 00007CH UTIM2 : 000080H • U-TIMER control register ch 0 to ch 2 Address bit 15 UTIM0 : 00007BH (Vacancy) UTIM1 : 00007FH UTIM2 : 000083H R/W R W -
bit 0
Initial value Access 0 0 0 0 0 0 0 0B W 0 0 0 0 0 0 0 0B
bit 0 UTIMC0 to UTIMC2
Initial value Access 0 - - 0 0 0 0 1B R/W
: Readable and writable : Read only : Write only : Unused
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MB91107/108
(2) Block diagram
15
0
UTIMR (reload register)
load 15 0
UTIM (timer) clock φ
underflow control
(Peripheral clock)
f.f. to UART
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5. PWM Timer
The PWM timer can output high accurate PWM waves efficiently. MB91101 has inner 4-channel PWM timers, and has the following features. • Each channel consists of a 16-bit down counter, a 16-bit data resister with a buffer for cycle setting, a 16-bit compare resister with a buffer for duty setting, and a pin controller. • The count clock of a 16-bit down counter can be selected from the following four inner clocks. • Inner clock φ, φ/4, φ/16, φ/64 • The counter value can be initialized “FFFFH” by the resetting or the counter borrow. • PWM output (each channel) • Resister description Cycle setting register: Reload data register with a buffer Duty factor setting register: Compare register with a buffer Transfer from the buffers uses the counter borrow method. • Pin control outline Set to ’1’ at a duty factor match. (Preferential) Set to ’0’ at a counter borrow. The output value fixed mode is available, which makes all ’L’ (or ’H’) output easy. The polarity can also be specified. • Interrupt requests can be generated by selected a combination of events: This timer is activated. A counter borrow is generated (cycle match). A duty factor match is generated. A counter borrow is generated (cycle match) or a duty factor match is generated. DMA transfer can be invoked by the above interrupt request. • Simultaneous activation of multiple channels of the PWM timer can be set by software or by using another interval timer. Restarting the PWM timer during operation can also be set.
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(1) Register configuration Address 0000DCH 0000DFH 0000E0H 0000E2H 0000E4H 0000E6H 0000E8H 0000EAH 0000ECH 0000EEH 0000F0H 0000F2H 0000F4H 0000F6H 0000F8H 0000FAH 0000FCH 0000FEH PCNH PCNH PTMR PCSR PDUT PCNL PCNH PTMR PCSR PDUT PCNL PCNH PTMR PCSR PDUT PCNL PTMR PCSR PDUT PCNL bit 15 GCN1 GCN2 bit 0 Initial value 0 0 1 1 0 0 1 0B 0 0 0 1 0 0 0 0B 0 0 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 -B 0 0 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 -B 0 0 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 -B 0 0 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 -B 0 0 0 0 0 0 0 0B X Access R/W R/W R W W R/W R W W R/W R W W R/W R (W) W R/W General control register 1 General control register 2 ch0 timer register ch0 cycle setting register ch0 duty setting register
ch0 control status register ch1 timer register ch1 cycle setting register ch1 duty setting register
ch1 control status register ch2 timer register ch2 cycle setting register ch2 duty setting register
ch2 control status register ch3 timer register ch3 cycle setting register ch3 duty setting register
ch3 control status register
R/W : Readable and writable R : Read only W : Write only
: Unused : Indeterminate
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(2) Block Diagram •General construction
16-bit reload timer ch0 16-bit reload timer ch1 General control register 1 (cause selection)
4
TRG input PWM timer ch0 TRG input PWM timer ch1
PWM0
PWM1
General control register 2 External TRG0 to TRG3
TRG input PWM timer ch2 TRG input PWM timer ch3
PWM2
4
PWM3
•For one channel
PCSR
PDUT
Prescaler
1/1 1/4 1/16 1/64
ck
Load
cmp
16-bit down counter Start Borrow PPG mask
S Q
PWM output
R
Peripheral clock
Reverse bit Interrupt selection Enable
IRQ
TRG input
Edge detect Soft trigger
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6. 16-bit Reload Timer
The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload timer, a prescaler for generating internal count clock and control registers. Internal clock can be selected from 3 types of internal clocks (divided by 2/8/32 of machine clock). The DMA transfer can be started by the interruption. The MB91107 consists of 3 channels of the 16-bit reload timer. (1) Register configuration
•Control status register
Address TMCSR0 : 00002EH TMCSR1 : 000036H TMCSR2 : 000042H
•16-bit timer register
bit 15 TMCSR0 to TMCSR2
bit 0
Initial value Access - - - - 0 0 0 0B R/W 0 0 0 0 0 0 0 0B
Address TMR0 : 00002AH TMR1 : 000032H TMR2 : 00003EH
•16-bit reload register
bit 15 TMR0 to TMR2
bit 0
Initial value Access XXXXXXXXB R XXXXXXXXB
Address TMRLR0 : 000028H TMRLR1 : 000030H TMRLR2 : 00003CH
bit 15 TMRLR0 to TMRLR2
bit 0
Initial value Access XXXXXXXXB W XXXXXXXXB
R/W : Readable and writable R : Read only W : Write only
X
: Unused : Indeterminate
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(2) Block diagram
16
16-bit reload register
8 R | B U S
Reload
RELD 16
16-bit down counter
2 GATE
UF
OUTE OUTL OUT CTL. 2 INTE UF CNTE IRQ
Clock selector
2
CSL1 CSL0 TRG
Retrigger
IN CTL. EXCK φ 21 φ 23 φ 25 3 MOD2 MOD1 PWM (ch 0, ch 1) A/D (ch 2)
Prescaler clear
Internal clock
3
MOD0
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7. Bit Search Module
The bit search module detects transitions of data (0 to 1/1 to 0) on the data written on the input registers and returns locations of the transitions. (1) Register configuration Address 0003F0H 0003F4H 0003F8H 0003FCH bit 31 BSD0 BSD1 BSDC BSRR bit 0 Initial value Access XXXXXXXXXXXXXXXXB W Zero-detection data register XXXXXXXXXXXXXXXXB XXXXXXXXXXXXXXXXB R/W Single-detection data register XXXXXXXXXXXXXXXXB XXXXXXXXXXXXXXXXB W Detection data register XXXXXXXXXXXXXXXXB XXXXXXXXXXXXXXXXB R Search result register XXXXXXXXXXXXXXXXB : Readable and writable : Read only : Write only : Indeterminate
R/W R W X
(2) Block diagram
D-BUS
Input latch Address decoder
Detection mode Single-detection data register
Bit search circuit
Search result
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8. A/D Converter (Successive Approximation Conversion Type)
The A/D converter is the module which converts an analog input voltage to a digital value, and it has following features. • Minimum converting time: 5.6 µs/ch. (system clock: 25 MHz) • Inner sample and hold circuit • Resolution: 10 bits • Analog input can be selected from 4 channels by program. Single convert mode: 1 channel is selected and converted. Scan convert mode: Converting continuous channels. Maximum 4 channels are programmable. Continuous convert mode: Converting the specified channel repeatedly. Stop convert mode: After converting one channel then stop and wait till next activation synchronising at the beginning of conversion can be peformed. • DMA transfer operation is available by interruption. • Operating factor can be selected from the software, the external trigger (falling edge), and 16-bit reroad timer (rising edge). (1) Register configuration
•A/D converter control register
Address 00003AH
bit 15 ADCS
bit 0
Initial value Access 0 0 0 0 0 0 0 0B R/W 0 0 0 0 0 0 0 0B
•A/D converter data register
Address 000038H
bit 15 ADCR
bit 0
Initial value Access - - - - - -XXB R XXXXXXXXB
R/W : Readable and writable R : Read only X : Indeterminate
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(2) Block diagram
AVCC AVRH AVSS
Internal voltage generator
MPX
AN0 AN1 AN2 AN3
Input circuit
Successive approximation register Comparator Sample & hold circuit
R | B U S
Decoder
Data register
ADCR
A/D control register Trigger start
ATG ADCS
TIM0 (Internal connection) (Reload timer ch2)
φ
Timer start Operating clock
Prescaler
(Peripheral clock)
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9. Interrupt Controller
The interrupt controller processes interrupt acknowledgments and arbitration between interrupts.
•Hardware configuration
This module consists of the following components: • ICR register • Interrupt priority evaluation circuit • Interrupt level/interrupt number (vector) generator • HOLD request cancel request generator
•Main Features
The major functions of this module are listed below: • NMI request/interrupt request detection • Priority evaluation (interrupt level and number) • Transfer of interrupt level as evaluation factor (to the CPU) • Transfer of interrupt number as evaluation factor (to the CPU) • Instruction of returning from the stop mode by NMI/interrupt generation • Generating a request to cancel the HOLD request to the bus master
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(1) Register configuration
•Interrupt control register 0 to 47
Address 000400H 000401H 000402H 000403H 000404H 000405H 000406H 000407H 000408H 000409H 00040AH 00040BH 00040CH 00040DH 00040EH 00040FH 000410H 000411H 000412H 000413H 000414H 000415H 000416H 000417H 000418H
bit 7 ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24
bit 0
Initial value Access - - - 11111B R/W - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Address 000419H 00041AH 00041BH 00041CH 00041DH 00041EH 00041FH 000420H 000421H 000422H 000423H 000424H 000425H 000426H 000427H 000428H 000429H 00042AH 00042BH 00042CH 00042DH 00042EH 00042FH
bit 7 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
bit 0
Initial value Access - - - 11111B R/W - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B - - - 11111B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
•Request level register for canceling hold request
Address 00000431H
bit 7 HRCL R/W : Readable and writable : Unused
bit 0
Initial value Access - - - 11111B R/W
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MB91107/108
(2) Block diagram
INT0∗2
IM
Priority judgment
OR NMI
NMI processing
4
5
LEVEL 4 ∼ 0∗4
LEVEL judgment
ICR00 RI00 6
LEVEL, VECTOR generation
HLDREQ cancel request
HLDCAN∗3
VECTOR judgment
ICR47 RI47 (DLYIRQ) DLYI∗1
VCT5 ∼ 0∗5
R-BUS
*1 : DLY I stands for delayed interrupt module (delayed interrupt generation block) (refer to the section “11. Delayed Interrupt Module” for detail). *2 : INT0 is a wake-up signal to clock control block in the sleep or stop status. *3 : HLDCAN is a bus release request signal for bus masters other than CPU. *4 : LEVEL 4 to LEVEL 0 are interrupt level outputs. *5 : VCT5 to VCT0 are interrupt vector outputs.
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10. External Interrupt/NMI Control Block
The external interrupt/NMI control block controls external interrupt request signals input to NMI pin and INT0 to INT7 pins. Detecting levels can be selected from “H”, “L”, rising edge and falling edge (not for NMI pin). (1) Register configuration
•Interrupt enable register
Address 000095H
bit 15 EIRR
bit 8 bit 7 ENIR
bit 0
Initial value 00000000B
Access R/W
•External interrupt cause register
bit 15 000094H EIRR
bit 8 bit 7 ENIR
bit 0 00000000B R/W
•Request level setting register
bit 15 000099H EIRR
bit 8 bit 7 ENIR
bit 0 00000000B R/W
(2) Block diagram
R BUS 8
Interrupt enable register
Edge detection circuit
Interrupt request
9
Gate
Cause F/
9
INT0 ~ INT7 NMI
8
Interrupt cause register
8
Request level setting register
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11. Delayed Interrupt Module
Delayed interrupt module is a module which generates a interrupt for changing a task. By using this delayed interrupt module, an interrupt request to CPU can be generated/cancelled by the software. Refer to the section “9. Interrupt Controller” for delayed interrupt module block diagram.
•Register configuration •Delayed interrupt control register
Address 000430H
bit 7 DICR R/W : Readable and writable : Unused
bit 0
Initial value Access - - - - - - - 0B R/W
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12. Clock Generation (Low-power consumption mechanism)
The clock control block is a module which undertakes the following functions. • CPU clock generation (including gear function) • Peripheral clock generation (including gear function) • Reset generation and cause hold • Standby function (including hardware standby) • DMA request prohibit • PLL (multiplier circuit) embedded (1) Register configuration
•Reset cause register/watchdog cycle control register
Address 000480H
bit 15 RSRR
bit 10 bit 8 WTCR
bit 0 (STCR)
Initial value Access 1XXXX - 0 0B R/W
•Stand-by controled register
Address 000481H
bit 15 bit 10 (RSRR/WTCR)
bit 8 STCR
bit 0
Initial value 0 0 0 111 - - B
R/W
•DMA controlerrequest prohibit resister
Address 000482H
bit 15 PDRR
bit 8 (CTBR)
bit 0
Initial value - - - - 0 0 0 0B
R/W
•Timebase timer clear resister
Address 000483H
•Gear control resister
bit 15 PDRR
bit 8 (CTBR)
bit 0
Initial value XXXXXXXXB
W
Address 000484H
bit 15 GCR
bit 8 (WPR)
bit 0
Initial value - - - - 0 0 0 0B
R/W
•Watchdog reset generation postpone resister
Address 000485H
•PLL control resister
bit 15 (GCR)
bit 8 WPR
bit 0
Initial value XXXXXXXXB
W
Address 000488H
bit 15 PCTR R/W W X
bit 8 Vacancy
bit 0
Initial value 00 - - 0 - - - B
W
: Readable and writable : Write only : Unused : Indeterminate
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MB91107/108
(2) Block diagram Gear control block GCR register
CPU gear
Peripheral gear
R | B U S
PCTR register
X0 X1
Oscillator
PLL 1/2
Selection circuit
Internal clock generator circuit
CPU clock Internal bus clock External bus clock
Peripheral DMA clock
Internal bus peripheral clock
Internal interrupt Internal reset
(Stop/sleep control section)
STCR register CPU hold enable HST pin Status transition control circuit STOP state SLEEP state CPU hold request
Reset generation F/F
Internal reset
DMA request
(DNA prohibit circuit)
PDRR register (Reset cause circuit) Power on cell
RST pin RSRR register (Watchdog control section) WPR register Watchdog F/F CTBR register Timebase timer Count clock
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13. External Bus Interface
The external bus interface controls the interface between the device and the external memory and also the external I/O, and has the following features. • 25-bit (32 Mbytes) address output • 6 independent banks owing to the chip select function. Can be set to anywhere on the logical address space for minimum unit 64 Kbytes. Total 32 Mbytes × 6 area setting is available by the address pin and the chip select pin. • 8/16-bit bus width setting are available for every chip select area. Areas 6 and 7 allow the inclusive areas to be set. • Programmable automatic memory wait (max. for 7 cycles) can be inserted. • DRAM interface support • Three kinds of DRAM interface: Double CAS DRAM (normally DRAM I/F) Single CAS DRAM Hyper DRAM • 2 banks independent control (RAS, CAS, etc. control signals) • DRAM select is available from 2CAS/1WE and 1CAS/2WE. • Hi-speed page mode supported • CBR/self refresh supported • Programmable wave form • Unused address/data pin can be used for I/O port. • Little endian mode supported • Clock doubler: Internal bus 50 MHz, external bus 25 MHz (1) Register configuration
•Area selection resister 1 to 5
Address 00060CH 000610H 000614H 000618H 00061CH
bit 15 ASR1 ASR2 ASR3 ASR4 ASR5
bit 0
Initial value 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 1 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 1B
Access W W W W W
•Area mask resister 1 to 5
Address 00060EH 000612H 000616H 00061AH 00061EH
bit 15 AMR1 AMR2 AMR3 AMR4 AMR5
bit 0
Initial value 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
W W W W W
(Continued)
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(Continued)
•Area mode resister 0, 1, 32, 4, 5
Address AMD0 : 000620H AMD1 : 000621H AMD32 : 000622H : 000023H AMD4 AMD5 : 000624H
bit 15 AMD0 AMD32 AMD5
bit 8 bit 7 AMD1 AMD4 (DSCR)
bit 0
Initial value Access - - - 0 0 1 1 1B 0 - - 0 0 0 0 0B R/W 0 0 0 0 0 0 0 0B 0 - - 0 0 0 0 0B 0 - - 0 0 0 0 0B R/W R/W
•DRAM signal control resister
Address 000625H
•Refresh control resister
bit 15 AMD5
bit 8 bit 7 DSCR
bit 0
Initial value 0 0 0 0 0 0 0 0B
W
Address 000626H
bit 15 RFCR
bit 0
Initial value
- - XXXXXXB 0 0 - - - 0 0 0B
R/W
•External pin control resister
Address 000628H 00062AH
•DRAM control resister 4, 5
bit 15 EPCR0 EPCR1
bit 0
Initial value - - - - 1 1 0 0B - 1 1 1 1 1 1 1B - - - - - - - 1B 1 1 1 1 1 1 1 1B
W W
Address 00062CH 00062EH
•Little endian resister
bit 15 DMCR4 DMCR5
bit 0
Initial value 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 -B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 -B
R/W R/W
Address 0007FEH
•Mode resister
bit 15 LER
bit 8 bit 7 (MODR)
bit 0
Initial value - - - - - 0 0 0B
W
Address 0007FFH
bit 15 (MODR) R/W W X
bit 8 bit 7 LER
bit 0
Initial value XXXXXXXXB
W
: Readable and writable : Write only : Unused : Indeterminate
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(2) Block diagram
ADDRESS BUS DATA BUS 32 32
A-OUT EXTERNAL DATA BUS write buffer switch MUX
read buffer
switch
DATA BLOCK ADDRESS BLOCK
+1or+2 inpage address buffer shifter
EXTERNAL ADDRESS BUS
ASR AMR comparator
CS0 ∼ CS7
DRAM control DMCR underflow refresh counter from TBT
RAS0, RAS1 CS0L, CS1L CS0H, CS1H DW0, DW1
External pin control block
RD WR0, WR1 BRQ BGRNT CLK RDY
All blocks control
registers & control
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s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Value Min. VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 0 −55 Max. VSS + 4.0 VSS + 4.0 VSS + 4.0 VCC + 0.3 AVCC + 0.3 VCC + 0.3 10 8 100 50 −10 −4 −50 −20 500 +70 +150 (AVSS = VSS = 0.0 V) Symbol VCC AVCC AVRH VI VIA VO IOL IOLAV ΣIOL ΣIOLAV IOH IOHAV ΣIOH ΣIOHAV PD TA Tstg Unit V V V V V V mA mA mA mA mA mA mA mA mW °C °C *5 *5 *3 *4 *3 *4 *1 *2 *2 Remarks
Parameter Power supply voltage Analog supply voltage Analog reference voltage Input voltage Analog pin input voltage Output voltage “L” level maximum output current “L” level average output current “L” level total maximum output current “L” level total average output current “H” level maximum output current “H” level average output current “H” level total maximum output current “H” level total average output current Power consumption Operating temperature Storage temperature
*1 : VCC must not be less than VSS – 0.3 V. *2 : Care must be taken that AVCC and AVRH do not exceed VCC + 0.3 V, such as when turning on the device. Also, care must be taken that AVRH does not exceed AVCC. *3 : Maximum output current is a peak current value measured at a corresponding pin. *4 : Average output current is an average current for a 100 ms period at a corresponding pin. *5 : Average total output current is an average current for a 100 ms period for all corresponding pins.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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2. Recommended Operating Conditions
Value Min. 3.0 3.0 VSS − 0.3 AVSS 0 Max. 3.6 3.6 VSS + 3.6 AVCC +70 V V V °C
(AVSS = VSS = 0.0 V) Unit Remarks Normal operation Retaining the RAM state in stop mode
Parameter
Symbol VCC
Power supply voltage Analog supply voltage Analog reference voltage Operating temperature
VCC AVCC AVRH TA
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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3. DC Characteristics
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C) Pin name Input pin except for hysteresis input *1 Input pin except for hysteresis input *1 All output pins All output pins VCC = 3.0 V IOH = −4.0 mA VCC = 3.0 V IOL = 8.0 mA VCC = 3.6 V 0.45 V 100 µs •The setting of internal clock must be within above ranges.
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(2) Clock Output Timing Pin name CLK CLK CLK
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C) Condition Value Min. tCP 2 × tCP Max. Unit ns ns ns *1 Using the doubler *2 *3 Remarks
Parameter Cycle time CLK↑→CLK↓ CLK↓→CLK↑
Symbol tCYC tCHCL tCLCH
1 / 2 × tCYC − 10 1 / 2 × tCYC + 10 1 / 2 × tCYC − 10 1 / 2 × tCYC + 10
tCYC tCHCL tCLCH VOH VOL
CLK
VOH
*1 : tCYC is a frequency for 1 clock cycle including a gear cycle. *2 : Rating at a gear cycle of × 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equations with 1/2, 1/4, 1/8, respectively. Min. : (1 – n/2) × tCYC – 10 Max. : (1 – n/2) × tCYC + 10 Select a gear cycle of × 1 when using the doubler. *3 : Rating at a gear cycle of × 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equations with 1/2, 1/4, 1/8, respectively. Min.: n/2 × tCYC – 10 Max.: n/2 × tCYC + 10 Select a gear cycle of × 1 when using the doubler.
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The relation between source oscillation input and CLK pin for configured by CHC/CCK1/CCK0 settings of GCR (gear control register) is as follows. However, in this chart source oscillation input means X0 input clock. Source oscillation input (When using the doublure) • PLL system (CHC bit of GCR set to “0”) (a) Gear × 1 CLK pin CCK1/0 : “00”
tCYC
tCYC
Source oscillation input • 2 dividing system (CHC bit of GCR set to “1”) (a) Gear × 1 CLK pin CCK1/0 : “00” (b) Gear × 1/2 CLK pin CCK1/0 : “01” (c) Gear × 1/4 CLK pin CCK1/0 : “10” (d) Gear × 1/8 CLK pin CCK1/0 : “11”
tCYC
tCYC
tCYC
tCYC
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(3) Reset Input Ratings Pin name RST
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C) Symbol tRSTL Condition Value Min. tCP × 5 Max. Unit ns Remarks
Parameter Reset input time
tRSTL
RST
0.2 VCC
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(4) Power-on Reset Pin name VCC
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C) Symbol Condition Value Min. 1 Max. 18 Unit Remarks VCC < 0.2 V before the power supply rising Repeated operations
Parameter Power supply rising time Power supply shut off time
tR
VCC = 3.3 V
ms
tOFF
VCC
ms
tR
VCC
0.9 VCC 0.2 V
•Notes 1) Sudden change in supply voltage during operation may initiate a power-on sequence. To change supply voltage during operation, it is recommended to smoothly raise the voltage to avoid rapid fluctuations in the supply voltage.
VCC
tOFF
Not less than 3 V
VSS
A voltage rising rate of 50 mV/ ms or less is recommended.
2) Set RST pin to “L” level when turning on the device, at least the tRSTL duration after the supply voltage reaches VCC is necessary before turning the RST to “H” level.
VCC
RST
tRSTL
3) If the supply voltage goes below the lower limit of the guaranteed operating voltage range, be sure to restart the power supply from the VSS level. This is because an internal power-on reset must be generated to restart operation without allowing the internal circuit to run out of control. The guaranteed operating voltage range of MB91107 is from 3.0 to 3.6 V.
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(5) Normal Bus Access Read/write Operation Symbol tCHCSL tCHCSH tCHAV tCHDV tCLRL tCLRH tCLWL tCLWH tAVDV tRLDV tDSRH tRHDX RD D31 to D16
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C) Condition Value Min. 10 0 Max. 15 15 15 15 15 15 15 15 3 / 2 × tCYC − 25 tCYC − 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns *1 *2 *1 Remarks
Parameter CS0 to CS7 delay time CS0 to CS7 delay time Address delay time Data delay time RD delay time RD delay time WR0, WR1 delay time WR0, WR1 delay time Valid address → valid data input time RD ↓→ valid data input time Data set up → RD ↑ time RD ↑→ data hold time
Pin name CLK CS0 to CS7 CLK A24 to A00 CLK D31 to D16 CLK RD CLK WR0 to WR1 A24 to A00 D31 to D16
*1: When bus timing is delayed by automatic wait insertion or RDY input, add (tCYC × extended cycle number for delay) to this rating. *2: Rating at a gear cycle of × 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equation with 1/2, 1/4, 1/8, respectively. Equation: (2 – n/2) × tCYC – 25
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tCYC BA1 BA2 2.4 V 0.8 V 0.8 V 2.4 V
CLK
2.4 V
tCHCSL
tCHCSH 2.4 V
CS0 ∼ CS7
0.8 V
tCHAV
A24 ∼ A00
2.4 V 0.8 V
2.4 V 0.8 V
tCLRL
tCLRH 2.4 V
RD
0.8 V tRLDV
tRHDX tAVDV
D31 ∼ D16
2.4 V 0.8 V
Read
2.4 V 0.8 V tDSRH
WR0 ∼ WR1
tCLWL 0.8 V 2.4 V tCLWH tCHDV
D31 ∼ D16
2.4 V 0.8 V
Write
2.4 V 0.8 V
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(6) Ready Input Timing
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C) Symbol tRDYS tRDYH Pin name RDY CLK CLK RDY Condition Value Min. 15 0 ns Max. Unit ns Remarks
Parameter RDY set up time → CLK ↓ CLK ↓→ RDY hold time
tCYC
CLK
2.4 V
0.8 V
2.4 V tRDYH
0.8 V tRDYH
tRDYS
tRDYS 2.4 V
RDY
(When wait is inserted.)
RDY
0.8 V
(When no wait is inserted.)
2.4 V
0.8 V
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(7) Hold Timing
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C) Symbol tCHBGL tCHBGH tXHAL tHAHV Pin name CLK BGRNT BGRNT Condition Value Min. tCYC − 10 tCYC − 10 Max. 6 6 tCYC + 10 tCYC + 10 Unit ns ns ns ns Remarks
Parameter BGRNT delay time BGRNT delay time Pin floating → BGRNT ↓ time BGRNT ↑→ pin valid time
Note : There is a delay time of more than 1 cycle from BRQ input to BGRNT change.
tCYC
CLK
2.4 V
2.4 V
2.4 V
2.4 V
BRQ
tCHBGL
tCHBGH 2.4 V
BGRNT
tXHAL
0.8 V
tHAHV
Each pin
High impedance
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(8) Normal DRAM Mode Read/Write Cycle
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C) Condition Value Min. 0 Max. 15 15 15 15 15 15 15 15 15 5 / 2 × tCYC − 16 tCYC − 17 Unit Remarks ns ns ns ns ns ns ns ns ns ns ns ns *1 *2 *1
Parameter RAS delay time RAS delay time CAS delay time CAS delay time ROW address delay time COLUMN address delay time DW delay time DW delay time Output data delay time RAS ↓→ valid data input time CAS ↓→ valid data input time CAS ↑→ data hold time
Symbol tCLRAH tCHRAL tCLCASL tCLCASH tCHRAV tCHCAV tCHDWL tCHDWH tCHDV1 tRLDV tCLDV tCADH
Pin name CLK RAS CLK CAS CLK A24 to A00 CLK DW CLK D31 to D16 RAS D31 to D16 CAS D31 to D16
*1 : When Q1 cycle or Q4 cycle is extended for 1 cycle, add tCYC time to this rating. *2 : Rating at a gear cycle of × 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equation with 1/2, 1/4, 1/8, respectively. •Equation: (3 – n/2) × tCYC – 16
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tCYC Q1 2.4 V 0.8 V Q2 Q3 2.4 V 0.8 V 0.8 V Q4 Q5 2.4 V
CLK
RAS
tCLRAH
2.4 V
0.8 V tCHRAL tCLCASL tCLCASH 2.4 V
CAS
0.8 V
tCHRAV
tCHCAV 2.4 V 0.8 V tRLDV tCLDV tCADH
COLUMN address
A24 to A00
2.4 V 0.8 V
2.4 V ROW address 0.8 V
2.4 V 0.8 V
D31 to D16
2.4 V 0.8 V
Read
2.4 V 0.8 V
DW
2.4 V 0.8 V tCHDWL tCHDWH
D31 to D16
2.4 V 0.8 V tCHDV1
Write
2.4 V 0.8 V
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(9) Normal DRAM Mode Fast Page Read/Write Cycle (VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C) Parameter RAS delay time CAS delay time CAS delay time COLUMN address delay time DW delay time Output data delay time CAS ↓→ valid data input time CAS ↑→ data hold time Symbol tCLRAH tCLCASL tCLCASH tCHCAV tCHDWH tCHDV1 tCLDV tCADH Pin name CLK, RAS CLK CAS CLK A24 to A00 CLK, DW CLK D31 to D16 CAS D31 to D16 Condition Value Min. 0 Max. 15 15 15 15 15 15 tCYC − 17 Unit Remarks ns ns ns ns ns ns ns ns *
* : When Q4 cycle is extended for 1 cycle, add tCYC time to this rating.
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Q5
Q4 2.4 V 0.8 V
Q5 0.8 V
Q4
Q5 2.4 V 0.8 V
CLK
tCLRAH
RAS
2.4 V
tCLCASL
tCLCASH 2.4 V
CAS
0.8 V
tCHCAV
A24 to A00 COLUMN address
2.4 V 0.8 V
COLUMN address
2.4 V 0.8 V
COLUMN address
tCLDV 2.4 V 0.8 V
tCADH 2.4 V 0.8 V
D31 to D16
Read
Read
Read
tCHDWH
DW
2.4 V
tCHDV1
D31 to D16
2.4 V 0.8 V
Write
2.4 V 0.8 V
2.4 V 0.8 V
Write
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(10) Single DRAM Timing
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C) Symbol tCLRAH2 tCHRAL2 tCHCASL2 tCHCASH2 tCHRAV2 tCHCAV2 tCHDWL2 tCHDWH2 tCHDV2 tCLDV2 tCADH2 Pin name CLK RAS CLK CAS CLK A24 to A00 CLK DW CLK, D31 to D16 CAS D31 to D16 Condition Value Min. 0 Max. 15 15 n / 2 × tCYC + tCHCASH2 15 15 15 15 15 15 (1 − n / 2) × tCYC − 17 Unit Remarks ns ns ns ns ns ns ns ns ns ns ns
Parameter RAS delay time RAS delay time CAS delay time CAS delay time ROW address delay time COLUMN address delay time DW delay time DW delay time Output data delay time CAS ↓→ Valid data input time CAS ↑→ data hold time
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tCYC Q1 Q2 2.4 V Q3 2.4 V 2.4 V
∗1
Q4S 2.4 V Q4S Q4S 2.4 V
CLK
0.8 V
RAS
2.4 V tCLRAH2
0.8 V tCHRAL2 tCHCASL2 tCHCASH2
CAS
2.4 V 0.8 V
2.4 V
2.4 V
A24 to A00
2.4 V 0.8 V
ROW address
2.4 V 0.8 V
COLUMN-0 0.8 V tCHCAV2
COLUMN-1
COLUMN-2 tCADH2
tCHRAV2
tCLDV2
D31 to D16
(Read)
Read-0 0.8 V Read-1 0.8 V Read-2
2.4 V
2.4 V
DW
(Read)
0.8 V tCHDWL2 tCHDWH2
2.4 V
∗2
D31 to D16
2.4 V 2.4 V 0.8 V
2.4 V
(Write)
2.4 V 0.8 V tCHDV2
Write-0
2.4 V 0.8 V tCHDV2
Write-1
0.8 V 0.8 V
Write-2
*1 : Q4S indicates Q4SR (Read) of Single DRAM cycle or Q4SW (Write) cycle. *2 : indicates the timing when the bus cycle begins from the high speed page mode.
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(11) Hyper DRAM Timing
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C) Symbol tCLRAH3 tCHRAL3 tCHCASL3 tCHCASH3 tCHRAV3 tCHCAV3 tCHRL3 tCHRH3 tCLRL3 tCHDWL3 tCHDWH3 tCHDV3 tCLDV3 tCADH3 CLK DW CLK D31 to D16 CAS D31 to D16 CLK RD Pin name CLK RAS CLK CAS CLK A24 to A00 Condition Value Min. 0 Max. 15 15 n / 2 × tCYC + tCHCASH3 15 15 15 15 15 15 15 15 15 tCYC − 17 Unit Remarks ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter RAS delay time RAS delay time CAS delay time CAS delay time ROW address delay time COLUMN address delay time RD delay time RD delay time RD delay time DW delay time DW delay time Output data delay time CAS ↓→ valid data input time CAS ↓→ data hold time
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tCYC Q1 Q2 2.4 V Q3 2.4 V 2.4 V
∗1
Q4H 0.8 V 2.4 V Q4H Q4H 2.4 V
CLK
0.8 V
RAS
2.4 V tCLRAH3
0.8 V tCHRAL3 tCHCASL3 tCHCASH3 2.4 V 0.8 V
CAS
0.8 V
0.8 V
2.4 V
A24 to A00
2.4 V 0.8 V
ROW address
2.4 V 0.8 V
COLUMN-0 0.8 V
COLUMN-1
COLUMN-2
tCHRAV3
tCHCAV3
∗2
RD
0.8 V tCHRL3 0.8 V tCLRL3 tCLDV3 2.4 V Read-0 0.8 V tCHRH3
2.4 V
(Read)
tCADH3
D31 to D16
(Read)
Read-1 0.8 V
2.4 V
DW
(Read)
0.8 V tCHDWL3 tCHDWH3
2.4 V
∗2
D31 to D16
2.4 V 2.4 V 0.8 V
2.4 V
(Write)
2.4 V 0.8 V tCHDV3
Write-0
2.4 V 0.8 V tCHDV3
Write-1
0.8 V 0.8 V
Write-2
*1 : Q4S indicates Q4HR (Read) of Single DRAM cycle or Q4HW (Write) cycle. *2 : indicates the timing when the bus cycle begins from the high speed page mode.
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(12) CBR Refresh
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C) Symbol tCLRAH tCHRAL tCLCASL tCLCASH Pin name CLK RAS CLK CAS Condition Value Min. Max. 15 15 15 15 Unit ns ns ns ns Remarks
Parameter RAS delay time RAS delay time CAS delay time CAS delay time
tCYC R1
R2 2.4 V 0.8 V
R3
R4 0.8 V
CLK
2.4 V 0.8 V
RAS
2.4 V tCLRAH
0.8 V tCHRAL
CAS
0.8 V tCLCASL
2.4 V tCLCASH
DW
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(13) Self Refresh
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C) Symbol tCLRAH tCHRAL tCLCASL tCLCASH Pin name CLK RAS CLK CAS Condition Value Min. Max. 15 15 15 15 Unit Remarks ns ns ns ns
Parameter RAS delay time RAS delay time CAS delay time CAS delay time
tCYC SR1
SR2 2.4 V 0.8 V 2.4 V
SR3
SR3 0.8 V tCLRAH 2.4 V
CLK
2.4 V
tCHRAL
RAS
0.8 V
CAS
0.8 V tCHCASL tCLCASH
2.4 V
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(14) UART Timing
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C) Symbol Pin name tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX External shift clock mode Internal shift clock mode Condition Value Min. 8 tCYCP −80 100 60 4 tCYCP 4 tCYCP 60 60 Max. 80 150 Unit Remarks ns ns ns ns ns ns ns ns ns
Parameter Serial clock cycle time SCLK ↓→ SOUT delay time Valid SIN → SCLK ↑ SCLK ↑→ valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCLK ↓→ SOUT delay time Valid SIN → SCLK ↑ SCLK ↑→ valid SIN hold time
Notes: • This rating is for AC characteristics in CLK synchronous mode. • tCYCP: A cycle time of peripheral system clock
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• Internal shift clock mode
tSCYC
SCLK
2.4 V 0.8 V tSLOV 2.4 V
SOUT
0.8 V tIVSH 0.8 VCC 0.2 VCC tSHIX
SIN
• External shift clock mode
tSLSH tSHSL 0.8 VCC 0.2 VCC tSLOV 2.4 V
SCLK
SOUT
0.8 V tIVSH 0.8 VCC 0.2 VCC tSHIX
SIN
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(15) Trigger System Input Timing to
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C) Pin name ATG TRG0 to TRG3 Condition Value Min. 5 tCYCP 5 tCYCP Max. Unit Remarks ns ns
Parameter A/D start trigger input time PPG start trigger input time
Symbol tATGX tPTGR
Note : tCYCP: A cycle time of peripheral system clock
tATGX
ATG TRG0 to TRG3
0.2 VCC
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(16) DMA Controller Timing
(VCC = 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C) Pin name DREQ0 to DREQ2 CLK DACK0 to DACK2 CLK EOP0 to EOP2 CLK DACK0 to DACK2 CLK EOP0 to EOP2 Condition Value Min. 2 tCYC Max. 6 6 6 6 n / 2 × tCYC 6 n / 2 × tCYC 6 Unit ns ns ns ns ns ns ns ns ns Remarks
Parameter DREQ input pulse width DACK delay time (Normal bus) (Normal DRAM) EOP delay time (Normal bus) (Normal DRAM) DACK delay time (Single DRAM) (Hyper DRAM) EOP delay time (Single DRAM) (Hyper DRAM)
Symbol tDRWH tCLDL tCLDH tCLEL tCLEH tCHDL tCHDH tCHEL tCHEH
tCYC
CLK
2.4 V 0.8 V
2.4 V 0.8 V
DACK0 to DACK2 EOP0 to EOP2
tCLDL tCLEL 0.8 V
tCLDH tCLEH 2.4 V
(Normal bus) (Normal DRAM)
DACK0 to DACK2 EOP0 to EOP2 (Single DRAM) (Hyper DRAM)
tCHDL tCHEL
0.8 V
2.4 V
tCHEH tCHDH tDRWH
DREQ0 to DREQ2
2.4 V
2.4 V
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5. A/D Converter Block Electrical Characteristics
(AVCC = VCC = +3.0 V to +3.6 V, AVSS = VSS = 0.0 V, AVRH = +3.0 V to +3.6 V, TA = 0 °C to +70 °C) Symbol VOT VFST IAIN VAIN IA IAH IR IRH Pin name AN0 to AN3 AN0 to AN3 AN0 to AN3 AN0 to AN3 AVRH AVCC AVRH AN0 to AN3 Value Min. −1.5 AVRH − 4.5 5.6* AVSS AVSS
1
Parameter Resolution Total error Linearity error Differentiation linearity error Zero transition voltage Full-scale transition voltage Conversion time Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Conversion variance between channels
Typ. 10 +0.5 AVRH − 1.5 0.1 500 500
Max. 10 ±4.0 ±3.0 ±2.5 +2.5 AVRH + 0.5 10 AVRH AVCC 5*2 5* 4
2
Unit bit LSB LSB LSB LSB LSB µs µA V V µA µA µA µA LSB
*1: AVCC = VCC = 3.0 V to 3.6 V(for a machine clock of 25 MHz). *2: Current value for A/D converters not in operation, CPU stop mode (VCC = AVCC = AVRH = 3.6 V) Notes: • As the absolute value of AVRH decreases, relative error increases. • Output impedance of external circuit of analog input under following conditions; Output impedance of external circuit < 7 kΩ. If output impedance of external circuit is too high, analog voltage sampling time may be too short for accurate sampling.
•Analog input circuit model plan Sample and hold circuit
C0
Analog input
RON1 RON1 : 5 kΩ RON2 : 620 Ω RON3 : 620 Ω RON4 : 480 Ω C0 : 2 pF C1 : 2 pF RON2 RON3 RON4 C1
Comparator
RONX, CX are preliminary value.
Note: Listed values are for reference purposes only. 88
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6. A/D Converter Glossary
• Resolution The smallest change in analog voltage detected by A/D converter. • Linearity error A deviation of actual conversion characteristic from a line connecting the zero-traction point (between “00 0000 0000” ↔ “00 0000 0001”) to the full-scale transition point (between “11 1111 1110” ↔ “11 1111 1111”). • Differential linearity error A deviation of a step voltage for changing the LSB of output code from ideal input voltage Linearity error
3FF 3FE {1 LSB × (N − 1) + VOT} 3FD
Differential linearity error
Ideal value
N+1
Actual conversion characteristic
Actual conversion characteristic
Digital output
Digital output
VFST
(Measured value)
004 003 002
N
(Measured value) Actual conversion characteristic Ideal value
VNT
N−1 V(N + 1)T VNT
(Measured
001 VOT AVRL
(Measured value)
AVRH
N−2
(Measured value) value) Actual conversion characteristic
AVRH
AVRL
Analog input Linearity error of digital output N = VNT − {1 LSB × (N − 1) + VOT} 1 LSB = V (N + 1) T − VNT 1 LSB −1
Analog input [LSB]
Differential linearity error of digital output N 1 LSB = VFST − VOT 1022
[LSB]
[V] AVRH − AVRL 1024 [V]
1 LSB (Ideal value) =
VOT : A voltage for causing transition of digital output from (000) H to (001) H VFST : A voltage for causing transition of digital output from (3FE) H to (3FF) H VNT : A voltage for causing transition of digital output from (N − 1) to N
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• Total error A difference between actual value and theoretical value. The overall error includes zero-transition error, fullscale transition error and linearity error.
Total error
3FF 1.5 LSB 3FE 3FD
Actual conversion characteristic
{1 LSB × (N − 1) + 0.5 LSB}
Digital output
004 003 002 001 0.5 LSB AVRL AVRH
(Measured value) Actual conversion characteristic Ideal value
VNT
Analog input
Total error of digital output N =
VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB
[LSB]
VOT (Ideal value) = AVRL + 0.5 LSB [V] VFST (Ideal value) = AVRH − 1.5 LSB [V] VNT : A voltage for causing transition of digital output from (N − 1) to N
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s REFERENCE DATA
(1) “H” level output voltage “H” level output voltage vs. power supply voltage
4.00 3.80 3.60 3.40 3.20 3.00 2.80 2.60 2.40 2.20 2.00 2.7
(2) “L” level output voltage “L” level output voltage vs. power supply voltage
140.0 135.0 130.0 VOL (V) 125.0 120.0 150.0 110.0 105.0 100.0 2.7
VOH (V)
3.0
3.3 VCC (V)
3.6
3.9
3.0
3.3 VCC (V)
3.6
3.9
(3) “H” level input / “L” level input voltage (CMOS input) Input level vs. power supply voltage (CMOS )
3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 2.7
(4) “H”level input / “L” level input voltage (Hysteresys input) Input level vs. power supply voltage (Hysteresys )
3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 2.7 VIH
VIN (V)
VIH VIL
VIN (V)
VIL
3.0
3.3 VCC (V)
3.6
3.9
3.0
3.3 VCC (V)
3.6
3.9
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(5) Power supply current Power supply current vs. voltage
100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 2.7
Power supply current (sleep mode) vs. power supply current
60.0 50 MHz ICCS (mA) 50.0 40.0 30.0 20.0 10.0 25 MHz 50 MHz
ICC (mA)
25 MHz
3.0
3.3 VCC (V)
3.6
3.9
0.0 2.7
3.0
3.3 VCC (V)
3.6
3.9
Power supply current (stop mode) vs. power supply voltage
100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 2.7
A/D conversion block Power supply current vs. power supply voltage (25 MHz)
450 400 350 300 IA (µA) 250 200 150 100 50 0 2.7
ICCH (µA)
3.0
3.3 VCC (V)
3.6
3.9
3.0
3.3 AVCC (V)
3.6
3.9
A/D conversion block reference voltage supply current vs. voltage (25 MHz)
300 280 260 IR (µA) 240 220 200 180 160 2.7 3.0 3.3 AVRH (V) 3.6 3.9
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(6) Pull-up / pull-down resistance Pull-down resistance vs. power supply voltage
100.0
Pull-up resistance vs. power supply voltage
100.0
R (Ω)
R (Ω) 10.0 2.7 10.0 2.7
3.0
3.3 VCC (V)
3.6
3.9
3.0
3.3 VCC (V)
3.6
3.9
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s ORDERING INFORMATION
Part number MB91107PFV MB91108PFV Package 120-pin Plastic LQFP (FPT-120P-M21) Remarks
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s PACKAGE DIMENSIONS
120-pin Plastic LQFP (FPT-120P-M21)
18.00±0.20(.709±.008)SQ 16.00±0.10(.630±.004)SQ
90 61
91
60
0.08(.003)
Details of "A" part 1.50 –0.10 .059 –.004
+0.20 +.008
(Mounting height)
INDEX
0~8°
120 31
"A" 0.10±0.05 (.004±.002) (Stand off) 0.25(.010)
LEAD No.
1
30
0.50(.020)
0.22±0.05 (.009±.002)
0.08(.003)
M
0.145 .006
+0.05 –0.03 +.002 –.001
0.60±0.15 (.024±.006)
C
2001 FUJITSU LIMITED F120033S-c-3-3
Dimensions in mm (inches)
95
MB91107/108
FUJITSU LIMITED
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