FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16506-1E
32-bit Microcontroller
CMOS
FR60Lite MB91230 Series
MB91233L/MB91F233/MB91F233L/MB91V230
s DESCRIPTION
The MB91230 series is a line of standard microcontrollers, based on a 32-bit high-performance RISC CPU and containing variety of I/O resources, for embedded control applications which require high CPU performance at high speed processing. Audio motor control storage : Designed to specifications for embedded control applications which high CPU performance power processing. The MB91230 series belongs to the FR60Lite family.
s FEATURES
• 32-bit RISC, load/store architecture with a 5 stage pipeline • Maximum operating frequency: 33.6 MHz (oscillation frequency = 4.2 MHz, oscillation frequency 8-multiplier (PLL clock multiplication method) ) • 16-bit fixed length instructions (basic instructions) • Execution speed of instructions : 1 instruction per cycle (Continued)
s PACKAGES
401-pin Ceramic PGA 120-pin Plastic LQFP 128-pin plastic FLGA
(PGA-401C-A02)
(FPT-120P-M05)
(LGA-128P-M01)
MB91230 Series
(Continued) • Memory-to-memory transfer, bit handling, and barrel shift instructions, etc. : Instructions suitable for embedded applications • Function entry/exit instructions, multiple-register load/store instructions : Instructions adapted for C-language • Register interlock function : Facilitates coding in assembler • Built-in multiplier with instruction-level support - 32-bit multiplication with sign : 5 cycles - 16-bit multiplication with sign : 3 cycles • Interrupt (PC and PS save) : 6 cycles (16 priority levels) • Harvard architecture allowing program access and data access to be executed simultaneously • Instruction compatible with FR family • Capacity of built-in ROM and ROM type - MASK ROM : 256 KB - FLASH ROM : 256 KB • Capacity of built-in RAM : 16 KB • General-purpose ports : Maximum 98 ports (including N-ch open-drain port : 4 ports) • A/D converter (series-parallel type) - Resolution : 10-bit : 8 ch (4 ch × 2 unit) - Conversion time : 1.69 µs (Minimum conversion time) • D/A converter (R-2R type) - Resolution : 8-bit : 2 ch (independence) - Conversion speed : 0.6 µs (when load capacitance 20 pF) • External interrupt input : 16 ch • Bit search module (for REALOS) - Function for searching the MSB (Upper bit) in each word for the first “0” or “1” inverted point • UART (full-duplex double buffer) : 4 ch - Selectable parity On/Off - Asynchronous (start-stop synchronized) or clock-synchronous communications selectable - Internal timer for dedicated baud rate (U-timer) on each channel - External clock can be used as transfer clock - Error detection function for parity, frame and overrun • PPG : 16-bit × 6 ch • Up/down counter : 2 ch (8-bit × 2 ch or 16-bit × 1 ch) • Reload timer : 16-bit × 4 ch • Free-run timer : 16-bit × 2 ch • Watch timer : 15-bit × 1 ch • PWC : 8-bit × 2 ch • Input capture : 2 ch (interface with free-run timer 0) • Output compare : 4 ch (free-run timer 0 and output compare unit 0/1 cooperate, free-run timer 1 and output compare units 2/3) • LCD controller : SEG00 to SEG31/COM0 to COM3 (also serving as a port) • Clock monitor (peripheral clock output function) : 1 ch • Timebase/watchdog timer (26-bit) • Real-time clock (counting even with the real-time clock stopped) • Low Power Consumption Mode • Sleep/stop function • Package : LQFP-120, FLGA-128 • Technology : CMOS 0.35 µm • Power supply • Dual power supply configuration [internal logic 3.3 V, I/O 5.5 V(3.3 V for ADC and DAC input/output)]
Note : Do not set the external bus mode in which the MB91230 series cannot operate.
2
MB91230 Series
s PIN ASSIGNMENT
• MB91233L, MB91F233, MB91F233L
(TOP VIEW)
P25/SOT2 P24/SIN2 P23/PWI1/OP3 P22/PWI0/OP2 P21/CKI1/OP1 P20/CKI0/OP0 P17/INT7 P16/INT6 P15/INT5 P14/INT4 P13/INT3 P12/INT2 X0 X1 VSS VCC P11/INT1 P10/INT0 P07/IC1 P06/IC0 P05/SCK1 P04/SOT1 P03/SIN1 P02/SCK0 P01/SOT0 P00/SIN0 V3 V2 V1 V0 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
P26/SCK2 P27/SIN3 P30/SOT3 P31/SCK3 P32/AIN0 P33/BIN0 P34/ZIN0 P35/AIN1 P36/BIN1 P37/ZIN1 P40/PPG0 P41/PPG1 X0A X1A VCC3B VSS VCC3 P42/PPG2 P43/PPG3 P44/TOT0 P45/TOT1 P46/TOT2 P47/CKOT P50/INT8 P51/INT9 P52/INT10 P53/INT11/PPG4 P54/INT12/PPG5 P55/INT13/TIN2 P56/INT14/TIN1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
INIT MD0 MD1 MD2 P73/COM3 P72/COM2 P71/COM1 P70/COM0 P67/SEG31∗ P66/SEG30∗ P65/SEG29∗ P64/SEG28∗ PB3/SEG27 PB2/SEG26 VSS VCC PB1/SEG25 PB0/SEG24 PA7/SEG23 PA6/SEG22 PA5/SEG21 PA4/SEG20 PA3/SEG19 PA2/SEG18 PA1/SEG17 PA0/SEG16 P97/SEG15 P96/SEG14 P95/SEG13 P94/SEG12
P57/INT15/TIN0/ADTG0 PF3/TOT3 PF4/TIN3/ADTG1 PD0/DA0 PD1/DA1 AVCC AVRH AVSS PC0/AN0 PC1/AN1 PC2/AN2 PC3/AN3 PC4/AN4 PC5/AN5 PC6/AN6 PC7/AN7 VSS VCC3IO P80/SEG0 P81/SEG1 P82/SEG2 P83/SEG3 P84/SEG4 P85/SEG5 P86/SEG6 P87/SEG7 P90/SEG8 P91/SEG9 P92/SEG10 P93/SEG11
* : Open-drain
(FPT-120P-M05)
(Continued)
3
MB91230 Series
(Continued) • MB91F233L
M L K J H G F E D C B A
M1 L1 K1 J1 H1 G1 F1 E1 D1 C1 B1 A1
M2 L2 K2 J2 H2 G2 F2 E2 D2 C2 B2 A2
M3 L3 K3 J3 H3 G3 F3 E3 D3 C3 B3 A3
M4 L4 K4 J4 H4 G4
M5 L5 K5 J5
M6 L6 K6 J6
M7 L7 K7 J7
M8 L8 K8 J8
M9 L9 K9 J9 H9 G9
M10 M11 M12 L10 K10 J10 H10 G10 F10 E10 D10 C10 B10 A10 L11 K11 J11 H11 G11 F11 E11 D11 C11 B11 A11 L12 K12 J12 H12 G12 F12 E12 D12 C12 B12 A12
TOP VIEW F4 E4 D4 C4 B4 A4 D5 C5 B5 A5 D6 C6 B6 A6 D7 C7 B7 A7 D8 C8 B8 A8 F9 E9 D9 C9 B9 A9
1
2
3
4
5
6
7
8
9
10
11
12
INDEX (LGA-128P-M01)
4
MB91230 Series
Pin correspondence table of LQFP-120 and FLGA-128 in MB91230 series (LGA-128P-M01) FLGA-128 FLGA-128 FLGA-128 LQFP-120 No. Signal LQFP-120 No. Signal LQFP-120 No. No. (JEDEC name No. (JEDEC name No. (JEDEC No.) No.) No.) 1 120 117 114 109 107 103 100 97 94 91 4 118 115 112 110 106 104 99 96 92 88 90 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 P26/SCK2 P25/SOT2 P22/PWI0/ OP2 P17/INT7 *5 P12/INT2 X1 P10/INT0 P05/SCK1 P02/SCK0 V3 V0 P31/SCK3 P23/PWI1/ OP3 P20/CKI0/ OP0 P15/INT5 P13/INT3 VSS P11/INT1 P04/SOT1 P01/SOT0 V1 MD1 INIT 98 93 85 87 10 6 8 119 111 101 95 89 86 82 84 13 9 12 5 81 83 80 C9 C10 C11 C12 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E9 E10 E11 E12 P03/SIN1 V2 P72/COM2 MD2 P37/ZIN1 P33/BIN0 P35/AIN1 P24/SIN2 P14/INT4 *5 P06/IC0 P00/SIN0 MD0 P73/COM3 P67/ SEG31*1 P71/COM1 X0A P36/BIN1 P41/PPG1 P32/AIN0 P66/ SEG30*1 P70/COM0 P65/ SEG29*1 *5 18 15 *2 17 71 75 74 77 21 19 23 20 65 72 69 73 24 22 26 29 35 40 47 50 G1 G2 G3*4 G4 G9 G10 G11 G12 H1 H2 H3 H4 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8
Signal name P42/PPG2 VCC3B VCC3*4 VCC3 PA6/ SEG22 VCC PB1/ SEG25 PB2/ SEG26 P45/TOT1 P43/PPG3 P47/CKOT P44/TOT0 PA0/ SEG16 PA7/ SEG23 PA4/ SEG20 PB0/ SEG24 P50/INT8 P46/TOT2 P52/INT10 P55/INT13/ TIN2 PD1/DA1 PC1/AN1 VSS P81/SEG1
(Continued)
5
MB91230 Series
(Continued)
LQFP-120 No. 7 2 3 116 FLGA-128 No. (JEDEC No.) C1 C2 C3 C4 Signal name P34/ZIN0 P27/SIN3 P30/SOT3 P21/CKI1/ OP1 P16/INT6 LQFP-120 No. 16 14 11 FLGA-128 No. (JEDEC No.) F1 F2 F3 F4 Signal name VSS *5 X1A P40/PPG0 PB3/ SEG27 P64/ SEG28*1 VSS *5 AVCC AVRL*4 PC4/AN4 PC6/AN6 P80/SEG0 P83/SEG3 P86/SEG6 P91/SEG9 P97/ SEG15 P57/ INT15/ TIN0/ ADTG0 PD0/DA0 LQFP-120 No. 59 68 66 70 FLGA-128 No. (JEDEC No.) J9 J10 J11 J12 Signal name P92/ SEG10 PA3/ SEG19 PA1/ SEG17 PA5/ SEG21 P53/ INT11/ PPG4 P51/INT9 PF4/TIN3/ ADTG1 AVSS AVRH PC0/AN0 PC3/AN3 PC7/AN7 *5 P82/SEG2 P85/SEG5 P90/SEG8 P93/ SEG11
113
C5
78
F9
27
K1
108 105 102 41 44 48 53 56 63 62 67
C6 C7 C8 K5 K6 K7 K8 K9 K10 K11 K12
X0 VCC P07/IC1 PC2/AN2 PC5/AN5 VCC3IO P84/SEG4 P87/SEG7 P96/ SEG14 P95/ SEG13 PA2/ SEG18 P56/ INT14/ TIN1 P54/ INT12/ PPG5 PF3/TOT3
79 76 36 *3 43 45 49 52 55 58
F10 F11 F12 L4 L5*4 L6 L7 L8 L9 L10 L11
25 33 38 37 39 42 46 51 54 57
K2 K3 K4 M3 M4 M5 M6 M7 M8 M9 M10
30
L1
64
L12
60
M11
28
L2
31
M1
61
M12
P94/ SEG12
32 *1 : Open-drain
L3
34
M2
*2 : Connected to pin 17(VCC3) on the LQFP120 version *3 : Connected to pin 38(AVSS) on the LQFP120 version *4 : Signals added to the FLGA version *5 : NC pin on the FLGA version 6
MB91230 Series
s PIN DESCRIPTION
Pin no. LQFP FLGA Pin name Circuit type Description UART2 clock input/output. This function is valid when corresponding bit of PFR2 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR2 register is set to port function. UART3 data input. When using this function, corresponding bit of DDR2 register is set to input. General purpose input/output port. This function is always valid. UART3 data output. This function is valid when corresponding bit of PFR3 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR3 register is set to port function. UART3 clock input/output. This function is valid when corresponding bit of PFR3 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR3 register is set to port function. Up/down counter 0 AIN input. When using this function, corresponding bit of DDR3 register is set to input. General purpose input/output port. This function is alwais valid. Up/down counter 0 BIN input. When using this function, corresponding bit of DDR3 register is set to input. General purpose input/output port. This function is always valid. Up/down counter 0 ZIN input. When using this function, corresponding bit of DDR3 register is set to input. General purpose input/output port. This function is always valid. Up/down counter 1 AIN input. When using this function, corresponding bit of DDR3 register is set to input. General purpose input/output port. This function is always valid.
SCK2 1 A1 P26 D
SIN3 2 C2 P27 D
SOT3 3 C3 P30 B
SCK3 4 B1 P31 B
AIN0 5 E4 P32 B
BIN0 6 D2 P33 B
ZIN0 7 C1 P34 B
AIN1 8 D3 P35 B
(Continued)
7
MB91230 Series
Pin no. LQFP FLGA
Pin name
Circuit type
Description Up/down counter 1 BIN input. When using this function, corresponding bit of DDR3 register is set to input. General purpose input/output port. This function is always valid. Up/down counter 1 ZIN input. When using this function, corresponding bit of DDR3 register is set to input. General purpose input/output port. This function is always valid. PPG0 output. This function is valid when corresponding bit of PFR4 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR4 register is set to port function. PPG1 output. This function is valid when corresponding bit of PFR4 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR4 register is set to port function. Sub-clock oscillation pin (32 kHz) Power supply pin for backup (RTC) Power supply pin (GND) Power supply pin (3.3 V internal logic) PPG2 output. This function is valid when corresponding bit of PFR4 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR4 register is set to port function. PPG3 output. This function is valid when corresponding bit of PFR4 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR4 register is set to port function.
BIN1 9 E2 P36 B
ZIN1 10 D1 P37 B
PPG0 11 F4 P40 D
PPG1 12 E3 P41 13 14 15 16 17 E1 F3 G2 F1 G4 X0A X1A VCC3B VSS VCC3 PPG2 18 G1 P42 D D
PPG3 19 H2 P43 D
(Continued)
8
MB91230 Series
Pin no. LQFP FLGA
Pin name
Circuit type
Description Reload timer 0 output port. This function is valid when corresponding bit of PFR4 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR4 register is set to port function. Reload timer 1 output port. This function is valid when corresponding bit of PFR4 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR4 register is set to port function. Reload timer 2 output port. This function is valid when corresponding bit of PFR4 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR4 register is set to port function. Clock monitor function output pin. This function is valid when corresponding bit of PFR4 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR4 register is set to port function. External interrupt input. When using this function, corresponding bit of DDR5 register is set to input. General purpose input/output port. This function is always valid. External interrupt input. When using this function, corresponding bit of DDR5 register is set to input. General purpose input/output port. This function is always valid. External interrupt input. When using this function, corresponding bit of DDR5 register is set to input. General purpose input/output port. This function is always valid.
TOT0 20 H4 P44 D
TOT1 21 H1 P45 D
TOT2 22 J2 P46 D
CKOT 23 H3 P47 D
INT8 24 J1 P50 C
INT9 25 K2 P51 C
INT10 26 J3 P52 C
(Continued)
9
MB91230 Series
Pin no. LQFP FLGA
Pin name
Circuit type
Description PPG4 output. This function is valid when corresponding bit of PFR5 register is set to peripheral function. External interrupt input. This function is enabled when corresponding bit of PFR5 register is set to port function and corresponding bit of DDR5 resister is set to input. General purpose input/output port. This function is valid when corresponding bit of PFR5 register is set to port function. PPG5 output. This function is valid when corresponding bit of PFR5 register is set to peripheral function. External interrupt input. This function is enabled when corresponding bit of PFR5 register is set to port function and corresponding bit of DDR5 resister is set to input. General purpose input/output port. This function is valid when corresponding bit of PFR5 register is set to port function. Reload timer 2 event input pin. This function is valid when corresponding bit of DDR5 register is set to input.
PPG4
27
K1
INT11
C
P53
PPG5
28
L2
INT12
C
P54
TIN2
29
J4
INT13
C
External interrupt input. This function is valid when corresponding bit of DDR5 register is set to input. General purpose input/output port. This function is always valid. Reload timer 1 event input pin. This function is valid when corresponding bit of DDR5 register is set to input.
P55
TIN1
30
L1
INT14
C
External interrupt input. This function is valid when corresponding bit of DDR5 register is set to input. General purpose input/output port. This function is always valid.
P56
(Continued)
10
MB91230 Series
Pin no. LQFP FLGA
Pin name
Circuit type
Description External trigger input pin of A/D converter 0. This function is valid when corresponding bit of DDR5 register is set to input. Reload timer 0 event input pin. This function is valid when corresponding bit of DDR5 register is set to input. External interrupt input. This function is valid when corresponding bit of DDR5 register is set to input. General purpose input/output port. This function is always valid. Reload timer 3 output port. This function is valid when corresponding bit of PFRF register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFRF register is set to port function. External trigger input pin of A/D converter 1. This function is valid when corresponding bit of DDRF register is set to input.
ADTG0
TIN0 31 M1 INT15 C
P57
TOT3 32 L3 PF3 D
ADTG1
33
K3
TIN3
D
Reload timer 3 event input pin. This function is valid when corresponding bit of DDRF register is set to input. General purpose input/output port. This function is always valid. D/A converter 0 output pin. This function is valid when corresponding bit of PFRD register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFRD register is set to port function. D/A converter 1 output pin. This function is valid when corresponding bit of PFRD register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFRD register is set to port function. Analog power supply (for A/D, D/A converter) . Analog reference power supply (for A/D, D/A converter) . GND level input for analog circuit (for A/D, D/A converter) .
PF4
DA0 34 M2 PD0 F
DA1 35 J5 PD1 36 37 38 L4 M3 K4 AVCC AVRH AVSS F
(Continued)
11
MB91230 Series
Pin no. LQFP FLGA
Pin name
Circuit type
Description Analog input pin for A/D converter. This function is valid when corresponding bit of PFRC register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFRC register is set to port function. Power supply pin (GND) Power supply pin (analog-shared pin I/O) LCD controller/driver LCD segment output pin. This function is valid when corresponding bit of PFR8 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR8 register is set to port function. LCD controller/driver LCD segment output pin. This function is valid when corresponding bit of PFR9 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR9 register is set to port function. LCD controller/driver LCD segment output pin. This function is valid when corresponding bit of PFRA register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFRA register is set to port function. LCD controller/driver LCD segment output pin. This function is valid when corresponding bit of PFRB register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFRB register is set to port function. Power supply pin (5 V I/O MB91V230/F233) Power supply pin (3.3 V internal logic, I/O MB91F233L/ MB91233L) Power supply pin (GND) LCD controller/driver LCD segment output pin. This function is valid when corresponding bit of PFRB register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFRB register is set to port function.
39 to 46
M4, J6, K5, M5, L6, K6, L7, M6
AN0 to AN7 E PC0 to PC7 VSS VCC3IO SEG0 to SEG7 I P80 to P87
47 48
J7 K7
49 to 56
L8, J8, M8, L9, K8, M9, L10, K9
57 to 64
M10, L11, J9, M11, M12, K11, K10, L12
SEG8 to SEG15 I P90 to P97
65 to 72
H9, J11, K12, J10, H11, J12, G9, H10
SEG16 to SEG23 I PA0 to PA7
SEG24, SEG25 73, 74 H12, G11 PB0, PB1 I
75 76
G10 F11
VCC VSS SEG26, SEG27
77, 78
G12, F9 PB2, PB3
I
(Continued)
12
MB91230 Series
Pin no. LQFP FLGA
Pin name SEG28 to SEG31
Circuit type
Description LCD controller/driver LCD segment output pin. This function is valid when corresponding bit of PFR6 register is set to peripheral function. General purpose input/output port. (open-drain) This function is valid when corresponding bit of PFR6 register is set to port function. LCD controller/driver common pins. This function is valid when corresponding bit of PFR7 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR7 register is set to port function. Mode input pin. External reset input. LCD controller/driver reference power supply input pins. UART0 data input. When using this function, corresponding bit of DDR0 register is set to input. General purpose input/output port. This function is always valid. UART0 data output. This function is valid when corresponding bit of PFR0 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR0 register is set to port function. UART0 clock input/output. This function is valid when corresponding bit of PFR0 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR0 register is set to port function. UART1 data input. This function is valid when corresponding bit of DDR0 register is set to input. General purpose input/output port. This function is always valid.
79 to 82
F10, E11, E9, D11
J P64 to P67
83 to 86
E10, D12, C11, D10
COM0 to COM3 I P70 to P73 MOD2, MOD1, MOD0 INIT V0 to V3
87 to 89 90 91 to 94
C12, B11, D9 B12 A12, B10, C10, A11
H G
SIN0 95 D8 P00 D
SOT0 96 B9 P01 D
SCK0 97 A10 P02 D
SIN1 98 C9 P03 D
(Continued)
13
MB91230 Series
Pin no. LQFP FLGA
Pin name Circuit type
Description UART1 data output. This function is valid when corresponding bit of PFR0 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR0 register is set to port function. UART1 clock input/output. This function is valid when corresponding bit of PFR0 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR0 register is set to port function. Input capture input 0. This function is valid when corresponding bit of DDR0 register is set to input. General purpose input/output port. This function is always valid. Input capture input 1. This function is valid when corresponding bit of DDR0 register is set to input. General purpose input/output port. This function is always valid. External interrupt input. This function is valid when corresponding bit of DDR1 register is set to input. General purpose input/output port. This function is always valid. External interrupt input. This function is valid when corresponding bit of DDR1 register is set to input. General purpose input/output port. This function is always valid. Power supply pin (5 V I/O MB91V230/F233)
SOT1 99 B8 P04 D
SCK1 100 A9 P05 D
IC0 101 D7 P06 D
IC1 102 C8 P07 D
INT0 103 A8 P10 A
INT1 104 B7 P11 A
105 106 107 108
C7 B6 A7 C6
VCC VSS X1 X0
Power supply pin (3.3 V internal logic, I/O MB91F233L/ MB91233L) Power supply pin (GND) Main-clock oscillation pin
(Continued)
14
MB91230 Series
Pin no. LQFP FLGA
Pin name Circuit type
Description External interrupt input. This function is valid when corresponding bit of DDR1 register is set to input. General purpose input/output port. This function is always valid. External interrupt input. This function is valid when corresponding bit of DDR1 register is set to input. General purpose input/output port. This function is always valid. External interrupt input. This function is valid when corresponding bit of DDR1 register is set to input. General purpose input/output port. This function is always valid. External interrupt input. This function is valid when corresponding bit of DDR1 register is set to input. General purpose input/output port. This function is always valid. External interrupt input. This function is valid when corresponding bit of DDR1 register is set to input. General purpose input/output port. This function is always valid. External interrupt input. This function is valid when corresponding bit of DDR1 register is set to input. General purpose input/output port. This function is always valid. External clock input pin for free-run timer 0. This function is enabled when corresponding bit of PFR2 register is set to port function and corresponding bit of DDR2 register is set to input.
INT2 109 A6 P12 A
INT3 110 B5 P13 A
INT4 111 D5 P14 A
INT5 112 B4 P15 A
INT6 113 C5 P16 A
INT7 114 A4 P17 A
CKI0
115
B3
OP0
D
Output compare 0 output pin. This function is valid when corresponding bit of PFR2 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR2 register is set to port function.
P20
(Continued)
15
MB91230 Series
(Continued) Pin no.
LQFP FLGA
Pin name Circuit type
Description External clock input pin for free-run timer 1. This function is enabled when corresponding bit of PFR2 register is set to port function and corresponding bit of DDR2 register is set to input.
CKI1
116
C4
OP1
D
Output compare1 output pin. This function is valid when corresponding bit of PFR2 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR2 register is set to port function. Pulse width counter 0 input. This function is enabled when corresponding bit of PFR2 register is set to port function and corresponding bit of DDR2 register is set to input.
P21
PWI0
117
A3
OP2
D
Output compare2 output pin. This function is valid when corresponding bit of PFR2 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR2 register is set to port function. Pulse width counter 1 input. This function is enabled when corresponding bit of PFR2 register is set to port function and corresponding bit of DDR2 register is set to input.
P22
PWI1
118
B2
OP3
D
Output compare3 output pin. This function is valid when corresponding bit of PFR2 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR2 register is set to port function. UART2 data input. This function is valid when corresponding bit of DDR2 register is set to input. General purpose input/output port. This function is always valid. UART2 data output. This function is valid when corresponding bit of PFR2 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR2 register is set to port function. Analog reference power supply (for A/D converter) Unconnected pin.
P23
SIN2 119 D4 P24 D
SOT2 120 A2 P25 (38) 16 L5 A5, D6, E12, F2, F12, M7 AVRL NC D
MB91230 Series
s I/O CIRCUIT TYPE
Type Circuit type Remarks With Pull-up control (50 kΩ)
P P N
Pull-up control Output drive Pch Output drive Nch Hysteresis input Standby control
CMOS level output IOH = 4 mA/IOL = 4 mA CMOS hysteresis input (with standby control)
A
With Pull-up control (50 kΩ)
P P N
Pull-up control Output drive Pch Output drive Nch Hysteresis input Standby control Test pin for FLASH Analog SW control
CMOS level output IOH = 4 mA/IOL = 4 mA CMOS hysteresis input (with standby control) Test pin for FLASH
B
CMOS level output
P
Output drive Pch Output drive Nch Hysteresis input Standby control
CMOS hysteresis input (with standby control)
C
N
P N
Output drive Pch Output drive Nch Hysteresis input Standby control Test pin for FLASH Analog SW control
CMOS level output IOH = 4 mA/IOL = 4 mA CMOS hysteresis input (with standby control) Test pin for FLASH
D
(Continued)
17
MB91230 Series
Type
Circuit type
Remarks CMOS level output IOH = 4 mA/IOL = 4 mA CMOS hysteresis input (with standby control) Also serving as an analog input
P N
Output drive Pch Output drive Nch Hysteresis input Standby control Analog input Analog SW control
E
P N
Output drive Pch Output drive Nch Hysteresis input Standby control Analog input Analog SW control
CMOS level output IOH = 4 mA/IOL = 4 mA CMOS hysteresis input (with standby control) Also serving as an analog input
F
With Pull-up control (50 kΩ) CMOS hysteresis input
P P
G
N
Hysteresis input High withstand-voltage input CMOS input (hysteresis level)
N N
Low impedance input High impedance input
H
N N
High voltage detection output
(Continued)
18
MB91230 Series
(Continued) Type
Circuit type
Remarks CMOS level output IOH = 4 mA/IOL = 4 mA CMOS hysteresis input (with standby control) LCDC output
P N
Output drive Pch Output drive Nch Hysteresis input Standby control LCDC output
I
P N
CMOS level output (open-drain) IOL = 20 mA CMOS hysteresis input (with standby control) LCDC output Output drive Nch Hysteresis input Standby control LCDC output Oscillation circuit
J
X1
Oscillation output K
X0
Standby control
19
MB91230 Series
s HANDLING DEVICES
Preventing Latchup Latch-up may occur in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output pin or if an above-rating voltage is applied between VCC and VSS. A latchup, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, be very careful not to exceed the absolute maximum rating. Treatment of Unused Pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a pullup or pull-down resistor. About Power Supply Pins In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS near this device. About Crystal Oscillator Circuit Noise near the X0 and X1 pins may cause the device to malfunction. Design the printed circuit board so that X0, X1, the crystal oscillator (or ceramic oscillator) , and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended to design the PC board artwork with the X0 and X1 pins surrounded by ground plane because stable operation can be expected with such a layout. Treatment of NC and OPEN Pins Pins marked as NC and OPEN must be left open-circuit. About Mode Pins (MD0 to MD2) These pins should be connected directly to VCC or VSS. To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that the distance between the mode pins and VCC or VSS is as short as possible and the connection impedance is low. Operation at Start-up Be sure to execute setting initialized reset (INIT) with INIT pin immediately after start-up. Also, in order to provide the oscillation stabilization wait time for the oscillation circuit immediately after start-up, hold the “L” level input to the INIT pin for the required stabilization wait time. (For INIT via the INIT pin, the oscillation stabilization wait time setting is initialized to the minimum value) . About Oscillation Input at Power On When turning the power on, maintain clock input untill the device is released from the oscillation stabilization wait state. 20
MB91230 Series
Clock Control Block Input the “L” signal to the INIT pin to assure the clock oscillation stabilization wait time. Switch Shared Port Function To switch between the use as a port and the use as a dedicated pin, use the port function register (PFR) . Low Power Consumption Mode To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the TBCR : timebse counter control register) and be sure to use the following sequence (LDI #value_of_standby, R0) : value_of_standby is write data to STCR. (LDI #_STCR, R12) : _STCR is address (481H) of STCR. STB R0, @R12 : Writing to standby control register (STCR) LDUB @R12, R0 : STCR read for synchronous standby LDUB @R12, R0 : Dummy re-read of STCR NOP : NOP × 5 for arrangement of timing NOP NOP NOP NOP In addition, please set I flag, ILM, and ICR to diverge to the interruption handler that is the return factor after the standby returns. • Please do not do the following when the monitor debugger is used. • Break point setting for above instruction lines • Step execution for above instruction lines Power-on sequence for dual-power-supply model • Notes on the power-on and power-off sequences Power-on sequence : Vcc3B, Vcc3→Vcc→Vcc3IO, AVRH, V0-V3 Power-off sequence : Vcc3IO, AVRH, V0-V3 Vcc3→Vcc→Vcc3B, Vcc3 When VCC is turned on earlier, a potential difference between VCC and VCC3 must fall within 3.6 V. • The LCD power supply V3 must not exceed VCC in voltage. Apply V3 after turning on VCC3. • Turn on VCC3 before applying the analog power supply AVCC or an analog signal.
21
MB91230 Series
Notes on the PS register As the PS register is processed by some instructions in advance, exception handling below may cause the interrupt handling routine to break when the debugger is used or the display contents of flags in the PS register to be updated. As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs operations before and after the EIT as specified in either case. • The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS instruction is (a) acceptance of a user interrupt, (b) single-stepped, or (c) breaks in response to a data event or emulator menu : 1) The D0 and D1 flags are updated in advance. 2) An EIT handling routine (user interrupt or emulator) is executed. 3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed, and the D0 and D1 flags are updated to the same values as in 1). • The following operations are performed when the ORCCR/STILM/MOVRi and PS instructions are executed to allow the interrupt. 1) The PS register is updated in advance. 2) An EIT handling routine (user interrupt) is executed. 3) Upon returning from the EIT, the above instructions are executed, and the PS register is updated to the same value as in 1). Watchdog Timer The watchdog timer built in this model monitors a program that it defers a reset within a certain period of time. The watchdog timer resets the CPU if the program runs out of controls, preventing the reset defer function from being executed. Once the function of the watchdog timer is enabled, therefore, the watchdog timer keeps on operating programs until it resets the CPU. As an exception, the watchdog timer defers a reset automatically under the condition in which the CPU stops program execution. For those conditions to which this exception applies, see the function description of watchdog timer. Step execution of RETI instruction If an interrupt occurs frequently during step execution, the corresponding interrupt handling routine is executed repeatedly after step execution. This will prevent the main routine and low-interrupt-level programs from being executed. Do not execute step of RETI instruction for escape. Disable the corresponding interrupt and execute debugger when the corresponding interrupt routine no longer needs debugging. Operand Break Do not apply a data event break to access to the area containing the address of a system stack pointer.
22
MB91230 Series
s BLOCK DIAGRAM
FR60Lite CPU Core 32 Bit Search 32
ROM/FLASH RAM Clock Control (Clock, Standby, Reset, Watchdog, TBT, Main-ClockStabilizationTimer) Watch Timer VCC3B Real Time Clock Interruption Controller INT0 to INT15 External interrupt 0 to 15 UART 0 to 3
Bus Converter External Memory I/F (MB91230 is not supported)
32 16 32 Adapter
X0, X1 MD0 to MD2 INIT X0A, X1A
16
Clock Monitor
PORT I/F
VCC PORTs CKOT COM0 to COM3 SEG0 to SEG31 V0 to V3 AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1 TO0 to TO3
LCDC, Driver, Internal Reference Voltage
Up/Down Counter 0, 1 Reload Timer 0 to 3 PPG 0 to 5
SIN0 to SIN3 SOT0 to SOT3 SCK0 to SCK3
PPG0 to PPG5
U-TIMER 0 to 3 AN0 to AN3 ADTG AVRH AN4 to AN7 ADTG AVCC DA0, DA1 4 ch Input 10/8-bit A/D 0 4 ch Input 10/8-bit A/D 1 2 ch Output 8-bit D/A 0, 1 Input Capture 0, 1 Free Run Timer 0 Output Compare 0, 1 Free Run Timer 1 Output Compare 2, 3 8-bit PWC 0, 1 IC0, IC1 CKI0 OP0, OP1 CKI1 OP2, OP3 PWI0, PWI1
: Trriger signal
23
MB91230 Series
s MEMORY SPACE
1. Memory space
The FR60 Lite family has 4 gigabytes of logical address space (232 addresses) available to the CPU by linear access. • Direct Addressing Areas The following address space areas are used as I/O areas. These areas are called direct addressing areas, in which the address of an operand can be specified directly during an instruction. The size of directly addressable areas depends on the length of the data being accessed as shown below. • byte data access • word data access : 0 to 0FFH : 0 to 3FFH • half word data access : 0 to 1FFH
2. Memory Map
MB91V230 0000 0000H 0000 0400H 0001 0000H I/O I/O
MB91F233/L, MB91233L
Direct Addressing Areas Refer to I/O Map
0001 0000H
I/O I/O
Access disallowed Built-in RAM 24 KB Access disallowed Emulation SRAM area 512 KB Access disallowed
Access disallowed Built-in RAM 16 KB Access disallowed Built-in FLASH ROM 256 KB Access disallowed
0003 A000H
0003 C000H 0004 0000H
0004 0000H 0008 0000H
000C 0000H
0010 0000H
0010 0000H
FFFF FFFFH
FFFF FFFFH
Note : Do not set the external bus mode in which the MB91230 series cannot operate.
24
MB91230 Series
s MODE SETTINGS
The FR family uses mode pins (MD2 to MD0) and a mode data to set the operation mode. • Mode Pins The MD2, MD1, and MD0 pins specify how the mode vector fetch and reset vector fetch is performed. Setting is prohibited other than that shown in the following table. Mode Pins MD2 0 0 MD1 0 0 MD0 0 1 Mode name Internal ROM mode vector External ROM mode vector Reset vector access area Internal External Not supported by this model. Remarks
• Mode data Data written to the internal mode register (MODR) by a mode vector fetch is called mode data. After an operation mode has been set in the mode register, the device operates in the operation mode. The mode data is set by all reset source. User programs cannot set data to the mode register. Details of mode data description
bit 31 0 30 0 29 0 28 0 27 0 26 1 25 1 24 1
Operation mode setting bits
[bit31 to bit24] Reserved bit Be sure to set this bit to “00000111”. Operation is not guaranteed when any value other than “00000111” is set. Note : Mode data set in the mode vector must be placed as byte data at 0x000FFFF8H. Use the highest byte from bit31 to bit24 for placement as the FR family uses the big endian for byte endian.
bit 31
24 23 XXXXXXXX
16 15 XXXXXXXX
87 Mode Data
0
Incorrect
0x000FFFF8H
XXXXXXXX
0x000FFFF8H
Mode Data
XXXXXXXX
XXXXXXXX
XXXXXXXX
Correct
0x000FFFFCH
Reset Vector
25
MB91230 Series
s I/O Map
[How to read the table] Address 000000H Register +0 +1 +2 +3 PDR0 [R/W] B PDR1 [R/W] B PDR2 [R/W] B PDR3 [R/W] B XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Block T-unit Port data register
Read/write attribute Access unit (B : byte, H : half word, W : word) Initial value of register after reset Register name (column 1 of the register is at address 4n, column 2 is at address 4n + 1...) Leftmost register address (For word-length access, column 1 of the register becomes the MSB of the data.) Note : Initial values of register bits are represented as follows : “ 1 ” : Initial Value “ 1 ” “ 0 ” : Initial Value “ 0 ” “ X ” : Initial Value “ undefined” “ - ” : No physical register at this location Access is barred with an undefined data access attribute.
26
MB91230 Series
Address 000000H 000004H 000008H 00000CH 000010H to 00003CH 000040H
Register +0 PDR0 [R/W] B XXXXXXXX PDR4 [R/W] B XXXXXXXX PDR8 [R/W] B XXXXXXXX PDRC [R/W] B XXXXXXXX EIRR0 [R/W] B, H, W 00000000 DICR [R/W] B, H, W -------0 +1 PDR1 [R/W] B XXXXXXXX PDR5 [R/W] B XXXXXXXX PDR9 [R/W] B XXXXXXXX PDRD [R/W] B ------XX ENIR0 [R/W] B, H, W 00000000 +2 PDR2 [R/W] B XXXXXXXX PDR6 [R/W] B XXXX---PDRA [R/W] B XXXXXXXX +3 PDR3 [R/W] B XXXXXXXX PDR7 [R/W] B ----XXXX PDRB [R/W] B ----XXXX PDRF [R/W] ---XX--
Block
Port data register
Unused
ELVR0 [R/W] B, H, W 00000000 00000000 TMR0 [R] H, W XXXXXXXX XXXXXXXX TMCSR0 [R/W] B, H, W ----0000 00000000 TMR1 [R] H, W XXXXXXXX XXXXXXXX TMCSR1 [R/W] B, H, W ----0000 00000000 TMR2 [R] H, W XXXXXXXX XXXXXXXX TMCSR2 [R/W] B, H, W ----0000 00000000 SCR0 [R/W] B, H, W 00000100 SCR1 [R/W] B, H, W 00000100 SMR0 [R/W] B, H, W 00--0-0-
External interrupt (INT0 to 7)
000044H
Delay interrupt
000048H 00004CH 000050H 000054H 000058H 00005CH
TMRLR0 [W] H, W XXXXXXXX XXXXXXXX TMRLR1 [W] H, W XXXXXXXX XXXXXXXX TMRLR2 [W] H, W XXXXXXXX XXXXXXXX SSR0 [R/W] B, H, W 00001000 SIDR0 [R] B, H, W SODR0 [W] B, H, W XXXXXXXX
Reload timer 0
Reload timer 1
Reload timer 2
000060H
UART0
000064H
UTIM0 [R] H (UTIMR0 [W] H) 00000000 00000000 SSR1 [R/W] B, H, W 00001000 SIDR1 [R] B, H, W SODR1 [W] B, H, W XXXXXXXX
UTIMC0 [R/W] B U-TIMER0 0--00001 SMR1 [R/W] B, H, W 00--0-0-
000068H
UART1
00006CH
UTIM1 [R] H (UTIMR1 [W] H) 00000000 00000000
UTIMC1 [R/W] B U-TIMER1 0--00001
(Continued)
27
MB91230 Series
Address
Register +0 SSR2 [R/W] B, H, W 00001000 +1 SIDR2 [R] B, H, W SODR2 [W] B, H, W XXXXXXXX +2 SCR2 [R/W] B, H, W 00000100 +3 SMR2 [R/W] B, H, W 00--0-0-
Block
000070H
UART2
000074H 000078H 00007CH 000080H 000084H 000088H 00008CH
UTIM2 [R] H (UTIMR1 [W] H) 00000000 00000000 ADCS0 [R/W] H, W XXXXXXXX XXXXXXXX ADT00 (ADTH0/ADTL0) [R] H, W 000000XX XXXXXXXX ADT02 (ADTH2/ADTL2) [R] H, W 000000XX XXXXXXXX ADCS1 [R/W] H, W XXXXXXXX XXXXXXXX ADT10 (ADTH0/ADTL0) [R] H, W 000000XX XXXXXXXX ADT12 (ADTH2/ADTL2) [R] H, W 000000XX XXXXXXXX
UTIMC2 [R/W] B U-TIMER2 0--00001
ADCT0 [R/W] H, W 000-0000 -000--00 ADT01 (ADTH1/ADTL1) [R] H, W 000000XX XXXXXXXX ADT03 (ADTH3/ADTL3) [R] H, W 000000XX XXXXXXXX ADCT1 [R/W] H, W 000-0000 --000--00 ADT11 (ADTH1/ADTL1) [R] H, W 000000XX XXXXXXXX ADT13 (ADTH3/ADTL3) [R] H, W 000000XX XXXXXXXX DACR1 [R/W] B, H, W -------0 DADR1 [R/W] B, H, W XXXXXXXX LCR0 [R/W] B, H, W 00010000 VRAM2 [R/W] B, H, W XXXXXXXX VRAM6 [R/W] B, H, W XXXXXXXX VRAM10 [R/W] B, H, W XXXXXXXX VRAM14 [R/W] B, H, W XXXXXXXX DACR0 [R/W] B, H, W -------0 DADR0 [R/W] B, H, W XXXXXXXX LCR1 [R/W] B, H, W 00000000 VRAM3 [R/W] B, H, W XXXXXXXX VRAM7 [R/W] B, H, W XXXXXXXX VRAM11 [R/W] B, H, W XXXXXXXX VRAM15 [R/W] B, H, W XXXXXXXX Clock monitor LCD controller/driver A/D converter 1 (series-parallel type) A/D converter 0 (series-parallel type)
000090H
D/A converter
000094H
LCDCMR [R/W] B, H, W ----0000 VRAM0 [R/W] B, H, W XXXXXXXX VRAM4 [R/W] B, H, W XXXXXXXX VRAM8 [R/W] B, H, W XXXXXXXX VRAM12 [R/W] B, H, W XXXXXXXX CKR [R/W] B, H, W ----0000
000098H
VRAM1 [R/W] B, H, W XXXXXXXX VRAM5 [R/W] B, H, W XXXXXXXX VRAM9 [R/W] B, H, W XXXXXXXX VRAM13 [R/W] B, H, W XXXXXXXX
00009CH
0000A0H
0000A4H
0000A8H
0000ACH
(Continued)
28
MB91230 Series
Address
Register +0 RCR1 [W] B, H, W 00000000 CCRH0 [R/W] B, H, W 00000000 CCRH1 [R/W] B, H, W 00000000 SSR [R/W] B, H, W 00001000 +1 RCR0 [W] B, H, W 00000000 CCRL0 [R/W] B, H, W 00001000 CCRL1 [R/W] B, H, W 00001000 SIDR 3 [R] B, H, W SODR 3 [W] B, H, W XXXXXXXX +2 UDCR1 [R] B, H, W 00000000 +3 UDCR0 [R] B, H, W 00000000 CSR0 [R/W] B, H, W 00000000 CSR1 [R/W] B, H, W 00000000 SMR [R/W] B, H, W 00--0-0UTIMC [R/W] B 0--00001 unused
Block
0000B0H
0000B4H
Up/down counter0, 1
0000B8H 0000BCH
SCR [R/W] B, H, W 00000100
0000C0H
UART3
0000C4H 0000C8H 0000CCH
UTIM [R] H (UTIMR [W] H) 00000000 00000000 TMRLR3 [W] H, W XXXXXXXX XXXXXXXX EIRR1 [R/W] B, H, W 00000000 ENIR1 [R/W] B, H, W 00000000
U-TIMER3
TMR3 [R] H, W XXXXXXXX XXXXXXXX TMCSR3 [R/W] B, H, W ---00000 00000000 ELVR1 [R/W] B, H, W 00000000 00000000 TCCS0 [R/W] B, H, W 00000000 TCCS1 [R/W] B, H, W 00000000
Reload timer 3
0000D0H
External interrupt (INT8 to 16)
0000D4H
TCDT0 [R/W] H, W 00000000 00000000 TCDT1 [R/W] H, W 00000000 00000000 IPCP1 [R] H, W XXXXXXXX XXXXXXXX
Free-run timer 0
0000D8H
Free-run timer 1
0000DCH
IPCP0 [R] H, W XXXXXXXX XXXXXXXX ICS01 [R/W] B, H, W 00000000 Input capture
0000E0H
0000E4H 0000E8H 0000ECH
OCCP1 [R/W] H, W XXXXXXXX XXXXXXXX OCCP3 [R/W] H, W XXXXXXXX XXXXXXXX OCS23 [R/W] B, H, W ---0--00 0000--00
OCCP0 [R/W] H, W XXXXXXXX XXXXXXXX OCCP2 [R/W] H, W XXXXXXXX XXXXXXXX OCS01 [R/W] B, H, W ---0-00 0000--00 Output compare
(Continued)
29
MB91230 Series
Address
Register +0 PWCC0 [R/W] B, H, W 0---00-0 WTHR [R/W] B, H ---XXXXX +1 PWCD0 [R] B, H, W XXXXXXXX WTDBL [R/W] B -------0 WTBR0 [R/W] B ---XXXXX WTMR [R/W] B, H --XXXXXX +2 PWCC1 [R/W] B, H, W 0---00-0 +3 PWCD1 [R] B, H, W XXXXXXXX
Block
0000F0H
PWC0, 1
0000F4H 0000F8H
WTCR [R/W] B, H 00000000 000-00-X WTBR1 [R/W] B XXXXXXXX WTSR [R/W] B --XXXXXX PCSR0 [W] H, W XXXXXXXX XXXXXXXX PCNH0 [R/W] B, H, W 00000000 PCNL0 [R/W] B, H, W 00000000 PPG0 WTBR2 [R/W] B Real-time clock XXXXXXXX
0000FCH 000100H to 000114H 000118H 00011CH 000120H
GCN20 [R/W] B 00000000
Unused
GCN10 [R/W] H 00110010 00010000 PTMR0 [R] H, W 11111111 11111111 PDUT0 [W] H, W XXXXXXXX XXXXXXXX PTMR1 [R] H, W 11111111 11111111 PDUT1 [W] H, W XXXXXXXX XXXXXXXX PTMR2 [R] H, W 11111111 11111111 PDUT2 [W] H, W XXXXXXXX XXXXXXXX PTMR3 [R] H, W 11111111 11111111 PDUT3 [W] H, W XXXXXXXX XXXXXXXX PTMR4 [R] H, W 11111111 11111111 PDUT4 [W] H, W XXXXXXXX XXXXXXXX
PPG Unused
000124H
000128H
PCSR1 [W] H, W XXXXXXXX XXXXXXXX PCNH1 [R/W] B, H, W 00000000 PCNL1 [R/W] B, H, W 00000000 PPG1
00012CH
000130H
PCSR2 [W] H, W XXXXXXXX XXXXXXXX PCNH2 [R/W] B, H, W 00000000 PCNL2 [R/W] B, H, W 00000000 PPG2
000134H
000138H
PCSR3 [W] H, W XXXXXXXX XXXXXXXX PCNH3 [R/W] B, H, W 00000000 PCNL3 [R/W] B, H, W 00000000 PPG3
00013CH
000140H
PCSR4 [W] H, W XXXXXXXX XXXXXXXX PCNH4 [R/W] B, H, W 00000000 PCNL4 [R/W] B, H, W 00000000 PPG4
000144H
(Continued)
30
MB91230 Series
Address 000148H
Register +0 +1 +2 +3 PTMR5 [R] H, W 11111111 11111111 PDUT5 [W] H, W XXXXXXXX XXXXXXXX PCSR5 [W] H, W XXXXXXXX XXXXXXXX PCNH5 [R/W] B, H, W 00000000 PCNL5 [R/W] B, H, W 00000000 PPG5
Block
00014CH 000150H to 0001FCH 000200H to 0003ECH 0003F0H 0003F4H 0003F8H 0003FCH 000400H 000404H 000408H 00040CH 000410H to 00041CH 000420H 000424H 000428H 00042CH 000430H to 00043CH
Unused
Unused
BSD0 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDR0 [R/W] B 00000000 DDR4 [R/W] B 00000000 DDR8 [R/W] B 00000000 DDRC [R/W] B 00000000 PFR0 [R/W] B --00-00PFR4 [R/W] B 00000000 PFR8 [R/W] B 00000000 PFRC [R/W] B ------- DDR1 [R/W] B 00000000 DDR5 [R/W] B 00000000 DDR9 [R/W] B 00000000 DDRD [R/W] B ------00 PFR1 [R/W] B -------PFR5 [R/W] B ---00--PFR9 [R/W] B 00000000 PFRD [R/W] B ------00 DDR2 [R/W] B 00000000 DDR6 [R/W] B 0000---DDRA [R/W] B 00000000 PFR2 [R/W] B -00-0000 PFR6 [R/W] B 0000---PFRA [R/W] B 00000000 DDR3 [R/W] B00000000 DDR7 [R/W] B ----0000 DDRB [R/W] B ----0000 DDRF [R/W] B ---00-- PFR3 [R/W] B ------00 PFR7 [R/W] B ----0000 PFRB [R/W] B ----0000 PFRF [R/W] B ----0-- Unused Unused Data direction register
Bit search
Port function register
(Continued)
31
MB91230 Series
Address
Register +0 ICR00 [R/W] B, H, W ---11111 ICR04 [R/W] B, H, W ---11111 ICR08 [R/W] B, H, W ---11111 ICR12 [R/W] B, H, W ---11111 ICR16 [R/W] B, H, W ---11111 ICR20 [R/W] B, H, W ---11111 ICR24 [R/W] B, H, W ---11111 ICR28 [R/W] B, H, W ---11111 ICR32 [R/W] B, H, W ---11111 ICR36 [R/W] B, H, W ---11111 ICR40 [R/W] B, H, W ---11111 ICR44 [R/W] B, H, W ---11111 +1 ICR01 [R/W] B, H, W ---11111 ICR05 [R/W] B, H, W ---11111 ICR09 [R/W] B, H, W ---11111 ICR13 [R/W] B, H, W ---11111 ICR17 [R/W] B, H, W ---11111 ICR21 [R/W] B, H, W ---11111 ICR25 [R/W] B, H, W ---11111 ICR29 [R/W] B, H, W ---11111 ICR33 [R/W] B, H, W ---11111 ICR37 [R/W] B, H, W ---11111 ICR41 [R/W] B, H, W ---11111 ICR45 [R/W] B, H, W ---11111 +2 ICR02 [R/W] B, H, W ---11111 ICR06 [R/W] B, H, W ---11111 ICR10 [R/W] B, H, W ---11111 ICR14 [R/W] B, H, W ---11111 ICR18 [R/W] B, H, W ---11111 ICR22 [R/W] B, H, W ---11111 ICR26 [R/W] B, H, W ---11111 ICR30 [R/W] B, H, W ---11111 ICR34 [R/W] B, H, W ---11111 ICR38 [R/W] B, H, W ---11111 ICR42 [R/W] B, H, W ---11111 ICR46 [R/W] B, H, W ---11111 +3 ICR03 [R/W] B, H, W ---11111 ICR07 [R/W] B, H, W ---11111 ICR11 [R/W] B, H, W ---11111 ICR15 [R/W] B, H, W ---11111 ICR19 [R/W] B, H, W ---11111 ICR23 [R/W] B, H, W ---11111 ICR27 [R/W] B, H, W ---11111 ICR31 [R/W] B, H, W ---11111 ICR35 [R/W] B, H, W ---11111 ICR39 [R/W] B, H, W ---11111 ICR43 [R/W] B, H, W ---11111 ICR47 [R/W] B, H, W ---11111 Unused
Block
000440H
000444H
000448H
00044CH
000450H
000454H
Interrupt control unit
000458H
00045CH
000460H
000464H
000468H
00046CH 000470H to 00047CH
(Continued)
32
MB91230 Series
(Continued)
Address Register +0 RSRR [R/W] B, H, W 10000000 CLKR [R/W] B, H, W 00000000 WPCR [R/W] B 00---000 OSCR [R/W] B 00---000 +1 STCR [R/W] B, H, W 00110011 WPR [R/W] B, H, W XXXXXXXX PCR1 [R/W] B 00000000 +2 TBCR [R/W] B, H, W 00XXXX00 DIVR0 [R/W] B, H, W 00000011 OSCCR [R/W] B XXXXXXX0 +3 CTBR [W] B, H, W XXXXXXXX DIVR1 [R/W] B, H, W 00000000 PCR3 [R/W] B 00000000 Watch timer Main clock oscillation stabilization wait timer Unused Pull-up control register Unused Clock control Block
000480H
000484H
000488H 00048CH 000490H 000494H to 0004FCH 000500H 000504H to 00051CH 000520H to 0007F8H 0007FCH 000800H to 000AFCH 000B00H to 000FFCH 001000H to 001FFCH
MODR* XXXXXXXX
Unused
Operation mode
Unused
Unused
Unused
* : This register is set when the mode vector is fetched. Not user-accessible.
33
MB91230 Series
s INTERRUPT VECTOR
Interrupt source Reset Mode vector System reserved System reserved System reserved System reserved System reserved Coprocessor absent trap Coprocessor error trap INTE instruction Instruction break exception Operand break trap Step trace trap NMI request (tool) Undefined instruction exception NMI request (This model has no NMI request) External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 Reload timer 0 Reload timer 1 Reload timer 2 UART0(Reception completed) UART0 (Transmission completed) UART1 (Reception completed) UART1 (Transmission completed) UART2 (Reception completed) UART2 (Transmission completed) Interrupt number 10 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 Interrupt level 15 (FH) fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3C0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H 37CH TBR default address 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H 000FFF7CH
(Continued)
34
MB91230 Series
Interrupt source UART3 (Reception completed) UART3 (Transmission completed) A/D ch0 A/D ch1 External interrupt8 External interrupt9 External interrupt 10 External interrupt 11 External interrupt 12 External interrupt 13 External interrupt 14 External interrupt 15 Real-time clock Main clock oscillation stabilization wait timer Timebase timer 0 overflow Reload timer 3 Watch timer UD Counter 0 UD Counter 1 PPG 0/1 PPG 2/3 PPG 4/5 Free-run timer 0 Free-run timer 1 ICU 0 (capture) ICU 1 (capture) OCU 0 (match) OCU 1 (match) OCU 2 (match) OCU 3 (match) Delay interrupt source bit System reserved (Used by REALOS) System reserved (Used by REALOS) System reserved
Interrupt number 10 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 16 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42
Interrupt level ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
Offset 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H 2F4H
TBR default address 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H 000FFEF4H
(Continued)
35
MB91230 Series
(Continued)
Interrupt source System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Used by INT instruction Interrupt number 10 67 68 69 70 71 72 73 74 75 76 77 78 79 80 to 255 16 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 to FF Interrupt level Offset 2F0H 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH to 000H TBR default address 000FFEF0H 000FFEECH 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH to 000FFC00H
36
MB91230 Series
s PIN STATUS IN EACH CPU STATE
Terms used as the status of pins mean as follows. • Input enabled Indicates that the input function can be used. • Input 0 fixed Indicates that the input level has been internally fixed to be “0” to prevent leakage when the input is released. • Output Hi-Z Means the placing of a pin in a high impedance state by preventing the transistor for driving the pin from driving. • Output is maintained Indicates the output in the output state existing immediately before this mode is established. If the device enters this mode with an internal output peripheral operating or while serving as an output port, the output is performed by the internal peripheral or the port output is maintained, respectively. • State existing immediately before is maintained When the device serves for output or input immediately before entering this mode, the device maintains the output or is ready for the input, respectively.
37
MB91230 Series
• Pin Status List Pin Pin no. name Port name Specified function name At initializing
Reset initialization
At Stop mode At sleep mode
Remarks
Input Output Input/ Function Output name
HIZ = 0
HIZ = 1
1 2
P26/ P26 SCK2 P27/ SIN3 P27
SIN3
SCK2 P26 P27 Pull-up options can be selected Pull-up options can be selected Pull-up options can be selected Pull-up options can be selected Pull-up options can be selected Pull-up options can be selected Pull-up options can be selected Pull-up options can be selected
3
P30/ P30 SOT3
SOT3
P30
4
P31/ P31 SCK3
SCK3 P31
5
P32/ AIN0
P32
AIN0
P32
6
P33/ BIN0
P33
BIN0
P33
7
P34/ ZIN0
P34
ZIN0
P34
Output Hi-Z/ Input enabled
Retention of the immediately prior state
Retention of the immediately prior state
Output Hi-Z/ Input 0 fixed
8
P35/ AIN1
P35
AIN1
P35
9
P36/ BIN1
P36
BIN1
P36
10
P37/ ZIN1
P37
ZIN1
PPG 0 PPG 1
P37
11 12
P40/ P40 PPG0 P41/ P41 PPG1
P40 P41
(Continued)
38
MB91230 Series
Pin no.
Pin name
Port name P42 P43 P44 P45 P46 P47 P50 P51 P52
Specified function name
Input
At initializing
Reset Output Input/ Function Output name initialization
At sleep mode
At Stop mode
Remarks
HIZ = 0
HIZ = 1
13 X0A 14 X1A 15 VCC3B/ VCC
INT8 INT9 INT10
PPG2 PPG3 TOT0 TOT1 TOT2 CKOT
P42 P43 P44 P45 P46 P47 P50 P51 P52
16 VSS 17 VCC3 18 19 20 21 22 23 24 25 26 P42/ PPG2 P43/ PPG3 P44/ TOT0 P45/ TOT1 P46/ TOT2 P47/ CKOT P50/ INT8 P51/ INT9 P52/ INT10
Retention of the immediately prior state
Output Hi-Z/ Input 0 fixed
Output Hi-Z/ Input enabled
Retention of the immediately prior state P: Retention P: of the Output immediately Hi-Z prior state F: F: Input Input enabled enabled
P53/ 27 INT11/ P53 PPG4 P54/ 28 INT12/ P54 PPG5 P55/ 29 INT13/ P55 TIN2 P56/ 30 INT14/ P56 TIN1
INT11 PPG4
P53
INT12 PPG5
P54
INT13 TIN2 INT14 TIN1
P55
P56
Note : P : Port selected, F : Specified function selected
(Continued)
39
MB91230 Series
Pin no.
Pin name
Port name
Specified function name
Input Output
At initializing
Input/ Function Reset Output name initialization
At sleep mode
At Stop mode HIZ = 0 HIZ = 1
Remarks
P57/ INT15/ 31 P57 TIN0/ ADTG0
INT15 TIN0 ADTG0
P57
32
PF3/ TOT3
PF3
TIN3 ADTG1 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
TOT3 DA0 DA1
PF3
Output Hi-Z/ Input enabled
Retention of the immediately prior state
P: Retention P: of the Output immediately Hi-Z prior state F: F: Input 0 Input enabled enabled
PF4/ 33 TIN3/ PF4 ADTG1 34 35 PD0/ DA0 PD1/ DA1 PD0 PD1 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
PF4
PD0 PD1 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 Output Hi-Z/ Input enabled Retention of the immediately prior state Output Hi-Z/ Input enabled Retention of the immediately prior state
Retention of the immediately prior state
Output Hi-Z/ Input 0 fixed
36 AVCC 37 AVRH 38 AVSS 39 40 41 42 43 44 45 46 PC0/ AN0 PC1/ AN1 PC2/ AN2 PC3/ AN3 PC4/ AN4 PC5/ AN5 PC6/ AN6 PC7/ AN7
Retention of the immediately prior state
Output Hi-Z/ Input 0 fixed
Retention of the immediately prior state
Output Hi-Z/ Input 0 fixed
Note : P : Port selected, F : Specified function selected
(Continued)
40
MB91230 Series
Pin Pin no. name 47 VSS 48 VCC3IO 49 50 51 52 53 54 55 P80/ SEG0 P81/ SEG1 P82/ SEG2 P83/ SEG3 P84/ SEG4 P85/ SEG5 P86/ SEG6
Port name P80 P81 P82 P83 P84 P85 P86 P87 P90 P91
Specified function name
Input Output
At initializing
Input/ Function Reset Output name initialization
At sleep mode
At Stop mode HIZ = 0 HIZ = 1
Remarks
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14
P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96
P87/ 56 SEG7 57 58 59 60 61 62 63 P90/ SEG8 P91/ SEG9
Output Hi-Z/ Input enabled
Retention of the immediately prior state
Retention of the immediately F: prior state Retention of the immediately prior state
P: Output Hi-Z/ Input 0 fixed
P92/ P92 SEG10 P93/ P93 SEG11 P94/ P94 SEG12 P95/ P95 SEG13 P96/ P96 SEG14
Note : P : Port selected, F : Specified function selected
(Continued)
41
MB91230 Series
Pin Pin Port no. name name P97/ P97 SEG15 PA0/ PA0 SEG16 PA1/ PA1 SEG17 PA2/ PA2 SEG18 PA3/ PA3 SEG19
Specified function name
Input Output
At initializing
Input/ Function Reset Output name initialization
At sleep mode
At Stop mode HIZ = 0 HIZ = 1
Remarks
64 65 66 67 68
SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27
P97 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 P: Output Hi-Z/ Input 0 fixed Output Hi-Z/ Input enabled Retention of the immediately prior state P: Output Hi-Z/ Input 0 fixed
PA4/ 69 PA4 SEG20 70 71 72 73 74 PA5/ PA5 SEG21 PA6/ PA6 SEG22 PA7/ PA7 SEG23 PB0/ PB0 SEG24 PB1/ PB1 SEG25
Retention of the immediately F : prior state Retention of the immediately prior state
75 VCC 76 VSS 77 78
PB2/ PB2 SEG26 PB3/ PB3 SEG27
79
P64/ P64 SEG28
SEG28
Output Hi-Z/ Input enabled
Retention of the immediately prior state
P64
Retention of the immediately F: prior state Retention of the immediately prior state
opendrain pin, IOL = 20 mA
Note : P : Port selected, F : Specified function selected
(Continued)
42
MB91230 Series
Pin Pin Port no. name name
Specified function name
Input Output
At initializing
Input/ Function Reset Output name initialization
At sleep mode
At Stop mode HIZ = 0 HIZ = 1
Remarks
80
P65/ P65 SEG29
SEG29
P65
opendrain pin, IOL = 20 mA opendrain pin, IOL = 20 mA
81
P66/ P66 SEG30
SEG30
P66
82
P67/ P67 SEG31
SEG31
P67
Output Hi-Z/ Input enabled
83 84 85 86
P70/ P70 COM0 P71/ P71 COM1 P72/ P72 COM2 P73/ P73 COM3
COM0 COM1 COM2 COM3
P70 P71 P72 P73
P: Output Hi-Z/ Retention Retention Input 0 fixed openof the of the drain immediately immediately F : pin, prior state prior state Retention IOL = of the 20 mA immediately prior state
87 MOD2 88 MOD1 89 MOD0 90 INIT 91 V0 92 V1 93 V2 94 V3
Note : P : Port selected, F : Specified function selected
(Continued)
43
MB91230 Series
Pin Pin no. name P00/ SIN0 P01/ SOT0 P02/ SCK0 P03/ SIN1 P04/ SOT1 P05/ SCK1 P06/ IC0 P07/ IC1
Port name
Specified function name
At initializing
Reset Input Output Input/ Function Output name initialization
At sleep mode
At Stop mode
Remarks
HIZ = 0
HIZ = 1
95 96 97 98 99 100 101 102
P00 P01 P02 P03 P04 P05 P06 P07
SIN0 SIN1 IC0 IC1
SOT0 SOT1
P00 P01
SCK0 P02 P03 P04 Output Hi-Z/ Input enabled Retention of the immediately prior state Retention of the immediately prior state Output Hi-Z/ Input 0 fixed
SCK1 P05 P06 P07
P10/ 103 INT0
P10
INT0
P10
P11/ 104 INT1 105 VCC 106 VSS 107 X1 108 X0
P11
INT1
P11
P: Retention P : Output of the Hi-Z immediately prior state F : Input enabled F : Input enabled
Pull-up options can be selected Pull-up options can be selected
Note : P : Port selected, F : Specified function selected
(Continued)
44
MB91230 Series
(Continued)
Pin Pin Port no. name name Specified function name
Input
At initializing
Input/ Reset Output Output Function initialization name
At sleep mode
At Stop mode
Remarks
HIZ = 0
HIZ = 1 Pull-up options can be selected Pull-up options can be selected
P12/ 109 INT2
P12
INT2
P12
P13/ 110 INT3
P13
INT3
P13 P: Retention P: of the Output immediately Hi-Z prior state F: F: Input Input enabled enabled
P14/ 111 INT4
P14
INT4
P14
Pull-up options can be selected Pull-up options can be selected Pull-up options can be selected Pull-up options can be selected
P15/ 112 INT5
P15
INT5
P15
P16/ 113 INT6
P16
INT6
P16 Output Hi-Z/ Input enabled Retention of the immediately prior state
P17/ 114 INT7
P17
INT7
P17
P20/ 115 CKI0/ P20 OP0 P21/ 116 CKI1/ P21 OP1 P22/ 117 PWI0/ P22 OP2 P23/ 118 PWI1/ P23 OP3 119 120 P24/ SIN2 P24
CKI0 OP0
P20
CKI1 OP1
P21 Retention of the immediately prior state Output Hi-Z/ Input 0 fixed
PWI0 OP2
P22
PWI1 OP3 SOT2
P23
SIN2
P24 P25
P25/ P25 SOT2
Note : P : Port selected, F : Specified function selected
45
MB91230 Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
MB91F233, MB91V230 Parameter Symbol VCC Power supply voltage* Analog power supply voltage* Input voltage* Input voltage* (open-drain) Analog pin input voltage* Output voltage* Operating ambient temperature Storage temperature VCC3 VCC3IO AVCC VI VIND VIA VO Ta Tstg Rating Min VSS−0.5 VSS−0.5 VSS−0.5 VSS−0.5 VSS−0.5 VSS−0.5 VSS−0.5 VSS−0.5 −40 −55 Max VSS + 6.0 VSS + 4.0 VSS + 4.0 VSS + 4.0 VCC + 0.5 VCC + 0.5 AVCC + 0.5 VCC + 0.5 + 85 + 125 Unit V V V V V V V V °C °C Remarks
* : This parameter is based on VSS = AVSS = 0.0 V. MB91F233L, MB91233L Parameter Symbol VCC Power supply voltage* Analog power supply voltage* Input voltage* Input voltage* (open-drain) Analog pin input voltage* Output voltage* Operating ambient temperature Storage temperature VCC3 VCC3IO AVCC VI VIND VIA VO Ta Tstg Rating Min VSS−0.5 VSS−0.5 VSS−0.5 VSS−0.5 VSS−0.5 VSS−0.5 VSS−0.5 VSS−0.5 −40 −55 Max VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 4.0 VCC + 0.5 VCC + 0.5 AVCC + 0.5 VCC + 0.5 + 85 + 125 Unit V V V V V V V V °C °C Remarks
* : This parameter is based on VSS = AVSS = 0.0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
46
MB91230 Series
2. Recommended Operating Conditions
MB91F233, MB91V230 Value Min −40 4.00 3.00 3.00 2.20 3.00 3.00 Max + 85 5.25 3.60 3.60 3.60 3.60 3.60 5.25 (VSS = AVSS = 0.0 V) Symbol Ta VCC VCC3 Power supply voltage VCC3B VCC3IO Analog power supply voltage LCD reference voltage AVCC V3 Unit °C V V V V V V V *3 *2 *1 *4 Remarks
Parameter Operating ambient temperature
MB91F233L, MB91233L Value Min −40 3.00 3.00 3.00 2.20 3.00 3.00 Max + 85 3.60 3.60 3.60 3.60 3.60 3.60 3.60
(VSS = AVSS = 0.0 V) Symbol Ta VCC VCC3 Unit °C V V V V V V V *3 *2 *1 *4 Remarks
Parameter Operating ambient temperature
Power supply voltage
VCC3B VCC3IO
Analog power supply voltage LCD reference voltage
AVCC V3
*1 : The standard power-supply voltage varies with the model of product. *2 : Only for backup. Set VCC3 = AVCC = VCC3IO. *3 : V3 must not exceed VCC. *4 : For the relationships between VCC3 and operating frequencies, see section “4. AC Characteristics (4) Operation Assurance Range”. For the MB91V230, please inquire separately. Note : For normal use, set VCC3 = VCC3B = AVCC = VCC3IO. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 47
MB91230 Series
3. DC Characteristics
MB91V230, MB91F233 (VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter Symbol Pin name Conditions FLASH model normal operation, Ta = +25 °C, FCP = 33 MHz, FCPP = 16.5 MHz FLASH model normal operation, Ta = +25 °C, FCP = 33 MHz, FCPP = 33 MHz VCC3 RTC mode, @Ta = +25 °C, FCP = 32 kHz STOP mode, @Ta = +25 °C, FCP = 0 kHz SLEEP mode FCP = 33 MHz, FCPP = 16.5 MHz SLEEP mode FCP = 33 MHz, FCPP = 33 MHz VIH X0A VIL X0A VOH VOL IIL Ileak VCC3B = 2.2 V to 3.6 V IOH = −4 mA IOL = 4 mA VSS VCC −0.5 VSS −5 −10 VCC3B = 2.2 V to 3.6 V Value Min Typ Max Unit Remarks
65
75
mA
ICC
73
83
mA
Power supply current
ICCT
20
50
µA
Watch timer, RTC, LCDC VCC3 = VCC3B = 2.4 V
ICCH
5
50
µA
21
25
mA
ICCS
VCC × 0.8 VCC3B × 0.8 VSS
30
35
mA
"H" level input voltage
VCC VCC3B VCC × 0.2 VSS + 0.4 VCC 0.4 5 10
V V V V V V µA µA When external clock is used When external clock is used
“L” level input voltage "H" level output voltage "L" level output voltage Input leakage current Open-drain output leakage current
P64 to 67 IOL = 20 mA
(Continued)
48
MB91230 Series
(Continued) (VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C)
Parameter LCD division resistance COM0 to COM3 output impedance SEG00 to SEG31 output impedance Symbol Pin name V0 - V1, V1 - V2, V2 - V3 COM0 to COM3 SEG00 to SEG31 V0 to V3, COM0 to COM3, SEG00 to SEG31 Conditions Value Min 50 V1 to V3 = 5.0 V 15 kΩ Typ 100 Max 200 Unit Remarks
RLCD
kΩ kΩ
RVCOM RVSEG
2.5
LCDC leakage current
ILCDC
−5
5
µA
49
MB91230 Series
MB91F233L, MB91233L (VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter Symbol Pin name Conditions FLASH model normal operation, Ta = +25 °C, FCP = 33 MHz, FCPP = 16.5 MHz FLASH model normal operation, Ta = +25 °C, FCP = 33 MHz, FCPP = 33 MHz ROM model normal operation, Ta = +25 °C, FCP = 33 MHz, FCPP = 16.5 MHz Vcc3 ROM model normal operation, Ta = +25 °C, FCP = 33 MHz, FCPP = 33 MHz RTC mode, @Ta = +25 °C, FCP = 32 kHz STOP mode, @Ta = +25 °C, FCP = 0 MHz SLEEP mode FCP = 33 MHz, FCPP = 16.5 MHz SLEEP mode FCP = 33 MHz, FCPP = 33 MHz VIH X0A VIL X0A VOH VCC3B = 2.2 V to 3.6 V VCC = 3.3 V, IOH = −2 mA VSS VCC −0.5 VCC3B = 2.2 V to 3.6 V Value Min Typ Max Unit Remarks
65
75
mA
ICC
73
83
mA
45
55
mA
ICC Power supply current
55
65
mA
ICCT
20
50
µA
Watch timer, RTC, LCDC VCC3 = VCC3B = 2.4 V
ICCH
5
50
µA
21
25
mA
ICCS
VCC × 0.8 VCC3B × 0.8 VSS
30
35 VCC VCC3B VCC × 0.15 VSS + 0.4 VCC
mA V V V V V When external clock is used When external clock is used
"H" level input voltage
"L" level input voltag "H" level output voltage
(Continued)
50
MB91230 Series
(Continued)
(VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter "L" level output voltage Input leakage current Open-drain output leakage current LCD division resistance COM0 to COM3 output impedance SEG00 to SEG31 output impedance LCDC leakage current Symbol VOL IIL Ileak RLCD RVCOM RVSEG Pin name V0 - V1, V1 - V2, V2 - V3 COM0 to COM3 SEG00 to SEG31 V0 to V3, COM0 to COM3, SEG00 to SEG31 Conditions IOL = 2 mA Value Min VSS −5 −10 50 V1 to V3 = 5.0 V 15 kΩ Typ 100 Max 0.4 5 10 200 2.5 Unit V µA µA kΩ kΩ Remarks
P64 to 67 IOL = 10 mA
ILCDC
−5
−5
µA
51
MB91230 Series
4. AC Characteristics
(1) Main clock input standard (MB91V230, MB91F233 : VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C) (MB91F233L, MB91233L : VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter Input frequency Input clock cycle Input clock pulse width Input clock rise time and fall time Internal operating clock frequency Internal operating clock cycle time Peripheral clock frequency Peripheral clock cycle time Symbol FC tCYL tCR tCF FCP tCP FCPP tCYCP X0 Pin name Conditions PWH/tCYL PWL/tCYL Value Min 3.6 40 29.7 29.7 Typ 4 250 Max 4.2 60 5 33.6 33.6 Unit MHz ns % ns MHz ns MHz ns Peripheral clock is derived from internal operating clock divided by 1/1 to 1/16. At external clock Remarks
tCYL 0.8 × VCC3 X0 0.8 × VCC3 VSS + 0.4 PWH tCF PWL tCR 0.8 × VCC3 VSS + 0.4
52
MB91230 Series
(2) Subclock input standard (MB91V230, MB91F233 : VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C) (MB91F233L, MB91233L : VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter Symbol Pin name Conditions PWLH/tLCYL PWLL/tLCYL tCR/tLCYL tCF/tLCYL Value Min Input frequency Input clock cycle Input clock pulse width Input clock rise time and fall time FCL tLCYL 28.571 28.0 45 Typ 32.768 32.768 Max 35.714 35.0 55 5 kHz µs % % At external clock At external clock Unit Remarks
X0A
tLCYL 0.8 × VCC3B X0A 0.8 × VCC3B VSS + 0.4 PWLH tCF PWLL tCR 0.8 × VCC3B VSS + 0.4
53
MB91230 Series
(3) Operation Assurance Range
4.0 3.8
33.6 MHz@ 3.6 V
Internal power supply voltage VCC3 [V]
3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 32 kHz 5 10 15 20 25 30 35 40 MB91F233 MB91F233L MB91233L 28 MHz@ 2.7 V PLL OFF PLL ON 32 MHz@ 3.0 V 8 MHz 33.6 MHz@ 3.3 V
33.6 MHz@ 3.0 V
Internal operation frequency [MHz]
54
MB91230 Series
(4) PLL oscillation stabilization time (LOCK UP time) (MB91V230, MB91F233 : VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to + 85 °C) (MB91F233L, MB91233L : VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to + 85 °C) Parameter PLL oscillation stabilization (LOCK UP time) Symbol value Min 500 Max Unit Remarks Time from when the PLL starts operating to when its oscillation becomes stable
tLOCK
µs
(5) Reset input standards (MB91V230, MB91F233 : VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to + 85 °C) (MB91F233L, MB91233L : VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to + 85 °C) Parameter Reset input time (at power-on) Reset input time (other than at power-on) Symbol Pin name Conditions Value Min tINITX INIT tCP × 10 ns *2 Max Unit ns Remarks *1
*1 : When turning the power on, keep INIT input until the oscillation circuit provides stable oscillation. *2 : tCP indicates cycle time of CPU operating clock.
tINITX
INIT
VIL
VIL
55
MB91230 Series
(6)UART timing (MB91V230, MB91F233 : VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C) (MB91F233L, MB91233L : VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → Valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → Valid SIN hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name SCK0 to SCK2 SCK0 to SCK2, SOT0 to SOT2 Conditions Value Min 8 tCYCP * −80 100 60 4 tCYCP * 4 tCYCP* 60 60 Max 80 150 Unit Remarks ns ns ns ns ns ns ns ns ns
Internal shift clock SCK0 to SCK2, operation SIN0 to SIN2 SCK0 to SCK2, SIN0 to SIN2 SCK0 to SCK2 SCK0 to SCK2 SCK0 to SCK2, SOT0 to SOT2 External shift clock operation SCK0 to SCK2, SIN0 to SIN2 SCK0 to SCK2, SIN0 to SIN2
* : tCYCP represents the cycle time of peripheral operating clock. Note : This specification applies to clock synchronous mode operation.
56
MB91230 Series
• Internal shift clock mode
tSCYC VOH
SCK0 to SCK2
VOL tSLOV
VOL
SOT0 to SOT2
VOH VOL tIVSH VOH tSHIX VOH VOL
SIN0 to SIN2
VOL
• External shift clock mode
tSLSH tSHSL VOH VOL tSLOV VOH VOL VOH
SCK0 to SCK2
SOT0 to SOT2
VOL tIVSH VOH tSHIX VOH VOL
SIN0 to SIN2
VOL
57
MB91230 Series
(7) Free-run timer clock, Reload timer event input, Up/down counter input, Input capture input, Interrupt input timing (MB91V230, MB91F233 : VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to + 85 °C) (MB91F233L, MB91233L : VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to + 85 °C) Parameter Symbol Pin name CKI0, CKI1 TIN0, TIN1, TIN2 IC0, IC1 AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1 INT0 to INT15 * : tCYCP indicates peripheral clock cycle time.
tTIWH VIH VIL VIL tTIWL VIH
Conditions
Value Min Max
Unit
Remarks
Input pulth width
tTIWH tTIWL
tCYCP × 2
ns
*
tCYCP × 3
ns
*
(8) A/D trigger, PWI (PWC) input timing (MB91V230, MB91F233 : VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to + 85 °C) (MB91F233L, MB91233L : VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to + 85 °C) Value CondiParameter Symbol Pin name Unit Remarks tions Min Max A/D trigger input (falling) PWI (PWC) input (rising) tTADTG tPWI ADTG0 ADTG1 PWI0, PWI1 tCYCP × 2 tCYCP × 2 ns ns * *
* : tCYCP indicates peripheral clock cycle time.
tTADTG VIH VIL VIL tTPWI VIH
58
MB91230 Series
5. Electrical Characteristics for the A/D Converter
(VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, AVRH = 3.0 V to 3.6 V, Ta = 0 °C to +85 °C) Parameter Resolution Total error*
1 1
Value Min −5.0 −3.5 −2.5 −2.0 AVRH−5.5 1.69*2
1
Typ +1.0 AVRH−1.0 3.6 470 40
Max 10 +5.0 +3.5 +2.5 +6.0 AVRH+3.0 5 10 4
Unit bit LSB LSB LSB LSB LSB µs mA µA µA µA pF LSB
Remarks
Nonlinear error*
Differential linear error*1 Zero transition voltage* Full transition voltage* Conversion time Power supply voltage (analog+digital) Reference power supply current (between AVRH and AVRL) Analog input capacitance Inter-channel disparity *1 : Measured in the CPU sleep state
1
AVCC = 3.3 V, At AVRH = 3.3 V At CPU sleep mode
AVRH = 3.0 V, At AVRL = 0.0 V*3 At power-down*4
*2 : It depends on the clock cycle supplied to peripheral resources. *3 : AVRL pin is only for FLGA package product. AVRL pin is connected to AVSS inside the IC on QFP package product. *4 : The current when the CPU is in stop mode and the A/D converter is not operaring.
59
MB91230 Series
• About the external impedance of the analog input and its sampling time • A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sampling and hold capacitor is insufficient, adversely affecting A/D conversion precision. • Analog input circuit model
R
Analog input
Comparator
C
During sampling : ON
R MB91233L MB91F233 MB91F233L Note : The values are reference values. 0.18 kΩ (Max) 0.18 kΩ (Max) 0.18 kΩ (Max) C 63.0 pF (Max) 39.0 pF (Max) 39.0 pF (Max)
• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. • The relationship between the external impedance and minimum sampling time (External impedance = 0 kΩ to 100 kΩ)
100 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 MB91F233 MB91F233L
(External impedance = 0 kΩ to 20 kΩ)
20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 MB91F233 MB91F233L
External impedance (kΩ)
External impedance (kΩ)
MB91233L
MB91233L
25
30
35
5
6
7
8
Minimum sampling time (µs)
Minimum sampling time (µs)
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. • About errors As |AVRH − AVSS| becomes smaller, values of relative errors grow larger. 60
MB91230 Series
6. Electrical Characteristics for the D/A Converter
(VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = 0 °C to +85 °C) Parameter Resolution Nonlinear error Differential linear error Value Min −2.0 −1.0 Conversion speed Output impedance 2.0 Analog current 3.0 2.9 40 0.1 3.8 460* µs kΩ µA µA µA 10 µs conversion, when the output is unloaded When the input digital code is fixed at 7AH or 85H At power-down Typ 0.6 Max 8 +2.0 +1.0 Unit bit LSB LSB µs When the output is unloaded When the output is unloaded When load capacitance (CL) = 20 pF When load capacitance (CL) = 100 pF Remarks
* : The current consumption by this D/A converter varies with input digital code. This standard value indicates the current consumed when the digital code that maximizes the current consumption is input.
7. Flash Memory Write/Erase Characteristics
Parameter Sector erase time Chip erase time Byte write time Chip write time Erase/write cycle Conditions Ta = + 25 °C, Vcc = 5.0 V Ta = + 25 °C, Vcc = 5.0 V Ta = + 25 °C, Vcc = 5.0 V Ta = + 25 °C, Vcc = 5.0 V Value Min 10,000 20 Typ 1 10 8 2.1 Max 15 3,600 Unit s s µs s cycle year * Remarks Excludes 00H programming prior erasure Excludes 00H programming prior erasure Not including system-level overhead time. Not including system-level overhead time.
Flash data retention time Average Ta = + 85 °C
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 85 °C).
61
MB91230 Series
s ORDERING INFORMATION
Part number MB91V230CR-ES MB91F233PFF-GE1 MB91F233LPFF-GE1 MB91F233LLGA-GE1 MB91233LPFF-G-xxx-BNDE1 MB91233LLGA-Gxxx-BNDE1 Package 401-pin ceramic PGA (PGA-401C-A02) 120-pin plastic LQFP (FPT-120P-M05) 120-pin plastic LQFP (FPT-120P-M05) 128-pin plastic FLGA (LGA-128P-M01) 120-pin plastic LQFP (FPT-120P-M05) 128-pin plastic FLGA (LGA-128P-M01) Remarks
62
MB91230 Series
s PACKAGE DIMENSIONS
401-pin Ceramic PGA (PGA-401C-A02)
48.26 ± 0.55 SQ (1.900 ± .022) 2.54 (.100) TYP 0.40 ± 0.10 DIA (.016 ± .004) 1.00 (.039) DIA TYP (4 PLCS)
45.72 (1.800) REF
INDEX AREA
1.20 ± 0.25 (.047 ± .010) 3.40 ± 0.40 (.134 ± .016) 5.27 (.207) MAX
1.02 (.040) C TYP (4 PLCS)
EXTRA INDEX PIN
C
1994 FUJITSU LIMITED R401002SC-2-2
Dimensions in mm (inches) . Note : The values in parentheses are reference values.
(Continued)
63
MB91230 Series
120-pin Plastic LQFP (FPT-120P-M05)
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
90
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
61
91
60
0.08(.003)
Details of "A" part 1.50 –0.10
+0.20 +.008
(Mounting height)
INDEX
.059 –.004
120
31
"A"
0~8˚
LEAD No.
1
30
0.40(.016)
0.16±0.03 (.006±.001)
0.07(.003)
M
0.145±0.055 (.006±.002)
0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006)
0.10±0.10 (.004±.004) (Stand off) 0.25(.010)
C
2003 FUJITSU LIMITED F120006S-c-4-5
Dimensions in mm (inches) . Note : The values in parentheses are reference values.
(Continued)
64
MB91230 Series
(Continued) 128-pin plastic FLGA (LGA-128P-M01)
8.30(.327) REF 7.15(.282) REF 0.65(.026) TYP 12 11 10 9 8 7 6 5 4 3 2 1 MLKJHGFEDCBA INDEX AREA 1.00(.040)MAX (Seated Height) 3-ø0.50 (3-ø.020) 128-ø0.35±0.05 (128-ø.014±.002) 0.08(.003) (0.50) ((.020)) Index
ø0.08(ø.003) M
9.00±0.10(.354±.004)SQ
8.30(.327) REF 7.15(.282) REF
0.65(.026) TYP
(0.50) ((.020))
C
2004 FUJITSU LIMITED L128001S-c-1-1
Dimensions in mm (inches) . Note : The values in parentheses are reference values.
65
MB91230 Series
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0410 © 2004 FUJITSU LIMITED Printed in Japan
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