MB91248PFV-GSE1

FUJITSU SEMICONDUCTOR DATA SHEET DS07-16803-1E 32-bit Microcontroller CMOS FR60Lite MB91245/S Series MB91247/247S/248/248S/F248/F248S/MB91V245A ■ OVERVIEW MB91245/S series is Fujitsu’s general-purpose 32-bit RISC microcontroller, which is designed for embedded control applications that require high-speed real-time processing of consumer appliances. This microcontroller uses FR60Lite as its CPU, compatible with other products in the FR* family. This series incorporates an LCD controller and stepping motor controller. * : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited. ■ FEATURES • FR60Lite CPU • 32-bit RISC, load/store architecture, 5-stage pipeline • Maximum operating frequency : 32 MHz (Source oscillation is 4 MHz with x8 multiplier – PLL clock multiplier system) • 16-bit fixed-length instructions (basic instructions) • Instruction execution speed : 1 instruction per cycle • Instruction set optimized for embedded application : Memory-to-memory transfer, bit manipulation, barrel shift instructions etc. • Instructions adapted for programming C language : Function entry/exit instructions, multiple-register load/store instructions. • Register interlock function : Easier assembler coding enabled • Built-in multiplier supported at the instruction level Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles (Continued) Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development. Copyright©2006 FUJITSU LIMITED All rights reserved MB91245/S Series (Continued) • Interrupt (PC/PS save) : 6 cycles (16 priority levels) • Harvard architecture allowing program access and data access to be executed simultaneously. • Instruction set compatible with FR family • Internal Peripheral Functions • Internal ROM size & ROM type MASK ROM : 256 Kbytes (MB91248/S) / 128 Kbytes (MB91247/S) Flash Memory : 256 Kbytes • Internal RAM size : 16 Kbytes (MB91248/S, MB91F248/S) / 8 Kbytes (MB91247/S) / 32 Kbytes (MB91V245A) • General-purpose ports : up to 120 ports (includes 4 input-only ports) • 8/10-bit A/D converter (Sequential comparison type) 8/10-bit resolution : 32 channels Conversion time : 3 µs (16/32 MHz) Set the PLL multiplier and the division ratio of peripheral circuit clocks so that the above conversion time is achieved. 32 MHz : Source oscillation (4 MHz) with x8 multiplier, divided by 1 16 MHz : Source oscillation with x8 multiplier, divided by 2 • External interrupt input : 8 channels • Bit search module (for REALOS) Search function to locate the position of the first bit that changes from “1” to “0” in one word, from the MSB (Most Significant Bit) • UART (full duplex double buffer type) : 1 channel Parity enable/disable selectable Asynchronous clock operation (start-stop synchronization) and synchronous clock operation selectable Dedicated baud-rate timer (U-Timer) embedded in each channel External clock can be used as transfer clock Parity, frame, overrun error detection functions provided • LIN-UART (full duplex double buffer type) : 3 channels Synchronous/asynchronous clock operations selectable Sync-break detection Dedicated built-in baud-rate generator • Stepping motor controller (SMC) : 6 channels 8-bit PWM with 4 high-current outputs for each channel • 8/16-bit PPG timer : 8/4 channels • 16-bit reload timer : 3 channels • 16-bit free-run timer : 2 channels (ICU/OCU linkage) • 16-bit pulse width counter : 1 channel • Input capture : 4 channels (linked to ch.0 and ch.1 of free-run timer) ch.0 linked to PWC • Output compare : 2 channels (linked to ch.0 of free-run timer) • LCD controller : SEG00 to SEG31/COM0 to COM3 (shared with port) • 16-bit timebase/watch dog timer • Sound generator • Real-time clock • 32 kHz sub clock (not supported in single clock products) • C-CAN : 2 channels • Low power consumption modes : sleep mode, stop mode, watch mode • Package : LQFP-144 (FPT-144P-M08) • CMOS technology : 0.35 µm • Power supply voltage : 5 V (Internal logic : 3.3 V, I/O : 5.0 V (step-down circuit used)) 2 MB91245/S Series ■ PRODUCT LINEUP A table below shows the product lineup of the MB91245/S series. Embedded peripheral functions which are not listed are common functions. MB91V245A MB91247/S MB91248/S MB91F248/S ROM/Flash size RAM size External interrupt DMA Controller A/D Converter UART LIN-UART Stepping Motor Controller 8 /16-bit PPG 16-bit Reload Timer 16-bit Free Run Timer 16-bit Pulse Width Counter Input Capture Unit Output Compare Unit LCD Controller Sound Generator Real Time Clock 32 kHz Sub Clock External bus Others On Chip Debug Support Unit C-CAN unit EVA device DSU4 2 channels 32-message buffer Yes External SRAM 32 Kbytes 128 Kbytes 8 Kbytes 8 channels 5 channels 32 channels 1 channel 3 channels 6 channels 8 channels/4 channels 3 channels 2 channels 1 channel 4 channels 2 channels 4 COM, 32 SEG 1 channel Yes Yes/No (S series) Yes/No (S series) Yes/No (S series) Addr 16 bits Data 16 bits MASK ROM product MASK ROM product ⎯ Flash memory product 256 Kbytes 16 Kbytes 256 Kbytes 16 Kbytes 3 MB91245/S Series ■ PIN ASSIGNMENT (TOP VIEW) P23/SEG03/A03 P22/SEG02/A02 P21/SEG01/A01 P20/SEG00/A00 PD7/COM3/PPG7 PD6/COM2/PPG5 PD5/COM1/PPG3 PD4/COM0/PPG1 PD3/IN3 PD2/TIN2/IN2 PD1/TIN1/IN1 PD0/TIN0/IN0/PWC0 PG3/TOT2/PPG6 PG2/TOT1/PPG4 PG1/TOT0/PPG2 X0 X1 VSS VCC PG0/PPG0 P47/SGO/SYSCLK P46/SGA/AS P57/OUT1/RDY P56/OUT0/WR1 P55/SCK5/WR0 P54/SOT5/RD P53/SIN5/CK1/CS3 P52/SCK4/CS2 P51/SOT4/CS1 P50/SIN4/CK0/CS0 P45/SCK3 P44/SOT3 P43/SIN3 P42/SCK0 P41/SOT0 P40/SIN0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 A04/SEG04/P24 A05/SEG05/P25 A06/SEG06/P26 A07/SEG07/P27 A08/SEG08/P30 A09/SEG09/P31 A10/SEG10/P32 A11/SEG11/P33 A12/SEG12/P34 A13/SEG13/P35 A14/SEG14/P36 A15/SEG15/P37 D08/SEG16/P10 D09/SEG17/P11 D10/SEG18/P12 X0A X1A VCC VSS VCC3C D11/SEG19/P13 D12/SEG20/P14 D13/SEG21/P15 D14/SEG22/P16 D15/SEG23/P17 D00/INT0/SEG24/P00 D01/INT1/SEG25/P01 D02/INT2/SEG26/P02 D03/INT3/SEG27/P03 D04/INT4/SEG28/P04 D05/INT5/SEG29/P05 D06/SEG30/P06 D07/ATG/SEG31/P07 RX0/INT6/P70 TX0/P71 RX1/INT7/P72 INIT MOD0 MOD1 MOD2 DVSS DVCC PE7/PWM2M5 PE6/PWM2P5 PE5/PWM1M5 PE4/PWM1P5 PE3/PWM2M4 PE2/PWM2P4 PE1/PWM1M4 PE0/PWM1P4 PA3/PWM2M3 PA2/PWM2P3 PA1/PWM1M3 PA0/PWM1P3 DVSS DVCC PF7/AN15 PF6/AN14 PF5/AN13 PF4/AN12 PF3/AN11 PF2/AN10 PF1/AN9 PF0/AN8 P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 4 P73/TX1 DVCC DVSS PB0/PWM1P0 PB1/PWM1M0 PB2/PWM2P0 PB3/PWM2M0 PB4/PWM1P1 PB5/PWM1M1 PB6/PWM2P1 PB7/PWM2M1 PC0/PWM1P2 PC1/PWM1M2 PC2/PWM2P2 PC3/PWM2M2 DVCC DVSS P97/AN31 P96/AN30 P95/AN29 P94/AN28 P93/AN27 P92/AN26 P91/AN25 P90/AN24 P87/AN23 P86/AN22 P85/AN21 P84/AN20 P83/AN19 P82/AN18 P81/AN17 P80/AN16 AVCC AVRH AVSS/AVRL (FPT-144P-M08) MB91245/S Series ■ PIN DESCRIPTIONS Pin no. Pin name P24 to P27 1 to 4 SEG04 to SEG07 A04 to A07 P30 to P37 5 to 12 SEG08 to SEG15 A08 to A15 P10 to P12 13 to 15 16 17 18 19 20 21 to 25 SEG16 to SEG18 D08 to D10 X0A X1A VCC VSS VCC3C P13 to P17 SEG19 to SEG23 D11 to D15 P00 to P05 26 to 31 SEG24 to SEG29 INT0 to INT5 D00 to D05 P06 32 SEG30 D06 P07 33 SEG31 ATG D07 P70 34 INT6 RX0 35 P71 TX0 I I G G G G B B ⎯ ⎯ ⎯ G F F I/O circuit type* SEG output pin for LCDC Bits 04 to 07 pins of external address bus General purpose I/O port pins SEG output pins for LCDC Bits 08 to 15 pins of external address bus General purpose I/O port pins SEG output pins for LCDC Bits 08 to 10 pins of external data bus Sub clock (oscillation) input Sub clock (oscillation) output Power supply pins GND pins Capacitor connection pin for internal regulator General purpose I/O port pins SEG output pins for LCDC Bits 11 to 15 pins of external data bus General purpose I/O port pins SEG output pins for LCDC External interrupt input pins Bits 00 to 05 pins of external data bus General purpose I/O port pin SEG output pins for LCDC Bit 06 pin of external data bus General purpose I/O port pin SEG output pin for LCDC External trigger input pin at using of A/D converter Bit 07 pin of external data bus General purpose I/O port pin External interrupt input pin RX0 input pin of CAN0 General purpose I/O port pin TX0 output pin of CAN0 (Continued) Function General purpose I/O port pins 5 MB91245/S Series Pin no. Pin name P72 I/O circuit type* I External interrupt input pin RX1 input pin of CAN1 I ⎯ ⎯ H H H H H H H H H H H H ⎯ ⎯ Function General purpose I/O port pin 36 INT7 RX1 P73 TX1 DVCC DVSS PB0 PWM1P0 PB1 PWM1M0 PB2 PWM2P0 PB3 PWM2M0 PB4 PWM1P1 PB5 PWM1M1 PB6 PWM2P1 PB7 PWM2M1 PC0 PWM1P2 PC1 PWM1M2 PC2 PWM2P2 PC3 PWM2M2 DVCC DVSS 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 General purpose I/O port pin TX1 output pin of CAN1 Power supply input pins for SMC GND pins for SMC General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller Power supply input pins for SMC GND pins for SMC (Continued) 6 MB91245/S Series Pin no. Pin name P97 to P90 I/O circuit type* Function General-purpose I/O port pins : Valid when analog input is prohibited Analog input pins of A/D converter : Valid when ADER register is set to analog input General-purpose I/O port pins : Valid when analog input is prohibited Analog input pins of A/D converter : Valid when ADER register is set to analog input Analog power supply input pin for A/D converter Analog base voltage input pin for A/D converter Analog GND/analog base low voltage input pin for A/D converter General-purpose I/O port pins : Valid when analog input is prohibited Analog input pins of A/D converter : Valid when ADER register is set to analog input General-purpose I/O port pins : Valid when analog input is prohibited Analog input pins of A/D converter : Valid when ADER register is set to analog input Power supply input pins for SMC GND pins for SMC General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller (Continued) 7 54 to 61 AN31 to AN24 P87 to P80 62 to 69 AN23 to AN16 70 71 72 AVCC AVRH AVSS/AVRL P60 to P67 73 to 80 AN0 to AN7 PF0 to PF7 81 to 88 AN8 to AN15 89 90 91 92 93 94 95 96 97 98 DVCC DVSS PA0 PWM1P3 PA1 PWM1M3 PA2 PWM2P3 PA3 PWM2M3 PE0 PWM1P4 PE1 PWM1M4 PE2 PWM2P4 PE3 PWM2M4 E E ⎯ ⎯ ⎯ E E ⎯ ⎯ H H H H H H H H MB91245/S Series Pin no. 99 100 101 102 103 104 105 106 107 108 Pin name PE4 PWM1P5 PE5 PWM1M5 PE6 PWM2P5 PE7 PWM2M5 DVCC DVSS MOD2 MOD1 MOD0 INIT P40 I/O circuit type* H H H H ⎯ ⎯ D D D C Function General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller Power supply input pins for SMC GND pins for SMC Mode pin 2 : Used to set basic operating mode and required to be connected to VCC or VSS Mode pin 1 : Used to set basic operating mode and required to be connected to VCC or VSS Mode pin 0 : Used to set basic operating mode and required to be connected to VCC or VSS External reset input pin General-purpose I/O port pin : Valid when UART0 data input is prohibited 109 SIN0 I UART0 serial data input pin, requiring output by ports to be stopped while UART0 is performing input operation, except when executed intentionally, as this input is always in use General-purpose I/O port pin : Valid when UART0 data output is prohibited UART0 serial data output pin : Valid when UART0 data output is permitted General-purpose I/O port pin : Valid when clock output of UART0 is prohibited UART0 clock input and output pin for serial communication : Valid when clock output of UART0 is permitted General-purpose I/O port pin : Valid when LIN-UART0 data input is prohibited P41 110 SOT0 P42 111 SCK0 P43 112 SIN3 I I I LIN-UART0 serial data input pin, requiring output by ports to be stopped while LIN-UART0 is performing input operation, except when executed intentionally, as this input is always in use General-purpose I/O port pin : Valid when LIN-UART0 data output is prohibited LIN-UART0 serial data output pin : Valid when data output of LIN-UART0 is permitted (Continued) P44 113 SOT3 I 8 MB91245/S Series Pin no. Pin name P45 I/O circuit type* Function General-purpose I/O port pin : Valid when clock output of LIN-UART0 is prohibited LIN-UART0 clock input and output pin for serial communication : Valid when clock output of LIN-UART0 is permitted General-purpose I/O port pin Serial data input pin of LIN-UART1 : LIN-UART1, requiring output by ports to be stopped while LIN-UART1 is performing input operation, except when executed intentionally, as this input is always in use External clock input pin of free-run timer 0 Output pin of chip select 0 : Valid when external bus mode is selected General-purpose I/O port pin LIN-UART1 serial data output pin : Valid when data output of LIN-UART1 is permitted Output pin of chip select 1 : Valid when output of chip select 1 is permitted General-purpose I/O port pin LIN-UART1 clock input and output pin for serial communication : Valid when clock output of LIN-UART1 is permitted Output pin of chip select 2 : Valid when output of chip select 2 is permitted General-purpose I/O port pin Serial data input pin of LIN-UART2 : LIN-UART2, requiring output by ports to be stopped while LIN-UART2 is performing input operation, except when executed intentionally, as this input is always in use External clock input pin of free-run timer 1 Output of chip select 3 : Valid when output of chip select 3 is permitted General-purpose I/O port pin Serial data output pin of LIN-UART2 : Valid when data output of LIN-UART2 is permitted Read strobe output pin of external bus : Valid when external bus mode is selected General-purpose I/O port pin LIN-UART2 clock input and output pin for serial communication : Valid when clock output of LIN-UART2 is permitted Write strobe output pin of external bus : Valid when WR0 output is permitted in external bus mode (Continued) 9 114 SCK3 P50 I SIN4 115 CK0 CS0 P51 116 SOT4 CS1 P52 117 SCK4 CS2 P53 I I I SIN5 118 CK1 CS3 P54 119 SOT5 RD P55 120 SCK5 WR0 I I I MB91245/S Series Pin no. Pin name P56 I/O circuit type* Function General-purpose I/O port pin 121 OUT0 WR1 P57 I Output compare output pin Write strobe output pin of external bus : Valid when WR1 output is permitted in external bus mode General-purpose I/O port pin Output compare output pin External ready input pin : Valid when external ready input is permitted General-purpose I/O port pin Sound generator pin External address strobe output pin : Valid when address strobe output is permitted General-purpose I/O port pin Sound generator pin 122 OUT1 RDY P46 J 123 SGA AS P47 SGO I 124 SYSCLK PG0 125 126 127 128 129 PPG0 VCC VSS X1 X0 PG1 130 TOT0 PPG2 PG2 131 TOT1 PPG4 PG3 132 TOT2 PPG6 I System clock output pin : Valid when system clock output is permitted and outputs the same clock as the operating frequency of external bus (Output is stopped in STOP mode) General-purpose I/O port pin Output of PPG timer 0 : Valid when output of PPG timer 0 is permitted Power supply pins GND pins Main clock (oscillation) output pin Main clock (oscillation) input pin General-purpose I/O port pin Output pin for reload timer Output pin of PPG timer 2 : Valid when output of PPG timer 2 is permitted General-purpose I/O port pin Output pin for reload timer Output pin of PPG timer 4 : Valid when output of PPG timer 4 is permitted General-purpose I/O port pin Output pin for reload timer Output pin of PPG timer 6 : Valid when output of PPG timer 6 is permitted (Continued) I ⎯ ⎯ A A I I I 10 MB91245/S Series (Continued) Pin no. Pin name PD0 TIN0 I/O circuit type* Function General-purpose I/O port pin Event input pin for reload timer Trigger input pin of input capture 0 : This sets input capture to trigger input and is enabled when input port is set up. When set as input capture input, it requires output by ports to be stopped, except when executed intentionally, as this input is always used. Input pin of pulse width counter 0 of PWC0 : Valid when input of pulse width counter 0 of PWC0 is permitted General-purpose I/O port pin Event input pin for reload timer K IN1 Trigger input pin of input capture 1 : This sets input capture to trigger input and is enabled when input port is set up. When set as input capture input, it requires output by ports to be stopped, except when executed intentionally, as this input is always used. General-purpose I/O port pin Event input pin for reload timer K IN2 Trigger input pin of input capture 2 : This sets input capture to trigger input and is enabled when input port is set up. When set as input capture input, it requires output by ports to be stopped, except when executed intentionally, as this input is always used. General-purpose I/O port pin K Trigger input pin of input capture 3 : This sets input capture to trigger input and is enabled when input port is set up. When set as input capture input, it requires output by ports to be stopped, except when executed intentionally, as this input is always used. General-purpose I/O port pin F Output pin of COM0 to COM3 of LCDC Output pin of PPG timer 1, 3, 5 and 7 : Valid when output of PPG timer 1, 3, 5 and 7 is permitted General purpose I/O port pins F SEG output pins for LCDC Bits 00 to 03 pins of external address bus 133 IN0 K PWC0 PD1 TIN1 134 PD2 TIN2 135 PD3 136 IN3 PD4 to PD7 137 to 140 COM0 to COM3 PPG1, PPG3, PPG5, PPG7 P20 to P23 141 to 144 SEG00 to SEG03 A00 to A03 * : For information about the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”. 11 MB91245/S Series ■ I/O CIRCUIT TYPE Group X1 Circuit Type Remarks For high speed (source oscillation of main clock) • Oscillation circuit • Feedback resistance X0 : approx. 1 MΩ Clock input A X0 Standby control X1A Clock input For low speed (source oscillation of sub clock) • Oscillation circuit • Feedback resistance X0A : approx. 7 MΩ B X0A Standby control • CMOS hysteresis input • Pull-up resistor provided • No standby control P-ch P-ch N-ch C R Digital input (Continued) 12 MB91245/S Series Group R Circuit Type MASK ROM product Hysteresis input Remarks • MASK ROM product Hysteresis input Pull-down resistor provided only for MOD2 & MOD1 • Flash memory product Hysteresis input High-voltage control for Flash test provided N-ch Flash memory product D N-ch N-ch N-ch N-ch R Control Mode input Diffused resistor P-ch Digital output N-ch E Digital output R • CMOS output (4 mA) • Hysteresis (Automotive level) input (Standby control provided) • Analog input (Analog input is valid when the corresponding ADER bit is set to 1.) Digital input Standby control Analog input P-ch N-ch • CMOS output (4 mA) • LCDC output • Hysteresis (Automotive level) input (Standby control provided) F R LCDC output R Hysteresis input Standby control (Continued) 13 MB91245/S Series Group P-ch N-ch Circuit Type Remarks • CMOS output (4 mA) • LCDC output • Hysteresis (Automotive level) input (Standby control provided) • Hysteresis (CMOS level) input (Standby control provided) G R R R LCDC output Hysteresis input (Automotive level) Hysteresis input (CMOS level) Standby control • CMOS output High current output for PWM (30 mA) • Hysteresis (Automotive level) input (Standby control provided) P-ch Digital output N-ch H R Digital output Digital input Standby control • CMOS output (4 mA) • Hysteresis (Automotive level) input (Standby control provided) P-ch Digital output N-ch I Digital output R Digital input Standby control (Continued) 14 MB91245/S Series (Continued) Group P-ch N-ch Circuit Type Remarks • CMOS output (4 mA) • Hysteresis (Automotive level) input (Standby control provided) • Hysteresis (CMOS level) input (Standby control provided) J R R Hysteresis input (Automotive level) Hysteresis input (CMOS level) Standby control P-ch • Hysteresis (Automotive level) input (Standby control provided) N-ch K R Digital input Standby control 15 MB91245/S Series ■ HANDLING DEVICES • Preventing Latch-up Latch-up may occur in a CMOS IC, if a voltage greater than VCC pin or less than VSS pin is applied to input and output pin, or if an above-rating voltage is applied between VCC and VSS. When latch-up occurs, it may significantly increase the power supply current, and may cause thermal destruction of an element. When you use a CMOS IC, be very careful not to exceed the maximum rating. • Treatment of Unused Input Pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by performing a pull-up or pull-down with a resistance of 2 kΩ or more. An unused I/O pin should be set to the output status and left open. When set to the input status, it should be handled in the same way as an input pin. • About power supply pins If there are multiple VCC and VSS pins, from the point of view of device design pins to be of the same potential are connected inside the device to prevent such malfunctioning as latch-up. However, you must connect all the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. Furthermore, it is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS near this device. This device incorporates a regulator. When using the device with 5V power supply, apply that power supply to the VCC pin and always connect a 1 µF or greater capacitor to the VCC3C for the regulator. Example of power supply connection 5V 5V VCC AVCC AVRH AVSS VSS VCC3C 1 µF GND 16 MB91245/S Series • Crystal oscillator circuit Noise near the X0/X1 pins and X0A/X1A pins may cause the device to malfunction. Design the PC board such that X0/X1 pins, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to the ground are placed as near one another as possible. When routing the X0 and X1 signals, they should be shielded for use on the board. Caution must be taken especially when using a pin next to the X0. It is strongly recommended to design the PC board artwork with the X0, X1, X0A and X1A pins surrounded by ground plane because stable operation can be expected with such a layout. In addition, a sub clock is required even when a dual clock product is used as a single clock product. When using MB91F248S/248S/247S, connect the X0A pin to GND and leave the X1A pin open. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. • Mode pins (MOD0 to MOD2) These pins should be connected directly to VCC or VSS pins. To prevent the device erroneously switching to test mode due to noise, design the PC board such that the distance between the mode pins and VCC or VSS pins is as short as possible and the connection impedance is now. • Operation at start-up Always use the INIT pin to perform a setting initialization reset (INIT) after power-on. Immediately after poweron, hold the low level input to the INIT pin for the stabilization wait time required for the oscillator circuit, to take the oscillation stabilization wait time for the oscillator circuit. For INIT via the INIT pin, the oscillation stabilization wait time setting is initialized to the minimum value. • Source oscillation input upon power-on When power-on, always input the clock for the duration of the oscillation stabilization delay time. • Treatment of power supply pins on A/D converter Connect to ensure “AVCC = AVRH = VCC and AVSS = VSS” even if the A/D converter is not in use. • Power-on sequence for power supply analog input of A/D converter Always supply power to the A/D converter (AVCC and AVRH) and apply analog input (AN0 to AN 31) after turning on the digital power supply (VCC). Also, turn off the power supply for the A/D converter and analog input before turning off the digital power supply (VCC). In so doing, the power supply must be turn on and off so that AVRH does not exceed AVCC. Even when using a pin shared with analog input as an input port, ensure that the input voltage does not exceed AVCC (There is no problem in turning on or off the analog and digital power supplies at the same time). • Handling of power supply for high-current output buffer pin (DVCC, DVSS) Always apply power to high-current output buffer pins (DVCC) after turning on the digital power supply (VCC). In addition, turn off the power supply for the high-current output buffer pins before turning off the digital power supply (VCC). Apply the same power as for high-current output buffer pins even when using such pins as general-purpose ports. (There is no problem in turning on or off the power supply for the high-current output buffer pins and the digital power supply at the same time.) Always use the GND pin (DVSS) for the high-current output buffer pin at the same potential as the digital GND (VSS). 17 MB91245/S Series • About switching from main clock mode to sub clock mode or stop mode Always stop the main clock after switching the main clock mode to the sub clock mode or stop mode. Also secure the oscillation stabilization wait time when returning from the sub clock mode or stop mode to the main clock mode. • About Flash write Note that Flash write is not possible in the sub mode. 18 MB91245/S Series ■ BLOCK DIAGRAM FR 60Lite CPU core 32 32 Bit search DMAC 5 channels 32 ROM 256 Kbytes/ 128 Kbytes/ Flash 256 Kbytes RAM 16 Kbytes/8 Kbytes Bus converter X0, X1 X0A, X1A* MOD0 to MOD2 INIT Clock control Interrupt controller 32 16 adapters 16 C-CAN 2 channels RX0, RX1 TX0, TX1 Port I/F Reload timer 3 channels PWC timer 1 channel 4 channels (when set to 16 bits) 8/16-bit PPG timer PORT INT0 to INT7 SIN0 SOT0 SCK0 external interrupt 8 channels UART 1 channel U-TIMER 1 channel ICU2 ICU 4 channels ICU3 ICU0 ICU1 TIN0 to TIN2 TOT0 to TOT2 PWC0 PPG0 to PPG7 IN0 to IN3 Real Time Clock CPU Detect Reset OUT0, OUT1 CK0, CK1 SGA SGO ATG AVCC/AVSS AVRH AN0 to AN31 SIN3 to SIN5 SOT3 to SOT5 SCK3 to SCK5 OCU OCU0 2 channels OCU1 FRT FRT0 2 channels FRT1 Sound Generator 8/10-bit 32 channels input A/D converter LIN-UART 3 channels LCD controller 32 SEG × 4 COM COM0 to COM3 SEG00 to SEG31 6 channels Stepper Motor Controller PWM1P0 to PWM1P5 PWM1M0 to PWM1M5 PWM2P0 to PWM2P5 PWM2M0 to PWM2M5 * : The sub clock is not supported in single clock products. 19 MB91245/S Series ■ MEMORY SPACE • Memory space The FR family has of 4 Gbytes logical address space (232 addresses) linearly accessible to the CPU space. • Direct addressing area The following address space areas are used as I/O areas. These areas are called direct addressing areas, in which the address of an operand can be specified directly during on instruction. The direct area varies depending on the size of data to be accessed as follows. → Byte data access : 000H to 0FFH → Halfword data access : 000H to 1FFH → Word data access : 000H to 3FFH 20 MB91245/S Series ■ MEMORY MAP MB91V245A Single chip mode 0000 0000H I/O 0000 0400H I/O 0001 0000H 0002 0000H 0002 01B4H 0003 8000H 0004 0000H 0005 0000H 0008 0000H I/O I/O I/O I/O Internal ROM External ROM external bus mode external bus mode Direct addressing area Refer to “■ I/O MAP”. Access prohibited I/O (C-CAN) Access prohibited I/O (C-CAN) Access prohibited I/O (C-CAN) Access prohibited Internal RAM 32 KB Access prohibited Internal RAM 32 KB Access prohibited Internal RAM 32 KB Access prohibited Access prohibited Access prohibited Emulation SRAM area 0010 0000H Emulation SRAM area External area Access prohibited FFFF FFFFH External area 21 MB91245/S Series MB91F248/S Single chip mode 0000 0000H I/O 0000 0400H I/O 0001 0000H 0002 0000H 0002 01B4H 0003 C000H 0004 0000H 0005 0000H 000C 0000H I/O I/O I/O I/O Internal ROM External ROM external bus mode external bus mode Direct addressing area Refer to “■ I/O MAP”. Access prohibited I/O (C-CAN) Access prohibited I/O (C-CAN) Access prohibited I/O (C-CAN) Access prohibited Internal RAM 16 KB Access prohibited Internal RAM 16 KB Access prohibited Internal RAM 16 KB Access prohibited Access prohibited Flash memory area 256 Kbytes Access prohibited FFFF FFFFH Access prohibited Flash memory area 256 Kbytes External area External area 0010 0000H MB91248/S Single chip mode 0000 0000H I/O 0000 0400H I/O 0001 0000H 0002 0000H 0002 01B4H 0003 C000H 0004 0000H 0005 0000H 000C 0000H I/O I/O I/O I/O Internal ROM External ROM external bus mode external bus mode Direct addressing area Refer to “■ I/O MAP”. Access prohibited I/O (C-CAN) Access prohibited I/O (C-CAN) Access prohibited I/O (C-CAN) Access prohibited Internal RAM 16 KB Access prohibited Internal RAM 16 KB Access prohibited Internal RAM 16 KB Access prohibited Access prohibited MASK ROM area 256 Kbytes Access prohibited FFFF FFFFH Access prohibited MASK ROM area 256 Kbytes External area External area 0010 0000H Note : Each mode is set depending on the mode vector fetch after INIT is negated (For mode settings, refer to “■ MODE SETTINGS”). 22 MB91245/S Series MB91247/S Single chip mode 0000 0000H I/O 0000 0400H I/O 0001 0000H 0002 0000H 0002 01B4H 0003 E000H 0004 0000H 0005 0000H 000E 0000H I/O I/O I/O I/O Internal ROM External ROM external bus mode external bus mode Direct addressing area Refer to “■ I/O MAP”. Access prohibited I/O (C-CAN) Access prohibited I/O (C-CAN) Access prohibited I/O (C-CAN) Access prohibited Internal RAM 8 KB Access prohibited Internal RAM 8 KB Access prohibited Internal RAM 8 KB Access prohibited Access prohibited MASK ROM area 128 Kbytes Access prohibited FFFF FFFFH Access prohibited MASK ROM area 128 Kbytes External area External area 0010 0000H Note : Each mode is set depending on the mode vector fetch after INIT is negated (For mode settings, refer to “■ MODE SETTINGS”). 23 MB91245/S Series ■ MODE SETTINGS The FR family, sets the operation mode using mode pins (MOD2 to MOD0) and mode data. • Mode pins The mode pins (MOD2 to MOD0) specify how the mode vector fetch and reset vector fetch is performed. Other settings than these in the table are prohibited. Mode pin Mode name MOD2 MOD1 MOD0 0 0 • Mode data Data written to the internal mode register (MODR) by mode vector fetch is called mode data. After an operating mode has been set in the mode register the device operates in that operating mode. The mode data is set by all reset sources. User programs cannot set data to the mode register. Detailed description of mode data bit 31 0 30 0 29 0 28 0 27 0 26 1 25 1 24 1 Reset vector access area Internal External 0 0 0 1 Internal ROM mode vector External ROM mode vector Operating mode setting bits Bit 31 to bit 24 are reserved. Always set the value to “00000111B”. Normal operation is not guaranteed when a value other than “00000111B” is set. Note : Mode data set in the mode vector must be placed as byte data at 0x000FFFF8H. Place the data in the most significant byte from bit 31 to bit 24 as the FR family uses the big endian system for byte endian. bit 31 XXXXXXXX 24 23 XXXXXXXX 16 15 XXXXXXXX 87 Mode Data 0 Incorrect 0x000FFFF8H Correct 0x000FFFF8H 0x000FFFFCH Mode Data XXXXXXXX XXXXXXXX XXXXXXXX Reset vector 24 MB91245/S Series ■ I/O MAP The following table shows the correspondence between the memory space area and each register of the peripheral resource. [How to read the map] Address 000000H Register +0 PDR0 [R/W] B XXXXXXXX +1 PDR1 [R/W] B XXXXXXXX +2 PDR2 [R/W] B XXXXXXXX +3 PDR3 [R/W] B XXXXXXXX Block T-unit Port data register Read/Write attribute, Access unit (B : byte, H : halfword, W : word) Initial value after reset Register name (First-column register at address 4n; second-column register at 4n + 1, etc.) Location of left-most register (When using word access, the register in column 1 is in the MSB side of the data.) Note : Initial values of register bits are represented as follows : “ 1 ” : Initial value “1” “ 0 ” : Initial value “0” “ X ” : Initial value “undefined” “-” : No physical register present at this location Access by any undescribed data access attribute is prohibited. 25 MB91245/S Series Address 00000000H 00000004H 00000008H 0000000CH 00000010H 00000014H to 0000003CH 00000040H Register +0 PDR0 [R/W] B, H XXXXXXXX PDR4 [R/W] B, H XXXXXXXX PDR8 [R/W] B, H XXXXXXXX PDRC [R/W] B, H ----XXXX PDRG [R/W] B, H ----XXXX ⎯ EIRR0 [R/W] B, H, W ENIR0 [R/W] B, H, W 00000000 00000000 DICR [R/W] B, H, W -------0 HRCL [R/W] B 0--11111 ELVR0 [R/W] B, H, W 00000000 00000000 ⎯ TMR0 [R] H, W XXXXXXXX XXXXXXXX TMCSR0 [R/W] B, H, W ----0000 00000000 TMR1 [R] H, W XXXXXXXX XXXXXXXX TMCSR1 [R/W] B, H, W ----0000 00000000 TMR2 [R] H, W XXXXXXXX XXXXXXXX TMCSR2 [R/W] B, H, W ----0000 00000000 SCR [R/W] B, H, W 00000100 DRCL [W] B -------⎯ ⎯ SGDBL [R/W] B -------0 SGCR [R/W] B, H, W 0-----00 000--000 SMR [R/W] B, H, W 00--0-0UTIMC [R/W] B 0--00001 +1 PDR1 [R/W] B, H XXXXXXXX PDR5 [R/W] B, H XXXXXXXX PDR9 [R/W] B, H XXXXXXXX PDRD [R/W] B, H 0000XXXX +2 PDR2 [R/W] B, H 00000000 PDR6 [R/W] B, H XXXXXXXX PDRA [R/W] B, H ----XXXX PDRE [R/W] B, H XXXXXXXX ⎯ +3 PDR3 [R/W] B, H XXXX0000 PDR7 [R/W] B, H ----XXXX PDRB [R/W] B, H XXXXXXXX PDRF [R/W] B, H XXXXXXXX Block Port Data Register Reserved External Interrupt Control (INT0 to INT7) Delay Interrupt Module 00000044H 00000048H 0000004CH 00000050H 00000054H 00000058H 0000005CH 00000060H 00000064H 00000068H to 0000008CH 00000090H 00000094H TMRLR0 [W] H, W XXXXXXXX XXXXXXXX ⎯ 00001000 Reload Timer 0 TMRLR1 [W] H, W XXXXXXXX XXXXXXXX ⎯ TMRLR2 [W] H, W XXXXXXXX XXXXXXXX ⎯ SSR [R/W] B, H, W 00001000 SIDR [R/W] B, H, W XXXXXXXX Reload Timer 1 Reload Timer 2 UART0 U-TIMER0 UTIM [R] H (UTIMR [W] H) 00000000 00000000 Reserved SGAR [R/W] B, H, W SGFR [R/W] B, H, W SGTR [R/W] B, H, W SGDR [R/W] B, H, W 00000000 XXXXXXXX XXXXXXXX XXXXXXXX Sound Generator (Continued) 26 MB91245/S Series Address Register +0 LCDCMR [R/W] B, H, W ----0000 VRAM0 [R/W] B, H, W XXXXXXXX VRAM4 [R/W] B, H, W XXXXXXXX VRAM8 [R/W] B, H, W XXXXXXXX VRAM12 [R/W] B, H, W XXXXXXXX +1 ⎯ VRAM1 [R/W] B, H, W XXXXXXXX VRAM5 [R/W] B, H, W XXXXXXXX VRAM9 [R/W] B, H, W XXXXXXXX VRAM13 [R/W] B, H, W XXXXXXXX ⎯ +2 LCR0 [R/W] B, H, W 00010000 VRAM2 [R/W] B, H, W XXXXXXXX VRAM6 [R/W] B, H, W XXXXXXXX VRAM10 [R/W] B, H, W XXXXXXXX VRAM14 [R/W] B, H, W XXXXXXXX +3 LCR1 [R/W] B, H, W 00000000 VRAM3 [R/W] B, H, W XXXXXXXX VRAM7 [R/W] B, H, W XXXXXXXX VRAM11 [R/W] B, H, W XXXXXXXX VRAM15 [R/W] B, H, W XXXXXXXX Block 00000098H 0000009CH 000000A0H LCD Controller Driver 000000A4H 000000A8H 000000A8H to 000000AFH 000000B0H Reserved RDR3/TDR3 [R/W] B, H, W -------BGR03 [R/W] B, H, W XXXXXXXX RDR4/TDR4 [R/W] B, H, W -------BGR04 [R/W] B, H, W XXXXXXXX RDR5/TDR5 [R/W] B, H, W -------BGR05 [R/W] B, H, W XXXXXXXX SCR3 [R/W] B, H, W SMR3 [R/W] B, H, W SSR3 [R/W] B, H, W 00000000 00000000 00001000 ESCR3 [R/W] B, H, W 00000X00 ECCR3 [R/W] B, H, W 000000XX BGR13 [R/W] B, H, W XXXXXXXX LIN-UART0 000000B4H 000000B8H SCR4 [R/W] B, H, W SMR4 [R/W] B, H, W SSR4 [R/W] B, H, W 00000000 00000000 00001000 ESCR4 [R/W] B, H, W 00000X00 ECCR4 [R/W] B, H, W 000000XX BGR14 [R/W] B, H, W XXXXXXXX LIN-UART1 000000BCH 000000C0H SCR5 [R/W] B, H, W SMR5 [R/W] B, H, W SSR5 [R/W] B, H, W 00000000 00000000 00001000 ESCR5 [R/W] B, H, W 00000X00 ECCR5 [R/W] B, H, W 000000XX ⎯ TCDT0 [R/W] H, W 00000000 00000000 TCDT1 [R/W] H, W 00000000 00000000 BGR15 [R/W] B, H, W XXXXXXXX LIN-UART2 000000C4H 000000C8H to 000000D0H 000000D4H Reserved TCCS0 [R/W] B, H, W 00000000 TCCS1 [R/W] B, H, W 00000000 ⎯ 16-bit Free Run Timer0 16-bit Free Run Timer1 000000D8H ⎯ (Continued) 27 MB91245/S Series Address 000000DCH to 000000E0H 000000E4H 000000E8H 000000ECH 000000F0H 000000F4H to 00000104H 00000108H 0000010CH 00000110H 00000114H to 0000012CH 00000130H 00000134H 00000138H 0000013CH to 00000140H 00000144H 00000148H 0000014CH 00000150H Register +0 +1 ⎯ IPCP1 [R] H, W XXXXXXXX XXXXXXXX ⎯ IPCP3 [R] H, W XXXXXXXX XXXXXXXX ⎯ ⎯ OCCP1 [R/W] H, W XXXXXXXX XXXXXXXX ⎯ ⎯ ⎯ PWCSR0 [R/W] B, H, W 0000000X 00000000 ⎯ ⎯ PDIVR0 [R/W] B, H, W -----000 ⎯ ⎯ ⎯ WTHR [R/W] B, H ---XXXXX WTDBL [R/W] B -------0 WTCR [R/W] B, H 00000000 000-00-0 ⎯ PWCR0 [R] H, W 00000000 00000000 OCS01 [R/W] B, H, W 11101100 00001100 OCCP0 [R/W] H, W XXXXXXXX XXXXXXXX IPCP0 [R] H, W XXXXXXXX XXXXXXXX ICS01 [R/W] B, H, W 00000000 IPCP2 [R] H, W XXXXXXXX XXXXXXXX ICS23 [R/W] B, H, W 00000000 +2 +3 Block Reserved 16-bit Input Capture 0, 1 16-bit Input Capture 2, 3 Reserved 16-bit Output Compare Reserved 16-bit PWC Reserved WTBR [R/W] B ---XXXXX XXXXXXXX XXXXXXXX WTMR [R/W] B, H --XXXXXX WTSR [R/W] B --XXXXXX ⎯ Real Time Clock ADERH [R/W] B, H, W 00000000 00000000 ADCS1 [R/W] B, H, W 00000000 ADCS0 [R/W] B, H, W 00000000 ADERL [R/W] B, H, W 00000000 00000000 ADCR1 [R] B, H, W ------XX ADCR0 [R] B, H, W XXXXXXXX A/D Converter 00000154H (Continued) 28 MB91245/S Series Address Register +0 ADCT1 [R/W] B, H, W 00010000 +1 ADCT0 [R/W] B, H, W 00101100 +2 ADSCH [R/W] B, H, W ---00000 +3 ADECH [R/W] B, H, W ---00000 Block 00000158H A/D Converter 0000015CH 00000160H CUCR [R/W] B, H, W -------- ---0--00 CUTR1 [R] B, H, W -------- 00000000 PWC20 [R/W] B, H, W XXXXXXXX ⎯ PWC21 [R/W] B, H, W XXXXXXXX ⎯ PWC22 [R/W] B, H, W XXXXXXXX ⎯ PWC23 [R/W] B, H, W XXXXXXXX ⎯ PWC24 [R/W] B, H, W XXXXXXXX ⎯ PWC25 [R/W] B, H, W XXXXXXXX ⎯ PWC10 [R/W] B, H, W XXXXXXXX PWC0 [R/W] B -0000--0 PWC11 [R/W] B, H, W XXXXXXXX PWC1 [R/W] B -0000--0 PWC12 [R/W] B, H, W XXXXXXXX PWC2 [R/W] B -0000--0 PWC13 [R/W] B, H, W XXXXXXXX PWC3 [R/W] B -0000--0 PWC14 [R/W] B, H, W XXXXXXXX PWC4 [R/W] B -0000--0 PWC15 [R/W] B, H, W XXXXXXXX PWC5 [R/W] B -0000--0 CUTD [R/W] B, H, W 10000000 00000000 CUTR2 [R] B, H, W 00000000 00000000 ⎯ PWS20 [R/W] B, H, W -0000000 ⎯ PWS21 [R/W] B, H, W -0000000 ⎯ PWS22 [R/W] B, H, W -0000000 ⎯ PWS23 [R/W] B, H, W -0000000 ⎯ PWS24 [R/W] B, H, W -0000000 ⎯ PWS25 [R/W] B, H, W -0000000 PWS15 [R/W] B, H, W --000000 PWS14 [R/W] B, H, W --000000 PWS13 [R/W] B, H, W --000000 PWS12 [R/W] B, H, W --000000 PWS11 [R/W] B, H, W --000000 Reserved PWS10 [R/W] B, H, W --000000 Clock Caliblator 00000164H 00000168H 0000016CH 00000170H 00000174H 00000178H Stepping Motor Controller 0000017CH 00000180H 00000184H 00000188H 0000018CH 00000190H (Continued) 29 MB91245/S Series Address 00000194H to 000001A4H 000001A8H 000001ACH 000001B0H Register +0 +1 ⎯ CANPRE [R/W] B, H, W 00000000 +2 +3 Block Reserved Reserved ⎯ ⎯ CAN Prescaler Reserved ⎯ PRLH0 [R/W] B, H, W XXXXXXXX PRLH2 [R/W] B, H, W XXXXXXXX PPGC0 [R/W] B, H, W 0000000X PRLH4 [R/W] B, H, W XXXXXXXX PRLH6 [R/W] B, H, W XXXXXXXX PPGC4 [R/W] B, H, W 0000000X TRG [R/W] B, H, W 00000000 PRLL0 [R/W] B, H, W XXXXXXXX PRLL2 [R/W] B, H, W XXXXXXXX PPGC1 [R/W] B, H, W 0000000X PRLL4 [R/W] B, H, W XXXXXXXX PRLL6 [R/W] B, H, W XXXXXXXX PPGC5 [R/W] B, H, W 0000000X ⎯ ⎯ PRLH1 [R/W] B, H, W XXXXXXXX PRLH3 [R/W] B, H, W XXXXXXXX PPGC2 [R/W] B, H, W 0000000X PRLH5 [R/W] B, H, W XXXXXXXX PRLH7 [R/W] B, H, W XXXXXXXX PPGC6 [R/W] B, H, W 0000000X REVC [R/W] B, H, W 00000000 PRLL1 [R/W] B, H, W XXXXXXXX PRLL3 [R/W] B, H, W XXXXXXXX PPGC3 [R/W] B, H, W 0000000X PRLL5 [R/W] B, H, W XXXXXXXX PRLL7 [R/W] B, H, W XXXXXXXX PPGC7 [R/W] B, H, W 0000000X Reserved PPG0 PPG0 000001B4H 000001B8H 000001BCH 000001C0H 000001C4H 000001C8H 000001CCH to 000001FCH 00000200H 00000204H 00000208H 0000020CH 00000210H 00000214H DMACA0 [R/W] B, H, W *1 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB0 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA1 [R/W] B, H, W *1 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB1 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA2 [R/W] B, H, W *1 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB2 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX DMAC (Continued) 30 MB91245/S Series Address 00000218H 0000021CH 00000220H 00000224H 00000228H to 0000023CH 00000240H 00000244H to 000003ECH 000003F0H 000003F4H 000003F8H 000003FCH 00000400H 00000404H 00000408H 0000040CH 00000410H 00000414H to 0000041CH 00000420H 00000424H Register +0 +1 +2 +3 DMACA3 [R/W] B, H, W *1 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB3 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA4 [R/W] B, H, W *1 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX ⎯ DMACR [R/W] B 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX ⎯ BSD0 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDR0 [R/W] B, H, W DDR1 [R/W] B, H, W DDR2 [R/W] B, H, W DDR3 [R/W] B, H, W 00000000 00000000 11111111 00001111 DDR4 [R/W] B, H, W DDR5 [R/W] B, H, W DDR6 [R/W] B, H, W DDR7 [R/W] B, H, W 00000000 00000000 00000000 ----0000 Block DMAC Reserved Bit Search Module DDR8 [R/W] B, H, W DDR9 [R/W] B, H, W DDRA [R/W] B, H, W DDRB [R/W] B, H, W Port Direction Register 00000000 00000000 ----0000 00000000 DDRC [R/W] B, H, W DDRD [R/W] B, H, W DDRE [R/W] B, H, W DDRF [R/W] B, H, W ----0000 1111---00000000 00000000 DDRG [R/W] B, H, W ----0000 ⎯ PFR0 [R/W] B, H, W PFR1 [R/W] B, H, W PFR2 [R/W] B, H, W PFR3 [R/W] B, H, W 00000000 00000000 00000000 00000000 PFR4 [R/W] B, H, W PFR5 [R/W] B, H, W 00000000 00000000 ⎯ PFR7 [R/W] B, H, W ----0000 ⎯ Reserved Port Function Register (Continued) 31 MB91245/S Series Address 00000428H 0000042CH 00000430H 00000434H to 0000043CH 00000440H 00000444H 00000448H 0000044CH 00000450H 00000454H 00000458H 0000045CH 00000460H 00000464H 00000468H 0000046CH 00000470H to 0000047CH 00000480H 00000484H 00000488H Register +0 ⎯ +1 +2 +3 Block PFRA [R/W] B, H, W PFRB [R/W] B, H, W ----0000 00000000 ⎯ Port Function Register PFRC [R/W] B, H, W PFRD [R/W] B, H, W PFRE [R/W] B, H, W ----0000 00000000 00000000 PFRG [R/W] B, H, W ----0000 ⎯ ⎯ Reserved ICR00 [R/W] B, H, W ICR01 [R/W] B, H, W ICR02 [R/W] B, H, W ICR03 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 ICR04 [R/W] B, H, W ICR05 [R/W] B, H, W ICR06 [R/W] B, H, W ICR07 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 ICR08 [R/W] B, H, W ICR09 [R/W] B, H, W ICR10 [R/W] B, H, W ICR11 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 ICR12 [R/W] B, H, W ICR13 [R/W] B, H, W ICR14 [R/W] B, H, W ICR15 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 ICR16 [R/W] B, H, W ICR17 [R/W] B, H, W ICR18 [R/W] B, H, W ICR19 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 ICR20 [R/W] B, H, W ICR21 [R/W] B, H, W ICR22 [R/W] B, H, W ICR23 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 ICR24 [R/W] B, H, W ICR25 [R/W] B, H, W ICR26 [R/W] B, H, W ICR27 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 ICR28 [R/W] B, H, W ICR29 [R/W] B, H, W ICR30 [R/W] B, H, W ICR31 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 ICR32 [R/W] B, H, W ICR33 [R/W] B, H, W ICR34 [R/W] B, H, W ICR35 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 ICR36 [R/W] B, H, W ICR37 [R/W] B, H, W ICR38 [R/W] B, H, W ICR39 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 ICR40 [R/W] B, H, W ICR41 [R/W] B, H, W ICR42 [R/W] B, H, W ICR43 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 ICR44 [R/W] B, H, W ICR45 [R/W] B, H, W ICR46 [R/W] B, H, W ICR47 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 ⎯ RSRR [R/W] B, H, W STCR [R/W] B, H, W TBCR [R/W] B, H, W 10000000 00110011 00XXXX11 CLKR [W] B, H, W 00000000 ⎯ CTBR [W] B, H, W XXXXXXXX Clock Control Unit Reserved Interrupt Control Unit WPR [R/W] B, H, W DIVR0 [R/W] B, H, W DIVR1 [R/W] B, H, W XXXXXXXX 00000011 00000000 OSCCR [R/W] B X000XXX0 ⎯ (Continued) 32 MB91245/S Series Address 0000048CH 00000490H 00000494H to 000004F8H 000004FCH 00000500H to 0000053CH 00000540H 00000544H 00000548H to 00000550H 00000554H to 00000578H 0000057CH 00000580H to 000005FCH 00000600H Register +0 OSCR [R/W] B 000--001 ⎯ PSCR [W] B XXXXXXXX ⎯ PILR0 [R/W] B, H, W PILR1 [R/W] B, H, W 00000000 00000000 ⎯ PILR5 [R/W] B, H, W 0------⎯ ⎯ ⎯ ⎯ +1 ⎯ +2 +3 Block Clock Control Unit ⎯ Reserved Port Input Level Select Register Reserved Port Input Level Select Register ⎯ Reserved LVRC [R/W] B, H, W 00011000 ⎯ EPFR2 [R/W] B, H, W 00000000 EPFR5 [R/W] B, H, W 00000000 ⎯ ⎯ EPFRG [R/W] B, H, W ----0000 ⎯ EPFRD [R/W] B, H, W 00000000 ⎯ ⎯ ⎯ EPFR3 [R/W] B, H, W 00000000 Reserved Reserved Reserved CPU Detection of operation Reserved ⎯ EPFR4 [R/W] B, H, W 00000000 00000604H 00000608H 0000060CH Extended Port Function Register 00000610H 00000614H to 0000063CH Extended Port Function Register Reserved (Continued) 33 MB91245/S Series Address 00000640H 00000644H 00000648H 0000064CH 00000650H to 0000065CH 00000660H 00000664H 00000668H to 0000067CH 00000680H 00000684H to 000007F8H 000007FCH 00000800H to 00000FFCH 00001000H 00001004H 00001008H 0000100CH 00001010H 00001014H 00001018H Register +0 +1 +2 +3 ASR0 [R/W] B, H, W 00000000 00000000 ASR1 [R/W] B, H, W XXXXXXXX XXXXXXXX ASR2 [R/W] B, H, W XXXXXXXX XXXXXXXX ASR3 [R/W] B, H, W XXXXXXXX XXXXXXXX ⎯ AWR0 [R/W] B, H, W 01110000 01011011 AWR2 [R/W] B, H, W 0XXX0000 XX0X1XXX ⎯ CSER [R/W] B, H, W XXXX0001 ⎯ ⎯ MODR *2 ⎯ DMASA0 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA0 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA2 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA2 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA3 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ⎯ ⎯ AWR1 [R/W] B, H, W XXXX0000 XX0X1XXX AWR3 [R/W] B, H, W 0XXX0000 0X0X1XXX ACR0 [R/W] B, H, W 1111XX00 00000000 ACR1 [R/W] B, H, W XXXXXXXX XXXXXXXX ACR2 [R/W] B, H, W XXXXXXXX XXXXXXXX ACR3 [R/W] B, H, W XXXXXXXX XXXXXXXX Block External Bus Control Unit Reserved External Bus Control Unit Reserved Mode register Reserved DMAC (Continued) 34 MB91245/S Series Address 0000101CH 00001020H 00001024H 00001028H to 00006FFCH 00007000H 00007004H 00007008H to 0000FFFCH 00020000H 00020004H 00020008H 0002000CH 00020010H 00020014H 00020018H 0002001CH 00020020H 00020024H Register +0 +1 +2 +3 DMADA3 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA4 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA4 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ⎯ FLCR [R/W] 01XX1000 FLWC [R/W] 00000011 ⎯ CTRLR0 ERRCNT0 INTR0 BRPER0 IF1CREQ0 IF1MSK20 IF1ARB20 IF1MCTR0 IF1DTA10 IF1DTB10 STATR0 BTR0 TESTR0 ⎯ IF1CMSK0 IF1MSK10 IF1ARB10 ⎯ IF1DTA20 IF1DTB20 ⎯ ⎯ Block DMAC Reserved Flash I/F (Only Mass Production Product) Reserved 00020028H, 0002002CH 00020030H 00020034H 00020038H, 0002003CH 00020040H 00020044H 00020048H 0002004CH 00020050H 00020054H IF2CREQ0 IF2MSK20 IF2ARB20 IF2MCTR0 IF2DTA10 IF2DTB10 ⎯ Reserved (IF1 data A mirror, little endian byte ordering) Reserved (IF1 data B mirror, little endian byte ordering) ⎯ IF2CMSK0 IF2MSK10 IF2ARB10 ⎯ IF2DTA20 IF2DTB20 CAN0 (Continued) 35 MB91245/S Series Address 00020058H, 0002005CH 00020060H 00020064H 00020068H, 0002007CH 00020080H 00020084H 00020088H, 0002008CH 00020090H 00020094H 00020098H, 0002009CH 000200A0H 000200A4H 000200A8H, 000200ACH 000200B0H 000200B4H 000200B8H, 000200FCH 00020100H 00020104H 00020108H 0002010CH 00020110H 00020114H 00020118H 0002011CH 00020120H 00020124H 00020128H, 0002012CH 00020130H 00020134H 00020138H, 0002013CH Register +0 +1 ⎯ Reserved (IF2 data A mirror, little endian byte ordering) Reserved (IF2 data B mirror, little endian byte ordering) ⎯ TREQR20 TREQR10 +2 +3 Block Reserved ( > 32..128 Message buffer) ⎯ NEWDT20 NEWDT10 CAN0 Reserved ( > 32..128 Message buffer) ⎯ INTPEND20 INTPEND10 Reserved ( > 32..128 Message buffer) ⎯ MESVAL20 MESVAL10 Reserved ( > 32..128 Message buffer) ⎯ CTRLR1 ERRCNT1 INTR1 BRPER1 IF1CREQ1 IF1MSK21 IF1ARB21 IF1MCTR1 IF1DTA11 IF1DTB11 ⎯ Reserved (IF1 data A mirror, little endian byte ordering) Reserved (IF1 data B mirror, little endian byte ordering) ⎯ STATR1 BTR1 TESTR1 ⎯ IF1CMSK1 IF1MSK11 IF1ARB11 ⎯ IF1DTA21 IF1DTB21 CAN1 (Continued) 36 MB91245/S Series (Continued) Address 00020140H 00020144H 00020148H 0002014CH 00020150H 00020154H 00020158H, 0002015CH 00020160H 00020164H 00020168H, 0002017CH 00020180H 00020184H 00020188H, 0002018CH 00020190H 00020194H 00020198H, 0002019CH 000201A0H 000201A4H 000201A8H, 000201ACH 000201B0H 000201B4H 000201B8H, 000201FCH 00038000H to 003FFFFCH 0003C000H to 003FFFFCH 0003E000H to 003FFFFCH MESVAL21 INTPND21 NEWDT21 TREQR21 Register +0 IF2CREQ1 IF2MSK21 IF2ARB21 IF2MCTR1 IF2DTA11 IF2DTB11 ⎯ Reserved (IF2 data A mirror, little endian byte ordering) Reserved (IF2 data B mirror, little endian byte ordering) ⎯ TREQR11 +1 +2 IF2CMSK1 IF2MSK11 IF2ARB11 ⎯ IF2DTA21 IF2DTB21 +3 Block Reserved ( > 32..128 Message buffer) ⎯ NEWDT11 CAN1 Reserved ( > 32..128 Message buffer) ⎯ INTPND11 Reserved ( > 32..128 Message buffer) ⎯ MESVAL11 Reserved ( > 32..128 Message buffer) ⎯ ⎯ F-bus RAM 32 Kbytes F-bus RAM 16 Kbytes F-bus RAM 8 Kbytes ⎯ ⎯ *1 : The lower 16 bits (DTC [15 : 0]) of DMACA0 to DMACA4 cannot be accessed in bytes. *2 : This register is set by a mode vector fetch and cannot be accessed by the user. 37 MB91245/S Series Address 000C0000H to 000FFFFCH Register +0 +1 ⎯ +2 +3 Block User ROM 256 Kbytes (Only Mass Production Product) Address 000E0000H to 000FFFFCH Register +0 +1 ⎯ +2 +3 Block User ROM 128 Kbytes (MB91247) 38 MB91245/S Series ■ VECTOR TABLE Interrupt number Interrupt source Reset Mode vector System reserved System reserved System reserved System reserved System reserved Coprocessor absent trap Coprocessor error trap INTE instruction System reserved System reserved Step trace trap NMI request (ICE) Undefined instruction exception NMI instruction External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 Reload timer 0 (Underflow) Reload timer 1 (Underflow) Reload timer 2 (Underflow) UART0 (Reception completed/error) UART0 (Transmission completed) LIN-UART0 (Reception completed/ error, LIN Sync break, bus idle) Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Hexadecimal 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D Interrupt level ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 15 (FH) Fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H TBR default address 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H DMA start source ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 6 7 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 9 10 0 3 1 (Continued) 39 MB91245/S Series Interrupt number Interrupt source LIN-UART0 (Transmission completed) LIN-UART1 (Reception completed/ error, LIN Sync break, bus idle) LIN-UART1 (Transmission completed) LIN-UART2 (Reception completed/ error, LIN Sync break, bus idle) LIN-UART2 (Transmission completed) CAN0 Reception/Transmission completed Node status transition CAN1 Reception/Transmission completed Node status transition System reserved System reserved System reserved PWC (Measurement completed) PWC (Overflow) DMAC transfer completed/error A/D converter Real-time clock Hour/minute/second overflow, corrected System reserved Main oscillation stabilization wait timer Timebase timer overflow PPG0/1 underflow PPG2/3 underflow PPG4/5 underflow PPG6/7 underflow 16-bit free-run timer 0 Overflow & OCU0 Compare match clear Decimal 30 31 32 33 34 Hexadecimal 1E 1F 20 21 22 Interrupt level ICR14 ICR15 ICR16 ICR17 ICR18 Offset TBR default address 000FFF84H 000FFF80H 000FFF7CH 000FFF78H 000FFF74H DMA start source 4 2 5 ⎯ ⎯ ⎯ 384H 380H 37CH 378H 374H 35 23 ICR19 370H 000FFF70H 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 14 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ (Continued) 40 MB91245/S Series (Continued) Interrupt number Interrupt source 16-bit free-run timer 1 Overflow ICU0 (Capture) ICU1 (Capture) ICU2 (Capture) ICU3 (Capture) OCU0 (Match) OCU1 (Match) System reserved System reserved Sound generator setup count completed Delay interrupt source bit System reserved (Used by REALOS) System reserved (Used by REALOS) System reserved Decimal 53 54 55 56 57 58 59 60 61 62 63 64 65 66 to 79 80 to 255 Hexadecimal 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 to 4F 50 to FF Interrupt level ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 ⎯ ⎯ ⎯ Offset 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H 2F4H to 2C0H 2BCH to 000H TBR default address 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H 000FFEF4H to 000FFEC0H 000FFEBCH to 000FFC00H DMA start source ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Used by INT instruction ⎯ ⎯ 41 MB91245/S Series ■ TABLE OF PIN STATUS IN EACH MODE • Single chip mode Pin name INIT X0 X1 X0A X1A MOD0 MOD1 MOD2 P00 P01 P02 P03 P04 Function name INIT X0 X1 X0A X1A MOD0 MOD1 MOD2 P00/SEG24/INT0/D00 P01/SEG25/INT1/D01 P02/SEG26/INT2/D02 P03/SEG27/INT3/D03 P04/SEG28/INT4/D04 Output Hi-Z input enabled Output Hi-Z input enabled P: Immediately preceding status held F: Operation or output held during LCDC output; INT0 to INT5 input enabled when PFR0 register is set to “0” Operation or output held during LCDC output, otherwise output Hi-Z / INT0 to INT5 input enabled when PFR0 register is set to “0” Input enabled Input enabled Input enabled Input enabled Input enabled Initial value INIT = “L” INIT = “H” In sleep state In stop state HIZ = 0 Hi-Z or input enabled HIZ = 1 Hi-Z or input enabled Input enabled Input enabled ”H” output or ”H” output or input enabled input enabled Hi-Z or input enabled Hi-Z or input enabled ”H” output or ”H” output or input enabled input enabled P05 P05/SEG29/INT5/D05 P06 P07 P10 to P17 P20 to P27 P30 to P33 P34 to P37 P06/SEG30/D06 P07/SEG31/ATG/D07 P10 to P17/ SEG16 to SEG23/ D08 to D15 P20 to P27/ SEG00 to SEG07/ A00 to A07 P30 to P33/ SEG08 to SEG11/ A08 to A11 P34 to P37/ SEG12 to SEG15/ A12 to A15 P: Immediately preceding status held F: Normal operation performed “L” output “L” output Output Hi-Z input enabled Output Hi-Z input enabled P: Immediately preceding status held F: Operation or output held during LCDC output; Otherwise Hi-Z Operation or output held during LCDC output; Otherwise output Hi-Z/ Input fixed to “0” (Continued) 42 MB91245/S Series Pin name P40 P41 P42 P43 P44 P45 P46 P47 P50 P51 P52 P53 P54 P55 P56 P57 P60 to P67 Function name P40/SIN0 P41/SOT0 P42/SCK0 P43/SIN3 P44/SOT3 P45/SCK3 P46/SGA/AS P47/SGO/SYSCLK P50/SIN4/CK0/CS0 P51/SOT4/CS1 P52/SCK4/CS2 P53/SIN5/CK1/CS3 P54/SOT5/RD P55/SCK5/WR0 P56/OUT0/WR1 P57/OUT1/RDY P60 to P67/AN0 to AN7 Initial value INIT = “L” INIT = “H” In sleep state In stop state HIZ = 0 HIZ = 1 P: Immediately preceding Output Hi-Z / status held Input fixed to F: “0” Output held or Hi-Z Output Hi-Z input enabled P: Immediately preceding Output Hi-Z status held input F: enabled Normal operation performed P70 P70/RX0/INT6 P: Immediately preceding status held F: Output held, INT6 input enabled P: Immediately preceding status held, F : Hi-Z P: Immediately preceding status held F: Output held, INT7 input enabled Output Hi-Z / INT6 input enabled when PFR7 register is set to “1” P71 P71/TX0 Output Hi-Z / Input fixed to “0” P72 P72/RX1/INT7 Output Hi-Z / INT7 input enabled when PFR7 register is set to “1” (Continued) 43 MB91245/S Series (Continued) Pin name P73 P80 to P87 P90 to P97 PA0 to PA3 PB0 to PB7 PC0 to PC3 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PE0 to PE7 PF0 to PF7 PG0 PG1 PG2 PG3 Function name P73/TX0 P80 to P87/AN16 to AN23 P: Immediately preceding Output Hi-Z status held input F: enabled Normal operation performed Initial value INIT = “L” INIT = “H” In sleep state In stop state HIZ = 0 HIZ = 1 P90 to P97/AN24 to AN31 Output Hi-Z input enabled PA0 to PA3/ PWMxxx to PWMxxx PB0 to PB7/ PWMxxx to PWMxxx PC0 to PC3/ PWMxxx to PWMxxx PD0/TIN0/IN0/PWC0 PD1/TIN1/IN1 PD2/TIN2/IN2 PD3/IN3 PD4/COM0/PPG1 PD5/COM1/PPG3 PD6/COM2/PPG5 PD7/COM3/PPG7 P: Immediately preceding Output Hi-Z / status held Input fixed to F: “0” Output held or Hi-Z Input enabled Input enabled Input enabled Hi-Z “L” output “L” output P: Immediately preceding status held F: Normal operation Output Hi-Z performed Input enabled P: Input fixed to Immediately “0” preceding status held LCDC : Output or hold PPG : Output held PE0 to PE7/ PWMxxx to PWMxxx PF0 to PF7/AN8 to AN15 PG0/ (WOT) /PPG0 PG1/TOT0/PPG2 PG2/TOT1/PPG4 PG3/TOT2/PPG6 Output Hi-Z Input enabled P: Immediately preceding Output Hi-Z / status held Input fixed to F: “0” Output held or Hi-Z 44 MB91245/S Series • External bus mode (8-bit) Pin name INIT X0 X1 X0A X1A MOD0 MOD1 MOD2 P00 P01 P02 P03 P04 P05 P06 Function name INIT X0 X1 X0A X1A MOD0 MOD1 MOD2 P00/SEG24/ INT0 P01/SEG25/ INT1 P02/SEG26/ INT2 P03/SEG27/ INT3 P04/SEG28/ INT4 P05/SEG29/ INT5 P06/SEG30 Output Hi-Z input enabled P: Immediately preceding status held Output F: Hi-Z input Normal operation enabled performed P: Immediately preceding status held F: Operation or output held during LCDC output; INT0 to INT5 input enabled when PFR0 register is set to “0” Operation or output held during LCDC output, otherwise output Hi-Z / INT0 to INT5 input enabled when PFR0 register is set to “0” Input enabled Input enabled Input enabled Input enabled Input enabled Initial value INIT = “L” INIT = “H” In sleep mode In stop mode HIZ = 0 Input enabled Hi-Z or input enabled ”H” output or input enabled Hi-Z or input enabled ”H” output or input enabled HIZ = 1 Input enabled Hi-Z or input enabled ”H” output or input enabled Hi-Z or input enabled ”H” output or input enabled P07 P07/SEG31/ ATG P: Immediately preceding status held F: Operation or output held during LCDC output, otherwise Hi-Z Hi-Z Operation or output held during LCDC output, otherwise output Hi-Z / Input fixed to “0” P10 to P17 P20 to P27 P30 to P33 D08 to D15 Hi-Z Output Hi-Z / Input fixed to “0” A00 to A07 “L” output A08 to A11 (Continued) 45 “H” output F : Address output F : Address output Output Hi-Z / Input fixed to “0” MB91245/S Series Pin name P34 to P37 P40 P41 P42 P43 P44 P45 Function name A12 to A15 P40/SIN0 P41/SOT0 P42/SCK0 P43/SIN3 P44/SOT3 P45/SCK3 Initial value INIT = “L” INIT = “H” Output Hi-Z input enabled In sleep mode In stop mode HIZ = 0 F : Address output HIZ = 1 “H” output F : Address output P: Immediately preceding Output status held Hi-Z input F: enabled Normal operation performed P: Immediately preceding status held, “H” output AS : “H” output, F: Normal operation performed Output Hi-Z input enabled P: Immediately preceding status held, CLK : CLK output, F: Normal operation performed P: Immediately preceding status held F: Output held or Hi-Z P46 P46/SGA/ AS P: Immediately preceding status held, AS : “H” output, F : Output held P47 P47/SGO/ SYSCLK CLK output P: Output Hi-Z / Immediately preceding Input fixed to “0” status held, CLK : “H” or “L” output, F : Output held P50 P51 P52 P53 P54 P55 P50/SIN4/ CK0/CS0 P51/SOT4/ CS1 P52/SCK4/ CS2 P53/SIN5/ CK1/CS3 P54/SOT5/ RD P55/SCK5/ WR0 (Continued) Bus control : “H” output P: Immediately preceding “H” output status held F: Normal operation performed Bus control : “H” output P: Immediately preceding status held F: Output held or Hi-Z 46 MB91245/S Series Pin name Function name Initial value INIT = “L” INIT = “H” In sleep mode In stop mode HIZ = 0 P: Immediately preceding status held F: Output held; “H” output when EPFR is set to “0” P: Immediately preceding status held F: Output held, RDY input P: Immediately preceding Output Hi-Z / status held Input fixed to “0” F: Output held or Hi-Z P: Immediately preceding status held F: Output held, INT6 input enabled Output Hi-Z / INT6 input enabled when PFR7 register is set to “1” HIZ = 1 P56 P56/OUT0 Output Hi-Z input enabled P57/OUT1/ RDY P: Immediately preceding status held F: “H” output Normal operation performed; “H” output when EPFR is set to “0” P: Immediately preceding status held RDY input F: Normal status, RDY input Output Hi-Z / Input fixed to “0” P57 P60 to P67 P60 to P77/ AN0 to AN7 P70 P70/RX0/ INT6 P71 P71/TX0 P: Immediately Output Hi-Z Output Hi-Z preceding status held input input F: enabled enabled Normal operation performed P: Immediately preceding Output Hi-Z / status held, Input fixed to “0” F : Hi-Z P: Immediately preceding status held F: Output held, INT7 input enabled Output Hi-Z / INT7 input enabled when PFR7 register is set to “1” (Continued) P72 P72/RX1/ INT7 47 MB91245/S Series (Continued) Pin name P80 to P87 P90 to P97 PA0 to PA3 PB0 to PB7 PC0 to PC3 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PE0 to PE7 PF0 to PF7 PG0 PG1 PG2 PG3 48 Function name P80 to P87/ AN16 to AN23 P90 to P97/ AN24 to AN31 PA0 to PA3/ PWMxxx to PWMxxx PB0 to PB7/ PWMxxx to PWMxxx PC0 to PC3/ PWMxxx to PWMxxx PD0/TIN0/ IN0/PWC0 PD1/TIN1 PD2/TIN2 PD3/IN3 PD4/COM0/ PPG1 PD5/COM1/ PPG3 PD6/COM2/ PPG5 PD7/COM3/ PPG7 PE0 to PE7/ PWMxxx to PWMxxx PF0 to PF7/ AN8 to AN15 PG0/ (WOT) / Output Hi-Z Output Hi-Z Input Input PPG0 enabled enabled PG1/TOT0/ PPG2 PG2/TOT1/ PPG4 PG3/TOT2/ PPG6 P: Immediately preceding status held F: Normal operation performed Input fixed to “0” P: Immediately preceding status held LCDC : Output or hold PPG : Output held Input enabled Input enabled Input enabled Hi-Z Initial value INIT = “L” INIT = “H” In sleep mode In stop mode HIZ = 0 HIZ = 1 P: Immediately Output Hi-Z Output Hi-Z preceding status input input held enabled enabled F : Normal operation performed P: Immediately preceding status held F: Normal operation performed Output Hi-Z / Input fixed to “0” “L” output “L” output P: Immediately preceding status held F: Output held or Hi-Z Output Hi-Z / Input fixed to “0” MB91245/S Series • External bus mode (16-bit) Initial value Pin Function name name INIT = “L” INIT = “H” INIT X0 X1 X0A X1A MOD0 MOD1 MOD2 P00 P01 P02 P03 P04 P05 P06 P07 P10 to P17 P20 to P27 P30 to P33 P34 to P37 P40 P41 P42 P43 P44 P45 INIT X0 X1 X0A X1A MOD0 MOD1 MOD2 D00 D01 D02 D03 D04 D05 D06 D07 D08 to D15 Output Hi-Z input enabled Output Hi-Z input enabled Hi-Z Hi-Z Input enabled Input enabled Input enabled Input enabled Input enabled In sleep mode In stop mode HIZ = 0 Input enabled Hi-Z or input enabled ”H” output or input enabled Hi-Z or input enabled ”H” output or input enabled HIZ = 1 Input enabled Hi-Z or input enabled ”H” output or input enabled Hi-Z or input enabled ”H” output or input enabled A00 to A07 “L” output A08 to A11 “H” output F : Address output F : Address output Output Hi-Z Input fixed to “0” A12 to A15 P40/SIN0 P41/SOT0 P42/SCK0 P43/SIN3 P44/SOT3 P45/SCK3 Output Hi-Z input enabled Output Hi-Z input enabled P: Immediately preceding status held F: Normal operation performed P: Immediately preceding status held F: Output held or Hi-Z (Continued) 49 MB91245/S Series Pin name Function name Initial value INIT = “L” INIT = “H” In sleep mode In stop mode HIZ = 0 P: Immediately preceding status held, AS : “H” output, F : Output held HIZ = 1 P46 P46/SGA/AS P: Immediately preceding status held, “H” output AS : “H” output, F: Normal operation performed P: Immediately preceding status held, CLK : CLK output, F: Normal operation performed P47 P47/SGO/ SYSCLK Output Hi-Z input enabled CLK output P: Immediately preceding status held, CLK : “H” or “L” output, F : Output held Output Hi-Z Input fixed to “0” P50 P51 P52 P53 P54 P55 P50/SIN4/ CK0/CS0 P51/SOT4/ CS1 P52/SCK4/ CS2 P53/SIN5/ CK1/CS3 P54/SOT5/ RD P55/SCK5/ WR0 P56/OUT0/ WR1 Output Hi-Z input enabled Bus control : “H” output P: Immediately preceding “H” output status held F: Normal operation performed Bus control : “H” output P: Immediately preceding “H” output status held F: Normal operation performed P: Immediately preceding status held RDY input F: Normal status, RDY input P: Immediately Output preceding status held Hi-Z input F: enabled Normal operation performed Bus control : “H” output P: Immediately preceding status held F: Output held or Hi-Z P56 Bus control : “H” output P: Immediately preceding status held F: Output held or Hi-Z P: Immediately preceding status held F : Output held, RDY input Output Hi-Z / Input fixed to “0” P57 P57/OUT1/ RDY P60 to P67 P60 to P77/ AN0 to AN7 Output Hi-Z input enabled P: Immediately preceding status held Output Hi-Z / F: Input fixed to “0” Output held or Hi-Z (Continued) 50 MB91245/S Series Pin name Function name Initial value INIT = “L” INIT = “H” In sleep mode In stop mode HIZ = 0 P: Immediately preceding status held F: Output held, INT6 input enabled HIZ = 1 Output Hi-Z / INT6 input enabled when PFR7 register is set to “1” P70 P70/RX0/ INT6 P: Immediately Output Hi-Z Output Hi-Z preceding status held input input F: enabled enabled Normal operation performed P71 P71/TX0 P: Immediately preceding Output Hi-Z / status held, Input fixed to “0” F : Hi-Z P: Immediately preceding status held F: Output held, INT7 input enabled Output Hi-Z / INT7 input enabled when PFR7 register is set to “1” P72 P72/RX1/ INT7 P80 to P87 P90 to P97 PA0 to PA3 PB0 to PB7 P80 to P87/ AN16 to AN23 P90 to P97/ AN24 to AN31 P: Immediately preceding status held F: Normal operation performed P: Immediately PA0 to PA3/ Output Hi-Z Output Hi-Z preceding status held PWMxxx to input input F: PWMxxx enabled enabled Normal operation PB0 to PB7/ performed PWMxxx to PWMxxx Output Hi-Z/ Input fixed to “0” PC0 PC0 to PC3/ to PWMxxx to PC3 PWMxxx PD0 PD1 PD2 PD3 PD0/TIN0/ IN0/PWC0 PD1/TIN1 PD2/TIN2 PD3/IN3 (Continued) Input enabled Input enabled Input enabled Hi-Z Input fixed to “0” 51 MB91245/S Series (Continued) Pin name PD4 PD5 PD6 PD7 PE0 to PE7 PF0 to PF7 PG0 PG1 PG2 PG3 Function name PD4/COM0/ PPG1 PD5/COM1/ PPG3 PD6/COM2/ PPG5 PD7/COM3/ PPG7 PE0 to PE7/ PWMxxx to PWMxxx PF0 to PF7/ AN8 to AN15 PG0/ (WOT) / Output Hi-Z Output Hi-Z Input Input PPG0 enabled enabled PG1/TOT0/ PPG2 PG2/TOT1/ PPG4 PG3/TOT2/ PPG6 P: Immediately preceding status held F: Normal operation performed Initial value INIT = “L” INIT = “H” In sleep mode In stop mode HIZ = 0 HIZ = 1 “L” output “L” output P: Immediately preceding status held LCDC : Output or hold PPG : Output held Input fixed to “0” P: Immediately preceding status held F: Output held or Hi-Z Output Hi-Z / Input fixed to “0” 52 MB91245/S Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol VCC Power supply voltage*1 AVCC VAVRH DVCC Input voltage*1 Output voltage*1 “L” level maximum output current*3 “L” level average output current*4 “L” level total maximum output current “L” level total average output current “H” level maximum output current “H” level average output current “H” level total maximum output current “H” level total average output current Power consumption VI VO IOL1 IOL2 IOLAV1 IOLAV2 ΣIOL1 ΣIOL2 ΣIOLAV1 ΣIOLAV2 I I OH1 3 Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ −40 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VCC + 0.3 VCC + 0.3 15 40 4 30 120 330 50 240 −15 −40 −4 −30 −120 −330 −50 −240 660 +105 +105 +85 +150 2 Unit V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mW °C °C °C °C mA *5 *6 *5 *6 *5 *6 *5 *6 *5 *6 *5 *6 *5 *6 *5 *6 AVCC = VCC*2 AVCC ≥ VAVRH DVCC = VCC*2 Remarks * * OH2 3 IOHAV1*4 IOHAV2*4 ΣIOH1 ΣIOH2 ΣIOHAV1*7 ΣIOHAV2*7 PD MASK ROM product (in single chip operation) Flash memory product (in single chip operation) MASK ROM/Flash memory product (in external bus operation) Operating temperature TA −40 −40 Storage temperature +B input standard (Maximum clamp current) +B input standard (Total maximum clamp current) Tstg IIHH ΣIIHH −55 ⎯ ⎯ Exclusive of dedicated input pins*8 20 mA (Continued) 53 MB91245/S Series (Continued) *1 : The parameter is base on VSS = AVSS = DVSS = 0.0 V. *2 : Caution must be taken that AVCC and DVCC do not exceed VCC upon power-on and under other circumstances. *3 : The maximum output current defines the peak current value of each of the corresponding pins. *4 : The average output current defines the average value of the current (100 ms) which passes through each of the corresponding pins. The average value represents a value calculated by multiplying the operating current by the operating rate. *5 : Output other than PA0 to PA3 pins, PB0 to PB7 pins, PC0 to PC3 pins, and PE0 to PE7 pins *6 : (PA0 to PA3 pins, PE0 to PE7 pins) + (PB0 to PB7 pins, PC0 to PC3 pins) The SMC pins are divided into two groups (12 pins each) and the value is calculated as the total current per group. *7 : The total average output current defines the average value of the current (100 ms) which passes through all the corresponding pins. The average value represents a value calculated by multiplying the operating current by the operating rate. *8 : +B input standard defines the current value for each of the corresponding pins. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 54 MB91245/S Series 2. Recommended Operating Conditions (VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Rating Min 4.5 Power supply voltage VCC AVCC DVCC 3.5 Max 5.5 5.5 Unit V V Remarks Recommended guaranteed operating range (MB91F248, MB91248) Guaranteed operating range*1 (MB91F248, MB91248) Guaranteed operating range for holding stop operation status*2 (MB91F248, MB91248) Use a ceramic capacitor or a capacitor with similar frequency characteristics. MASK ROM product (in single chip operation) Flash memory product (in single chip operation) MASK ROM/Flash memory product (in external bus operation) 2.0 Smoothing capacitor*3 5.5 V µF CS −40 1 +105 +105 +85 °C °C °C Operating temperature TA −40 −40 *1 : Exclusive of A/D operation *2 : Internal voltage held in RAM : 1.8 V (Min) /3.6 V (Max) *3 : For how to connect the smoothing capacitor CS, refer to the figure below. • C Pin Connection Diagram C CS VSS DVSS AVSS < + B input (12 V to 16 V) conditions> • Do not connect +B potential directly to a microcontroller pin. • Always connect a resistor between the microcontroller pin and +B signal to limit the current. lIHH = 2 mA per pin (Max.) [In the steady state and transient state between power-on and power-off, etc.] It can be connected to any general-purpose input port except the output pin for LCDC. • The protection diode in the microcontroller turns the potential upon +B input between the limiting resistor and microcontroller pin into “VCC + protection diode ON voltage”. Configure the circuit so that these are not interfered and the potential is not exceeded. 55 MB91245/S Series Recommended example circuit MB91245/S series Protection diode lIHH +B Input (12 V to 16 V) Current limiting resistor WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 56 MB91245/S Series 3. DC Specifications (TA : Recommended operating conditions; Vcc = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol VIHS “H” level input voltage VIH VIHM VIHX VILS “L” level input voltage VIL VILM VILX Pin name ⎯ P00 to P07, P10 to P17, P57 ⎯ X0, X1, X0A, X1A, INIT ⎯ P00-P07, P10-P17, P57 ⎯ X0, X1, X0A, X1A, INIT Condition ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Value Min 0.8 VCC 0.7 VCC VCC − 0.3 0.8 VCC VSS − 0.3 VSS − 0.3 VSS − 0.3 ⎯ ⎯ ⎯ ⎯ ⎯ Typ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 55 55 100 290 Max VCC + 0.3 VCC + 0.3 VCC + 0.3 ⎯ 0.5 VCC 0.3 VCC Vss + 0.3 0.2 VCC 85 85 150 450 Unit V V V V V V V V mA Flash memory product Automotive level input pins*1 CMOS hysteresis input pins*2 MOD pins*3 Remarks Automotive level input pins*1 CMOS hysteresis input pins*2 MOD pins*3 ICC Operating frequency : FCP = 32 MHz in main mode Operating frequency : FCP = 32 kHz, TA = +25 °C in sub mode TA = +25 °C, Vcc = 5V in stop mode (oscillation stopped) TA = +25 °C, Vcc = 5V in stop mode (RTC in use) All input pins Other than Vcc, VSS, DVcc, DVSS, AVcc, AVSS, PA0 to PA3, PB0 to PB7, PC0 to PC3, PE0 to PE7 PA0 to PA3, PB0 to PB7, PC0 to PC3, PE0 to PE7 INIT VCC = DVCC = AVCC = 5.5 V VSS < VI < VCC mA MASK ROM product mA In Flash-Write mode µA Power supply current*4 ICCL VCC ICCH ⎯ ⎯ −5 95 150 µA µA µA At 4 MHz ICTS Input leak current 390 ⎯ 500 +5 IIL Input capacity 1 CIN1 ⎯ ⎯ 5 15 pF Input capacity 2 Pull-up resistance CIN2 ⎯ ⎯ 15 45 pF RUP ⎯ 25 50 100 kΩ (Continued) 57 MB91245/S Series (Continued) (TA : Recommended operating conditions; Vcc = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V) Symbol Pin name Condition ⎯ Value Min 25 Typ 50 Max 100 Unit kΩ Remarks MASK ROM products only Parameter Pull-down resistance RDOWN MOD1, MOD2 Other than PA0 to PA3, PB0 to PB7, PC0 to PC3, PE0 to PE7 PA0 to PA3, PB0 to PB7, PC0 to PC3, PE0 to PE7 Other than PA0 to PA3, PB0 to PB7, PC0 to PC3, PE0 to PE7 PA0 to PA3, PB0 to PB7, PC0 to PC3, PE0 to PE7 Output “H” voltage 1 VOH1 Vcc = 4.5 V IOH = −4.0 mA VCC − 0.5 ⎯ ⎯ V Output “H” voltage 2 VOH2 Vcc = 4.5 V IOH = −30.0 mA VCC − 0.5 ⎯ ⎯ V Output “L” voltage 1 VOL1 Vcc = 4.5 V IOL = 4.0 mA ⎯ ⎯ 0.4 V Output “L” voltage 2 VOL2 Vcc = 4.5 V IOL = 30.0 mA Vcc = 4.5 V IOH = 30.0 mA Maximum deviation of VOH2 Vcc = 4.5 V IOL = 30.0 mA Maximum deviation of VOL2 ⎯ ⎯ ⎯ ⎯ 0.55 V PWM1Pn, High current output PWM1Mn, Drive capacity ∆VOH2 PWM2Pn, Phase-to-phase PWM2Mn, deviation 1 n = 0 to 5 High current output Drive capacity Phase-to-phase deviation 2 COM0 to COM3 Output impedance SEG00 to SEG31 Output impedance LCDC leak current PWM1Pn, PWM1Mn, PWM2Pn, PWM2Mn, n = 0 to 5 COMm (m = 0 to 3) SEGn (n = 00 to 31) COMm (m = 0 to 3) , SEGn, (n = 00 to 31) 0 ⎯ 90 mV *5 ∆VOL2 0 ⎯ 90 mV *5 RVCOM RVSEG ⎯ ⎯ ⎯ 15 2.5 30 kΩ kΩ ILCDC TA = +25 °C −0.5 ⎯ +0.5 µA *1 : All input pins except X0, X1, X0A, X1A, MOD0, MOD1, MOD2 and INIT pins *2 : Can be selected by the input level select register (PILR). *3 : MOD0, MOD1 and MOD2 *4 : They represent current values used when supplying power to the external clock from pin X1. *5 : Defined by the maximum deviation of VOH2/VOL2 of each pin, when PWM1P0, PWM1M0, PWM2P0 and PWM2M0 in ch.0 are simultaneously turned on. The same applies to other channels. 58 MB91245/S Series 4. Flash Memory Write/Erase Characteristics Parameter Sector erase time Chip erase time Halfword write time Chip write time Erase/write cycle Flash memory data retain time Condition TA = +25 °C, Vcc = 5.0 V TA = +25 °C, Vcc = 5.0 V TA = +25 °C, Vcc = 5.0 V TA = +25 °C, Vcc = 5.0 V ⎯ TA = +85 °C (average) Value Min ⎯ ⎯ ⎯ ⎯ 10000 10 Typ 1 5 16 2.1 ⎯ ⎯ Max 15 ⎯ 3600 ⎯ ⎯ ⎯ Unit s s µs s cycle year * Remarks Exclusive of internal write time prior to erase Exclusive of internal write time prior to erase Exclusive of overhead time at system level Exclusive of overhead time at system level * : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 85 °C) . 59 MB91245/S Series 5. AC Specifications (1) Clock timing (TA : Recommended operating conditions; Vcc = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V) Parameter Frequency of source oscillation clock Source oscillation clock Cycle time Input clock pulse width Symbol FC Fca tCYL PWH , PWL fCPB Frequency of internal operating clock fCPT fCPP tCPB Internal operating clock cycle tCPT tCPP Input clock Rise/fall time Frequency of internal base clock Internal base clock Cycle time tcr tcf FCP X0 ⎯ ⎯ ⎯ ⎯ 32 ⎯ ⎯ ⎯ ⎯ Pin name X0, X1 X0A, X1A X0, X1 ⎯ Condition Value Min ⎯ ⎯ ⎯ 100 0.0312 0.0312 0.0312 31.25 62.5 31.25 ⎯ Typ 4 32 250 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Max ⎯ ⎯ ⎯ ⎯ 32 16 32 32000 32000 32000 5 Unit MHz kHz ns The duty ratio normally ranges from 40% to 60%. External bus based (CLKT) Peripheral based (CLKP) CPU based (CLKB) External bus based (CLKT) Peripheral based (CLKP) When external clock is used Remarks X0 ns MHz CPU based (CLKB) MHz MHz ns ns ns ns When main oscillation MHz is at 4 MHz and PLL multiplied by 8 is used ns When main oscillation is at 4 MHz and PLL multiplied by 8 is used tCP ⎯ ⎯ 31.25 ⎯ ⎯ • X0/X1 Clock Timing tCYL 0.8 VCC 0.2 VCC X0 PWH tcf PWL tcr 60 MB91245/S Series • Operations Oscillation should be performed as described below : [Source oscillation] : X0/X1 : 4 MHz, PLL : multiplied by 8, Internal frequency : 32 MHz : X0A/X1A : 32 kHz, PLL : no multiplied, Internal frequency : 32 kHz Note that the PLL oscillation stabilization wait time should be set to 500 µs or more. Example oscillation circuit X0 X1 R C1 C2 AC specifications are defined by the following measurement standard voltage values : • Input signal waveform Hysteresis input pin 0.8 VCC 0.5 VCC • Output signal waveform Output pin 2.4 V 0.8 V 61 MB91245/S Series (2) Reset input (TA : Recommended operating conditions; Vcc = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Pin name Condition Value Min 500 ⎯ 10 tCP Oscillation time of oscillator* + 10 tcp + 12 µs Max ⎯ ⎯ ⎯ Unit ns ns Remarks Flash memory product MASK ROM product In stop mode INIT input time tINTL INIT ms * : The oscillation time of the oscillator refers to the time when the amplitude has reached 90%. The oscillation time of the crystal oscillator ranges from several ms to tens of ms. The oscillation time of the ceramic oscillator ranges from several hundreds to several ms, while that of the external clock is 0 ms. tINTL INIT 0.2 VCC 0.2 VCC • In stop mode tINTL INIT 0.2 VCC 0.2 VCC X0 90% of amplitude Internal operation clock Oscillation time of oscillator Internal reset 10 tcp + 12 µs Oscillation stabilization wait time Instruction executed 62 MB91245/S Series [External reset input specifications (INIT) and internal reset signal cancellation timing] • When an external reset input is generated, a maximum of 256 tcp is designed to be spent until it reaches the internal reset signal to transmit all reset signals to the internal logic. (Max 8 µs at 32 MHz) • The following chart shows how to set the timing for instruction execution start (start of application operation) after external reset input. Time from external reset input to instruction start = Max 256 tcp + 61 tcp • Timing Chart INIT Min 10 tcp Internal reset input timing 61 tcp Max 256 tcp Internal reset Internal reset cancellation timing [Pin state in external bus mode] In the external bus mode, it is not guaranteed to hold the RAM value upon external reset (INIT = “0”) input. In the external bus mode, the value of the internal bus is output to each pin during the time from the internal reset input to its cancellation as well as the RAM value is not guaranteed to be held. • Timing Chart (Pin State for External Bus Mode : 1) INIT Min 10 tcp Internal reset Max 256 tcp 61 tcp Pin state of external bus Hi-Z Value immediately before reset Initial value at reset 63 MB91245/S Series It can be avoided by the following external reset input to continue Hi-Z. • Timing Chart (Pin State for External Bus Mode : 2) INIT 256 tcp Internal reset Max 256 tcp 61 tcp Pin state of external bus Hi-Z Initial value at reset 64 MB91245/S Series (3) Power-on Conditions (TA : Recommended operating conditions; VSS = 0.0 V) Parameter Power supply rising time Power supply start voltage Power supply peak voltage Power supply cut-off time Symbol Pin name tR VOFF Vcc VON tOFF ⎯ 3.5 50 ⎯ ⎯ V ms Due to repetitive operation Condition Value Min 0.05 ⎯ Max 30 0.2 Unit ms V Remarks tR Vcc 0.2 V 4.5 V 0.2 V tOFF 0.2 V Power supply drop time, power supply voltages and external reset input to retain RAM data in MB91245/S Satisfy the following reset input standard to retain the RAM data used in the single chip mode. Vcc (V) Voltage drop time External reset input standard (INIT) 4.0 V → 3.5 V dropped Min 256 tcp Min 256 tcp Vcc 4V 3.5 V 3.5 V 4V INIT 256 tcp To retain RAM data, enter 256 tcp of INIT or more before dropping VCC to 3.5 V or lower. 65 MB91245/S Series (4) Clock Output Timing (VCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V) Parameter Cycle time SYSCLK↑→SYSCLK↓ SYSCLK↓→SYSCLK↑ Symbol tCYC tCHCL tCLCH Pin name SYSCLK SYSCLK SYSCLK ⎯ Condition Value Min tCPT Max ⎯ Unit ns ns ns Remarks *1 *2 *3 tCYC / 2 − 10 tCYC / 2 + 10 tCYC / 2 − 10 tCYC / 2 + 10 tCYC tCHCL tCLCH VOH VOH VOL SYSCLK *1 : tCYC is the frequency of one clock cycle including the gear cycle. *2 : The ratings are based on conditions with “gear cycle × 1”. When the gear cycle is set to 1/2, 1/4 or 1/8, perform calculation by substituting 1/2, 1/4 or 1/8 for “n” in the following formula, respectively. ( 1 / 2 × 1 / n ) × tCYC − 10 *3 : This is the value for the gear cycle × 1. 66 MB91245/S Series (5) Normal Bus Access : Read/Write Operation (VCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V, TA = 0 °C to + 70 °C) Parameter Symbol tCSLCH CS0 to CS3 setup tCSDLCH CS0 to CS3 hold tCHCSH tASCH Address setup tASWL tASRL tCHAX Address hold tWHAX tRHAX Valid address → valid data input time WR0, WR1 delay time WR0, WR1 delay time WR0, WR1 minimum pulse width WR0, WR1↑→ data hold time RD delay time RD delay time RD ↓ → valid data input time Data setup → RD ↑ time RD ↑ → data hold time RD minimum pulse width AS setup AS hold tAVDV tCHWL tCHWH tWLWH tWHDX tCHRL tCHRH tRLDV tDSRH tRHDX tRLRH tASLCH tCHASH RD SYSCLK AS RD D00 to D15 SYSCLK A00 to A15 WR0, WR1 A00 to A15 RD A00 to A15 SYSCLK A00 to A15 WR0, WR1 A00 to A15 RD A00 to A15 A00 to A15 D00 to D15 SYSCLK WR0, WR1 WR0, WR1 D00 to D15 SYSCLK RD ⎯ SYSCLK CS0 to CS3 Pin name Condition AWRxL : W02 = 0 AWRxL : W02 = 1 Value Min 3 −8 3 3 3 3 3 3 3 ⎯ ⎯ ⎯ tCYC − 5 3 ⎯ ⎯ ⎯ 20 0 tCYC − 5 3 3 Max ⎯ ⎯ tCYC / 2 + 25 ⎯ ⎯ ⎯ tCYC / 2 + 25 ⎯ ⎯ 3 / 2 × tCYC + 45 8 8 ⎯ ⎯ 6 6 tCYC − 30 ⎯ ⎯ ⎯ ⎯ tCYC / 2 + 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *1 *1, *2 Remarks *1 : If the bus is expanded by automatic wait insertion or RDY input, add time (tCYC × the number of expanded cycles) to the rated value. *2 : The ratings are based on conditions with “gear cycle × 1”. If the gear cycle is set to 1/2 to 1/16, perform calculation by substituting the corresponding value for “n” in the following formula. Formula : 3/ (2n) × tCYC + 45 67 MB91245/S Series tCYC VOH VOH VOH VOH SYSCLK tASLCH tCHASH VOH AS VOL tCSLCH tCSDLCH tCHCSH VOH CS0 to CS3 VOL tASCH tCHAX VOH VOL A00 to A15 VOH VOL tCHRL tRLRH tCHRH RD tASRL VOL tRHAX tRLDV tAVDV VOH VOH VOL tDSRH tRHDX D00 to D15 VOL tCHWL tWLWH VOL tASWL tCHWH VOH tWHAX tWHDX WR0, WR1 D00 to D15 VOH VOL VOH VOL 68 MB91245/S Series (6) Ready Input Timing (VCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V) Parameter RDY setup time →SYSCLK↓ SYSCLK↑→ RDY hold time Symbol tRDYS tRDYH Pin name SYSCLK RDY SYSCLK RDY Condition Value Min 10 ⎯ 0 ⎯ ns Max ⎯ Unit ns Remarks tcyc VoH VoH VoL SYSCLK VoL tRDYS tRDYH tRDYS tRDYH With RDY wait VoH VoL VoL VoH Without RDY wait VoH VoL VoH VoL 69 MB91245/S Series (7) UART Timing (TA : Recommended operating conditions; VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V) Parameter Serial clock Cycle time SCK↓→ SOT delay time Valid SIN→ SCK↑ SCK↑→ Valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK↓→ SOT delay time Valid SIN→ SCK↑ SCK↑→ Valid SIN hold time Symbol tSCYC tSLOV tIVSH SCK0, SIN0 tSHIX tSHSL SCK0 tSLSH tSLOV tIVSH SCK0, SIN0 tSHIX 60 ⎯ ns SCK0, SOT0 ⎯ 4 tCP ⎯ 60 ⎯ 150 ⎯ ns ns ns For external shift clock mode output pin, CL = 80 pF+1⋅TTL 60 4 tCP ⎯ ⎯ ns ns Pin name SCK0 SCK0, SOT0 ⎯ 100 ⎯ ns Condition Value Min 8 tCP −80 Max ⎯ +80 Unit ns ns For internal shift clock mode output pin, CL = 80 pF+1⋅TTL Remarks Notes : • The above ratings are the values for clock synchronous mode. • CL is a load capacitance connected to pins during testing. 70 MB91245/S Series • Internal Shift Clock Mode tSCYC SCK 0.8 V tSLOV 2.4 V 0.8 V SOT 2.4 V 0.8 V tIVSH 0.8 Vcc tSHIX 0.8 Vcc 0.5 Vcc SIN 0.5 Vcc • External Shift clock Mode tSLSH tSHSL 0.8 Vcc 0.8 Vcc SCK 0.6 Vcc tSLOV 2.4 V 0.8 V tIVSH 0.8 Vcc 0.6 Vcc SOT tSHIX 0.8 Vcc 0.5 Vcc SIN 0.5 Vcc 71 MB91245/S Series (8) Timer Input Timing (TA : Recommended operating conditions; VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V) Parameter Input pulse width Symbol tTIWH tTIWL Pin name TIN0 to TIN2, PWC IN0 to IN3 Condition ⎯ Value Min 4 tCP Max ⎯ Unit ns Remarks • Timer Input Timing tTIWH tTIWL TINx INx 0.8 Vcc 0.8 Vcc 0.5 Vcc 0.5 Vcc (9) External Interrupt Timing (TA : Recommended operating conditions; VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V) Parameter Input pulse width Symbol tINTH, INTL Pin name INT0 to INT7 Condition ⎯ Value Min 3 tCP Max ⎯ Unit ns Remarks • External interrupt input timing tINTH 0.8 Vcc 0.8 Vcc 0.5 Vcc 0.5 Vcc tINTL INTx Note : For INTx level detection time required to recover from the stop mode, add the stabilization time for the internal step-down circuit (12 µs). 72 MB91245/S Series 6. A/D Converter Electrical Characteristics (1) Electrical Characteristics (TA : Recommended operating conditions; VCC = AVCC = 5.0 V ±10%, VSS = AVSS = 0.0 V) Parameter Resolution Total error Non-linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Sampling time Compare time A/D conversion time Analog port input current Analog input voltage Standard voltage Power supply current*4 Standard voltage supply current Variation between channels *1 : *2 : *3 : *4 : *5 : Symbol ⎯ ⎯ ⎯ ⎯ VOT VFST tSMP tCMP tCNV IAIN VAIN AVR + IA IAH IR IRH ⎯ Pin name ⎯ ⎯ ⎯ ⎯ AN0 to AN31 AN0 to AN31 ⎯ ⎯ ⎯ AN0 to AN31 AN0 to AN31 AVRH AVCC AVRH AVRH AN0 to AN31 Value Min ⎯ ⎯ ⎯ ⎯ AVSS − 1.5 LSB AVRH − 3.5 LSB 1.375 1.375 2.750 ⎯ 0 4.0 ⎯ ⎯ ⎯ ⎯ ⎯ Typ ⎯ ⎯ ⎯ ⎯ AVSS + 0.5 LSB AVRH − 1.5 LSB ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2.4 ⎯ 500 ⎯ ⎯ Max 10 ±3.0 ±2.5 ±1.9 AVSS + 2.5 LSB AVRH + 0.5 LSB ⎯ ⎯ ⎯ 10 AVRH AVcc 4.7 5 900 5 5 Unit bit LSB LSB LSB V V µs µs µs µA V V mA µA µA µA LSB *5 VAVRH = 5.0 V *5 Remarks 1 LSB = (AVRH − AVSS) / 1024 *1 *2 *3 VAVSS ≤ VAIN ≤ VAVCC When FCP is 32 MHz : tSMP = (Rext + Rin) × Cin × 7 = ST × CLKP cycle = 2 channels × 31.25 ns = 1.375 µs When FCP is 32 MHz : tCMP = CKIN × 11 = CT × CLKP cycle × 11 = 4 h × 31.25 ns × 11 = 1.375 µs This represents the conversion time per channel when tSMP and tCMP are selected while FCP is 32 MHz. The current values are targeted temporary ratings. This defines the power supply current when the A/D converter is not in operation and the CPU is stopped (at “Vcc = AVcc = AVRH = 5.0 V”) Notes : • As AVRH becomes smaller, the error becomes greater. • Use the output impedance rS of the external circuit for analog input under the following conditions : Output impedance rS of the external circuit = 5 kΩ (Max) • If the output impedance of the external circuit is too high, the sampling time of the analog voltage may not be sufficient. When placing a DC blocking capacitor between the external circuit and input pin, set the capacitance to the value calculated by multiplying CSH by several thousands as a guideline in order to minimize the impact from dividing voltage capacitance with CSH. 73 MB91245/S Series • Analog Input Equivalent Circuit Circuit in microcontroller Input pin AN0 rs RSH CSH Comparator Input pin AN7 Vs S/H circuit External circuit Analog channel selector rS = 5 kΩ or less RSH = approx. 2.5 kΩ CSH = approx. 10 pF Note : These element parameters should be regarded as tentative values used only for design purposes. They are not guaranteed values. 74 MB91245/S Series (2) Term Definitions • Resolution Level of analog variation that can be distinguished by the A/D converter. When the number of bits is 10, the analog voltage can be resolved into 210 = 1024. • Total error Difference between actual and theoretical values, which is a total value derived from an offset error, gain error, non-linearity error and noise. • Linearity error Deviation between the value along a straight line connecting the zero transition point (“00 0000 0000”←→ “00 0000 0001”) of a device and the full-scale transition point (“11 1111 1110”←→“11 1111 1111”) compared with the actual conversion values obtained. • Differential linearity error Deviation of input voltage, which is required for changing output code by1 LSB, from an ideal value. 75 MB91245/S Series • 10-bit A/D Converter- Conversion Characteristics 11 1111 1111B 11 1111 1110B 11 1111 1101B 11 1111 1100B . . . . . . . . . . . . . 00 0000 0011B 00 0000 0010B 00 0000 0001B 00 0000 0000B 1 LSB x N + VOT Digital output Linearity error VOT VNT V(N + 1)T VFST Analog input 1 LSB = VFST− VOT 1022 VNT− (1 LSB × N + VOT) 1 LSB V (N + 1) T − VNT −1 1 LSB Linearity error = [LSB] Differential linearity error = [LSB] N VOT VFST VNT : A/D converter digital output value. : Voltage at which digital output transits from 000H to 001H. : Voltage at which digital output transits from 3FEH to 3FFH. : A voltage at which digital output transits from (N − 1) to N. 76 MB91245/S Series ■ EXAMPLE CHARACTERISTICS (1) Power supply current (at main RUN) ICC - VCC 100 90 80 70 ICCL (µA) ICC (mA) 60 50 40 30 20 10 0 3.5 4 4.5 VCC (V) 5 5.5 (2) Power supply current (at sub RUN) ICCL - VCC 500 450 400 350 300 250 200 150 100 50 0 3.5 4 4.5 VCC (V) 5 5.5 TA = + 25 °C TA = + 25 °C (3) Power supply current (at stop : when oscillation stops) ICCH - VCC 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 3.5 (4) Power supply current (at stop : when using RTC 4 MHz) ICTS - VCC 500 450 400 350 ICTS (µA) 300 250 200 150 100 50 TA = + 25 °C TA = + 25 °C ICCH (µA) 4 4.5 VCC (V) 5 5.5 0 3.5 4 4.5 VCC (V) 5 5.5 (Continued) 77 MB91245/S Series (5) A/D power supply current IA - VCC VCC = AVCC = AVRH TA = + 25 °C (6) A/D reference voltage supply current IR - VCC VCC = AVCC = AVRH TA = + 25 °C 5 4.5 4 3.5 IA (mA) 3 2.5 2 1.5 1 0.5 0 3.5 4 1000 900 800 700 600 IR (µA) 500 400 300 200 100 4.5 VCC (V) 5 5.5 0 3.5 4 4.5 VCC (V) 5 5.5 (7) “H” level input voltage/“L” level input voltage (8) “H” level input voltage/“L” level input voltage (Automotive input) (CMOS hysteresis input) VIN - VCC 5 4.5 4 3.5 VIN (V) 2.5 2 1.5 1 0.5 0 3.5 4 4.5 VCC (V) 5 5.5 VILS VIN (V) 3 VIHS TA = + 25 °C VIN - VCC 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 3.5 4 4.5 VCC (V) VIL VIH TA = + 25 °C 5 5.5 (Continued) 78 MB91245/S Series (Continued) (9) “H” level output voltage VCC = DVCC = 5.0 V TA = + 25 °C (10) “H” level output voltage VCC = DVCC = 5.0 V TA = + 25 °C VOH1 - IOH VOH2 - IOH 0.8 0.7 0.6 VCC - VOH1 (V) 0.8 0.7 0.6 VCC - VOH2 (V) 0.5 0.4 0.3 0.2 0.1 0.5 0.4 0.3 0.2 0.1 0 0 −1 −2 −3 IOH (mA) −4 −5 0 0 −10 −20 IOH (mA) −30 −40 (11) “L” level output voltage VCC = DVCC = 5.0 V TA = + 25 °C (12) “L” level output voltage VCC = DVCC = 5.0 V TA = + 25 °C VOL1 - IOL VOL2 - IOL 0.8 0.7 0.6 VOL1 (V) 0.8 0.7 0.6 VOL2 (V) 0.5 0.4 0.3 0.2 0.1 0 0.5 0.4 0.3 0.2 0.1 0 0 1 2 IOL (mA) 3 4 5 0 10 20 IOL (mA) 30 40 79 MB91245/S Series ■ ORDERING INFORMATION Part number MB91V245ACR-ES MB91F248PFV-GSE1 MB91F248SPFV-GSE1 MB91247PFV-GSE1 MB91247SPFV-GSE1 MB91248PFV-GSE1 MB91248SPFV-GSE1 Package 401-pin ceramic PGA (PGA-401C-A02) 144-pin plastic LQFP (FPT-144P-M08) 144-pin plastic LQFP (FPT-144P-M08) 144-pin plastic LQFP (FPT-144P-M08) 144-pin plastic LQFP (FPT-144P-M08) 144-pin plastic LQFP (FPT-144P-M08) 144-pin plastic LQFP (FPT-144P-M08) Remarks Evaluation product Dual clock product Single clock product Dual clock product Single clock product Dual clock product Single clock product 80 MB91245/S Series ■ PACKAGE DIMENSION 144-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.50 mm 20.0 × 20.0 mm Gullwing Plastic mold 1.70 mm MAX 1.20g P-LFQFP144-20×20-0.50 (FPT-144P-M08) Code (Reference) 144-pin plastic LQFP (FPT-144P-M08) 22.00±0.20(.866±.008)SQ * 20.00±0.10(.787±.004)SQ 108 73 Note 1) *:Values do not include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 0.145±0.055 (.006±.002) 109 72 0.08(.003) Details of "A" part 1.50 –0.10 +0.20 +.008 .059 –.004 (Mounting height) INDEX 0˚~8˚ 0.10±0.10 (.004±.004) (Stand off) 144 37 "A" LEAD No. 1 36 0.50(.020) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) 0.22±0.05 (.009±.002) 0.08(.003) M C 2003 FUJITSU LIMITED F144019S-c-4-6 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 81 MB91245/S Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. 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Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Edited Business Promotion Dept. F0610