MB91F464HB

FUJITSU MICROELECTRONICS DATA SHEET DS07-16616-1E 32-bit Microcontroller CMOS FR60 MB91460H Series MB91F464HB ■ DESCRIPTION MB91460H series is a line of general-purpose 32-bit RISC microcontrollers designed for embedded control applications which require high-speed real-time processing, such as consumer devices and on-board vehicle systems. This series uses the FR60 CPU, which is compatible with the FR family* of CPUs. This series contains the LIN-USART and CAN controllers. * : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Microelectronics Limited. ■ FEATURES 1. FR60 CPU core • • • • • • • 32-bit RISC, load/store architecture, five-stage pipeline 16-bit fixed-length instructions (basic instructions) Instruction execution speed: 1 instruction per cycle Instructions including memory-to-memory transfer, bit manipulation, and barrel shift instructions: Instructions suitable for embedded applications Function entry/exit instructions and register data multi-load store instructions : Instructions supporting C language Register interlock function: Facilitating assembly-language coding Built-in multiplier with instruction-level support Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles Interrupts (save PC/PS) : 6 cycles (16 priority levels) Harvard architecture enabling program access and data access to be performed simultaneously Instructions compatible with the FR family • • • For the information for microcontroller supports, see the following web site. This web site includes the "Customer Design Review Supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development. http://edevice.fujitsu.com/micom/en-support/ Copyright©2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2009.8 MB91460H Series 2. Internal peripheral resources • General-purpose ports : Maximum 108 ports • DMAC (DMA Controller) Maximum of 5 channels able to operate simultaneously 2 transfer sources (internal peripheral/software) Activation source can be selected using software Addressing mode specifies full 32-bit addresses (increment/decrement/fixed) Transfer mode (demand transfer/burst transfer/step transfer/block transfer) Transfer data size selectable from 8/16/32-bit Multi-byte transfer enabled (by software) DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H) • A/D converter (successive approximation type) 10-bit resolution: maximum 32 channels Conversion time: minimum 1 μs • External interrupt inputs : maximum 16 channels 3 channels shared with CAN RX or I2C pins • Bit search module (for REALOS) Function to search the first bit position of ‘’1’’, ‘’0’’, ‘’changed’’ from the MSB (most significant bit) within one word • LIN-USART (full duplex double buffer): 4 or 7 channels Clock synchronous/asynchronous selectable Sync-break detection Internal dedicated baud rate generator • I2C bus interface (supports 400 kbps): 2 channels Master/slave transmission and reception Arbitration function, clock synchronization function • CAN controller (C-CAN): 1 channel Maximum transfer speed: 1 Mbps 32 transmission/reception message buffers • Sound generator : 1 channel Tone frequency : PWM frequency divide-by-two (reload value + 1) • Alarm comparator : 1 channel Monitor external voltage Generate an interrupt in case of voltage lower/higher than the defined thresholds (reference voltage) • 16-bit PPG timer : maximum 16 channels • 16-bit reload timer: 8 channels • 16-bit free-run timer: 8 channels (1 channel each for ICU and OCU) • Input capture: maximum 8 channels (operates in conjunction with the free-run timer) • Output compare: maximum 8 channels (operates in conjunction with the free-run timer) • Up/Down counter: 2 channels (2*8-bit or 1*16-bit) • Watchdog timer • Real-time clock • Low-power consumption modes : Sleep/stop mode function • Low voltage detection circuit (Continued) 2 DS07-16616-1E MB91460H Series (Continued) • Clock supervisor Monitors the sub-clock (32 kHz) and the main clock (4 MHz) , and switches to a recovery clock (CR oscillator, etc.) when the oscillations stop. • Clock modulator • Clock monitor • Sub-clock calibration Corrects the real-time clock timer when operating with the 32 kHz or CR oscillator • Main oscillator stabilization timer Generates an interrupt in sub-clock mode after the stabilization wait time has elapsed on the 23-bit stabilization wait time counter • Sub-oscillator stabilization timer Generates an interrupt in main clock mode after the stabilization wait time has elapsed on the 15-bit stabilization wait time counter 3. Package and technology • • • • Package : QFP-144 CMOS 180 nm technology Power supply range 3 V to 5 V (1.8 V internal logic provided by a step-down voltage converter) Operating temperature range: between - 40°C and + 105°C DS07-16616-1E 3 MB91460H Series ■ PRODUCT LINEUP Feature Max. core frequency (CLKB) Max. resource frequency (CLKP) Max. external bus frequency (CLKT) Max. CAN frequency (CLKCAN) Technology Watchdog Watchdog (RC osc. based) Bit Search Reset input (INITX) MB91FV460B 100 MHz 50 MHz 50 MHz 50 MHz 0.18μm yes yes (disengageable) yes yes MB91F464HB 100 MHz 50 MHz 50 MHz 50 MHz 0.18μm yes yes yes yes Clock Modulator Clock Monitor Low Power Mode DMA MMU/MPU yes yes yes 5 ch MPU (16 ch)*1 yes yes yes 5 ch MPU (8 ch)*1 Flash memory Flash Protection Internal Flash memory 2112KB + external emulation SRAM with 64bit read data yes 416 KByte yes D-RAM ID-RAM Flash-Cache (Instruction cache) Boot-ROM / BI-ROM 64 KByte 64 KByte 16 KByte 16 KByte Boot Flash + 1KB Boot ROM 24 KByte 16 KByte 8 KByte 4 KByte RTC Free Running Timer ICU OCU Reload Timer PPG 16-bit 1 ch 12 ch 10 ch 8 ch 16 ch 32 ch 1 ch 8 ch*2 MD_3=0: 8 ch MD_3=1: 4 ch*3 MD_3=0: 8 ch MD_3=1: 4 ch*4 8 ch*5 MD_3=0: 16 ch MD_3=1: 8 ch*6 Sound Generator Up/Down Counter (8/16 bit) 1 ch (old) + 1 ch (new) 4 ch (8-bit) / 2 ch (16-bit) 1 ch (old) MD_3=0: 2 ch (8-bit) / 1 ch (16bit) MD_3=1: NA*7 C_CAN LIN-USART I2C (400K) 6 ch (128msg) 16 ch (FIFO) 8 ch 1 ch (32msg) MD_3=0: 3 ch + 4 ch FIFO*8 MD_3=1: 4 ch FIFO 2 ch FR external bus yes (32bit addr, 32bit data) MD_3=0: no MD_3=1: yes (22bit addr, 16bit data) 4 DS07-16616-1E MB91460H Series Feature MB91FV460B MB91F464HB MD_3=0: 16 ch MD_3=1: 12 ch*9 1 ch External Interrupts NMI Interrupts 32 ch 1 ch ADC (10-bit) Alarm Comparator 32 ch + 22 ch 2 ch MD_3=0: 32 ch MD_3=1: 16 ch 1 ch Supply Supervisor (low voltage detection) Clock Supervisor yes yes yes yes Main clock oscillator Sub clock oscillator RC oscillator PLL 4 MHz 32kHz 100kHz / 2MHz x 25 4 MHz 32kHz 100kHz / 2MHz x 25 DSU4 EDSU yes yes (32 BP)*1 no yes (16 BP)*1 Supply voltage Regulator Power consumption Temperature Range (Ta) 1.8V + 3V/5V no 1.5 W 0..70 C 3V/5V yes 16 ...100MHz) ESD Protection (Human body model) RC Oscillator Vsurge fRC100kHz fRC2MHz 2 50 1 100 2 200 4 TA CS Value Min 3.0 3.0 3.0 ⎯ ⎯ − 40 10 0.6 Typ ⎯ ⎯ ⎯ 4.7 ⎯ ⎯ Max 5.5 5.5 5.5 ⎯ 50 + 105 Unit V V V μF V/ms °C ms ms kV Rdischarge = 1.5kΩ Cdischarge = 100pF Internal regulator A/D converter Use a X7R ceramic capacitor or a capacitor that has similar frequency characteristics. Remarks kHz VDDCORE > 1.65V MHz WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. VCC18C VSS5 CS AVSS5 DS07-16616-1E 83 MB91460H Series 3. DC characteristics (VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 °C to + 105 °C) Parameter Symbol Pin name Condition Port inputs if CMOS Hysteresis 0.8/0.2 input is selected Value Min 0.8 × VDD Typ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Max VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 Unit Remarks CMOS hysteresis input 4.5 V < VDD < 5.5 V 3 V < VDD < 4.5 V ⎯ V V V V ⎯ VIH ⎯ ⎯ VIHR INITX MD_3 to MD_0 X0, X0A Port inputs if CMOS 0.7 × VDD Hysteresis 0.7/0.3 0.74 × VDD input is selected AUTOMOTIVE Hysteresis input is selected Port inputs if TTL input is selected ⎯ ⎯ ⎯ ⎯ Port inputs if CMOS Hysteresis 0.8/0.2 input is selected Port inputs if CMOS Hysteresis 0.7/0.3 input is selected Port inputs if AUTOMOTIVE Hysteresis input is selected Port inputs if TTL input is selected ⎯ ⎯ ⎯ 0.8 × VDD Input “H” voltage 2.0 VDD + 0.3 V INITX input pin (CMOS Hysteresis) Mode input pins External clock in “Oscillation mode” External clock in “Fast Clock Input mode” 0.8 × VDD VDD + 0.3 V VIHM VIHX0S VDD - 0.3 2.5 VDD + 0.3 VDD + 0.3 V V VIHX0F X0 0.8 × VDD VDD + 0.3 V ⎯ VSS - 0.3 ⎯ 0.2 × VDD V ⎯ VIL ⎯ Input “L” voltage ⎯ VILR INITX MD_3 to MD_0 X0, X0A VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.3 × VDD 0.5 × VDD 0.46 × VDD 0.8 V V V V INITX input pin (CMOS Hysteresis) Mode input pins External clock in “Oscillation mode” 4.5 V < VDD < 5.5 V 3 V < VDD < 4.5 V VSS - 0.3 0.2 × VDD V VILM VILXDS VSS - 0.3 VSS - 0.3 VSS + 0.3 0.5 V V 84 DS07-16616-1E MB91460H Series Pin name X0 Value Min VSS - 0.3 Typ ⎯ Max 0.2 × VDD Parameter Symbol Input “L” voltage Condition Unit Remarks External clock in “Fast Clock Input mode” Driving strength set to 2 mA VILXDF ⎯ V VOH2 4.5V ≤ VDD ≤ 5.5V, Normal IOH = - 2mA outputs 3.0V ≤ VDD < 4.5V, IOH = - 1.6mA 4.5V ≤ VDD ≤ 5.5V, Normal IOH = − 5mA outputs 3.0V ≤ VDD < 4.5V, IOH = - 3mA I2C 3.0V ≤ VDD ≤ 5.5V, outputs IOH = - 3mA 4.5V ≤ VDD ≤ 5.5V, Normal IOL = + 2mA outputs 3.0V ≤ VDD < 4.5V, IOL = + 1.6mA 4.5V ≤ VDD ≤ 5.5V, Normal IOL = + 5mA outputs 3.0V ≤ VDD < 4.5V, IOL = + 3mA I2C 3.0V ≤ VDD ≤ 5.5V, outputs IOL = + 3mA 3.0V ≤ VDD ≤ 5.5V VSS5 < VI < VDD Pnn_m TA=25 °C *1 3.0V ≤ VDD ≤ 5.5V VSS5 < VI < VDD TA=105 °C 3.0V ≤ VDD ≤ 5.5V TA=25 °C 3.0V ≤ VDD ≤ 5.5V TA=105 °C 3.0V ≤ VDD ≤ 3.6V 4.5V ≤ VDD ≤ 5.5V 3.0V ≤ VDD ≤ 3.6V 4.5V ≤ VDD ≤ 5.5V VDD - 0.5 ⎯ ⎯ V Output “H” voltage VOH5 VDD - 0.5 ⎯ ⎯ V Driving strength set to 5 mA VOH3 VDD - 0.5 ⎯ ⎯ V VOL2 ⎯ ⎯ 0.4 V Driving strength set to 2 mA Output “L“ voltage VOL5 ⎯ ⎯ 0.4 V Driving strength set to 5 mA VOL3 ⎯ -1 ⎯ ⎯ 0.4 V +1 μA Input leakage current IIL -3 ⎯ ⎯ ⎯ 100 50 100 50 +3 μA μA kΩ kΩ Analog input leakage current Pull-up resistance Pull-down resistance -1 -3 40 25 40 25 +1 +3 160 100 180 100 IAIN ANn*2 RUP Pnn_m *3 INITX Pnn_m *4 RDOWN DS07-16616-1E 85 MB91460H Series Pin name Value Min Typ Max Parameter Symbol Condition Unit Remarks Input capacitance CIN All except VDD5, VDD5R, f = 1 MHz VSS5, AVCC5, AVSS5, AVRH5 CLKB: 100 MHz CLKP: 50 MHz VDD5R CLKT: 50 MHz CLKCAN: 50 MHz TA = + 25 °C TA = + 105 °C TA = + 25 °C TA = + 105 °C TA = + 25 °C TA = + 105 °C - 5 15 pF ICC - 100 130 mA μA μA μA μA μA μA μA μA μA μA Code fetch from Flash ⎯ ⎯ - 30 300 100 500 50 400 70 50 250 20 150 2000 500 2400 250 2200 150 100 500 40 At stop mode *5 RTC : 4 MHz mode *5 RTC : 100 kHz mode *5 External low voltage detection Internal low voltage detection Main clock (4 MHz) Sub clock (32 kHz) Power supply current MB91 F464HB ICCH VDD5R ILVE ILVI VDD5 VDD5R ⎯ ⎯ - IOSC VDD5 - 1. 2. 3. 4. Pnn_m includes all GPIO pins. Analog (AN) channels and PullUp/PullDown are disabled. ANn includes all pins where AN channels are enabled. Pnn_m includes all GPIO pins. The pull up resistors must be enabled by PPER/PPCR setting and the pins must be in input direction. Pnn_m includes all GPIO pins. The pull down resistors must be enabled by PPER/PPCR setting and the pins must be in input direction. 86 DS07-16616-1E MB91460H Series 4. A/D converter characteristics (VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C) Parameter Resolution Total error Nonlinearity error Differential nonlinearity error Zero reading voltage Full scale reading voltage Symbol Pin name ⎯ ⎯ ⎯ ⎯ VOT VFST ⎯ ⎯ ⎯ ⎯ ANn ANn Value Min ⎯ −3 − 2.5 − 1.9 AVRL− 1.5 LSB AVRH− 3.5 LSB 0.6 Compare time Tcomp ⎯ 2.0 ⎯ ⎯ ⎯ ⎯ μs μs Typ ⎯ ⎯ ⎯ ⎯ AVRL + 0.5 LSB AVRH− 1.5 LSB ⎯ Max 10 +3 + 2.5 + 1.9 AVRL + 2.5 LSB AVRH + 0.5 LSB 16,500 Unit bit LSB LSB LSB V V μs 4.5 V ≤ AVCC5 ≤ 5.5 V 3.0 V ≤ AVCC5 ≤ 4.5 V 4.5 V ≤ AVCC5 ≤ 5.5 V, REXT < 2 kΩ 3.0 V ≤ AVCC5 ≤ 4.5 V, REXT < 1 kΩ 4.5 V ≤ AVCC5 ≤ 5.5 V 3.0 V ≤ AVCC5 ≤ 4.5 V 4.5 V ≤ AVCC5 ≤ 5.5 V 3.0 V ≤ AVCC5 ≤ 4.5 V TA = + 25 °C TA = + 105 °C Remarks 0.4 Sampling time Tsamp ⎯ 1.0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 11 2.6 12.1 +1 +3 AVRH 4 μs μs μs pF kΩ kΩ μA μA V LSB 1.0 Conversion time Tconv ⎯ 3.0 Input capacitance CIN ANn ⎯ ⎯ Input resistance RIN ANn ⎯ Analog input leakage current Analog input voltage range Offset between input channels IAIN VAIN ⎯ ANn ANn ANn −1 −3 AVRL ⎯ (Continued) Note : The accuracy gets worse as AVRH - AVRL becomes smaller DS07-16616-1E 87 MB91460H Series (Continued) Parameter Symbol Pin name AVRH Reference voltage range AVRL IA IAH IR IRH AVSS5 AVCC5 AVCC5 AVRH5 AVRH5 AVRH5 Value Min 0.75 × AVCC5 AVSS5 ⎯ ⎯ ⎯ ⎯ Typ ⎯ ⎯ 2.5 ⎯ 0.7 ⎯ Max AVCC5 AVCC5 × 0.25 5 5 1 5 Unit V V mA μA mA μA A/D Converter active A/D Converter not operated *1 A/D Converter active A/D Converter not operated *2 Remarks Power supply current per ADC macro *3 Reference voltage current per ADC macro *3 *1 : Supply current at AVCC5, if A/D converter and ALARM comparator are not operating, (VDD5 = AVCC5 = AVRH = 5.0 V) *2 : Input current at AVRH5, if A/D converter is not operating, (VDD5 = AVCC5 = AVRH = 5.0 V) *3 : The current consumption per ADC macro is given here. On devices having more then one A/D converter, the current values have to be multiplied by the number of macros. Sampling Time Calculation Tsamp = ( 2.6 kOhm + REXT) × 11pF × 7; for 4.5V ≤ AVCC5 ≤ 5.5V Tsamp = (12.1 kOhm + REXT) × 11pF × 7; for 3.0V ≤ AVCC5 < 4.5V Conversion Time Calculation Tconv = Tsamp + Tcomp 88 DS07-16616-1E MB91460H Series Definition of A/D converter terms • Resolution Analog variation that is recognizable by the A/D converter. • Nonlinearity error Deviation between actual conversion characteristics and a straight line connecting the zero transition point (00 0000 0000B ↔ 00 0000 0001B) and the full scale transition point (11 1111 1110B ↔ 11 1111 1111B). • Differential nonlinearity error Deviation of the input voltage from the ideal value that is required to change the output code by 1 LSB. • Total error This error indicates the difference between actual and theoretical values, including the zero transition error, full scale transition error, and nonlinearity error. Total error 3FFH 3FEH 3FDH 1.5 LSB’ Actual conversion characteristics {1 LSB’ (N - 1) + 0.5 LSB’} Digital output 004H VNT 003H 002H 001H 0.5 LSB' AVSS5 AVRH (measurement value) Actual conversion characteristics Ideal characteristics Analog input 1LSB' (ideal value) = AVRH − AVSS5 [V] 1024 Total error of digital output N = VNT − {1 LSB' × (N − 1) + 0.5 LSB'} 1 LSB' N : A/D converter digital output value VOT' (ideal value) = AVSS5 + 0.5 LSB' [V] VFST' (ideal value) = AVRH − 1.5 LSB' [V] VNT : Voltage at which the digital output changes from (N + 1) H to NH (Continued) DS07-16616-1E 89 MB91460H Series (Continued) Nonlinearity error 3FFH 3FEH {1 LSB (N - 1) + VOT} 3FDH Actual conversion characteristics Differential nonlinearity error Actual conversion characteristics (N+1)H VFST (measurement value) Digital output Digital output Ideal characteristics NH 004H 003H 002H 001H VNT (measurement value) (N-1)H VFST VNT (measurement value) Actual conversion characteristics (measurement value) Ideal characteristics (N-2)H VTO (measurement value) AVSS5 AVRH AVSS5 Actual conversion characteristics AVRH Analog input Analog input Nonlinearity error of digital output N = VNT − {1LSB × (N − 1) + VOT} [LSB] 1LSB V (N + 1) T − VNT 1LSB − 1 [LSB] Differential nonlinearity error of digital output N = 1LSB = VFST − VOT 1022 [V] N : A/D converter digital output value VOT : Voltage at which the digital output changes from 000H to 001H. VFST : Voltage at which the digital output changes from 3FEH to 3FFH. 90 DS07-16616-1E MB91460H Series 5. Alarm comparator characteristics Parameter Symbol Pin name Value Min ⎯ Typ Max Unit Remarks Alarm comparator enabled in fast mode (per channel) *1 Alarm comparator enabled in normal mode (per channel) *1 IA5ALMF 25 40 μA Power supply current AVCC5 IA5ALMS ⎯ 7 10 μA IA5ALMH ALARM pin input current ALARM pin input voltage range Alarm upper limit voltage Alarm lower limit voltage Alarm hysteresis voltage Alarm input resistance IALIN ⎯ -1 -3 0 ⎯ ⎯ ⎯ ⎯ 5 +1 +3 AVCC5 μA μA μA V Alarm comparator disabled TA=25 °C TA=105 °C VALIN VIAH AVCC5 × 0.78 - 3% AVCC5 × 0.36 - 5% ALARM_n AVCC5 × 0.78 AVCC5 × 0.78 + 3% AVCC5 × 0.36 + 5% V VIAL AVCC5 × 0.36 V VIAHYS 50 ⎯ ⎯ 0.1 250 ⎯ 0.2 mV MΩ μs Alarm comparator enabled in fast mode *1 Alarm comparator enabled in normal mode *1 RIN 5 ⎯ tCOMPF Comparion time tCOMPS ⎯ 1 2 μs Note: *1 : The fast Alarm Comparator mode is enabled by setting ACSR.MD=1 Setting ACSR.MD=0 sets the normal mode. DS07-16616-1E 91 MB91460H Series 6. FLASH memory program/erase characteristics 6.1. MB91F464HB Value Min 10 000 20 Typ 0.9 n*0.9 23 Max 3.6 n*3.6 370 (TA = 25oC, Vcc = 5.0V) Parameter Sector erase time Chip erase time Word (16-bit or 32-bit width) programming time Programme/Erase cycle Flash data retention time Unit s s μs cycle year *1 Remarks Erasure programming time not included n is the number of Flash sector of the device System overhead time not included *1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high temperature measurements into normalized value at 85oC) 92 DS07-16616-1E MB91460H Series 7. AC characteristics 7.1. Clock timing (VDD5 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 105 °C) Parameter Symbol Pin name X0 X1 X0A X1A Value Min 3.5 32 Typ 4 32.768 Max 16 100 Unit MHz kHz Condition Opposite phase external supply or crystal Clock frequency fC • Clock timing condition tC X0, X1, X0A, X1A PWH PWL 0.8 VCC 0.2 VCC 7.2. Reset input ratings (VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 °C to + 105 °C) Parameter Symbol Pin name Condition Value Min 8 tINTL INITX ⎯ 20 ⎯ μs Max ⎯ Unit ms INITX input time (at power-on) INITX input time (other than the above) tINTL INITX 0.2 VCC DS07-16616-1E 93 MB91460H Series 7.3. LIN-USART Timings at VDD5 = 3.0 to 5.5 V • Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 5 mA - VDD5 = 3.0 V to 5.5 V, Iload = 3 mA - VSS5 = 0 V - Ta = -40 °C to +105 °C - Cl = 50 pF (load capacity value of pins when testing) - VOL = 0.2 x VDD5 - VOH = 0.8 x VDD5 - EPILR = 0, PILR = 1 (Automotive Level = worst case) (VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 °C to + 105 °C) Parameter Serial clock cycle time SCK ↓ → SOT delay time SOT → SCK ↓ delay time Valid SIN → SCK ↑ setup time SCK ↑ → valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SOT delay time Valid SIN → SCK ↑ setup time SCK ↑ → valid SIN hold time SCK rising time SCK falling time Symbol tSCYCI tSLOVI tOVSHI tIVSHI tSHIXI tSHSLE tSLSHE tSLOVE tIVSHE tSHIXE tFE tRE Pin name SCKn SCKn SOTn SCKn SOTn SCKn SINn SCKn SINn SCKn SCKn SCKn SOTn SCKn SINn SCKn SINn SCKn SCKn External clock operation (slave mode) Internal clock operation (master mode) Condition VDD5 = 3.0 V to 4.5 V VDD5 = 4.5 V to 5.5 V Min 4 tCLKP - 30 m× tCLKP - 30* tCLKP + 55 0 tCLKP + 10 tCLKP + 10 ⎯ 10 tCLKP + 10 ⎯ ⎯ Max ⎯ 30 ⎯ ⎯ ⎯ ⎯ ⎯ 2 tCLKP + 55 ⎯ ⎯ 20 20 Min 4 tCLKP - 20 m× tCLKP - 20* tCLKP + 45 0 tCLKP + 10 tCLKP + 10 ⎯ 10 tCLKP + 10 ⎯ ⎯ Max ⎯ 20 ⎯ ⎯ ⎯ ⎯ ⎯ 2 tCLKP + 45 ⎯ ⎯ 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns * : Parameter m depends on tSCYCI and can be calculated as : • if tSCYCI = 2*k*tCLKP, then m = k, where k is an integer > 2 • if tSCYCI = (2*k + 1)*tCLKP, then m = k + 1, where k is an integer > 1 Notes : • The above values are AC characteristics for CLK synchronous mode. • tCLKP is the cycle time of the peripheral clock. 94 DS07-16616-1E MB91460H Series • Internal clock mode (master mode) tSCYCI SCKn for ESCR:SCES = 0 VOL VOH VOL SCKn for ESCR:SCES = 1 VOH VOL VOH tSLOVI tOVSHI VOH VOL tIVSHI VIH VIL SOTn tSHIXI VIH VIL SINn • External clock mode (slave mode) tSLSHE tSHSLE VOH VOL VOL VOL SCKn for ESCR:SCES = 0 VOH SCKn for ESCR:SCES = 1 VOL tFE VOH VOH tRE VOL VOH tSLOVE VOH VOL tIVSHE VIH VIL tSHIXE VIH VIL SOTn SINn DS07-16616-1E 95 MB91460H Series 7.4. I2C AC Timings at VDD5 = 3.0 to 5.5 V • Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 3 mA - VDD5 = 3.0 V to 5.5 V, Iload = 3 mA - VSS5 = 0 V - Ta = - 40 °C to + 105 °C - Cl = 50 pF - VOL = 0.3 × VDD5 - VOH = 0.7 × VDD5 - EPILR = 0, PILR = 0 (CMOS Hysteresis 0.3 × VDD5/0.7 × VDD5) Fast mode: (VDD5 = 3.5 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 °C to + 105 °C) Parameter SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Setup time for a repeated START condition Data hold time for I2C-bus devices Data setup time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Setup time for STOP condition Bus free time between a STOP and START condition Capacitive load for each bus line Pulse width of spike suppressed by input filter Symbol fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF Cb tSP Pin name SCLn SCLn, SDAn SCLn SCLn SCLn, SDAn SCLn, SDAn SCLn SDAn SCLn, SDAn SCLn, SDAn SCLn, SDAn SCLn, SDAn SCLn, SDAn SCLn, SDAn Value Min 0 0.6 1.3 0.6 0.6 0 100 20 + 0.1Cb 20 + 0.1Cb 0.6 1.3 ⎯ 0 Max 400 ⎯ ⎯ ⎯ ⎯ 0.9 ⎯ 300 300 ⎯ ⎯ 400 (1..1.5) × tCLKP Unit kHz μs μs μs μs μs ns ns ns μs μs pF ns *1 Remark *1 The noise filter will suppress single spikes with a pulse width of 0ns and between (1 to 1.5) cycles of peripheral clock, depending on the phase relationship between I2C signals (SDA, SCL) and peripheral clock. Note: tCLKP is the cycle time of the peripheral clock. 96 DS07-16616-1E DS07-16616-1E Sr tr S P S tf SDA tBUF tHD;DAT tSU;DAT tHD;STA tSU;STA tSP tSU;ST0 tHD;STA SCL tLOW tHIGH tf tr MB91460H Series 97 MB91460H Series 7.5. Free-run timer clock (VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 °C to + 105 °C) Parameter Input pulse width Symbol tTIWH tTIWL Pin name CKn Condition ⎯ Value Min 4tCLKP Max ⎯ Unit ns Note : tCLKP is the cycle time of the peripheral clock. CKn VIH VIH VIL tTIWH tTIWL VIL 7.6. Trigger input timing (VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 °C to + 105 °C) Parameter Symbol tINP tATGX Pin name ICUn ATGX Condition ⎯ ⎯ Value Min 5tCLKP 5tCLKP Max ⎯ ⎯ Unit ns ns Input capture input trigger A/D converter trigger Note : tCLKP is the cycle time of the peripheral clock. tATGX, tINP ICUn, ATGX 98 DS07-16616-1E MB91460H Series 7.7. External Bus AC Timings at VDD35 = 3.0 to 5.5 V • Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 5 mA - VDD35 = 4.5 V to 5.5 V, Iload = 3 mA - VSS5 = 0 V - Ta = - 40 °C to + 105 °C - Cl = 50 pF - VOL = 0.5 × VDD35 - VOH = 0.5 × VDD35 - EPILR = 0, PILR = 1 (Automotive Level = worst case) 7.7.1. Basic Timing (VDD35 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 105 °C) Parameter Symbol tCLCH tCHCL tCLCSL tCLCSH tCHCSL tCLAV SYSCLK A21 to A0 SYSCLK CSXn Pin name SYSCLK Value Min 1/2 × tCLKT - 1 1/2 × tCLKT - 9 ⎯ ⎯ -6 ⎯ Max 1/2 × tCLKT + 9 1/2 × tCLKT + 1 8 12 +1 13 Unit ns ns ns ns ns ns SYSCLK SYSCLK ↓ to CSXn delay time SYSCLK ↑ to CSXn delay time (Addr → CS delay) SYSCLK ↓ to Address valid delay time Note : tCLKT is the cycle time of the external bus clock. DS07-16616-1E 99 MB91460H Series tCLCH tCHCL tCYC SYSCLK tCLCSL tCLCSH CSXn tCHCSL delayed CSXn tCLASH tCLASL ASX tCLAV ADDRESS tCLBAH tCLBAL BAAX 100 DS07-16616-1E MB91460H Series 7.7.2. Synchronous/Asynchronous read access (VDD35 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 105 °C) Parameter SYSCLK ↑ to RDX delay time Data valid to RDX ↑ setup time RDX ↑ to Data valid hold time SYSCLK ↓ to WRXn (as byte enable) delay time SYSCLK ↓ to CSXn delay time Symbol TCHRL TCHRH TDSRH TRHDX TCLWRL TCLWRH TCLCSL TCLCSH Pin name SYSCLK RDX RDX D31 to D16 RDX D31 to D16 SYSCLK WRXn SYSCLK CSXn Value Min -7 -4 33 0 ⎯ 0 ⎯ ⎯ Max 1 2 ⎯ ⎯ 8 ⎯ 8 12 Unit ns ns ns ns ns ns ns ns SYSCLK tCLCSL tCLCSH CSXn tCLWRL tCLWRH WRXn (as byte enable) tCHRH tCHRL RDX tDSRH tRHDX DATA IN DS07-16616-1E 101 MB91460H Series 7.7.3. Synchronous write access (VDD35 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 105 °C) Parameter SYSCLK ↓ to WRXn delay time Data valid to WRXn ↓ setup time WRXn ↑ to Data valid hold time SYSCLK ↓ to CSXn delay time Symbol TCLWRL TCLWRH TDSWRL TWRHDH TCLCSL TCLCSH Pin name SYSCLK WRXn WRXn D31 to D16 WRXn D31 to D16 SYSCLK CSXn Value Min ⎯ 0 -7 tCLKT - 20 ⎯ ⎯ Max 8 ⎯ ⎯ ⎯ 8 12 Unit ns ns ns ns ns ns SYSCLK tCLCSL tCLCSH CSXn tCLWRH tCLWRL WRXn tDSWRL tWRHDH DATA OUT 102 DS07-16616-1E MB91460H Series 7.7.4. Asynchronous write access (VDD35 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 105 °C) Parameter WRXn ↓ to WRXn ↑ pulse width Data valid to WRXn ↓ setup time WRXn ↑ to Data valid hold time WRXn to CSXn delay time Symbol TWRLWRH TDSWRL TWRHDH TCLWRL TWRHCH Pin name WRXn WRXn D31 to D16 WRXn D31 to D16 WRXn CSXn Value Min tCLKT 1/2 × tCLKT - 10 1/2 × tCLKT - 19 ⎯ 1/2 × tCLKT Max ⎯ ⎯ ⎯ 1/2 × tCLKT ⎯ Unit ns ns ns ns ns CSXn TCLWRL TWRLWRH TWRHCH WRXn TDSWRL TWRHDH DATA OUT DS07-16616-1E 103 MB91460H Series 7.7.5. RDY waitcycle insertion (VDD35 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 105 °C) Parameter RDY setup time RDY hold time Symbol TRDYS TRDYH Pin name SYSCLK RDY SYSCLK RDY Value Min 34 0 Max ⎯ ⎯ Unit ns ns SYSCLK tRDYS tRDYH RDY 104 DS07-16616-1E MB91460H Series ■ ORDERING INFORMATION Part number MB91F464HBPMC-GSE2 Package 144-pin plastic LQFP (FPT-144P-M08) Remarks Lead-free package DS07-16616-1E 105 MB91460H Series ■ PACKAGE DIMENSION 144-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.50 mm 20.0 × 20.0 mm Gullwing Plastic mold 1.70 mm MAX 1.20g P-LFQFP144-20×20-0.50 (FPT-144P-M08) Code (Reference) 144-pin plastic LQFP (FPT-144P-M08) 22.00±0.20(.866±.008)SQ * 20.00±0.10(.787±.004)SQ 108 73 Note 1) *:Values do not include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 0.145±0.055 (.006±.002) 109 72 0.08(.003) Details of "A" part 1.50 –0.10 .059 –.004 +0.20 +.008 (Mounting height) INDEX 0˚~8˚ 0.10±0.10 (.004±.004) (Stand off) 144 37 "A" LEAD No. 1 36 0.50(.020) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) 0.22±0.05 (.009±.002) 0.08(.003) M ©2003-2008 FUJITSU MICROELECTRONICS LIMITED F144019S-c-4-7 C 2003 FUJITSU LIMITED F144019S-c-4-6 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ 106 DS07-16616-1E MB91460H Series ■ REVISION HISTORY Version 2.0 Date 2009-01-07 Initial version Remark DS07-16616-1E 107 MB91460H Series ■ MAIN CHANGES IN THIS EDITION Page 87 Section 4. A/D converter characteristics Change Results Corrected "Zero reading voltage" and "Full scale reading voltage". The vertical lines marked in the left side of the page show the changes. 108 DS07-16616-1E MB91460H Series MEMO DS07-16616-1E 109 MB91460H Series MEMO 110 DS07-16616-1E MB91460H Series MEMO DS07-16616-1E 111 MB91460H Series FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. 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Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department