MB91F467DA

FUJITSU MICROELECTRONICS DATA SHEET DS07-16612-2E 32-bit Microcontroller CMOS FR60 MB91460D Series MB91F465DA, MB91F467DA/F467DB ■ DESCRIPTION MB91460D series is a line of general-purpose 32-bit RISC microcontrollers designed for embedded control applications which require high-speed real-time processing, such as consumer devices and on-board vehicle systems. This series uses the FR60 CPU, which is compatible with the FR family* of CPUs. This series contains the LIN-USART and CAN controllers. * : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Microelectronics Limited. ■ FEATURES 1. FR60 CPU core • • • • • • • 32-bit RISC, load/store architecture, five-stage pipeline 16-bit fixed-length instructions (basic instructions) Instruction execution speed: 1 instruction per cycle Instructions including memory-to-memory transfer, bit manipulation, and barrel shift instructions: Instructions suitable for embedded applications Function entry/exit instructions and register data multi-load store instructions : Instructions supporting C language Register interlock function: Facilitating assembly-language coding Built-in multiplier with instruction-level support Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles Interrupts (save PC/PS) : 6 cycles (16 priority levels) (Continued) • For the information for microcontroller supports, see the following web site. This web site includes the "Customer Design Review Supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development. http://edevice.fujitsu.com/micom/en-support/ Copyright©2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2009.8 MB91460D Series (Continued) • Harvard architecture enabling program access and data access to be performed simultaneously • Instructions compatible with the FR family 2. Internal peripheral resources • General-purpose ports : Maximum 170 ports • DMAC (DMA Controller) Maximum of 5 channels able to operate simultaneously. (External to external : 1 channel) 3 transfer sources (external pin/internal peripheral/software) Activation source can be selected using software. Addressing mode specifies full 32-bit addresses (increment/decrement/fixed) Transfer mode (demand transfer/burst transfer/step transfer/block transfer) Fly-by transfer support (between external I/O and memory) Transfer data size selectable from 8/16/32-bit Multi-byte transfer enabled (by software) DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H) • A/D converter (successive approximation type) 10-bit resolution: 24 channels Conversion time: minimum 1 μs • External interrupt inputs : 14 channels 8 channels shared with CAN RX or I2C pins • Bit search module (for REALOS) Function to search from the MSB (most significant bit) for the position of the first “0”, “1”, or changed bit in a word • LIN-USART (full duplex double buffer): 5 channels Clock synchronous/asynchronous selectable Sync-break detection Internal dedicated baud rate generator • I2C bus interface (supports 400 kbps): 3 channels Master/slave transmission and reception Arbitration function, clock synchronization function • CAN controller (C-CAN): 3 channels Maximum transfer speed: 1 Mbps 32 transmission/reception message buffers • Stepper motor controller : 6 channels 4 high current output to each channel 2 synchronized PWMs per channel (8/10-bit) • Sound generator : 1 channel Tone frequency : PWM frequency divide-by-two (reload value + 1) • Alarm comparator : 1 channel Monitor external voltage Generate an interrupt in case of voltage lower/higher than the defined thresholds (reference voltage) • 16-bit PPG timer : 12 channels • 16-bit PFM timer : 1 channel • 16-bit reload timer: 8 channels • 16-bit free-run timer: 8 channels (1 channel each for ICU and OCU) • Input capture: 8 channels (operates in conjunction with the free-run timer) • Output compare: 4 channels (operates in conjunction with the free-run timer) • Up/Down counter: 3 channels (3*8-bit or 1*16-bit + 1*8-bit) • Watchdog timer (Continued) 2 DS07-16612-2E MB91460D Series (Continued) • Real-time clock • Low-power consumption modes : Sleep/stop mode function • Supply Supervisor: Low voltage detection circuit for external VDD5 and internal 1.8V core voltage • Clock supervisor Monitors the sub-clock (32 kHz) and the main clock (4 MHz) , and switches to a recovery clock (CR oscillator, etc.) when the oscillations stop. • Clock modulator • Clock monitor • Sub-clock calibration Corrects the real-time clock timer when operating with the 32 kHz or CR oscillator • Main oscillator stabilization timer Generates an interrupt in sub-clock mode after the stabilization wait time has elapsed on the 23-bit stabilization wait time counter • Sub-oscillator stabilization timer Generates an interrupt in main clock mode after the stabilization wait time has elapsed on the 15-bit stabilization wait time counter 3. Package and technology • • • • Package : QFP-208 CMOS 0.18 μm technology Power supply range 3 V to 5 V (1.8 V internal logic provided by a step-down voltage converter) Operating temperature range: between − 40°C and + 105°C DS07-16612-2E 3 MB91460D Series ■ PRODUCT LINEUP Feature Max. core frequency (CLKB) Max. resource frequency (CLKP) Max. external bus freq. (CLKT) Max. CAN frequency (CLKCAN) Max. FlexRay frequency (SCLK) Technology Watchdog timer Watchdog timer (RC osc. based) Bit Search Reset input (INITX) Hardware Standby input (HSTX) Clock Modulator Clock Monitor Low Power Mode DMA MAC (uDSP) MMU/MPU MB91V460A 80MHz 40MHz 40MHz 20MHz 0.35μm yes yes (disengageable) yes yes yes yes yes yes 5 ch no MPU (16 ch) 1) MB91F465DA 100MHz 50MHz 50MHz 50MHz 0.18μm yes yes yes yes no yes yes yes 5 ch no MPU (8 ch) 1) MB91F467DA MB91F467DB 96MHz 48MHz 48MHz 48MHz 0.18μm yes yes yes yes no yes yes yes 5 ch no MPU (8 ch) 1) Flash memory Satellite Flash memory Flash Protection Emulation SRAM 32bit read data - 544 KByte no yes 1088 KByte no yes D-RAM ID-RAM Flash-Cache (Instruction cache) Boot-ROM / BI-ROM 64 KByte 64 KByte 16 KByte 4 KByte fixed 32 KByte 16 KByte 8 KByte 4 KByte 32 KByte 32 KByte 8 KByte 4 KByte RTC Free Running Timer ICU OCU Reload Timer PPG 16-bit PFM 16-bit Sound Generator Up/Down Counter (8/16-bit) 1 ch 8 ch 8 ch 8 ch 8 ch 16 ch 1 ch 1 ch 4 ch (8-bit) / 2 ch (16-bit) 1 ch 8 ch 8 ch 4 ch 8 ch 12 ch 1 ch 1 ch 3 ch (8-bit) / 1 ch (16-bit) 1 ch 8 ch 8 ch 4 ch 8 ch 12 ch 1 ch 1 ch 3 ch (8-bit) / 1 ch (16-bit) C_CAN LIN-USART I2C (400k) 6 ch (128msg) 4 ch + 4 ch FIFO + 8 ch 4 ch 3 ch (32msg) 1 ch + 4 ch FIFO 3 ch 3 ch (32msg) 1 ch + 4 ch FIFO 3 ch FR external bus yes (32bit addr, 32bit data) yes (26bit addr, 32bit data) yes (26bit addr, 32bit data) 4 DS07-16612-2E MB91460D Series Feature MB91V460A MB91F465DA MB91F467DA MB91F467DB External Interrupts NMI Interrupts 16 ch 1 ch 14 ch - 14 ch - SMC LCD controller (40x4) 6 ch 1 ch 6 ch - 6 ch - ADC (10 bit) Alarm Comparator 32 ch 2 ch 24 ch 1 ch 24 ch 1 ch Supply Supervisor (low voltage detection) Clock Supervisor yes yes yes yes yes yes Main clock oscillator Sub clock oscillator RC Oscillator PLL 4MHz 32kHz 100kHz x 20 4MHz 32kHz 100kHz / 2MHz x 25 4MHz 32kHz 100kHz / 2MHz x 24 DSU4 EDSU yes yes (32 BP) *1 yes (16 BP) *1 yes (16 BP) *1 Supply Voltage Regulator Power Consumption Temperature Range (Ta) 3V / 5V yes n.a. 0..70 C 3V / 5V yes 2 • if tSCYCI = (2*k + 1)*tCLKP, then m = k + 1, where k is an integer > 1 Notes : • The above values are AC characteristics for CLK synchronous mode. • tCLKP is the cycle time of the peripheral clock. 100 DS07-16612-2E MB91460D Series • Internal clock mode (master mode) tSCYCI SCKn for ESCR:SCES = 0 VOL VOH VOL SCKn for ESCR:SCES = 1 VOH VOL VOH tSLOVI tOVSHI VOH VOL tIVSHI VOH VOL SOTn tSHIXI VOH VOL SINn • External clock mode (slave mode) tSLSHE tSHSLE VOH VOL VOL VOL SCKn for ESCR:SCES = 0 VOH SCKn for ESCR:SCES = 1 VOL tFE VOH VOH tRE tSLOVE VOH VOL tIVSHE VOH VOL VOL VOH SOTn tSHIXE VOH VOL SINn DS07-16612-2E 101 MB91460D Series 7.4. I2C AC Timings at VDD5 = 3.0 to 5.5 V • Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 3 mA - VDD5 = 3.0 V to 5.5 V, Iload = 3 mA (VDD = 4.5 V to 5.5 V for MB91F467Dx) - VSS5 = 0 V - Ta = − 40 °C to + 105 °C - Cl = 50 pF - VOL = 0.3 × VDD5 - VOH = 0.7 × VDD5 - EPILR = 0, PILR = 0 (CMOS Hysteresis 0.3 × VDD5/0.7 × VDD5) Fast mode: (VDD5 = 3.5 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C) Parameter SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Setup time for a repeated START condition Data hold time for I2C-bus devices Data setup time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Setup time for STOP condition Bus free time between a STOP and START condition Capacitive load for each bus line Pulse width of spike suppressed by input filter Symbol fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF Cb tSP Pin name SCLn SCLn, SDAn SCLn SCLn SCLn, SDAn SCLn, SDAn SCLn SDAn SCLn, SDAn SCLn, SDAn SCLn, SDAn SCLn, SDAn SCLn, SDAn SCLn, SDAn Value Min 0 0.6 1.3 0.6 0.6 0 100 20 + 0.1Cb 20 + 0.1Cb 0.6 1.3 ⎯ 0 Max 400 ⎯ ⎯ ⎯ ⎯ 0.9 ⎯ 300 300 ⎯ ⎯ 400 (1..1.5) × tCLKP Unit kHz μs μs μs μs μs ns ns ns μs μs pF ns *2 *1 Remark *1 *1 On MB91F467Dx only guaranteed for 4.5 V < VDD5 < 5.5 V. *2 The noise filter will suppress single spikes with a pulse width of 0ns and between (1 to 1.5) cycles of peripheral clock, depending on the phase relationship between I2C signals (SDA, SCL) and peripheral clock. Note: tCLKP is the cycle time of the peripheral clock. 102 DS07-16612-2E DS07-16612-2E Sr tr S P S tf SDA tBUF tHD;DAT tSU;DAT tHD;STA tSU;STA tSP tSU;ST0 tHD;STA SCL tLOW tHIGH tf tr MB91460D Series 103 MB91460D Series 7.5. Free-run timer clock (VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C) Parameter Input pulse width Symbol tTIWH tTIWL Pin name CKn Condition ⎯ Value Min 4tCLKP Max ⎯ Unit ns Note : tCLKP is the cycle time of the peripheral clock. CKn VIH VIH VIL tTIWH tTIWL VIL 7.6. Trigger input timing (VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C) Parameter Symbol tINP tATGX Pin name ICUn ATGX Condition ⎯ ⎯ Value Min 5tCLKP 5tCLKP Max ⎯ ⎯ Unit ns ns Input capture input trigger A/D converter trigger Note : tCLKP is the cycle time of the peripheral clock. tATGX, tINP ICUn, ATGX 104 DS07-16612-2E MB91460D Series 7.7. External Bus AC Timings at VDD35 = 4.5 to 5.5 V • Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 5 mA - VDD35 = 4.5 V to 5.5 V, Iload = 5 mA - VSS5 = 0 V - Ta = − 40 °C to + 105 °C - Cl = 50 pF - VOL = 0.2 × VDD35 - VOH = 0.8 × VDD35 - EPILR = 0, PILR = 1 (Automotive Level = worst case) 7.7.1. Basic Timing (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter Symbol tCLCH tCHCL tCLCSL tCLCSH tCHCSL tCLASL tCLASH tCLBAL tCLBAH tCLAV MCLKO ASX MCLKO BAAX MCLKO A25 to A0 MCLKO CSXn Pin name MCLKO Value Min 1/2 x tCLKT − 7 1/2 × tCLKT − 7 ⎯ ⎯ −5 ⎯ ⎯ ⎯ 1 ⎯ Max 1/2 × tCLKT + 7 1/2 × tCLKT + 7 9 8 +2 8 8 5 ⎯ 11 Unit ns ns ns ns ns ns ns ns ns ns MCLKO MCLKO ↓ to CSXn delay time MCLKO ↑ to CSXn delay time (Addr → CS delay) MCLKO ↓ to ASX delay time MCLKO ↓ to BAAX delay time MCLKO ↓ to Address valid delay time Note : tCLKT is the cycle time of the external bus clock. DS07-16612-2E 105 MB91460D Series tCLCH tCHCL tCYC MCLKO tCLCSL tCLCSH CSXn tCHCSL delaved CSXn tCLASH tCLASL ASX tCLAV ADDRESS tCLBAH tCLBAL BAAX 106 DS07-16612-2E MB91460D Series 7.7.2. Synchronous/Asynchronous read access with external MCLKI input (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter Symbol tCHRL tCHRH tDSRH tRHDX tDSCH tCHDX tCLWRL tCLWRH tCLCSL tCLCSH Pin name MCLKO RDX MCLKI RDX RDX D31 to D0 RDX D31 to D0 MCLKI D31 to D0 MCLKI D31 to D0 MCLKO WRXn MCLKO CSXn Value Min −5 8 19 0 3 1 ⎯ −1 ⎯ ⎯ Max 2 16 ⎯ ⎯ ⎯ ⎯ 9 ⎯ 9 8 Unit ns ns ns ns ns ns ns ns ns ns MCLKO ↑ /MCLKI ↑ to RDX delay time Data valid to RDX ↑ setup time RDX ↑ to Data valid hold time (external MCLKI input) Data valid to MCLKI ↑ setup time MCLKI ↑ to Data valid hold time MCLKO ↓ to WRXn (as byte enable) delay time MCLKO ↓ to CSXn delay time Note: The usage of the external feedback from MCLKO to MCLKI is not recommended. DS07-16612-2E 107 MB91460D Series MCLKO MCLKI tCLCSL tCLCSH CSXn tCLWRL tCLWRH WRXn (as byte enable) tCHRH tCHRL RDX tDSRH tRHDX tDSCH tCHDX DATA IN 108 DS07-16612-2E MB91460D Series 7.7.3. Synchronous/Asynchronous read access with internal MCLKO --> MCLKI feedback (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter MCLKO ↑ to RDX delay time Data valid to RDX ↑ setup time RDX ↑ to Data valid hold time (internal MCLKO → MCLKI / /MCLKI feedback) MCLKO ↓ to WRXn (as byte enable) delay time MCLKO ↓ to CSXn delay time Symbol TCHRL TCHRH TDSRH Pin name MCLKO RDX RDX D31 to D0 RDX D31 to D0 MCLKO WRXn MCLKO CSXn Value Min −5 −5 20 Max 2 2 ⎯ ⎯ 9 ⎯ 9 8 Unit ns ns ns TRHDX TCLWRL TCLWRH TCLCSL TCLCSH 0 ⎯ −1 ⎯ ⎯ ns ns ns ns ns MCLKO TCLCSL TCLCSH CSXn TCLWRL TCLWRH WRXn (as byte enable) TCHRH TCHRL RDX TDSRH TRHDX DATA IN DS07-16612-2E 109 MB91460D Series 7.7.4. Synchronous write access - byte control type (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter MCLKO ↓ to WEX delay time Data valid to WEX ↓ setup time WEX ↑ to Data valid hold time MCLKO ↓ to WRXn (as byte enable) delay time MCLKO ↓ to CSXn delay time Symbol TCLWL TCLWH TDSWL TWHDH TCLWRL TCLWRH TCLCSL TCLCSH Pin name MCLKO WEX WEX D31 to D0 WEX D31 to D0 MCLKO WRXn MCLKO CSXn Value Min ⎯ 2 − 11 tCLKT − 10 ⎯ −1 ⎯ ⎯ Max 9 ⎯ ⎯ ⎯ 9 ⎯ 9 8 Unit ns ns ns ns ns ns ns ns MCLKO TCLCSL TCLCSH CSXn TCLWRL TCLWRH WRXn (as byte enable) TCLWH TCLWL WEX TDSWL TWHDH DATA OUT 110 DS07-16612-2E MB91460D Series 7.7.5. Synchronous write access - no byte control type (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter MCLKO ↓ to WRXn delay time Data valid to WRXn ↓ setup time WRXn ↑ to Data valid hold time MCLKO ↓ to CSXn delay time Symbol TCLWRL TCLWRH TDSWRL TWRHDH TCLCSL TCLCSH Pin name MCLKO WRXn WRXn D31 to D0 WRXn D31 to D0 MCLKO CSXn Value Min ⎯ −1 − 12 tCLKT − 8 ⎯ ⎯ Max 9 ⎯ ⎯ ⎯ 9 8 Unit ns ns ns ns ns ns MCLKO TCLCSL TCLCSH CSXn TCLWRH TCLWRL WRXn TDSWRL TWRHDH DATA OUT DS07-16612-2E 111 MB91460D Series 7.7.6. Asynchronous write access - byte control type (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter WEX ↓ to WEX ↑ pulse width Data valid to WEX ↓ setup time WEX ↑ to Data valid hold time WEX to WRXn delay time WEX to CSXn delay time Symbol TWLWH TDSWL TWHDH TWRLWL TWHWRH TCLWL TWHCH Pin name WEX WEX D31 to D0 WEX D31 to D0 WEX WRXn WEX CSXn Value Min tCLKT − 2 1/2 × tCLKT − 13 1/2 × tCLKT − 10 ⎯ 1/2 × tCLKT − 4 ⎯ 1/2 × tCLKT − 5 Max ⎯ ⎯ ⎯ 1/2 × tCLKT + 2 ⎯ 1/2 × tCLKT ⎯ Unit ns ns ns ns ns ns ns CSXn TCLWL TWHCH WRXn (as byte enable) TWRLWL TWLWH TWHWRH WEX TDSWL TWHDH DATA OUT 112 DS07-16612-2E MB91460D Series 7.7.7. Asynchronous write access - no byte control type (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter WRXn ↓ to WRXn ↑ pulse width Data valid to WRXn ↓ setup time WRXn ↑ to Data valid hold time WRXn to CSXn delay time Symbol TWRLWRH TDSWRL TWRHDH TCLWRL TWRHCH Pin name WRXn WRXn D31 to D0 WRXn D31 to D0 WRXn CSXn Value Min tCLKT − 1 1/2 × tCLKT − 14 1/2 × tCLKT − 7 ⎯ 1/2 × tCLKT − 3 Max ⎯ ⎯ ⎯ 1/2 × tCLKT − 1 ⎯ Unit ns ns ns ns ns CSXn TCLWRL TWRLWRH TWRHCH WRXn TDSWRL TWRHDH DATA OUT DS07-16612-2E 113 MB91460D Series 7.7.8. RDY waitcycle insertion (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter RDY setup time RDY hold time Symbol TRDYS TRDYH Pin name MCLKO RDY MCLKO RDY Value Min 21 0 Max ⎯ ⎯ Unit ns ns MCLKO TRDYS TRDYH RDY 114 DS07-16612-2E MB91460D Series 7.7.9. Bus hold timing (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter MCLKO ↓ to BGRNTX delay time Bus HIZ to BGRNTX ↓ Symbol TCLBGL TCLBGH TAXBGL Pin name MCLKO BGRNTX BGRNTX MCLK* A0 to An RDX, ASX WRXn,WEX CSXn,BAAX Value Min ⎯ ⎯ tCLKT − 6 Max 2 × tCLKT + 5 2 × tCLKT + 2 ⎯ Unit ns ns ns BGRNTX ↑ to Bus drive TBGHAV tCLKT + 8 ⎯ ns Note : BRQ must be kept High until the bus is granted (this is acknowledged by the falling edge of BGRNTX). It must be kept High as long as the bus shall be hold. After releasing the bus (BRQ set to Low) this is acknowledged by the rising edge of BGRNTX. MCLKO BRQ TCLBGL TCLBGH BGRNTX TAXBGL ADDR,RDX,WRX, WEX,CSXn,ASX, MCLKE,MCLKI, BAAX TBGHAV DS07-16612-2E 115 MB91460D Series 7.7.10. Clock relationships (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter MCLKO ↓ to MCLKE (in sleep mode) Symbol TCLML TCLMH Pin name MCLKO MCLKE Value Min ⎯ −1 Max 7 ⎯ Unit ns ns MCLKO TCLML TCLMH MCLKE(sleep) 116 DS07-16612-2E MB91460D Series 7.7.11. DMA transfer (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter MCLKO ↓ to DACKX delay time MCLKO ↓ to DEOP delay time MCLKO ↑ to DACKX delay time (ADDR → delayed CS) MCLKO ↑ to DEOP delay time (ADDR → delayed CS) DREQ setup time DREQ hold time DEOTXn setup time DEOTXn hold time Symbol TCLDAL TCLDAH TCLDEL TCLDEH TCHDAL TCHDEL TDRQS TDRQH TDTXS TDTXH Pin name MCLKO DACKXn MCLKO DEOPn MCLKO DACKXn MCLKO DEOPn MCLKO DREQn MCLKO DREQn MCLKO DEOTXn MCLKO DEOTXn Value Min ⎯ ⎯ ⎯ ⎯ −4 −4 23 0 24 0 Max 9 6 8 9 3 3 ⎯ ⎯ ⎯ ⎯ Unit ns ns ns ns ns ns ns ns ns ns Note : DREQ and DEOTX must be applied for at least 5 × tCLKT to ensure that they are really sampled and evaluated. Under best case conditions (DMA not busy) only setup and hold times are required. DS07-16612-2E 117 MB91460D Series MCLKO TCLDAL TCLDAH DACKX TCLDEL TCLDEH DEOP TCHDAL delayed DACKX TCHDEL delayed DEOP TDRQS TDRQH DREQ TDTXS TDTXH DEOTX 118 DS07-16612-2E MB91460D Series 7.8. External Bus AC Timings at VDD35 = 3.0 to 4.5 V • Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 5 mA - VDD35 = 3.0 V to 4.5 V, Iload = 3 mA - VSS5 = 0 V - Ta = − 40 °C to + 105 °C - Cl = 50 pF - VOL = 0.2 × VDD35 - VOH = 0.8 × VDD35 - EPILR = 0, PILR = 1 (Automotive Level = worst case) 7.8.1. Basic Timing (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter Symbol TCLCH TCHCL TCLCSL TCLCSH TCHCSL TCLASL TCLASH TCLBAL TCLBAH TCLAV MCLKO ASX MCLKO BAAX MCLKO A25 to A0 MCLKO CSXn Pin name MCLKO Value Min 1/2 × tCLKT − 13 1/2 × tCLKT − 13 ⎯ ⎯ − 11 ⎯ ⎯ ⎯ 1 ⎯ Max 1/2 × tCLKT + 13 1/2 × tCLKT + 13 6 7 0 6 9 3 ⎯ 13 Unit ns ns ns ns ns ns ns ns ns ns MCLKO MCLKO ↓ to CSXn delay time MCLKO ↑ to CSXn delay time (Addr → CS delay) MCLKO ↓ to ASX delay time MCLKO ↓ to BAAX delay time MCLKO ↓ to Address valid delay time DS07-16612-2E 119 MB91460D Series TCLCH TCHCL TCYC MCLKO TCLCSL TCLCSH CSXn TCHCSL delayed CSXn TCLASH TCLASL ASX TCLAV ADDRESS TCLBAH TCLBAL BAAX 120 DS07-16612-2E MB91460D Series 7.8.2. Synchronous/Asynchronous read access with external MCLKI input (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter Symbol TCHRL TCHRH TDSRH TRHDX TDSCH TCHDX TCLWRL TCLWRH TCLCSL TCLCSH Pin name MCLKO RDX MCLKI RDX RDX D31 to D0 RDX D31 to D0 MCLKI D31 to D0 MCLKI D31 to D0 MCLKO WRXn MCLKO CSXn Value Min − 12 12 28 0 3 1 ⎯ 0 ⎯ ⎯ Max 0 26 ⎯ ⎯ ⎯ ⎯ 6 ⎯ 6 7 Unit ns ns ns ns ns ns ns ns ns ns MCLKO ↑/MCLKI ↑ to RDX delay time Data valid to RDX ↑ setup time RDX ↑ to Data valid hold time (external MCLKI input) Data valid to MCLKI ↑ setup time MCLKI ↑ to Data valid hold time MCLKO ↓ to WRXn (as byte enable) delay time MCLKO ↓ to CSXn delay time Note: The usage of the external feedback from MCLKO to MCLKI is not recommended. DS07-16612-2E 121 MB91460D Series MCLKO MCLKI TCLCSL TCLCSH CSXn TCLWRL TCLWRH WRXn (as byte enable) TCHRH TCHRL RDX TDSRH TRHDX TDSCH TCHDX DATA IN 122 DS07-16612-2E MB91460D Series 7.8.3. Synchronous/Asynchronous read access with internal MCLKO --> MCLKI feedback (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter MCLKO ↑ to RDX delay time Data valid to RDX ↑ setup time RDX ↑ to Data valid hold time (internal MCLKO → MCLKI / /MCLKI feedback) MCLKO ↓ to WRXn (as byte enable) delay time MCLKO ↓ to CSXn delay time Symbol TCHRL TCHRH TDSRH Pin name MCLKO RDX RDX D31 to D0 RDX D31 to D0 MCLKO WRXn MCLKO CSXn Value Min − 12 −9 29 Max 0 1 ⎯ ⎯ 6 ⎯ 6 7 Unit ns ns ns TRHDX TCLWRL TCLWRH TCLCSL TCLCSH 0 ⎯ 0 ⎯ ⎯ ns ns ns ns ns MCLKO TCLCSL TCLCSH CSXn TCLWRL TCLWRH WRXn (as byte enable) TCHRH TCHRL RDX TDSRH TRHDX DATA IN DS07-16612-2E 123 MB91460D Series 7.8.4. Synchronous write access - byte control type (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter MCLKO ↓ to WEX delay time Data valid to WEX ↓ setup time WEX ↑ to Data valid hold time MCLKO ↓ to WRXn (as byte enable) delay time MCLKO ↓ to CSXn delay time Symbol TCLWL TCLWH TDSWL TWHDH TCLWRL TCLWRH TCLCSL TCLCSH Pin name MCLKO WEX WEX D31 to D0 WEX D31 to D0 MCLKO WRXn MCLKO CSXn Value Min ⎯ 1 − 20 tCLKT − 19 ⎯ 0 ⎯ ⎯ Max 7 ⎯ ⎯ ⎯ 6 ⎯ 6 7 Unit ns ns ns ns ns ns ns ns MCLKO TCLCSL TCLCSH CSXn TCLWRL TCLWRH WRXn (as byte enable) TCLWH TCLWL WEX TDSWL TWHDH DATA OUT MB91460D Series 7.8.5. Synchronous write access - no byte control type (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter MCLKO ↓ to WRXn delay time Data valid to WRXn ↓ setup time WRXn ↑ to Data valid hold time MCLKO ↓ to CSXn delay time Symbol TCLWRL TCLWRH TDSWRL TWRHDH TCLCSL TCLCSH Pin name MCLKO WRXn WRXn D31 to D0 WRXn D31 to D0 MCLKO CSXn Value Min ⎯ 0 − 20 tCLKT − 14 ⎯ ⎯ Max 6 ⎯ ⎯ ⎯ 6 7 Unit ns ns ns ns ns ns MCLKO TCLCSL TCLCSH CSXn TCLWRH TCLWRL WRXn TDSWRL TWRHDH DATA OUT DS07-16612-2E 125 MB91460D Series 7.8.6. Asynchronous write access - byte control type (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter WEX ↓ to WEX ↑ pulse width Data valid to WEX ↓ setup time WEX ↑ to Data valid hold time WEX to WRXn delay time WEX to CSXn delay time Symbol TWLWH TDSWL TWHDH TWRLWL TWHWRH TCLWL TWHCH Pin name WEX WEX D31 to D0 WEX D31 to D0 WEX WRXn WEX CSXn Value Min tCLKT − 2 1/2 × tCLKT − 20 1/2 × tCLKT − 20 ⎯ 1/2 × tCLKT − 7 ⎯ 1/2 × tCLKT − 4 Max ⎯ ⎯ ⎯ 1/2 × tCLKT + 3 ⎯ 1/2 × tCLKT − 1 ⎯ Unit ns ns ns ns ns ns ns CSXn TCLWL TWHCH WRXn (as byte enable) TWRLWL TWLWH TWHWRH WEX TDSWL TWHDH DATA OUT 126 DS07-16612-2E MB91460D Series 7.8.7. Asynchronous write access - no byte control type (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter WRXn ↓ to WRXn ↑ pulse width Data valid to WRXn ↓ setup time WRXn ↑ to Data valid hold time WRXn to CSXn delay time Symbol TWRLWRH TDSWRL TWRHDH TCLWRL TWRHCH Pin name WRXn WRXn D31 to D0 WRXn D31 to D0 WRXn CSXn Value Min tCLKT − 2 1/2 × tCLKT − 21 1/2 × tCLKT − 18 ⎯ 1/2 × tCLKT − 4 Max ⎯ ⎯ ⎯ 1/2 × tCLKT − 1 ⎯ Unit ns ns ns ns ns CSXn TCLWRL TWRLWRH TWRHCH WRXn TDSWRL TWRHDH DATA OUT DS07-16612-2E 127 MB91460D Series 7.8.8. RDY waitcycle insertion (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter RDY setup time RDY hold time Symbol TRDYS TRDYH Pin name MCLKO RDY MCLKO RDY Value Min 37 0 Max ⎯ ⎯ Unit ns ns MCLKO TRDYS TRDYH RDY 128 DS07-16612-2E MB91460D Series 7.8.9. Bus hold timing (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter MCLKO ↓ to BGRNTX delay time Bus HIZ to BGRNTX ↓ Symbol TCLBGL TCLBGH TAXBGL Pin name MCLKO BGRNTX BGRNTX MCLK* A0 to An RDX, ASX WRXn,WEX CSXn,BAAX Value Min ⎯ ⎯ tCLKT + 1 Max 2 × tCLKT + 16 2 × tCLKT + 3 ⎯ Unit ns ns ns BGRNTX ↑ to Bus drive TBGHAV tCLKT + 1 ⎯ ns Note : BRQ must be kept High until the bus is granted (this is acknowledged by the falling edge of BGRNTX). It must be kept High as long as the bus shall be hold. After releasing the bus (BRQ set to Low) this is acknowledged by the rising edge of BGRNTX. MCLKO BRQ TCLBGL TCLBGH BGRNTX TAXBGL ADDR,RDX,WRX, WEX,CSXn,ASX, MCLKE,MCLKI, BAAX TBGHAV DS07-16612-2E 129 MB91460D Series 7.8.10. Clock relationships (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter MCLKO ↓ to MCLKE (in sleep mode) Symbol TCLML TCLMH Pin name MCLKO MCLKE Value Min ⎯ 0 Max 3 ⎯ Unit ns ns MCLKO TCLML TCLMH MCLKE(sleep) 130 DS07-16612-2E MB91460D Series 7.8.11. DMA transfer (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C) Parameter MCLKO ↓ to DACKX delay time MCLKO ↓ to DEOP delay time MCLKO ↑ to DACKX delay time (ADDR → delayed CS) MCLKO ↑ to DEOP delay time (ADDR → delayed CS) DREQ setup time DREQ hold time DEOTXn setup time DEOTXn hold time Symbol TCLDAL TCLDAH TCLDEL TCLDEH TCHDAL TCHDEL TDRQS TDRQH TDTXS TDTXH Pin name MCLKO DACKXn MCLKO DEOPn MCLKO DACKXn MCLKO DEOPn MCLKO DREQn MCLKO DREQn MCLKO DEOTXn MCLKO DEOTXn Value Min ⎯ ⎯ ⎯ ⎯ − 10 − 10 38 0 39 0 Max 7 8 7 11 2 1 ⎯ ⎯ ⎯ ⎯ Unit ns ns ns ns ns ns ns ns ns ns Note : DREQ and DEOTX must be applied for at least 5 × tCLKT to ensure that they are really sampled and evaluated. Under best case conditions (DMA not busy) only setup and hold times are required. DS07-16612-2E 131 MB91460D Series MCLKO TCLDAL TCLDAH DACKX TCLDEL TCLDEH DEOP TCHDAL delayed DACKX TCHDEL delayed DEOP TDRQS TDRQH DREQ TDTXS TDTXH DEOTX 132 DS07-16612-2E MB91460D Series ■ ORDERING INFORMATION Part number MB91F467DAPFVS-GSE2 MB91F467DBPFVS-GSE2 MB91F467DAPVS-GSE2 MB91F467DBPVS-GSE2 208-pin plastic QFP (FPT-208P-M04) Package Remarks not recommended not recommended not recommended Lead-free package DS07-16612-2E 133 MB91460D Series ■ PACKAGE DIMENSION 208-pin plastic QFP Lead pitch Pa ckage width × package length Lead shape Sealing method Mounting height We ight 0.50 mm 28.0 × 28.0 mm Gullwing Plastic mold 3.95 mm MAX 5.71g Low heat resistance type (FPT-208P-M04) Remar k 208-pin plastic QFP (FPT -208P-M04) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 30.60±0.20(1.205±.008)SQ * 28.00±0.10(1.102±.004)SQ 0.17 156 105 .007 104 +0.03 –0.08 +.001 –.003 157 0.08(.003) Details of "A" par t 3.75 .148 +0.20 –0.30 +.008 –.012 (Mounting height) 0.40 INDEX 0 ˚ ~8 ˚ 53 .016 (Stand off) +0.10 –0.15 +.004 –.006 208 "A" LEAD No . 1 52 0.50(.020) 0.22±0.05 (.009±.002) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) 0.08(.003) M C 2003-2008 FUJITSU MICROELECTRONICS LIMITED F208020S-c-3-5 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 134 DS07-16612-2E MB91460D Series ■ REVISION HISTORY Version 2.0 Date 2007-09-04 Initial version Revision history table added Fixed PDF generation problem before section “AD converter characteristics” Absolute maximum ratings: Smoothing capacitor size at VCC18C changed to “typ 4.7uF” Output voltage 2 is max. VDD35 Recommended operating conditions: Power supply slew rate fixed Exchanged the sequence of device names into “MB91F465DA, MB91F467DA” where they appeare on one line Moved revision history to the end of file Features: Added Clock Monitor Corrected VCC18C pin number in table “Power supply/Ground pins” pg.14 Remark 2.1 2007-10-08 2.2 2007-10-16 Electrical characteristics: Added section 7.FLASH memory program/erase characteristics 2.3 2007-10-22 DC characterisitcs: Corrected ICCH in STOP + RTC 100kHz mode and ILV (Icc of low volt detection) max. value 2.4 2007-10-25 FLASH memory program/erase characteristics: Typo fixed in note *1 Recommended operating conditions: Corrected text for smoothing capacitor at VCC18C pin Naming inconsistency AVSS / AVSS5 fixed Features: added Up/Down counter Product lineup: fixed number of interrupt channels Handling devices: changed the notes about external clock supply and removed section “Single phase clock supply” Clock timing: removed “Single phase clock supply” from freq. table DC characterisitcs: IIL = +/- 3 uA at 105 deg.C IO CIRCUIT TYPE: Corrected oscillator pin block diagrams ELECTRICAL CHARACTERISTICS: re-arranged section sequence Fixed typos in ALARM comparator spec. Added MB91F467DB (called F467Dx if the text item is for bot revisions) Corrected IO-MAP according to latest proofread on F460G series Various corrections after proofread by FJ Added MEMO and DISCLAIMER AC-Characteristics: Replaced “rising”/”falling” with arrow-up/arrow-down 2.5 2008-1-11 2.6 2.7 2008-02-04 2008-02-18 DS07-16612-2E 135 MB91460D Series Version Date Remark Corrected missing bullets on PDF pages 2+3 Pin Assignment, Block Diagram: Corrected naming and assignments of TTG inputs, SGO and DACKX0 Notes on PS register: Re-formatted for better understanding ADC Characteristics: Offset between ADC channels is max. 4 LSB DC Characteristics: Added ILVI (ICC of internal low voltage detection), renamed ILV into ILVE (for external low voltage detection) AC Characteristics for external bus: Added notes that the usage of external feedback MCLKO --> MCLKI is not recommended. Flash parallel programming mode: Added notes about the pins to be set fix-0 / fix-1 (MD_2:0,...) Added section about the wait times after power on Flash operation modes: Added note about the BootROM fuction entry address for operation mode switch. Package Dimension: Updated package drawing All pages: Corrected typos and formatting bugs found by FJ proofread EMBEDDED PROGRAM/DATA MEMORY (FLASH): Corrected "The operation mode of the flash memory ..." instead of "of the MCU" Resources,Product lineup: Added Supply Supervisor (Low voltage detection) DC Characteristics: Updated pull-up/pull-down resistance values, updated and re-numbered the table footnotes Interrupt Vector Table: corrected the footnotes Flash Security: Corrected the sector assignments of FSV1/FSV2 bits Electrical Characteristics: removed the note that analog input/output pins cannot accept +B signal input. Ordering information: updated the part numbers All pages: Kilobytes are now written with "K" 2.8 2008-06-20 2.9 2008-06-30 2.10 2008-08-04 2.11 2008-08-18 136 DS07-16612-2E MB91460D Series ■ MEMO AND DISCLAIMER MEMO DS07-16612-2E 137 MB91460D Series MEMO 138 DS07-16612-2E MB91460D Series MEMO DS07-16612-2E 139 MB91460D Series FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department