MB91F475

FUJITSU SEMICONDUCTOR DATA SHEET DS07-16901-2E 32-bit Microcontrollers CMOS FR60 MB91470/480 Series MB91482/F475/F478/F479/F487/ MB91FV470 ■ DESCRIPTION The MB91470/480 series is Fujitsu's general-purpose 32-bit RISC microcontroller, which is designed for embedded control applications that require high-speed processing performance. This series uses the FR60 CPU, which is compatible with the FR* family of CPUs. * : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited. ■ FEATURES • FR60 CPU • 32-bit RISC, load/store architecture, five-stage pipeline • Operating frequency of 80 MHz (PLL clock multiplied) • 16-bit fixed-length instructions (basic instructions) • Instruction execution speed : one instruction per cycle • Memory-to-memory transfer, bit processing, barrel shift instructions, etc. : instructions suitable for embedded applications • Function entry and exit instructions, multi load/store instructions of register contents : instructions compatible with C language. • Register interlock function to facilitate assembly-language coding • Built-in multiplier/instruction-level support • Signed 32-bit multiplication : 5 cycles • Signed 16-bit multiplication : 3 cycles • Interrupts (save PC and PS) : 6 cycles, 16 priority levels • Harvard architecture allowing program access and data access to be executed simultaneously • Instructions compatible with the FR family (Continued) Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development. Copyright©2006-2007 FUJITSU LIMITED All rights reserved MB91470/480 Series • Built-in Peripheral functions • Combinations of built-in Flash/ROM and RAM capacities MB91470 series 144 pins Flash memory product 256 Kbytes/16 Kbytes 384 Kbytes/24 Kbytes 512 Kbytes/32 Kbytes • • • • • • • • MB91F475 MB91F478 MB91F479 MASK ROM product ⎯ ⎯ ⎯ MB91480 series 100 pins Flash memory product ⎯ ⎯ MB91F487 MASK ROM product MB91482 ⎯ ⎯ • • • • I/O ports NMI (Non Maskable Interrupt) External interrupts Bit search module (for REALOS) Function to search for the position of the first bit that has changed from 1 to 0 in a word starting from the MSB 16-bit reload timers Timing generator 8/16-bit PPG timers Multi-function timer • 16-bit free-run Timer • Input capture (Linked to free-run timer) • Output compare (Linked to free-run timer) • A/D start up compare (Linked to free-run timer) • Wave form generator Various wave forms are generated by using output compare output, 16-bit PPG timer and 16-bit dead timer. Base timer Only one timer function can be selected from the 16-bit PWM timer, 16-bit PPG timer, 16/32-bit reload timer, and 16/32-bit PWC timer. 8/16-bit up/down counter Multi-function serial interface • Full-duplex double buffer • With 16-byte FIFO • Asynchronous (start-stop synchronization) communication, clock synchronous communication, I2C* standard mode (Max 100 kbps), I2C high-speed mode (selectable various modes at maximum of 400 kbps) • Selectable parity On/Off • Each channel has built-in baud rate generator • Error detection function for parity, frame and overrun errors • External clock can be used as transfer clock • With I2C function 8/10-bit A/D Converter (Successive comparison type) • Resolution : 8-bit or 10-bit resolution selectable • Conversion Time : 1.2 µs (minimum conversion time for 33 MHz system clock) 1.2 µs (minimum conversion time for 40 MHz system clock) (Continued) 2 MB91470/480 Series (Continued) • 12-bit A/D Converter (successive approximation type) • Resolution : 12 bits • Conversion Time : 2.0 µs (minimum conversion time for 33 MHz system clock) 2.2 µs (minimum conversion time for 40 MHz system clock) • Differential input mode is available. • Clock monitor • Peripheral clock (CLKP) divided by 2/4/8/16/32/64/128/256 can be output. • Multiplication and Addition Calculator • RAM : Instruction RAM (I-RAM) 256 × 16-bit Factor RAM (X-RAM) 64 × 32-bit Variable RAM (Y-RAM) 64 × 32-bit • High-speed multiplication and addition (seven-stage pipeline processing) • Product addition (32-bit × 32-bit + 72-bit) • Operation result is extracted rounded from 72 bits to 32 bits or 72-bit result data reading. • DMAC (DMA Controller) • Transfers can be started by software or by interrupts from the built-in peripherals. • Wild register • Instructions or data located at a target address can be replaced (in the built-in Flash/ROM area only) . • External bus interface • Maximum operating frequency of 40 MHz • 16-bit address full output (64 Kbytes space) capability • 8/16-bit data output • Use of unused data/address pins as general-purpose I/O ports • Totally independent 3-area chip select outputs that can be set at minimum of 64 Kbytes. • Support of interface for various memory (SRAM, ROM/Flash) • Basic bus cycle : 2 cycles • Automatic wait cycle generator that can be programmed for each area and can insert waits • External wait cycle using RDY input • Other Features • Watchdog timer • Low-power consumption modes • Sleep/stop function • CMOS technologies : 0.18 µm • Power supply : Single power supply (VCC = 4.0 V to 5.5 V) * : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. 3 MB91470/480 Series ■ PRODUCT LINEUP Characteristics Pin number Built-in Flash/ROM capacity Built-in RAM capacity External bus I/O ports External interrupts Reload timer Timing generator PPG Multi-function timer Free-run timer OCU ICU A/D activation compare Wave form generator Base timer Up/down counter Multi-function serial interface 8/10-bit A/D converter 12-bit A/D converter Clock monitor Multiplication and addition calculator DMAC Wild register Debug function MB91470/480 series common EVA MB91FV470 224 pins 512 Kbytes (Flash) 40 Kbytes Yes 160 NMI 16 channels 2 channels 2 units 8-bit × 16 channels 16-bit × 8 channels 2 units 6 channels 12 channels 8 channels 6 channels 12 channels 6 channels 2 channels 6 units 4 channels × 2 units 16 channels × 1 unit 4 channels × 2 units 1 unit 1 unit 5 channels 16 channels DSU4 MB91470 series MB91F475 MB91F478 144 pins 256 Kbytes 384 Kbytes (Flash) (Flash) 16 Kbytes 24 Kbytes Yes 113 NMI 10 channels 2 channels 1 unit 8-bit × 8 channels 16-bit × 4 channels 1 unit 3 channels 6 channels 4 channels 3 channels 6 channels 4 channels 1 channel 6 units 12 channels × 1 unit 4 channels × 2 units ⎯ 1 unit 5 channels 16 channels ⎯ 512 Kbytes (Flash) 32 Kbytes MB91F479 MB91480 series MB91F487 512 Kbytes (Flash) 32 Kbytes ⎯ 77 NMI 10 channels 2 channels 2 units 8-bit × 16 channels 16-bit × 8 channels 2 units 6 channels 12 channels 8 channels 6 channels 12 channels 4 channels ⎯ 3 units 4 channels × 2 units 10 channels × 1 unit ⎯ 1 unit 1 unit 5 channels 16 channels ⎯ MB91482 256 Kbytes (ROM) 16 Kbytes 100 pins 4 MB91470/480 Series ■ PACKAGE AND CORRESPONDING PRODUCTS Series name Package FPT-100P-M20 (LQFP-0.50 mm) FPT-144P-M12 (LQFP-0.40 mm) BGA-144P-M06 (PFBGA-0.80 mm) : Supported Note : For details of each package, refer to “■ PACKAGE DIMENSIONS”. MB91470 series MB91F475 MB91F478 MB91F479 ⎯ ⎯ ⎯ ⎯ ⎯ MB91F487 MB91480 series MB91482 5 MB91470/480 Series ■ PIN ASSIGNMENT • LQFP-144 (MB91470 series) (TOP VIEW) VSS P50/CS0X P37/A15 P36/A14 P35/A13 P34/A12 P33/A11 P32/A10 P31/A09 P30/A08 P27/A07 P26/A06 P25/A05 P24/A04 P23/A03 P22/A02 P21/A01 P20/A00 VCC VSS P17/D31 P16/D30 P15/D29 P14/D28 P13/D27 P12/D26 P11/D25 P10/D24 P07/D23 P06/D22 P05/D21 P04/D20 P03/D19 P02/D18 P01/D17 P00/D16 VCC P51/CS1X P52/CS2X P53/ASX P54/RDX P55/WR0X P56/WR1X P60/SYSCLK P61/RDY PJ0/TIN0 PJ1/TOUT0 PJ2/TIN1 PJ3/TOUT1 PJ4/TIN2 PJ5/TOUT2 PJ6/TIN3 PJ7/TOUT3 VCC VSS P80/INT0 P81/INT1 P82/INT2 P83/INT3 P84/INT4/PPG4 P85/INT5/PPG5 P86/INT6/PPG6 P87/INT7/PPG7 P90/INT8 P91/INT9 NMIX PL0/AIN0 PL1/BIN0 PL2/ZIN0 INITX VCC VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PH5/SOT3 PH4/SIN3 PH3/SCK3 PH2/SOT2 PH1/SIN2 PH0/SCK2 PG5/SOT1 PG4/SIN1 PG3/SCK1 PG2/SOT0 PG1/SIN0 PG0/SCK0 AVSS10 AVRH2 AVCC10 PD3/AN2-11 PD2/AN2-10 PD1/AN2-9 PD0/AN2-8 PC7/AN2-7 PC6/AN2-6 PC5/AN2-5/SOT5 PC4/AN2-4/SIN5 PC3/AN2-3/SCK5 PC2/AN2-2/SOT4 PC1/AN2-1/SIN4 PC0/AN2-0/SCK4 VCC VSS PE7/AN4-3/AN4-1N PE6/AN4-2/AN4-1P PE5/AN4-1/AN4-0N PE4/AN4-0/AN4-0P AVRH4 AVCC12 AVRH3 6 VCC PQ0/RTO0 PQ1/RTO1 PQ2/RTO2 PQ3/RTO3 PQ4/RTO4 PQ5/RTO5 VCC VSS PP0/IC0 PP1/IC1 PP2/IC2 PP3/IC3 MD2 MD1 MD0 X0 X1 VSS PP4/CKI0 PP5/DTTI0 C VSS VCC PM0/PPG0 PM1/PPG1 PM2/PPG2 PM3/PPG3 PA2/ADTG2 PA3/ADTG3 PA4/ADTG4 PE0/AN3-0/AN3-0P PE1/AN3-1/AN3-0N PE2/AN3-2/AN3-1P PE3/AN3-3/AN3-1N AVSS12 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 (FPT-144P-M12) MB91470/480 Series • PFBGA-144 (MB91470 series) (TOP VIEW) ▼ Index A B C D E F G H J K L M N 1 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 48 49 50 51 52 53 54 55 56 57 58 59 14 2 3 47 88 89 90 91 92 93 94 95 96 97 60 15 3 4 46 87 120 121 122 123 124 125 126 127 98 61 16 4 128 99 62 17 5 129 100 63 18 6 130 101 64 19 7 131 102 65 20 8 132 103 66 21 9 5 45 86 119 144 6 44 85 118 143 7 43 84 117 142 8 42 83 116 141 9 41 82 115 140 10 40 81 114 139 138 137 136 135 134 133 104 67 22 10 11 39 80 113 112 111 110 109 108 107 106 105 68 23 11 12 38 79 78 77 76 75 74 73 72 71 70 69 24 12 13 37 36 35 34 33 32 31 30 29 28 27 26 25 13 (BGA-144P-M06) 7 MB91470/480 Series • LQFP-100 (MB91480 series) (TOP VIEW) VSS P85/INT5/PPG5 P84INT4/PPG4 P83/INT3 P82/INT2 P81/INT1 P80/INT0 PJ7/TOUT3 PJ6/TIN3 PJ5/TOUT2 PJ4/TIN2 PJ3/TOUT1 PJ2/TIN1 PJ1/TOUT0 PJ0/TIN0 PH2/SOT2 PH1/SIN2 PH0/SCK2 PG5/SOT1 PG4/SIN1 PG3/SCK1 PG2/SOT0 PG1/SIN0 PG0/SCK0 VCC VCC P86/INT6/PPG6 P87/INT7/PPG7 P90/INT8/PPG8 P91/INT9/PPG9 NMIX PM0/PPG0 PM1/PPG1 PM2/PPG2 PM3/PPG3 PF0/CLKPOUT PP0/IC0 PP1/IC1 PP2/IC2 PP3/IC3 PP4/CKI0 PP5/DTTI0 VSS VCC PQ0/RTO0 PQ1/RTO1 PQ2/RTO2 PQ3/RTO3 PQ4/RTO4 PQ5/RTO5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS PA1/ADTG1 PA0/ADTG0 PB7/AN1-3 PB6/AN1-2 PB5/AN1-1 PB4/AN1-0 PB3/AN0-3 PB2/AN0-2 PB1/AN0-1 PB0/AN0-0 AVSS10 AVRH2 AVCC10 PD1/AN2-9 PD0/AN2-8 PC7/AN2-7 PC6/AN2-6 PC5/AN2-5 PC4/AN2-4 PC3/AN2-3 PC2/AN2-2 PC1/AN2-1 PC0/AN2-0 VCC 8 PS0/RTO6 PS1/RTO7 PS2/RTO8 PS3/RTO9 PS4/RTO10 PS5/RTO11 VCC VCC VSS C PR0/IC4 PR1/IC5 PR2/IC6 PR3/IC7 PR4/CKI1 PR5/DTTI1 MD2 MD1 MD0 X0 X1 VSS INITX PA2/ADTG2 VSS 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (FPT-100P-M20) MB91470/480 Series ■ PIN DESCRIPTIONS Pin no. MB91470 series LQFP144 MB91480 I/O series Pin name circuit type* PFBGA- LQFP144 100 Function 50 M6 42 MD2 H, K Mode pin 2 This pin sets the basic operating mode. Connect this pin to either VCC pin or VSS pin. Use circuit type K on the Flash memory model. Mode pin 1 This pin sets the basic operating mode. Connect this pin to either VCC pin or VSS pin. Use circuit type K on the Flash memory model. Mode pin 0 This pin sets the basic operating mode. Connect this pin to either VCC pin or VSS pin. Use circuit type K on the Flash memory model. Clock (oscillation) input Clock (oscillation) output External reset input NMI (Non Maskable Interrupt) input Bit 16 of external data bus I/O pin General-purpose I/O port Bit 17 of external data bus I/O pin General-purpose I/O port Bit 18 of external data bus I/O pin General-purpose I/O port Bit 19 of external data bus I/O pin General-purpose I/O port Bit 20 of external data bus I/O pin General-purpose I/O port Bit 21 of external data bus I/O pin General-purpose I/O port Bit 22 of external data bus I/O pin General-purpose I/O port Bit 23 of external data bus I/O pin General-purpose I/O port Bit 24 of external data bus I/O pin General-purpose I/O port (Continued) 9 51 N6 43 MD1 H, K 52 K5 44 MD0 H, K 53 54 34 30 109 110 111 112 113 114 115 116 117 L6 K6 L1 J4 A12 B12 A11 B11 C12 B10 A10 C11 C10 45 46 48 6 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ X0 X1 INITX NMIX D16 P00 D17 P01 D18 P02 D19 P03 D20 P04 D21 P05 D22 P06 D23 P07 D24 P10 A A I H C C C C C C C C C MB91470/480 Series Pin no. MB91470 series LQFP144 118 119 120 121 122 123 124 127 128 129 130 131 132 133 134 135 MB91480 I/O series Pin name circuit type* PFBGA- LQFP144 100 B9 A9 D10 C9 B8 A8 D9 A7 B7 C7 D7 A6 B6 C6 D6 A5 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ D25 P11 D26 P12 D27 P13 D28 P14 D29 P15 D30 P16 D31 P17 A00 P20 A01 P21 A02 P22 A03 P23 A04 P24 A05 P25 A06 P26 A07 P27 A08 P30 C C C C C C C C C C C C C C C C Function Bit 25 of external data bus I/O pin General-purpose I/O port Bit 26 of external data bus I/O pin General-purpose I/O port Bit 27 of external data bus I/O pin General-purpose I/O port Bit 28 of external data bus I/O pin General-purpose I/O port Bit 29 of external data bus I/O pin General-purpose I/O port Bit 30 of external data bus I/O pin General-purpose I/O port Bit 31 of external data bus I/O pin General-purpose I/O port Bit 0 of external address bus output pin General-purpose I/O port Bit 1 of external address bus output pin General-purpose I/O port Bit 2 of external address bus output pin General-purpose I/O port Bit 3 of external address bus output pin General-purpose I/O port Bit 4 of external address bus output pin General-purpose I/O port Bit 5 of external address bus output pin General-purpose I/O port Bit 6 of external address bus output pin General-purpose I/O port Bit 7 of external address bus output pin General-purpose I/O port Bit 8 of external address bus output pin General-purpose I/O port (Continued) 10 MB91470/480 Series Pin no. MB91470 series LQFP144 136 137 138 139 140 141 142 143 2 3 4 5 MB91480 I/O series Pin name circuit type* PFBGA- LQFP144 100 B5 C5 D5 A4 B4 C4 A3 A2 B2 C1 C2 B3 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ A09 P31 A10 P32 A11 P33 A12 P34 A13 P35 A14 P36 A15 P37 CS0X P50 CS1X P51 CS2X P52 ASX P53 RDX P54 WR0X P55 7 D1 ⎯ WR1X P56 8 C3 ⎯ SYSCLK P60 C C C C C C C C C C C C C C Function Bit 9 of external address bus output pin General-purpose I/O port Bit 10 of external address bus output pin General-purpose I/O port Bit 11 of external address bus output pin General-purpose I/O port Bit 12 of external address bus output pin General-purpose I/O port Bit 13 of external address bus output pin General-purpose I/O port Bit 14 of external address bus output pin General-purpose I/O port Bit 15 of external address bus output pin General-purpose I/O port External chip select 0 output General-purpose I/O port External chip select 1 output General-purpose I/O port External chip select 2 output General-purpose I/O port External address strobe output General-purpose I/O port External read strobe output General-purpose I/O port External write strobe output Corresponding to bit 31 to bit 24 of external data bus I/O General-purpose I/O port External write strobe output Corresponding to bit 23 to bit 16 of external data bus I/O General-purpose I/O port External clock output General-purpose I/O port (Continued) 6 D2 ⎯ C 11 MB91470/480 Series Pin no. MB91470 series LQFP144 9 20 21 22 23 MB91480 I/O series Pin name circuit type* PFBGA- LQFP144 100 D3 G2 G3 G4 H1 ⎯ 94 95 96 97 RDY P61 INT0 P80 INT1 P81 INT2 P82 INT3 P83 INT4 24 H2 98 PPG4 P84 INT5 25 H3 99 PPG5 P85 INT6 26 H4 2 PPG6 P86 INT7 27 J1 3 PPG7 P87 INT8 28 J2 4 PPG8 P90 INT9 29 J3 5 PPG9 P91 INT10 ⎯ ⎯ ⎯ PPG10 P92 D D D D D D D C D D D D External ready input General-purpose I/O port External interrupt 0 input General-purpose I/O port External interrupt 1 input General-purpose I/O port External interrupt 2 input General-purpose I/O port External interrupt 3 input General-purpose I/O port External interrupt 4 input Output of PPG timer 4 General-purpose I/O port External interrupt 5 input Output of PPG timer 5 General-purpose I/O port External interrupt 6 input Output of PPG timer 6 General-purpose I/O port External interrupt 7 input Output of PPG timer 7 General-purpose I/O port External interrupt 8 input Output of PPG timer 8 (MB91480 series only) General-purpose I/O port External interrupt 9 input Output of PPG timer 9 (MB91480 series only) General-purpose I/O port External interrupt 10 input Output of PPG timer 10 General-purpose I/O port (Continued) Function 12 MB91470/480 Series Pin no. MB91470 series LQFP144 ⎯ MB91480 I/O series Pin name circuit type* PFBGA- LQFP144 100 INT11 ⎯ ⎯ PPG11 P93 INT12 ⎯ ⎯ ⎯ PPG12 P94 INT13 ⎯ ⎯ ⎯ PPG13 P95 INT14 ⎯ ⎯ ⎯ PPG14 P96 INT15 ⎯ ⎯ ⎯ PPG15 P97 ⎯ ⎯ 65 66 67 ⎯ ⎯ ⎯ ⎯ ⎯ L9 K9 N10 ⎯ ⎯ ⎯ 73 74 49 ⎯ ⎯ 65 66 67 ADTG0 PA0 ADTG1 PA1 ADTG2 PA2 ADTG3 PA3 ADTG4 PA4 AN0-0 PB0 AN0-1 PB1 AN0-2 PB2 D D D D D G G G D D D D D Output of PPG timer 11 General-purpose I/O port External interrupt 12 input Output of PPG timer 12 General-purpose I/O port External interrupt 13 input Output of PPG timer 13 General-purpose I/O port External interrupt 14 input Output of PPG timer 14 General-purpose I/O port External interrupt 15 input Output of PPG timer 15 General-purpose I/O port External trigger input of 8/10-bit A/D converter 0 General-purpose I/O port External trigger input of 8/10-bit A/D converter 1 General-purpose I/O port External trigger input of 8/10-bit A/D converter 2 General-purpose I/O port External trigger input of 12-bit A/D converter 3 General-purpose I/O port External trigger input of 12-bit A/D converter 4 General-purpose I/O port Analog 0 input of 8/10-bit A/D converter 0 General-purpose I/O port Analog 1 input of 8/10-bit A/D converter 0 General-purpose I/O port Analog 2 input of 8/10-bit A/D converter 0 General-purpose I/O port (Continued) Function External interrupt 11 input 13 MB91470/480 Series Pin no. MB91470 series LQFP144 ⎯ ⎯ ⎯ ⎯ ⎯ MB91480 I/O series Pin name circuit type* PFBGA- LQFP144 100 ⎯ ⎯ ⎯ ⎯ ⎯ 68 69 70 71 72 AN0-3 PB3 AN1-0 PB4 AN1-1 PB5 AN1-2 PB6 AN1-3 PB7 AN2-0 82 J12 52 SCK4 PC0 AN2-1 83 J13 53 SIN4 PC1 AN2-2 84 K10 54 SOT4 PC2 AN2-3 85 J11 55 SCK5 PC3 AN2-4 86 H12 56 SIN5 PC4 AN2-5 87 H13 57 SOT5 PC5 88 J10 58 AN2-6 PC6 G G G G G G G G G G G G Function Analog 3 input of 8/10-bit A/D converter 0 General-purpose I/O port Analog 0 input of 8/10-bit A/D converter 1 General-purpose I/O port Analog 1 input of 8/10-bit A/D converter 1 General-purpose I/O port Analog 2 input of 8/10-bit A/D converter 1 General-purpose I/O port Analog 3 input of 8/10-bit A/D converter 1 General-purpose I/O port Analog 0 input of 8/10-bit A/D converter 2 Clock I/O of multi-function serial interface 4 (not used in I2C mode) (MB91470 series only) General-purpose I/O port Analog 1 input of 8/10-bit A/D converter 2 Data input of multi-function serial interface 4 (not used in I2C mode) (MB91470 series only) General-purpose I/O port Analog 2 input of 8/10-bit A/D converter 2 Data output of multi-function serial interface 4 (MB91470 series only) General-purpose I/O port Analog 3 input of 8/10-bit A/D converter 2 Clock I/O of multi-function serial interface 5 (MB91470 series only) General-purpose I/O port Analog 4 input of 8/10-bit A/D converter 2 Data input of multi-function serial interface 5 (not used in I2C mode) (MB91470 series only) General-purpose I/O port Analog 5 input of 8/10-bit A/D converter 2 Data output of multi-function serial interface 5 (MB91470 series only) General-purpose I/O port Analog 6 input of 8/10-bit A/D converter 2 General-purpose I/O port (Continued) 14 MB91470/480 Series Pin no. MB91470 series LQFP144 89 90 91 92 93 MB91480 I/O series Pin name circuit type* PFBGA- LQFP144 100 H11 H10 G13 G12 G11 59 60 61 ⎯ ⎯ AN2-7 PC7 AN2-8 PD0 AN2-9 PD1 AN2-10 PD2 AN2-11 PD3 AN3-0/ AN3-0P PE0 AN3-1/ AN3-0N PE1 AN3-2/ AN3-1P PE2 AN3-3/ AN3-1N PE3 AN4-0/ AN4-0P PE4 AN4-1/ AN4-0N PE5 G G G G G Function Analog 7 input of 8/10-bit A/D converter 2 General-purpose I/O port Analog 8 input of 8/10-bit A/D converter 2 General-purpose I/O port Analog 9 input of 8/10-bit A/D converter 2 General-purpose I/O port Analog 10 input of 8/10-bit A/D converter 2 General-purpose I/O port Analog 11 input of 8/10-bit A/D converter 2 General-purpose I/O port 12-bit A/D converter 3 analog 0 input (in single input mode) 12-bit A/D converter 3 analog 0 ( + ) side input (in differential input mode) General-purpose I/O port 12-bit A/D converter 3 analog 1 input (in single input mode) 12-bit A/D converter 3 analog 0 ( − ) side input (in differential input mode) General-purpose I/O port 12-bit A/D converter 3 analog 2 input (in single input mode) 12-bit A/D converter 3 analog 1 ( + ) side input (in differential input mode) General-purpose I/O port 12-bit A/D converter 3 analog 3 input (in single input mode) 12-bit A/D converter 3 analog 1 ( − ) side input (in differential input mode) General-purpose I/O port 12-bit A/D converter 4 analog 0 input (in single input mode) 12-bit A/D converter 4 analog 0 ( + ) side input (in differential input mode) General-purpose I/O port 12-bit A/D converter 4 analog 1 input (in single input mode) 12-bit A/D converter 4 analog 0 ( − ) side input (in differential input mode) General-purpose I/O port (Continued) 68 M10 ⎯ G 69 L10 ⎯ G 70 N11 ⎯ G 71 N12 ⎯ G 76 L12 ⎯ G 77 M11 ⎯ G 15 MB91470/480 Series Pin no. MB91470 series LQFP144 MB91480 I/O series Pin name circuit type* PFBGA- LQFP144 100 AN4-2/ AN4-1P PE6 AN4-3/ AN4-1N PE7 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 97 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ F11 11 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 77 CLKPOUT PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 SCK0 PG0 SIN0 PG1 99 100 E13 E12 79 80 SOT0 PG2 SCK1 PG3 SIN1 PG4 102 103 E10 D13 82 83 SOT1 PG5 SCK2 PH0 D D D D D D D D D D D D D Function 78 K12 ⎯ G 12-bit A/D converter 4 analog 2 input (in single input mode) 12-bit A/D converter 4 analog 1 ( + ) side input (in differential input mode) General-purpose I/O port 12-bit A/D converter 4 analog 3 input (in single input mode) 12-bit A/D converter 4 analog 1 ( − ) side input (in differential input mode) General-purpose I/O port Clock monitor output General-purpose I/O port General-purpose I/O port General-purpose I/O port General-purpose I/O port General-purpose I/O port General-purpose I/O port General-purpose I/O port General-purpose I/O port Clock I/O of multi-function serial interface 0 General-purpose I/O port Data input of multi-function serial interface 0 (not used in I2C mode) General-purpose I/O port Data output of multi-function serial interface 0 General-purpose I/O port Clock I/O of multi-function serial interface 1 General-purpose I/O port Data input of multi-function serial interface 1 (not used in I2C mode) General-purpose I/O port Data output of multi-function serial interface 1 General-purpose I/O port Clock I/O of multi-function serial interface 2 General-purpose I/O port (Continued) 79 K13 ⎯ G 98 F10 78 D 101 E11 81 D 16 MB91470/480 Series Pin no. MB91470 series LQFP144 104 MB91480 I/O series Pin name circuit type* PFBGA- LQFP144 100 D12 84 SIN2 PH1 105 106 D11 C13 85 ⎯ SOT2 PH2 SCK3 PH3 SIN3 PH4 108 10 11 12 13 14 15 16 17 31 32 A13 E2 E1 D4 E3 F2 F1 E4 F3 K1 K2 ⎯ 86 87 88 89 90 91 92 93 ⎯ ⎯ SOT3 PH5 TIN0 PJ0 TOUT0 PJ1 TIN1 PJ2 TOUT1 PJ3 TIN2 PJ4 TOUT2 PJ5 TIN3 PJ6 TOUT3 PJ7 AIN0 PL0 BIN0 PL1 D D D D D D D D D D D D D D Function Data input of multi-function serial interface 2 (not used in I2C mode) General-purpose I/O port Data output of multi-function serial interface 2 General-purpose I/O port Clock I/O of multi-function serial interface 3 General-purpose I/O port Data input of multi-function serial interface 3 (not used in I2C mode) General-purpose I/O port Data output of multi-function serial interface 3 General-purpose I/O port Base timer 0 input General-purpose I/O port Base timer 0 output General-purpose I/O port Base timer 1 input General-purpose I/O port Base timer 1 output General-purpose I/O port Base timer 2 input General-purpose I/O port Base timer 2 output General-purpose I/O port Base timer 3 input General-purpose I/O port Base timer 3 output General-purpose I/O port 8/16-bit up count input pin for up/down counter 0 General-purpose I/O port 8/16-bit down count input pin for up/down counter 0 General-purpose I/O port (Continued) 107 B13 ⎯ D 17 MB91470/480 Series Pin no. MB91470 series LQFP144 33 61 62 63 64 46 47 48 49 56 MB91480 I/O series Pin name circuit type* PFBGA- LQFP144 100 K3 L8 K8 N9 M9 M5 N5 K4 L5 M7 ⎯ 7 8 9 10 12 13 14 15 16 ZIN0 PL2 PPG0 PM0 PPG1 PM1 PPG2 PM2 PPG3 PM3 IC0 PP0 IC1 PP1 IC2 PP2 IC3 PP3 CKI0 PP4 DTTI0 PP5 38 39 40 41 M2 N3 M3 L2 20 21 22 23 RTO0 PQ0 RTO1 PQ1 RTO2 PQ2 RTO3 PQ3 J J J J D D D D D D D D D D Function 8/16-bit reset input pin for up/down counter 0 General-purpose I/O port Output of PPG timer 0 General-purpose I/O port Output of PPG timer 1 General-purpose I/O port Output of PPG timer 2 General-purpose I/O port Output of PPG timer 3 General-purpose I/O port Trigger input of input capture 0 General-purpose I/O port Trigger input of input capture 1 General-purpose I/O port Trigger input of input capture 2 General-purpose I/O port Trigger input of input capture 3 General-purpose I/O port External clock input pin of free-run timer ch.0 to ch.2 General-purpose I/O port Input signal controlling wave form generator outputs RTO0 to RTO5 of multi-function timer 0 General-purpose I/O port Wave form generator output of multi-function timer 0 General-purpose I/O port Wave form generator output of multi-function timer 0 General-purpose I/O port Wave form generator output of multi-function timer 0 General-purpose I/O port Wave form generator output of multi-function timer 0 General-purpose I/O port (Continued) 57 L7 17 D 18 MB91470/480 Series (Continued) Pin no. MB91470 series LQFP144 42 43 ⎯ ⎯ ⎯ ⎯ ⎯ MB91480 I/O series Pin name circuit type* PFBGA- LQFP144 100 M4 N4 ⎯ ⎯ ⎯ ⎯ ⎯ 24 25 36 37 38 39 40 RTO4 PQ4 RTO5 PQ5 IC4 PR0 IC5 PR1 IC6 PR2 IC7 PR3 CKI1 PR4 DTTI1 PR5 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 26 27 28 29 30 31 RTO6 PS0 RTO7 PS1 RTO8 PS2 RTO9 PS3 RTO10 PS4 RTO11 PS5 J J J J J J J J D D D D D Function Wave form generator output of multi-function timer 0 General-purpose I/O port Wave form generator output of multi-function timer 0 General-purpose I/O port Trigger input of input capture 4 General-purpose I/O port Trigger input of input capture 5 General-purpose I/O port Trigger input of input capture 6 General-purpose I/O port Trigger input of input capture 7 General-purpose I/O port External clock input pin of free-run timer ch.3 to ch.5 General-purpose I/O port Input signal controlling wave form generator outputs RTO6 to RTO11 of multi-function timer 1 General-purpose I/O port Wave form generator output of multi-function timer 1 General-purpose I/O port Wave form generator output of multi-function timer 1 General-purpose I/O port Wave form generator output of multi-function timer 1 General-purpose I/O port Wave form generator output of multi-function timer 1 General-purpose I/O port Wave form generator output of multi-function timer 1 General-purpose I/O port Wave form generator output of multi-function timer 1 General-purpose I/O port ⎯ ⎯ 41 D * : Refer to “■ I/O CIRCUIT TYPE” for I/O circuit type. 19 MB91470/480 Series Power supply pins and GND pins Pin number MB91470 series LQFP144 1 18 35 37 44 60 81 126 19 36 45 55 59 80 125 144 58 94 96 74 72 ⎯ ⎯ 95 73 75 PFBGA144 B1 F4 M1 N2 L3 M8 K11 D8 A1 G1 N1 L4 N7 N8 L11 C8 K7 G10 F12 M12 N13 ⎯ ⎯ F13 M13 L13 MB91480 series Pin name LQFP100 ⎯ 1 19 32 33 51 76 ⎯ ⎯ 18 34 47 50 75 100 ⎯ 35 62 64 ⎯ ⎯ ⎯ ⎯ 63 ⎯ ⎯ Function VCC Power supply pins Connect all pins to the same potential. VSS GND pins Connect all pins to the same potential. C Capacitor coupling pin for internal regulator AVCC10 Analog power supply pin for 8/10-bit A/D converter 0/1/2 AVSS10 Analog GND pin for 8/10-bit A/D converter AVCC12 Analog power supply pin for 12-bit A/D converter 3/4 AVSS12 Analog GND pin for 12-bit A/D converter 3/4 AVRH0 AVRH1 AVRH2 AVRH3 AVRH4 Analog reference power supply pin for 8/10-bit A/D converter 0 Analog reference power supply pin for 8/10-bit A/D converter 1 Analog reference power supply pin for 8/10-bit A/D converter 2 Analog reference power supply pin for 12-bit A/D converter 3 Analog reference power supply pin for 12-bit A/D converter 4 20 MB91470/480 Series ■ I/O CIRCUIT TYPE Type X1 Circuit Remarks Oscillation feedback resistance for high speed (main clock oscillation) approx. 1 MΩ Clock input A X0 Standby control Pull-up control • CMOS level output • CMOS level input • With standby control • With pull-up control P-ch Digital output P-ch C R N-ch Digital output Digital input Standby control Pull-up control • CMOS level output • CMOS level hysteresis input • With standby control • With pull-up control P-ch Digital output P-ch D R N-ch Digital output Digital input Standby control (Continued) 21 MB91470/480 Series Type Circuit Pull-up control Remarks • Analog/CMOS level hysteresis I/O pin • CMOS level output • CMOS level hysteresis input (with standby control) • Analog input (Operates as an analog input when the corresponding AICR register bit is “1”.) • With pull-up control Digital output P-ch P-ch G R N-ch Digital output Digital input Standby control Analog input • CMOS level hysteresis input • Without standby control P-ch H R N-ch Digital input • CMOS level hysteresis input P-ch • Without standby control • With pull-up resistance P-ch I R N-ch Digital input (Continued) 22 MB91470/480 Series (Continued) Type Circuit Pull-up control Remarks • CMOS level output • CMOS level hysteresis input • With standby control • With pull-up control Digital output P-ch P-ch J R N-ch Digital output Digital input Standby control Flash memory product only • CMOS level input • High voltage control for testing Flash memory N-ch N-ch N-ch K N-ch N-ch Control signal Mode input R 23 MB91470/480 Series ■ HANDLING DEVICES • Preventing latch-up Latch-up phenomenon may occur with CMOS IC, when a voltage higher than VCC or lower than VSS is applied to either the input or output terminals, or when a voltage is applied between VCC pin and VSS pin that exceeds the rated voltage. When latch-up occurs, a significant power-supply current surge results, which may damage some elements due to the excess heat, so great care must be taken to ensure that the maximum rating is never exceeded during use. • Treatment of unused input pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a pull-up or pull-down resistor. • Power pins In products with multiple VCC and VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to the same potential power supply and a ground line externally to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between VCC and VSS near this device. • Crystal oscillator circuit Noise near the X0 and X1 pins may cause the device to malfunction. Design the printed circuit board so that X0, X1, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended to design the PC board artwork with the X0 and X1pins surrounded by ground plane because stable operation can be expected with such a layout. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. • About mode pins (MD0 to MD2) These pins should be connected directly to VCC pin or VSS pin. To prevent the device erroneously switching to test mode due to noise, the pattern length between each mode pins and VCC or VSS on the printed circuit board should be as short as possible, and they should be connected at low impedance. • Operation at start-up Be sure to execute setting initialized reset (INIT) with INITX pin immediately after start-up. Immediately after that, also, hold the "L"-level input to the INITX pin for the stabilization wait time required for the oscillator circuit to take the oscillation stabilization wait time for the oscillator circuit and the stabilization wait time for the regulator (For INIT via the INITX pin, the oscillation stabilization wait time setting is initialized to the minimum value). 24 MB91470/480 Series • Notes upon power-on sequence It requires more than 600 µs (between 0.0 V to 5.0 V) to rise voltage upon power on in order to prevent the device malfunction caused by the overshooting in the built-in voltage step-down circuit. After the supply voltage is stable (voltage is risen) , it takes 600 µs until internal supply is stable. Hold the input to the INITX pin during that period. If it takes less than 600 µs (between 0.0 V to 5.0 V) for power up, it requires 2 ms* until internal supply is stable after voltage supply is stable (voltage is risen) . Hold the input to the INITX pin during that period. CASE : voltage rising time is more than 600 µs (0.0 V to 5.0 V) 5.0 VCC (V) 0 600 (µs) t Hold for more than 600 µs INITX Internal power supply waits until stable Power-on Start operating CASE : voltage rising time is less than 600 µs (0.0 V to 5.0 V) 5.0 VCC (V) 0 600 (µs) t Hold for more than 2 ms* INITX Power-on Internal power supply waits until stable Start operating * : In case of which it takes less than 600 µs (between 0.0 V to 5.0 V) to rise voltage, the time to make internal power supply stable is proportional to the capacitance value of the bypass capacitor for the pin C. It takes 2 ms if the pin C = 4.7 µF ; 4 ms if the pin C = 9.4 µF. 25 MB91470/480 Series • Order of power turning ON/OFF Use the following procedure for turning the power on or off. If not using the A/D converter, connect AVCC =VCC and AVSS = VSS. Turn on the power supply in the sequence VCC → AVCC → AVRH, and turn off the power in the reverse sequence. • Source oscillation input when turning on the power When turning the power on, maintain the clock input until the device is released from the oscillation stabilization wait state. • Cautions for operation during PLL clock mode Even if the oscillator comes off or the clock input stops with the PLL clock selected for MB91470/480 series, MB91470/480 series may continue to operate at the free-run frequency of the PLL’s internal self-oscillating oscillator circuit. Performance of this operation, however, cannot be guaranteed. • Using an external clock When using an external clock, you must always input clock signals with opposite phase from X0 pin to X1 pin simultaneously. However, as the X1 pin halts with an output at the "H" level during stop mode, insert a resistor of approximately 1 kΩ externally to prevent a conflict between the two outputs if using stop mode (oscillation stop mode). The figure below shows an example of how to use an external clock. • Example of Using an External Clock X0 MB91470/480 series X1 • C pin As MB91470/480 series includes an internal regulator, always connect a bypass capacitor of approximately 4.7 µF to the C pin for use by the regulator. MB91470/480 series C 4.7 µF VSS GND • Software reset on the synchronous mode Be sure to meet the following two conditions before setting 0 to the SRST bit of STCR (standby control register) when the software reset is used on the synchronous mode. • Set the interrupt enable flag (I-Flag) to interrupts disabled (I-Flag=0). • Not used NMI 26 MB91470/480 Series ■ BLOCK DIAGRAM •MB91470 series (144 pins) VCC VSS C Downconversion circuit FR60 CPU core Watchdog timer 32 Bit search Flash/ROM (Max 512 Kbytes) 32 MAC D-bus RAM (Max 28 Kbytes) F-bus RAM (Max 4 Kbytes) 32 SYSCLK Bus converter 32 DMAC 5 channels MD2 to MD0 INITX X0 X1 32 ↔ 16 adapter Clock control 16 3 channels external bus I/F A15 to A00 D31 to D16 ASX CS0X to CS2X RDX WR0X, WR1X RDY NMIX INT0 to INT9 1+10 channels external interrupt 16 SCK0 to SCK5 SIN0 to SIN5 SOT0 to SOT5 6 channels multi-function serial interface Interrupt controller 1 unit timing generator Port I/F 1 channel up/down counter 2 channels reload timer PPG0 to PPG7 GPIO AIN0 BIN0 ZIN0 AVCC10 AVSS10 AVRH2 ADTG2 AN2-0 to AN2-11 AVCC12 AVSS12 AVRH3 ADTG3 AN3-0 to AN3-3 AVRH4 ADTG4 AN4-0 to AN4-3 12 channels input 8/10-bit A/D converter 2 8 channels PPG Multi-function timer 4 channels input 12-bit A/D converter 3 4 channels input 12-bit A/D converter 4 3 channels A/D activating compare 4 channels input capture 3 channels free-run timer 6 channels output compare 6 channels wave form generator IC0 to IC3 CKI0 TIN0 to TIN3 TOUT0 to TOUT3 4 channels base timer -PWC -Reload timer -PWM -PPG RTO0 to RTO5 DTTI0 27 MB91470/480 Series • MB91480 series (100 pins) VCC VSS C Downconversion circuit FR60 CPU core Watchdog timer 32 Bit search Flash/ROM (Max 512 Kbytes) 32 MAC D-bus RAM (Max 28 Kbytes) F-bus RAM (Max 4 Kbytes) Bus converter 32 32 DMAC 5 channels MD2 to MD0 INITX X0 X1 Clock control 1+10 channels external interrupt 16 32 ↔ 16 adapter 16 NMIX INT0 to INT9 Clock monitor CLKPOUT SCK0 to SCK2 SIN0 to SIN2 SOT0 to SOT2 3 channels multi-function serial interface Interrupt controller 2 units timing generator Port I/F GPIO AVCC10 AVSS10 AVRH2 ADTG2 AN2-0 to AN2-9 10 channels input 8/10-bit A/D converter 2 4 channels input 8/10-bit A/D converter 0 4 channels input 8/10-bit A/D converter 1 4 channels base timer -PWC -Reload timer -PWM -PPG 16 channels PPG 2 channels reload timer PPG0 to PPG15 Multi-function timer ADTG0 AN0-0 to AN0-3 ADTG1 AN1-0 to AN1-3 6 channels A/D activating compare 8 channels input capture 6 channels free-run timer 12 channels output compare 12 channels wave form generator IC0 to IC7 CKI0,CKI1 TIN0 to TIN3 TOUT0 to TOUT3 RTO0 to RTO11 DTTI0,DTTI1 28 MB91470/480 Series ■ MEMORY SPACE 1. Memory Space The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access. • Direct Addressing Areas The following address space areas are used as I/O areas. These areas are called direct addressing areas, in which the address of an operand can be specified directly by the instruction. The size of directly addressable areas depends on the length of the data being accessed as shown below. → byte data access : 000H to 0FFH → half word data access : 000H to 1FFH → word data access : 000H to 3FFH 2. Memory Map • MB91470 series Single chip mode 0000 0000H Internal ROM external bus mode I/O I/O External ROM external bus mode I/O I/O I/O 0000 0400H Direct addressing area Refer to “■I/O MAP” I/O 0001 0000H Access prohibited 0003 F000H 0004 0000H Access prohibited F-bus RAM 4 Kbytes Access prohibited F-bus RAM 4 Kbytes F-bus RAM 4 Kbytes D-bus RAM 28 Kbytes 0004 7000H 0005 0000H 0008 0000H D-bus RAM 28 Kbytes D-bus RAM 28 Kbytes Access prohibited Access prohibited Access prohibited Maximum value • 12 Kbytes : 00040000H to 00042FFFH • 20 Kbytes : 00040000H to 00044FFFH • 28 Kbytes : 00040000H to 00046FFFH Maximum value • 256 Kbytes : 000C0000H to 000FFFFFH • 384 Kbytes : 000A0000H to 000FFFFFH • 512 Kbytes : 00080000H to 000FFFFFH 512 Kbytes Flash/ROM 0010 0000H 512 Kbytes Flash/ROM Access prohibited 0020 0000H External area Access prohibited External area FFFF FFFFH 144 pins 144 pins 144 pins 29 MB91470/480 Series •MB91480 series Single chip mode 0000 0000H I/O 0000 0400H Direct addressing area Refer to “■I/O MAP” I/O 0001 0000H Access prohibited 0003 F000H 0004 0000H F-bus RAM 4 Kbytes D-bus RAM 28 Kbytes 0004 7000H 0005 0000H 0008 0000H Maximum value • 12 Kbytes : 00040000H to 00042FFFH • 28 Kbytes : 00040000H to 00046FFFH Access prohibited Maximum value • 256 Kbytes : 000C0000H to 000FFFFFH • 512 Kbytes : 00080000H to 000FFFFFH 512 Kbytes Flash/ROM 0010 0000H 0020 0000H Access prohibited FFFF FFFFH 100 pins 30 MB91470/480 Series ■ MODE SETTINGS The FR family uses mode pins (MD2 to MD0) and mode data to set the operation mode. 1. Mode Pins The MD2 to MD0 pins specify how the mode vector fetch and reset vector fetch is performed. Settings other than those shown in the following table are prohibited. Mode Pins MD2 0 0 MD1 0 0 MD0 0 1 Reset vector access area Internal External The bus width is set by mode register. Mode name Internal ROM mode vector External ROM mode vector Remarks 2. Mode data The data that is written to the internal mode register (MODR) by the mode vector fetch is called mode data. After the mode register is set, the device runs in the operating mode specified by this register. The mode data is set by all of the reset sources. User programs cannot set the mode register. bit23 0 bit22 0 bit21 0 bit20 0 bit19 0 bit18 ROMA bit17 WTH1 bit16 WTH0 Operation mode setting bits [bit 23 to bit 19] Reserved bits Be sure to set these bits to “00000B”. Operation is not guaranteed if these bits are set to a value other than “00000B”. [bit 18] ROMA (Internal Flash/ROM enable bit) This bit configures whether the internal Flash/ROM area (8 0000H to F FFFFH) is enabled. ROMA 0 1 Function External ROM mode Internal ROM mode Remarks Internal Flash/ROM area (8 0000H to F FFFFH) is used as an external area. Internal Flash/ROM area (8 0000H to F FFFFH) is enabled. 31 MB91470/480 Series [bit 17, bit 16] WTH1, WTH0 (Bus width specification bit) These bits configure the bus width in external bus mode. In external bus mode, this value is set to the DBW1 and DBW0 bits of AWR0 (CS0 area). WTH1 0 0 1 1 WTH0 0 1 0 1 Single chip mode Function 8-bit bus width 16-bit bus width ⎯ External bus mode External bus mode (Setting prohibited) Single chip mode Remarks 3. Note The mode data set in the mode vector must be stored as byte data at 0x000FFFF8H. The data should be located in the highest byte from bit 31 to bit 24 because the FR family uses big endian byte ordering. bit 31 Incorrect 0x000FFFF8H Correct 0x000FFFF8H 0x000FFFFCH 24 23 16 15 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 87 Mode data XXXXXXXX 0 XXXXXXXX Mode data Reset vector 32 MB91470/480 Series ■ I/O MAP [How to read the table] Address 000000H Register +0 +1 +2 +3 PDR0 [R/W] B PDR1 [R/W] B PDR2 [R/W] B PDR3 [R/W] B XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Block T-unit Port data register Read/write attribute, Access unit (B : byte, H : half word, W : word) Initial value of register after reset Register name (column 1 of the register is at address 4n, column 2 is at address 4 n + 1...) Leftmost register address (For word-length access, column 1 of the register is the MSB of the data.) Note : Initial values of register bits are represented as follows : “ 1 ” : Initial Value “ 1 ” “ 0 ” : Initial Value “ 0 ” “ X ” : Initial Value “ undefined ” “ - ” : No physical register at this location Access to addresses where the data access properties have not been documented is prohibited. 33 MB91470/480 Series Address Register +0 PDR0 [R/W] B, H, W XXXXXXXX PDR5 [R/W] B, H, W -XXXXXXX PDRA [R/W] B, H, W ---XXXXX PDRE [R/W] B, H, W XXXXXXXX PDRJ [R/W] B, H, W XXXXXXXX PDRP [R/W] B, H, W --XXXXXX +1 PDR1 [R/W] B, H, W XXXXXXXX PDR6 [R/W] B, H, W ------XX PDRB [R/W] B, H, W XXXXXXXX PDRF [R/W] B, H, W XXXXXXXX ⎯ PDRQ [R/W] B, H, W --XXXXXX ⎯ EIRR0 [R/W] B, H, W 00000000 DICR [R/W] B, H, W -------0 ENIR0 [R/W] B, H, W 00000000 HCRL [R/W, R] B, H, W 0--11111 +2 PDR2 [R/W] B, H, W XXXXXXXX PDR8 [R/W] B, H, W XXXXXXXX PDRC [R/W] B, H, W XXXXXXXX PDRG [R/W] B, H, W --XXXXXX PDRL [R/W] B, H, W -----XXX PDRR [R/W] B, H, W --XXXXXX +3 PDR3 [R/W] B, H, W XXXXXXXX PDR9 [R/W] B, H, W XXXXXXXX PDRD [R/W] B, H, W ----XXXX PDRH [R/W] B, H, W --XXXXXX PDRM [R/W] B, H, W ----XXXX PDRS [R/W] B, H, W --XXXXXX Block 000000H 000004H 000008H Port data register 00000CH 000010H 000014H 000018H to 00003CH (Reserved) External interrupt (INT0 to INT7) Delay interrupt/ hold request Reload timer 0 000040H ELVR0 [R/W] B, H, W 00000000 00000000 000044H ⎯ TMR0 [R] H, W XXXXXXXX XXXXXXXX TMCSR0 [R/W, R] B, H, W ----00-- ---00000 TMR1 [R] H, W XXXXXXXX XXXXXXXX TMCSR1 [R/W, R] B, H, W ----00-- ---00000 ⎯ 000048H 00004CH 000050H 000054H 000058H to 00005CH TMRLR0 [W] H, W XXXXXXXX XXXXXXXX ⎯ TMRLR1 [W] H, W XXXXXXXX XXXXXXXX ⎯ Reload timer 1 (Reserved) (Continued) 34 MB91470/480 Series Address Register +0 SSR0 [R/W, R] B, H, W 00000011 BGR01[R/W] B, H, W 00000000 ⎯ FBYTE02 [R/W] B, H, W 00000000 SSR1 [R/W, R] B, H, W 00000011 BGR11 [R/W] B, H, W 00000000 ⎯ FBYTE21 [R/W] B, H, W 00000000 SSR2 [R/W, R] B, H, W 00000011 BGR21 [R/W] B, H, W 00000000 ⎯ FBYTE22 [R/W] B, H, W 00000000 FBYTE21 [R/W] B, H, W 00000000 FBYTE11 [R/W] B, H, W 00000000 ESCR2 [R/W]/ IBSR2 [R/W, R] B, H, W 00000000 BGR20 [R/W] B, H, W 00000000 FBYTE01 [R/W] B, H, W 00000000 ESCR1 [R/W]/ IBSR1 [R/W, R] B, H, W 00000000 BGR10 [R/W] B, H, W 00000000 +1 ESCR0 [R/W]/ IBSR0 [R/W, R] B, H, W 00000000 BGR00 [R/W] B, H, W 00000000 +2 SCR0 [R/W] / IBCR0 [R/W, R] B, H, W 00000000 RDR0 [R]/ TDR0 [W]H, W -------0 00000000 ISMK0 [R/W] B, H, W 01111111 FCR01 [R/W] B, H, W ---00100 SCR1 [R/W] / IBCR1 [R/W, R] B, H, W 00000000 RDR1 [R]/ TDR1 [W]H, W -------0 00000000 ISMK1 [R/W] B, H, W 01111111 FCR11 [R/W] B, H, W ---00100 SCR2 [R/W] / IBCR2 [R/W, R] B, H, W 00000000 RDR2 [R]/ TDR2 [W]H, W -------0 00000000 ISMK2 [R/W] B, H, W 01111111 FCR21 [R/W] B, H, W ---00100 +3 SMR0 [R/W] B, H, W 000-0000 RDR0 [R]/ TDR0 [W]H, W -------0 00000000 ISBA0 [R/W] B, H, W 00000000 FCR00 [R/W, R] B, H, W -0000000 SMR1 [R/W] B, H, W 000-0000 RDR1 [R]/ TDR1 [W]H, W -------0 00000000 ISBA1 [R/W] B, H, W 00000000 FCR10 [R/W, R] B, H, W -0000000 SMR2 [R/W] B, H, W 000-0000 RDR2 [R]/ TDR2 [W]H, W -------0 00000000 ISBA2 [R/W] B, H, W 00000000 FCR20 [R/W, R] B, H, W -0000000 Block 000060H 000064H 000068H Multifunction serial interface 0 00006CH 000070H 000074H 000078H Multifunction serial interface 1 00007CH 000080H 000084H 000088H Multifunction serial interface 2 00008CH (Continued) 35 MB91470/480 Series Address Register +0 SSR3 [R/W, R] B, H, W 00000011 BGR31 [R/W] B, H, W 00000000 ⎯ FBYTE32 [R/W] B, H, W 00000000 FBYTE31 [R/W] B, H, W 00000000 +1 ESCR3 [R/W]/ IBSR3 [R/W, R] B, H, W 00000000 BGR30 [R/W] B, H, W 00000000 +2 SCR3 [R/W] / IBCR3 [R/W, R] B, H, W 00000000 RDR3 [R]/ TDR3 [W]H, W -------0 00000000 ISMK3 [R/W] B, H, W 01111111 FCR31 [R/W] B, H, W ---00100 +3 SMR3 [R/W] B, H, W 000-0000 RDR3 [R]/ TDR3 [W]H, W -------0 00000000 ISBA3 [R/W] B, H, W 00000000 FCR30 [R/W, R] B, H, W -0000000 Block 000090H 000094H 000098H Multifunction serial interface 3 00009CH 0000A0H OCCPBH0, OCCPBL0 [W]/ OCCPH0, OCCPL0 [R] H, W 00000000 00000000 OCCPBH2, OCCPBL2 [W]/ OCCPH2, OCCPL2 [R] H, W 00000000 00000000 OCCPBH4, OCCPBL4 [W]/ OCCPH4, OCCPL4 [R] H, W 00000000 00000000 OCSH1 [R/W] B, H, W -1100000 OCSH5 [R/W] B, H, W -1100000 OCSL0 [R/W] B, H, W 00001100 OCSL4 [R/W] B, H, W 00001100 OCCPBH1, OCCPBL1 [W]/ OCCPH1, OCCPL1 [R] H, W 00000000 00000000 OCCPBH3, OCCPBL3 [W]/ OCCPH3, OCCPL3 [R] H, W 00000000 00000000 OCCPBH5, OCCPBL5 [W]/ OCCPH5, OCCPL5 [R] H, W 00000000 00000000 OCSH3 [R/W] B, H, W -1100000 OCMOD0 [R/W] B, H, W --000000 OCSL2 [R/W] B, H, W 00001100 ⎯ OCU0 0000A4H 0000A8H 0000ACH 0000B0H 0000B4H CPCLRBH0, CPCLRBL0 [W]/ CPCLRH0, CPCLRL0 [R] H, W 11111111 11111111 TCCSH0 [R/W] B, H, W 00000000 TCCSL0 [R/W] B, H, W 01000000 TCDTH0, TCDTL0 [R/W] H, W 00000000 00000000 TCCSM0 [R/W] B, H, W ----0000 ADTRGC0 [R/W] B, H, W -000-000 Free-run timer 0 0000B8H 0000BCH CPCLRBH1, CPCLRBL1 [W] / CPCLRH1, CPCLRL1 [R] H, W 11111111 11111111 TCCSH1 [R/W] B, H, W 00000000 TCCSL1 [R/W] B, H, W 01000000 TCDTH1, TCDTL1 [R/W] H, W 00000000 00000000 TCCSM1 [R/W] B, H, W ----0000 ADTRGC1 [R/W] B, H, W -000-000 Free-run timer 1 0000C0H (Continued) 36 MB91470/480 Series Address Register +0 +1 +2 +3 CPCLRBH2, CPCLRBL2 [W] / CPCLRH2, CPCLRL2 [R] H, W 11111111 11111111 TCCSH2 [R/W] B, H, W 00000000 ⎯ TCCSL2 [R/W] B, H, W 01000000 Block 0000C4H TCDTH2, TCDTL2 [R/W] H, W 00000000 00000000 TCCSM2 [R/W] B, H, W ----0000 ADTRGC2 [R/W] B, H, W -000-000 Free-run timer 2 0000C8H 0000CCH 0000D0H 0000D4H 0000D8H FRS2 [R/W] B, H, W FRS1 [R/W] B, H, W FRS0 [R/W] B, H, W -000-000 -000-000 -000-000 ⎯ FRS4 [R/W] B, H, W FRS3 [R/W] B, H, W -000-000 -000-000 IPCPH1, IPCPL1 [R] H, W XXXXXXXX XXXXXXXX IPCPH3, IPCPL3 [R] H, W XXXXXXXX XXXXXXXX ICSH23 [R] B, H, W ------00 ICSL23[R/W] B, H, W 00000000 Free-run timer selector 0 IPCPH0, IPCPL0 [R] H, W XXXXXXXX XXXXXXXX IPCPH2, IPCPL2 [R] H, W XXXXXXXX XXXXXXXX PICSH01 [W, R] B, H, W 00000000 PICSL01 [R/W] B, H, W 00000000 ICU0 0000DCH 0000E0H 0000E4H TMRRH0, TMRRL0 [R/W] H, W XXXXXXXX XXXXXXXX TMRRH2, TMRRL2 [R/W] H, W XXXXXXXX XXXXXXXX DTCR0 [R/W] B, H, W 00000000 ⎯ DTCR1 [R/W] B, H, W 00000000 SIGCR10 [R/W] B, H, W 00000000 TMRRH1, TMRRL1 [R/W] H, W XXXXXXXX XXXXXXXX ⎯ DTCR2 [R/W] B, H, W 00000000 ⎯ ⎯ SIGCR20 [R/W] B, H, W 000000-1 Wave form generator 0 0000E8H 0000ECH 0000F0H ADCOMP0 [W]/ ADCOMPB0 [R] H, W 00000000 00000000 ADCOMP1 [W]/ ADCOMPB1 [R] H, W 00000000 00000000 ADCOMP2 [W]/ ADCOMPB2 [R] H, W 00000000 00000000 ⎯ ADTGBUF0 [R/W] B, H, W -000-111 ADCOMPD0 [W]/ ADCOMPDB0 [R] H, W 00000000 00000000 ADCOMPD1 [W]/ ADCOMPDB1 [R] H, W 00000000 00000000 ADCOMPD2 [W]/ ADCOMPDB2 [R] H, W 00000000 00000000 ADTGSEL0 [R/W] B, H, W --000000 ADTGCE0 [R/W] B, H, W --000000 (Continued) 0000F4H 0000F8H A/D activating compare 0 0000FCH 37 MB91470/480 Series Address Register +0 PRLH0 [R/W] B, H, W XXXXXXXX PRLH2 [R/W] B, H, W XXXXXXXX PPGC0 [R/W] B, H, W 00000000 PRLH4 [R/W] B, H, W XXXXXXXX PRLH6 [R/W] B, H, W XXXXXXXX PPGC4 [R/W] B, H, W 00000000 PRLH8 [R/W] B, H, W XXXXXXXX PRLH10 [R/W] B, H, W XXXXXXXX PPGC8 [R/W] B, H, W 00000000 PRLH12 [R/W] B, H, W XXXXXXXX PRLH14 [R/W] B, H, W XXXXXXXX PPGC12 [R/W] B, H, W 00000000 +1 PRLL0 [R/W] B, H, W XXXXXXXX PRLL2 [R/W] B, H, W XXXXXXXX PPGC1 [R/W] B, H, W 00000000 PRLL4 [R/W] B, H, W XXXXXXXX PRLL6 [R/W] B, H, W XXXXXXXX PPGC5 [R/W] B, H, W 00000000 PRLL8 [R/W] B, H, W XXXXXXXX PRLL10 [R/W] B, H, W XXXXXXXX PPGC9 [R/W] B, H, W 00000000 PRLL12 [R/W] B, H, W XXXXXXXX PRLL14 [R/W] B, H, W XXXXXXXX PPGC13 [R/W] B, H, W 00000000 +2 PRLH1 [R/W] B, H, W XXXXXXXX PRLH3 [R/W] B, H, W XXXXXXXX PPGC2 [R/W] B, H, W 00000000 PRLH5 [R/W] B, H, W XXXXXXXX PRLH7 [R/W] B, H, W XXXXXXXX PPGC6 [R/W] B, H, W 00000000 PRLH9 [R/W] B, H, W XXXXXXXX PRLH11 [R/W] B, H, W XXXXXXXX PPGC10 [R/W] B, H, W 00000000 PRLH13 [R/W] B, H, W XXXXXXXX PRLH15 [R/W] B, H, W XXXXXXXX PPGC14 [R/W] B, H, W 00000000 ⎯ ⎯ +3 PRLL1 [R/W] B, H, W XXXXXXXX PRLL3 [R/W] B, H, W XXXXXXXX PPGC3 [R/W] B, H, W 00000000 PRLL5 [R/W] B, H, W XXXXXXXX PRLL7 [R/W] B, H, W XXXXXXXX PPGC7 [R/W] B, H, W 00000000 PRLL9 [R/W] B, H, W XXXXXXXX PRLL11 [R/W] B, H, W XXXXXXXX PPGC11 [R/W] B, H, W 00000000 PRLL13 [R/W] B, H, W XXXXXXXX PRLL15 [R/W] B, H, W XXXXXXXX PPGC15 [R/W] B, H, W 00000000 GATEC0 [R/W] B --00--00 GATEC4 [R/W] B ------00 GATEC8 [R/W] B --00--00 Block 000100H 000104H 000108H 00010CH 000110H 000114H 000118H PPG 00011CH 000120H 000124H 000128H 00012CH 000130H 000134H 000138H TRG [R/W] B, H 00000000 00000000 REVC [R/W] B, H 00000000 00000000 ⎯ (Continued) 38 MB91470/480 Series Address 00013CH 000140H 000144H Register +0 +1 ⎯ ⎯ TTCR0 [R/W, W, R] B, H, W 11110000 COMP0 [R/W] B, H, W 00000000 TTCR1 [R/W, W, R] B, H, W 11110000 COMP1 [R/W] B, H, W 00000000 EIRR1 [R/W] B, H, W 00000000 COMP3 [R/W] B, H, W 00000000 ENIR1 [R/W] B, H, W 00000000 ⎯ ⎯ BT0TMR [R] B, H, W 00000000 00000000 ⎯ BT0STC [R/W] B 00000000 CMCLKR [R/W] B ----0000 BT0TMCR [R/W] B, H, W 00000000 00000000 ⎯ BT0PDUT/BT0PRLH/BT0DTBF [R/W] H, W XXXXXXXX XXXXXXXX ⎯ AICR2 [R/W] B, H, W ----1111 11111111 ADCS2 [R/W, W] B, H, W 0000000⎯ ADCH2 [R/W] B, H, W 00000000 ⎯ ADMD2 [R/W] B, H, W 00001111 COMP2 [R/W] B, H, W 00000000 ⎯ COMP4 [R/W] B, H, W 00000000 ⎯ COMP5 [R/W] B, H, W 00000000 COMP7 [R/W] B, H, W 00000000 COMP6 [R/W] B, H, W 00000000 +2 +3 GATEC12 [R/W] B ------00 Block PPG (Reserved) Timing generator 0 000148H 00014CH Timing generator 1 000150H 000154H ELVR1 [R/W] B, H, W 00000000 00000000 External interrupt (INT8 to INT15) (Reserved) Clock monitor 000158H 00015CH 000160H 000164H Base timer 0 000168H 00016CH 000170H BT0PCSR/BT0PRLL [R/W] H, W XXXXXXXX XXXXXXXX (Reserved) 000174H 000178H 00017CH ADCD002 [R] B, H, W 10----XX XXXXXXXX ADCD022 [R] B, H, W 10----XX XXXXXXXX ADCD012 [R] B, H, W 10----XX XXXXXXXX ADCD032 [R] B, H, W 10----XX XXXXXXXX 8/10-bit A/D converter 2 (12 channels) (Continued) 39 MB91470/480 Series Address 000180H 000184H 000188H 00018CH 000190H 000194H 000198H 00019CH Register +0 +1 +2 +3 ADCD042 [R] B, H, W 10----XX XXXXXXXX ADCD062 [R] B, H, W 10----XX XXXXXXXX ADCD082 [R] B, H, W 10----XX XXXXXXXX ADCD102 [R] B, H, W 10----XX XXXXXXXX ⎯ ⎯ ⎯ ⎯ OCCPBH6, OCCPBL6 [W]/ OCCPH6, OCCPL6 [R] H, W 00000000 00000000 OCCPBH8, OCCPBL8 [W]/ OCCPH8, OCCPL8 [R] H, W 00000000 00000000 OCCPBH10, OCCPBL10 [W]/ OCCPH10, OCCPL10 [R] H, W 00000000 00000000 OCSH7 [R/W] B, H, W -1100000 OCSH11 [R/W] B, H, W -1100000 OCSL6 [R/W] B, H, W 00001100 OCSL10 [R/W] B, H, W 00001100 OCCPBH7, OCCPBL7 [W]/ OCCPH7, OCCPL7 [R] H, W 00000000 00000000 OCCPBH9, OCCPBL9 [W]/ OCCPH9, OCCPL9 [R] H, W 00000000 00000000 OCCPBH11, OCCPBL11 [W]/ OCCPH11, OCCPL11 [R] H, W 00000000 00000000 OCSH9 [R/W] B, H, W -1100000 OCMOD1 [R/W] B, H, W --000000 OCSL8 [R/W] B, H, W 00001100 ⎯ ADCD052 [R] B, H, W 10----XX XXXXXXXX ADCD072 [R] B, H, W 10----XX XXXXXXXX ADCD092 [R] B, H, W 10----XX XXXXXXXX ADCD112 [R] B, H, W 10----XX XXXXXXXX Block 8/10-bit A/D converter 2 (12 channels) (Reserved) (Reserved) (Reserved) (Reserved) 0001A0H 0001A4H OCU1 0001A8H 0001ACH 0001B0H 0001B4H CPCLRBH3, CPCLRBL3 [W]/ CPCLRH3, CPCLRL3 [R] H, W 11111111 11111111 TCCSH3 [R/W] B, H, W 00000000 TCCSL3 [R/W] B, H, W 01000000 TCDTH3, TCDTL3 [R/W] H, W 00000000 00000000 TCCSM3 [R/W] B, H, W ----0000 ADTRGC3 [R/W] B, H, W -000-000 Free-run timer 3 0001B8H 0001BCH CPCLRBH4, CPCLRBL4 [W] / CPCLRH4, CPCLRL4 [R] H, W 11111111 11111111 TCCSH4 [R/W] B, H, W 00000000 TCCSL4 [R/W] B, H, W 01000000 TCDTH4, TCDTL4 [R/W] H, W 00000000 00000000 TCCSM4 [R/W] B, H, W ----0000 ADTRGC4 [R/W] B, H, W -000-000 Free-run timer 4 0001C0H (Continued) 40 MB91470/480 Series Address Register +0 +1 +2 +3 CPCLRBH5, CPCLRBL5 [W] / CPCLRH5, CPCLRL 5 [R] H, W 11111111 11111111 TCCSH5 [R/W] B, H, W 00000000 ⎯ TCCSL5 [R/W] B, H, W 01000000 Block 0001C4H TCDTH5, TCDTL5 [R/W] H, W 00000000 00000000 TCCSM5 [R/W] B, H, W ----0000 ADTRGC5 [R/W] B, H, W -000-000 Free-run timer 5 0001C8H 0001CCH 0001D0H 0001D4H 0001D8H FRS7 [R/W] B, H, W FRS6 [R/W] B, H, W FRS5 [R/W] B, H, W -011-011 -011-011 -011-011 ⎯ FRS9 [R/W] B, H, W FRS8 [R/W] B, H, W -011-011 -011-011 IPCPH5, IPCPL5 [R] H, W XXXXXXXX XXXXXXXX IPCPH7, IPCPL7 [R] H, W XXXXXXXX XXXXXXXX ICSH67 [R] B, H, W ------00 ICSL67 [R/W] B, H, W 00000000 Free-run timer selector 1 IPCPH4, IPCPL4 [R] H, W XXXXXXXX XXXXXXXX IPCPH6, IPCPL6 [R] H, W XXXXXXXX XXXXXXXX PICSH45 [W, R] B, H, W 00000000 PICSL45 [R/W] B, H, W 00000000 ICU1 0001DCH 0001E0H 0001E4H TMRRH3, TMRRL3 [R/W] H, W XXXXXXXX XXXXXXXX TMRRH5, TMRRL5 [R/W] H, W XXXXXXXX XXXXXXXX DTCR3 [R/W] B, H, W 00000000 ⎯ DTCR4 [R/W] B, H, W 00000000 SIGCR11 [R/W] B, H, W 00000000 TMRRH4, TMRRL4 [R/W] H, W XXXXXXXX XXXXXXXX ⎯ DTCR5 [R/W] B, H, W 00000000 ⎯ ⎯ SIGCR21 [R/W] B, H, W 000000-1 Wave form generator 1 0001E8H 0001ECH 0001F0H ADCOMP3 [W]/ ADCOMPB3 [R] H, W 00000000 00000000 ADCOMP4 [W]/ ADCOMPB4 [R] H, W 00000000 00000000 ADCOMP5 [W]/ ADCOMPB5 [R] H, W 00000000 00000000 ⎯ ADTGBUF1 [R/W] B, H, W -000-111 ADCOMPD3 [W]/ ADCOMPDB3 [R] H, W 00000000 00000000 ADCOMPD4 [W]/ ADCOMPDB4 [R] H, W 00000000 00000000 ADCOMPD5 [W]/ ADCOMPDB5 [R] H, W 00000000 00000000 ADTGSEL1 [R/W] B, H, W --000000 ADTGCE1[R/W] B, H, W --000000 (Continued) 0001F4H 0001F8H A/D activating compare 1 0001FCH 41 MB91470/480 Series Address 000200H 000204H 000208H 00020CH 000210H 000214H 000218H 00021CH 000220H 000224H 000228H to 00023CH 000240H 000244H to 00039CH 0003A0H Register +0 +1 +2 +3 DMACA0 [R/W] B, H, W *1 00000000 ----XXXX XXXXXXXX XXXXXXXX DMACB0 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA1 [R/W] B, H, W *1 00000000 ----XXXX XXXXXXXX XXXXXXXX DMACB1 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA2 [R/W] B, H, W *1 00000000 ----XXXX XXXXXXXX XXXXXXXX DMACB2 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA3 [R/W] B, H, W *1 000000000 ----XXXX XXXXXXXX XXXXXXXX DMACB3 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA4 [R/W] B, H, W *1 00000000 ----XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX ⎯ DMACR [R/W] B, H, W 0--00000 -------- -------- -------⎯ DSP-PC [R/W] B, H, W 000000-0 DSP-CSR [R/W, R, W] B, H, W 00000000 Block DMAC (Reserved) DMAC (Reserved) ⎯ 0003A4H 0003A8H 0003ACH 0003B0H 0003B4H DSP-LY [R/W], W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DSP-OT0 [R], W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DSP-OT1 [R], W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DSP-OT2 [R], W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DSP-OT3 [R], W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX (Continued) MAC 42 MB91470/480 Series Address 0003B8H 0003BCH 0003C0H 0003C4H 0003C8H 0003CCH 0003D0H 0003D4H to 0003ECH 0003F0H 0003F4H 0003F8H 0003FCH Register +0 +1 +2 +3 DSP-OT4 [R], W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DSP-OT5 [R], W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DSP-OT6 [R], W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DSP-OT7 [R], W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DSP-AC0 [R], W -------- -------- -------- 00000000 DSP-AC1 [R], W 00000000 00000000 00000000 00000000 DSP-AC2 [R], W 00000000 00000000 00000000 00000000 ⎯ BSD0 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDR0 [R/W] B, H, W 00000000 DDR5 [R/W] B, H, W -0000000 DDRA [R/W] B, H, W ---00000 DDRE [R/W] B, H, W 00000000 DDRJ [R/W] B, H, W 00000000 DDR1 [R/W] B, H, W 00000000 DDR6 [R/W] B, H, W ------00 DDRB [R/W] B, H, W 00000000 DDRF [R/W] B, H, W 00000000 ⎯ DDR2 [R/W] B, H, W 00000000 DDR8 [R/W] B, H, W 00000000 DDRC [R/W] B, H, W 00000000 DDRG [R/W] B, H, W --000000 DDRL [R/W] B, H, W -----000 DDR3 [R/W] B, H, W 00000000 DDR9 [R/W] B, H, W 00000000 DDRD [R/W] B, H, W ----0000 DDRH [R/W] B, H, W --000000 DDRM [R/W] B, H, W ----0000 Block MAC (Reserved) Bit search module 000400H 000404H 000408H Port direction register 00040CH 000410H (Continued) 43 MB91470/480 Series Address Register +0 DDRP [R/W] B, H, W --000000 +1 DDRQ [R/W] B, H, W --000000 ⎯ ⎯ PFR0 [R/W] B, H, W PFR1 [R/W] B, H, W PFR2 [R/W] B, H, W PFR3 [R/W] B, H, W 11111111 11111111 11111111 11111111 PFR5 [R/W] B, H, W PFR6 [R/W] B, H, W PFR8 [R/W] B, H, W PFR9 [R/W] B, H, W -1111111 ------11 0000---00000000 ⎯ ⎯ PFRJ [R/W] B, H, W 0-0-0-0⎯ PFRQ [R/W] B, H, W --000000 ⎯ ⎯ ICR00 [R/W, R] B, H, W ---11111 ICR04 [R/W, R] B, H, W ---11111 ICR08 [R/W, R] B, H, W ---11111 ICR12 [R/W, R] B, H, W ---11111 ICR16 [R/W, R] B, H, W ---11111 ICR20 [R/W, R] B, H, W ---11111 ICR01 [R/W, R] B, H, W ---11111 ICR05 [R/W, R] B, H, W ---11111 ICR09 [R/W, R] B, H, W ---11111 ICR13 [R/W, R] B, H, W ---11111 ICR17 [R/W, R] B, H, W ---11111 ICR21 [R/W, R] B, H, W ---11111 ICR02 [R/W, R] B, H, W ---11111 ICR06 [R/W, R] B, H, W ---11111 ICR10 [R/W, R] B, H, W ---11111 ICR14 [R/W, R] B, H, W ---11111 ICR18 [R/W, R] B, H, W ---11111 ICR22 [R/W, R] B, H, W ---11111 ICR03 [R/W, R] B, H, W ---11111 ICR07 [R/W, R] B, H, W ---11111 ICR11 [R/W, R] B, H, W ---11111 ICR15 [R/W, R] B, H, W ---11111 ICR19 [R/W, R] B, H, W ---11111 ICR23 [R/W, R] B, H, W ---11111 ⎯ PFRF [R/W] B, H, W -------0 ⎯ PFRC [R/W] B, H, W --0-00-0 PFRG [R/W] B, H, W --0-00-0 ⎯ PFRH [R/W] B, H, W --0-00-0 PFRM [R/W] B, H, W ----0000 ⎯ PFRS [R/W] B, H, W --000000 +2 DDRR [R/W] B, H, W --000000 +3 DDRS [R/W] B, H, W --000000 Block Port direction register (Reserved) 000414H 000418H 00041CH 000420H 000424H 000428H 00042CH Port function register 000430H 000434H 000438H 00043CH 000440H (Reserved) 000444H 000448H Interrupt controller 00044CH 000450H 000454H (Continued) 44 MB91470/480 Series Address Register +0 ICR24 [R/W, R] B, H, W ---11111 ICR28 [R/W, R] B, H, W ---11111 ICR32 [R/W, R] B, H, W ---11111 ICR36 [R/W, R] B, H, W ---11111 ICR40 [R/W, R] B, H, W ---11111 ICR44 [R/W, R] B, H, W ---11111 +1 ICR25 [R/W, R] B, H, W ---11111 ICR29 [R/W, R] B, H, W ---11111 ICR33 [R/W, R] B, H, W ---11111 ICR37 [R/W, R] B, H, W ---11111 ICR41 [R/W, R] B, H, W ---11111 ICR45 [R/W, R] B, H, W ---11111 ⎯ RSRR [R/W] B, H, W 1-0-0-00 CLKR [R/W] B, H, W -000-000 STCR [R/W] B, H, W 001100-1 ⎯ TBCR [R/W] B, H, W 00XXX-00 DIVR0 [R/W] B, H, W 00000011 ⎯ AICR0 [R/W] B, H, W ----1111 ⎯ ADCH0 [R/W] B, H, W --00--00 CTBR [W] B, H, W XXXXXXXX DIVR1 [R/W] B, H, W 00000000 +2 ICR26 [R/W, R] B, H, W ---11111 ICR30 [R/W, R] B, H, W ---11111 ICR34 [R/W, R] B, H, W ---11111 ICR38 [R/W, R] B, H, W ---11111 ICR42 [R/W, R] B, H, W ---11111 ICR46 [R/W, R] B, H, W ---11111 +3 ICR27 [R/W, R] B, H, W ---11111 ICR31 [R/W, R] B, H, W ---11111 ICR35 [R/W, R] B, H, W ---11111 ICR39 [R/W, R] B, H, W ---11111 ICR43 [R/W, R] B, H, W ---11111 ICR47 [R/W, R] B, H, W ---11111 Block 000458H 00045CH 000460H Interrupt controller 000464H 000468H 00046CH 000470H to 00047CH 000480H (Reserved) 000484H 000488H to 0004FCH 000500H Clock control block (Reserved) ⎯ ADCS0 [R/W, W] B, H, W 0000000- ⎯ ADMD0 [R/W] B, H, W 00001111 8/10-bit A/D converter 0 (4 channels) 000504H 000508H 00050CH ADCD000 [R] B, H, W 10----XX XXXXXXXX ADCD020 [R] B, H, W 10----XX XXXXXXXX ADCD010 [R] B, H, W 10----XX XXXXXXXX ADCD030 [R] B, H, W 10----XX XXXXXXXX (Continued) 45 MB91470/480 Series Address Register +0 ⎯ ADCS1 [R/W, W] B, H, W 0000000+1 AICR1 [R/W] B, H, W ----1111 ⎯ ADCH1 [R/W] B, H, W --00--00 +2 ⎯ ADMD1 [R/W] B, H, W 00001111 +3 Block 000510H 000514H 000518H 00051CH ADCD001 [R] B, H, W 10----XX XXXXXXXX ADCD021 [R] B, H, W 10----XX XXXXXXXX ⎯ ADCS3 [R/W, W] B, H, W 0000000AICR3 [R/W] B, H, W ----1111 ⎯ ADCD011 [R] B, H, W 10----XX XXXXXXXX ADCD031 [R] B, H, W 10----XX XXXXXXXX ⎯ ADCH3 [R/W] B, H, W --00--00 ADMD3 [R/W] B, H, W 00001111 8/10-bit A/D converter 1 (4 channels) 000520H 000524H 000528H 00052CH ADCD003 [R] B, H, W 10--XXXX XXXXXXXX ADCD023 [R] B, H, W 10--XXXX XXXXXXXX ⎯ ADCS4 [R/W, W] B, H, W 0000000AICR4 [R/W] B, H, W ----1111 ⎯ ADCD013 [R] B, H, W 10--XXXX XXXXXXXX ADCD033 [R] B, H, W 10--XXXX XXXXXXXX ⎯ ADCH4 [R/W] B, H, W --00--00 ADMD4 [R/W] B, H, W 00001111 12-bit A/D converter 3 (4 channels) 000530H 000534H 000538H 00053CH ADCD004 [R] B, H, W 10--XXXX XXXXXXXX ADCD024 [R] B, H, W 10--XXXX XXXXXXXX RCR10 [W] B, H, W RCR00 [W] B, H, W XXXXXXXX XXXXXXXX CCRH0 [R/W] B, H, W 00000000 CCRL0 [R/W, R] B, H, W -0001000 ⎯ ADCD014 [R] B, H, W 10--XXXX XXXXXXXX ADCD034 [R] B, H, W 10--XXXX XXXXXXXX UDCR10 [R] B, H, W 00000000 ⎯ UDCR00 [R] B, H, W 00000000 CSR0 [R/W, R] B, H, W 00000000 12-bit A/D converter 4 (4 channels) 000540H Up/down counter 0 000544H 000548H to 00055CH (Reserved) (Continued) 46 MB91470/480 Series Address Register +0 SSR4 [R/W, R] B, H, W 00000011 BGR41 [R/W] B, H, W 00000000 ⎯ FBYTE42 [R/W] B, H, W 00000000 SSR5 [R/W, R] B, H, W 00000011 BGR51 [R/W] B, H, W 00000000 ⎯ FBYTE52 [R/W] B, H, W 00000000 FBYTE51 [R/W] B, H, W 00000000 FBYTE41 [R/W] B, H, W 00000000 ESCR5 [R/W]/ IBSR5 [R/W, R] B, H, W 00000000 BGR50 [R/W] B, H, W 00000000 +1 ESCR4 [R/W]/ IBSR4 [R/W, R] B, H, W 00000000 BGR40 [R/W] B, H, W 00000000 +2 SCR4 [R/W] / IBCR4 [R/W, R] B, H, W 00000000 +3 SMR4 [R/W] B, H, W 000-0000 Block 000560H 000564H RDR4 [R]/TDR4 [W]H, W -------0 00000000 ISMK4 [R/W] B, H, W 01111111 FCR41 [R/W] B, H, W ---00100 SCR5 [R/W] / IBCR5 [R/W, R] B, H, W 00000000 ISBA4 [R/W] B, H, W 00000000 FCR40 [R/W, R] B, H, W -0000000 SMR5 [R/W] B, H, W 000-0000 000568H Multifunction serial interface 4 00056CH 000570H 000574H RDR5 [R]/TDR5 [W]H, W -------0 00000000 ISMK5 [R/W] B, H, W 01111111 FCR51 [R/W] B, H, W ---00100 ISBA5 [R/W] B, H, W 00000000 FCR50 [R/W, R] B, H, W -0000000 000578H Multifunction serial interface 5 00057CH 000580H 000584H BT1TMR [R] B, H, W 00000000 00000000 ⎯ BT1STC [R/W] B 00000000 BT1TMCR [R/W] B, H, W 00000000 00000000 ⎯ BT1PDUT/BT1PRLH/BT1DTBF [R/W] H, W XXXXXXXX XXXXXXXX ⎯ (Reserved) BT2TMCR [R/W] B, H, W 00000000 00000000 ⎯ BT2PDUT/BT2PRLH/BT2DTBF [R/W] H, W XXXXXXXX XXXXXXXX ⎯ (Reserved) (Continued) 47 Base timer 2 Base timer 1 000588H 00058CH 000590H 000594H BT1PCSR/BT1PRLL [R/W] H, W XXXXXXXX XXXXXXXX BT2TMR [R] B, H, W 00000000 00000000 ⎯ BT2STC [R/W] B 00000000 000598H 00059CH BT2PCSR/BT2PRLL [R/W] H, W XXXXXXXX XXXXXXXX MB91470/480 Series Address 0005A0H 0005A4H Register +0 +1 +2 +3 BT3TMR [R] B, H, W 00000000 00000000 ⎯ BT3STC [R/W] B 00000000 BT3TMCR [R/W] B, H, W 00000000 00000000 ⎯ BT3PDUT/BT3PRLH/BT3DTBF [R/W] H, W XXXXXXXX XXXXXXXX ⎯ ⎯ PCR0 [R/W] B, H, W 00000000 PCR5 [R/W] B, H, W -0000000 PCRA [R/W] B, H, W ---00000 PCRE [R/W] B, H, W 00000000 PCRJ [R/W] B, H, W 00000000 PCRP [R/W] B, H, W --000000 PCR1 [R/W] B, H, W 00000000 PCR6 [R/W] B, H, W ------00 PCRB [R/W] B, H, W 00000000 PCRF [R/W] B, H, W 00000000 ⎯ PCRQ [R/W] B, H, W --000000 ⎯ ASR0 [R/W] H, W 00000000 00000000 *2 ASR1 [R/W] H, W XXXXXXXX XXXXXXXX *2 ASR2 [R/W] H, W XXXXXXXX XXXXXXXX *2 ⎯ ACR0 [R/W] H, W 1111XX-- --000000 *2 ACR1 [R/W] H, W XXXXXX-- --XXXXXX *2 ACR2 [R/W] H, W XXXXXX-- --XXXXXX *2 PCR2 [R/W] B, H, W 00000000 PCR8 [R/W] B, H, W 00000000 PCRC [R/W] B, H, W 00000000 PCRG [R/W] B, H, W --000000 PCRL [R/W] B, H, W -----000 PCRR [R/W] B, H, W --000000 PCR3 [R/W] B, H, W 00000000 PCR9 [R/W] B, H, W 00000000 PCRD [R/W] B, H, W ----0000 PCRH [R/W] B, H, W --000000 PCRM [R/W] B, H, W ----0000 PCRS [R/W] B, H, W --000000 Block Base timer 3 0005A8H 0005ACH 0005B0H to 0005FCH 000600H BT3PCSR/BT3PRLL [R/W] H, W XXXXXXXX XXXXXXXX (Reserved) (Reserved) 000604H 000608H 00060CH Pull-up resistor control register 000610H 000614H 000618H to 00063CH 000640H 000644H 000648H 00064CH (Reserved) External bus interface (Continued) 48 MB91470/480 Series Address 000650H 000654H 000658H 00065CH 000660H 000664H 000668H 00066CH 000670H 000674H 000678H 00067CH 000680H 000684H to 0007F8H 0007FCH 000800H to 000FFCH 001000H 001004H 001008H 00100CH 001010H 001014H 001018H Register +0 +1 ⎯ ⎯ ⎯ ⎯ AWR0 [R/W] H, W 0111---- 1111-111 *2 AWR2 [R/W] H, W XXXX---- XXXX-XXX *2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ CSER [R/W] B, H -----001 ⎯ ⎯ MODR [W] XXXXXXXX ⎯ DMASA0 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA0 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA2 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA2 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA3 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ⎯ ⎯ AWR1 [R/W] H, W XXXX---- XXXX-XXX *2 ⎯ +2 +3 Block External bus interface (Reserved) Mode register (Reserved) DMAC (Continued) 49 MB91470/480 Series Address 00101CH 001020H 001024H 001028H to 006FFCH 007000H 007004H 007008H 00700CH 007010H 007014H to 00701CH 007020H 007024H 007028H 00702CH 007030H 007034H 007038H 00703CH 007040H 007044H 007048H 00704CH Register +0 +1 +2 +3 DMADA3 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA4 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA4 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ⎯ FLCR [R/W, R] B ----X-0FLWC [R/W] B --11-011 ⎯ ⎯ ⎯ ⎯ WREN [R/W] H 00000000 00000000 ⎯ ⎯ ⎯ WA00 [R/W] W -------- ----XXXX XXXXXXXX XXXXXX-WD00 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WA01 [R/W] W -------- ----XXXX XXXXXXXX XXXXXX-WD01 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WA02 [R/W] W -------- ----XXXX XXXXXXXX XXXXXX-WD02 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WA03 [R/W] W -------- ----XXXX XXXXXXXX XXXXXX-WD03 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ⎯ ⎯ ⎯ Block DMAC (Reserved) Flash memory (Reserved) Wild register control block (Continued) 50 MB91470/480 Series Address 007050H 007054H 007058H 00705CH 007060H 007064H 007068H 00706CH 007070H 007074H 007078H 00707CH 007080H 007084H 007088H 00708CH 007090H 007094H 007098H 00709CH Register +0 +1 +2 +3 WA04 [R/W] W -------- ----XXXX XXXXXXXX XXXXXX-WD04 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WA05 [R/W] W -------- ----XXXX XXXXXXXX XXXXXX-WD05 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WA06 [R/W] W -------- ----XXXX XXXXXXXX XXXXXX-WD06 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WA07 [R/W] W -------- ----XXXX XXXXXXXX XXXXXX-WD07 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WA08 [R/W] W -------- ----XXXX XXXXXXXX XXXXXX-WD08 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WA09 [R/W] W -------- ----XXXX XXXXXXXX XXXXXX-WD09 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WA10 [R/W] W -------- ----XXXX XXXXXXXX XXXXXX-WD10 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WA11 [R/W] W -------- ----XXXX XXXXXXXX XXXXXX-WD11 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WA12 [R/W] W -------- ----XXXX XXXXXXXX XXXXXX-WD12 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WA13 [R/W] W -------- ----XXXX XXXXXXXX XXXXXX-WD13 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Block Wild register control block (Continued) 51 MB91470/480 Series (Continued) Address 0070A0H 0070A4H 0070A8H 0070ACH 0070B0H to 00BFFCH 00C000H to 00C0FCH 00C100H to 00C1FCH 00C200H to 00C3FCH 00C400H to 00FFFCH 010000H to 0FFFFCH Register +0 +1 +2 +3 WA14 [R/W] W -------- ----XXXX XXXXXXXX XXXXXX-WD14 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WA15 [R/W] W -------- ----XXXX XXXXXXXX XXXXXX-WD15 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ⎯ X-RAM (coefficient RAM) [R/W] 64 × 32-bit Y-RAM (variable RAM) [R/W] 64 × 32-bit I-RAM (instruction RAM) [R/W] 128 × 32-bit ⎯ (Reserved) MAC (Reserved) Wild register control block Block ⎯ (Reserved) *1 : The lower 16 bits (DTC15 to DTC0) of DMACA0 to DMACA4 cannot be accessed as bytes. *2 : Register whose initial value depends on the reset level. The initial values shown are for INITX = “L”. Notes : • Data is undefined in reserved or (⎯) area. • Do not execute read modify write (RMW) instruction on registers having a write-only bit. • The initial values are varied depending on the product series. Please refer to the hardware manual of MB91470/480 for more details. 52 MB91470/480 Series ■ INTERRUPT VECTOR Interrupt number Interrupt source Reset Mode vector System reserved System reserved System reserved System reserved System reserved Coprocessor absent trap Coprocessor error trap INTE instruction System reserved System reserved Step trace trap NMI request (tool) Undefined instruction exception NMI request External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 Reload timer 0 Reload timer 1 Base timer 0 (source 0/source 1) Multi-function serial interface 0 (UART transmission completed/reception completed/I2C status) Multi-function serial interface 1 (UART transmission completed/reception completed/I2C status) Base timer 1 (source 0/source 1) Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Hexadecimal 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B Interrupt level ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H TBR default address 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 28 29 1C 1D ICR12 ICR13 38CH 388H 000FFF8CH 000FFF88H (Continued) 53 MB91470/480 Series Interrupt number Interrupt source Base timer 2/3 (source 0/source 1) Up/down counter 0 DTTI0/DTTI1 DMAC0 (end/error) DMAC1 (end/error) DMAC2/3/4 (end/error) Multi-function serial interface 2 (UART transmission completed/reception completed/I2C status) Multi-function serial interface 3 (UART transmission completed/reception completed/I2C status) Multi-function serial interface 4 (UART transmission completed/reception completed/I2C status) Multi-function serial interface 5 (UART transmission completed/reception completed/I2C status) MAC PPG0/PPG1 PPG2/PPG3/PPG8/PPG9 PPG4/PPG5/PPG10/PPG11 PPG6/PPG7/PPG12/PPG13/PPG14/PPG15 Wave form generator 0/3 (underflow) Wave form generator 1/4 (underflow) Wave form generator 2/5 (underflow) Timebase timer overflow External interrupt 8/9/10/11/12/13/14/15 Free-run timer 0/3 (compare clear) Free-run timer 0/3 (zero detection) Free-run timer 1/4 (compare clear) Free-run timer 1/4 (zero detection) Free-run timer 2/5 (compare clear) Free-run timer 2/5 (zero detection) 8/10-bit A/D converter 2 8/10-bit A/D converter 0/ 12-bit A/D converter 3 Decimal 30 31 32 33 34 35 Hexadecimal 1E 1F 20 21 22 23 Interrupt level ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 Offset TBR default address 000FFF84H 000FFF80H 000FFF7CH 000FFF78H 000FFF74H 000FFF70H 384H 380H 37CH 378H 374H 370H 36 24 ICR20 36CH 000FFF6CH 37 25 ICR21 368H 000FFF68H 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH (Continued) 54 MB91470/480 Series (Continued) Interrupt number Interrupt source 8/10-bit A/D converter 1/ 12-bit A/D converter 4 ICU0/ICU1/ICU4/ICU5 (capture) ICU2/ICU3/ICU6/ICU7 (capture) OCU0/OCU1/OCU6/OCU7 (match) OCU2/OCU3/OCU8/OCU9 (match) OCU4/OCU5/OCU10/OCU11 (match) Interrupt delay source bit System reserved (Used by REALOS) System reserved (Used by REALOS) System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Used by INT instruction Decimal 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 to 255 Hexadecimal 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 to FF Interrupt level ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Offset TBR default address 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H 000FFEF4H 000FFEF0H 000FFEECH 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH to 000FFC00H 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H 2F4H 2F0H 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH to 000H 55 MB91470/480 Series ■ PIN STATUS IN EACH CPU STATE Terms used as the status of pins mean as follows. • Input enabled Means that the input function can be used. • Input fixed to “0” A state of a pin, in which "0" is transmitted to internal circuitry, with the external input shut off by the input gate adjacent to the pin. • Output Hi-Z Means to place a pin in a high impedance state by disabling the pin driving transistor from driving. • Output storage Means to output the state existing immediately prior to entering this mode. That is, to output according to an internal resource with an output when it is operating or to preserve an output when the output is provided, for example, as a port. • Preserving the previous state Means to be able to output or input the state existing immediately prior to entering this mode. 56 MB91470/480 Series • List of pin status Pin name P00 to P07 P10 to P17 P20 to P27 P30 to P37 P50 to P52 P53 P54 P55, P56 P60 P61 NMIX P80 to P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 PA0 to PA4 Function D16 to D23 D24 to D31 A00 to A07 A08 to A15 CS0X to CS2X ASX RDX WR0X, WR1X SYSCLK RDY NMIX INT0 to INT3 INT4/PPG4 INT5/PPG5 INT6/PPG6 INT7/PPG7 INT8/PPG8 INT9/PPG9 INT10/PPG10 INT11/PPG11 INT12/PPG12 INT13/PPG13 INT14/PPG14 INT15/PPG15 ADTG0 to ADTG4 Output Hi-Z/ Output Hi-Z/ Input disabled Input disabled Retention of the Retention of the immediately immediately prior state prior state Output Hi-Z/ Input “0” fixed Output Hi-Z/ Output Hi-Z/ Input disabled Input enabled Input enabled Input enabled Input enabled (only when external interrupt is enabled) Input enabled Input enabled Input enabled Input enabled Input enabled Output Hi-Z/ Output Hi-Z/ Input disabled Input disabled Retention of the Retention of the immediately immediately prior state prior state Output Hi-Z/ Input “0” fixed During initialization INITX = “L”* 1 INITX = “H”* 2 In sleep mode In stop mode HIZ = 0 HIZ = 1 PB0 to PB3 AN0-0 to AN0-3 PB4 to PB7 AN1-0 to AN1-3 PC0 PC1 PC2 PC3 PC4 PC5 PC6, PC7 AN2-0/SCK4 AN2-1/SIN4 AN2-2/SOT4 AN2-3/SCK5 AN2-4/SIN5 AN2-5/SOT5 AN2-6, AN2-7 (Continued) 57 Output Hi-Z/ Output Hi-Z/ Input disabled Input disabled Retention of the Retention of the immediately immediately prior state prior state Output Hi-Z/ Input “0” fixed MB91470/480 Series (Continued) Pin name Function During initialization INITX = “L”* 1 INITX = “H”* 2 In sleep mode In stop mode HIZ = 0 HIZ = 1 PD0 to PD3 AN2-8 to AN2-11 PE0 to PE3 PE4 to PE7 PF0 PF1 to PF6 PG0, PG3 PG1, PG4 PG2, PG5 PH0, PH3 PH1, PH4 PH2, PH5 PJ0, PJ2, PJ4, PJ6 PJ1, PJ3, PJ5, PJ7 PL0 PL1 PL2 AN3-0 to AN3-3 AN4-0 to AN4-3 CLKPOUT GPIO SCK0, SCK1 SIN0, SIN1 SOT0, SOT1 SCK2, SCK3 SIN2, SIN3 SOT2, SOT3 TIN0 to TIN3 TOUT0 to TOUT3 AIN0 BIN0 ZIN0 Output Hi-Z/ Output Hi-Z/ Input disabled Input disabled Output Hi-Z/ Output Hi-Z/ Input disabled Input disabled Output Hi-Z/ Output Hi-Z/ Input disabled Input disabled Output Hi-Z/ Output Hi-Z/ Input disabled Input disabled Output Hi-Z/ Output Hi-Z/ Input disabled Input disabled Output Hi-Z/ Output Hi-Z/ Input disabled Input disabled Retention of the Retention of the Output Hi-Z/ immediately immediately Input “0” fixed prior state prior state Retention of the Retention of the Output Hi-Z/ immediately immediately Input “0” fixed prior state prior state Retention of the Retention of the Output Hi-Z/ immediately immediately Input “0” fixed prior state prior state Retention of the Retention of the Output Hi-Z/ immediately immediately Input “0” fixed prior state prior state Retention of the Retention of the Output Hi-Z/ immediately immediately Input “0” fixed prior state prior state Retention of the Retention of the Output Hi-Z/ immediately immediately Input “0” fixed prior state prior state Retention of the Retention of the Output Hi-Z/ immediately immediately Input “0” fixed prior state prior state PM0 to PM3 PPG0 to PPG3 PP0 to PP3 PP4 PP5 PQ0 to PQ5 PR0 to PR3 PR4 PR5 PS0 to PS5 IC0 to IC3 CKI0 DTTI0 RTO0 to RTO5 IC4 to IC7 CKI1 DTTI1 RTO6 to RTO11 Output Hi-Z/ Output Hi-Z/ Input disabled Input disabled Output Hi-Z/ Output Hi-Z/ Input disabled Input disabled Retention of the Retention of the Output Hi-Z/ immediately immediately Input “0” fixed prior state prior state *1 : INITX = “L” : Indicates the pin status with INITX remaining at the “L” level. *2 : INITX = “H” : Indicates the pin status existing immediately after INITX transition from “L” to “H” level. 58 MB91470/480 Series • List of pin status (external bus mode) Pin name P00 to P07 P10 to P17 P20 to P27 P30 to P37 P50 to P52 P53 P54 P55, P56 P60 P61 Function D16 to D23 D24 to D31 A00 to A07 A08 to A15 CS0X to CS2X ASX RDX WR0X, WR1X SYSCLK RDY Input disabled Input disabled Input “0” fixed Output Hi-Z Output Hi-Z Retention of the Retention of the Output Hi-Z immediately immediately prior state prior state During initialization INITX = “L”* 1 INITX = “H”* 2 In sleep mode In Stop mode HIZ = 0 HIZ = 1 *1 : INITX = “L” : Indicates the pin status with INITX remaining at the “L” level. *2 : INITX = “H” : Indicates the pin status existing immediately after INITX transition from “L” to “H” level. 59 MB91470/480 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Power supply voltage*1 Analog power supply voltage*1,*2,*6 Analog reference voltage*7 Input voltage* 1 Symbol VCC AVCC10 AVCC12 AVRHn VI VIA VO IOL IOLAV ΣIOL ΣIOLAV IOH IOHAV ΣIOH ΣIOHAV PD TSTG Rating Min VSS − 0.5 VSS − 0.5 VSS − 0.5 VSS − 0.3 VSS − 0.3 VSS − 0.3 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ −55 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VCC + 0.3 AVCC + 0.3 VCC + 0.3 10 4 12 100 50 −10 −4 −12 −100 −50 800 +125 Unit V V V V V V mA mA mA mA mA mA mA mA mA mA mW °C Remarks Analog pin input voltage*1 Output voltage*1 “L” level maximum output current*3 “L” level average output current*4 “L” level total maximum output current “L” level total average output current*5 “H” level maximum output current*3 “H” level average output current *4 “H” level total maximum output current “H” level total average output current*5 Power consumption Storage temperature Except port Q0 to Q5 and S0 to S5 Port Q0 to Q5 and S0 to S5 Except port Q0 to Q5 and S0 to S5 Port Q0 to Q5 and S0 to S5 *1 : The parameter is based on VSS = AVSS10 = AVSS12 = 0 V. *2 : Be careful not to exceed VCC + 0.3 V, for example, when the power is turned on. Be careful to set AVCC10, AVCC12 equal VCC, for example, when the power is turned on. *3 : The maximum output current is the peak value for a single pin. *4 : The average output is the average current for a single pin over a period of 100 ms. *5 : The total average output current is the average current for all pins over a period of 100 ms. *6 : AVCC10 is the analog supply voltage for the 8/10-bit A/D converter, and AVCC12 is the analog supply voltage for the 12-bit A/D converter. *7 : AVRHn=AVRH0/AVRH1/AVRH2 are the analog reference voltage for the 8/10-bit A/D converter, and AVRH3/ AVRH4 are the analog reference voltage for the 12-bit A/D converter. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 60 MB91470/480 Series 2. Recommended Operating Conditions (VSS = AVSS10 = AVSS12 = 0.0 V) Parameter Power supply voltage Symbol VCC AVCC10 Analog power supply voltage AVCC12 AVRH0 AVRH1 Analog reference voltage AVRH2 AVRH3 AVRH4 (-) Analog input signal voltage range (+) Analog input signal voltage range ANINN-ANINP voltage difference ANINN ANINP ANINN− ANINP VSS + 4.0 AVSS10 AVSS10 AVSS10 AVSS12 AVSS12 AVSS12 AVSS12 ⎯ VSS + 5.5 AVCC10 AVCC10 AVCC10 AVCC12 AVCC12 AVCC12/2 AVCC12 AVCC12/4 + 70 Operating temperature TA − 40 + 85 * : The remaining rating values assume four-layer PCB. Note : During power-on, it takes approximately 600 µs for the internal power supply to stabilize after the VCC power supply has stabilized. Continue to assert the INITX pin during this period. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. °C V V V V V V V V V When mounted on single-layer PCB* When mounted on four-layer PCB* For all 12-bit A/D converters (common use) (under differential mode) Value Min 4.0 VSS + 4.0 Max 5.5 VSS + 5.5 Unit V V For all 8/10-bit A/D converter (common use) For all 12-bit A/D converter (common use) For 8/10-bit A/D converter 0 For 8/10-bit A/D converter 1 For 8/10-bit A/D converter 2 For 12-bit A/D converter 3 For 12-bit A/D converter 4 Remarks 61 MB91470/480 Series 3. DC Characteristics (VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V) Parameter Symbol VIH “H” level input voltage Pin CMOS input pin CMOS hysteresis input pin CMOS input pin CMOS hysteresis input pin Conditions ⎯ ⎯ ⎯ ⎯ Value Min VCC × 0.7 VCC × 0.8 VSS Typ ⎯ ⎯ ⎯ ⎯ Max VCC Unit V Remarks VIHS VCC VCC × 0.3 VCC × 0.2 V VIL “L” level input voltage V VILS VSS V VOH1 “H” level output voltage VOH2 Except port VCC = 5.0 V, Q0 to Q5 and IOH = 4 mA port S0 to S5 Port Q0 to Q5 and port S0 to S5 VCC = 5.0 V, IOH = 12 mA VCC − 0.5 ⎯ ⎯ V VCC − 0.5 ⎯ ⎯ V VOL1 “L” level output voltage VOL2 Input leak current Pull-up resistance Except port VCC = 5.0 V, Q0 to Q5 and IOL = 4 mA port S0 to S5 Port Q0 to Q5 and port S0 to S5 ⎯ INITX, pull-up pin VCC = 5.0 V, IOL = 12 mA VCC = 5.0 V, VSS < VI < VCC ⎯ ⎯ ⎯ VSS + 0.4 V ⎯ −5 ⎯ ⎯ ⎯ 50 VSS + 0.4 ⎯ ⎯ V µA kΩ When the multiply and mA accumulate unit is not used. When the multiply and mA accumulate unit is used. (Continued) ILI RPULL Power supply current ICC VCC Flash memory VCC = 5.0 V, fC = 20 MHz, PLL × 4, CLKB = 80 MHz CLKP = 40 MHz CLKT = 40 MHz ⎯ 100 ⎯ ⎯ 140 ⎯ 62 MB91470/480 Series (Continued) (VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V) Symbol Pin Conditions Value Min Typ Max Unit Remarks Parameter ICC VCC MASK ROM VCC = 5.0 V, fC = 20 MHz, PLL × 4, CLKB = 80 MHz CLKP = 40 MHz CLKT = 40 MHz ⎯ 65 ⎯ When the multiply and mA accumulate unit is not used. When the multiply and mA accumulate unit is used. In sleep mode (When multiplication mA and addition calculator circuit is not used.) In sleep mode (When multiplication mA and addition calculator circuit is used.) µA µA In stop mode In stop mode ⎯ 105 ⎯ Power supply current ICCS VCC ⎯ VCC = 5.0 V, fC = 20 MHz, PLL × 4, CLKB = 80 MHz CLKP = 40 MHz CLKT = 40 MHz ⎯ 50 ⎯ 80 ⎯ ICCH VCC VCC = 5.0 V, TA = + 25 °C VCC = 5.0 V, TA = + 85 °C ⎯ ⎯ 350 1500 ⎯ ⎯ Input capacitance CIN Other than VCC, VSS, AVSS12, AVSS10, AVCC12, AVCC10, AVRH0, AVRH1, AVRH2, AVRH3, AVRH4 ⎯ ⎯ 5 15 pF 63 MB91470/480 Series 4. Flash Memory Write/Erase Characteristics Parameter Sector erase time (8 Kbytes sectors) Word write time Chip write time Erase/write cycle Flash memory data hold time Conditions VCC = 5.0 V, TA = + 25 °C VCC = 5.0 V, TA = + 25 °C VCC = 5.0 V, TA = + 25 °C ⎯ ⎯ Value Min ⎯ ⎯ ⎯ 10000 10 Typ 0.5 6 1.8 ⎯ ⎯ Max 2.0 100 29.5 ⎯ ⎯ Unit s µs s cycle year Remarks Not including time for internal writing before deletion. Not including system-level overhead time. Not including system-level overhead time. 64 MB91470/480 Series 5. AC Characteristics (1) Clock Timing (VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V) Parameter Sym- Pin bol Name X0 X1 ⎯ Clock cycle time tC X0 X1 100 ⎯ 50*2 Condition Value Min Typ Max Unit Remarks Clock frequency fC 10*2 ⎯ 20 When using the PLL within the MHz self-oscillating range, set the multiplier so that the internal clock does not exceed ns the internal operating clock frequency. MHz CPU MHz Peripheral MHz External bus ns ns ns CPU Peripheral External bus fCP Internal operating clock frequency fCPP fCPT tCP Internal operating clock cycle time tCPP tCPT *1 : The values assume a gear cycle of 1/16. ⎯ ⎯ When 20 MHz is input as the X0 clock frequency and the oscillator circuit PLL system is set to × 4 multiplication 5*1 5*1 5*1 12.5 25 25 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 80 40 40 200 200 200 *2 : When the PLL is used, the PLL multiplication rate varies depending on the frequency of the clock input to the X0 and X1 pins. Set the PLL multiplication rate so that the PLL output clock frequency is in the range between 40 MHz and 80 MHz. PLL Multiplication Rate PLL output clock frequency when X0 = 10 MHz PLL output clock frequency when X0 = 20 MHz 1 2 3 4 40 MHz 5 50 MHz 6 60 MHz 7 70 MHz 8 80 MHz (Setting not allowed) (Setting not allowed) 40 MHz 60 MHz 80 MHz (Setting not allowed) • Conditions for measuring the clock timing ratings tC 0.8 VCC Output pin C = 50 pF 65 MB91470/480 Series • Operation assurance range VCC (V) Power supply voltage 5.5 4.0 fCP (MHz) 0 0.31 80 but the upper limit of fCPT/fCPP is 40 MHz. Internal clock • Internal clock setting range (MHz) 80 CPU (CLKB) : Internal clock Peripheral (CLKP) External bus (CLKT) : 40 5 Oscillation input clock fC = 20 MHz (PLL multiplied by 4) 16 :16 2:2 1:2 CPU : Divided ratio for peripherals/external bus. Notes : • When the PLL is used, the external clock input should be in the range of 10 MHz to 20 MHz. • Treat the PLL oscillation stabilization time as > 600 µs • Set the internal clock gear setting to within the values shown in the clock timing ratings table. 66 MB91470/480 Series (2) Clock Output Timing (VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Cycle time SYSCLK↑→ SYCSCLK↓ SYSCLK↓→ SYCSCLK↑ Symbol Pin Name tCYC tCHCL tCLCH SYSCLK ⎯ Condition Value Min tCPT tCYC/2 − 5 tCYC/2 − 5 Max ⎯ tCYC/2 + 5 tCYC/2 + 5 Unit Remarks ns ns ns *1 *2 *1 : tCYC is the frequency of one clock cycle including the gear cycle. *2 : The following ratings are for the gear ratio set to × 2. For the ratings when the gear ratio is set to 1/4 and 1/8, can be calculated by substituting 1/4 or 1/8 for n respectively in the following equation. (1/2 × 1/n) × tCYC-5 Note : For tCPT (internal clock cycle time) , refer to “(1) Clock Timing”. tCYC tCHCL VOH SYSCLK VOL tCLCH VOH (3) PLL Oscillation stabilization time (LOCK UP TIME) (VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V, TA = − 40 °C to + 85 °C) Parameter PLL Oscillation stabilization wait time (LOCK UP TIME) Symbol tLOCK* Pin Name ⎯ Condition ⎯ Value Min 600 Max ⎯ Unit µs * : The length of time to wait for the PLL oscillations to stabilize. 67 MB91470/480 Series (4) Reset Input Ratings (VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V, TA = − 40 °C to + 85 °C) Parameter INITX input time (at power-on and stop mode) INITX input time (other than the above) Symbol Pin Name Condition Value Min Oscillation time of oscillator tc × 10 tc × 10 Max ⎯ ⎯ Unit ns tINTL INITX ⎯ ns Notes : • It takes approximately 600 µs for the internal power to stabilize after the power supply has stabilized. Continue to input “L” level to the INITX pin during this period. • For tCPT (internal clock cycle time) , refer to “(1) Clock Timing”. tINTL INITX 0.2 VCC 68 MB91470/480 Series (5) Normal Bus Access Read/Write Operation (VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V, TA = − 40 °C to + 85 °C) Value CondiParameter Symbol Pin Name Unit Remarks tion Min Max ASX setup ASX hold CS0X to CS2X setup CS0X to CS2X hold tASLCH tCHASH tCSLCH tCHCSH tASCH Address setup tASRL tASWL tCHAX Address hold tRHAX tWHAX Valid address → Valid data input time RDX delay time RDX ↓ → Valid data input time Data setup → RDX ↑ time RDX ↑ → Data hold time RDX minimum pulse width WR0X, WR1X delay time Data setup → WR0X, WR1X ↑ time WR0X, WR1X ↑ → Data hold time WR0X, WR1X minimum pulse width tAVDV tCHRL tCHRH tRLDV tDSRH tRHDX tRLRH tCHWL tCHWH tDSWH tWHDX tWLWH RDX SYSCLK RDX WR0X, WR1X D31 to D16 ⎯ ⎯ RDX D31 to D16 ⎯ SYSCLK ASX SYSCLK CS0X to CS2X SYSCLK A15 to A00 RDX A15 to A00 WR0X, WR1X A15 to A00 SYSCLK A15 to A00 RDX A15 to A00 WR0X, WR1X A15 to A00 A15 to A00 D31 to D16 SYSCLK RDX ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 3 3 3 3 3 3 3 3 3 3 ⎯ ⎯ ⎯ ⎯ 18 0 tCYC − 5 ⎯ ⎯ tCYC ⎯ 3 ⎯ tCYC − 5 ⎯ ⎯ ns ns (Continued) ⎯ 1/2 × tCYC + 10 ⎯ 1/2 × tCYC + 10 ⎯ ⎯ ⎯ 1/2 × tCYC + 10 ⎯ ⎯ 3/2 × tCYC − 7 10 10 tCYC − 5 ⎯ ⎯ ⎯ 10 10 ⎯ ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *1 *1 *2 WR0X, WR1X 69 MB91470/480 Series (Continued) *1 : When the bus timing is delayed by an automatic wait instruction or RDY input, add the time (tCYC × the number of delay cycles added) to this rating. *2 : The following ratings are for the gear ratio set to × 2. For the ratings when the gear ratio is set to between 1/3 and 1/16, substitute the value between 1/3 and 1/16 for n in the following equation. Formula : 3/ (2n) × tCYC−15 Note : Load capacitance C = 50 pF tCYC SYSCLK VOH VOH tASLCH ASX VOL tCHASH VOH tCSLCH CS0X to CS2X tCHCSH VOH VOL tASCH A15 to A00 VOH VOL tCHAX VOH VOL tCHRL tRLRH RDX tASRL tRLDV tAVDV D31 to D16 (Read) VOH VOL tDSRH VOL tCHRH VOH tRHAX tRHDX VOH VOL tCHWL tWLWH WR0X, WR1X tASWL tCHWH VOH tWHAX tDSWH tWHDX VOH VOL D31 to D16 (Write) VOH VOL 70 MB91470/480 Series (6) Multiplex Bus Access Read/Write Operation (VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V, TA = − 40 °C to + 85 °C) Parameter A15 to A00 address setup time → SYSCLK ↑ SYSCLK ↑ → A15 to A00 address Hold Time A15 to A00 address setup time → ASX ↑ ASX ↑ → A15 to A00 address hold time Symbol tASCH tCHAX tASASH tASHAX Pin Name Condition Value Min 3 3 ⎯ ASX, D31 to D16 12 tCYC − 5 ⎯ tCYC + 5 ns ns Max ⎯ 1/2 × tCYC + 10 Unit ns ns SYSCLK, D31 to D16 Notes : • This rating is not guaranteed when the CSX → RDX/WRX Setup Delay setting by AWR : bit1 is “0”. • Normal bus interface ratings are applicable except this rating. • For tCYC (cycle time), refer to “(2) Clock Output Timing”. tCYC VOH VOH SYSCLK AS VOL tASASH tASCH VOH tASHAX tCHAX D31 to D16 (A15 to A00) VOH VOL 71 MB91470/480 Series (7) Ready Input Timing (VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V, TA = − 40 °C to + 85 °C) Parameter RDY setup time → SYSCLK ↑ SYSCLK ↑ → RDY hold time Symbol tRDYS tRDYH Pin Name Condition Value Min 18 ⎯ 0 ⎯ ns Max ⎯ Unit ns SYSCLK, RDY tCYC VOH VOH VOL SYSCLK VOL tRDYS tRDYH tRDYS tRDYH RDY (When WAIT is used) VOL VOH VOL VOH RDY (When WAIT is not used) VOH VOL VOH VOL 72 MB91470/480 Series (8) UART Timing (VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Serial clock cycle time SCK↓→SOT delay time Valid SIN→SCK↑ SCK↑→ Valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK↓→SOT delay time Valid SIN→SCK↑ SCK↑→ Valid SIN hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin SCK0 to SCK5 SCK0 to SCK5 SOT0 to SOT5 SCK0 to SCK5 SIN0 to SIN5 SCK0 to SCK5 SIN0 to SIN5 SCK0 to SCK5 SCK0 to SCK5 SCK0 to SCK5 SOT0 to SOT5 SCK0 to SCK5 SIN0 to SIN5 SCK0 to SCK5 SIN0 to SIN5 External shift clock mode Conditions Value Min 8 × tCYCP −50 Internal shift clock mode 50 0 4 × tCYCP 4 × tCYCP ⎯ 50 50 Max ⎯ +50 ⎯ ⎯ ⎯ ⎯ 50 ⎯ ⎯ Unit ns ns ns ns ns ns ns ns ns Notes : • The above ratings are the AC characteristics for CLK synchronous mode. • tCYCP indicates the peripheral clock cycle time. 73 MB91470/480 Series • Internal shift clock mode tSCYC SCK0 to SCK5 VOH VOL VOL tSLOV SOT0 to SOT5 VOH VOL tIVSH VOH VOL tSHIX VOH VOL SIN0 to SIN5 • External shift clock mode tSLSH VOH tSHSL SCK0 to SCK5 VOL VOL VOL tSLOV SOT0 to SOT5 VOH VOL tIVSH VOH VOL tSHIX VOH VOL SIN0 to SIN5 74 MB91470/480 Series (9) Free-run Timer Clock, Up/Down Counter, Base Timer, and External Interrupt Input Timing (VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Free-run timer input clock pulse width Up-down counter input pulse width Base timer input pulse width External interrupt input pulse width Symbol Pin Name CKI0, CKI1 AIN0 BIN0 ZIN0 TIN0 to TIN3 INT0 to INT15 Condition Value Min 4 × tCYCP 4 × tCYCP ⎯ 4 × tCYCP 4 × tCYCP 1.0 ⎯ ⎯ ⎯ ns ns µs Max ⎯ ⎯ Unit ns ns tTIWH tTIWL Note : tCYCP indicates the peripheral clock cycle time. tTIWH VOH CKI0, CKI1 AIN0, BIN0, ZIN0 TIN0 to TIN3 INT0 to INT15 VOH tTIWL VOL VOL 75 MB91470/480 Series (10) Trigger Input Timing (VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Input Capture trigger input Base timer trigger input A/D activation trigger input Symbol tICWH tICWL tTGINWH tTGINWL tADTGWH tADTGWL Pin Name IC0 to IC7 TIN0 to TIN3 ADTG0 to ADTG4 ⎯ Condition Value Min 5 × tCYCP 4 × tCYCP 5 × tCYCP Max ⎯ ⎯ ⎯ Unit ns ns ns Note : tCYCP indicates the peripheral clock cycle time. tICWH tTGINWH tADTGWH VOH IC0 to IC7 TIN0 to TIN 3 ADTG0 to ADTG4 VOH tICWL tTGINWL tADTGWL VOL VOL 76 MB91470/480 Series (11) I2C Timing a. Master Mode (VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V, TA = − 40 °C to + 85 °C) Parameter SCL clock frequency “L” width of the SCL clock “H” width of the SCL clock Bus free time between STOP and START conditions SCL↓→ SDA output delay time Setup time for a repeated START condition SCL↑→SDA↓ Hold time for a repeated START condition SDA↓→SCL↓ Setup time for STOP condition SCL↑→SDA↑ SDA Data input hold time (vs. SCL↓) SDA Data input setup time (vs. SCL↑) Symbol Condition fSCL tLOW tHIGH Standard Mode Min 0 4.7 4.0 Max 100 ⎯ ⎯ ⎯ 5 × tCYCP *1 ⎯ Fast Mode *3 Min 0 1.3 0.6 Max 400 ⎯ ⎯ ⎯ 5 × tCYCP *1 ⎯ Unit kHz ms ms Remarks tBUS 4.7 ⎯ 4.7 1.3 ⎯ 0.6 ms tDLDAT ns tSUSTA R=1 kΩ, C=50 pF*4 ms The first clock pulse is generated after this. tHDSTA 4.0 ⎯ 0.6 ⎯ ms tSUSTO 4.0 2 × tCYCP *1 250 ⎯ ⎯ ⎯ 0.6 2 × tCYCP *1 100 *2 ⎯ ⎯ ⎯ ms tHDDAT tSUDAT ms ns *1 : tCYCP indicates the peripheral clock cycle time. *2 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSUDAT ≥ 250 ns must then be met. If a device does not extend the “L” period of the SCL signal, it is necessary to output the next piece of data to the SDA line 1250 ns (SDA and SCL rising Max time + tSUDAT) before the SCL line is released. *3 : For use at over 100 kHz, set the resource clock to at least 6 MHz. *4 : R and C are the pull-up resistance and load capacitance of the SCL and SDA lines. 77 MB91470/480 Series b. Slave Mode (VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V, TA = − 40 °C to + 85 °C) Parameter SCL clock frequency “L” width of the SCL clock “H” width of the SCL clock Bus free time between STOP and START conditions SCL ↓ → SDA output delay time Setup time for a repeated START condition SCL ↑ → SDA ↓ Hold time for a repeated START condition SDA ↓ → SCL ↓ Setup time for STOP condition SCL ↑ → SDA ↑ SDA Data input hold time (vs. SCL ↓) SDA Data input setup time (vs. SCL ↑) Symbol Condition fSCL tLOW tHIGH Standard Mode Min 0 4.7 4.0 Max 100 ⎯ ⎯ ⎯ 5 × tCYCP *1 Fast Mode *3 Min 0 1.3 0.6 Max 400 ⎯ ⎯ ⎯ 5 × tCYCP *1 Unit kHz µs µs µs ns Remarks tBUS 4.7 ⎯ 1.3 ⎯ tDLDAT tSUSTA R=1 kΩ, C=50 pF*4 4.7 ⎯ 0.6 ⎯ µs The first clock pulse is generated after this. tHDSTA 4.0 ⎯ 0.6 ⎯ µs tSUSTO 4.0 ⎯ 0.6 ⎯ µs tHDDAT 2 × tCYCP *1 ⎯ 2 × tCYCP *1 ⎯ µs tSUDAT 250 ⎯ 100 *2 ⎯ ns *1 : tCYCP indicates the peripheral clock cycle time. *2 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSUDAT ≥ 250 ns must then be met. If a device does not extend the “L” period of the SCL signal, it is necessary to output the next piece of data to the SDA line 1250 ns (SDA and SCL rising Max time + tSUDAT) before the SCL line is released. *3 : For use at over 100 kHz, set the resource clock to at least 6 MHz. *4 : R and C are pull-up resistance and load capacitance of the SCL and SDA lines. 78 MB91470/480 Series 6. Electrical Characteristics for the A/D Converter (1) 8/10-bit A/D Converter (VCC = 4.0 V to 5.5 V, AVRHn = 4.0 V to 5.5 V, VSS = AVSS10 = 0 V, TA = − 40 °C to + 85 °C) Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Conversion time*1 Analog port input current Analog input voltage Reference voltage Power supply current (Analog + digital) Reference voltage supply current (between AVRH and AVSS) Analog input capacitance Interchannel disparity Symbol ⎯ ⎯ ⎯ ⎯ VOT Pin Name ⎯ ⎯ ⎯ ⎯ Value Min ⎯ −4 − 3.5 −3 Typ ⎯ ⎯ ⎯ ⎯ Max 10 +4 + 3.5 +3 Unit bit LSB LSB LSB Remarks When AVRHn = AN0-0 to AN0-3 5.0 V AN1-0 to AN1-3 AVSS10−3.5 AVSS10+0.5 AVSS10+4.5 LSB AN2-0 to AN2-11 AN0-0 to AN0-3 AN1-0 to AN1-3 AVRHn−5.5 AN2-0 to AN2-11 ⎯ AN0-0 to AN0-3 AN1-0 to AN1-3 AN2-0 to AN2-11 AN0-0 to AN0-3 AN1-0 to AN1-3 AN2-0 to AN2-11 AVRHn AVCC10 AVCC10 AVRHn 1.2 ⎯ AVRHn−1.5 ⎯ ⎯ AVRHn+2.5 LSB ⎯ 10 µs µA VFST ⎯ IAIN VAIN ⎯ IA IAH*2 IR AVSS10 AVSS10 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2 ⎯ 1 ⎯ ⎯ ⎯ AVRHn AVCC10 ⎯ 5 ⎯ 5 12.5 V V mA µA For each 1 unit For each 1 unit, mA at AVRHn = 5.0 V AVSS10 = 0 V µA pF For each 1 unit, at stop mode IRH*2 ⎯ ⎯ AVRHn ⎯ AN0-0 to AN0-3 AN1-0 to AN1-3 AN2-0 to AN2-11 4 LSB *1 : When VCC = AVCC10 = 5.0 V and Machine clock = 33 MHz *2 : The current when the CPU is in stop mode and the A/D converter is not operating (at VCC = AVCC10 = AVRHn = 5.0 V) . Notes : • The above figures do not guarantee the accuracy between each unit. • Output impedance of the external circuit ≤ 2 kΩ. • AVRHn = AVRH0, AVRH1, and AVRH2 79 MB91470/480 Series (2) 12-bit A/D Converter (VCC = 4.0 V to 5.5 V, AVRHn = 4.0 V to 5.5 V, VSS = AVSS12 = 0 V, TA = − 40 °C to + 85 °C) Parameter Resolution Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Symbol ⎯ ⎯ ⎯ VOT VFST Pin Name ⎯ ⎯ ⎯ AN3-0 to AN3-3 AN4-0 to AN4-3 AN3-0 to AN3-3 AN4-0 to AN4-3 Value Min ⎯ −3.6 −3 Typ − 20 mV Typ − 20 mV 2.0 Conversion time ⎯ ⎯ 2.2 Analog port input current Analog input voltage Reference voltage Analog supply current (analog + digital) Reference voltage supply current (between AVRH and AVSS) Analog input capacitance Interchannel disparity IAIN VAIN ⎯ IA IAH* IR AN3-0 to AN3-3 AN4-0 to AN4-3 AN3-0 to AN3-3 AN4-0 to AN4-3 AVRHn AVCC12 AVCC12 AVRHn ⎯ AVSS12 AVSS12 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2 ⎯ 1 ⎯ ⎯ ⎯ ⎯ 10 AVRHn AVCC12 ⎯ 5 ⎯ 5 18 4 µs µA V V mA µA For each unit Typ ⎯ ⎯ ⎯ AVSS12 + 0.5 LSB AVRHn − 1.5 LSB ⎯ Max 12 + 3.6 +3 Typ + 20 mV Typ + 20 mV ⎯ Unit bit LSB LSB ⎯ ⎯ µs When machine clock = 33 MHz When machine clock = 40 MHz When AVRHn = 5.0 V Remarks For each unit, mA at AVRHn = 5.0 V, AVSS12 = 0 V µA pF LSB For each unit, at stop mode IRH* ⎯ ⎯ AVRHn ⎯ AN3-0 to AN3-3 AN4-0 to AN4-3 * : The current when the CPU is in stop mode and the A/D converter is not operating (at VCC = AVCC10 = AVRHn = 5.0 V) . Notes : • The above figures do not guarantee the accuracy between each unit. • Output impedance of the external circuit ≤ 2 kΩ • AVRHn = AVRH3, AVRH4 80 MB91470/480 Series • External impedance and sampling time of analog inputs • The A/D converter is fitted with a sample and hold circuit. If the external impedance is so high that there is not sufficient time for sampling, the internal sample and hold capacitor will not fully charge to the analog voltage, and the precision of the A/D conversion will be adversely affected. Therefore, in order to satisfy the A/D conversion precision specifications, either adjust the register values and operating frequency or reduce the external impedance so that the sampling time is greater than the minimum value as given by the relationship between external impedance and minimum sampling time. If you are still unable to hold enough sampling time, connect a capacitor of about 0.1 µF to the analog input pin. • Analog input circuit schematic R Analog input Comparator C During sampling : ON R 4.6 kΩ 1.0 kΩ C 12.5 pF 18.0 pF 8/10-bit A/D converter 12-bit A/D converter Note : The values are reference values. • To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. • The relationship between the external impedance and minimum sampling time (External impedance = 0 kΩ to 100 kΩ) 100 90 80 70 60 50 40 30 20 10 0 0 2 4 6 8/10-bit A/D converter 20 (External impedance = 0 kΩ to 20 kΩ) 8/10-bit A/D converter External impedance [kΩ] External impedance [kΩ] 18 16 14 12 10 8 6 4 2 0 0 0.4 0.8 1.2 12-bit A/D converter 12-bit A/D converter 8 10 12 14 1.6 2.0 2.4 2.8 3.2 Minimum sampling time [µs] Minimum sampling time [µs] • About errors • The relative error increases as the value of |AVRH − AVSS| decreases. 81 MB91470/480 Series • Definition of 8/10-bit A/D Converter Terms • Resolution • Linearity error : Analog variation that is recognized by the A/D converter. : Deviation between the line connecting zero transition point (0000000000←→0000000001) and full-scale transition point (1111111110←→1111111111) and actual conversion characteristics. • Differential linear error : Deviation from the ideal value of input voltage necessary to change the output code by ILSB. • Total Error : This error is the difference between actual and ideal values, including the zero transition error/full-scale transition error/linearity error. Linearity error FFFH FFEH {1 LSB (N − 1) + V OT} FFDH Differential linear error Actual conversion characteristic (N + 1)H Actual conversion characteristic Digital output Digital output (Measurement value) VFST Ideal characteristic NH 004H 003H 002H 001H (Measurement value) VNT (N − 1)H V(N+1)T (Measurement value) Actual conversion characteristic Ideal characteristic (N − 2)H VNT (Measurement value) VOT AVSS (Measurement value) Actual conversion characteristic Analog input AVRH AVSS Analog input AVRH VNT − {1 LSB × (N − 1) + VOT} [LSB] 1 LSB V (N+1) T − VNT Differential linear error in digital output N = − 1 [LSB] 1 LSB VFST − VOT 1 LSB = 1022 N : A/D converter digital output value VOT : Voltage at which digital output changes from 000H to 001H. VFST : Voltage at which digital output changes from 3FEH to 3FFH. VNT : Voltage at which digital output changes from (N − 1) H to NH. Linear error in digital output N = (Continued) 82 MB91470/480 Series (Continued) Total error 3FFH 1.5 LSB' 3FEH 3FDH Actual conversion characteristic {1 LSB' (N − 1) + 0.5 LSB'} Digital output 004H 003H 002H 001H 0.5 LSB' AVSS (Measurement value) VNT Actual conversion characteristic Ideal characteristic Analog input AVRH AVRH − AVSS [V] 1024 VNT − {1 LSB’ × (N − 1) + 0.5 LSB’} Total error of digital output N = 1 LSB’ N : A/D converter digital output value VNT : Voltage at which digital output changes from (N + 1) H to NH. VOT’ (ideal value) = AVSS + 0.5 LSB’ [V] VFST’ (ideal value) = AVRH − 1.5 LSB’ [V] 1 LSB’ (ideal value) = 83 MB91470/480 Series • Definition of 12-bit A/D Converter Terms • Resolution • Linearity error : Analog variation that is recognized by the A/D converter. : Deviation between the line connecting zero transition point (000000000000←→000000000001) and full-scale transition point (111111111110←→111111111111) and actual conversion characteristics. • Differential linear error : Deviation from the ideal value of input voltage necessary to the output code by ILSB. Linearity error FFFH FFEH {1 LSB (N − 1) + V OT} FFDH Differential linear error Actual conversion characteristic (N + 1)H Actual conversion characteristic Digital output Digital output (Measurement value) VFST Ideal characteristic NH 004H 003H 002H 001H (Measurement value) VNT (N − 1)H V(N+1)T (Measurement value) Actual conversion characteristic Ideal characteristic (N − 2)H VNT (Measurement value) VOT AVSS (Measurement value) Actual conversion characteristic Analog input AVRH AVSS Analog input AVRH VNT − {1 LSB’ × (N − 1) + VOT} [LSB] 1 LSB’ V (N+1) T − VNT Differential linear error in digital output N = − 1 [LSB] 1 LSB’ VFST − VOT 1 LSB = 4094 N : A/D converter digital output value VOT : Voltage at which digital output changes from 000H to 001H. VFST : Voltage at which digital output changes from FFEH to FFFH. VNT : Voltage at which digital output changes from (N − 1)H to NH. Linear error in digital output N = 84 MB91470/480 Series ■ ORDERING INFORMATION Part No. MB91F475PMC1-GE1 MB91F475BGL-GE1 MB91F478PMC1-GE1 MB91F478BGL-GE1 MB91F479PMC1-GE1 MB91F479BGL-GE1 MB91F487PMC-GE1 MB91482PMC-GE1 Package FPT-144P-M12 BGA-144P-M06 FPT-144P-M12 BGA-144P-M06 FPT-144P-M12 BGA-144P-M06 FPT-100P-M20 FPT-100P-M20 85 MB91470/480 Series ■ PACKAGE DIMENSIONS 100-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.50 mm 14.0 mm × 14.0 mm Gullwing Plastic mold 1.70 mm Max 0.65 g P-LFQFP100-14×14-0.50 (FPT-100P-M20) Code (Reference) 100-pin plastic LQFP (FPT-100P-M20) 16.00±0.20(.630±.008)SQ Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. * 14.00±0.10(.551±.004)SQ 75 51 76 50 0.08(.003) Details of "A" part INDEX 1.50 –0.10 .059 –.004 (Mounting height) 26 +0.20 +.008 100 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) 0˚~8˚ "A" (0.50(.020)) 0.60±0.15 (.024±.006) 1 25 0.50(.020) 0.20±0.05 (.008±.002) 0.08(.003) M 0.145±0.055 (.0057±.0022) C 2005 FUJITSU LIMITED F100031S-c-2-1 Dimensions in mm (inches). Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html (Continued) 86 MB91470/480 Series 144-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.40 mm 16.0 × 16.0 mm Gullwing Plastic mold 1.70 mm MAX 0.88 g P-LFQFP144-16×16-0.40 (FPT-144P-M12) Code (Reference) 144-pin plastic LQFP (FPT-144P-M12) 18.00±0.20(.709±.008)SQ +0.40 +.016 *16.00 –0.10 .630 –.004 SQ 108 73 Note 1) * : These dimensions include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 109 72 0.08(.003) Details of "A" part 1.50 –0.10 .059 –.004 +0.20 +.008 (Mounting height) INDEX 0~8˚ 144 37 "A" 0.60±0.15 (.024±.006) 0.10±0.05 (.004±.002) (Stand off) 0.25(.010) LEAD No. 1 36 +0.05 +.002 –.001 0.40(.016) 0.18±0.035 .007±.001 0.07(.003) M 0.145 –0.03 .006 C 2003 FUJITSU LIMITED F144024S-c-3-3 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html (Continued) 87 MB91470/480 Series (Continued) 144-ball plastic PFBGA Ball pitch Package width × package length Lead shape Sealing method Ball size Mounting height 0.80 mm 12.00 × 12.00 mm Soldering ball Plastic mold ∅0.45 mm 1.45 mm Max. 0.32 g (BGA-144P-M06) Weight 144-ball plastic PFBGA (BGA-144P-M06) 12.00±0.10(.472±.004) B 0.20(.008) S B 0.80(.031) REF 13 12 11 10 9 8 7 6 5 4 3 2 1 0.80(.031) REF A 12.00±0.10 (.472±.004) (INDEX AREA) 0.35±0.10 (.014±.004) (Stand off) 0.20(.008) S A 1.25±0.20 (.049±.008) (Seated height) S NMLKJHGFEDCBA INDEX 144-ø0.45±0.10 (144-ø.018±.004) ø0.08(.003) M SAB 0.10(.004) S C 2003 FUJITSU LIMITED B144006S-c-1-1 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 88 MB91470/480 Series ■ MAIN CHANGES IN THIS EDITION Page Section Change Results Changed the pin name as follows : PE0/AN3-0 → PE0/AN3-0/AN3-0P PE1/AN3-1 → PE1/AN3-1/AN3-0N PE2/AN3-2 → PE2/AN3-2/AN3-1P PE3/AN3-3 → PE3/AN3-3/AN3-1N PE7/AN4-3 → PE7/AN4-3/AN4-1N PE6/AN4-2 → PE6/AN4-2/AN4-1P PE5/AN4-1 → PE5/AN4-1/AN4-0N PE4/AN4-0 → PE4/AN4-0/AN4-0P Added the following description in the Function of PPG8, PPG9; (MB91480 series only) Added the following description in the Function of SCK4, SIN4, SOT4, SCK5, SIN5, SOT5; (MB91470 series only) Added the “• Notes upon power-on sequence” Changed in the figure In the figure of “Conditions for measuring the clock timing ratings”, deleted tCF, tCR and PWH, PWL and its range lines. Changed as follows in the “Operation assurance range” fCPS → fCP but the upper limit of fCPT/fCPP is 40 MHz. → but the upper limit of fCPT/fCPP is 40 MHz. Changed in the figure as follows : tCHAH → tCHAX 6 ■ PIN ASSIGNMENT • LQFP-144 (MB91470 series) 12 ■ PIN DESCRIPTIONS 14 25 27, 28 65 ■ ELECTRICAL CHARACTERISTICS 5. AC Characteristics (1) Clock Timing ■ HANDLING DEVICES ■ BLOCK DIAGRAM 66 71 ■ ELECTRICAL CHARACTERISTICS 5. AC Characteristics (6) Multiplex Bus Access Read/Write Operation ■ ELECTRICAL CHARACTERISTICS 6. Electrical Characteristics for the A/D converter ■ ORDERING INFORMATION 83 Changed in the figure of “Total error” Changed the part number MB91F487PMC1-GE1 → MB91F487PMC-GE1 85 The vertical lines marked in the left side of the page show the changes. 89 MB91470/480 Series The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. 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