MB95F118BWPV2

FUJITSU MICROELECTRONICS DATA SHEET DS07-12615-1Ea 8-bit Proprietary Microcontrollers CMOS F2MC-8FX MB95110B Series MB95116B/F118BS/F118BW/FV100D-101 ■ DESCRIPTION The MB95110B series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions. Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller. ■ FEATURES • F2MC-8FX CPU core Instruction set that is optimum to the controllers • Multiplication and division instructions • 16-bit arithmetic operation • Bit test branch instruction • Bit manipulation instructions etc. • Clock • Main clock • Main PLL clock • Sub clock (for dual clock product) • Sub PLL clock (for dual clock product) (Continued) Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://edevice.fujitsu.com/micom/en-support/ “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development. Copyright©2006-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2006.12 MB95110B Series (Continued) • Timer • 8/16-bit compound timer × 2 channels • 8/16-bit PPG × 2 channels • 16-bit PPG • Time-base timer • Watch prescaler (for dual clock product) • LIN-UART • Full duplex double buffer • Clock asynchronous (UART) or Clock synchronous (SIO) serial data transfer capable • UART/SIO • Full duplex double buffer • Clock asynchronous (UART) or Clock synchronous (SIO) serial data transfer capable • I2C* Built-in wake-up function • External interrupt • Interrupt by edge detection (rising, falling, or both edges can be selected) • Can be used to recover from low-power consumption (standby) modes. • 8/10-bit A/D converter • 8-bit or 10-bit resolution can be selected • Low-power consumption (standby) mode • Stop mode • Sleep mode • Watch mode (for dual clock product) • Time-base timer mode • I/O port: • The number of maximum ports • Single clock product : 39 ports • Dual clock product : 37 ports • Port configuration • General-purpose I/O ports (N-ch open drain) : 2 ports • General-purpose I/O ports (CMOS) : Single clock product : 37 ports Dual clock product : 35 ports • Flash memory security function Protects the content of Flash memory (Flash memory device only) * : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. 2 MB95110B Series ■ PRODUCT LINEUP Part number Parameter Type ROM capacity RAM capacity Reset output Option*1 Clock system Low voltage detection reset Selectable single/dual clock*2 MB95116B MASK ROM product 32 Kbytes 1 Kbyte No Single clock No Number of basic instructions : 136 Instruction bit length : 8 bits Instruction length : 1 to 3 bytes Data bit length : 1, 8, and 16 bits Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25MHz) Interrupt processing time : 0.6 μs (at machine clock frequency 16.25 MHz) • Single clock product : 39 ports (N-ch open drain : 2 ports, CMOS : 37 ports) • Dual clock product : 37 ports (N-ch open drain : 2 ports, CMOS : 35 ports) Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz) Reset generated cycle At main oscillation clock 10 MHz : Minimum 105 ms At sub oscillation clock 32.768 kHz (for dual clock product) : Minimum 250 ms Capable of replacing 3 bytes of ROM data Master/slave sending and receiving Bus error function and arbitration function Detecting transmitting direction function Start condition repeated generation and detection functions Built-in wake-up function Data transfer capable in UART/SIO Full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate generator NRZ type transfer format, error detected function LSB-first or MSB-first can be selected. Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable. Dedicated reload timer allowing a wide range of communication speeds to be set. Full duplex double buffer. Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable. LIN functions available as the LIN master or LIN slave. Dual clock MB95F118BS MB95F118BW Flash memory product 60 Kbytes 2 Kbytes CPU functions General-purpose I/O port Time-base timer Watchdog timer Wild register Peripheral functions I2C UART/SIO LIN-UART 8/10-bit A/D converter 8-bit or 10-bit resolution can be selected. (8 channels) (Continued) 3 MB95110B Series (Continued) Part number Parameter 8/16-bit compound timer (2 channels) MB95116B MB95F118BS MB95F118BW Each channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit timer × 1 channel”. Built-in timer function, PWC function, PWM function, capture function and square wave form output Count clock : 7 internal clocks and external clock can be selected. PWM mode or one-shot mode can be selected. Counter operating clock : 8 selectable clock sources Support for external trigger start Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG × 1 channel”. Counter operating clock : Eight selectable clock sources 16-bit PPG Peripheral functions 8/16-bit PPG (2 channels) Count clock : Four selectable clock sources (125ms, 250ms, 500ms, or 1s) Watch counter Counter value can be set from 0 to 63. (Capable of counting for 1 minute when (for dual clock product) selecting clock source 1 second and setting counter value to 60) Watch prescaler 4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s) (for dual clock product) External interrupt (8 channels) Interrupt by edge detection (rising, falling, or both edges can be selected) Can be used to recover from standby modes. Supports automatic programming, Embedded AlgorithmTM *3 Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of write/erase cycles (Minimum) : 10000 times Data retention time : 20 years Boot block configuration Erase can be performed on each block Block protection with external programming voltage Flash Security Feature for protecting the content of the Flash Sleep, stop, watch (for dual clock product) , and time-base timer Flash memory Standby mode *1 : For details of option, refer to “■ MASK OPTIONS”. *2 : Specify clock mode when ordering MASK ROM. *3 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc. Note : Part number of the evaluation products in MB95110B series is MB95FV100D-101. When using it, the MCU board (MB2146-301A) is required. 4 MB95110B Series ■ SELECT OF OSCILLATION STABILIZATION WAIT TIME (MASK ROM PRODUCT ONLY) For the MASK ROM product, you can set the mask option when ordering MASK ROM to select the initial value of main clock oscillation stabilization wait time from among the following four values. Note that the evaluation and Flash memory products are fixed their initial value of main clock oscillation stabilization wait time at the maximum value. Selection of oscillation stabilization wait time (2 − 2) /FCH 2 Remarks 0.5 μs (at main oscillation clock 4 MHz) Approx. 1.02 ms (at main oscillation clock 4 MHz) Approx. 2.05 ms (at main oscillation clock 4 MHz) Approx. 4.10 ms (at main oscillation clock 4 MHz) (212 − 2) /FCH (213 − 2) /FCH (2 − 2) /FCH 14 ■ PACKAGES AND CORRESPONDING PRODUCTS Part number MB95116B Package LCC-48P-M09 FPT-48P-M26 FPT-52P-M01 BGA-224P-M08 : Available : Unavailable * : Under development * MB95F118BS/F118BW MB95FV100D-101 5 MB95110B Series ■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS • Notes on Using Evaluation Products The evaluation product has not only the functions of the MB95110B corresponding products series but also those of other products to support software development for multiple series and models of the F2MC-8FX family. The I/O addresses for peripheral resources not used by the MB95110B series are therefore access-barred. Read/write access to these access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting in unexpected malfunctions of hardware or software. Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are used, the address may be read or written unexpectedly). Note that the values read from barred addresses are different between the evaluation product and the Flash memory product. Therefore, the value must not be used for program. The evaluation product do not support the functions of some bits in single-byte registers. Read/write access to these bits does not cause hardware malfunctions. The evaluation, Flash memory, and MASK ROM products are designed to behave completely the same way in terms of hardware and software. • Difference of Memory Spaces If the amount of memory on the evaluation product is different from that of the Flash memory or MASK ROM product, carefully check the difference in the amount of memory from the model to be actually used when developing software. For details of memory space, refer to “■ CPU CORE”. • Current Consumption The current consumption of Flash memory product is greater than for MASK ROM product. For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”. • Package For details of information on each package, refer to “■ PACKAGE DIMENSIONS”. • Operating voltage The operating voltage are different among the evaluation, Flash memory, and MASK ROM products. For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS” • Difference between RST and MOD pins The input type of RST and MOD pins is CMOS input on the Flash memory product. The RST and MOD pins are hysteresis inputs on the MASK ROM product. A pull - down resistor is provided for the MOD pin of the MASK ROM product. 6 MB95110B Series ■ PIN ASSIGNMENTS (TOP VIEW) P13/TRG0/ADTG P61/PPG11 P60/PPG10 P65/SCK P66/SOT P67/SIN P37/AN07 P36/AN06 P35/AN05 P34/AN04 P33/AN03 P32/AN02 P31/AN01 P30/AN00 AVss 1 2 3 4 5 6 7 8 9 10 11 12 13 AVcc 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P06/INT06 P05/INT05 P04/INT04 P03/INT03 P02/INT02 P01/INT01 P00/INT00 RST PG1/X0A* PG2/X1A* PG0 Vcc 14 P24/EC0 15 P23/TO01 16 P22/TO00 17 P21/PPG01 18 P20/PPG00 19 P51/SDA0 20 P50/SCL0 21 MOD 22 X0 23 X1 24 Vss 25 (LCC-48P-M09) * : The pins are general-purpose port in single clock product or sub clock oscillation pin in dual clock product. (Continued) P07/INT07 P14/PPG0 P12/UCK0 P63/TO11 P62/TO10 P11/UO0 P64/EC1 P10/UI0 P15 7 MB95110B Series (TOP VIEW) P13/TRG0/ADTG P61/PPG11 P60/PPG10 48 47 46 45 44 43 42 41 40 39 38 37 P65/SCK P66/SOT P67/SIN P37/AN07 P36/AN06 P35/AN05 P34/AN04 P33/AN03 P32/AN02 P31/AN01 P30/AN00 AVss 1 2 3 4 5 6 7 8 9 10 11 12 P07/INT07 P14/PPG0 P12/UCK0 P63/TO11 P62/TO10 P11/UO0 P64/EC1 P10/UI0 P15 36 35 34 33 32 31 30 29 28 27 26 25 P06/INT06 P05/INT05 P04/INT04 P03/INT03 P02/INT02 P01/INT01 P00/INT00 RST PG1/X0A* PG2/X1A* PG0 Vcc 13 14 15 16 17 18 19 20 21 22 23 24 P23/TO01 P22/TO00 P21/PPG01 P20/PPG00 P51/SDA0 P50/SCL0 AVcc P24/EC0 MOD X0 X1 Vss (FPT-48P-M26) * : The pins are general-purpose port in single clock product or sub clock oscillation pin in dual clock product. (Continued) 8 MB95110B Series (Continued) (TOP VIEW) P13/TRG0/ADTG P61/PPG11 P60/PPG10 52 51 50 49 48 47 46 45 44 43 42 41 40 P07/INT07 P14/PPG0 P12/UCK0 P63/TO11 P62/TO10 P11/UO0 P64/EC1 P10/UI0 P15 NC P65/SCK P66/SOT P67/SIN P37/AN07 P36/AN06 P35/AN05 NC P34/AN04 P33/AN03 P32/AN02 P31/AN01 P30/AN00 AVss 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 P06/INT06 P05/INT05 P04/INT04 P03/INT03 P02/INT02 P01/INT01 NC P00/INT00 RST PG1/X0A* PG2/X1A* PG0 Vcc 14 15 16 17 18 19 20 21 22 23 24 25 26 P23/TO01 P22/TO00 P21/PPG01 P20/PPG00 P51/SDA0 P50/SCL0 AVcc P24/EC0 NC MOD X0 X1 Vss (FPT-52P-M01) * : The pins are general-purpose port in single clock product or sub clock oscillation pin in dual clock product. 9 MB95110B Series ■ PIN DESCRIPTION Pin no. LQFP*1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 LQFP*2 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 Pin name I/O Circuit type*3 Function General-purpose I/O port. The pin is shared with LIN-UART clock I/O. General-purpose I/O port. The pin is shared with LIN-UART data output. General-purpose I/O port. The pin is shared with LIN-UART data input. P65/SCK K P66/SOT P67/SIN P37/AN07 P36/AN06 P35/AN05 P34/AN04 P33/AN03 P32/AN02 P31/AN01 P30/AN00 AVss AVcc P24/EC0 P23/TO01 P22/TO00 P21/PPG01 P20/PPG00 P51/SDA0 I P50/SCL0 MOD X0 X1 Vss Vcc PG0 B A ⎯ ⎯ H H ⎯ ⎯ J L General-purpose I/O port. The pins are shared with A/D converter analog input. A/D converter power supply pin (GND) A/D converter power supply pin General-purpose I/O port. The pin is shared with 8/16-bit compound timer ch.0 clock input. General-purpose I/O port. The pins are shared with 8/16-bit compound timer ch.0 output. General-purpose I/O port. The pins are shared with 8/16-bit PPG ch.0 output. General-purpose I/O port. The pin is shared with I2C ch.0 data I/O. General-purpose I/O port. The pin is shared with I2C ch.0 clock I/O. Operating mode designation pin Main clock input oscillation pin Main clock input/output oscillation pin Power supply pin (GND) Power supply pin General-purpose I/O port. (Continued) 10 MB95110B Series (Continued) Pin no. LQFP*1 27 28 29 30 31 32 33 34 35 36 37 38 39 40 LQFP*2 29 30 31 32 34 35 36 37 38 39 40 41 42 43 Pin name I/O Circuit type*3 Function This pin is general-purpose port in single clock product (PG2) . This pin is sub clock oscillation pin in dual clock product (32 kHz) . This pin is general-purpose port in single clock product (PG1) . This pin is sub clock oscillation pin in dual clock product (32 kHz) . Reset pin PG2/X1A H/A PG1/X0A RST P00/INT00 P01/INT01 P02/INT02 P03/INT03 P04/INT04 P05/INT05 P06/INT06 P07/INT07 P10/UI0 P11/UO0 P12/UCK0 P13/TRG0/ ADTG P14/PPG0 P15 P60/PPG10 P61/PPG11 P62/TO10 P63/TO11 P64/EC1 NC ⎯ K H G C B’ General-purpose I/O port. The pins are shared with external interrupt input. Large current port. General-purpose I/O port. The pin is shared with UART/SIO ch.0 data input. General-purpose I/O port. The pin is shared with UART/SIO ch.0 data output. General-purpose I/O port. The pin is shared with UART/SIO ch.0 clock I/O. General-purpose I/O port. The pin is shared with 16-bit PPG ch.0 trigger input (TRG0) and A/D converter trigger input (ADTG). General-purpose I/O port. The pin is shared with 16-bit PPG ch.0 output. General-purpose I/O port. General-purpose I/O port. The pins are shared with 8/16-bit PPG ch.1 output. General-purpose I/O port. The pins are shared with 8/16-bit compound timer ch.1 output. General-purpose I/O port. The pin is shared with 8/16-bit compound timer ch.1 clock input. Internal connect pin. Be sure this pin is left open. 41 44 42 43 44 45 46 47 48 ⎯ 45 47 48 49 50 51 52 7, 20, 33, 46 *1 : FPT-48P-M26 *2 : FPT-52P-M01 *3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE” 11 MB95110B Series ■ I/O CIRCUIT TYPE Type Circuit Remarks • Oscillation circuit • High-speed side Feedback resistance value : approx. 1 MΩ • Low-speed side Feedback resistance : approx. 24 MΩ (Evaluation product : approx. 10 MΩ) Dumping resistance : approx. 144 kΩ (Evaluation product : without dumping resistance) • Only for input • Hysteresis input only for MASK ROM product • With pull-down resistor only for MASK ROM product Hysteresis input only for MASK ROM product • CMOS output • Hysteresis input Digital output Digital output N-ch X1 (X1A) Clock input N-ch A X0 (X0A) Standby control B R Mode input B’ Reset input P-ch C Standby control External interrupt enable Hysteresis input R P-ch P-ch Pull-up control Digital output Digital output CMOS input • • • • CMOS output CMOS input Hysteresis input With pull-up control G N-ch Standby control Hysteresis input (Continued) 12 MB95110B Series (Continued) Type Circuit Remarks • CMOS output • Hysteresis input • With pull-up control R P-ch P-ch Pull-up control H N-ch Digital output Digital output Hysteresis input Standby control N-ch Digital output CMOS input • N-ch open drain output • CMOS input • Hysteresis input I Standby control Hysteresis input • • • • CMOS output Hysteresis input Analog input With pull-up control R P-ch P-ch Pull-up control Digital output Digital output Analog input J N-ch A/D control Standby control Hysteresis input • CMOS output • Hysteresis input Digital output Digital output N-ch P-ch K Standby control Hysteresis input P-ch Digital output L N-ch • CMOS output • CMOS input • Hysteresis input Digital output CMOS input Standby control Hysteresis input 13 MB95110B Series ■ HANDLING DEVICES • Preventing Latch-up Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used. Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC pin and VSS pin. When latch-up occurs, power supply current increases rapidly and might thermally damage elements. Also, take care to prevent the analog power supply voltage (AVCC) and analog input voltage from exceeding the digital power supply voltage (VCC) when the analog system power supply is turned on or off. • Stable Supply Voltage Supply voltage should be stabilized. A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range of the VCC power-supply voltage. For stabilization, in principle, keep the variation in VCC ripple (p-p value) in a commercial frequency range (50 Hz/60 Hz) not to exceed 10% of the standard VCC value and suppress the voltage variation so that the transient variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched. • Precautions for Use of External Clock Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from sub clock mode or stop mode. 14 MB95110B Series ■ PIN CONNECTION • Treatment of Unused Input Pin Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. If there is unused output pin, make it to open. • Treatment of Power Supply Pins on A/D Converter Connect to be AVCC = VCC and AVSS = VSS even if the A/D converter is not in use. Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 μF ceramic capacitor as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device. • Power Supply Pins In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic capacitor of approximately 0.1 μF as a bypass capacitor between VCC and VSS pins near this device. • Mode Pin (MOD) Connect the MOD pin directly to VCC or VSS pins. To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the MOD pin to VCC or VSS pins and to provide a low-impedance connection. • Analog Power Supply Always set the same potential to AVCC and VCC . When VCC > AVCC, the current may flow through the AN00 to AN07 pins. 15 MB95110B Series ■ PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL PROGRAMMER • Supported Parallel Programmers and Adapters The following table lists supported parallel programmers and adapters. Package Applicable adapter model FPT-48P-M26 FPT-52P-M01 LCC-48P-M09 TEF110-118F37AP TEF110-95F118PMC TEF100-118F41AP Parallel programmers AF9708 (Ver 02.35G or more) AF9709/B (Ver 02.35G or more) AF9723+AF9834 (Ver 02.08E or more) Note: For information on applicable adapter models and parallel programmers, contact the following: Flash Support Group, Inc. TEL: +81-53-428-8380 • Sector Configuration The individual sectors of Flash memory correspond to addresses used for CPU access and programming by the parallel programmer as follows: Flash memory SA1 (4 Kbytes) Lower bank Upper bank 1FFFH 2000H SA2 (4 Kbytes) 2FFFH 3000H SA3 (4 Kbytes) 3FFFH 4000H SA4 (16 Kbytes) 7FFFH 8000H SA5 (16 Kbytes) BFFFH C000H SA6 (4 Kbytes) CFFFH D000H SA7 (4 Kbytes) DFFFH E000H SA8 (4 Kbytes) EFFFH F000H SA9 (4 Kbytes) FFFFH 7FFFFH 7EFFFH 7F000H 7DFFFH 7E000H 7CFFFH 7D000H 7BFFFH 7C000H 77FFFH 78000H 73FFFH 74000H 72FFFH 73000H 71FFFH 72000H CPU address 1000H Writer address* 71000H *: Programmer addresses are equivalent to CPU addresses, used when the parallel programmer programs data into Flash memory. These programmer addresses are used for the parallel programmer to program or erase data in Flash memory. 16 MB95110B Series • Programming Method 1) Set the type code of the parallel programmer to “17226”. 2) Load program data to programmer addresses 71000H to 7FFFFH. 3) Programmed by parallel programmer. 17 MB95110B Series ■ BLOCK DIAGRAM F MC-8FX CPU RST X0,X1 PG2/X1A* PG1/X0A* PG0 Reset control Clock control Watch prescaler Watch counter P00/INT00 to P07/INT07 P10/UI0 P11/UO0 P12/UCK0 P13/TRG0/ADTG P14/PPG0 P15 P20/PPG00 P21/PPG01 P22/TO00 P23/TO01 P24/EC0 P30/AN00 to P37/AN07 AVCC AVSS P50/SCL0 P51/SDA0 I 2C Port Port 8/16-bit PPG ch.0 16-bit PPG UART/SIO Internal bus 8/16-bit compound timer ch.1 External interrupt 8/16-bit PPG ch.1 P60/PPG10 P61/PPG11 P62/TO10 P63/TO11 P64/EC1 P65/SCK LIN-UART P66/SOT P67/SIN ROM RAM Interrupt control Wild register 2 8/16-bit compound timer ch.0 8/10-bit A/D converter Other pins MOD, VCC, VSS * : The pins are general-purpose port in single clock product and sub clock oscillation pin in dual clock product. 18 MB95110B Series ■ CPU CORE 1. Memory space Memory space of the MB95110B series is 64 Kbytes and consists of I/O area, data area, and program area. The memory space includes special-purpose areas such as the general-purpose registers and vector table. Memory map of the MB95110B series shown in below. • Memory Map MB95116B 0000H I/O 0080H 0100H 0200H 0480H 0F80H 1000H Access prohibited RAM 1 Kbyte Register MB95F118BS MB95F118BW 0000H I/O 0080H 0100H 0200H 0880H 0F80H MB95FV100D-101 0000H I/O 0080H RAM 3.75 Kbytes 0100H 0200H Register RAM 2 Kbytes Register Access prohibited Extension I/O Access prohibited Extension I/O 0F80H Extension I/O 1000H 1000H 8000H MASK ROM 32 Kbytes FFFFH FFFFH Flash memory 60 Kbytes Flash memory 60 Kbytes FFFFH 19 MB95110B Series 2. Register The MB95110B series has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The dedicated registers are as follows: : A 16-bit register to indicate locations where instructions are stored. Program counter (PC) Accumulator (A) : A 16-bit register for temporary storage of arithmetic operations. In the case of an 8-bit data processing instruction, the lower one byte is used. Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator. In the case of an 8-bit data processing instruction, the lower one byte is used. : A 16-bit register for index modification Index register (IX) : A 16-bit pointer to point to a memory address. Extra pointer (EP) : A 16-bit register to indicate a stack area. Stack pointer (SP) Program status (PS) : A 16-bit register for storing a register bank pointer, a direct bank pointer, and a condition code register 16-bit PC A T IX EP SP PS Initial Value : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status FFFDH 0000H 0000H 0000H 0000H 0000H 0030H The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer (DP) and the lower 8 bits for use as a condition code register (CCR). (Refer to the diagram below.) • Structure of the program status bit15 bit14 bit13 bit12 bit11 bit10 PS R4 R3 R2 R1 R0 DP2 bit9 DP1 bit8 DP0 bit7 H bit6 I bit5 IL1 bit4 IL0 bit3 N bit2 Z bit1 V bit0 C RP DP CCR 20 MB95110B Series The RP indicates the address of the register bank currently being used. The relationship between the content of RP and the real address conforms to the conversion rule illustrated below: • Rule for Conversion of Actual Addresses in the General-purpose Register Area RP upper "0" "0" "0" "0" "0" "0" "0" A9 "1" A8 R4 A7 R3 A6 R2 A5 R1 A4 R0 A3 OP code lower b2 A2 b1 A1 b0 A0 Generated address A15 A14 A13 A12 A11 A10 The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct addresses to 0080H to 00FFH. Direct bank pointer (DP2 to DP0) XXXB (no effect to mapping) 000B (initial value) 001B 010B 011B 100B 101B 110B 111B 0080H to 00FFH Specified address area 0000H to 007FH Mapping area 0000H to 007FH (without mapping) 0080H to 00FFH (without mapping) 0100H to 017FH 0180H to 01FFH 0200H to 027FH 0280H to 02FFH 0300H to 037FH 0380H to 03FFH 0400H to 047FH The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that control CPU operations at interrupt. H flag : Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. This flag is for decimal adjustment instructions. I flag : Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”. The flag is set to “0” when reset. IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 0 0 1 1 N flag Z flag V flag C flag IL0 0 1 0 1 Interrupt level 0 1 2 3 Low = no interruption Priority High : Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the bit is set to “0”. : Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise. : Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0” otherwise. : Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. Set to the shift-out value in the case of a shift instruction. 21 MB95110B Series The following general-purpose registers are provided: General-purpose registers: 8-bit data storage registers The general-purpose registers are 8 bits and located in the register banks on the memory. One bank contains eight registers. Up to a total of 32 banks can be used on the MB95110B series. The bank currently in use is specified by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0) to general-purpose register 7 (R7). • Register Bank Configuration 8-bit 1F8H This address = 0100H + 8 × (RP) Address 100H R0 R1 R2 R3 R4 R5 107H R6 R7 Bank 0 R0 R0 R1 R2 R3 R4 R5 R6 R7 R1 R2 R3 R4 R5 R6 1FFH R7 Bank 31 32 banks 32 banks (RAM area) The number of banks is limited by the usable RAM capacitance. Memory area 22 MB95110B Series ■ I/O MAP Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H, 0013H 0014H 0015H 0016H 0017H 0018H to 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H to 0034H Register abbreviation PDR0 DDR0 PDR1 DDR1 ⎯ WATR PLLC SYCC STBC RSRR TBTC WPCR WDTC ⎯ PDR2 DDR2 PDR3 DDR3 ⎯ PDR5 DDR5 PDR6 DDR6 ⎯ PDRG DDRG ⎯ PUL1 PUL2 PUL3 ⎯ Register name Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register (Disabled) Oscillation stabilization wait time setting register PLL control register System clock control register Standby control register Reset source register Time-base timer control register Watch prescaler control register Watchdog timer control register (Disabled) Port 2 data register Port 2 direction register Port 3 data register Port 3 direction register (Disabled) Port 5 data register Port 5 direction register Port 6 data register Port 6 direction register (Disabled) Port G data register Port G direction register (Disabled) Port 1 pull-up register Port 2 pull-up register Port 3 pull-up register (Disabled) R/W R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R R/W R/W R/W ⎯ R/W R/W R/W R/W ⎯ R/W R/W R/W R/W ⎯ R/W R/W ⎯ R/W R/W R/W ⎯ Initial value 00000000B 00000000B 00000000B 00000000B ⎯ 11111111B 00000000B 1010X011B 00000000B XXXXXXXXB 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B ⎯ (Continued) 23 MB95110B Series Address 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH to 0041H 0042H 0043H 0044H to 0047H 0048H 0049H 004AH 004BH 004CH to 004FH 0050H 0051H 0052H 0053H 0054H 0055H 0056H 0057H 0058H 0059H 005AH 005BH to 005FH Register abbreviation PULG T01CR1 T00CR1 T11CR1 T10CR1 PC01 PC00 PC11 PC10 ⎯ PCNTH0 PCNTL0 ⎯ EIC00 EIC10 EIC20 EIC30 ⎯ SCR SMR SSR RDR/TDR ESCR ECCR SMC10 SMC20 SSR0 TDR0 RDR0 ⎯ Register name Port G pull-up register 8/16-bit compound timer 01 control status register 1 ch.0 8/16-bit compound timer 00 control status register 1 ch.0 8/16-bit compound timer 11 control status register 1 ch.1 8/16-bit compound timer 10 control status register 1 ch.1 8/16-bit PPG1 control register ch.0 8/16-bit PPG0 control register ch.0 8/16-bit PPG1 control register ch.1 8/16-bit PPG0 control register ch.1 (Disabled) 16-bit PPG status control register (Upper byte) ch.0 16-bit PPG status control register (Lower byte) ch.0 (Disabled) External interrupt circuit control register ch.0/ch.1 External interrupt circuit control register ch.2/ch.3 External interrupt circuit control register ch.4/ch.5 External interrupt circuit control register ch.6/ch.7 (Disabled) LIN-UART serial control register LIN-UART serial mode register LIN-UART serial status register LIN-UART reception/transmission data register LIN-UART extended status control register LIN-UART extended communication control register UART/SIO serial mode control register 1 ch.0 UART/SIO serial mode control register 2 ch.0 UART/SIO serial status register ch.0 UART/SIO serial output data register ch.0 UART/SIO serial input data register ch.0 (Disabled) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ⎯ R/W R/W ⎯ R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R ⎯ Initial value 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00001000B 00000000B 00000100B 000000XXB 00000000B 00100000B 00000001B 00000000B 00000000B ⎯ (Continued) 24 MB95110B Series Address 0060H 0061H 0062H 0063H 0064H 0065H 0066H to 006BH 006CH 006DH 006EH 006FH 0070H 0071H 0072H 0073H 0074H 0075H 0076H 0077H 0078H 0079H 007AH 007BH 007CH 007DH 007EH 007FH 0F80H 0F81H 0F82H 0F83H 0F84H 0F85H Register abbreviation IBCR00 IBCR10 IBSR0 IDDR0 IAAR0 ICCR0 ⎯ ADC1 ADC2 ADDH ADDL WCSR ⎯ FSR SWRE0 SWRE1 ⎯ WREN WROR ⎯ ILR0 ILR1 ILR2 ILR3 ILR4 ILR5 ⎯ WRARH0 WRARL0 WRDR0 WRARH1 WRARL1 WRDR1 2 2 2 Register name I2C bus control register 0 ch.0 I C bus control register 1 ch.0 I2C bus status register ch.0 I2C data register ch.0 I C address register ch.0 I C clock control register ch.0 (Disabled) 8/10-bit A/D converter control register 1 8/10-bit A/D converter control register 2 8/10-bit A/D converter data register (Upper byte) 8/10-bit A/D converter data register (Lower byte) Watch counter status register (Disabled) Flash memory status register Flash memory sector writing control register 0 Flash memory sector writing control register 1 (Disabled) Wild register address compare enable register Wild register data test setting register (Mirror of register bank pointer (RP) and direct bank pointer (DP) ) Interrupt level setting register 0 Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt level setting register 4 Interrupt level setting register 5 (Disabled) Wild register address setting register (Upper byte) ch.0 Wild register address setting register (Lower byte) ch.0 Wild register data setting register ch.0 Wild register address setting register (Upper byte) ch.1 Wild register address setting register (Lower byte) ch.1 Wild register data setting register ch.1 R/W R/W R/W R R/W R/W R/W ⎯ R/W R/W R/W R/W R/W ⎯ R/W R/W R/W ⎯ R/W R/W ⎯ R/W R/W R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W Initial value 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ 000X0000B 00000000B 00000000B ⎯ 00000000B 00000000B ⎯ 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued) 25 MB95110B Series Address 0F86H 0F87H 0F88H 0F89H to 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H 0F98H 0F99H 0F9AH 0F9BH 0F9CH 0F9DH 0F9EH 0F9FH 0FA0H 0FA1H 0FA2H 0FA3H 0FA4H 0FA5H 0FA6H to 0FA9H 0FAAH 0FABH 0FACH 0FADH 0FAEH 0FAFH Register abbreviation WRARH2 WRARL2 WRDR2 ⎯ T01CR0 T00CR0 T01DR T00DR TMCR0 T11CR0 T10CR0 T11DR T10DR TMCR1 PPS01 PPS00 PDS01 PDS00 PPS11 PPS10 PDS11 PDS10 PPGS REVC ⎯ PDCRH0 PDCRL0 PCSRH0 PCSRL0 PDUTH0 PDUTL0 Register name Wild register address setting register (Upper byte) ch.2 Wild register address setting register (Lower byte) ch.2 Wild register data setting register ch.2 (Disabled) 8/16-bit compound timer 01 control status register 0 ch.0 8/16-bit compound timer 00 control status register 0 ch.0 8/16-bit compound timer 01 data register ch.0 8/16-bit compound timer 00 data register ch.0 8/16-bit compound timer 00/01 timer mode control register ch.0 8/16-bit compound timer 11 control status register 0 ch.1 8/16-bit compound timer 10 control status register 0 ch.1 8/16-bit compound timer 11 data register ch.1 8/16-bit compound timer 10 data register ch.1 8/16-bit compound timer 10/11 timer mode control register ch.1 8/16-bit PPG1 cycle setting buffer register ch.0 8/16-bit PPG0 cycle setting buffer register ch.0 8/16-bit PPG1 duty setting buffer register ch.0 8/16-bit PPG0 duty setting buffer register ch.0 8/16-bit PPG1 cycle setting buffer register ch.1 8/16-bit PPG0 cycle setting buffer register ch.1 8/16-bit PPG1 duty setting buffer register ch.1 8/16-bit PPG0 duty setting buffer register ch.1 8/16-bit PPG starting register 8/16-bit PPG output inversion register (Disabled) 16-bit PPG down counter register (Upper byte) ch.0 16-bit PPG down counter register (Lower byte) ch.0 16-bit PPG cycle setting buffer register (Upper byte) ch.0 16-bit PPG cycle setting buffer register (Lower byte) ch.0 16-bit PPG duty setting buffer register (Upper byte) ch.0 16-bit PPG duty setting buffer register (Lower byte) ch.0 R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ⎯ R R R/W R/W R/W R/W Initial value 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B ⎯ 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B (Continued) 26 MB95110B Series (Continued) Address 0FB0H to 0FBBH 0FBCH 0FBDH 0FBEH 0FBFH 0FC0H to 0FC2H 0FC3H 0FC4H to 0FE2H 0FE3H 0FE4H to 0FEDH 0FEEH 0FEFH 0FF0H to 0FFFH Register abbreviation ⎯ BGR1 BGR0 PSSR0 BRSR0 ⎯ AIDRL ⎯ WCDR ⎯ ILSR WICR ⎯ Register name (Disabled) LIN-UART baud rate generator register 1 LIN-UART baud rate generator register 0 UART/SIO dedicated baud rate generator prescaler selection register ch.0 UART/SIO dedicated baud rate generator baud rate setting register ch.0 (Disabled) A/D input disable register (Lower byte) (Disabled) Watch counter data register (Disabled) Input level select register Interrupt pin control register (Disabled) R/W ⎯ R/W R/W R/W R/W ⎯ R/W ⎯ R/W ⎯ R/W R/W ⎯ Initial value ⎯ 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B ⎯ 00111111B ⎯ 00000000B 01000000B ⎯ • R/W access symbols R/W : Readable/Writable R : Read only W : Write only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value. 27 MB95110B Series ■ INTERRUPT SOURCE TABLE Interrupt source External interrupt ch.0 External interrupt ch.4 External interrupt ch.1 External interrupt ch.5 External interrupt ch.2 External interrupt ch.6 External interrupt ch.3 External interrupt ch.7 UART/SIO ch.0 8/16-bit compound timer ch.0 (Lower) 8/16-bit compound timer ch.0 (Upper) LIN-UART (reception) LIN-UART (transmission) 8/16-bit PPG ch.1 (Lower) 8/16-bit PPG ch.1 (Upper) (Unused) 8/16-bit PPG ch.0 (Upper) 8/16-bit PPG ch.0 (Lower) 8/16-bit compound timer ch.1 (Upper) 16-bit PPG ch.0 I2C ch.0 (Unused) 8/10-bit A/D converter Time-base timer Watch prescaler/watch counter (Unused) 8/16-bit compound timer ch.1 (Lower) Flash memory Interrupt request number IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 IRQ20 IRQ21 IRQ22 IRQ23 Vector table address Upper FFFAH FFF8H FFF6H FFF4H FFF2H FFF0H FFEEH FFECH FFEAH FFE8H FFE6H FFE4H FFE2H FFE0H FFDEH FFDCH FFDAH FFD8H FFD6H FFD4H FFD2H FFD0H FFCEH FFCCH Lower FFFBH FFF9H FFF7H FFF5H FFF3H FFF1H FFEFH FFEDH FFEBH FFE9H FFE7H FFE5H FFE3H FFE1H FFDFH FFDDH FFDBH FFD9H FFD7H FFD5H FFD3H FFD1H FFCFH FFCDH Same level Bit name of priority order interrupt level (at simultaneous setting register occurrence) L00 [1 : 0] L01 [1 : 0] L02 [1 : 0] L03 [1 : 0] L04 [1 : 0] L05 [1 : 0] L06 [1 : 0] L07 [1 : 0] L08 [1 : 0] L09 [1 : 0] L10 [1 : 0] L11 [1 : 0] L12 [1 : 0] L13 [1 : 0] L14 [1 : 0] L15 [1 : 0] L16 [1 : 0] L17 [1 : 0] L18 [1 : 0] L19 [1 : 0] L20 [1 : 0] L21 [1 : 0] L22 [1 : 0] L23 [1 : 0] Low High 28 MB95110B Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Power supply voltage*1 Input voltage*1 Output voltage*1 Maximum clamp current Total maximum clamp current “L” level maximum output current Symbol Vcc, AVcc VI1 VI2 VO ICLAMP Σ|ICLAMP| IOL1 IOL2 IOLAV1 “L” level average current IOLAV2 “L” level total maximum output current “L” level total average output current “H” level maximum output current ⎯ 12 Rating Min Vss − 0.3 Vss − 0.3 Vss − 0.3 Vss − 0.3 − 2.0 ⎯ ⎯ Max Vss + 4.0 Vss + 4.0 Vss + 6.0 Vss + 4.0 + 2.0 20 15 15 4 mA Unit V V V mA mA mA *2 Other than P50, P51*3 P50, P51 *3 Applicable to pins*4 Applicable to pins*4 Other than P00 to P07 P00 to P07 Other than P00 to P07 Average output current = operating current × operating ratio (1 pin) P00 to P07 Average output current = operating current × operating ratio (1 pin) Remarks ΣIOL ΣIOLAV IOH1 IOH2 IOHAV1 ⎯ ⎯ ⎯ 100 50 − 15 − 15 −4 mA mA Total average output current = operating current × operating ratio (total of pins) Other than P00 to P07 P00 to P07 Other than P00 to P07 Average output current = operating current × operating ratio (1 pin) P00 to P07 Average output current = operating current × operating ratio (1 pin) mA “H” level average current IOHAV2 “H” level total maximum output current “H” level total average output current Power consumption Operating temperature Storage temperature ⎯ −8 mA ΣIOH ΣIOHAV Pd TA Tstg ⎯ ⎯ ⎯ − 40 − 55 − 100 − 50 320 + 85 + 150 mA mA mW °C °C (Continued) 29 Total average output current = operating current × operating ratio (total of pins) MB95110B Series (Continued) *1 : The parameter is based on AVCC = VSS = 0.0 V. *2 : Apply equal potential to AVcc and Vcc. *3 : VI1 and VO should not exceed VCC + 0.3 V. VI1 must not exceed the rating voltage. However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI1 rating. *4 : • • • • • • • • • • Applicable to pins : P00 to P07, P10 to P15, P20 to P24, P30 to P37, PG0 Use within recommended operating conditions. Use at DC voltage (current). +B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting resistance placed between the + B signal and the microcontroller. The value of the limiting resistance should be set so that when the + B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. Note that if the + B input is applied during power-on, the power supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. Care must be taken not to leave the + B input pin open. Sample recommended circuits : • Input/Output Equivalent Circuits Protective diode Limiting resistance Vcc P-ch N-ch R + B input (0 V to 16 V) WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 30 MB95110B Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Parameter Symbol Pin name Conditions Value Min 1.8* Typ ⎯ Max 3.3 Unit Remarks At normal operating, Flash memory product, TA = − 10 °C to + 85 °C At normal operating, MASK ROM product, TA = − 10 °C to + 85 °C At normal operating, Flash memory product, TA = − 40 °C to + 85 °C V 1.8* ⎯ 3.6 2.0* Power supply voltage VCC, AVCC ⎯ ⎯ ⎯ 3.3 2.0* ⎯ ⎯ ⎯ 3.6 At normal operating, MASK ROM product, TA = − 40 °C to + 85 °C MB95FV100D-101, TA = + 5 °C to + 35 °C Retain status of stop mode operation, Flash memory product Retain status of stop mode operation, MASK ROM product 2.6 3.6 1.5 3.3 1.5 Operating temperature ⎯ ⎯ − 40 ⎯ ⎯ 3.6 + 85 °C TA * : The values vary with the operating frequency. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. 31 MB95110B Series 3. DC Characteristics (Vcc = AVcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Symbol Pin name Conditions Value Min 0.7 Vcc Typ ⎯ Max Vcc + 0.3 Unit Remarks At selecting of CMOS input level (hysteresis input) At selecting of CMOS input level (hysteresis input) VIH1 P10, P67 *1 V VIH2 P50, P51 P00 to P07, P10 to P15, P20 to P24, P30 to P37, P60 to P67, PG0, PG1*1, PG2*1 P50, P51 *1 0.7 Vcc ⎯ Vss + 5.5 V “H” level input voltage VIHS1 *1 0.8 Vcc ⎯ Vcc + 0.3 V Hysteresis input VIHS2 *1 ⎯ 0.8 Vcc 0.7 Vcc ⎯ ⎯ Vss + 5.5 Vcc + 0.3 V V Hysteresis input CMOS input (Flash memory product) Hysteresis input (MASK ROM product) At selecting of CMOS input level (hysteresis input) VIHM RST, MOD ⎯ P10, P50, P51, P67 P00 to P07, P10 to P15, P20 to P24, P30 to P37, P50, P51, P60 to P67, PG0, PG1*1, PG2*1 0.8 Vcc ⎯ Vcc + 0.3 V VIL *1 Vss − 0.3 ⎯ 0.3 Vcc V VILS “L” level input voltage *1 Vss − 0.3 ⎯ 0.2 Vcc V Hysteresis input ⎯ VILM RST, MOD ⎯ Open drain output application voltage Vss − 0.3 ⎯ 0.3 Vcc V CMOS input (Flash memory product) Hysteresis input (MASK ROM product) Vss − 0.3 ⎯ 0.2 Vcc V VD P50, P51 ⎯ Vss − 0.3 ⎯ Vss + 5.5 V (Continued) 32 MB95110B Series (Vcc = AVcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Symbol VOH1 “H” level output voltage VOH2 Pin name Output pin other than P00 to P07 P00 to P07 Output pin other than P00 to P07 P00 to P07 Conditions IOH = − 4.0 mA IOH = − 8.0 mA IOL = 4.0 mA IOL = 12 mA Value Min 2.4 Typ ⎯ Max ⎯ Unit Remarks MB95FV100D-101 a conditional : IOH = − 2.0 mA MB95FV100D-101 a conditional : IOH = − 5.0 mA MB95FV100D-101 a conditional : IOL = 3.0 mA MB95FV100D-101 a conditional : IOL = 8.0 mA When no pull-up prohibition setting V 2.4 ⎯ ⎯ V VOL1 “L” level output voltage VOL2 Input leakage current (Hi-Z output leakage current) Open drain output leakage current ⎯ ⎯ 0.4 V ⎯ ⎯ 0.4 V ILI Port other than P50, P51 0.0 V < VI < Vcc −5 ⎯ +5 μA ILIOD P50, P51 0.0 V < VI < Vss + 5.5 V ⎯ ⎯ 5 μA Pull-up resistor RPULL P10 to P15, P20 to P24, P30 to P37, VI = 0.0 V PG0, PG1*2, PG2*2 VI = Vcc 25 50 100 kΩ When pull-up permission setting Pull-down resistor RMOD MOD 50 100 200 kΩ MASK ROM product ⎯ Power supply current*3 VCC (external clock operation) FCH = 20 MHz FMP = 10 MHz Main clock mode (divided by 2) 11 14 Flash memory product mA (at other than Flash memory writing and erasing) Flash memory product mA (at Flash memory writing and erasing) mA MASK ROM product (Continued) ICC ⎯ 7.3 10 ⎯ 30 35 33 MB95110B Series (Vcc = AVcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Symbol Pin name Conditions Value Min Typ Max Unit Remarks Flash memory product (at other than Flash memory writing and erasing) Flash memory product (at Flash memory writing and erasing) MASK ROM product ⎯ FCH = 32 MHz FMP = 16 MHz Main clock mode (divided by 2) 17.6 22.4 mA ICC ⎯ 38.1 44.9 mA ⎯ FCH = 20 MHz FMP = 10 MHz Main sleep mode (divided by 2) FCH = 32 MHz FMP = 16 MHz Main sleep mode (divided by 2) FCL = 32 kHz VCC FMPL = 16 kHz (external clock Sub clock mode operation) (divided by 2) , TA = + 25 °C FCL = 32 kHz FMPL = 16 kHz Sub sleep mode (divided by 2) , TA = + 25 °C FCL = 32 kHz Watch mode Main stop mode TA = + 25 °C FCH = 4 MHz FMP = 10 MHz Main PLL mode (multiplied by 2.5) ICCMPLL 11.7 16.0 mA ⎯ 4.5 6 mA ICCS ⎯ 7.2 9.6 mA Power supply current*3 ICCL ⎯ 25 35 μA ICCLS ⎯ 7 15 μA ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2 1 10 6.7 16.0 10.8 10 5 14 10 22.4 16.0 μA μA mA mA mA mA ICCT Flash memory product MASK ROM product Flash memory product MASK ROM product Flash memory product MASK ROM product (Continued) FCH = 6.4 MHz FMP = 16 MHz Main PLL mode (multiplied by 2.5) 34 MB95110B Series (Continued) (Vcc = AVcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Symbol Pin name Conditions FCL = 32 kHz FMPL = 128 kHz Sub PLL mode (multiplied by 4) , TA = + 25 °C Value Min Typ Max Unit Remarks ICCSPLL ⎯ 190 250 μA ICTS Power supply current*3 ICCH IA VCC (external clock FCH = 10 MHz Time-base timer operation) mode TA = + 25 °C Sub stop mode TA = + 25 °C ⎯ 0.4 0.5 mA ⎯ ⎯ 1 1.3 5 2.2 μA mA FCH = 10 MHz At A/D converting AVcc FCH = 10 MHz At A/D converting stop TA = + 25 °C f = 1 MHz IAH ⎯ 1 5 μA Input capacitance CIN Other than AVcc, AVss, Vcc, and Vss ⎯ 5 15 pF *1 : P10, P50, P51, and P67 can switch the input level to either the “CMOS input level” or “hysteresis input level”. The switching of the input level can be set by the input level selection register (ILSR). *2 : Single clock products only *3 : The power-supply current is determined by the external clock. • Refer to “4. AC characteristics (1) Clock Timing” for FCH and FCL. • Refer to “4. AC characteristics (2) Source Clock/Machine Clock” for fMP and fMPL. 35 MB95110B Series 4. AC Characteristics (1) Clock Timing (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Symbol Pin Conditions Value Min 1.00 1.00 FCH X0, X1 3.00 3.00 3.00 Clock frequency 3.00 ⎯ FCL X0A, X1A ⎯ 100 50 tLCYL tWH1 tWL1 tWH2 tWL2 tCR tCF X0A, X1A X0 X0A X0, X0A ⎯ 10 ⎯ ⎯ ⎯ ⎯ 30.5 ⎯ 15.2 ⎯ 1000 1000 ⎯ ⎯ ⎯ 5 ns ns μs ns μs ns Typ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 32.768 Max 16.25 32.50 10.00 8.13 6.50 4.06 ⎯ Unit MHz Remarks When using main oscillation circuit MHz When using external clock MHz Main PLL multiplied by 1 MHz Main PLL multiplied by 2 MHz Main PLL multiplied by 2.5 MHz Main PLL multiplied by 4 kHz When using sub oscillation circuit When using sub PLL Flash memory product : Vcc = 2.3 V to 3.3 V MASK ROM product : Vcc = 2.3 V to 3.6 V When using main oscillation circuit When using external clock When using sub oscillation circuit, When using external clock When using external clock Duty ratio is about 30% to 70%. When using external clock ⎯ 32.768 ⎯ kHz tHCYL Clock cycle time X0, X1 Input clock pulse width Input clock rise time and fall time 36 MB95110B Series • Input Wave form when using External Clock (Main clock) tHCYL tWH1 tCR tCF 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC tWL1 X0 • Figure of Main Clock Input Port External Connection When using a crystal or ceramic oscillator Microcontroller X0 X1 FCH C1 C2 When using external clock Microcontroller X0 X1 Open FCH • Input Wave form when using External Clock (Sub clock) tLCYL tWH2 tCR tCF 0.8 VCC 0.8 VCC 0.1 VCC 0.1 VCC 0.1 VCC tWL2 X0A • Figure of Sub clock Input Port External Connection When using a crystal or ceramic oscillator Microcontroller X0A X1A FCL C1 C2 When using external clock Microcontroller X0A X1A Open FCL 37 MB95110B Series (2) Source Clock/Machine Clock (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Sym- Pin bol name Value Min 61.5 tSCLK ⎯ 7.6 FSP Source clock frequency FSPL ⎯ ⎯ 0.5 16.38 4 100 tMCLK ⎯ 7.6 FMP FMPL 0.031 1.024 ⎯ ⎯ ⎯ 976.5 μs ⎯ ⎯ ⎯ ⎯ 61.0 16.25 μs Typ ⎯ Max 2000 Unit Remarks When using Main clock Min : FCH = 8.125 MHz, PLL multiplied by 2 Max : FCH = 1 MHz, divided by 2 When using Sub clock Min : FCL = 32 kHz, PLL multiplied by 4 Max : FCL = 32 kHz, divided by 2 Source clock*1 (Clock before setting division) ns MHz When using Main clock 131.072 kHz When using Sub clock When using Main clock Min : FSP = 16.25 MHz, no division Max : FSP = 0.5 MHz, divided by 16 When using Sub clock Min : FSPL = 131 kHz, no division Max : FSPL = 16 kHz, divided by 16 Machine clock*2 (Minimum instruction execution time) 32000 ns Machine clock frequency ⎯ 16.250 MHz When using Main clock 131.072 kHz When using Sub clock *1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes the machine clock. Further, the source clock can be selected as follow. • Main clock divided by 2 • PLL multiplication of main clock (select from 1, 2, 2.5 4 multiplication) • Sub clock divided by 2 • PLL multiplication of sub clock (select from 2, 3, 4 multiplication) *2 : Operation clock of the microcontroller. Machine clock can be selected as follow. • Source clock (no division) • Source clock divided by 4 • Source clock divided by 8 • Source clock divided by 16 38 MB95110B Series • Outline of clock generation block FCH (main oscillation) Divided by 2 Main PLL ×1 ×2 × 2.5 ×4 SCLK ( source clock ) FCL (sub oscillation) Divided by 2 Clock mode select bit ( SYCC : SCS1, SCS0 ) Division circuit ×1 × 1/4 × 1/8 × 1/16 MCLK ( machine clock ) Sub PLL ×2 ×3 ×4 39 MB95110B Series • Operating voltage - Operating frequency (When TA = − 10 °C to + 85 °C) • MB95116B Sub PLL operation guarantee range Sub clock mode and watch mode operation guarantee range 3.6 Main clock mode and main PLL mode operation guarantee range Operating voltage (V) 3.6 Operating voltage (V) 2.7 2.3 1.8 16.384 kHz 32 kHz 131.072 kHz 1.8 0.5 MHz 3 MHz 5 MHz 16.25 MHz PLL operation guarantee range Source clock frequency (FSP) • MB95F118BS, MB95F118BW Sub PLL operation guarantee range Sub clock mode and watch mode operation guarantee range 3.3 PLL operation guarantee range Main clock operation guarantee range Source clock frequency (FSP) Main clock mode and main PLL mode operation guarantee range 3.3 Operating voltage (V) Operating voltage (V) 2.7 2.3 1.8 16.384 kHz 32 kHz 131.072 kHz 1.8 0.5 MHz 3 MHz 5 MHz 10 MHz 16.25 MHz PLL operation guarantee range Source clock frequency (FSP) PLL operation guarantee range Main clock operation guarantee range Source clock frequency (FSP) 40 MB95110B Series • Operating voltage - Operating frequency (When TA = − 40 °C to + 85 °C) • MB95116B Sub PLL operation guarantee range Sub clock mode and watch mode operation guarantee range 3.6 3.6 Main clock mode and main PLL mode operation guarantee range Operating voltage (V) Operating voltage (V) 2.7 2.3 2.0 16.384 kHz 32 kHz 131.072 kHz 2.0 0.5 MHz 3 MHz 5 MHz 16.25 MHz PLL operation guarantee range Source clock frequency (FSP) • MB95F118BS, MB95F118BW Sub PLL operation guarantee range Sub clock mode and watch mode operation guarantee range 3.3 PLL operation guarantee range Main clock operation guarantee range Source clock frequency (FSP) Main clock mode and main PLL mode operation guarantee range Operating voltage (V) 3.3 Operating voltage (V) 2.7 2.3 2.0 16.384 kHz 32 kHz 131.072 kHz 2.0 0.5 MHz 3 MHz 7.5 MHz 16.25 MHz PLL operation guarantee range Source clock frequency (FSP) PLL operation guarantee range Main clock operation guarantee range Source clock frequency (FSP) 41 MB95110B Series • Operating voltage - Operating frequency (When TA = + 5 °C to + 35 °C) • MB95FV100D-101 Sub PLL , Sub clock mode and watch mode operation guarantee range Operating voltage (V) Operating voltage (V) 3.6 3.6 3.3 2.6 Main clock mode and main PLL mode operation guarantee range 2.6 16.384 kHz 32 kHz 131.072 kHz 0.5 MHz 3 MHz 10 MHz 16.25 MHz PLL operation guarantee range Source clock frequency (FSP) PLL operation guarantee range Main clock operation guarantee range Source clock frequency (FSP) 42 MB95110B Series • Main PLL operation frequency [MHz] 16.25 16 15 ×4 12 × 2.5 ×2 Source clock frequency (FSP) 10 ×1 7.5 6 5 3 0 3 4 4.062 5 6.4 6.5 8 8.125 10 [MHz] Main clock frequency (FMP) 43 MB95110B Series (3) External Reset (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter RST “L” level pulse width Symbol Value Min 2 tMCLK*1 tRSTL Oscillation time of oscillator*2 + 2 tMCLK*1 Max ⎯ ⎯ Unit ns ns Remarks At normal operating At stop mode, sub clock mode, sub sleep mode, and watch mode *1 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. *2 : Oscillation time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of μs and several ms. In the external clock, the oscillation time is 0 ms. • At normal operating tRSTL RST 0.2 VCC 0.2 VCC • At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on RST 90% of amplitude tRSTL 0.2 VCC 0.2 VCC X0 Internal operating clock Oscillation time of oscillator 2 tMCLK Oscillation stabilization wait time Execute instruction Internal reset 44 MB95110B Series (4) Power-on Reset (AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Power supply rising time Power supply cutoff time Symbol tR tOFF Conditions ⎯ ⎯ Value Min ⎯ 1 Max 36 ⎯ Unit ms ms Waiting time until power-on Remarks Note : The power supply must be turned on within the selected oscillation stabilization time. tR 1.5 V tOFF VCC 0.2 V 0.2 V 0.2 V Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power supply voltages during operation, set the slope of rising within 20 mV/ms as shown below. VCC 1.5 V Limiting the slope of rising within 20 mV/ms is recommended. Hold condition in stop mode VSS 45 MB95110B Series (5) Peripheral Input Timing (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Peripheral input “H” pulse width Peripheral input “L” pulse width Symbol tILIH tIHIL Pin name Value Min 2 tMCLK* 2 tMCLK* Max ⎯ ⎯ Unit ns ns INT00 to INT07, EC0, EC1, TRG0/ADTG * : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. tILIH tIHIL INT00 to INT07, EC0, EC1, TRG0/ADTG 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 46 MB95110B Series (6) UART/SIO, Serial I/O Timing (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Serial clock cycle time UCK ↓ → UO time Valid UI → UCK ↑ UCK ↑ → valid UI hold time Serial clock “H” pulse width Serial clock “L” pulse width UCK ↓ → UO time Valid UI → UCK ↑ UCK ↑ → valid UI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name UCK0 UCK0, UO0 UCK0, UI0 UCK0, UI0 UCK0 UCK0 UCK0, UO0 UCK0, UI0 UCK0, UI0 External clock operation output pin : CL = 80 pF + 1 TTL. Internal clock operation output pin : CL = 80 pF + 1 TTL. Conditions Value Min 4 tMCLK* − 190 2 tMCLK* 2 tMCLK* 4 tMCLK* 4 tMCLK* ⎯ 2 tMCLK* 2 tMCLK* Max ⎯ + 190 ⎯ ⎯ ⎯ ⎯ 190 ⎯ ⎯ Unit ns ns ns ns ns ns ns ns ns * : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. • Internal shift clock mode tSCYC UCK0 2.4 V 0.8 V tSLOV 0.8 V UO0 2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC UI0 0.8 VCC 0.2 VCC • External shift clock mode tSLSH tSHSL 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tSLOV UCK0 UO0 2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC UI0 0.8 VCC 0.2 VCC 47 MB95110B Series (7) LIN-UART Timing Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2 (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0) (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C) Parameter Serial clock cycle time SCK ↑→ SOT delay time Valid SIN→SCK↑ SCK↑→ valid SIN hold time Serial clock “L” pulse width Serial clock “H” pulse width SCK ↓→SOT delay time Valid SIN→SCK↑ SCK↑→ valid SIN hold time SCK fall time SCK rise time SymPin name bol tSCYC tSLOVI tIVSHI tSHIXI tSLSH tSHSL tIVSHE tSHIXE tF tR SCK Internal clock SCK, SOT operation output pin : SCK, SIN CL = 80 pF + 1 TTL SCK, SIN SCK SCK External clock SCK, SIN operation output pin : CL = 80 pF + 1 TTL SCK, SIN SCK SCK t Conditions Value Min 5 tMCLK*3 − 95 MCLK 3 Max ⎯ + 95 ⎯ ⎯ ⎯ ⎯ 2t MCLK 3 Unit ns ns ns ns ns ns ns ns ns ns ns * + 190 0 3 tMCLK*3 − tR t MCLK 3 * + 95 ⎯ tSLOVE SCK, SOT * + 95 190 tMCLK*3 + 95 ⎯ ⎯ ⎯ ⎯ 10 10 *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. 48 MB95110B Series • Internal shift clock mode tSCYC 2.4 V 0.8 V tSLOVI 2.4 V 0.8 V tIVSHI tSHIXI 0.8 V SCK SOT SIN 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSLSH tSHSL 0.8 VCC 0.2 VCC tF tSLOVE 2.4 V 0.8 V tIVSHE tSHIXE 0.2 VCC tR 0.8 VCC SCK 0.8 VCC SOT SIN 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 49 MB95110B Series Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2 (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0) (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Serial clock cycle time SCK↑→ SOT delay time Valid SIN→SCK↓ SCK↓→ valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK↑ →SOT delay time Valid SIN→SCK↓ SCK↓→ valid SIN hold time SCK fall time SCK rise time Symbol tSCYC tSHOVI tIVSLI tSLIXI tSHSL tSLSH tSHOVE tIVSLE tSLIXE tF tR Pin name SCK SCK, SOT Internal clock operation output pin : SCK, SIN CL = 80 pF + 1 TTL SCK, SIN SCK SCK SCK, SOT External clock SCK, SIN operation output pin : CL = 80 pF + 1 TTL SCK, SIN SCK SCK t Conditions Value Min 5 tMCLK*3 − 95 MCLK 3 Max ⎯ + 95 ⎯ ⎯ ⎯ ⎯ 2t MCLK 3 Unit ns ns ns ns ns ns ns ns ns ns ns * + 190 0 3 tMCLK*3 − tR tMCLK*3 + 95 ⎯ 190 tMCLK*3 + 95 ⎯ ⎯ * + 95 ⎯ ⎯ 10 10 *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. 50 MB95110B Series • Internal shift clock mode tSCYC SCK 2.4 V 0.8 V tSHOVI 2.4 V 0.8 V tIVSLI tSLIXI 2.4 V SOT SIN 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSHSL tSLSH 0.8 VCC 0.2 VCC tSHOVE 2.4 V 0.8 V tIVSLE tSLIXE tF 0.2 VCC SCK 0.2 VCC tR 0.8 VCC SOT SIN 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 51 MB95110B Series Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2 (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1) (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Serial clock cycle time SCK↑→ SOT delay time Valid SIN→SCK↓ SCK↓→ valid SIN hold time SOT→SCK↓ delay time Symbol tSCYC tSHOVI tIVSLI tSLIXI tSOVLI Pin name SCK SCK, SOT SCK, SIN SCK, SIN SCK, SOT Internal clock operation output pin : CL = 80 pF + 1 TTL t Conditions Value Min 5 tMCLK*3 − 95 MCLK 3 Max ⎯ + 95 ⎯ ⎯ 4 tMCLK*3 Unit ns ns ns ns ns * + 190 0 ⎯ *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. tSCYC SCK 0.8 V tSOVLI 2.4 V 0.8 V tIVSLI 2.4 V tSHOVI 2.4 V 0.8 V tSLIXI 0.8 VCC 0.2 VCC 0.8 V SOT SIN 0.8 VCC 0.2 VCC 52 MB95110B Series Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2 (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1) (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Serial clock cycle time SCK↓→SOT hold time Valid SIN→SCK↑ SCK↑ → valid SIN hold time SOT→SCK↑ delay time Symbol tSCYC tSLOVI tIVSHI tSHIXI tSOVHI Pin name SCK SCK, SOT Internal clock SCK, SIN operating output pin : CL = 80 pF + 1 TTL SCK, SIN t Conditions Value Min 5 tMCLK*3 − 95 MCLK 3 Max ⎯ + 95 ⎯ ⎯ 4 tMCLK*3 Unit ns ns ns ns ns * + 190 0 ⎯ SCK, SOT *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. tSCYC SCK tSOVHI 2.4 V 0.8 V tSLOVI 2.4 V 0.8 V tIVSHI tSHIXI 0.8 VCC 0.2 VCC 2.4 V 0.8 V 2.4 V SOT SIN 0.8 VCC 0.2 VCC 53 MB95110B Series (8) I2C Timing (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Value Parameter Symbol Pin name SCL0 SCL0 SDA0 SCL0 SCL0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 R = 1.7 kΩ, C = 50 pF*1 Conditions Standardmode Min SCL clock frequency (Repeat) Start condition hold time SDA ↓ → SCL ↓ SCL clock “L” width SCL clock “H” width (Repeat) Start condition setup time SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓ ↑ Data setup time SDA ↓ ↑ → SCL ↑ Stop condition setup time SCL ↑ → SDA ↑ Bus free time between stop condition and start condition fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF 0 4.0 4.7 4.0 4.7 0 0.25 4 4.7 Max 100 ⎯ ⎯ ⎯ ⎯ 3.45*2 ⎯ ⎯ ⎯ Fast-mode Min 0 0.6 1.3 0.6 0.6 0 0.1 0.6 1.3 Max 400 ⎯ ⎯ ⎯ ⎯ 0.9*3 ⎯ ⎯ ⎯ kHz μs μs μs μs μs μs μs μs Unit *1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : The maximum tHD;DAT have only to be met if the device dose not stretch the “L” width (tLOW) of the SCL signal. *3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. tWAKEUP SDA0 tLOW SCL0 tHD;STA tSU;DAT tSU;STA tSU;STO tHD;DAT tHIGH tHD;STA tBUF 54 MB95110B Series (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C) Parameter SCL clock “L” width SCL clock “H” width Sym- Pin Condition bol name tLOW tHIGH SCL0 SCL0 Value*2 Min (2 + nm / 2) tMCLK − 20 (nm / 2) tMCLK − 20 Max ⎯ (nm / 2 ) tMCLK + 20 Unit ns ns Remarks Master mode Master mode Master mode Maximum value is applied when m, n = 1, 8. Otherwise, the minimum value is applied. Master mode Master mode Start condition hold time tHD;STA SCL0 SDA0 (−1 + nm / 2) tMCLK − 20 (−1 + nm) tMCLK + 20 ns Stop condition setup time Start condition setup time Bus free time between stop condition and start condition Data hold time tSU;STO tSU;STA SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 (1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20 (1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20 ns ns tBUF (2 nm + 4) tMCLK − 20 ⎯ ns tHD;DAT 3 tMCLK − 20 ⎯ ns Master mode Master mode When assuming that “L” of SCL is not extended, the minimum value is applied to first bit of continuous data. Otherwise, the maximum value is applied. Minimum value is applied to interrupt at 9th SCL↓. Maximum value is applied to interrupt at 8th SCL↓. At reception At reception Undetected when 1 tMCLK is used at reception Undetected when 1 tMCLK is used at reception Undetected when 1 tMCLK is used at reception At reception At slave transmission mode At slave transmission mode Data setup time tSU;DAT SCL0 SDA0 (−2 + nm / 2) tMCLK − 20 (−1 + nm / 2) tMCLK + 20 ns R = 1.7 kΩ, C = 50 pF*1 Setup time between clearing interrupt and tSU;INT SCL0 SCL rising (nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20 ns SCL clock “L” width SCL clock “H” width Start condition detection Stop condition detection Restart condition detection condition Bus free time Data hold time Data setup time tLOW tHIGH tHD;STA tSU;STO tSU;STA tBUF tHD;DAT tSU;DAT SCL0 SCL0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 4 tMCLK − 20 4 tMCLK − 20 2 tMCLK − 20 2 tMCLK − 20 2 tMCLK − 20 2 tMCLK − 20 2 tMCLK − 20 tLOW − 3 tMCLK − 20 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ns ns ns ns ns ns ns ns (Continued) 55 MB95110B Series (Continued) Parameter Data hold time Data setup time SDA↓→SCL↑ (at wake-up function) Sym- Pin Condition bol name tHD;DAT tSU;DAT SCL0 SDA0 SCL0 R = 1.7 kΩ, SDA0 C = 50 pF*1 SCL0 SDA0 Value*2 Min 0 tMCLK − 20 Oscillation stabilization wait time + 2 tMCLK − 20 Max ⎯ ⎯ ⎯ Unit ns ns Remarks At reception At reception tWAKEUP ns *1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : • Refer to “ (2) Source Clock/Machine Clock” for tMCLK. • m is CS4 bit and CS3 bit (bit 4 and bit 3) of clock control register (ICCR) . • n is CS2 bit to CS0 bit (bit 2 to bit 0) of clock control register (ICCR) . • Actual timing of I2C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of ICCR0 register. • Standard-mode : m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz. Setting of m and n limits the machine clock that can be used below. (m, n) = (1, 8) : 0.9 MHz < tMCLK ≤ 1 MHz (m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz (m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz (m, n) = (1, 98) : 0.9 MHz < tMCLK ≤ 10 MHz • Fast-mode : m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz. Setting of m and n limits the machine clock that can be used below. (m, n) = (1, 8) : 3.3 MHz < tMCLK ≤ 4 MHz (m, n) = (1, 22) , (5, 4) : 3.3 MHz < tMCLK ≤ 8 MHz (m, n) = (6, 4) : 3.3 MHz < tMCLK ≤ 10 MHz 56 MB95110B Series 5. A/D Converter (1) A/D Converter Electrical Characteristics (AVcc = Vcc = 1.8 V to 3.3 V [Flash memory product], AVcc = Vcc = 1.8 V to 3.6 V [MASK ROM product], AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Resolution Total error Linearity error Differential linear error ⎯ Symbol Value Min ⎯ − 3.0 − 2.5 − 1.9 Typ ⎯ ⎯ ⎯ ⎯ Max 10 + 3.0 + 2.5 + 1.9 Unit bit LSB LSB LSB Flash memory product : 2.7 V ≤ AVcc ≤ 3.3 V MASK ROM product : 2.7 V ≤ AVcc ≤ 3.6 V 1.8 V ≤ AVcc < 2.7 V Flash memory product : 2.7 V ≤ AVcc ≤ 3.3 V MASK ROM product : 2.7 V ≤ AVcc ≤ 3.6 V 1.8 V ≤ AVcc < 2.7 V Flash memory product : 2.7 V ≤ AVcc ≤ 3.3 V MASK ROM product : 2.7 V ≤ AVcc ≤ 3.6 V 1.8 V ≤ AVcc < 2.7 V Flash memory product : 2.7 V ≤ AVcc ≤ 3.3 V MASK ROM product : 2.7 V ≤ AVcc ≤ 3.6 V external impedance < at 1.8 kΩ 1.8 V ≤ AVcc < 2.7 V external impedance < at 14.8 kΩ Remarks Zero transition voltage VOT AVss − 1.5 LSB AVss + 0.5 LSB AVss + 2.5 LSB AVss − 0.5 LSB AVss + 1.5 LSB AVss + 3.5 LSB AVcc − 3.5 LSB AVcc − 1.5 LSB AVcc + 0.5 LSB AVcc − 2.5 LSB AVcc − 0.5 LSB AVcc + 1.5 LSB 1.3 ⎯ ⎯ 140 V V Full-scale transition voltage VFST V V μs μs Compare time ⎯ 20 140 0.4 Sampling time ⎯ ⎯ ∞ μs 30 Analog input current Analog input voltage Reference voltage Reference voltage supply current −0.3 AVss AVss + 1.8 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 400 ⎯ ∞ + 0.3 AVcc AVcc 600 5 μs μA V V μA μA IAIN VAIN ⎯ IR IRH AVcc pin AVcc pin, During A/D operation AVcc pin, at stop mode 57 MB95110B Series (2) Notes on Using A/D Converter • About the external impedance of analog input and its sampling time A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin. • Analog input equivalent circuit R Analog input pin C During sampling : ON Comparator 2.7 V ≤ AVcc ≤ 3.6 V 1.8 V ≤ AVcc < 2.7 V Note : The values are reference values. R 1.7 kΩ (Max) 84 kΩ (Max) C 14.5 pF (Max) 25.2 pF (Max) • The relationship between external impedance and minimum sampling time (External impedance = 0 kΩ to 100 kΩ) AVcc ≥ 2.7 V 100 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 (External impedance = 0 kΩ to 20 kΩ) AVcc ≥ 2.7 V External impedance [kΩ] AVcc ≥ 1.8 V 20 25 30 35 40 External impedance [kΩ] Minimum sampling time [μs] Minimum sampling time [μs] • About errors As |AVCC − AVSS| becomes smaller, values of relative errors grow larger. 58 MB95110B Series (3) Definition of A/D Converter Terms • Resolution The level of analog variation that can be distinguished by the A/D converter. When the number of bits is 10, analog voltage can be divided into 210 = 1024. • Linearity error (unit : LSB) The deviation between the value along a straight line connecting the zero transition point (“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point (“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained. • Differential linear error (Unit : LSB) Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. • Total error (unit: LSB) Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error, linearity error, quantum error, and noise. Ideal I/O characteristics 3FFH 3FEH 3FDH 1.5 LSB VFST 3FFH 3FEH 3FDH Total error Actual conversion characteristic Digital output 004H 003H 002H 001H 0.5 LSB AVSS AVCC VOT 1 LSB Digital output {1 LSB × (N − 1) + 0.5 LSB} 004H 003H 002H 001H AVSS AVCC VNT Actual conversion characteristic Ideal characteristics Analog input Analog input 1 LSB = AVCC − AVSS (V) 1024 Total error of digital output N = VNT − {1 LSB × (N − 1) + 0.5 LSB} [LSB] 1 LSB N : A/D converter digital output value VNT : A voltage at which digital output transits from (N − 1) to N. (Continued) 59 MB95110B Series (Continued) Zero transition error 004H Actual conversion characteristic Full-scale transition error Ideal characteristics 3FFH Digital output Digital output 003H Ideal characteristics Actual conversion characteristic Actual conversion characteristic 3FEH VFST 002H 3FDH (measurement value) 001H VOT (measurement value) Actual conversion characteristic 3FCH AVSS Analog input AVCC AVSS Analog input AVCC Linearity error 3FFH 3FEH 3FDH Actual conversion characteristic Differential linear error Ideal characteristics N + 1H {1 LSB × N + VOT} VFST (measurement value) Actual conversion characteristic Digital output Digital output V (N + 1) T NH VNT 004H 003H 002H 001H AVSS Actual conversion characteristic Ideal characteristics VOT (measurement value) N − 1H VNT Actual conversion characteristic N − 2H AVCC AVSS AVCC Analog input Analog input Linear error in digital output N = VNT − {1 LSB × N + VOT} 1 LSB −1 (N + 1) T − VNT Differential linear error in digital output N = V 1 LSB N : A/D converter digital output value VNT : A voltage at which digital output transits from (N − 1) to N. VOT (Ideal value) = AVSS + 0.5 LSB [V] VFST (Ideal value) = AVCC − 1.5 LSB [V] 60 MB95110B Series 6. Flash Memory Program/Erase Characteristics Parameter Sector erase time (4 Kbytes sector) Sector erase time (16 Kbytes sector) Byte programming time Erase/program cycle Power supply voltage at erase/program Flash data retention time Value Min ⎯ ⎯ ⎯ 10000 2.7 20*3 Typ 0.2*1 0.5*1 32 ⎯ ⎯ ⎯ Max 3.0*2 12.0*2 3600 ⎯ 3.3 ⎯ Unit s s μs cycle V year Average TA = +85 °C Remarks Excludes 00H programming prior erasure Excludes 00H programming prior erasure Excludes system-level overhead *1 : TA = +25 °C, Vcc = 3.0 V, 10000 cycles *2 : TA = +85 °C, Vcc = 2.7 V, 10000 cycles *3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at +85 °C) . 61 MB95110B Series ■ MASK OPTIONS Part number No Specifying procedure Clock mode select • Single-system clock mode • Dual-system clock mode Low voltage detection reset* • With low voltage detection reset • Without low voltage detection reset MB95116B MB95F118BS MB95F118BW Setting disabled Dual-system clock mode MB95FV100D-101 Setting disabled Changing by the switch on MCU board Specify when Setting disabled ordering MASK Selectable Single-system clock mode 1 2 No No No No 3 Selectable Selection of oscillation 1 : ( 22 − 2) /FCH stabilization wait time • Selectable the initial value 2 : ( 212 − 2) /FCH 3 : ( 213 − 2) /FCH of main clock oscillation stabilization wait time 4 : ( 214 − 2) /FCH Fixed to oscillation stabilization wait time of (214-2) /FCH Fixed to oscillation stabilization wait time of (214-2) /FCH Fixed to oscillation stabilization wait time of (214-2) /FCH * : Low voltage detection reset is options of 5-V products. ■ ORDERING INFORMATION Part number MB95116BPV2 MB95F118BSPV2 MB95F118BWPV2 MB95116BPMT MB95F118BSPMT MB95F118BWPMT MB95116BPMC MB95F118BSPMC MB95F118BWPMC MB2146-301A (MB95FV100D-101PBT) Package 48-pin plastic BCC (LCC-48P-M09) 48-pin plastic LQFP (FPT-48P-M26) 52-pin plastic LQFP (FPT-52P-M01) MCU board 224-pin plastic PFBGA (BGA-224P-M08) ( ) 62 MB95110B Series ■ PACKAGE DIMENSIONS 48-pin plastic BCC Lead pitch Package width × package length Sealing method Mounting height Weight 0.50 mm 7.00 mm × 7.00 mm Plastic mold 0.80 mm Max 0.06 g (LCC-48P-M09) 48-pin plastic BCC (LCC-48P-M09) 7.00±0.10(.276±.004) 37 25 25 0.75±0.05 (.030±.002) (Mount height) 6.20(.244)TYP 0.50±0.10 (.020±.004) 37 0.50(.020) TYP 0.50(.020) TYP 6.15(.242)TYP 7.00±0.10 (.276±.004) INDEX AREA 6.20(.244) TYP 0.50±0.10 (.020±.004) 6.15(.242) TYP 6.25(.246) REF 5.00(.197) REF "A" 1 13 13 "C" 0.075±0.025 (.003±.001) (Stand off) Details of "A" part 8-0.60±0.06 (8-.024±.002) 5.00(.197)REF 6.25(.246)REF "B" 1 Details of "B" part 0.65±0.06 (.026±.002) C0.2(.008) 0.55±0.06 (.022±.002) Details of "C" part 0.55±0.06 (.022±.002) 0.05(.002) 0.14(.006) MIN 0.30±0.06 (.012±.002) 0.55±0.06 (.022±.002) 0.55±0.06 (.022±.002) C 2004 FUJITSU LIMITED C48062S-c-1-1 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 63 MB95110B Series 48-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.50 mm 7 × 7 mm Gullwing Plastic mold 1.70 mm MAX 0.17 g P-LFQFP48-7×7-0.50 (FPT-48P-M26) Code (Reference) 48-pin plastic LQFP (FPT-48P-M26) Note 1) * : These dimensions include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 9.00±0.20(.354±.008)SQ * 7.00 –0.10 .276 –.004 SQ 36 25 +0.40 +.016 0.145±0.055 (.006±.002) 37 24 0.08(.003) INDEX Details of "A" part 1.50 –0.10 .059 –.004 +0.20 +.008 (Mounting height) 48 13 "A" 0˚~8˚ LEAD No. 0.50(.020) 1 12 0.10±0.10 (.004±.004) (Stand off) 0.20±0.05 (.008±.002) 0.08(.003) M 0.25(.010) 0.60±0.15 (.024±.006) C 2003 FUJITSU LIMITED F48040S-c-2-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 64 MB95110B Series (Continued) 52-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Code (Reference) 0.65 mm 10.0 × 10.0 mm Gullwing Plastic mold 1.70 mm Max P-LQFP52-10×10-0.65 (FPT-52P-M01) 52-pin plastic LQFP (FPT-52P-M01) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 12.00±0.20(.472±.008)SQ * 10.00±0.10(.394±.004)SQ 39 27 0.145±0.055 (.006±.002) 40 26 Details of "A" part 0.10(.004) 1.50 –0.10 .059 –.004 +0.20 +.008 (Mounting height) INDEX 0˚~8˚ 52 14 0.10±0.10 (.004±.004) (Stand off) "A" 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) LEAD No. 1 13 0.65(.026) 0.30 .012 +0.065 –0.035 +.0027 –.0014 0.13(.005) M C 2005 FUJITSU LIMITED F52001S-c-1-1 Dimensions in mm (inches). Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ 65 MB95110B Series MEMO 66 MB95110B Series MEMO 67 FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD. 151 Lorong Chuan, #05-08 New Tech Park, Singapore 556741 Tel: +65-6281-0770 Fax: +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. 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