MB95F118NS

FUJITSU SEMICONDUCTOR DATA SHEET DS07-12611-1E 8-bit Proprietary Microcontrollers CMOS F2MC-8FX MB95110M series MB95117M/F114MS/F114NS/F116MS/F116NS/ MB95F118MS/F118NS/F114MW/F114NW/F116MW/F116NW/ MB95F118MW/F118NW/FV100D-103 ■ DESCRIPTION The MB95110M series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions. Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller. ■ FEATURES • F2MC-8FX CPU core Instruction set optimized for controllers • Multiplication and division instructions • 16-bit arithmetic operations • Bit test branch instruction • Bit manipulation instructions etc. • Clock • Main clock • Main PLL clock • Sub clock (for dual clock product) • Sub PLL clock (for dual clock product) • Timer • 8/16-bit compound timer × 2 channels • 8/16-bit PPG × 2 channels • 16-bit PPG • Timebase timer • Watch prescaler (for dual clock product) (Continued) Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development. Copyright©2006 FUJITSU LIMITED All rights reserved MB95110M Series (Continued) • LIN-UART • Full duplex double buffer • Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable • UART/SIO • Full duplex double buffer • Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable • I2C* Built-in wake-up function • External interrupt • Interrupt by edge detection (rising, falling, or both edges can be selected) • Can be used to recover from low-power consumption (standby) modes. • 8/10-bit A/D converter 8-bit or 10-bit resolution can be selected • Low-power consumption (standby) mode • Stop mode • Sleep mode • Watch mode (for dual clock product) • Timebase timer mode • I/O port • The number of maximum ports • Single clock product : 39 ports • Dual clock product : 37 ports • Configuration • General-purpose I/O ports (N-ch open drain) : 2 ports • General-purpose I/O ports (CMOS) : Single clock product : 37 ports Dual clock product : 35 ports • Programmable input voltage levels of port Automotive input level / CMOS input level / hysteresis input level • Flash memory security function Protects the content of Flash memory (Flash memory device only) * : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. 2 MB95110M Series ■ MEMORY LINEUP Flash memory MB95F114MS/F114NS MB95F114MW/F114NW MB95F116MS/F116NS MB95F116MW/F116NW MB95F118MS/F118NS MB95F118MW/F118NW 16 Kbytes 32 Kbytes 60 Kbytes RAM 512 bytes 1 Kbyte 2 Kbytes 3 MB95110M Series ■ PRODUCT LINEUP Part number MB95117M Parameter Type ROM capacity* Reset output Option*2 Clock system Low voltage detection reset Selectable single/ dual clock*3 Yes / No No : : : : : : 1 MB95F114MS MB95F114NS MB95F114MW MB95F114NW MB95F116MS MB95F116NS MB95F116MW MB95F116NW MB95F118MS MB95F118NS MB95F118MW MB95F118NW Flash memory product 60 Kbytes (Max) 2 Kbytes (Max) Yes Single clock Yes No Dual clock Yes MASK ROM product 48 Kbytes 2 Kbytes RAM capacity*1 CPU functions Number of basic instructions Instruction bit length Instruction length Data bit length Minimum instruction execution time Interrupt processing time 136 8 bits 1 to 3 bytes 1, 8, and 16 bits 61.5 ns (at machine clock frequency 16.25 MHz) 0.6 µs (at machine clock frequency 16.25 MHz) • Single clock product : 39 ports (N-ch open drain : 2 ports, CMOS : 37 ports) General purpose I/O • Dual clock product : 37 ports (N-ch open drain : 2 ports, CMOS : 35 ports) ports Programmable input voltage levels of port : Automotive input level / CMOS input level / hysteresis input level Timebase timer Peripheral functions Watchdog timer Wild register Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz) Reset generated cycle At main oscillation clock 10 MHz : Min 105 ms At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms Capable of replacing 3 bytes of ROM data Master/slave sending and receiving Bus error function and arbitration function Detecting transmitting direction function Start condition repeated generation and detection functions Built-in wake-up function Data transfer capable in UART/SIO Full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate generator NRZ type transfer format, error detected function LSB-first or MSB-first can be selected. Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable (Continued) I2C UART/SIO 4 MB95110M Series (Continued) Part number MB95117M Parameter MB95F114MS MB95F114NS MB95F114MW MB95F114NW MB95F116MS MB95F116NS MB95F116MW MB95F116NW MB95F118MS MB95F118NS MB95F118MW MB95F118NW LIN-UART Dedicated reload timer allowing a wide range of communication speeds to be set. Full duplex double buffer. Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable. LIN functions available as the LIN master or LIN slave. 8/10-bit A/D converter 8-bit or 10-bit resolution can be selected. (8 channels) Each channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit timer × 1 channel”. Built-in timer function, PWC function, PWM function, capture function, and square waveform output Count clock : 7 internal clocks and external clock can be selected PWM mode or one-shot mode can be selected. Counter operating clock : 8 selectable clock sources Support for external trigger start Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG × 1 channel”. Counter operating clock : Eight selectable clock sources Peripheral functions 8/16-bit compound timer (2 channels) 16-bit PPG 8/16-bit PPG (2 channels) Count clock : 4 selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s) Watch counter Counter value can be set from 0 to 63. (Capable of counting for 1minute when (for dual clock product) selecting clock source 1 second and setting counter value to 60) Watch prescaler 4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s) (for dual clock product) External interrupt (8 channels) Interrupt by edge detection (rising, falling, or both edges can be selected.) Can be used to recover from standby modes. Supports automatic programming, Embedded AlgorithmTM *4 Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of write/erase cycles (Minimum) : 10000 times Data retention time : 20 years Erase can be performed on each block Block protection with external programming voltage Flash Security Feature for protecting the content of the Flash Sleep, stop, watch (for dual clock product) , and timebase timer Flash memory Standby mode *1 : For ROM capacity and RAM capacity, refer to “1. Memory space” in “■ CPU CORE”. *2 : For details of option, refer to “■ MASK OPTION”. *3 : Specify clock mode when ordering MASK ROM. *4 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc. Note : Part number of the evaluation device in MB95110M series is MB95FV100D-103. When using it, the MCU board (MB2146-303A) is required. 5 MB95110M Series ■ OSCILLATION STABILIZATION WAIT TIME The initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. The maximum value is shown as follows. Oscillation stabilization wait time (2 −2) /FCH 14 Remarks Approx. 4.10 ms (at main oscillation clock 4 MHz) ■ PACKAGES AND CORRESPONDING PRODUCTS Part number MB95117M Package FPT-52P-M01 BGA-224P-M08 : Available : Unavailable MB95F114MS/F114NS MB95F114MW/F114NW MB95F116MS/F116NS MB95F116MW/F116NW MB95FV100D-103 MB95F118MS/F118NS MB95F118MW/F118NW 6 MB95110M Series ■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS • Notes on Using Evaluation Products The Evaluation product has not only the functions of the MB95110M series but also those of other products to support software development for multiple series and models of the F2MC-8FX family. The I/O addresses for peripheral resources not used by the MB95110M series are therefore access-barred. Read/write access to these access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting in unexpected malfunctions of hardware or software. Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are used, the address may be read or write unexpectedly) . Note that the values read from barred addresses are different between the Evaluation product and the Flash memory or MASK ROM product. Therefore, the data must not be used for software processing. The Evaluation product do not support the functions of some bits in single-byte registers. Read/write access to these bits does not cause hardware malfunctions. Since the Evaluation, Flash memory, and MASK ROM products are designed to behave completely the same way in terms of hardware and software. • Difference of Memory Spaces If the amount of memory on the Evaluation product is different from that of the Flash memory or MASK ROM product, carefully check the difference in the amount of memory from the model to be actually used when developing software. For details of memory space, refer to “■ CPU CORE”. • Current Consumption • The current consumption of Flash memory product is typically greater than for MASK ROM product. • For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”. • Package For details of information on each package, refer to “■ PACKAGE AND CORRESPONDING PRODUCTS” and “■ PACKAGE DIMENSIONS”. • Operating Voltage The operating voltage are different among the Evaluation, Flash memory, and MASK ROM products. For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS” • Difference between RST and MOD Pins The input type of RST and MOD pins is CMOS inputs on the Flash memory product. The RST and MOD pins are hysteresis inputs on the MASK ROM product. A pull-down resistor is provided for the MOD pin of the MASK ROM product. 7 MB95110M Series ■ PIN ASSIGNMENTS (TOP VIEW) P13/TRG0/ADTG P61/PPG11 P60/PPG10 52 51 50 49 48 47 46 45 44 43 42 41 40 P65/SCK P66/SOT P67/SIN P37/AN07 P36/AN06 P35/AN05 NC P34/AN04 P33/AN03 P32/AN02 P31/AN01 P30/AN00 AVss 1 2 3 4 5 6 7 8 9 10 11 12 13 P07/INT07 P14/PPG0 P12/UCK0 P63/TO11 P62/TO10 P11/UO0 P64/EC1 P10/UI0 P15 NC 39 38 37 36 35 34 33 32 31 30 29 28 27 P06/INT06 P05/INT05 P04/INT04 P03/INT03 P02/INT02 P01/INT01 NC P00/INT00 RST PG1/X0A* PG2/X1A* C Vcc 14 15 16 17 18 19 20 21 22 23 24 25 26 AVcc NC P51/SDA0 P50/SCL0 MOD X0 X1 P24/EC0 P23/TO01 P22/TO00 P21/PPG01 (FPT-52P-M01) * : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin. 8 P20/PPG00 Vss MB95110M Series ■ PIN DESCRIPTION Pin no. 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 30 31 Pin name P65/SCK K P66/SOT P67/SIN P37/AN07 P36/AN06 P35/AN05 P34/AN04 P33/AN03 P32/AN02 P31/AN01 P30/AN00 AVss AVcc P24/EC0 P23/TO01 P22/TO00 P21/PPG01 P20/PPG00 P51/SDA0 I P50/SCL0 MOD X0 X1 Vss Vcc C PG2/X1A H/A PG1/X0A RST B’ B A ⎯ ⎯ ⎯ H ⎯ ⎯ A/D converter power supply pin (GND) A/D converter power supply pin General-purpose I/O port. The pin is shared with 8/16-bit compound timer ch.0 clock input. General-purpose I/O port. The pins are shared with 8/16-bit compound timer ch.0 output. General-purpose I/O port. The pins are shared with 8/16-bit PPG ch.0 output. General-purpose I/O port. The pin is shared with I2C ch.0 data I/O. General-purpose I/O port. The pin is shared with I2C ch.0 clock I/O. Operating mode designation pin Main clock oscillation input pin Main clock oscillation I/O pin Power supply pin (GND) Power supply pin Capacitor connection pin Single clock product is general-purpose port (PG2). Dual clock product is sub clock I/O oscillation pin (32 kHz). Single clock product is general-purpose port (PG1). Dual clock product is sub clock input oscillation pin (32 kHz). Reset pin (Continued) J General-purpose I/O port. The pins are shared with A/D converter analog input. L I/O Circuit type* Function General-purpose I/O port. The pin is shared with LIN-UART clock I/O. General-purpose I/O port. The pin is shared with LIN-UART data output. General-purpose I/O port. The pin is shared with LIN-UART data input. 9 MB95110M Series (Continued) Pin no. 32 34 35 36 37 38 39 40 41 42 43 Pin name P00/INT00 P01/INT01 P02/INT02 P03/INT03 P04/INT04 P05/INT05 P06/INT06 P07/INT07 P10/UI0 P11/UO0 P12/UCK0 P13/TRG0/ ADTG P14/PPG0 P15 P60/PPG10 P61/PPG11 P62/TO10 P63/TO11 P64/EC1 NC ⎯ K H G General-purpose I/O port. The pin is shared with UART/SIO ch.0 data input. General-purpose I/O port. The pin is shared with UART/SIO ch.0 data output. General-purpose I/O port. The pin is shared with UART/SIO ch.0 clock I/O. General-purpose I/O port. The pin is shared with 16-bit PPG ch.0 trigger input (TRG0) and A/D trigger input (ADTG). General-purpose I/O port. The pin is shared with 16-bit PPG ch.0 output. General-purpose I/O port. General-purpose I/O port. The pins are shared with 8/16-bit PPG ch.1 output. General-purpose I/O port. The pins are shared with 8/16-bit compound timer ch.1 output. General-purpose I/O port. The pin is shared with 8/16-bit compound timer ch.1 clock input. Internal connect pin. Be sure this pin is left open. C General-purpose I/O port. The pins are shared with external interrupt input. Large current port. I/O Circuit type* Function 44 45 47 48 49 50 51 52 7, 20, 33, 46 *: For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE” 10 MB95110M Series ■ I/O CIRCUIT TYPE Type Circuit Remarks • Oscillation circuit • High-speed side Feedback resistance : approx. 1 MΩ • Low-speed side Feedback resistance : approx. 24 MΩ (Evaluation product : approx. 10 MΩ) Dumping resistance : approx. 144 MΩ) (Evaluation product : without dumping resistance) • Only for input Hysteresis input only for MASK ROM product With pull-down resistor only for MASK ROM product • Reset output • Hysteresis input X1 (X1A) Clock input N-ch A X 0 (X0A) Standby control B R Mode input Reset input B’ N-ch Reset output P-ch Digital output Digital output • CMOS output • Hysteresis input • Automotive input N-ch C Standby control External interrupt enable Hysteresis input Automotive input R P-ch P-ch Pull-up control Digital output Digital output CMOS input Hysteresis input Automotive input • • • • • CMOS output CMOS input Hysteresis input With pull-up control Automotive input G N-ch Standby control (Continued) 11 MB95110M Series Type Circuit • • • • Remarks CMOS output Hysteresis input With pull-up control Automotive input R P-ch P-ch Pull-up control Digital output Digital output N-ch H Hysteresis input Standby control Automotive input • • • • N-ch open drain output CMOS input Hysteresis input Automotive input N-ch Digital output CMOS input Hysteresis input I Standby control Automotive input • • • • • CMOS output Hysteresis input Analog input With pull-up control Automotive input R P-ch P-ch Pull-up control Digital output Digital output Analog input Hysteresis input J N-ch A/D control Standby control P-ch Automotive input • CMOS output • Hysteresis input • Automotive input Digital output Digital output Hysteresis input K N-ch Standby control Automotive input (Continued) 12 MB95110M Series (Continued) Type Circuit P-ch Remarks Digital output Digital output CMOS input Hysteresis input Automotive input • • • • CMOS output CMOS input Hysteresis input Automotive input N-ch L Standby control 13 MB95110M Series ■ HANDLING DEVICES • Preventing Latch-up Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used. Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC pin and VSS pin. When latch-up occurs, power supply current increases rapidly and might thermally damage elements. Also, take care to prevent the analog power supply voltage (AVCC) and analog input voltage from exceeding the digital power supply voltage (VCC) when the analog system power supply is turned on or off. • Stable Supply Voltage Supply voltage should be stabilized. A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range of the Vcc power-supply voltage. For stabilization, in principle, keep the variation in Vcc ripple (p-p value) in a commercial frequency range (50/60 Hz) not to exceed 10% of the standard Vcc value and suppress the voltage variation so that the transient variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched. • Precautions for Use of External Clock Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from sub clock mode or stop mode. 14 MB95110M Series ■ PIN CONNECTION • Treatment of Unused Pin Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/ output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. If there is unused output pin, make it open. • Treatment of Power Supply Pins on A/D Converter Connect to be AVCC = VCC and AVSS = VSS even if the A/D converter is not in use. Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 µF ceramic capacitor as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device. • Power Supply Pins In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS pins near this device. • Mode Pin (MOD) Connect the mode pin directly to VCC or VSS pins. To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the mode pins to VCC or VSS pins and to provide a low-impedance connection. Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC pin must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the diagram below. • C pin connection diagram C CS • NC Pins Any pins marked “NC” (not connected) must be left open. • Analog Power Supply Always set the same potential to AVCC and VCC. When VCC > AVCC, the current may flow through the AN00 to AN07 pins. 15 MB95110M Series ■ PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL PROGRAMMER • Supported Parallel Programmers and Adapters The following table lists supported parallel programmers and adapters. Package Applicable adapter model FPT-52P-M01 TEF110-95118PMC Parallel programmers AF9708 (Ver 02.35G or more) AF9709/B (Ver 02.35G or more) AF9723+AF9834 (Ver 02.08E or more) Note : For information on applicable adapter models and parallel programmers, contact the following: Flash Support Group, Inc. TEL: +81-53-428-8380 • Sector Configuration The individual sectors of Flash memory correspond to addresses used for CPU access and programming by the parallel programmer as follows: • MB95F118MS/F118NS/F118MW/F118NW (60 Kbytes) Flash memory SA1 (4 Kbytes) SA2 (4Kbytes) 2FFFH 3000H SA3 (4 Kbytes) 3FFFH 4000H SA4 (16 Kbytes) 7FFFH 8000H SA5 (16 Kbytes) SA6 (4 Kbytes) CFFFH D000H SA7 (4 Kbytes) DFFFH E000H SA8 (4 Kbytes) EFFFH F000H SA9 (4 Kbytes) FFFFH 7FFFFH *: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer programs data into Flash memory. These programmer addresses are used for the parallel programmer to program or erase data in Flash memory. 7EFFFH 7F000H 7DFFFH 7E000H 7CFFFH 7D000H Upper bank Lower bank CPU address 1000H 1FFFH 2000H Programmer address* 71000H 71FFFH 72000H 72FFFH 73000H 73FFFH 74000H 77FFFH 78000H 7BFFFH 7C000H BFFFH C000H 16 MB95110M Series • MB95F116MS/F116NS/F116MW/F116NW (32 Kbytes) Flash memory SA5 (16 Kbytes) BFFFH C000H SA6 (4 Kbytes) CFFFH D000H SA7 (4 Kbytes) DFFFH E000H SA8 (4 Kbytes) EFFFH F000H SA9 (4 Kbytes) FFFFH 7FFFFH *: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer programs data into Flash memory. These programmer addresses are used for the parallel programmer to program or erase data in Flash memory. 7EFFFH 7F000H 7DFFFH 7E000H 7CFFFH 7D000H 7BFFFH 7C000H CPU address 8000H Programmer address* 78000H • MB95F114MS/F114NS/F114MW/F114NW (16 Kbytes) Flash memory SA6 (4 Kbytes) CFFFH D000H SA7 (4 Kbytes) DFFFH E000H SA8 (4 Kbytes) EFFFH F000H SA9 (4 Kbytes) FFFFH 7FFFFH *: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer programs data into Flash memory. These programmer addresses are used for the parallel programmer to program or erase data in Flash memory. 7EFFFH 7F000H 7DFFFH 7E000H 7CFFFH 7D000H CPU address C000H Programmer address* 7C000H • Programming Method 1) Set the type code of the parallel programmer to “17222”. 2) Load program data to programmer addresses 71000H to 7FFFFH. 3) Programmed by parallel programmer 17 MB95110M Series ■ BLOCK DIAGRAM F MC-8FX CPU RST X0,X1 PG2/X1A* PG1/X0A* Reset control Clock control Watch prescaler Watch counter P00/INT00 to P07/INT07 P10/UI0 P11/UO0 P12/UCK0 P13/TRG0/ADTG P14/PPG0 P15 P20/PPG00 P21/PPG01 P22/TO00 P23/TO01 P24/EC0 P30/AN00 to P37/AN07 AVCC AVSS P50/SCL0 P51/SDA0 8/16-bit PPG ch.0 16-bit PPG UART/SIO Internal bus 8/16-bit compound timer ch.1 External interrupt 8/16-bit PPG ch.1 P60/PPG10 P61/PPG11 P62/TO10 P63/TO11 P64/EC1 P65/SCK LIN-UART P66/SOT P67/SIN ROM RAM Interrupt control Wild register 2 8/16-bit compound timer ch.0 8/10-bit A/D converter I 2C Port Port Other pins MOD, VCC, VSS, C, NC * : Single clock product is a general-purpose port, and dual clock product is a sub clock oscillation pin. 18 MB95110M Series ■ CPU CORE 1. Memory space Memory space of the MB95110M series is 64 Kbytes and consists of I/O area, data area, and program area. The memory space includes special-purpose areas such as the general-purpose registers and vector table. Memory map of the MB95110M series is shown below. • Memory Map MB95117M 0000H I/O 0080H 0100H 0200H 0880H 0F80H Expanded I/O 1000H Access prohibited 4000H MASK ROM 48 Kbytes FFFFH RAM 2 Kbytes Register MB95F114MS/F114NS MB95F114MW/F114NW MB95F116MS/F116NS MB95F116MW/F116NW MB95F118MS/F118NS MB95F118MW/F118NW 0000H I/O 0080H RAM 2 Kbytes 0000H MB95FV100D-103 I/O 0080H RAM 3.75 Kbytes 0100H Register 0200H Address #1 0F80H Expanded I/O Address #2 0100H Register 0200H Access prohibited Access prohibited 0F80H Expanded I/O 1000H Flash memory Flash memory 60 Kbytes FFFFH FFFFH Flash memory MB95F114MS/F114NS MB95F114MW/F114NW MB95F116MS/F116NS MB95F116MW/F116NW MB95F118MS/F118NS MB95F118MW/F118NW 16 Kbytes 32 Kbytes 60 Kbytes RAM 512 bytes 1 Kbyte 2 Kbytes Address #1 0280H 0480H 0880H Address #2 C000H 8000H 1000H 19 MB95110M Series 2. Register The MB95110M series has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The dedicated registers are as follows: Program counter (PC) : A 16-bit register to indicate locations where instructions are stored. Accumulator (A) : A 16-bit register for temporary storage of arithmetic operations. In the case of an 8-bit data processing instruction, the lower 1 byte is used. Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator. In the case of an 8-bit data processing instruction, the lower 1 byte is used. Index register (IX) : A 16-bit register for index modification. Extra pointer (EP) : A 16-bit pointer to point to a memory address. Stack pointer (SP) : A 16-bit register to indicate a stack area. Program status (PS) : A 16-bit register for storing a register bank pointer, a direct bank pointer, and a condition code register. 16-bit PC A T IX EP SP PS Initial Value : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status FFFDH 0000H 0000H 0000H 0000H 0000H 0030H The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer (DP) and the lower 8 bits for use as a condition code register (CCR) . (Refer to the diagram below.) • Structure of the program status bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 PS R4 R3 R2 R1 R0 DP2 DP1 bit 8 DP0 bit 7 H bit 6 I bit 5 IL1 bit 4 IL0 bit 3 N bit 2 Z bit 1 V bit 0 C RP DP CCR 20 MB95110M Series The RP indicates the address of the register bank currently being used. The relationship between the content of RP and the real address conforms to the conversion rule illustrated below: • Rule for Conversion of Actual Addresses in the General-purpose Register Area RP upper "0" "0" "0" "0" "0" "0" "0" "1" A8 R4 A7 R3 A6 R2 A5 R1 A4 R0 A3 OP code lower b2 A2 b1 A1 b0 A0 Generated address A15 A14 A13 A12 A11 A10 A9 The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct addresses to 0080H to 00FFH. Direct bank pointer (DP2 to DP0) Specified address area Mapping area XXXB (no effect to mapping) 000B (initial value) 001B 010B 011B 100B 101B 110B 111B 0080H to 00FFH 0000H to 007FH 0000H to 007FH (without mapping) 0080H to 00FFH (without mapping) 0100H to 017FH 0180H to 01FFH 0200H to 027FH 0280H to 02FFH 0300H to 037FH 0380H to 03FFH 0400H to 047FH The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that control CPU operations at interrupt. : Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. This flag is for decimal adjustment instructions. I flag : Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”. The flag is set to “0” when reset. IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level is higher than the value indicated by these bits. IL1 0 0 1 1 N flag Z flag V flag C flag IL0 0 1 0 1 Interrupt level 0 1 2 3 Low = no interruption Priority High H flag : Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the bit is set to “0”. : Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise. : Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0” otherwise. : Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. Set to the shift-out value in the case of a shift instruction. 21 MB95110M Series The following general-purpose registers are provided: General-purpose registers: 8-bit data storage registers The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8-register. Up to a total of 32 banks can be used on the MB95110M series. The bank currently in use is specified by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0) to general-purpose register 7 (R7). • Register Bank Configuration 8-bit 1F8H This address = 0100H + 8 × (RP) Address 100H R0 R1 R2 R3 R4 R5 107H R6 R7 Bank 0 R0 R0 R1 R2 R3 R4 R5 R6 R7 R1 R2 R3 R4 R5 R6 1FFH R7 Bank 31 32 banks 32 banks (RAM area) The number of banks is limited by the usable RAM capacitance. Memory area 22 MB95110M Series ■ I/O MAP Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H, 0013H 0014H 0015H 0016H 0017H 0018H to 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H to 0034H Register abbreviation PDR0 DDR0 PDR1 DDR1 ⎯ WATR PLLC SYCC STBC RSRR TBTC WPCR WDTC ⎯ PDR2 DDR2 PDR3 DDR3 ⎯ PDR5 DDR5 PDR6 DDR6 ⎯ PDRG DDRG ⎯ PUL1 PUL2 PUL3 ⎯ Register name Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register (Disabled) Oscillation stabilization wait time setting register PLL control register System clock control register Standby control register Reset source register Timebase timer control register Watch prescaler control register Watchdog timer control register (Disabled) Port 2 data register Port 2 direction register Port 3 data register Port 3 direction register (Disabled) Port 5 data register Port 5 direction register Port 6 data register Port 6 direction register (Disabled) Port G data register Port G direction register (Disabled) Port 1 pull-up register Port 2 pull-up register Port 3 pull-up register (Disabled) R/W R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R R/W R/W R/W ⎯ R/W R/W R/W R/W ⎯ R/W R/W R/W R/W ⎯ R/W R/W ⎯ R/W R/W R/W ⎯ Initial value 00000000B 00000000B 00000000B 00000000B ⎯ 11111111B 00000000B 1010X011B 00000000B XXXXXXXXB 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B ⎯ (Continued) 23 MB95110M Series Address 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH to 0041H 0042H 0043H 0044H to 0047H 0048H 0049H 004AH 004BH 004CH to 004FH 0050H 0051H 0052H 0053H 0054H 0055H 0056H 0057H 0058H 0059H 005AH 005BH to 005FH Register abbreviation PULG T01CR1 T00CR1 T11CR1 T10CR1 PC01 PC00 PC11 PC10 ⎯ PCNTH0 PCNTL0 ⎯ EIC00 EIC10 EIC20 EIC30 ⎯ SCR SMR SSR RDR/TDR ESCR ECCR SMC10 SMC20 SSR0 TDR0 RDR0 ⎯ Register name Port G pull-up register 8/16-bit compound timer 01 control status register 1 ch.0 8/16-bit compound timer 00 control status register 1 ch.0 8/16-bit compound timer 11 control status register 1 ch.1 8/16-bit compound timer 10 control status register 1 ch.1 8/16-bit PPG1 control register ch.0 8/16-bit PPG0 control register ch.0 8/16-bit PPG1 control register ch.1 8/16-bit PPG0 control register ch.1 (Disabled) 16-bit PPG status control register (Upper byte) ch.0 16-bit PPG status control register (Lower byte) ch.0 (Disabled) External interrupt circuit control register ch.0/1 External interrupt circuit control register ch.2/3 External interrupt circuit control register ch.4/5 External interrupt circuit control register ch.6/7 (Disabled) LIN-UART serial control register LIN-UART serial mode register LIN-UART serial status register LIN-UART reception/transmission data register LIN-UART extended status control register LIN-UART extended communication control register UART/SIO serial mode control register 1 ch.0 UART/SIO serial mode control register 2 ch.0 UART/SIO serial status register ch.0 UART/SIO serial output data register ch.0 UART/SIO serial input data register ch.0 (Disabled) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ⎯ R/W R/W ⎯ R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R ⎯ Initial value 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00001000B 00000000B 00000100B 000000XXB 00000000B 00100000B 00000001B 00000000B 00000000B ⎯ (Continued) 24 MB95110M Series Address 0060H 0061H 0062H 0063H 0064H 0065H 0066H to 006BH 006CH 006DH 006EH 006FH 0070H 0071H 0072H 0073H 0074H 0075H 0076H 0077H 0078H 0079H 007AH 007BH 007CH 007DH 007EH 007FH 0F80H 0F81H 0F82H 0F83H 0F84H 0F85H Register abbreviation IBCR00 IBCR10 IBSR0 IDDR0 IAAR0 ICCR0 ⎯ ADC1 ADC2 ADDH ADDL WCSR ⎯ FSR SWRE0 SWRE1 ⎯ WREN WROR ⎯ ILR0 ILR1 ILR2 ILR3 ILR4 ILR5 ⎯ WRARH0 WRARL0 WRDR0 WRARH1 WRARL1 WRDR1 2 2 2 Register name I2C bus control register 0 ch.0 I C bus control register 1 ch.0 I2C bus status register ch.0 I2C data register ch.0 I C address register ch.0 I C clock control register ch.0 (Disabled) 8/10-bit A/D converter control register 1 8/10-bit A/D converter control register 2 8/10-bit A/D converter data register (Upper byte) 8/10-bit A/D converter data register (Lower byte) Watch counter status register (Disabled) Flash memory status register Flash memory sector writing control register 0 Flash memory sector writing control register 1 (Disabled) Wild register address compare enable register Wild register data test setting register (Mirror of register bank pointer (RP) and direct bank pointer (DP) ) Interrupt level setting register 0 Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt level setting register 4 Interrupt level setting register 5 (Disabled) Wild register address setting register (Upper byte) ch.0 Wild register address setting register (Lower byte) ch.0 Wild register data setting register ch.0 Wild register address setting register (Upper byte) ch.1 Wild register address setting register (Lower byte) ch.1 Wild register data setting register ch.1 R/W R/W R/W R R/W R/W R/W ⎯ R/W R/W R/W R/W R/W ⎯ R/W R/W R/W ⎯ R/W R/W ⎯ R/W R/W R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W Initial value 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ 000X0000B 00000000B 00000000B ⎯ 00000000B 00000000B ⎯ 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued) 25 MB95110M Series Address 0F86H 0F87H 0F88H 0F89H to 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H 0F98H 0F99H 0F9AH 0F9BH 0F9CH 0F9DH 0F9EH 0F9FH 0FA0H 0FA1H 0FA2H 0FA3H 0FA4H 0FA5H 0FA6H to 0FA9H 0FAAH 0FABH 0FACH 0FADH 0FAEH 0FAFH Register abbreviation WRARH2 WRARL2 WRDR2 ⎯ T01CR0 T00CR0 T01DR T00DR TMCR0 T11CR0 T10CR0 T11DR T10DR TMCR1 PPS01 PPS00 PDS01 PDS00 PPS11 PPS10 PDS11 PDS10 PPGS REVC ⎯ PDCRH0 PDCRL0 PCSRH0 PCSRL0 PDUTH0 PDUTL0 Register name Wild register address setting register (Upper byte) ch.2 Wild register address setting register (Lower byte) ch.2 Wild register data setting register ch.2 (Disabled) 8/16-bit compound timer 01 control status register 0 ch.0 8/16-bit compound timer 00 control status register 0 ch.0 8/16-bit compound timer 01 data register ch.0 8/16-bit compound timer 00 data register ch.0 8/16-bit compound timer 00/01 timer mode control register ch.0 8/16-bit compound timer 11 control status register 0 ch.1 8/16-bit compound timer 10 control status register 0 ch.1 8/16-bit compound timer 11 data register ch.1 8/16-bit compound timer 10 data register ch.1 8/16-bit compound timer 10/11 timer mode control register ch.1 8/16-bit PPG1 cycle setting buffer register ch.0 8/16-bit PPG0 cycle setting buffer register ch.0 8/16-bit PPG1 duty setting buffer register ch.0 8/16-bit PPG0 duty setting buffer register ch.0 8/16-bit PPG1 cycle setting buffer register ch.1 8/16-bit PPG0 cycle setting buffer register ch.1 8/16-bit PPG1 duty setting buffer register ch.1 8/16-bit PPG0 duty setting buffer register ch.1 8/16-bit PPG starting register 8/16-bit PPG output inversion register (Disabled) 16-bit PPG down counter register (Upper byte) ch.0 16-bit PPG down counter register (Lower byte) ch.0 16-bit PPG cycle setting buffer register (Upper byte) ch.0 16-bit PPG cycle setting buffer register (Lower byte) ch.0 16-bit PPG duty setting buffer register (Upper byte) ch.0 16-bit PPG duty setting buffer register (Lower byte) ch.0 R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ⎯ R R R/W R/W R/W R/W Initial value 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B ⎯ 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B (Continued) 26 MB95110M Series (Continued) Address 0FB0H to 0FBBH 0FBCH 0FBDH 0FBEH 0FBFH 0FC0H to 0FC2H 0FC3H 0FC4H to 0FE2H 0FE3H 0FE4H to 0FE6H 0FE7H 0FE8H to 0FEDH 0FEEH 0FEFH 0FF0H to 0FFFH Register abbreviation ⎯ BGR1 BGR0 PSSR0 BRSR0 ⎯ AIDRL ⎯ WCDR ⎯ ILSR2 ⎯ ILSR WICR ⎯ Register name (Disabled) LIN-UART baud rate generator register 1 LIN-UART baud rate generator register 0 UART/SIO dedicated baud rate generator prescaler selection register ch.0 UART/SIO dedicated baud rate generator baud rate setting register ch.0 (Disabled) A/D input disable register (Lower byte) (Disabled) Watch counter data register (Disabled) Input level select register 2 (Disabled) Input level select register Interrupt pin control register (Disabled) R/W ⎯ R/W R/W R/W R/W ⎯ R/W ⎯ R/W ⎯ R/W ⎯ R/W R/W ⎯ Initial value ⎯ 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B ⎯ 00111111B ⎯ 00000000B ⎯ 00000000B 01000000B ⎯ • R/W access symbols R/W : Readable/Writable R : Read only W : Write only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value. 27 MB95110M Series ■ INTERRUPT SOURCE TABLE Interrupt source External interrupt ch.0 External interrupt ch.4 External interrupt ch.1 External interrupt ch.5 External interrupt ch.2 External interrupt ch.6 External interrupt ch.3 External interrupt ch.7 UART/SIO ch.0 8/16-bit compound timer ch.0 (Lower) 8/16-bit compound timer ch.0 (Upper) LIN-UART (reception) LIN-UART (transmission) 8/16-bit PPG ch.1 (Lower) 8/16-bit PPG ch.1 (Upper) (Unused) 8/16-bit PPG ch.0 (Upper) 8/16-bit PPG ch.0 (Lower) 8/16-bit compound timer ch.1 (Upper) 16-bit PPG ch.0 I2C ch.0 (Unused) 8/10-bit A/D converter Timebase timer Watch timer/counter (Unused) 8/16-bit compound timer ch.1 (Lower) Flash memory Interrupt request number IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 IRQ20 IRQ21 IRQ22 IRQ23 Vector table address Upper FFFAH FFF8H FFF6H FFF4H FFF2H FFF0H FFEEH FFECH FFEAH FFE8H FFE6H FFE4H FFE2H FFE0H FFDEH FFDCH FFDAH FFD8H FFD6H FFD4H FFD2H FFD0H FFCEH FFCCH Lower FFFBH FFF9H FFF7H FFF5H FFF3H FFF1H FFEFH FFEDH FFEBH FFE9H FFE7H FFE5H FFE3H FFE1H FFDFH FFDDH FFDBH FFD9H FFD7H FFD5H FFD3H FFD1H FFCFH FFCDH Same level Bit name of priority order interrupt level (at simultaneous setting register occurrence) L00 [1 : 0] L01 [1 : 0] L02 [1 : 0] L03 [1 : 0] L04 [1 : 0] L05 [1 : 0] L06 [1 : 0] L07 [1 : 0] L08 [1 : 0] L09 [1 : 0] L10 [1 : 0] L11 [1 : 0] L12 [1 : 0] L13 [1 : 0] L14 [1 : 0] L15 [1 : 0] L16 [1 : 0] L17 [1 : 0] L18 [1 : 0] L19 [1 : 0] L20 [1 : 0] L21 [1 : 0] L22 [1 : 0] L23 [1 : 0] Low High 28 MB95110M Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Power supply voltage*1 Input voltage*1 Output voltage* 1 Symbol Vcc AVcc VI VO ICLAMP Σ|ICLAMP| IOL1 IOL2 Rating Min Vss − 0.3 Vss − 0.3 Vss − 0.3 − 2.0 ⎯ ⎯ Max Vss + 6.0 Vss + 6.0 Vss + 6.0 + 2.0 20 15 15 Unit V V V mA mA mA *2 *3 *3 Remarks Maximum clamp current Total maximum clamp current “L” level maximum output current Applicable to pins*4 Applicable to pins*4 Other than P00 to P07 P00 to P07 Other than P00 to P07 Average output current = operating current × operating ratio (1 pin) P00 to P07 Average output current = operating current × operating ratio (1 pin) IOLAV1 “L” level average current IOLAV2 ⎯ 4 mA 12 “L” level total maximum output current “L” level total average output current “H” level maximum output current ΣIOL ΣIOLAV IOH1 IOH2 ⎯ ⎯ ⎯ 100 mA Total average output current = operating current × operating ratio (Total of pins) Other than P00 to P07 P00 to P07 Other than P00 to P07 Average output current = operating current × operating ratio (1 pin) P00 to P07 Average output current = operating current × operating ratio (1 pin) 50 − 15 − 15 −4 mA mA IOHAV1 “H” level average current IOHAV2 ⎯ mA −8 “H” level total maximum output current “H” level total average output current ΣIOH ΣIOHAV ⎯ ⎯ − 100 − 50 mA Total average output current = operating current × operating ratio (Total of pins) (Continued) mA 29 MB95110M Series (Continued) Parameter Power consumption Operating temperature Storage temperature Symbol Pd TA Tstg Rating Min ⎯ − 40 − 55 Max 320 + 85 + 150 Unit mW °C °C Remarks *1 : The parameter is based on AVSS = VSS = 0.0 V. *2 : Apply equal potential to AVcc and Vcc. *3 : VI and Vo should not exceed VCC + 0.3 V. VI must not exceed the rating voltage. However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *4 : Applicable to pins : P00 to P07, P10 to P15, P20 to P24, P30 to P37, P60 to P67 • Use within recommended operating conditions. • Use at DC voltage (current). • +B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting resistance placed between the + B signal and the microcontroller. • The value of the limiting resistance should be set so that when the + B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this affects other devices. • Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. • Note that if the + B input is applied during power-on, the power supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. • Care must be taken not to leave the + B input pin open. • Sample recommended circuits : • Input/Output Equivalent circuits Protective diode Limiting resistance Vcc P-ch N-ch R + B input (0 V to 16 V) WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 30 MB95110M Series 2. Recommended Operating Conditions (AVss = Vss = 0.0 V) Parameter Symbol Pin name Conditions Value Min 2.5*1 Max 5.5 Unit V In normal operation Hold condition in STOP mode In normal operation Remarks 2.3 Power supply voltage VCC, AVCC ⎯ ⎯ 2.7 5.5 V Other than MB95FV100D103 5.5 V 2.3 5.5 Vcc + 0.3 Vss + 5.5 Vcc + 0.3 V MB95FV100DHold 103 condition in STOP mode VIH1 VIH2 VIHA P10, P67 P50, P51 ⎯ P00 to P07, P10 to P15, P20 to P24, P30 to P37, P60 to P67, PG1*3, PG2*3 P50, P51 *2 *2 ⎯ 0.7 Vcc 0.7 Vcc 0.8 Vcc V V V At selecting of CMOS input level At selecting of CMOS input level Pin input at selecting of AUTOMOTIVE input level “H” level input voltage VIHS1 *2 0.8 Vcc Vcc + 0.3 V Hysteresis input VIHS2 *2 ⎯ 0.8 Vcc 0.7 Vcc 0.8 Vcc Vss + 5.5 Vcc + 0.3 Vcc + 0.3 V V V Hysteresis input CMOS input (Flash memory product) Hysteresis input (MASK ROM product) (Continued) VIHM RST, MOD ⎯ 31 MB95110M Series (Continued) Conditions *2 ⎯ Value Min Vss − 0.3 Vss − 0.3 Max 0.3 Vcc 0.5 Vcc (AVss = Vss = 0.0 V) Symbol VIL VILA Pin name P10, P50, P51, P67 ⎯ P00 to P07, P10 to P15, P20 to P24, P30 to P37, P50, P51, P60 to P67, PG1*3, PG2*3 Unit V V Remarks At selecting of CMOS input level Pin input at selecting of AUTOMOTIVE input level Parameter “L” level input voltage VILS *2 Vss − 0.3 0.2 Vcc V Hysteresis input ⎯ VILM RST, MOD ⎯ Smoothing capacitor Operating temperature CS TA ⎯ ⎯ ⎯ ⎯ Vss − 0.3 Vss − 0.3 0.1 − 40 +5 0.3 Vcc 0.2 Vcc 1.0 + 85 + 35 V V µF CMOS input (Flash memory product) Hysteresis input (MASK ROM product) *4 °C Other than MB95FV100D-103 °C MB95FV100D-103 *1 : The value is 2.9 V when the low voltage detection reset is used. *2 : P10, P50, P51, and P67 can switch the input level to either the “CMOS input level” or “hysteresis input level”. The switching of the input level can be set by the input level selection register (ILSR). *3 : Single clock products only *4 : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC pin must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the diagram below. • C pin connection diagram C CS 32 MB95110M Series WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 33 MB95110M Series 3. DC Characteristics Parameter “H” level output voltage Symbol Pin name (Vcc = AVcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Value Conditions Unit Remarks Min Typ Max IOH = − 4.0 mA IOH = − 8.0 mA IOL = 4.0 mA IOL = 12 mA ⎯ VCC − 0.5 VCC − 0.5 ⎯ ⎯ Vss − 0.3 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.4 0.4 Vss + 5.5 V V V V V “L” level output voltage Open-drain output application voltage Input leakage current (Hi-Z output leakage current) Open-drain output leakage current Pull-up resistor Pull-down resistor Output pin VOH1 other than P00 to P07 VOH2 P00 to P07 Output pin VOL1 other than P00 to P07 VOL2 P00 to P07 VD P50, P51 ILI Port other 0.0 V < VI < Vcc than P50, P51 0.0 V < VI < Vss + 5.5 V −5 ⎯ +5 µA When the pull-up prohibition setting ILIOD P50, P51 ⎯ ⎯ 5 µA RPULL P10 to P15, P20 to P24, VI = 0.0 V P30 to P37, 1, PG2*1 PG1* VI = Vcc 25 50 100 kΩ kΩ When the pull-up permission setting MASK ROM product Flash memory product (at other than Flash memory writing and erasing) Flash memory product (at Flash memory writing and erasing) MASK ROM product Flash memory product (at other than Flash memory writing and erasing) Flash memory product (at Flash memory writing and erasing) MASK ROM product (Continued) RMOD MOD 25 50 100 ⎯ VCC = 5.5 V FCH = 20 MHz FMP = 10 MHz Main clock mode (divided by 2) Vcc (External clock operation) VCC = 5.5 V FCH = 32 MHz FMP = 16 MHz Main clock mode (divided by 2) 9.5 12.5 mA ⎯ ⎯ 30 35 mA Power supply current*2 7.2 9.5 mA ICC ⎯ 15.2 20.0 mA ⎯ ⎯ 35.7 42.5 mA 11.6 15.2 mA 34 MB95110M Series (Vcc = AVcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Symbol Pin name Conditions VCC = 5.5 V FCH = 20 MHz FMP = 10 MHz Main sleep mode (divided by 2) VCC = 5.5 V FCH = 32 MHz FMP = 16 MHz Main sleep mode (divided by 2) VCC = 5.5 V FCL = 32 kHz FMPL = 16 kHz Sub clock mode (divided by 2) , TA = + 25 °C VCC = 5.5 V FCL = 32 kHz FMPL = 16 kHz Sub sleep mode (divided by 2) , TA = + 25 °C VCC = 5.5 V FCL = 32 kHz Watch mode Main stop mode TA = + 25 °C VCC = 5.5 V FCH = 4 MHz FMP = 10 MHz Main PLL mode (multiplied by 2.5) VCC = 5.5 V FCH = 6.4 MHz FMP = 16 MHz Main PLL mode (multiplied by 2.5) Value Min Typ Max Unit Remarks ⎯ 4.5 7.5 mA ICCS ⎯ 7.2 12.0 mA ICCL ⎯ 45 100 µA Power supply current*2 ICCLS VCC (External clock operation) *2 ⎯ 10 81 µA ICCT ⎯ 4.6 27 µA ⎯ 9.3 12.5 mA Flash memory product MASK ROM product Flash memory product MASK ROM product (Continued) ⎯ 7.0 9.5 mA ICCMPLL ⎯ 14.9 20.0 mA ⎯ 11.2 15.2 mA 35 MB95110M Series (Continued) Symbol (Vcc = AVcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Pin name Conditions VCC = 5.5 V FCL = 32 kHz FMPL = 128 kHz Sub PLL mode (multiplied by 4) TA = + 25 °C VCC (External clock operation) *2 VCC = 5.5 V FCH = 10 MHz Timebase timer mode TA = + 25 °C VCC = 5.5 V FCH = 16 MHz Timebase timer mode TA = + 25 °C VCC = 5.5 V Sub stop mode TA = + 25 °C VCC Current consumption for low voltage detection circuit only VCC = 5.5 V FCH = 16 MHz At operating of A/D conversion AVcc IAH VCC = 5.5 V FCH = 16 MHz At stopping A/D conversion TA = + 25 °C Value Min Typ Max Unit Remarks Parameter ICCSPLL ⎯ 160 400 µA ⎯ 0.15 1.10 mA ICTS ⎯ 0.24 1.76 mA Power supply current*2 ICCH ⎯ 5 20 µA Main stop mode for single clock product ILVD ⎯ 38 50 µA IA ⎯ 2.4 4.7 mA ⎯ 1 5 µA Input capacitance CIN Other than AVcc, f = 1 MHz AVss, Vcc, Vss ⎯ 5 15 pF *1 : Single clock product only *2 : • The power-supply current is determined by the external clock. When both low voltage detection option is selected, the power-supply current will be a value of adding current consumption of the low voltage detection circuit (ILVD) to the specified value. • Refer to “4. AC Characteristics (1) Clock Timing” for FCH and FCL. • Refer to “4. AC Characteristics (2) Source Clock/Machine Clock” for FMP and FMPL. 36 MB95110M Series 4. AC Characteristics (1) Clock Timing (Vcc = 2.5 V to 5.5 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter SymCondiPin name bol tions Value Min 1.00 1.00 FCH Clock frequency X0, X1 3.00 3.00 3.00 ⎯ FCL X0A, X1A ⎯ ⎯ tHCYL Clock cycle time tLCYL tWH1 tWL1 tWH2 tWL2 tCR tCF X0A, X1A X0 X0A X0, X0A X0, X1 61.5 30.8 ⎯ 61.5 ⎯ ⎯ 32.768 ⎯ ⎯ 30.5 ⎯ 15.2 ⎯ ⎯ 1000 1000 ⎯ ⎯ ⎯ 5 kHz ns ns µs ns µs ns Typ ⎯ ⎯ ⎯ ⎯ ⎯ 32.768 Max 16.25 32.50 16.25 8.13 6.50 ⎯ Unit MHz Remarks When using main oscillation circuit MHz When using external clock MHz Main PLL multiplied by 1 MHz Main PLL multiplied by 2 MHz Main PLL multiplied by 2.5 kHz When using sub oscillation circuit When using sub PLL VCC = 2.3 V to 3.6 V When using main oscillation circuit When using external clock When using sub oscillation circuit When using external clock Duty ratio is about 30% to 70%. When using external clock Input clock pulse width Input clock rise time and fall time 37 MB95110M Series tHCYL tWH1 tCR tCF 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC tWL1 X0 • Figure of main clock input port external connection When using a crystal or ceramic oscillator Microcontroller X0 X1 FCH When using external clock Microcontroller X0 X1 Open FCH tLCYL tWH2 tCR tCF 0.8 VCC 0.8 VCC 0.1 VCC 0.1 VCC 0.1 VCC tWL2 X0A • Figure of sub clock input port external connection When using a crystal or ceramic oscillator Microcontroller X0A X1A FCL When using external clock Microcontroller X0A X1A Open FCL 38 MB95110M Series (2) Source Clock/Machine Clock (Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Sym- Pin bol name Value Min 61.5 tSCLK ⎯ 7.6 FSP FSPL ⎯ ⎯ 0.50 16.384 61.5 tMCLK ⎯ 7.6 FMP FMPL ⎯ 0.031 1.024 ⎯ ⎯ ⎯ 976.5 ⎯ ⎯ ⎯ ⎯ 61.0 16.25 Typ ⎯ Max 2000 Unit Remarks Source clock cycle time*1 (Clock before setting division) When using main clock ns Min : FCH = 16.25 MHz, PLL multiplied by 1 Max : FCH = 1 MHz, divided by 2 When using sub clock µs Min : FCL = 32 kHz, PLL multiplied by 4 Max : FCL = 32 kHz, divided by 2 MHz When using main clock When using main clock ns Min : FSP = 16.25 MHz, no division Max : FSP = 0.5 MHz, divided by 16 When using sub clock µs Min : FSPL = 131 kHz, no division Max : FSPL = 16 kHz, divided by 16 Source clock frequency 131.072 kHz When using sub clock 32000 Machine clock cycle time*2 (Minimum instruction execution time) Machine clock frequency 16.250 MHz When using main clock 131.072 kHz When using sub clock *1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes the machine clock. Further, the source clock can be selected as follows. • Main clock divided by 2 • PLL multiplication of main clock (select from 1, 2, 2.5 multiplication) • Sub clock divided by 2 • PLL multiplication of sub clock (select from 2, 3, 4 multiplication) *2 : Operation clock of the microcontroller. Machine clock can be selected as follows. • Source clock (no division) • Source clock divided by 4 • Source clock divided by 8 • Source clock divided by 16 • Outline of clock generation block FCH (main oscillation) Devided by 2 Main PLL ×1 ×2 × 2.5 SCLK ( source clock ) FCL (sub oscillation) Devided by 2 Clock mode select bit ( SYCC : SCS1, SCS0 ) Division circuit ×1 × 1/4 × 1/8 × 1/16 MCLK ( machine clock ) Sub PLL ×2 ×3 ×4 39 MB95110M Series • Operating voltage − Operating frequency (TA = − 40 °C to + 85 °C) • MB95F114MS/F114NS/F116MS/F116NS/F118MS/F118NS/F114MW/F114NW/F116MW/F116NW/F118MW/F118 NW Sub PLL operating guarantee range Sub clock mode, watch mode, operating guarantee range Main clock mode, main PLL mode, operating guarantee range Operating voltage (V) Operating voltage (V) 5.5 5.5 3.5 2.45 16.384 kHz 32 kHz 131.072 kHz 2.45 0.5 MHz 3 MHz 10 MHz 16.25 MHz PLL operating guarantee range PLL operating guarantee range Main clock operating guarantee range Source clock frequency (FSPL) Source clock frequency (FSP) • Operating voltage − Operating frequency (TA = + 5 °C to + 35 °C) • MB95FV100D-103 Sub PLL, sub clock mode and watch mode operation guarantee range 5.5 5.5 Main clock mode and main PLL mode operation guarantee range Operating voltage (V) Operating voltage (V) 3.5 2.7 2.7 16.384 kHz 32 kHz 131.072 kHz 0.5MHz 3 MHz 10 MHz 16.25 MHz PLL operation guarantee range PLL operation guarantee range Main clock operation guarantee range Source clock frequency (FSPL) • Main PLL operation frequency 10 MHz 9 MHz Source clock frequency (FSP) × 2.5 ×2 ×1 Source clock frequency (FSP) 8 MHz 7.5 MHz 7 MHz 6 MHz 5 MHz 4 MHz 3 MHz 3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz 9 MHz 10 MHz Main clock frequency (FMP) 40 MB95110M Series (3) External Reset (Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Symbol Value Min 2 tMCLK*1 RST “L” level pulse width tRSTL Oscillation time of oscillator*2 + 100 100 *1 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. *2 : Oscillation start time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of µs and several ms. In the external clock, the oscillation time is 0 ms. • At normal operating Max ⎯ ⎯ ⎯ Unit ns µs µs Remarks At normal operating At stop mode, sub clock mode, sub sleep mode, and watch mode At timebase timer mode tRSTL RST 0.2 VCC 0.2 VCC • At stop mode, sub clock mode, sub sleep mode, and watch mode, and power-on tRSTL 0.2 VCC 0.2 VCC RST 90% of amplitude X0 Internal operating clock Oscillation time Oscillation stabilization wait time of oscillator Execute instruction Internal reset 100 µs 41 MB95110M Series (4) Power-on Reset (AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Power supply rising time Power supply cutoff time Symbol tR tOFF Conditions ⎯ ⎯ Value Min ⎯ 1 Max 50 ⎯ Unit ms ms Waiting time until power-on Remarks tR 2.5 V tOFF VCC 0.2 V 0.2 V 0.2 V Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power supply voltages during operation, set the slope of rising within 30 mV/ms as shown below. VCC 2.3 V Limiting the slope of rising within 30 mV/ms is recommended. Hold condition in STOP mode VSS 42 MB95110M Series (5) Peripheral Input Timing (Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Peripheral input “H” pulse width Peripheral input “L” pulse width Symbol tILIH tIHIL Pin name Value Min 2 tMCLK* 2 tMCLK* Max ⎯ ⎯ Unit ns ns Remarks INT00 to INT07, EC0, EC1, TRG0/ADTG * : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. tILIH tIHIL INT00 to INT07, EC0, EC1, TRG0/ADTG 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 43 MB95110M Series (6) UART/SIO, Serial I/O Timing (Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Serial clock cycle time UCK ↓ → UO time Valid UI → UCK ↑ UCK ↑ → valid UI hold time Serial clock “H” pulse width Serial clock “L” pulse width UCK ↓ → UO time Valid UI → UCK ↑ UCK ↑ → valid UI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name UCK0 UCK0, UO0 UCK0, UI0 UCK0, UI0 UCK0 UCK0 UCK0, UO0 UCK0, UI0 UCK0, UI0 Conditions Internal clock operation Output pin: CL = 80 pF + 1TTL. External clock operation Output pin: CL = 80 pF + 1TTL. Value Min 4 tMCLK* − 190 2 tMCLK* 2 tMCLK* 4 tMCLK* 4 tMCLK* ⎯ 2 tMCLK* 2 tMCLK* Max ⎯ + 190 ⎯ ⎯ ⎯ ⎯ 190 ⎯ ⎯ Unit ns ns ns ns ns ns ns ns ns Remarks * : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. • Internal shift clock mode tSCYC UCK0 2.4 V 0.8 V tSLOV 0.8 V UO0 2.4 V 0.8 V tIVSH tSHIX UI0 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSLSH tSHSL 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tSLOV UCK0 UO0 2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC UI0 0.8 VCC 0.2 VCC 44 MB95110M Series (7) LIN-UART Timing Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2 (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0) (Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C) Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time Serial clock “L” pulse width Serial clock “H” pulse width SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time SCK fall time SCK rise time SymPin name bol tSCYC tSLOVI tIVSHI tSHIXI tSLSH tSHSL tIVSHE tSHIXE tF tR SCK Conditions Value Min 5 tMCLK*3 Max ⎯ + 95 ⎯ ⎯ ⎯ ⎯ 2 tMCLK*3 + 95 ⎯ ⎯ 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns Internal clock SCK, SOT −95 operation output pin : SCK, SIN CL = 80 pF + 1 TTL. tMCLK*3 + 190 SCK, SIN 0 SCK SCK SCK, SIN SCK, SIN SCK SCK External clock operation output pin : CL = 80 pF + 1 TTL. 3t t MCLK 3 * − tR MCLK 3 * + 95 tSLOVE SCK, SOT ⎯ 190 t MCLK 3 * + 95 ⎯ ⎯ *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. 45 MB95110M Series • Internal shift clock mode tSCYC 2.4 V 0.8 V tSLOVI 2.4 V 0.8 V tIVSHI tSHIXI 0.8 V SCK SOT SIN 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSLSH tSHSL 0.8 VCC 0.2 VCC tF tSLOVE 2.4 V 0.8 V tIVSHE tSHIXE 0.2 VCC tR 0.8 VCC SCK 0.8 VCC SOT SIN 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 46 MB95110M Series Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2 (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0) (Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C) Parameter Serial clock cycle time SCK ↑ → SOT delay time Valid SIN → SCK ↓ SCK ↓ → valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↑ → SOT delay time Valid SIN → SCK ↓ SCK ↓ → valid SIN hold time SCK fall time SCK rise time Symbol tSCYC tSHOVI tIVSLI tSLIXI tSHSL tSLSH tSHOVE tIVSLE tSLIXE tF tR Pin name SCK Internal clock SCK, SOT operation output pin : SCK, SIN CL = 80 pF + 1 TTL. SCK, SIN SCK SCK SCK, SOT SCK, SIN SCK, SIN SCK SCK External clock operation output pin : CL = 80 pF + 1 TTL. t Conditions Value Min 5 tMCLK*3 −95 MCLK 3 Max ⎯ + 95 ⎯ ⎯ ⎯ ⎯ 2t MCLK 3 Unit ns ns ns ns ns ns ns ns ns ns ns * + 190 0 3 tMCLK*3 − tR t MCLK 3 * + 95 ⎯ 190 tMCLK*3 + 95 ⎯ ⎯ * + 95 ⎯ ⎯ 10 10 *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. 47 MB95110M Series • Internal shift clock mode tSCYC SCK 2.4 V 0.8 V tSHOVI 2.4 V 0.8 V tIVSLI tSLIXI 2.4 V SOT SIN 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSHSL tSLSH 0.8 VCC 0.2 VCC tSHOVE 2.4 V 0.8 V tIVSLE tSLIXE tF 0.2 VCC SCK 0.2 VCC tR 0.8 VCC SOT SIN 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 48 MB95110M Series Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2 (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1) (Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C) Parameter Serial clock cycle time SCK ↑ → SOT delay time Valid SIN → SCK ↓ SCK ↓ → valid SIN hold time SOT → SCK ↓ delay time Symbol tSCYC tSHOVI tIVSLI tSLIXI tSOVLI Pin name SCK SCK, SOT SCK, SIN SCK, SIN SCK, SOT Internal clock operation output pin : CL = 80 pF + 1 TTL. t Conditions Value Min 5 tMCLK*3 −95 MCLK 3 Max ⎯ + 95 ⎯ ⎯ 4 tMCLK*3 Unit ns ns ns ns ns * + 190 0 ⎯ *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. tSCYC SCK 0.8 V tSOVLI 2.4 V 0.8 V tIVSLI tSLIXI 2.4 V tSHOVI 2.4 V 0.8 V 0.8 V SOT SIN 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC 49 MB95110M Series Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2 (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1) (Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C) Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time SOT → SCK ↑ delay time Symbol tSCYC tSLOVI tIVSHI tSHIXI tSOVHI Pin name SCK SCK, SOT Internal clock SCK, SIN operating output pin : CL = 80 pF + 1 TTL. SCK, SIN t Conditions Value Min 5 tMCLK*3 −95 MCLK 3 Max ⎯ + 95 ⎯ ⎯ 4 tMCLK*3 Unit ns ns ns ns ns * + 190 0 ⎯ SCK, SOT *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. tSCYC SCK tSOVHI 2.4 V 0.8 V tSLOVI 2.4 V 0.8 V tIVSHI tSHIXI 0.8 VCC 0.2 VCC 2.4 V 0.8 V 2.4 V SOT SIN 0.8 VCC 0.2 VCC 50 MB95110M Series (8) I2C Timing (Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Value Parameter Symbol Pin name SCL0 SCL0 SDA0 SCL0 SCL0 SCL0 SDA0 R = 1.7 kΩ, SCL0 C = 50 pF*1 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 Conditions Standardmode Min SCL clock frequency (Repeat) Start condition hold time SDA ↓ → SCL ↓ SCL clock “L” width SCL clock “H” width (Repeat) Start condition setup time SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓ ↑ Data setup time SDA ↓ ↑ → SCL ↑ Stop condition setup time SCL ↑ → SDA ↑ Bus free time between stop condition and start condition fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF 0 4.0 4.7 4.0 4.7 0 0.25 4 4.7 Max 100 ⎯ ⎯ ⎯ ⎯ 3.45*2 ⎯ ⎯ ⎯ Fast-mode Unit Remarks Min 0 0.6 1.3 0.6 0.6 0 0.1 0.6 1.3 Max 400 ⎯ ⎯ ⎯ ⎯ 0.9*3 ⎯ ⎯ ⎯ kHz µs µs µs µs µs µs µs µs *1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : The maximum tHD;DAT have only to be met if the device dose not stretch the “L” width (tLOW) of the SCL signal. *3 : A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. tWAKEUP SDA0 tLOW SCL0 tHD;STA tSU;DAT tSU;STA tSU;STO tHD;DAT tHIGH tHD;STA tBUF 51 MB95110M Series (Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C) Parameter SCL clock “L” width SCL clock “H” width Sym- Pin Condition bol name tLOW tHIGH SCL0 SCL0 Value*2 Min (2 + nm / 2) tMCLK − 20 (nm / 2) tMCLK − 20 Max ⎯ (nm / 2 ) tMCLK + 20 Unit ns ns Remarks Master mode Master mode Master mode Maximum value is applied when m, n = 1, 8. Otherwise, the minimum value is applied. Master mode Master mode Start condition hold time tHD;STA SCL0 SDA0 (−1 + nm / 2) tMCLK − 20 (−1 + nm) tMCLK + 20 ns Stop condition setup time Start condition setup time Bus free time between stop condition and start condition Data hold time tSU;STO tSU;STA SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 (1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20 (1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20 ns ns tBUF (2 nm + 4) tMCLK − 20 ⎯ ns tHD;DAT 3 tMCLK − 20 ⎯ ns Master mode Master mode When assuming that “L” of SCL is not extended, the minimum value is applied to first bit of continuous data. Otherwise, the maximum value is applied. Minimum value is applied to interrupt at 9th SCL↓. Maximum value is applied to interrupt at 8th SCL↓. At reception At reception Undetected when 1 tMCLK is used at reception Undetected when 1 tMCLK is used at reception Undetected when 1 tMCLK is used at reception At reception At slave transmission mode At slave transmission mode Data setup time tSU;DAT SCL0 SDA0 (−2 + nm / 2) tMCLK − 20 (−1 + nm / 2) tMCLK + 20 ns R = 1.7 kΩ, C = 50 pF*1 Setup time between clearing interrupt and tSU;INT SCL0 SCL rising (nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20 ns SCL clock “L” width SCL clock “H” width Start condition detection Stop condition detection Restart condition detection condition Bus free time Data hold time Data setup time tLOW tHIGH tHD;STA tSU;STO tSU;STA tBUF tHD;DAT tSU;DAT SCL0 SCL0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 4 tMCLK − 20 4 tMCLK − 20 2 tMCLK − 20 2 tMCLK − 20 2 tMCLK − 20 2 tMCLK − 20 2 tMCLK − 20 tLOW − 3 tMCLK − 20 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ns ns ns ns ns ns ns ns (Continued) 52 MB95110M Series (Continued) (Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C) Sym- Pin Condition bol name tHD;DAT tSU;DAT SCL0 SDA0 SCL0 R = 1.7 kΩ, SDA0 C = 50 pF*1 SCL0 SDA0 Value*2 Min 0 tMCLK − 20 Oscillation stabilization wait time + 2 tMCLK − 20 Max ⎯ ⎯ ⎯ Unit ns ns Remarks At reception At reception Parameter Data hold time Data setup time SDA↓→SCL↑ (at wake-up function) tWAKEUP ns *1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : • Refer to “ (2) Source Clock/Machine Clock” for tMCLK. • m is CS4 bit and CS3 bit (bit 4 and bit 3) of clock control register (ICCR0) . • n is CS2 bit to CS0 bit (bit 2 to bit 0) of clock control register (ICCR0) . • Actual timing of I2C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of ICCR0 register. • Standard-mode : m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz. Setting of m and n limits the machine clock that can be used below. (m, n) = (1, 8) : 0.9 MHz < tMCLK ≤ 1 MHz (m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz (m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz (m, n) = (1, 98) : 0.9 MHz < tMCLK ≤ 10 MHz • Fast-mode : m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz. Setting of m and n limits the machine clock that can be used below. (m, n) = (1, 8) : 3.3 MHz < tMCLK ≤ 4 MHz (m, n) = (1, 22) , (5, 4) : 3.3 MHz < tMCLK ≤ 8 MHz (m, n) = (6, 4) : 3.3 MHz < tMCLK ≤ 10 MHz 53 MB95110M Series (9) Low Voltage Detection (AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C) Parameter Release voltage Detection voltage Hysteresis width Power-supply start voltage Power-supply end voltage Power-supply voltage change time (at power supply rise) Symbol VDL+ VDLVHYS Voff Von Value Min 2.55 2.45 70 ⎯ 4.9 0.3 tr ⎯ 300 tf ⎯ td1 td2 ILVD ⎯ ⎯ ⎯ 300 ⎯ ⎯ 38 ⎯ 400 30 50 µs µs µs µA Current consumption for low voltage detection circuit only 3000 ⎯ ⎯ ⎯ µs µs Typ 2.70 2.60 100 ⎯ ⎯ ⎯ Max 2.85 2.75 ⎯ 2.3 ⎯ ⎯ Unit V V mV V V µs Slope of power supply that reset release signal generates Slope of power supply that reset release signal generates within rating (VDL+) Slope of power supply that reset detection signal generates Slope of power supply that reset detection signal generates within rating (VDL-) Remarks At power-supply rise At power-supply fall Power-supply voltage change time (at power supply fall) Reset release delay time Reset detection delay time Current consumption VCC Von Voff time VCC tf tr VDL+ VDL- VHYS Internal reset signal td2 td1 54 MB95110M Series 5. A/D Converter (1) A/D Converter Electrical Characteristics (AVcc = Vcc = 4.0 V to 5.5 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Resolution Total error Linearity error Differential linear error Zero transition voltage Full-scale transition voltage Compare time VOT VFST ⎯ ⎯ Symbol Value Min ⎯ − 3.0 − 2.5 − 1.9 Typ ⎯ ⎯ ⎯ ⎯ Max 10 + 3.0 + 2.5 + 1.9 Unit bit LSB LSB LSB V V µs µs µs 4.5 V ≤ AVcc ≤ 5.5 V 4.0 V ≤ AVcc < 4.5 V 4.5 V ≤ AVcc ≤ 5.5 V, At external impedance < 5.4 kΩ 4.0 V ≤ AVcc < 4.5 V, At external impedance < 2.4 kΩ Remarks AVss − 1.5 LSB AVss + 0.5 LSB AVss + 2.5 LSB AVcc − 3.5 LSB AVcc − 1.5 LSB AVcc + 0.5 LSB 0.9 1.8 0.6 ⎯ ⎯ ⎯ 16500 16500 ∞ Sampling time ⎯ 1.2 ⎯ ⎯ ⎯ ⎯ 600 ⎯ ∞ + 0.3 AVcc AVcc 900 5 µs µA V V µA µA Analog input current Analog input voltage Reference voltage Reference voltage supply current IAIN VAIN ⎯ IR IRH −0.3 AVss AVss + 4.0 ⎯ ⎯ AVcc pin AVcc pin, During A/D operation AVcc pin, At stop mode 55 MB95110M Series (2) Notes on Using A/D Converter • About the external impedance of analog input and its sampling time A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/ D conversion precision, Therefore, to satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. • Analog input equivalent circuit R Analog input C Comparator During sampling : ON 4.5 V ≤ AVcc ≤ 5.5 V 4.0 V ≤ AVcc < 4.5 V Note : The values are reference values. R 2.0 kΩ (Max) 8.2 kΩ (Max) C 16 pF (Max) 16 pF (Max) • The relationship between external impedance and minimum sampling time (External impedance = 0 kΩ to 100 kΩ) 100 90 80 70 60 50 40 30 20 10 0 0 2 4 (External impedance = 0 kΩ to 20 kΩ) 20 18 16 14 12 10 8 6 4 2 0 0 External impedance [kΩ] External impedance [kΩ] AVCC ≥ 4.5 V AVCC ≥ 4.5 V AVCC ≥ 4.0 V AVCC ≥ 4.0 V 6 8 10 12 14 1 2 3 4 Minimum sampling time [µs] Minimum sampling time [µs] • About errors As |AVCC − AVSS| becomes smaller, values of relative errors grow larger. 56 MB95110M Series (3) Definition of A/D Converter Terms • Resolution The level of analog variation that can be distinguished by the A/D converter. When the number of bits is 10, analog voltage can be divided into 210 = 1024. • Linearity error (unit : LSB) The deviation between the value along a straight line connecting the zero transition point (“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point (“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained. • Differential linear error (Unit : LSB) Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. • Total error (unit: LSB) Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error, linearity error, quantum error, and noise. Ideal I/O characteristics VFST Total error 3FFH 3FEH 3FFH 3FEH 1.5 LSB Actual conversion characteristic {1 LSB × (N − 1) + 0.5 LSB} Digital output Digital output 3FDH 3FDH 004H 003H 002H 001H 0.5 LSB AVSS AVCC VOT 1 LSB 004H 003H 002H 001H AVSS AVCC VNT Actual conversion characteristic Ideal characteristics Analog input 1 LSB = AVcc − AVss 1024 (V) Analog input Total error of VNT − {1 LSB × (N − 1) + 0.5 LSB} = [LSB] digital output N 1 LSB N : A/D converter digital output value VNT : A voltage at which digital output transits from (N − 1) to N. (Continued) 57 MB95110M Series (Continued) Zero transition error 004H Actual conversion characteristic Full-scale transition error Ideal characteristics 3FFH Digital output 003H Ideal characteristics Digital output Actual conversion characteristic 3FEH VFST 002H Actual conversion characteristic 3FDH (measurement value) 001H VOT (measurement value) Actual conversion characteristic 3FCH AVSS AVCC AVSS AVCC Analog input Analog input Linearity error 3FFH 3FEH Actual conversion characteristic Differential linear error Ideal characteristics N+1 {1 LSB × N + VOT} VFST (measurement value) Digital output Digital output 3FDH Actual conversion characteristic V (N+1)T N VNT 004H 003H 002H 001H AVSS Actual conversion characteristic Ideal characteristics N-1 VNT Actual conversion characteristic N-2 VOT (measurement value) Analog input AVCC AVSS Analog input AVCC Linearity error in = VNT − {1 LSB × N + VOT} 1 LSB digital output N Differential linear error = in digital output N V (N + 1) T − VNT 1 LSB −1 N : A/D converter digital output value VNT : A voltage at which digital output transits from (N − 1) to N. VOT (Ideal value) = AVSS + 0.5 LSB [V] VFST (Ideal value) = AVCC − 1.5 LSB [V] 58 MB95110M Series 6. Flash Memory Program/Erase Characteristics Parameter Sector erase time (4 Kbytes sector) Sector erase time (16 Kbytes sector) Byte programming time Program/erase cycle Power supply voltage at program/erase Flash memory data retention time Value Min ⎯ ⎯ ⎯ 10000 4.5 20*3 Typ 0.2*1 0.5*1 32 ⎯ ⎯ ⎯ Max 0.5*2 7.5*2 3600 ⎯ 5.5 ⎯ Unit s s µs cycle V year Average TA = +85 °C Remarks Excludes 00H programming prior erasure. Excludes 00H programming prior erasure. Excludes system-level overhead. *1 : TA = + 25 °C, VCC = 5.0 V, 10000 cycles *2 : TA = + 85 °C, VCC = 4.5 V, 10000 cycles *3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at +85 °C) . 59 MB95110M Series ■ MASK OPTION Part number No. Specifying procedure Clock mode select • Single-system clock mode • Dual-system clock mode Low voltage detection reset* • With low voltage detection reset • Without low voltage detection reset Oscillation stabilization wait time MB95F114MS/F114NS MB95F114MW/F114NW MB95117M MB95F116MS/F116NS MB95F116MW/F116NW MB95F118MS/F118NS MB95F118MW/F118NW Setting disabled Specify when ordering MASK Setting disabled Setting disabled MB95FV100D-103 Setting disabled 1 Single-system clock mode Dual-system clock mode Changing by the switch on MCU board 2 Specify when ordering MASK Specified by part number Specified by part number Changing by the switch on MCU board 3 Fixed to oscillation Fixed to oscillation stabilization stabilization wait time of wait time of (214−2) /FCH (214−2) /FCH Fixed to oscillation stabilization wait time of (214−2) /FCH Fixed to oscillation stabilization wait time of (214−2) /FCH * : Refer to table below about clock mode select, low voltage detection reset and reset output. 60 MB95110M Series Part number Clock mode select Single-system Low voltage detection reset No Yes No Yes No Yes No Yes No Yes No Yes No Yes No Yes No MB95117M Dual-system MB95F114MS MB95F114NS MB95F116MS MB95F116NS MB95F118MS MB95F118NS MB95F114MW MB95F114NW MB95F116MW MB95F116NW MB95F118MW MB95F118NW Single-system MB95FV100D-103 Dual-system Dual-system Single-system Yes Yes No Yes Yes 61 MB95110M Series ■ ORDERING INFORMATION Part number MB95117MPMC MB95F114MSPMC MB95F114NSPMC MB95F116MSPMC MB95F116NSPMC MB95F118MSPMC MB95F118NSPMC MB95F114MWPMC MB95F114NWPMC MB95F116MWPMC MB95F116NWPMC MB95F118MWPMC MB95F118NWPMC MB2146-303A (MB95FV100D-103PBT) Package Remarks 52-pin plastic LQFP (FPT-52P-M01) ( MCU board 224-pin plastic PFBGA (BGA-224P-M08) ) 62 MB95110M Series ■ PACKAGE DIMENSION 52-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Code (Reference) 0.65 mm 10.0 × 10.0 mm Gullwing Plastic mold 1.70 mm Max P-LQFP52-10×10-0.65 (FPT-52P-M01) 52-pin plastic LQFP (FPT-52P-M01) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 12.00±0.20(.472±.008)SQ * 10.00±0.10(.394±.004)SQ 39 27 0.145±0.055 (.006±.002) 40 26 Details of "A" part 0.10(.004) 1.50 –0.10 .059 –.004 +0.20 +.008 (Mounting height) INDEX 0˚~8˚ 52 14 0.10±0.10 (.004±.004) (Stand off) "A" 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) LEAD No. 1 13 0.65(.026) 0.30 .012 +0.065 –0.035 +.0027 –.0014 0.13(.005) M C 2005 FUJITSU LIMITED F52001S-c-1-1 Dimensions in mm (inches). Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 63 MB95110M Series The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html FUJITSU LIMITED All Rights Reserved. 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Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Edited Business Promotion Dept. F0608