MB95F128DPF

FUJITSU SEMICONDUCTOR DATA SHEET DS07-12616-1E 8-bit Proprietary Microcontrollers CMOS F2MC-8FX MB95120 series MB95F128D/F128E/FV100D-101/FV100D-102 ■ DESCRIPTION The MB95120 series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions. Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller. ■ FEATURE • F2MC-8FX CPU core Instruction set optimized for controllers • Multiplication and division instructions • 16-bit arithmetic operations • Bit test branch instruction • Bit manipulation instructions etc. • Clock • Main clock • Main PLL clock • Sub clock • Sub PLL clock • Timer • 8/16-bit compound timer × 2 channels • 16-bit reload timer • 8/16-bit PPG × 2 channels • 16-bit PPG × 2 channels • Timebase timer • Watch prescaler (Continued) Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development. Copyright©2007 FUJITSU LIMITED All rights reserved MB95120 Series (Continued) • LIN-UART • Full duplex double buffer • Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable • UART/SIO • Full duplex double buffer • Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable • I2C* • Built-in wake-up function • External interrupt • Interrupt by edge detection (rising, falling, or both edges can be selected) • Can be used to recover from low-power consumption (standby) modes. • 8/10-bit A/D converter • 8-bit or 10-bit resolution can be selected • LCD controller (LCDC) • 40 SEG × 4 COM (Max 160 pixels) • With blinking function • Built-in division resistance for LCD drive/booster : selected by mask option • Low-power consumption (standby) mode • Stop mode • Sleep mode • Watch mode • Timebase timer mode • I/O port • The number of maximum ports : Max 87 • Port configuration • General-purpose I/O ports (N-ch open drain) : 2 ports • General-purpose I/O ports (CMOS) : 85 ports • Programmable input voltage levels of port • CMOS input level / hysteresis input level • Dual operation Flash memory • Erase/write and read can be executed in the different bank (Upper Bank/Lower Bank) at the same time. • Flash memory security function Protects the content of Flash memory (Flash memory product only) *: Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. 2 MB95120 Series ■ PRODUCT LINEUP Part number*1 MB95F128D Parameter Type ROM capacity RAM capacity Reset output Option*2 Clock system Low voltage detection reset Flash memory product 60 Kbytes 2 Kbytes No Dual clock No Number of basic instructions : 136 Instruction bit length : 8 bits Instruction length : 1 to 3 bytes Data bit length : 1, 8, and 16 bits Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 MHz) Interrupt processing time : 0.6 µs (at machine clock frequency 16.25 MHz) General-purpose I/O port (N-ch open drain) General-purpose I/O port (CMOS) Programmable input voltage levels of port CMOS input level / hysteresis input level Reset generated cycle At main oscillation clock 10 MHz At sub oscillation clock 32.768 kHz Capable of replacing 3 bytes of ROM data Master/slave sending and receiving Bus error function and arbitration function Detecting transmitting direction function Start condition repeated generation and detection functions Built-in wake-up function Data transfer capable in UART/SIO Full duplex double buffer Variable data length (5/6/7/8-bit), built-in baud rate generator NRZ type transfer format, error detected function LSB-first or MSB-first can be selected Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable Dedicated reload timer allowing a wide range of communication speeds to be set Full duplex double buffer Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable LIN functions available as the LIN master or LIN slave : 2 ports : 85 ports MB95F128E CPU functions Ports (Max 87 ports) Timebase timer Watchdog timer Wild register Peripheral functions Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz) : Min 105 ms : Min 250 ms I2C UART/SIO LIN-UART 8/10-bit A/D converter 8-bit or 10-bit resolution can be selected (12 channels) (Continued) 3 MB95120 Series (Continued) Part number*1 MB95F128D Parameter COM output : 4 (Max) SEG output : 40 (Max) LCD drive power supply (bias) pin :4 40 SEG × 4 COM : 160 pixels can be displayed Duty LCD mode With blinking function Division resistance for LCD drive/booster : selected by mask option Built-in internal division resistance : selected by mask option 16-bit reload timer Peripheral functions Built-in booster circuit : selected by mask option MB95F128E LCD controller (LCDC) Two clock modes and two counter operating modes can be selected Square wave form output Count clock : 7 internal clocks and external clock can be selected Counter operating mode : reload mode or one-shot mode can be selected Each channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit timer × 1 channel” 8/16-bit compound Built-in timer function, PWC function, PWM function, capture function and square timer (2 channels) wave form output Count clock : 7 internal clocks and external clock can be selected 16-bit PPG (2 channels) 8/16-bit PPG (2 channels) Watch counter Watch prescaler External interrupt (12 channels) PWM mode or one-shot mode can be selected Counter operating clock : Eight selectable clock sources Support for external trigger start Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG × 1 channel” Counter operating clock : Eight selectable clock sources Count clock : Four selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s) Counter value can be set from 0 to 63 (Capable of counting for 1 minute when selecting clock source 1 second and setting counter value to 60) 4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s) Interrupt by edge detection (rising, falling, or both edges can be selected) Can be used to recover from standby modes Supports automatic programming, Embedded AlgorithmTM *3 Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of write/erase cycles (Minimum) : 10000 times Data retention time : 20 years Erase can be performed on each block Block protection with external programming voltage Dual operation Flash memory Flash Security Feature for protecting the content of the Flash Sleep, stop, watch, and timebase timer Flash memory Standby mode *1 : MASK ROM products are currently under consideration. *2 : For details of option, refer to “■ MASK OPTION”. *3 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc. Note : Part number of evaluation product in MB95120 series is MB95FV100D-101 (internal division resistance included) or MB95FV100D-102 (LCD booster circuit included) . When using it, the MCU board (MB2146301A or MB2146-302A) is required. 4 MB95120 Series ■ OSCILLATION STABILIZATION WAIT TIME The initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. The maximum value is shown as follows. Oscillation stabilization wait time (214−2) /FCH Remarks Approx. 4.10 ms (at main oscillation clock 4 MHz) ■ PACKAGES AND CORRESPONDING PRODUCTS Part number Package FPT-100P-M20 FPT-100P-M06 BGA-224P-M08 : Available : Unavailable MB95F128D/F128E MB95FV100D-101/102 5 MB95120 Series ■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS • Notes on Using Evaluation Products The Evaluation product has not only the functions of the MB95120 series but also those of other products to support software development for multiple series and models of the F2MC-8FX family. The I/O addresses for peripheral resources not used by the MB95120 series are therefore access-barred. Read/write access to these access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting in unexpected malfunctions of hardware or software. Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are used, the address may be read or written unexpectedly). Also, as the read values of prohibited addresses on the evaluation product are different to the values on the Flash memory and mask ROM products, do not use these values in the program. The functions corresponding to certain bits in single-byte registers may not be supported on Flash memory products. However, reading or writing to these bits will not cause malfunction of the hardware. Also, as the evaluation and Flash memory products are designed to have identical software operation, no particular precautions are required. • Difference of Memory Spaces If the amount of memory on the Evaluation product is different from that of the Flash memory product, carefully check the difference in the amount of memory from the model to be actually used when developing software. For details of memory space, refer to “■ CPU CORE”. • Current Consumption For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”. • Package For details of information on each package, refer to “■ PACKAGES AND CORRESPONDING PRODUCTS” and “■ PACKAGE DIMENSIONS”. • Operating voltage The operating voltage are different between the Evaluation and Flash memory products. For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”. 6 MB95120 Series ■ PIN ASSIGNMENT (TOP VIEW) VCC P90/V3 P91/V2 P92/V1 P93/V0 P94/C0 P95/C1 PA0/COM0 PA1/COM1 PA2/COM2 PA3/COM3 PB0/SEG00 PB1/SEG01 PB2/SEG02 PB3/SEG03 PB4/SEG04 PB5/SEG05 PB6/SEG06 PB7/SEG07 PC0/SEG08 PC1/SEG09 PC2/SEG10 PC3/SEG11 PC4/SEG12 VCC 10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VSS PG0 P00/INT00 P01/INT01 P02/INT02 P03/INT03 P04/INT04 P05/INT05 P06/INT06 P07/INT07 P10/UI0 P11/UO0 P12/UCK0 P13/TRG0/ADTG P14/PPG0 P20/PPG00 P21/PPG01 P22/TO00 P23/TO01 P24/EC0 P50/SCL0 P51/SDA0 P52/PPG1 AVR AVCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PC5/SEG13 PC6/SEG14 PC7/SEG15 PD0/SEG16 PD1/SEG17 PD2/SEG18 PD3/SEG19 PD4/SEG20 PD5/SEG21 PD6/SEG22 PD7/SEG23 PE0/SEG24 PE1/SEG25 PE2/SEG26 PE3/SEG27 PE4/SEG28/INT10 PE5/SEG29/INT11 PE6/SEG30/INT12 PE7/SEG31/INT13 P60/SEG32/PPG10 P61/SEG33/PPG11 MOD X0 X1 VSS Note : The P90 to P95 are not used as a general-purpose ports in the MB95F128E. (Continued) AVSS P30/AN00 P31/AN01 P32/AN02 P33/AN03 P34/AN04 P35/AN05 P36/AN06 P37/AN07 P40/AN08 P41/AN09 P42/AN10 P43/AN11 P53/TRG1 P70/TO0 P71/TI0 P67/SEG39/SIN P66/SEG38/SOT P65/SEG37/SCK P64/SEG36/EC1 P63/SEG35/TO11 P62/SEG34/TO10 RST X0A X1A (FPT-100P-M20) 7 MB95120 Series (Continued) (TOP VIEW) P92/V1 P93/V0 P94/C0 P95/C1 PA0/COM0 PA1/COM1 PA2/COM2 PA3/COM3 PB0/SEG00 PB1/SEG01 PB2/SEG02 PB3/SEG03 PB4/SEG04 PB5/SEG05 PB6/SEG06 PB7/SEG07 PC0/SEG08 PC1/SEG09 PC2/SEG10 PC3/SEG11 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P91/V2 P90/V3 VCC VSS PG0 P00/INT00 P01/INT01 P02/INT02 P03/INT03 P04/INT04 P05/INT05 P06/INT06 P07/INT07 P10/UI0 P11/UO0 P12/UCK0 P13/TRG0/ADTG P14/PPG0 P20/PPG00 P21/PPG01 P22/TO00 P23/TO01 P24/EC0 P50/SCL0 P51/SDA0 P52/PPG1 AVR AVCC AVSS P30/AN00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PC4/SEG12 VCC PC5/SEG13 PC6/SEG14 PC7/SEG15 PD0/SEG16 PD1/SEG17 PD2/SEG18 PD3/SEG19 PD4/SEG20 PD5/SEG21 PD6/SEG22 PD7/SEG23 PE0/SEG24 PE1/SEG25 PE2/SEG26 PE3/SEG27 PE4/SEG28/INT10 PE5/SEG29/INT11 PE6/SEG30/INT12 PE7/SEG31/INT13 P60/SEG32/PPG10 P61/SEG33/PPG11 MOD X0 X1 VSS X1A X0A RST 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note : The P90 to P95 are not used as a general-purpose ports in the MB95F128E. 8 P31/AN01 P32/AN02 P33/AN03 P34/AN04 P35/AN05 P36/AN06 P37/AN07 P40/AN08 P41/AN09 P42/AN10 P43/AN11 P53/TRG1 P70/TO0 P71/TI0 P67/SEG39/SIN P66/SEG38/SOT P65/SEG37/SCK P64/SEG36/EC1 P63/SEG35/TO11 P62/SEG34/TO10 (FPT-100P-M06) MB95120 Series ■ PIN DESCRIPTION Pin no. LQFP *1 1 2 3 4 5 6 7 8 9 10 11 12 13 QFP *2 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin name VSS PG0 P00/INT00 P01/INT01 P02/INT02 P03/INT03 P04/INT04 P05/INT05 P06/INT06 P07/INT07 P10/UI0 P11/UO0 P12/UCK0 P13/TRG0/ ADTG P14/PPG0 P20/PPG00 P21/PPG01 P22/TO00 P23/TO01 P24/EC0 H H G General-purpose I/O port The pin is shared with UART/SIO ch.0 data input. General-purpose I/O port The pin is shared with UART/SIO ch.0 data output. General-purpose I/O port The pin is shared with UART/SIO ch.0 clock I/O. General-purpose I/O port The pin is shared with 16-bit PPG ch.0 trigger input (TRG0) and A/D converter trigger input (ADTG). General-purpose I/O port The pin is shared with 16-bit PPG ch.0 output. General-purpose I/O port The pins are shared with 8/16-bit PPG ch.0 output. General-purpose I/O port The pins are shared with 8/16-bit compound timer ch.0 output. General-purpose I/O port The pin is shared with 8/16-bit compound timer ch.0 clock input. General-purpose I/O port The pin is shared with I2C ch.0 clock I/O. General-purpose I/O port The pin is shared with I2C ch.0 data I/O. General-purpose I/O port The pin is shared with 16-bit PPG ch.1 output. A/D converter reference input pin A/D converter power supply pin (Continued) C General-purpose I/O port The pins are shared with external interrupt input. Large current port. I/O circuit type*3 ⎯ H Function Power supply pin (GND) General-purpose I/O port 14 17 15 16 17 18 19 20 18 19 20 21 22 23 21 22 23 24 25 24 25 26 27 28 P50/SCL0 I P51/SDA0 P52/PPG1 AVR AVCC H ⎯ ⎯ 9 MB95120 Series Pin no. LQFP *1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 QFP *2 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin name AVSS P30/AN00 P31/AN01 P32/AN02 P33/AN03 P34/AN04 P35/AN05 P36/AN06 P37/AN07 P40/AN08 P41/AN09 P42/AN10 P43/AN11 P53/TRG1 P70/TO0 I/O circuit type*3 ⎯ Function A/D converter power supply pin (GND) J General-purpose I/O port The pins are shared with A/D converter analog input. J General-purpose I/O port The pins are shared with A/D converter analog input. H General-purpose I/O port The pin is shared with 16-bit PPG ch.1 trigger input. General-purpose I/O port The pin is shared with 16-bit reload timer ch.0 output. General-purpose I/O port The pin is shared with 16-bit reload timer ch.0 input. General-purpose I/O port The pin is shared with LIN-UART data input (SIN) and LCDC SEG output (SEG39) . General-purpose I/O port The pin is shared with LIN-UART data output (SOT) and LCDC SEG output (SEG38) . General-purpose I/O port The pin is shared with LIN-UART clock I/O (SCK) and LCDC SEG output (SEG37) . H P71/TI0 P67/SEG39/ SIN P66/SEG38/ SOT P65/SEG37/ SCK P64/SEG36/ EC1 P63/SEG35/ TO11 P62/SEG34/ TO10 RST X0A X1A VSS B' A ⎯ M 42 45 N 43 46 44 47 45 46 47 48 49 50 51 48 49 50 51 52 53 54 General-purpose I/O port The pin is shared with 8/16-bit compound timer ch.1 clock input (EC1) and LCDC SEG output (SEG36) . General-purpose I/O port The pins are shared with 8/16-bit compound timer ch.1 output (TO10, TO11) and LCDC SEG output (SEG34, SEG35) . Reset pin Sub clock oscillation pins (32 kHz) Power supply pin (GND) (Continued) 10 MB95120 Series Pin no. LQFP *1 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 QFP *2 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 Pin name X1 X0 MOD P61/SEG33/ PPG11 P60/SEG32/ PPG10 PE7/SEG31/ INT13 PE6/SEG30/ INT12 PE5/SEG29/ INT11 PE4/SEG28/ INT10 PE3/SEG27 PE2/SEG26 PE1/SEG25 PE0/SEG24 PD7/SEG23 PD6/SEG22 PD5/SEG21 PD4/SEG20 PD3/SEG19 PD2/SEG18 PD1/SEG17 PD0/SEG16 PC7/SEG15 PC6/SEG14 PC5/SEG13 VCC I/O circuit type*3 A B Function Main clock oscillation pins An operating mode designation pin General-purpose I/O port The pins are shared with 8/16-bit PPG ch.1 output (PPG10, PPG11) and LCDC SEG output (SEG32, SEG33) . M Q General-purpose I/O port The pins are shared with external interrupt input (INT10 to INT13) and LCDC SEG output (SEG28 to SEG31) . M General-purpose I/O port The pins are shared with LCDC SEG output. M General-purpose I/O port The pins are shared with LCDC SEG output. M ⎯ General-purpose I/O port The pins are shared with LCDC SEG output. Power supply pin (Continued) 11 MB95120 Series (Continued) Pin no. LQFP *1 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 *1 : FPT-100P-M20 *2 : FPT-100P-M06 *3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”. *4 : The P90 to P95 are not used as a general-purpose ports in the MB95F128E. QFP *2 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 Pin name PC4/SEG12 PC3/SEG11 PC2/SEG10 PC1/SEG09 PC0/SEG08 PB7/SEG07 PB6/SEG06 PB5/SEG05 PB4/SEG04 PB3/SEG03 PB2/SEG02 PB1/SEG01 PB0/SEG00 PA3/COM3 PA2/COM2 PA1/COM1 PA0/COM0 P95*4/C1 P94*4/C0 P93*4/V0 P92*4/V1 P91*4/V2 P90*4/V3 VCC ⎯ Power supply pin R General-purpose I/O port The pins are shared with power supply pins for LCDC drive. S General-purpose I/O port M General-purpose I/O port The pins are shared with LCDC COM output. M General-purpose I/O port The pins are shared with LCDC SEG output. M General-purpose I/O port The pins are shared with LCDC SEG output. I/O circuit type*3 Function 12 MB95120 Series ■ I/O CIRCUIT TYPE Type Circuit Remarks • Oscillation circuit • High-speed side Feedback resistance : approx. 1 MΩ • Low-speed side Feedback resistance : approx. 24 MΩ (Evaluation product : approx.10 MΩ) Damping resistance : approx.144 kΩ (Evaluation product : non-damping resistance ) • Only for input • Hysteresis input X1 (X1A) X 0 (X0A) N-ch Clock input A Standby control B Mode input Hysteresis input B’ Reset input • CMOS output • Hysteresis input P-ch Digital output Digital output Hysteresis input C Standby control External interrupt enable N-ch R P-ch P-ch Pull-up control Digital output Digital output CMOS input • • • • CMOS output CMOS input Hysteresis input With pull-up control G N-ch Standby control Hysteresis input • CMOS output • Hysteresis input • With pull-up control R P-ch P-ch Pull-up control Digital output Digital output Hysteresis input H N-ch Standby control (Continued) 13 MB95120 Series Type Circuit Remarks • N-ch open drain output • CMOS input • Hysteresis input N-ch Digital output CMOS input Hysteresis input I Standby control R P-ch P-ch Pull-up control Digital output Digital output Analog input • • • • CMOS output Hysteresis input Analog input With pull-up control J N-ch A/D control Standby control P-ch Hysteresis input • CMOS output • LCD output • Hysteresis input Digital output Digital output LCD output M N-ch LCD control Standby control P-ch Hysteresis input • • • • CMOS output LCD output CMOS input Hysteresis input Digital output Digital output LCD output N-ch N CMOS input Hysteresis input (Continued) LCD control Standby control 14 MB95120 Series (Continued) Type Circuit P-ch Remarks • CMOS output • LCD output • Hysteresis input Digital output Digital output LCD output N-ch Q LCD control Standby control Hysteresis input External interrupt control P-ch Digital output Digital output LCD internal division resistance I/O • CMOS output • LCD power supply • Hysteresis input N-ch R LCD control Standby control P-ch Hysteresis input • CMOS output • LCD power supply • Hysteresis input Digital output Digital output LCD booster I/O S Standby control N-ch Hysteresis input 15 MB95120 Series ■ HANDLING DEVICES • Preventing Latch-up Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used. Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC pin and VSS pin. When latch-up occurs, power supply current increases rapidly and might thermally damage elements. Also, take care to prevent the analog power supply voltage (AVCC , AVR) and analog input voltage from exceeding the digital power supply voltage (VCC) when the analog system power supply is turned on or off. • Stable Supply Voltage Supply voltage should be stabilized. A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range of the VCC power-supply voltage. For stabilization, in principle, keep the variation in VCC ripple (p-p value) in a commercial frequency range (50/60 Hz) not to exceed 10% of the standard VCC value and suppress the voltage variation so that the transient variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched. • Precautions for Use of External Clock Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from sub clock mode or stop mode. ■ PIN CONNECTION • Treatment of Unused Pin Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/ output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. If there is unused output pin, make it open. • Treatment of Power Supply Pins on A/D Converter Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D converter is not in use. Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 µF ceramic capacitor as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device. • Power Supply Pins In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS near this device. 16 MB95120 Series • Mode Pin (MOD) Connect the MOD pin directly to VCC or VSS pins. To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the MOD pin to VCC or VSS pins and to provide a low-impedance connection. • Analog Power Supply Always set the same potential to AVCC and VCC pins. When VCC > AVCC, the current may flow through the AN00 to AN11 pins. 17 MB95120 Series ■ PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL PROGRAMMER • Supported Parallel Programmers and Adapters The following table lists supported parallel programmers and adapters. Package Applicable adapter model FPT-100P-M20 FPT-100P-M06 TEF110-95F128HSPFV TEF110-95F128HSPF Parallel programmers AF9708 (Ver 02.35G or more) AF9709/B (Ver 02.35G or more) AF9723+AF9834 (Ver 02.08E or more) Note : For information on applicable adapter models and parallel programmers, contact the following: Flash Support Group, Inc. TEL: +81-53-428-8380 • Sector Configuration The individual sectors of Flash memory correspond to addresses used for CPU access and programming by the parallel programmer as follows: • MB95F128D/F128E (60 Kbytes) Flash memory CPU address 1000H SA1 (4 Kbytes) SA2 (4 Kbytes) 2FFFH 3000H SA3 (4 Kbytes) 3FFFH 4000H SA4 (16 Kbytes) 7FFFH 8000H SA5 (16 Kbytes) SA6 (4 Kbytes) CFFFH D000H SA7 (4 Kbytes) DFFFH E000H SA8 (4 Kbytes) EFFFH F000H SA9 (4 Kbytes) FFFFH 7FFFFH *: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer programs data into Flash memory. These programmer addresses are used for the parallel programmer to program or erase data in Flash memory. • Programming Method 1) Set the type code of the parallel programmer to 17222. 2) Load program data to programmer addresses 71000H to 7FFFFH. 3) Programmed by parallel programmer 18 7EFFFH 7F000H 7DFFFH 7E000H 7CFFFH 7D000H Upper bank Lower bank Programmer address* 71000H 71FFFH 72000H 72FFFH 73000H 73FFFH 74000H 77FFFH 78000H 7BFFFH 7C000H 1FFFH 2000H BFFFH C000H MB95120 Series ■ BLOCK DIAGRAM F MC-8FX CPU RST X0/X1 X0A/X1A Reset control Clock control Watch prescaler PG0 P00/INT00 to P07/INT07 P10/UI0 P11/UO0 P12/UCK0 16-bit PPG ch.0 Internal bus P13/TRG0/ADTG P14/PPG0 P20/PPG00 P21/PPG01 P22/TO00 P23/TO01 P24/EC0 P30/AN00 to P37/AN07 P40/AN08 to P43/AN11 AVCC AVSS AVR P50/SCL0 P51/SDA0 P52/PPG1 P53/TRG1 I2C 8/10-bit A/D converter 8/16-bit compound timer ch.0 8/16-bit PPG ch.0 UART/SIO P62/SEG34/TO10 8/16-bit compound timer ch.1 P63/SEG35/TO11 P64/SEG36/EC1 P65/SEG37/SCK LIN-UART P66/SEG38/SOT P67/SEG39/SIN P70/TO0 P71/TI0 P90/V3 to P93/V0 P94/C0, P95/C1 PA0/COM0 to PA3/COM3 PB0/SEG00 to PB7/SEG07 PC0/SEG08 to PC7/SEG15 PD0/SEG16 to PD7/SEG23 PE0/SEG24 to PE3/SEG27 PE4/SEG28/INT10 PE5/SEG29/INT11 PE6/SEG30/INT12 PE7/SEG31/INT13 Watch counter External interrupt ch.0 to ch.7 2 ROM RAM Interrupt control Wild register P60/SEG32/PPG10 P61/SEG33/PPG11 8/16-bit PPG ch.1 16-bit reload timer LCDC 16-bit PPG ch.1 Port Other pins MOD, VCC External interrupt ch.8 to ch.11 Port 19 MB95120 Series ■ CPU CORE 1. Memory space Memory space of the MB95120 series is 64 Kbytes and consists of I/O area, data area, and program area. The memory space includes special - purpose areas such as the general - purpose registers and vector table. Memory map of the MB95120 series is shown below. • Memory Map MB95F128D MB95F128E 0000H I/O 0080H 0100H 0200H 0880H 0F80H Extended I/O 1000H 1000H RAM 2 Kbytes Register MB95FV100D-101 MB95FV100D-102 0000H I/O 0080H 0100H 0200H RAM 3.75 Kbytes Register Access prohibited 0F80H Extended I/O Flash memory 60 Kbytes Flash memory 60 Kbytes FFFFH FFFFH 20 MB95120 Series 2. Register The MB95120 series has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The dedicated registers are as follows: Program counter (PC) : A 16-bit register to indicate locations where instructions are stored. Accumulator (A) : A 16-bit register for temporary storage of arithmetic operations. In the case of an 8-bit data processing instruction, the lower 1 byte is used. Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator. In the case of an 8-bit data processing instruction, the lower 1 byte is used. Index register (IX) : A 16-bit register for index modification Extra pointer (EP) : A 16-bit pointer to point to a memory address. Stack pointer (SP) : A 16-bit register to indicate a stack area. Program status (PS) : A 16-bit register for storing a register bank pointer, a direct bank pointer, and a condition code register 16-bit PC A T IX EP SP PS Initial Value : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status FFFDH 0000H 0000H 0000H 0000H 0000H 0030H The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer (DP) and the lower 8 bits for use as a condition code register (CCR) . (Refer to the diagram below.) • Structure of the program status bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 PS R4 R3 R2 R1 R0 DP2 DP1 bit 8 DP0 bit 7 H bit 6 I bit 5 IL1 bit 4 IL0 bit 3 N bit 2 Z bit 1 V bit 0 C RP DP CCR 21 MB95120 Series The RP indicates the address of the register bank currently being used. The relationship between the content of RP and the real address conforms to the conversion rule illustrated below: • Rule for Conversion of Actual Addresses in the General-purpose Register Area RP upper "0" "0" "0" "0" "0" "0" "0" A9 "1" A8 R4 A7 R3 A6 R2 A5 R1 A4 OP code lower R0 A3 b2 A2 b1 A1 b0 A0 Generated address A15 A14 A13 A12 A11 A10 The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct addresses to 0080H to 00FFH. Direct bank pointer (DP2 to DP0) Specified address area Mapping area XXXB (no effect to mapping) 000B (initial value) 001B 010B 011B 100B 101B 110B 111B 0080H to 00FFH 0000H to 007FH 0000H to 007FH (without mapping) 0080H to 00FFH (without mapping) 0100H to 017FH 0180H to 01FFH 0200H to 027FH 0280H to 02FFH 0300H to 037FH 0380H to 03FFH 0400H to 047FH The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that control CPU operations at interrupt. H flag : Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. This flag is for decimal adjustment instructions. I flag : Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”. The flag is cleared to “0” when reset. IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level is higher than the value indicated by these bits. IL1 0 0 1 1 N flag Z flag V flag C flag IL0 0 1 0 1 Interrupt level 0 1 2 3 Low = no interruption Priority High : Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the bit is set to “0”. : Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise. : Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0” otherwise. : Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. Set to the shift-out value in the case of a shift instruction. 22 MB95120 Series The following general-purpose registers are provided: General-purpose registers: 8-bit data storage registers The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8-register. Up to a total of 32 banks can be used on the MB95120 series. The bank currently in use is indicated by the register bank pointer (RP).8-register. Up to a total of 32 banks can be used on the MB95120 series. The bank currently in use is specified by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0) to general-purpose register 7 (R7). • Register Bank Configuration 8-bit 1F8H This address = 0100H + 8 × (RP) Address 100H R0 R1 R2 R3 R4 R5 107H R6 R7 Bank 0 R0 R0 R1 R2 R3 R4 R5 R6 R7 R1 R2 R3 R4 R5 R6 1FFH R7 Bank 31 32 banks 32 banks (RAM area) The number of banks is limited by the usable RAM capacitance. Memory area 23 MB95120 Series ■ I/O MAP Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH, 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H 0023H Register abbreviation PDR0 DDR0 PDR1 DDR1 ⎯ WATR PLLC SYCC STBC RSRR TBTC WPCR WDTC ⎯ PDR2 DDR2 PDR3 DDR3 PDR4 DDR4 PDR5 DDR5 PDR6 DDR6 PDR7 DDR7 ⎯ PDR9 DDR9 PDRA DDRA PDRB DDRB PDRC DDRC Register name Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register (Disabled) Oscillation stabilization wait time setting register PLL control register System clock control register Standby control register Reset source register Timebase timer control register Watch prescaler control register Watchdog timer control register (Disabled) Port 2 data register Port 2 direction register Port 3 data register Port 3 direction register Port 4 data register Port 4 direction register Port 5 data register Port 5 direction register Port 6 data register Port 6 direction register Port 7 data register Port 7 direction register (Disabled) Port 9 data register Port 9 direction register Port A data register Port A direction register Port B data register Port B direction register Port C data register Port C direction register R/W R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B 00000000B 00000000B 00000000B ⎯ 11111111B 00000000B 1010X011B 00000000B XXXXXXXXB 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued) 24 MB95120 Series Address 0024H 0025H 0026H 0027H 0028H, 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H, 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH 0040H, 0041H 0042H 0043H 0044H 0045H 0046H, 0047H 0048H 0049H Register abbreviation PDRD DDRD PDRE DDRE ⎯ PDRG DDRG ⎯ PUL1 PUL2 PUL3 PUL4 PUL5 PUL7 ⎯ PULG T01CR1 T00CR1 T11CR1 T10CR1 PC01 PC00 PC11 PC10 TMCSRH0 TMCSRL0 ⎯ PCNTH0 PCNTL0 PCNTH1 PCNTL1 ⎯ EIC00 EIC10 Register name Port D data register Port D direction register Port E data register Port E direction register (Disabled) Port G data register Port G direction register (Disabled) Port 1 pull-up register Port 2 pull-up register Port 3 pull-up register Port 4 pull-up register Port 5 pull-up register Port 7 pull-up register (Disabled) Port G pull-up register 8/16-bit compound timer 01 control status register 1 ch.0 8/16-bit compound timer 00 control status register 1 ch.0 8/16-bit compound timer 11 control status register 1 ch.1 8/16-bit compound timer 10 control status register 1 ch.1 8/16-bit PPG1 control register ch.0 8/16-bit PPG0 control register ch.0 8/16-bit PPG1 control register ch.1 8/16-bit PPG0 control register ch.1 16-bit reload timer control status register (upper byte) ch.0 16-bit reload timer control status register (lower byte) ch.0 (Disabled) 16-bit PPG status control register (upper byte) ch.0 16-bit PPG status control register (lower byte) ch.0 16-bit PPG status control register (upper byte) ch.1 16-bit PPG status control register (lower byte) ch.1 (Disabled) External interrupt circuit control register ch.0/ch.1 External interrupt circuit control register ch.2/ch.3 R/W R/W R/W R/W R/W ⎯ R/W R/W ⎯ R/W R/W R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ⎯ R/W R/W R/W R/W ⎯ R/W R/W Initial value 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B (Continued) 25 MB95120 Series Address 004AH 004BH 004CH 004DH 004EH, 004FH 0050H 0051H 0052H 0053H 0054H 0055H 0056H 0057H 0058H 0059H 005AH 005BH to 005FH 0060H 0061H 0062H 0063H 0064H 0065H 0066H to 006BH 006CH 006DH 006EH 006FH 0070H 0071H 0072H Register abbreviation EIC20 EIC30 EIC01 EIC11 ⎯ SCR SMR SSR RDR/TDR ESCR ECCR SMC10 SMC20 SSR0 TDR0 RDR0 ⎯ IBCR00 IBCR10 IBSR0 IDDR0 IAAR0 ICCR0 ⎯ ADC1 ADC2 ADDH ADDL WCSR ⎯ FSR 2 Register name External interrupt circuit control register ch.4/ch.5 External interrupt circuit control register ch.6/ch.7 External interrupt circuit control register ch.8/ch.9 External interrupt circuit control register ch.10/ch.11 (Disabled) LIN-UART serial control register LIN-UART serial mode register LIN-UART serial status register LIN-UART reception/transmission data register LIN-UART extended status control register LIN-UART extended communication control register UART/SIO serial mode control register 1 ch.0 UART/SIO serial mode control register 2 ch.0 UART/SIO serial status register ch.0 UART/SIO serial output data register ch.0 UART/SIO serial input data register ch.0 (Disabled) I2C bus control register 0 ch.0 I2C bus control register 1 ch.0 I2C bus status register ch.0 I C data register ch.0 I C address register ch.0 I2C clock control register ch.0 (Disabled) 8/10-bit A/D converter control register 1 8/10-bit A/D converter control register 2 8/10-bit A/D converter data register (upper byte) 8/10-bit A/D converter data register (lower byte) Watch counter status register (Disabled) Flash memory status register 2 R/W R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R ⎯ R/W R/W R R/W R/W R/W ⎯ R/W R/W R/W R/W R/W ⎯ R/W Initial value 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00001000B 00000000B 00000100B 000000XXB 00000000B 00100000B 00000001B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ 000X0000B (Continued) 26 MB95120 Series Address 0073H 0074H 0075H 0076H 0077H 0078H 0079H 007AH 007BH 007CH 007DH 007EH 007FH 0F80H 0F81H 0F82H 0F83H 0F84H 0F85H 0F86H 0F87H 0F88H 0F89H to 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H 0F98H 0F99H 0F9AH Register abbreviation SWRE0 SWRE1 ⎯ WREN WROR ⎯ ILR0 ILR1 ILR2 ILR3 ILR4 ILR5 ⎯ WRARH0 WRARL0 WRDR0 WRARH1 WRARL1 WRDR1 WRARH2 WRARL2 WRDR2 ⎯ T01CR0 T00CR0 T01DR T00DR TMCR0 T11CR0 T10CR0 T11DR T10DR Register name Flash memory sector writing control register 0 Flash memory sector writing control register 1 (Disabled) Wild register address compare enable register Wild register data test setting register Register bank pointer (RP) , Mirror of direct bank pointer (DP) Interrupt level setting register 0 Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt level setting register 4 Interrupt level setting register 5 (Disabled) Wild register address setting register (upper byte) ch.0 Wild register address setting register (lower byte) ch.0 Wild register data setting register ch.0 Wild register address setting register (upper byte) ch.1 Wild register address setting register (lower byte) ch.1 Wild register data setting register ch.1 Wild register address setting register (upper byte) ch.2 Wild register address setting register (lower byte) ch.2 Wild register data setting register ch.2 (Disabled) 8/16-bit compound timer 01 control status register 0 ch.0 8/16-bit compound timer 00 control status register 0 ch.0 8/16-bit compound timer 01 data register ch.0 8/16-bit compound timer 00 data register ch.0 8/16-bit compound timer 00/01 timer mode control register ch.0 8/16-bit compound timer 11 control status register 0 ch.1 8/16-bit compound timer 10 control status register 0 ch.1 8/16-bit compound timer 11 data register ch.1 8/16-bit compound timer 10 data register ch.1 R/W R/W R/W ⎯ R/W R/W ⎯ R/W R/W R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B 00000000B ⎯ 00000000B 00000000B ⎯ 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued) 27 MB95120 Series Address 0F9BH 0F9CH 0F9DH 0F9EH 0F9FH 0FA0H 0FA1H 0FA2H 0FA3H 0FA4H 0FA5H 0FA6H 0FA7H 0FA8H, 0FA9H 0FAAH 0FABH 0FACH 0FADH 0FAEH 0FAFH 0FB0H 0FB1H 0FB2H 0FB3H 0FB4H 0FB5H 0FB6H to 0FBBH 0FBCH 0FBDH 0FBEH Register abbreviation TMCR1 PPS01 PPS00 PDS01 PDS00 PPS11 PPS10 PDS11 PDS10 PPGS REVC TMRH0/ TMRLRH0 TMRL0/ TMRLRL0 ⎯ PDCRH0 PDCRL0 PCSRH0 PCSRL0 PDUTH0 PDUTL0 PDCRH1 PDCRL1 PCSRH1 PCSRL1 PDUTH1 PDUTL1 ⎯ BGR1 BGR0 PSSR0 Register name 8/16-bit compound timer 10/11 timer mode control register ch.1 8/16-bit PPG1 cycle setting buffer register ch.0 8/16-bit PPG0 cycle setting buffer register ch.0 8/16-bit PPG1 duty setting buffer register ch.0 8/16-bit PPG0 duty setting buffer register ch.0 8/16-bit PPG1 cycle setting buffer register ch.1 8/16-bit PPG0 cycle setting buffer register ch.1 8/16-bit PPG1 duty setting buffer register ch.1 8/16-bit PPG0 duty setting buffer register ch.1 8/16-bit PPG start register 8/16-bit PPG output inversion register 16-bit reload timer/reload register (upper byte) ch.0 16-bit reload timer/reload register (lower byte) ch.0 (Disabled) 16-bit PPG down counter register (upper byte) ch.0 16-bit PPG down counter register (lower byte) ch.0 16-bit PPG cycle setting buffer register (upper byte) ch.0 16-bit PPG cycle setting buffer register (lower byte) ch.0 16-bit PPG duty setting buffer register (upper byte) ch.0 16-bit PPG duty setting buffer register (lower byte) ch.0 16-bit PPG down counter register (upper byte) ch.1 16-bit PPG down counter register (lower byte) ch.1 16-bit PPG cycle setting buffer register (upper byte) ch.1 16-bit PPG cycle setting buffer register (lower byte) ch.1 16-bit PPG duty setting buffer register (upper byte) ch.1 16-bit PPG duty setting buffer register (lower byte) ch.1 (Disabled) LIN-UART baud rate generator register 1 LIN-UART baud rate generator register 0 UART/SIO dedicated baud rate generator prescaler select register ch.0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ⎯ R R R/W R/W R/W R/W R R R/W R/W R/W R/W ⎯ R/W R/W R/W Initial value 00000000B 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B ⎯ 00000000B 00000000B 00000000B (Continued) 28 MB95120 Series (Continued) Address 0FBFH 0FC0H, 0FC1H 0FC2H 0FC3H 0FC4H 0FC5H 0FC6H 0FC7H 0FC8H 0FC9H 0FCAH 0FCBH 0FCCH 0FCDH to 0FE0H 0FE1H, 0FE2H 0FE3H 0FE4H to 0FEDH 0FEEH 0FEFH 0FF0H to 0FFFH Register abbreviation BRSR0 ⎯ AIDRH AIDRL LCDCC LCDCE1 LCDCE2 LCDCE3 LCDCE4 LCDCE5 LCDCE6 LCDCB1 LCDCB2 LCDRAM ⎯ WCDR ⎯ ILSR WICR ⎯ Register name UART/SIO dedicated baud rate generator baud rate setting register ch.0 (Disabled) A/D input disable register (upper byte) A/D input disable register (lower byte) LCDC control register LCDC enable register 1 LCDC enable register 2 LCDC enable register 3 LCDC enable register 4 LCDC enable register 5 LCDC enable register 6 LCDC blinking setting register 1 LCDC blinking setting register 2 LCDC display RAM (Disabled) Watch counter data register (Disabled) Input level select register Interrupt pin select circuit control register (Disabled) R/W R/W ⎯ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ⎯ R/W ⎯ R/W R/W ⎯ Initial value 00000000B ⎯ 00000000B 00000000B 00010000B 00110000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ 00111111B ⎯ 00000000B 01000000B ⎯ • R/W access symbols R/W : Readable/Writable R : Read only W : Write only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value. 29 MB95120 Series ■ INTERRUPT SOURCE TABLE Interrupt source External interrupt ch.0 External interrupt ch.4 External interrupt ch.1 External interrupt ch.5 External interrupt ch.2 External interrupt ch.6 External interrupt ch.3 External interrupt ch.7 UART/SIO ch.0 8/16-bit compound timer ch.0 (Lower) 8/16-bit compound timer ch.0 (Upper) LIN-UART (reception) LIN-UART (transmission) 8/16-bit PPG ch.1 (Lower) 8/16-bit PPG ch.1 (Upper) 16-bit reload timer ch.0 8/16-bit PPG ch.0 (Upper) 8/16-bit PPG ch.0 (Lower) 8/16-bit compound timer ch.1 (Upper) 16-bit PPG ch.0 I2C ch.0 16-bit PPG ch.1 8/10-bit A/D converter Timebase timer Watch prescaler/watch counter External interrupt ch.8 External interrupt ch.9 External interrupt ch.10 External interrupt ch.11 8/16-bit compound timer ch.1 (Lower) Flash memory IRQ22 IRQ23 FFCEH FFCCH FFCFH FFCDH L22 [1 : 0] L23 [1 : 0] Low IRQ21 FFD0H FFD1H L21 [1 : 0] Interrupt request number IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 IRQ20 Vector table address Upper FFFAH FFF8H FFF6H FFF4H FFF2H FFF0H FFEEH FFECH FFEAH FFE8H FFE6H FFE4H FFE2H FFE0H FFDEH FFDCH FFDAH FFD8H FFD6H FFD4H FFD2H Lower FFFBH FFF9H FFF7H FFF5H FFF3H FFF1H FFEFH FFEDH FFEBH FFE9H FFE7H FFE5H FFE3H FFE1H FFDFH FFDDH FFDBH FFD9H FFD7H FFD5H FFD3H Same level Bit name of priority order interrupt level (at simultaneous setting register occurrence) L00 [1 : 0] L01 [1 : 0] L02 [1 : 0] L03 [1 : 0] L04 [1 : 0] L05 [1 : 0] L06 [1 : 0] L07 [1 : 0] L08 [1 : 0] L09 [1 : 0] L10 [1 : 0] L11 [1 : 0] L12 [1 : 0] L13 [1 : 0] L14 [1 : 0] L15 [1 : 0] L16 [1 : 0] L17 [1 : 0] L18 [1 : 0] L19 [1 : 0] L20 [1 : 0] High 30 MB95120 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol Vcc AVcc AVR V0 to V3 V0 Power supply voltage for LCD V1 V2 V3 C0, C1 Input voltage*1 Output voltage* 1 Rating Min Vss − 0.3 Vss − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 Vss − 0.3 Vss − 0.3 Vss − 0.3 − 2.0 ⎯ ⎯ Max Vss + 4.0 Vss + 4.0 VSS + 4.0 VSS + 2.0 VSS + 2.0 VSS + 4.0 VSS + 6.0 VSS + 6.0 Vss + 4.0 Vss + 6.0 Vss + 4.0 + 2.0 20 15 15 Unit *2 *2 Remarks Power supply voltage* 1 V Products with LCD internal division resistance*3 V Products with booster circuit* 3 VI1 VI2 VO ICLAMP Σ|ICLAMP| IOL1 IOL2 V V mA mA mA Other than P50, P51*4 P50, P51 *4 Applicable to pins*5 Applicable to pins*5 Other than P00 to P07 P00 to P07 Other than P00 to P07 Average output current = operating current × operating ratio (1 pin) P00 to P07 Average output current = operating current × operating ratio (1 pin) Maximum clamp current Total maximum clamp current “L” level maximum output current IOLAV1 “L” level average current IOLAV2 ⎯ 4 mA 12 “L” level total maximum output current “L” level total average output current “H” level maximum output current ΣIOL ΣIOLAV IOH1 IOH2 ⎯ ⎯ ⎯ 100 mA Total average output current = operating current × operating ratio (Total of pins) Other than P00 to P07 P00 to P07 (Continued) 50 − 15 − 15 mA mA 31 MB95120 Series (Continued) Parameter Symbol Rating Min Max −4 ⎯ IOHAV2 −8 mA Unit Remarks Other than P00 to P07 Average output current = operating current × operating ratio (1 pin) P00 to P07 Average output current = operating current × operating ratio (1 pin) IOHAV1 “H” level average current “H” level total maximum output current “H” level total average output current Power consumption Operating temperature Storage temperature ΣIOH ΣIOHAV Pd TA Tstg ⎯ ⎯ ⎯ − 40 − 55 − 100 − 50 320 + 85 + 150 mA Total average output current = operating current × operating ratio (Total of pins) mA mW °C °C *1 : The parameter is based on AVSS = VSS = 0.0 V. *2 : Apply equal potential to AVcc and Vcc. AVR should not exceed AVcc + 0.3 V. *3 : V0 to V3 should not exceed VCC + 0.3 V. *4 : VI1 and Vo should not exceed VCC + 0.3 V. VI1 must not exceed the rating voltage. However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI1 rating. *5 : Applicable to pins : P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P52, P53 • Use within recommended operating conditions. • Use at DC voltage (current). • +B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting resistance placed between the + B signal and the microcontroller. • The value of the limiting resistance should be set so that when the + B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this affects other devices. • Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. • Note that if the + B input is applied during power-on, the power supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. • Care must be taken not to leave the + B input pin open. • Note that analog system input/output pins other than the A/D input pins (LCD drive pins, etc.) cannot accept +B signal input. 32 MB95120 Series • Sample recommended circuits : • Input/Output Equivalent circuits Protective diode Limiting resistance Vcc P-ch N-ch R + B input (0 V to 16 V) WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 33 MB95120 Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Parameter Symbol Pin name Condition Value Min 1.8* Max 3.3 Unit Remarks At normal operation, Flash memory product, TA = −10 °C to +85 °C At normal operation, Flash memory product, TA = −40 °C to +85 °C Evaluation product TA = +5 °C to +35 °C Holds condition in stop mode, Flash memory product The range of liquid crystal power supply: without up-conversion (The optimal value depends on liquid crystal display elements used.) Power supply voltage VCC, AVCC ⎯ ⎯ 2.0* 3.3 V 2.6 1.5 3.6 3.3 Power supply voltage for LCD V0 to V3 ⎯ ⎯ VSS VCC V A/D converter reference input voltage Operating temperature AVR ⎯ ⎯ ⎯ ⎯ 1.8 − 40 AVCC + 85 V °C TA * : The values vary with the operating frequency, machine clock or analog guarantee range. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 34 MB95120 Series 3. DC Characteristics (VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Symbol VIH1 VIH2 Pin name P10 (selectable at UI0) , P67 (selectable at SIN) P50, P51 (selectable at I2C) P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P50 to P53, P60 to P67, P70, P71, P90 to P95, PA0 to PA3, PB0 to PB7, PC0 to PC7, PD0 to PD7, PE0 to PE7 P50, P51 RST, MOD P10 (selectable at UI0) , P50, P51 (selectable at I2C) P67 (selectable at SIN) P00 to P07 P10 to P14, P20 to P24, P30 to P37, P40 to P43, P50 to P53, P60 to P67, P70, P71, P90 to P95, PA0 to PA3, PB0 to PB7, PC0 to PC7, PD0 to PD7, PE0 to PE7 RST, MOD Conditions ⎯ ⎯ Value Min 0.7 VCC 0.7 VCC Typ ⎯ ⎯ Max VCC + 0.3 VSS + 5.5 Unit V V Remarks When selecting CMOS input level (Hysteresis input) “H” level input voltage VIHS1 ⎯ 0.8 VCC ⎯ VCC + 0.3 V Hysteresis input VIHS2 VIHM “L” level input voltage VIL ⎯ ⎯ ⎯ 0.8 VCC 0.8 VCC VSS − 0.3 ⎯ ⎯ ⎯ VSS + 5.5 VCC + 0.3 0.3 VCC V V V Hysteresis input When selecting CMOS input level (Hysteresis input) “L” level input voltage VILS ⎯ VSS − 0.3 ⎯ 0.2 VCC V Hysteresis input VILM Open-drain output application voltage ⎯ ⎯ VSS − 0.3 VSS − 0.3 ⎯ ⎯ 0.2 VCC VSS + 5.5 V Hysteresis input VD1 P50, P51 V (Continued) 35 MB95120 Series (VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter “H” level output voltage Symbol VOH1 VOH2 VOL1 VOL2 Input leakage current (Hi-Z output leakage current) Open-drain output leakage current Pin name Conditions Value Min 2.4 2.4 ⎯ ⎯ −5 Typ ⎯ ⎯ ⎯ ⎯ ⎯ Max ⎯ ⎯ 0.4 0.4 +5 Unit V V V V µA When the pull-up prohibition setting Remarks Output pin other IOH = − 4.0 mA than P00 to P07 P00 to P07 IOH = − 8.0 mA Output pin other than P00 to IOL = 4.0 mA P07, RST P00 to P07 Port other than P50, P51 IOL = 12 mA 0.0 V < VI < VCC “L” level output voltage ILI ILIOD P50, P51 P10 to P14, P20 to P24, P30 to P37, P40 to P43, P52, P53, P70, P71 Other than AVCC, AVSS, AVR, VCC, VSS 0.0 V < VI < VSS + 5.5 V ⎯ ⎯ 5 µA Pull-up resistor RPULL VI = 0.0 V 25 50 100 kΩ When the pull-up permission setting Input capacitance CIN f = 1 MHz ⎯ 5 15 pF (Continued) 36 MB95120 Series (VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Symbol Pin name Conditions Value Min ⎯ Typ Max Unit Remarks FCH = 20 MHz FMP = 10 MHz Main clock mode (divided by 2) ICC FCH = 32 MHz FMP = 16 MHz Main clock mode (divided by 2) 11.0 14.0 At other than Flash memory mA writing and erasing At Flash mA memory writing and erasing At other than Flash memory mA writing and erasing At Flash mA memory writing and erasing ⎯ 30.0 35.0 ⎯ 17.6 22.4 ⎯ 38.1 44.9 ICCS Power supply current* VCC (External clock operation) ICCL FCH = 20 MHz FMP = 10 MHz Main Sleep mode (divided by 2) FCH = 32 MHz FMP = 16 MHz Main Sleep mode (divided by 2) FCL = 32 kHz FMPL = 16 kHz Sub clock mode (divided by 2) FCL = 32 kHz FMPL = 16 kHz Sub sleep mode (divided by 2) FCL = 32 kHz Watch mode Main stop mode TA = + 25 °C FCH = 4 MHz FMP = 10 MHz Main PLL mode (multiplied by 2.5) FCH = 6.4 MHz FMP = 16 MHz Main PLL mode (multiplied by 2.5) ⎯ 4.5 6.0 mA ⎯ 7.2 9.6 mA ⎯ 25 35 µA ICCLS ⎯ 7 15 µA ICCT ⎯ 2 10 µA ⎯ 10 14 mA ICCMPLL ⎯ 16.0 22.4 mA (Continued) 37 MB95120 Series (Continued) Symbol (VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Pin name Conditions FCL = 32 kHz FMPL = 128 kHz Sub PLL mode (multiplied by 4) , T A = + 25 ° C FCH = 10 MHz Timebase timer mode T A = + 25 ° C Sub stop mode T A = + 25 ° C FCH = 16 MHz At operating of A/D conversion AVCC IAH FCH = 16 MHz At stopping of A/D conversion T A = + 25 ° C ⎯ V0 to V3, COM0 to COM3 SEG00 to SEG39 V3 V2 V1 Between V3 and VSS Value Min Typ Max Unit Remarks Parameter ICCSPLL VCC (External clock operation) ⎯ 190 250 µA ICTS Power supply current* ⎯ ⎯ ⎯ 0.4 0.5 mA µA mA ICCH 1 5 IA 1.3 2.2 ⎯ 1 5 µA Products with LCD internal kΩ division resistance only µA V V V Products with booster circuit only LCD internal division resistance LCD leakage current Output voltage for LCD boost Reference voltage for LCD boost Reference voltage input impedance COM0 to COM3 output impedance SEG00 to SEG39 output impedance LCD leak current RLCD ⎯ 300 ⎯ ILCDL VV3 VV2 VV1 ⎯ V1 = 1.5 V V1 = 1.5 V IIN = 0.0 µA ⎯ 4.3 2.9 1.4 ⎯ 4.5 3.0 1.5 ±1 4.7 3.1 1.7 RRIN V1 ⎯ 8.5 9.8 11 kΩ RVCOM COM0 to COM3 V1 to V3 = 3.6 V ⎯ ⎯ 5 kΩ RVSEG SEG00 to SEG39 V0 to V3, COM0 to COM3 SEG00 to SEG39 ⎯ ⎯ ⎯ 7 kΩ ILCDL ⎯ −1 ⎯ +1 µA * : The power-supply current is determined by the external clock. • Refer to “4. AC characteristics (1) Clock Timing” for FCH and FCL. • Refer to “4. AC characteristics (2) Source Clock/Machine Clock” for FMP and FMPL. 38 MB95120 Series 4. AC Characteristics (1) Clock Timing (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter SymCondiPin name bol tions Value Min 1.00 1.00 FCH Clock frequency X0, X1 3.00 3.00 3.00 3.00 ⎯ FCL X0A, X1A ⎯ tHCYL Clock cycle time tLCYL tWH1 tWL1 tWH2 tWL2 tCR tCF X0A, X1A X0 X0A X0, X0A X0, X1 ⎯ 61.5 30.8 ⎯ 61.5 ⎯ ⎯ 32.768 ⎯ ⎯ 30.5 ⎯ 15.2 ⎯ ⎯ 1000 1000 ⎯ ⎯ ⎯ 5 kHz ns ns µs ns µs ns Typ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 32.768 Max 16.25 32.50 10.00 8.13 6.50 4.06 ⎯ Unit MHz Remarks When using main oscillation circuit MHz When using external clock MHz Main PLL multiplied by 1 MHz Main PLL multiplied by 2 MHz Main PLL multiplied by 2.5 MHz Main PLL multiplied by 4 kHz When using sub oscillation circuit When using sub PLL VCC = 2.3 V to 3.3 V When using main oscillation circuit When using external clock When using sub oscillation circuit When using external clock Duty ratio is about 30% to 70%. When using external clock Input clock pulse width Input clock rise time and fall time 39 MB95120 Series • Input wave form for using external clock (main clock) tHCYL tWH1 tCR tCF 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC tWL1 X0 • Figure of Main Clock Input Port External Connection When using a crystal or ceramic oscillator Microcontroller X0 X1 FCH C1 C2 When using external clock Microcontroller X0 X1 Open FCH • Input wave form for using external clock (sub clock) tLCYL tWH2 tCR tCF 0.8 VCC 0.8 VCC 0.1 VCC 0.1 VCC 0.1 VCC tWL2 X0A • Figure of Sub clock Input Port External Connection When using a crystal or ceramic oscillator Microcontroller X0A X1A FCL C1 C2 When using external clock Microcontroller X0A X1A Open FCL 40 MB95120 Series (2) Source Clock/Machine Clock (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter SymPin bol name Value Min Typ ⎯ Max Unit Remarks When using main clock Min : FCH = 16.25 MHz, PLL multiplied by 1 Max : FCH = 1 MHz, divided by 2 When using sub clock Min : FCL = 32 kHz, PLL multiplied by 4 Max : FCL = 32 kHz, divided by 2 61.5 Source clock cycle time* (Clock before setting division) 1 2000 ns tSCLK ⎯ 7.6 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 61.0 µs Source clock frequency FSP FSPL 0.50 16.384 61.5 16.25 MHz When using main clock When using main clock Min : FSP = 16.25 MHz, no division Max : FSP = 0.5 MHz, divided by 16 When using sub clock Min : FSPL = 131 kHz, no division Max : FSPL = 16 kHz, divided by 16 131.072 kHz When using sub clock 32000 ns Machine clock cycle time*2 (Minimum instruction execution time) tMCLK ⎯ 7.6 ⎯ ⎯ ⎯ 976.5 16.250 µs Machine clock frequency FMP FMPL ⎯ 0.031 1.024 MHz When using main clock 131.072 kHz When using sub clock *1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes the machine clock. Further, the source clock can be selected as follows. • Main clock divided by 2 • PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication) • Sub clock divided by 2 • PLL multiplication of sub clock (select from 2, 3, 4 multiplication) *2 : Operation clock of the microcontroller. Machine clock can be selected as follows. • Source clock (no division) • Source clock divided by 4 • Source clock divided by 8 • Source clock divided by 16 • Outline of clock generation block FCH (main oscillation) Divided by 2 Main PLL ×1 ×2 × 2.5 ×4 SCLK (source clock) FCL (sub oscillation) Divided by 2 Clock mode select bit (SYCC: SCS1, SCS0) Division circuit ×1 × 1/4 × 1/8 × 1/16 MCLK (machine clock) Sub PLL ×2 ×3 ×4 41 MB95120 Series • Operating voltage - Operating frequency (When TA = − 10 °C to + 85 °C) • MB95F128D/F128E Sub clock mode and watch mode operation guarantee range Operating voltage (V) 3.6 3.6 Main clock mode and main PLL mode operation guarantee range Operating voltage (V) 2.7 2.3 1.8 1.8 16.384 kHz 32 kHz 131.072 kHz 0.5 MHz 3 MHz 5 MHz 16.25 MHz PLL operation guarantee range PLL operation guarantee range Main clock operation guarantee range Source clock frequency (FSPL) Source clock frequency (FSP) • Operating voltage - Operating frequency (TA = − 40 °C to + 85 °C) • MB95F128D/F128E Sub PLL operation guarantee range Sub clock mode and watch mode operation guarantee range 3.3 3.3 Main clock mode and main PLL mode operation guarantee range Operating voltage (V) Operating voltage (V) 2.7 2.3 2.0 2.0 16.384 kHz 32 kHz 131.072 kHz 0.5 MHz 3 MHz 7.5 MHz 16.25 MHz PLL operation guarantee range PLL operation guarantee range Main clock operation guarantee range Source clock frequency (FSPL) Source clock frequency (FSP) 42 MB95120 Series • Operating voltage - Operating frequency (TA = + 5 °C to + 35 °C) • MB95FV100D-101/102 Sub PLL, Sub clock mode and watch mode operation guarantee range 3.6 3.6 FRAM, Main clock mode and main PLL mode operation guarantee range Operating voltage (V) Operating voltage (V) 3.3 2.6 2.6 16.384 kHz 32 kHz 131.072 kHz 0.5 MHz 3 MHz 10 MHz 16.25 MHz PLL operation guarantee range PLL operation guarantee range Main clock operation guarantee range Source clock frequency (FSPL) Source clock frequency (FSP) 43 MB95120 Series • Main PLL operation frequency [MHz] 16.25 16 15 ×4 12 × 2.5 Source clock frequency (Fsp) 10 ×2 ×1 7.5 6 5 3 0 3 4 4.062 5 6.4 6.5 8 8.125 10 [MHz] Machine clock frequency (FMP) 44 MB95120 Series (3) External Reset (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter RST “L” level pulse width Symbol Value Min 2 tMCLK*1 tRSTL Oscillation time of oscillator*2 + 2 tMCLK Max ⎯ ⎯ Unit ns µs Remarks At normal operating At stop mode, sub clock mode, sub sleep mode, and watch mode *1 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. *2 : Oscillation start time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of µs and several ms. In the external clock, the oscillation time is 0 ms. • At normal operating tRSTL RST 0.2 VCC 0.2 VCC • At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on RST 90% of amplitude tRSTL 0.2 VCC 0.2 VCC X0 Internal operating clock 2 tMCLK Oscillation time Oscillation stabilization wait time of oscillator Execute instruction Internal reset 45 MB95120 Series (4) Power-on Reset (AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Power supply rising time Power supply cutoff time Symbol tR tOFF Conditions ⎯ ⎯ Value Min ⎯ 1 Max 36 ⎯ Unit ms ms Waiting time until power-on Remarks tR 1.5 V tOFF VCC 0.2 V 0.2 V 0.2 V Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power supply voltages during operation, set the slope of rising within 30 mV/ms as shown below. VCC 1.5 V Limiting the slope of rising within 20 mV/ms is recommended. Hold Condition in stop mode VSS 46 MB95120 Series (5) Peripheral Input Timing (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Peripheral input “H” pulse width Peripheral input “L” pulse width Symbol tILIH tIHIL Pin name INT00 to INT07, INT10 to INT13, EC0, EC1, TI0, TRG0/ADTG, TRG1 Value Min 2 tMCLK* 2 tMCLK* Max ⎯ ⎯ Unit ns ns * : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. tILIH tIHIL INT00 to INT07, INT10 to INT13, EC0, EC1, TI0, TRG0/ADTG, TRG1 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 47 MB95120 Series (6) UART/SIO, Serial I/O Timing (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Serial clock cycle time UCK ↓ → UO time Valid UI → UCK ↑ UCK ↑ → valid UI hold time Serial clock “H” pulse width Serial clock “L” pulse width UCK ↓ → UO time Valid UI → UCK ↑ UCK ↑ → valid UI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name UCK0 UCK0, UO0 UCK0, UI0 UCK0, UI0 UCK0 UCK0 UCK0, UO0 UCK0, UI0 UCK0, UI0 External clock operation output pin : CL = 80 pF + 1TTL. Internal clock operation output pin : CL = 80 pF + 1TTL. Conditions Value Min 4 tMCLK* − 190 2 tMCLK* 2 tMCLK* 4 tMCLK* 4 tMCLK* 0 2 tMCLK* 2 tMCLK* Max ⎯ +190 ⎯ ⎯ ⎯ ⎯ 190 ⎯ ⎯ Unit ns ns ns ns ns ns ns ns ns * : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. • Internal shift clock mode tSCYC UCK0 2.4 V 0.8 V tSLOV 0.8 V UO0 2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC UI0 0.8 VCC 0.2 VCC • External shift clock mode tSLSH tSHSL 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tSLOV UCK0 UO0 2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC UI0 0.8 VCC 0.2 VCC 48 MB95120 Series (7) LIN-UART Timing Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2 (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0) (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C) Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time Serial clock “L” pulse width Serial clock “H” pulse width SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time SCK fall time SCK rise time SymPin name bol tSCYC tSLOVI tIVSHI tSHIXI tSLSH tSHSL tIVSHE tSHIXE tF tR SCK Internal clock SCK, SOT operation output pin : SCK, SIN CL = 80 pF + 1 TTL. SCK, SIN SCK SCK External clock SCK, SIN operation output pin : CL = 80 pF + 1 TTL. SCK, SIN SCK SCK t Conditions Value Min 5 tMCLK*3 −95 MCLK 3 Max ⎯ +95 ⎯ ⎯ ⎯ ⎯ 2t MCLK 3 Unit ns ns ns ns ns ns ns ns ns ns ns * + 190 0 3 tMCLK*3 − tR t MCLK 3 * + 95 tSLOVE SCK, SOT ⎯ 190 tMCLK*3 + 95 ⎯ ⎯ * + 95 ⎯ ⎯ 10 10 *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. 49 MB95120 Series • Internal shift clock mode tSCYC 2.4 V 0.8 V tSLOVI 2.4 V 0.8 V tIVSHI tSHIXI 0.8 V SCK SOT SIN 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSLSH tSHSL 0.8 VCC 0.2 VCC tR 0.8 VCC SCK 0.8 VCC 0.2 VCC tF tSLOVE 2.4 V 0.8 V tIVSHE SOT tSHIXE SIN 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 50 MB95120 Series Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2 (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0) (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C) Parameter Serial clock cycle time SCK ↑ → SOT delay time Valid SIN → SCK ↓ SCK ↓ → valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↑ → SOT delay time Valid SIN → SCK ↓ SCK ↓ → valid SIN hold time SCK fall time SCK rise time Symbol tSCYC tSHOVI tIVSLI tSLIXI tSHSL tSLSH tSHOVE tIVSLE tSLIXE tF tR Pin name SCK SCK, SOT Internal clock operation output pin : SCK, SIN CL = 80 pF + 1 TTL. SCK, SIN SCK SCK SCK, SOT External clock SCK, SIN operation output pin : SCK, SIN CL = 80 pF + 1 TTL. SCK SCK t Conditions Value Min 5 tMCLK*3 −95 MCLK 3 Max ⎯ +95 ⎯ ⎯ ⎯ ⎯ 2t MCLK 3 Unit ns ns ns ns ns ns ns ns ns ns ns * + 190 0 3 tMCLK*3 − tR tMCLK*3 + 95 ⎯ 190 tMCLK*3 + 95 ⎯ ⎯ * + 95 ⎯ ⎯ 10 10 *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. 51 MB95120 Series • Internal shift clock mode tSCYC SCK 2.4 V 0.8 V tSHOVI 2.4 V 0.8 V tIVSLI tSLIXI 2.4 V SOT SIN 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSHSL tSLSH 0.8 VCC 0.2 VCC tSHOVE 2.4 V 0.8 V tIVSLE tSLIXE tF 0.2 VCC SCK 0.2 VCC tR 0.8 VCC SOT SIN 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 52 MB95120 Series Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2 (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1) (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C) Parameter Serial clock cycle time SCK ↑ → SOT delay time Valid SIN → SCK ↓ SCK ↓ → valid SIN hold time SOT → SCK ↓ delay time Symbol tSCYC tSHOVI tIVSLI tSLIXI tSOVLI Pin name SCK SCK, SOT SCK, SIN SCK, SIN SCK, SOT Internal clock operation output pin : CL = 80 pF + 1 TTL. t Conditions Value Min 5 tMCLK*3 −95 MCLK 3 Max ⎯ +95 ⎯ ⎯ 4 tMCLK*3 Unit ns ns ns ns ns * + 190 0 ⎯ *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. tSCYC SCK 0.8 V tSOVLI 2.4 V 0.8 V tIVSLI tSLIXI 2.4 V tSHOVI 2.4 V 0.8 V 0.8 V SOT SIN 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC 53 MB95120 Series Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2 (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1) (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C) Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time SOT → SCK ↑ delay time Symbol tSCYC tSLOVI tIVSHI tSHIXI tSOVHI Pin name SCK SCK, SOT Internal clock SCK, SIN operating output pin : CL = 80 pF + 1 TTL. SCK, SIN t Conditions Value Min 5 tMCLK*3 −95 MCLK 3 Max ⎯ +95 ⎯ ⎯ 4 tMCLK*3 Unit ns ns ns ns ns * + 190 0 ⎯ SCK, SOT *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. tSCYC SCK tSOVHI 2.4 V 0.8 V tSLOVI 2.4 V 0.8 V tIVSHI tSHIXI 0.8 VCC 0.2 VCC 2.4 V 0.8 V 2.4 V SOT SIN 0.8 VCC 0.2 VCC 54 MB95120 Series (8) I2C Timing (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Value Parameter SCL clock frequency (Repeat) Start condition hold time SDA ↓ → SCL ↓ SCL clock “L” width SCL clock “H” width (Repeat) Start condition setup time SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓ ↑ Data setup time SDA ↓ ↑ → SCL ↑ Stop condition setup time SCL ↑ → SDA ↑ Bus free time between stop condition and start condition Symbol fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF Pin name SCL0 SCL0 SDA0 SCL0 SCL0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 R = 1.7 kΩ, C = 50 pF*1 Conditions Standard-mode Min 0 4.0 4.7 4.0 4.7 0 0.25 4.0 4.7 Max 100 ⎯ ⎯ ⎯ ⎯ 3.45*2 ⎯ ⎯ ⎯ Fast-mode Min 0 0.6 1.3 0.6 0.6 0 0.1 0.6 1.3 Max 400 ⎯ ⎯ ⎯ ⎯ 0.9*3 ⎯ ⎯ ⎯ kHz µs µs µs µs µs µs µs µs Unit *1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : The maximum tHD;DAT have only to be met if the device dose not stretch the “L” width (tLOW) of the SCL signal. *3 : A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. tWAKEUP SDA0 tLOW SCL0 tHD;STA tSU;DAT fSCL tSU;STA tSU;STO tHD;DAT tHIGH tHD;STA tBUF 55 MB95120 Series (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C) Parameter SCL clock “L” width SCL clock “H” width Sym- Pin bol name tLOW tHIGH SCL0 SCL0 Conditions Value*2 Min (2 + nm / 2) tMCLK − 20 (nm / 2) tMCLK − 20 Max ⎯ (nm / 2 ) tMCLK + 20 Unit ns ns Remarks Master mode Master mode Master mode Maximum value is applied when m, n = 1, 8. Otherwise, the minimum value is applied. Master mode Master mode Start condition SCL0 tHD;STA hold time SDA0 (−1 + nm / 2) tMCLK − 20 (−1 + nm) tMCLK + 20 ns Stop condition SCL0 tSU;STO setup time SDA0 Start condition SCL0 tSU;STA setup time SDA0 Bus free time between stop condition and start condition tBUF SCL0 SDA0 SCL0 SDA0 R = 1.7 kΩ, C = 50 pF*1 (1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20 (1 + nm / 2) tMCLK + 20 ns ns (2 nm + 4) tMCLK − 20 ⎯ ns Data hold time tHD;DAT 3 tMCLK − 20 ⎯ ns Master mode Master mode When assuming that “L” of SCL is not extended, the minimum value is applied to first bit of continuous data. Otherwise, the maximum value is applied. Minimum value is applied to interrupt at 9th SCL↓. Maximum value is applied to interrupt at 8th SCL↓. At reception At reception Undetected when 1 tMCLK is used at reception (Continued) Data setup time tSU;DAT SCL0 SDA0 (−2 + nm / 2) tMCLK − 20 (−1 + nm / 2) tMCLK + 20 ns Setup time between clearing interrupt and SCL rising SCL clock “L” width SCL clock “H” width tSU;INT SCL0 (nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20 ns tLOW tHIGH SCL0 SCL0 4 tMCLK − 20 4 tMCLK − 20 2 tMCLK − 20 ⎯ ⎯ ⎯ ns ns ns Start condition SCL0 tHD;STA detection SDA0 56 MB95120 Series (Continued) Sym- Pin bol name tSU;STO SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 R = 1.7 kΩ, 1 SCL0 C = 50 pF* SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 Conditions (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C) Value*2 Min 2 tMCLK − 20 Parameter Stop condition detection Restart condition detection condition Bus free time Data hold time Data setup time Data hold time Data setup time SDA↓→SCL↑ (at wakeup function) Max ⎯ Unit Remarks Undetected when 1 tMCLK is used at reception Undetected when 1 tMCLK is used at reception At reception At slave transmission mode At slave transmission mode At reception At reception ns tSU;STA 2 tMCLK − 20 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ns tBUF tHD;DAT tSU;DAT tHD;DAT tSU;DAT tWAKEUP 2 tMCLK − 20 2 tMCLK − 20 tLOW − 3 tMCLK − 20 0 tMCLK − 20 Oscillation stabilization wait time + 2 tMCLK − 20 ns ns ns ns ns ⎯ ns *1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : • • • • Refer to “ (2) Source Clock/Machine Clock” for tMCLK. m is CS4 bit and CS3 bit (bit 4 and bit 3) of I2C clock control register (ICCR) . n is CS2 bit to CS0 bit (bit 2 to bit 0) of I2C clock control register (ICCR) . Actual timing of I2C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of ICCR0 register. • Standard-mode : m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz. Setting of m and n determines the machine clock that can be used below. (m, n) = (1, 8) : 0.9 MHz < tMCLK ≤ 1 MHz (m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz (m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz (m, n) = (1, 98) : 0.9 MHz < tMCLK ≤ 10 MHz • Fast-mode : m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz. Setting of m and n determines the machine clock that can be used below. (m, n) = (1, 8) : 3.3 MHz < tMCLK ≤ 4 MHz (m, n) = (1, 22) , (5, 4) : 3.3 MHz < tMCLK ≤ 8 MHz (m, n) = (6, 4) : 3.3 MHz < tMCLK ≤ 10 MHz 57 MB95120 Series 5. A/D Converter (1) A/D Converter Electrical Characteristics (AVcc = Vcc = 1.8 V to 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Resolution Total error Linearity error Differential linear error ⎯ Symbol Value Min ⎯ − 3.0 − 2.5 − 1.9 Typ ⎯ ⎯ ⎯ ⎯ Max 10 + 3.0 + 2.5 + 1.9 Unit bit LSB LSB LSB V V V V µs µs 2.7 V ≤ AVcc ≤ 3.3 V 1.8 V ≤ AVcc < 2.7 V 2.7 V ≤ AVcc ≤ 3.3 V 1.8 V ≤ AVcc < 2.7 V 2.7 V ≤ AVcc ≤ 3.3 V 1.8 V ≤ AVcc < 2.7 V 2.7 V ≤ AVcc ≤ 3.3 V, At external impedance < 1.8 kΩ 1.8 V ≤ AVcc < 2.7 V, At external impedance < 14.8 kΩ Remarks AVss − 1.5 LSB AVss + 0.5 LSB AVss + 2.5 LSB Zero transition voltage VOT AVss − 0.5 LSB AVss + 1.5 LSB AVss + 3.5 LSB AVR − 3.5 LSB AVR − 1.5 LSB AVR + 0.5 LSB VFST AVR − 2.5 LSB AVR − 0.5 LSB AVR + 1.5 LSB 0.6 Compare time ⎯ 20 ⎯ 140 ⎯ 140 Full-scale transition voltage 0.4 Sampling time ⎯ 30 ⎯ ∞ µs ⎯ ∞ +0.3 AVR AVcc 600 µs Analog input current Analog input voltage Reference voltage IAIN VAIN ⎯ IR −0.3 AVss AVss + 1.8 ⎯ ⎯ ⎯ ⎯ ⎯ 400 ⎯ µA V V µA µA AVR pin AVR pin, During A/D operation AVR pin, At stop mode Reference voltage supply current IRH 5 58 MB95120 Series (2) Notes on Using A/D Converter • About the external impedance of analog input and its sampling time A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. Therefore to satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. • Analog input equivalent circuit R Analog input C Comparator During sampling : ON 2.7 V ≤ AVcc ≤ 3.6 V 1.8 V ≤ AVcc < 2.7 V Note : The values are reference values. R 1.7 kΩ (Max) 84 kΩ (Max) C 14.5 pF (Max) 25.2 pF (Max) • The relationship between external impedance and minimum sampling time (External impedance = 0 kΩ to 100 kΩ) AVCC ≥ 2.7 V 100 90 80 70 60 50 40 30 20 10 0 0 5 10 15 (External impedance = 0 kΩ to 20 kΩ) AVCC ≥ 2.7 V 20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 External impedance [kΩ] AVCC ≥ 1.8 V 20 25 30 35 40 External impedance [kΩ] Minimum sampling time [µs] Minimum sampling time [µs] • About errors As |AVR − AVSS| becomes smaller, values of relative errors grow larger. 59 MB95120 Series (3) Definition of A/D Converter Terms • Resolution The level of analog variation that can be distinguished by the A/D converter. When the number of bits is 10, analog voltage can be divided into 210 = 1024. • Linearity error (unit : LSB) The deviation between the value along a straight line connecting the zero transition point (“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point (“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained. • Differential linear error (Unit : LSB) Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. • Total error (unit: LSB) Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error, linearity error, quantum error, and noise. Ideal I/O characteristics VFST Total error 3FFH 3FEH 3FFH 3FEH 1.5 LSB Actual conversion characteristic {1 LSB × (N − 1) + 0.5 LSB} Digital output Digital output 3FDH 3FDH 004H 003H 002H 001H 0.5 LSB AVSS AVR VOT 1 LSB 004H 003H 002H 001H AVSS AVR VNT Actual conversion characteristic Ideal characteristics Analog input 1 LSB = AVR − AVSS 1024 (V) Analog input Total error of VNT − {1 LSB × (N − 1) + 0.5 LSB} = [LSB] digital output N 1 LSB N : A/D converter digital output value VNT : A voltage at which digital output transits from (N - 1) to N. (Continued) 60 MB95120 Series (Continued) Zero transition error 004H Actual conversion characteristic Full-scale transition error Ideal characteristics 3FFH Digital output 003H Ideal characteristics Digital output Actual conversion characteristic 3FEH VFST 002H Actual conversion characteristic 3FDH (measurement value) 001H VOT (measurement value) 3FCH Actual conversion characteristic AVSS AVR AVSS AVR Analog input Analog input Linearity error 3FFH 3FEH 3FDH Actual conversion characteristic Differential linear error Ideal characteristics N+1H {1 LSB × N + VOT} VFST (measurement value) Actual conversion characteristic Digital output Digital output V (N+1)T NH VNT 004H 003H 002H 001H VOT (measurement value) Actual conversion characteristic Ideal characteristics N-1H VNT Actual conversion characteristic N-2H AVSS AVR AVSS Analog input Linear error in = VNT − {1 LSB × N + VOT} 1 LSB digital output N Analog input AVR Differential linear error = in digital output N V (N + 1) T − VNT 1 LSB −1 N : A/D Converter digital output value VNT : A voltage at which digital output transits from (N − 1) to N. VOT (Ideal value) = AVSS + 0.5 LSB [V] VFST (Ideal value) = AVR − 1.5 LSB [V] 61 MB95120 Series 6. Flash Memory Program/Erase Characteristics Parameter Sector erase time (4 Kbytes sector) Sector erase time (16 Kbytes sector) Byte programming time Program/erase cycle Power supply voltage at program/erase Flash memory data retention time Value Min ⎯ ⎯ ⎯ 10000 2.7 20*3 Typ 0.2*1 0.5*1 32 ⎯ ⎯ ⎯ Max 3.0*2 12.0*2 3600 ⎯ 3.3 ⎯ Unit s s µs cycle V year Average TA = +85 °C Remarks Excludes 00H programming prior erasure. Excludes 00H programming prior erasure. Excludes system-level overhead. *1 : TA = + 25 °C, VCC = 3.0 V, 10000 cycles *2 : TA = + 85 °C, VCC = 2.7 V, 10000 cycles *3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at +85 °C) . 62 MB95120 Series ■ MASK OPTION Part number No. Specifying procedure MB95F128D MB95F128E MB95FV100D-101 Setting disabled MB95FV100D-102 Setting disabled Setting disabled 1 Clock mode select • Single-system clock mode • Dual-system clock mode LCDC Booster circuit select • Internal division resistance • Booster circuit Low voltage detection reset* • With low voltage detection reset • Without low voltage detection reset Clock supervisor* • With clock supervisor • Without clock supervisor Oscillation stabilization wait time Dual-system clock mode internal division resistance No Changing by the switch on MCU board internal division resistance No Booster circuit 2 Booster circuit 3 4 No Fixed to oscillation stabilization wait time of (214−2) /FCH No 5 Fixed to oscillation stabilization wait time of (214−2) /FCH * : Low voltage detection reset and clock supervisor are options of 5-V products. 63 MB95120 Series ■ ORDERING INFORMATION Part number MB95F128DPMC MB95F128EPMC MB95F128DPF MB95F128EPF MB2146-301A (MB95FV100D-101PBT) MB2146-302A (MB95FV100D-102PBT) Package 100-pin plastic LQFP (FPT-100P-M20) 100-pin plastic QFP (FPT-100P-M06) Remarks ( MCU board 224-pin plastic PFBGA (BGA-224P-M08) ) Included LCDC internal division resistance Included LCDC booster 64 MB95120 Series ■ PACKAGE DIMENSIONS 100-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.50 mm 14.0 mm × 14.0 mm Gullwing Plastic mold 1.70 mm Max 0.65 g P-LFQFP100-14×14-0.50 (FPT-100P-M20) Code (Reference) 100-pin plastic LQFP (FPT-100P-M20) 16.00±0.20(.630±.008)SQ Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. * 14.00±0.10(.551±.004)SQ 75 51 76 50 0.08(.003) Details of "A" part INDEX 1.50 –0.10 .059 –.004 (Mounting height) 26 +0.20 +.008 100 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) 0˚~8˚ "A" (0.50(.020)) 0.60±0.15 (.024±.006) 1 25 0.50(.020) 0.20±0.05 (.008±.002) 0.08(.003) M 0.145±0.055 (.0057±.0022) C 2005 FUJITSU LIMITED F100031S-c-2-1 Dimensions in mm (inches). Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html (Continued) 65 MB95120 Series (Continued) 100-pin plastic QFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Code (Reference) 0.65 mm 14.00 × 20.00 mm Gullwing Plastic mold 3.35 mm MAX P-QFP100-14×20-0.65 (FPT-100P-M06) 100-pin plastic QFP (FPT-100P-M06) 23.90±0.40(.941±.016) * 20.00±0.20(.787±.008) 80 51 Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 81 50 0.10(.004) 17.90±0.40 (.705±.016) *14.00±0.20 (.551±.008) INDEX Details of "A" part 100 31 1 30 0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8˚ 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.25±0.20 (.010±.008) (Stand off) 0.65(.026) 0.32±0.05 (.013±.002) 0.13(.005) M "A" C 2002 FUJITSU LIMITED F100008S-c-5-5 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 66 MB95120 Series The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. 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Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept. F0701