MB95F133MBSPF

FUJITSU SEMICONDUCTOR DATA SHEET DS07-12621-1E 8-bit Microcontrollers CMOS F2MC-8FX MB95130MB Series MB95136MB/F133MBS/F133NBS/F133JBS/F134MBS/F134NBS/F134JBS/ MB95F136MBS/F136NBS/F136JBS/F133MBW/F133NBW/F133JBW/F134MBW/ MB95F134NBW/F134JBW/F136MBW/F136NBW/F136JBW/FV100D-103 ■ DESCRIPTION The MB95130MB series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions. Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller. ■ FEATURES • F2MC-8FX CPU core Instruction set optimized for controllers • Multiplication and division instructions • 16-bit arithmetic operations • Bit test branch instruction • Bit manipulation instructions etc. • Clock • Main clock • Main PLL clock • Sub clock (for dual clock product) • Sub PLL clock (for dual clock product) (Continued) Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development. Copyright©2007 FUJITSU LIMITED All rights reserved MB95130MB Series (Continued) • Timer • 8/16-bit compound timer × 1 channel • 8/16-bit PPG × 1 channel • 16-bit PPG × 1 channel • Timebase timer × 1 channel • Watch prescaler (for dual clock product) × 1 channel • LIN-UART × 1 channel • LIN function, Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable • Full duplex double buffer • UART/SIO × 1 channel • Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable • Full duplex double buffer • External interrupt × 8 channels • Interrupt by edge detection (rising, falling, or both edges can be selected) • Can be used to recover from low-power consumption (standby) modes. • 8/10-bit A/D converter × 8 channels • 8-bit or 10-bit resolution can be selected. • Low-power consumption (standby) mode • Stop mode • Sleep mode • Watch mode (for dual clock product) • Timebase timer mode • I/O port • The number of maximum ports • Single clock product : 20 ports • Dual clock product : 18 ports • Configuration • General-purpose I/O ports (COMS) : Single clock product : 20 ports Dual clock product : 18 ports • Programmable input voltage levels of port Automotive input level / CMOS input level / hysteresis input level • Flash memory security function Protects the content of Flash memory (Flash memory device only) 2 MB95130MB Series ■ MEMORY LINEUP Flash memory MB95F133MBS/F133NBS/F133JBS MB95F133MBW/F133NBW/F133JBW MB95F134MBS/F134NBS/F134JBS MB95F134MBW/F134NBW/F134JBW MB95F136MBS/F136NBS/F136JBS MB95F136MBW/F136NBW/F136JBW 8 Kbytes 16 Kbytes 32 Kbytes RAM 256 bytes 512 bytes 1 Kbyte 3 MB95130MB Series ■ PRODUCT LINEUP Part number MB95136MB Parameter MB95 F133MBS/ F134MBS/ F136MBS MB95 F133NBS/ F134NBS/ F136NBS MB95 F133MBW/ F134MBW/ F136MBW MB95 F133NBW/ F134NBW/ F136NBW MB95 F133JBS/ F134JBS/ F136JBS MB95 F133JBW/ F134JBW/ F136JBW Type ROM capacity*1 RAM capacity*1 Reset output Clock system Option*2 Low voltage detection reset Clock supervisor MASK ROM product Flash memory product 32 Kbytes (Max) 1 Kbyte (Max) Yes No Dual clock Single clock Dual clock Selectable single/dual clock*3 Yes/No Yes/No Single clock No Yes No No Yes Yes Number of basic instructions : 136 Instruction bit length : 8 bits Instruction length : 1 to 3 bytes CPU functions Data bit length : 1, 8, and 16 bits Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 MHz) Interrupt processing time : 0.6 µs (at machine clock frequency 16.25 MHz) • Single clock product : 20 ports General• Dual clock product : 18 ports purpose Programmable input voltage levels of port : I/O port Automotive input level / CMOS input level / hysteresis input level Timebase timer Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz) (1 channel) Reset generated cycle Watchdog At main oscillation clock 10 MHz : Min 105 ms timer At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms Wild register Capable of replacing 3 bytes of ROM data Data transfer capable in UART/SIO Full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate generator UART/SIO NRZ type transfer format, error detected function (1 channel) LSB-first or MSB-first can be selected. Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable Dedicated reload timer allowing a wide range of communication speeds to be set. LIN-UART Full duplex double buffer. (1 channel) Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable LIN functions available as the LIN master or LIN slave. 8/10-bit A/D 8-bit or 10-bit resolution can be selected. converter (8 channels) Peripheral functions (Continued) 4 MB95130MB Series (Continued) Part number MB95136MB Parameter MB95 F133MBS/ F134MBS/ F136MBS MB95 F133NBS/ F134NBS/ F136NBS MB95 F133MBW/ F134MBW/ F136MBW MB95 F133NBW/ F134NBW/ F136NBW MB95 F133JBS/ F134JBS/ F136JBS MB95 F133JBW/ F134JBW/ F136JBW 8/16-bit Each channel of the timer can be used as “8-bit timer x 2 channels” or “16-bit timer x 1 channel”. compound Built-in timer function, PWC function, PWM function, capture function and square wave-form output timer Count clock: 7 internal clocks and external clock can be selected. (1 channel) PWM mode or one-shot mode can be selected. 16-bit PPG Counter operating clock: Eight selectable clock sources (1 channel) Support for external trigger start 8/16-bit PPG Each channel of the PPG can be used as “8-bit PPG x 2 channels” or “16-bit PPG x 1 channel”. (1 channel) Counter operating clock: Eight selectable clock sources Watch counter Count clock : Four selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s) (for dual Counter value can be set from 0 to 63. (Capable of counting for 1 minute when selecting clock clock source 1 second and setting counter value to 60) product) (1 channel) Watch prescaler (for dual Four selectable interval times (125 ms, 250 ms, 500 ms, or 1 s) clock product) (1 channel) External Interrupt by edge detection (rising, falling, or both edges can be selected.) interrupt Can be used to recover from standby modes. (8 channels) Supports automatic programming, Embedded AlgorithmTM *4 Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of write/erase cycles (Minimum) : 10000 times Flash memory Data retention time : 20 years Erase can be performed on each block Block protection with external programming voltage Flash Security Feature for protecting the content of the Flash (MB95F136MBS/F136NBS/F136JBS/F136MBW/F136NBW/F136JBW) Standby mode Sleep, stop, watch (for dual clock product), and timebase timer *1 : For ROM capacity and RAM capacity, refer to “■ MEMORY LINEUP”. *2 : For details of option, refer to “■ MASK OPTION”. *3 : Specify clock mode when ordering MASK ROM. *4 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc. Note : Part number of evaluation product in MB95130MB series is MB95FV100D-103. When using it, the MCU board (MB2146-303A) is required. Peripheral functions 5 MB95130MB Series ■ OSCILLATION STABILIZATION WAIT TIME The initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. The maximum value is shown below. Oscillation stabilization wait time (2 -2) /FCH 14 Remarks Approx. 4.10 ms (at main oscillation clock 4 MHz) ■ PACKAGES AND CORRESPONDING PRODUCTS Part number MB95F133MBS MB95F133NBS MB95F134MBS MB95F134NBS MB95F136MBS MB95F136NBS MB95F133JBS MB95F134JBS MB95F136JBS MB95F133MBW MB95F133NBW MB95F134MBW MB95F134NBW MB95F136MBW MB95F136NBW MB95F133JBW MB95F134JBW MB95F136JBW MB95136MB MB95FV100D-103 Package FPT-28P-M17 FPT-30P-M02 BGA-224P-M08 : Available : Unavailable 6 MB95130MB Series ■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS • Notes on using evaluation products The Evaluation product has not only the functions of the MB95130MB series but also those of other products to support software development for multiple series and models of the F2MC-8FX. The I/O addresses for peripheral resources not used by the MB95130MB series are therefore access-barred. Read/write access to those accessbarred addresses may cause peripheral resources supposed to be unused to operate, resulting in unexpected malfunctions of hardware or software. Particularly, do not use word access to an odd-numbered-byte address in the prohibited areas (If such access is used, the address may be read or written unexpectedly) . Also, as the read values of prohibited addresses on the evaluation product are different to the values on the flash memory and mask ROM products, do not use these values in the software processing. The Evaluation product does not support the functions of some bits in single-byte registers. Read/write access to these bits does not cause hardware malfunctions. No particular precautions are required to the flash memory and mask ROM products, as they have the identical read/write operation to the evaluation products. • Difference of memory spaces If the amount of memory on the Evaluation product is different from that of the Flash memory or MASK ROM product, carefully check the difference in the amount of memory from the model to be actually used when developing software. For details of memory space, refer to “■ CPU CORE”. • Current consumption • The current consumption of Flash memory product is greater than for MASK ROM product. • For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”. • Package For details of information on each package, refer to “■ PACKAGES AND CORRESPONDING PRODUCTS” and “■ PACKAGE DIMENSION”. • Operating voltage The operating voltage is different among the Evaluation, Flash memory, and MASK ROM products. For details of the operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”. • Difference MOD Pins A pull-down resistor is provided for the MOD pin of the MASK ROM product. 7 MB95130MB Series ■ PIN ASSIGNMENT (TOP VIEW) P16 PF0 PF1 MOD X0 X1 VSS VCC C PG2/X1A* PG1/X0A* RST AVCC AVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 P15 P14/PPG0 P13/TRG0/ADTG P12/UCK0/EC0 P11/UO0 P10/UI0 P07/INT07/AN07 P06/INT06/AN06/TO01 P05/INT05/AN05/TO00 P04/INT04/AN04/SIN P03/INT03/AN03/SOT P02/INT02/AN02/SCK P01/INT01/AN01/PPG01 P00/INT00/AN00/PPG00 SOP-28 22 21 20 19 18 17 16 15 (FPT-28P-M17) * : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin. 8 MB95130MB Series (TOP VIEW) P16 PF0 PF1 MOD X0 X1 VSS VCC C PG2/X1A* PG1/X0A* RST AVCC AVSS P00/INT00/AN00/PPG00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P15 P14/PPG0 P13/TRG0/ADTG P12/UCK0/EC0 NC P11/UO0 P10/UI0 P07/INT07/AN07 P06/INT06/AN06/TO01 P05/INT05/AN05/TO00 P04/INT04/AN04/SIN NC P03/INT03/AN03/SOT P02/INT02/AN02/SCK P01/INT01/AN01/PPG01 SSOP-30 (FPT-30P-M02) * : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin. 9 MB95130MB Series ■ PIN DESCRIPTION Pin no. SSOP*1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SOP*2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin name P16 PF0 PF1 MOD X0 X1 VSS VCC C PG2/X1A H/A PG1/X0A RST AVCC AVSS P00/INT00/ AN00/ PPG00 P01/INT01/ AN01/ PPG01 P02/INT02/ AN02/SCK P03/INT03/ AN03/SOT P04/INT04/ AN04/SIN P05/INT05/ AN05/TO00 P06/INT06/ AN06/TO01 P07/INT07/ AN07 D B’ ⎯ ⎯ I/O circuit type*3 H K B A ⎯ ⎯ ⎯ General-purpose I/O port General-purpose I/O port for large current Operating mode designation pin Main clock oscillation input pin Main clock oscillation input/output pin Power supply pin (GND) Power supply pin Capacity connection pin Single clock product is general-purpose port (PG2) . Dual clock product is sub clock input/output oscillation pin (32 kHz) . Single clock product is general-purpose port (PG1) . Dual clock product is sub clock input oscillation pin (32 kHz) . Reset pin A/D converter power supply pin A/D converter power supply pin (GND) General-purpose I/O port Shared with external interrupt input (INT00), A/D converter analog input (AN00) and 8/16-bit PPG ch.0 output (PPG00). General-purpose I/O port Shared with external interrupt input (INT01), A/D converter analog input (AN01) and 8/16-bit PPG ch.0 output (PPG01). General-purpose I/O port Shared with external interrupt input (INT02), A/D converter analog input (AN02) and LIN-UART clock I/O (SCK). General-purpose I/O port Shared with external interrupt input (INT03), A/D converter analog input (AN03) and LIN-UART data output (SOT). E General-purpose I/O port Shared with external interrupt input (INT04), A/D converter analog input (AN04) and LIN-UART data input (SIN). General-purpose I/O port Shared with external interrupt input (INT05 & INT06), A/D converter analog input (AN05 & AN06) and 8/16-bit compound timer ch.0 output (TO00 & TO01). General-purpose I/O port Shared with external interrupt input (INT07) and A/D converter analog input (AN07). (Continued) 10 Function 16 16 D 17 17 18 18 20 19 21 22 20 21 23 22 MB95130MB Series (Continued) Pin no. SSOP*1 24 25 SOP*2 23 24 Pin name P10/UIO P11/UO0 P12/UCK0/ EC0 P13/TRG0/ ADTG P14/PPG0 P15 NC ⎯ H I/O circuit type*3 G Function General-purpose I/O port Shared with UART/SIO ch.0 data input (UI0) General-purpose I/O port Shared with UART/SIO ch.0 data output (UO0) General-purpose I/O port Shared with UART/SIO ch.0 clock I/O (UCK0) and 8/16-bit compound timer ch.0 clock input (EC0) General-purpose I/O port Shared with 16-bit PPG ch.0 trigger input (TRG0) and A/D converter trigger input (ADTG) General-purpose I/O port Shared with 16-bit PPG ch.0 output (PPG0) General-purpose I/O port Internally connected pins. Be sure to leave it open. 27 25 28 26 29 30 19,26 27 28 ⎯ *1 : FPT-30P-M02 *2 : FPT-28P-M17 *3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”. 11 MB95130MB Series ■ I/O CIRCUIT TYPE Type Circuit Remarks • Oscillation circuit • High-speed side Feedback resistance: approx. 1 MΩ • Low-speed side Feedback resistance: approx. 10 MΩ X1 (X1A) A X 0 (X0A) N-ch Clock input Standby control Only for input • Hysteresis input only for MASK ROM product • Pull-down resistor available only to MASK ROM product • Hysteresis input only for MASK ROM product • Reset output Mode input B R Reset input B’ N-ch Reset output R P-ch P-ch • • Pull-up control • • Digital output • Digital output CMOS output Hysteresis input Analog input Pull-up control available Automotive input N-ch D Analog input Automotive input A/D control Standby control External interrupt control Hysteresis input (Continued) 12 MB95130MB Series (Continued) Type Circuit • • Pull-up control • • Digital output • Digital output • Analog input CMOS input Hysteresis input Remarks CMOS output CMOS input Hysteresis input Analog input Pull-up control available Automotive input R P-ch P-ch N-ch E A/D control Standby control External interrupt control Automotive input R P-ch P-ch Pull-up control Digital output Digital output N-ch • • • • • CMOS output CMOS input Hysteresis input Pull-up control available Automotive input G CMOS input Hysteresis input Standby control Automotive input • • • • CMOS output Hysteresis input Pull-up control available Automotive input R P-ch P-ch Pull-up control Digital output Digital output N-ch H Hysteresis input Standby control P-ch Automotive input • CMOS output • Hysteresis input • Automotive input Digital output Digital output Hysteresis input K N-ch Standby control Automotive input 13 MB95130MB Series ■ HANDLING DEVICES • Preventing latch-up Care must be taken to ensure that maximum voltage ratings are not exceeded when the devices are used. Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-withstand voltage pins or if voltage higher than the rating voltage is applied between VCC pin and VSS pin. When latch-up occurs, power supply current increases rapidly and might thermally damage elements. Also, take care to prevent the analog power supply voltage (AVCC) and analog input voltage from exceeding the digital power supply voltage (VCC) when the analog system power supply is turned on or off. • Stable supply voltage Supply voltage should be stabilized. A sudden change in power supply voltage may cause a malfunction even within the guaranteed operating range of the VCC power supply voltage. For stabilization, in principle, keep the variation in VCC ripple (p-p value) in a commercial frequency range (50 / 60 Hz) not to exceed 10% of the standard VCC value and suppress the voltage variation so that the transient variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched. • Precautions for use of external clock Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from the sub clock mode or stop mode. PIN CONNECTION • Treatment of unused pins Leaving unused input pins unconnected can cause abnormal operation or latch-up, leading to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/output pins may be set to the output mode and left open, or set to the input mode and treated the same as unused input pins. If there is any unused output pin, make it open. • Treatment of power supply pins on A/D converter Connect to be AVCC = VCC and AVSS = VSS even if the A/D converter is not in use. Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 µF ceramic capacitor as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device. • Power Supply Pins In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, all the pins must be connected to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS pins near this device. • Mode pin (MOD) Connect the mode pin directly to VCC or VSS pins. To prevent the device unintentionally entering the test mode due to noise, lay out the printed circuit board so as to minimize the distance from the mode pins to VCC or VSS pins and to provide a low-impedance connection. 14 MB95130MB Series Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC pin must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the diagram below. • C Pin Connection Diagram C CS • Analog power supply Always set the same potential to AVCC and VCC. When VCC > AVCC, the current may flow through the AN00 to AN07 pins. • NC pins Any pins marked “NC”(not connected) must be left open. 15 MB95130MB Series ■ PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL PROGRAMMER • Supported parallel programmers and adapters The following table lists supported parallel programmers and adapters. Package Applicable adapter model FPT-28P-M17 FPT-30P-M02 TEF110-95F136HSPF TEF110-95F136MB Parallel programmers AF9708 (Since Rev 02.43E ) AF9709/B (Since Rev 02.43E ) Note : For information about applicable adapter models and parallel programmers, contact the following: Flash Support Group, Inc. TEL: +81-53-428-8380 • Sector configuration The following table shows sector-specific addresses for data access by CPU and by the parallel programmer. • MB95F136MBS/F136NBS/F136MBW/F136NBW/F136JBS/F136JBW (32 Kbytes) Flash memory 32 Kbytes FFFFH 1FFFFH *: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer programs data into Flash memory. These programmer addresses are used for the parallel programmer to program or erase data in Flash memory. • Programming method 1) Set the type code of the parallel programmer to “17237”. 2) Load program data to programmer addresses 18000H to 1FFFFH. 3) Write data with the parallel programmer. CPU address 8000H Programmer address* 18000H • MB95F134MBS/F134NBS/F134JBS/F134MBW/F134NBW/F134JBW (16 Kbytes) Flash memory 16 Kbytes FFFFH 1FFFFH *: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer programs data into Flash memory. These programmer addresses are used for the parallel programmer to program or erase data in Flash memory. • Programming method 1) Set the type code of the parallel programmer to “17237”. 2) Load program data to programmer addresses 1C000H to 1FFFFH. 3) Write data with the parallel programmer. CPU address C000H Programmer address* 1C000H 16 MB95130MB Series • MB95F133MBS/F133NBS/F133JBS/F133MBW/F133NBW/F133JBW (8 Kbytes) Flash memory 8 Kbytes FFFFH 1FFFFH *: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer programs data into Flash memory. These programmer addresses are used for the parallel programmer to program or erase data in Flash memory. CPU address E000H Programmer address* 1E000H • Programming method 1) Set the type code of the parallel programmer to “17237”. 2) Load program data to programmer addresses 1E000H to 1FFFFH. 3) Write data with the parallel programmer. 17 MB95130MB Series ■ BLOCK DIAGRAM F2MC-8FX CPU RST X0/X1 PG2/(X1A)* PG1/(X0A)* Reset control Clock control Watch counter Watch prescaler ROM 32 Kbytes RAM 1 Kbyte Interrupt control Wild register Internal bus P00/INT00 to P07/INT07 P10/U10 P11/UO0 P12/UCK0 P13/TRG0/ADTG P14/PPG0 P15/P16 P00/AN00 to P07/AN07 AVCC AVSS External interrupt 8 channels 8/16-bit PPG 2 channels LIN-UART 1 channel (P00/PPG00) (P01/PPG01) (P02/SCK) (P03/SOT) (P04/SIN) (P05/TO00) (P06/TO01) (P12/EC0) PF0/PF1 UART/SIO 1 channel 16-bit PPG 1 channel 8/10-bit A/D converter 8 channels Port 8/16-bit compound timer 1 channel Port Other pins MOD, VCC, VSS, C *: Single clock product is a general-purpose port, and dual clock product is a sub clock oscillation pin. 18 MB95130MB Series ■ CPU CORE 1. Memory Space Memory space of the MB95130MB series is 64 Kbytes and consists of I/O area, data area, and program area. The memory space includes special-purpose areas such as the general-purpose registers and vector table. Memory map of the MB95130MB series is shown below. • Memory Map MB95136MB 0000H I/O 0080H 0100H 0200H 0480H 0F80H Extended I/O 1000H RAM 1 Kbyte Register MB95F133MBS/F133NBS/F133JBS MB95F134MBS/F134NBS/F134JBS MB95F136MBS/F136NBS/F136JBS MB95F133MBW/F133NBW/F133JBW MB95F134MBW/F134NBW/F134JBW MB95F136MBW/F136NBW/F136JBW 0000H I/O 0080H RAM 0000H MB95FV100D-103 I/O 0080H RAM 3.75 Kbytes 0100H Register 0200H Address #1 0100H Register 0200H Access prohibited Access prohibited 0F80H Extended I/O Extended I/O 1000H 0F80H 1000H Access prohibited 8000H MASK ROM 32 Kbytes FFFFH FFFFH Address #2 Access prohibited Flash memory 60 Kbytes Flash memory FFFFH Flash memory MB95F133MBS/F133NBS/F133JBS MB95F133MBW/F133NBW/F133JBW MB95F134MBS/F134NBS/F134JBS MB95F134MBW/F134NBW/F134JBW MB95F136MBS/F136NBS/F136JBS MB95F136MBW/F136NBW/F136JBW 8 Kbytes 16 Kbytes 32 Kbytes RAM 256 bytes 512 bytes 1 Kbyte Address #1 0180H 0280H 0480H Address #2 E000H C000H 8000H 19 MB95130MB Series 2. Register The MB95130MB series has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The dedicated registers are as include: Program counter (PC) Accumulator (A) Temporary accumulator (T) Index register (IX) Extra pointer (EP) Stack pointer (SP) Program status (PS) : A 16-bit register to indicate locations where instructions are stored. : A 16-bit register for temporary storage of arithmetic operations. In the case of an 8-bit data processing instruction, the lower 1-byte is used. : A 16-bit register which performs arithmetic operations with the accumulator. In the case of an 8-bit data processing instruction, the lower 1-byte is used. : A 16-bit register for index modification : A 16-bit pointer to point to a memory address. : A 16-bit register to indicate a stack area. : A 16-bit register for storing a register bank pointer, a direct bank pointer, and a condition code register 16 bits PC AH TH IX EP SP PS AL TL Initial Value : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status FFFDH 0000H 0000H 0000H 0000H 0000H 0030H The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer (DP) and the lower 8 bits for use as a condition code register (CCR). (Refer to the diagram below.) • Structure of the program status bit15 bit14 bit13 bit12 bit11 bit10 PS R4 R3 R2 R1 R0 DP2 bit9 DP1 bit8 DP0 bit7 H bit6 I bit5 IL1 bit4 IL0 bit3 N bit2 Z bit1 V bit0 C RP DP CCR 20 MB95130MB Series The RP indicates the address of the register bank currently being used. The relationship between the content of RP and the real address conforms to the conversion rule illustrated below: • Rule for Conversion of Actual Addresses in the General-purpose Register Area RP upper “0” “0” “0” “0” “0” “0” “0” “1” A8 R4 A7 R3 A6 R2 A5 R1 A4 R0 A3 OP code lower b2 A2 b1 A1 b0 A0 Generated address A15 A14 A13 A12 A11 A10 A9 The DP specifies the area for mapping instructions (16 different types of instructions such as MOV A and dir) using direct addresses to 0080H to 00FFH. Direct bank pointer (DP2 to DP0) Specified address area Mapping area XXXB (no effect to mapping) 000B (initial value) 001B 010B 011B 100B 101B 110B 111B 0080H to 00FFH 0000H to 007FH 0000H to 007FH (without mapping) 0080H to 00FFH (without mapping) 0100H to 017FH 0180H to 01FFH 0200H to 027FH 0280H to 02FFH 0300H to 037FH 0380H to 03FFH 0400H to 047FH The CCR consists of the bits indicating arithmetic operation results or transfer data content and the bits that control CPU operations at interrupt. H flag : Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. This flag is for decimal adjustment instructions. I flag : Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”. The flag is cleared to “0” when reset. IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level is higher than the value indicated by these bits. IL1 0 0 1 1 N flag Z flag V flag C flag IL0 0 1 0 1 Interrupt level 0 1 2 3 Low (no interruption) Priority High : Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the bit is set to “0”. : Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise. : Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0” otherwise. : Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. Set to the shift-out value in the case of a shift instruction. 21 MB95130MB Series The following general-purpose registers are provided: General-purpose registers: 8-bit data storage registers The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8 registers. Up to a total of 32 banks can be used on the MB95130MB series. The bank currently in use is specified by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0) to general-purpose register 7 (R7). • Register Bank Configuration 8-bit 1F8H This address = 0100H + 8 × (RP) Address 100H R0 R1 R2 R3 R4 R5 107H R6 R7 Bank 0 R0 R0 R1 R2 R3 R4 R5 R6 R7 R1 R2 R3 R4 R5 R6 1FFH R7 Bank 31 32 banks 32 banks (RAM area) The number of banks is limited by the usable RAM capacitance. Memory area 22 MB95130MB Series ■ I/O MAP Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH to 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH to 0034H 0035H 0036H 0037H 0038H, 0039H 003AH 003BH 003CH to 0041H 0042H 0043H Register abbreviation PDR0 DDR0 PDR1 DDR1 ⎯ WATR PLLC SYCC STBC RSRR TBTC WPCR WDTC ⎯ PDRF DDRF PDRG DDRG PUL0 PUL1 ⎯ PULG T01CR1 T00CR1 ⎯ PC01 PC00 ⎯ PCNTH0 PCNTL0 Register name Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register (Disabled) Oscillation stabilization wait time setting register PLL control register System clock control register Standby control register Reset source register Timebase timer control register Watch prescaler control register Watchdog timer control register (Disabled) Port F data register Port F direction register Port G data register Port G direction register Port 0 pull-up register Port 1 pull-up register (Disabled) Port G pull-up register 8/16-bit compound timer 01 control status register 1 ch.0 8/16-bit compound timer 00 control status register 1 ch.0 (Disabled) 8/16-bit PPG1 control register ch.0 8/16-bit PPG0 control register ch.0 (Disabled) 16-bit PPG control status register (Upper byte) ch.0 16-bit PPG control status register (Lower byte) ch.0 R/W R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W ⎯ R/W R/W R/W ⎯ R/W R/W ⎯ R/W R/W Initial value 00000000B 00000000B 00000000B 00000000B ⎯ 11111111B 00000000B 1010X011B 00000000B XXXXXXXXB 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B ⎯ 00000000B 00000000B (Continued) 23 MB95130MB Series Address 0044H to 0047H 0048H 0049H 004AH 004BH 004CH to 004FH 0050H 0051H 0052H 0053H 0054H 0055H 0056H 0057H 0058H 0059H 005AH 005BH to 006BH 006CH 006DH 006EH 006FH 0070H 0071H 0072H 0073H 0074H 0075H 0076H 0077H Register abbreviation ⎯ EIC00 EIC10 EIC20 EIC30 ⎯ SCR SMR SSR RDR/TDR ESCR ECCR SMC10 SMC20 SSR0 TDR0 RDR0 ⎯ ADC1 ADC2 ADDH ADDL WCSR ⎯ FSR SWRE0 SWRE1 ⎯ WREN WROR Register name R/W ⎯ R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R ⎯ R/W R/W R/W R/W R/W ⎯ R/W R/W R/W ⎯ R/W R/W Initial value ⎯ 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00001000B 00000000B 00000100B 000000XXB 00000000B 00100000B 00000001B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ 000X0000B 00000000B 00000000B ⎯ 00000000B 00000000B (Continued) (Disabled) External interrupt circuit control register ch.0,ch.1 External interrupt circuit control register ch.2,ch.3 External interrupt circuit control register ch.4,ch.5 External interrupt circuit control register ch.6,ch.7 (Disabled) LIN-UART serial control register LIN-UART serial mode register LIN-UART serial status register LIN-UART reception/transmission data register LIN-UART extended status control register LIN-UART extended communication control register UART/SIO serial mode control register 1 ch.0 UART/SIO serial mode control register 2 ch.0 UART/SIO serial status register ch.0 UART/SIO serial output data register ch.0 UART/SIO serial input data register ch.0 (Disabled) 8/10-bit A/D converter control register 1 8/10-bit A/D converter control register 2 8/10-bit A/D converter data register (Upper byte) 8/10-bit A/D converter data register (Lower byte) Watch counter status register (Disabled) Flash memory status register Flash memory sector writing control register 0 Flash memory sector writing control register 1 (Disabled) Wild register address compare enable register Wild register data test setting register 24 MB95130MB Series Address 0078H 0079H 007AH 007BH 007CH 007DH 007EH 007FH 0F80H 0F81H 0F82H 0F83H 0F84H 0F85H 0F86H 0F87H 0F88H 0F89H to 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H to 0F9BH 0F9CH 0F9DH 0F9EH 0F9FH 0FA0H to 0FA3H Register abbreviation ⎯ ILR0 ILR1 ILR2 ILR3 ILR4 ILR5 ⎯ WRARH0 WRARL0 WRDR0 WRARH1 WRARL1 WRDR1 WRARH2 WRARL2 WRDR2 ⎯ T01CR0 T00CR0 T01DR T00DR TMCR0 ⎯ PPS01 PPS00 PDS01 PDS00 ⎯ Register name (Register bank pointer (RP) Mirror of direct bank pointer (DP) Interrupt level setting register 0 Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt level setting register 4 Interrupt level setting register 5 (Disabled) Wild register address setting register (Upper byte) ch.0 Wild register address setting register (Lower byte) ch.0 Wild register data setting register ch.0 Wild register address setting register (Upper byte) ch.1 Wild register address setting register (Lower byte) ch.1 Wild register data setting register ch.1 Wild register address setting register (Upper byte) ch.2 Wild register address setting register (Lower byte) ch.2 Wild register data setting register ch.2 (Disabled) 8/16-bit compound timer 01 control status register 0 ch.0 8/16-bit compound timer 00 control status register 0 ch.0 8/16-bit compound timer 01 data register ch.0 8/16-bit compound timer 00 data register ch.0 8/16-bit compound timer 00/01 timer mode control register ch.0 (Disabled) 8/16-bit PPG1 cycle setting buffer register ch.0 8/16-bit PPG0 cycle setting buffer register ch.0 8/16-bit PPG1 duty setting buffer register ch.0 8/16-bit PPG0 duty setting buffer register ch.0 (Disabled) R/W ⎯ R/W R/W R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W ⎯ R/W R/W R/W R/W ⎯ Initial value ⎯ 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ 11111111B 11111111B 11111111B 11111111B ⎯ (Continued) 25 MB95130MB Series (Continued) Address 0FA4H 0FA5H 0FA6H to 0FA9H 0FAAH 0FABH 0FACH 0FADH 0FAEH 0FAFH 0FB0H to 0FBBH 0FBCH 0FBDH 0FBEH 0FBFH 0FC0H to 0FC2H 0FC3H 0FC4H to 0FE2H 0FE3H 0FE4H to 0FE6H 0FE7H 0FE8H, 0FE9H 0FEAH 0FEBH to 0FEDH 0FEEH 0FEFH 0FF0H to 0FFFH 26 Register abbreviation PPGS REVC ⎯ PDCRH0 PDCRL0 PCSRH0 PCSRL0 PDUTH0 PDUTL0 ⎯ BGR1 BGR0 PSSR0 BRSR0 ⎯ AIDRL ⎯ WCDR ⎯ ILSR2 ⎯ CSVCR ⎯ ILSR WICR ⎯ Register name 8/16-bit PPG start register 8/16-bit PPG output inversion register (Disabled) 16-bit PPG down counter register (Upper byte) ch.0 16-bit PPG down counter register (Lower byte) ch.0 16-bit PPG cycle setting buffer register (Upper byte) ch.0 16-bit PPG cycle setting buffer register (Lower byte) ch.0 16-bit PPG duty setting buffer register (Upper byte) ch.0 16-bit PPG duty setting buffer register (Lower byte) ch.0 (Disabled) LIN-UART baud rate generator register 1 LIN-UART baud rate generator register 0 UART/SIO dedicated baud rate generator prescaler selection register ch.0 UART/SIO dedicated baud rate generator baud rate setting register ch.0 (Disabled) A/D input disable register (Lower byte) (Disabled) Watch counter data register (Disabled) Input level select register 2 (option) (Disabled) Clock supervisor control register (Disabled) Input level select register Interrupt pin control register (Disabled) R/W R/W R/W ⎯ R R R/W R/W R/W R/W ⎯ R/W R/W R/W R/W ⎯ R/W ⎯ R/W ⎯ R/W ⎯ R/W ⎯ R/W R/W ⎯ Initial value 00000000B 00000000B ⎯ 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B ⎯ 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B ⎯ 00111111B ⎯ 00000000B ⎯ 00011100B ⎯ 00000000B 01000000B ⎯ MB95130MB Series • R/W access symbols R/W : Readable / Writable R : Read only W : Write only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value. 27 MB95130MB Series ■ INTERRUPT SOURCE TABLE Interrupt source Interrupt request number IRQ0 Vector table address Upper Lower Same level Bit name of priority order interrupt level (at simultaneous setting register occurrence) High FFFAH FFFBH L00 [1 : 0] External interrupt ch.0 External interrupt ch.4 External interrupt ch.1 External interrupt ch.5 External interrupt ch.2 External interrupt ch.6 External interrupt ch.3 External interrupt ch.7 UART/SIO ch.0 8/16-bit compound timer ch.0 (Lower) 8/16-bit compound timer ch.0 (Higher) LIN-UART (reception) LIN-UART (transmission) (Unused) (Unused) (Unused) 8/16-bit PPG ch.0 (Upper) 8/16-bit PPG ch.0 (Lower) (Unused) 16-bit PPG ch.0 (Unused) (Unused) 8/10-bit A/D converter Timebase timer Watch prescaler/Watch counter (Unused) (Unused) Flash memory IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 IRQ20 IRQ21 IRQ22 IRQ23 FFF8H FFF6H FFF4H FFF2H FFF0H FFEEH FFECH FFEAH FFE8H FFE6H FFE4H FFE2H FFE0H FFDEH FFDCH FFDAH FFD8H FFD6H FFD4H FFD2H FFD0H FFCEH FFCCH FFF9H FFF7H FFF5H FFF3H FFF1H FFEFH FFEDH FFEBH FFE9H FFE7H FFE5H FFE3H FFE1H FFDFH FFDDH FFDBH FFD9H FFD7H FFD5H FFD3H FFD1H FFCFH FFCDH L01 [1 : 0] L02 [1 : 0] L03 [1 : 0] L04 [1 : 0] L05 [1 : 0] L06 [1 : 0] L07 [1 : 0] L08 [1 : 0] L09 [1 : 0] L10 [1 : 0] L11 [1 : 0] L12 [1 : 0] L13 [1 : 0] L14 [1 : 0] L15 [1 : 0] L16 [1 : 0] L17 [1 : 0] L18 [1 : 0] L19 [1 : 0] L20 [1 : 0] L21 [1 : 0] L22 [1 : 0] L23 [1 : 0] Low 28 MB95130MB Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Power supply voltage*1 Input voltage*1 Output voltage* 1 Symbol VCC AVCC VI VO ICLAMP Σ|ICLAMP| IOL1 IOL2 Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 − 2.0 ⎯ ⎯ Max VSS + 6.0 VSS + 6.0 VSS + 6.0 + 2.0 20 15 15 Unit V V V mA mA mA *2 *3 *3 Remarks Maximum clamp current Total maximum clamp current “L” level maximum output current Applicable to pins*4 Applicable to pins*4 Other than PF0, PF1 PF0, PF1 Other than PF0, PF1 Average output current = operating current × operating ratio (1 pin) PF0, PF1 Average output current = operating current × operating ratio (1 pin) IOLAV1 “L” level average current IOLAV2 ⎯ 4 mA 12 “L” level total maximum output current “L” level total average output current “H” level maximum output current ΣIOL ΣIOLAV IOH1 IOH2 ⎯ ⎯ ⎯ 100 mA Total average output current = operating current × operating ratio (Total of pins) Other than PF0, PF1 PF0, PF1 Other than PF0, PF1 Average output current = operating current × operating ratio (1 pin) PF0, PF1 Average output current = operating current × operating ratio (1 pin) 50 − 15 − 15 −4 mA mA IOHAV1 “H” level average current IOHAV2 ⎯ mA −8 “H” level total maximum output current “H” level total average output current Power consumption Operating temperature Storage temperature ΣIOH ΣIOHAV Pd TA Tstg ⎯ ⎯ ⎯ − 40 − 55 − 100 − 50 320 + 85 + 150 mA Total average output current = operating current × operating ratio (Total number of pins) mA mW °C °C 29 MB95130MB Series *1: The parameter is based on AVSS = VSS = 0.0 V. *2: Apply equal potential to AVCC and VCC. *3: VI and VO should not exceed Vcc + 0.3 V. VI must not exceed the rating voltage. However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *4: Applicable pins: P10 to P15, PF0, PF1 (Inapplicable pins: PG1, PG2) • Use within recommended operating conditions. • Use at DC voltage (current). • +B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting resistance placed between the + B signal and the microcontroller. • The value of the limiting resistance should be set so that when the + B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this affects other devices. • Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. • Note that if the + B input is applied during power-on, the power supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. • Care must be taken not to leave the + B input pin open. • Note that analog system input/output pins other than the A/D input pins (LCD drive pins, etc.) cannot accept +B signal input. • Sample recommended circuits : • Input/Output Equivalent circuits Protective diode Limiting resistance Vcc P-ch N-ch R + B input (0 V to 16 V) WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 30 MB95130MB Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Parameter Power supply voltage Smoothing capacitor Operating temperature Symbol VCC, AVCC CS TA Value Min 2.42*2 2.3 0.1 − 40 Max 5.5*1 5.5 1.0 + 85 Unit V µF °C Remarks At normal operation Holds condition in stop mode *3 *1: The value varies depending on the operating frequency. *2: The value is 2.88 V when the low-voltage detection reset is used. *3: Use ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC pin must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the diagram below. • C pin connection diagram C CS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 31 MB95130MB Series 3. DC Characteristics (VCC = = AVCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Symbol Pin name P04 (selectable in SIN), P10 (selectable in UI0) P00 to P07, P10 to P16, PF0, PF1, PG1, PG2 P00 to P07, P10 to P16, PF0, PF1, PG1, PG2 Condition Value Min 0.7 VCC Typ ⎯ Max VCC + 0.3 Unit Remarks VIHI ⎯ V Hysteresis input VIHSI “H” level input voltage ⎯ 0.8 VCC ⎯ VCC + 0.3 V Hysteresis input VIHA ⎯ 0.8 Vcc ⎯ VCC + 0.3 V Pin input at selecting of Automotive input level CMOS input (Flash memory product) Hysteresis input (MASK ROM product) Hysteresis input ⎯ VIHM RST, MOD ⎯ P04 (selectable in SIN), P10 (selectable in UI0) P00 to P07, P10 to P16, PF0, PF1, PG1, PG2 P00 to P07, P10 to P16, PF0, PF1, PG1, PG2 0.7 VCC ⎯ VCC + 0.3 V 0.8 VCC ⎯ VCC + 0.3 V VIL ⎯ VSS − 0.3 ⎯ 0.3 VCC V VILS “L” level input voltage ⎯ VSS − 0.3 ⎯ 0.2 VCC V Hysteresis input VILA ⎯ VSS − 0.3 ⎯ 0.5 VCC V Pin input at selecting of Automotive input level CMOS input (Flash memory product) Hysteresis input (MASK ROM product) ⎯ VILM RST, MOD ⎯ “H” level output voltage “L” level output voltage VOH1 VOH2 VOL1 VOL2 VSS − 0.3 ⎯ 0.3 VCC V VSS − 0.3 ⎯ ⎯ ⎯ ⎯ ⎯ 0.2 VCC ⎯ ⎯ 0.4 0.4 V V V V V Output pins other IOH = − 4.0 mA VCC − 0.5 than PF0, PF1 PF0, PF1 IOH = − 8.0 mA VCC − 0.5 ⎯ ⎯ Output pins other than PF0 to PF7, IOL = 4.0 mA RST*1 PF0, PF1 IOL = 12 mA (Continued) 32 MB95130MB Series (VCC = AVCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Symbol Input leakage current (Hi-Z output leakage current) Pull-up resistor Pull-down resistor Input capacity Pin name Condition Value Min Typ Max Unit Remarks ILI P00 to P07, P10 to P16, PF0, 0.0 V < VI < VCC PF1, PG1, PG2 −5 ⎯ +5 When the pull-up µA prohibition setting When the pull-up permission setting MASK ROM product only RPULL P00 to P07, P10 to P16, PG1, VI = 0.0 V PG2 MOD Other than AVCC, AVss, C, Vcc and Vss VI = VCC f = 1 MHz 25 50 100 kΩ RMOD 50 ⎯ 100 200 kΩ pF CIN 5 15 ⎯ VCC = 5.5 V FCH = 20 MHz FMP = 10 MHz Main clock mode (divided by 2) 9.5 12.5 Flash memory product (at other than mA Flash memory writing and erasing) Flash memory product mA (at Flash memory writing and erasing) mA MASK ROM product ⎯ 30 35 Power supply current*2 ICC VCC (External clock operation) ⎯ 7.2 9.5 ⎯ FCH = 32 MHz FMP = 16 MHz Main clock mode (divided by 2) 15.2 20.0 Flash memory product (at other than mA Flash memory writing and erasing) Flash memory product mA (at Flash memory writing and erasing) mA MASK ROM product (Continued) ⎯ 35.7 42.5 ⎯ 11.6 15.2 33 MB95130MB Series (VCC = AVCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Value Condition Unit Remarks Min Typ Max VCC = 5.5 V FCH = 20 MHz FMP = 10 MHz Main Sleep mode (divided by 2) FCH = 32 MHz FMP = 16 MHz Main Sleep mode (divided by 2) VCC = 5.5 V FCL = 32 kHz FMPL = 16 kHz Sub clock mode (divided by 2) , TA = + 25 °C VCC = 5.5 V FCL = 32 kHz FMPL = 16 kHz Sub sleep mode (divided by 2) , TA = + 25 °C VCC = 5.5 V FCL = 32 kHz Watch mode Main stop mode TA = + 25 °C VCC = 5.5 V FCH = 4 MHz FMP = 10 MHz Main PLL mode (multiplied by 2.5) FCH = 6.4 MHz FMP = 16 MHz Main PLL mode (multiplied by 2.5) VCC = 5.5 V FCL = 32 kHz FMPL = 128 kHz Sub PLL mode (multiplied by 4) , TA = + 25 °C Parameter Symbol Pin name ⎯ 4.5 7.5 mA ICCS ⎯ 7.2 12.0 mA ICCL ⎯ 45 100 µA Dual clock product only ICCLS Power supply current*2 ICCT VCC (External clock operation) ⎯ 10 81 µA Dual clock product only ⎯ 4.6 27 µA Dual clock product only ⎯ ⎯ ⎯ ⎯ 9.3 7 14.9 11.2 12.5 9.5 20.0 15.2 mA mA mA mA Flash memory product MASK ROM product Flash memory product MASK ROM product ICCMPLL ICCSPLL ⎯ 160 400 µA Dual clock product only (Continued) 34 MB95130MB Series (Continued) Parameter Symbol Pin name (VCC = AVCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Value Condition Unit Remarks Min Typ Max VCC = 5.5 V FCH = 10 MHz Timebase timer mode TA = + 25 °C VCC = 5.5 V Sub stop mode TA = + 25 °C VCC = 5.5 V FCH = 16 MHz When A/D conversion is in operation AVcc IAH VCC = 5.5 V FCH = 16 MHz When A/D conversion is stopped TA = + 25 °C ICTS VCC (External clock operation) ⎯ 0.15 1.1 mA ICCH Power supply current*2 ⎯ 3.5 20.0 µA Main stop mode for single clock product IA ⎯ 2.4 4.7 mA ⎯ 1 5 µA *1: Product without clock supervisor only *2: • The power supply current is specified by the external clock. When the low-voltage detection and clock supervisor options are selected, the consumption current values of both the low-voltage detection circuit (ILVD) and the built-in CR oscillator (ICSV) must also be added to the power supply current value. • Refer to “4. AC Characteristics: (1) Clock Timing” for FCH and FCL. • Refer to “4. AC Characteristics: (2) Source Clock/Machine Clock” for FMP and FMPL. 35 MB95130MB Series 4. AC Characteristics (1) Clock Timing (VCC = 2.42 V to 5.0 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter SymCondiPin name bol tion Value Min 1.00 1.00 FCH Clock frequency X0, X1 3.00 3.00 3.00 3.00 ⎯ FCL X0A, X1A ⎯ tHCYL Clock cycle time tLCYL tWH1 tWL1 tWH2 tWL2 tCR tCF X0A, X1A X0 X0A X0, X0A X0, X1 ⎯ 61.5 30.8 ⎯ 61.5 ⎯ ⎯ 32.768 ⎯ ⎯ 30.5 ⎯ 15.2 ⎯ ⎯ 1000 1000 ⎯ ⎯ ⎯ 5 kHz ns ns µs ns µs ns Typ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 32.768 Max 16.25 32.50 10.00 8.13 6.50 4.06 ⎯ Unit MHz Remarks When using main oscillation circuit MHz When using external clock MHz Main PLL multiplied by 1 MHz Main PLL multiplied by 2 MHz Main PLL multiplied by 2.5 MHz Main PLL multiplied by 4 kHz When using sub oscillation circuit When using sub PLL VCC = 2.3 V to 3.6 V When using main oscillation circuit When using external clock When using sub oscillation circuit When using external clock duty ratio is about 30% to 70%. When using external clock Input clock pulse width Input clock rise/fall time 36 MB95130MB Series • Input wave form for using external clock (main clock) tHCYL tWH1 tCR tCF 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC tWL1 X0 • Figure of Main Clock Input Port External Connection When using crystal or ceramic oscillator Microcontroller When using external clock Microcontroller X0 X1 FCH C1 C2 X0 X1 Open FCH • Input wave form for using external clock (sub clock) tLCYL tWH2 tCR tCF 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC tWL2 X0A • Figure of Sub clock Input Port External Connection When using crystal or ceramic oscillator Microcontroller When using external clock Microcontroller X0A X1A FCL X0A X1A Open FCL C1 C2 37 MB95130MB Series (2) Source Clock/Machine Clock (VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Symbol Pin name Value Min 61.5 tSCLK ⎯ 7.6 FSP FSPL ⎯ ⎯ 0.50 16.384 61.5 tMCLK ⎯ 7.6 FMP FMPL 0.031 1.024 ⎯ ⎯ ⎯ 976.5 16.250 131.072 µs ⎯ ⎯ ⎯ ⎯ 61.0 16.25 131.072 32000 µs Typ ⎯ Max 2000 Unit Remarks When using main clock Min : FCH = 8.125 MHz, PLL multiplied by 2 Max : FCH = 1 MHz, divided by 2 When using sub clock Min : FCL = 32 kHz, PLL multiplied by 4 Max : FCL = 32 kHz, divided by 2 Source clock cycle time*1 (Clock before setting division) Source clock frequency Machine clock cycle time*2 (Minimum instruction execution time) Machine clock frequency ns MHz When using main clock kHz When using sub clock ns When using main clock Min : FSP = 16.25 MHz, no division Max : FSP = 0.5 MHz, divided by 16 When using sub clock Min : FSPL = 131 kHz, no division Max : FSPL = 16 kHz, divided by 16 ⎯ MHz When using main clock kHz When using sub clock *1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes the machine clock. Further, the source clock can be selected as follows. • Main clock divided by 2 • PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication) • Sub clock divided by 2 • PLL multiplication of sub clock (select from 2, 3, 4 multiplication) *2 : Operation clock of the microcontroller. Machine clock can be selected as follows. • Source clock (no division) • Source clock divided by 4 • Source clock divided by 8 • Source clock divided by 16 • Outline of clock generation block FCH (main oscillation) Divided by 2 Main PLL ×1 ×2 × 2.5 ×4 SCLK (source clock) FCL (sub oscillation) Divided by 2 Clock mode select bit (SYCC: SCS1, SCS0) Division circuit ×1 × 1/4 × 1/8 × 1/16 MCLK (machine clock) Sub PLL ×2 ×3 ×4 38 MB95130MB Series • Operating voltage - Operating frequency (When TA = − 40 °C to + 85 °C) • MB95F133MBS/F133NBS/F133JBS/F134MBS/F134NBS/F134JBS/F136MBS/F136NBS/F136JBS/ MB95F133MBW/F133NBW/F133JBW/F134MBW/F134NBW/F134JBW/F136MBW/F136NBW/ MB95F136JBW Sub PLL, sub clock mode and watch mode operation guarantee range 5.5 5.5 Main clock mode and main PLL mode operation guarantee range Operating voltage (V) Operating voltage (V) 3.5 2.42 2.42 16.384 kHz 32 kHz 131.072 kHz 0.5 MHz 3 MHz 10 MHz 16.25 MHz PLL operation guarantee range PLL operation guarantee range Main clock operation guarantee range Source clock frequency (FSPL) Source clock frequency (FSP) • Operating voltage - Operating frequency (When TA = + 5 °C to + 35 °C) • MB95FV100D-103 Sub PLL, sub clock mode and watch mode operation guarantee range 5.5 5.5 Main clock mode and main PLL mode operation guarantee range Operating voltage (V) Operating voltage (V) 3.5 2.7 2.7 16.384 kHz 32 kHz 131.072 kHz 0.5 MHz 3 MHz 10 MHz 16.25 MHz PLL operation guarantee range PLL operation guarantee range Main clock operation guarantee range Source clock frequency (FSPL) Source clock frequency (FSP) 39 MB95130MB Series • Main PLL operation frequency [MHz] 16.25 16 15 ×4 12 Source clock frequency (FSP) × 2.5 10 ×2 ×1 7.5 6 5 3 0 3 4 4.062 5 6.4 6.5 8 8.125 10 [MHz] Machine clock frequency (FMP) 40 MB95130MB Series (3) External Reset (VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Symbol Pin name Value Min 2 tMCLK*1 RST “L” level pulse width tRSTL RST Oscillation time of oscillator*2 + 100 100 *1 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. *2 : Oscillation start time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of µs and several ms. In the external clock, the oscillation time is 0 ms. Max ⎯ ⎯ ⎯ Unit ns µs µs Remarks At normal operation At stop mode, sub clock mode, sub sleep mode & watch mode At timebase timer mode • At normal operation tRSTL RST 0.2 VCC 0.2 VCC • At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on tRSTL 0.2 VCC 0.2 VCC RST 90% of amplitude X0 Internal operating clock Oscillation time Oscillation stabilization wait time of oscillator Execute instruction Internal reset 100 µs 41 MB95130MB Series (4) Power-on Reset (AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Power supply rising time Power supply cutoff time Symbol tR tOFF VCC Pin name Condition ⎯ ⎯ Value Min ⎯ 1 Max 50 ⎯ Unit ms ms Waiting time until power-on Remarks Note : Complete the power-on process within the selected oscillation stabilization wait time. tR 2.5 V tOFF VCC 0.2 V 0.2 V 0.2 V Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power supply voltages during operation, set the slope of rising within 30 mV/ms as shown below. VCC 2.3 V Limiting the slope of rising within 30 mV/ms is recommended. Hold Condition in stop mode VSS 42 MB95130MB Series (5) Peripheral Input Timing (VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Peripheral input “H” pulse Peripheral input “L” pulse Symbol tILIH tIHIL Pin name INT00 to INT07, EC0, TRG0/ADTG Value Min 2 tMCLK* 2 tMCLK* Max ⎯ ⎯ Unit ns ns * : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. tILIH tIHIL 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC INT00 to INT07, EC0,TRG0/ADTG 43 MB95130MB Series (6) UART/SIO Serial I/O Timing (VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Serial clock cycle time UCK ↓ → UO time Valid UI → UCK ↑ UCK ↑→ valid UI hold time Serial clock “H” pulse width Serial clock “L” pulse width UCK ↓ → UO time Valid UI → UCK ↑ UCK ↑→ valid UI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name UCK0 UCK0, UO0 UCK0, UI0 UCK0, UI0 UCK0 UCK0 UCK0, UO0 UCK0, UI0 UCK0, UI0 External clock operation output pin : CL = 80 pF + 1 TTL. Internal clock operation output pin : CL = 80 pF + 1 TTL. Condition Value Min 4 tMCLK* − 190 2 tMCLK* 2 tMCLK* 4 tMCLK* 4 tMCLK* ⎯ 2 tMCLK* 2 tMCLK* Max ⎯ +190 ⎯ ⎯ ⎯ ⎯ 190 ⎯ ⎯ Unit ns ns ns ns ns ns ns ns ns * : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. • Internal shift clock mode tSCYC UCK0 2.4 V 0.8 V tSLOV 0.8 V UO0 2.4 V 0.8 V tIVSH tSHIX UI0 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSLSH tSHSL 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tSLOV UCK0 UO0 2.4 V 0.8 V tIVSH tSHIX UI0 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 44 MB95130MB Series (7) LIN-UART Timing Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2 (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0) (VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Serial clock cycle time SCK ↓→ SOT delay time Valid SIN → SCK↑ SCK ↑→ valid SIN hold time Serial clock “L” pulse width Serial clock “H” pulse width SCK ↓ → SOT delay time Valid SIN → SCK↑ SCK↑→ valid SIN hold time SCK fall time SCK rise time SymPin name bol tSCYC tSLOVI tIVSHI tSHIXI tSLSH tSHSL tIVSHE tSHIXE tF tR SCK Internal clock SCK, SOT operation output pin : SCK, SIN CL = 80 pF + 1 TTL. SCK, SIN SCK SCK External clock SCK, SIN operation output pin : CL = 80 pF + 1 TTL. SCK, SIN SCK SCK t Condition Value Min 5 tMCLK*3 − 95 MCLK 3 Max ⎯ +95 ⎯ ⎯ ⎯ ⎯ 2t MCLK 3 Unit ns ns ns ns ns ns ns ns ns ns ns * + 190 0 3 tMCLK*3 − tR t MCLK 3 * + 95 tSLOVE SCK, SOT ⎯ 190 tMCLK*3 + 95 ⎯ ⎯ * + 95 ⎯ ⎯ 10 10 *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. 45 MB95130MB Series • Internal shift clock mode tSCYC SCK 0.8 V tSLOVI 2.4 V 0.8 V 2.4 V 0.8 V SOT tIVSHI tSHIXI SIN 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSLSH tSHSL 0.8 VCC 0.2 VCC tF tSLOVE 2.4 V 0.8 V tIVSHE tSHIXE 0.2 VCC tR 0.8 VCC SCK 0.8 VCC SOT SIN 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 46 MB95130MB Series Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2 (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0) (VCC = 5.0 V± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Serial clock cycle time SCK↑→ SOT delay time Valid SIN → SCK↓ SCK ↓→ valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK↑ → SOT delay time Valid SIN → SCK↓ SCK ↓→ valid SIN hold time SCK fall time SCK rise time Symbol tSCYC tSHOVI tIVSLI tSLIXI tSHSL tSLSH tSHOVE tIVSLE tSLIXE tF tR Pin name SCK SCK, SOT Internal clock operation output pin : SCK, SIN CL = 80 pF + 1 TTL. SCK, SIN SCK SCK SCK, SOT External clock SCK, SIN operation output pin : SCK, SIN CL = 80 pF + 1 TTL. SCK SCK t Condition Value Min 5 tMCLK*3 − 95 MCLK 3 Max ⎯ +95 ⎯ ⎯ ⎯ ⎯ 2t MCLK 3 Unit ns ns ns ns ns ns ns ns ns ns ns * + 190 0 3 tMCLK*3 − tR tMCLK*3 + 95 ⎯ 190 tMCLK*3 + 95 ⎯ ⎯ * + 95 ⎯ ⎯ 10 10 *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. 47 MB95130MB Series • Internal shift clock mode tSCYC SCK 2.4 V 0.8 V tSHOVI 2.4 V 0.8 V tIVSLI tSLIXI 2.4 V SOT SIN 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSHSL tSLSH 0.8 VCC 0.2 VCC tR tSHOVE 2.4 V 0.8 V tIVSLE tSLIXE tF 0.2 VCC SCK 0.8 VCC SOT SIN 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 48 MB95130MB Series Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2 (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1) (VCC = 5.0 V± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Serial clock cycle time SCK↑→ SOT delay time Valid SIN → SCK↓ SCK ↓→ valid SIN hold time SOT → SCK ↓ delay time Symbol tSCYC tSHOVI tIVSLI tSLIXI tSOVLI Pin name SCK SCK, SOT SCK, SIN SCK, SIN SCK, SOT Internal clock operation output pin : CL = 80 pF + 1 TTL. t Condition Value Min 5 tMCLK*3 − 95 MCLK 3 Max ⎯ +95 ⎯ ⎯ 4 tMCLK*3 Unit ns ns ns ns ns * + 190 0 ⎯ *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. tSCYC SCK 0.8 V tSOVLI 2.4 V 0.8 V tIVSLI 2.4 V tSHOVI 2.4 V 0.8 V tSLIXI 0.8 VCC 0.2 VCC 0.8 V SOT SIN 0.8 VCC 0.2 VCC 49 MB95130MB Series Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2 (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1) (VCC = 5.0 V± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Serial clock cycle time SCK ↓→ SOT delay time Valid SIN → SCK↑ SCK↑→ valid SIN hold time SOT → SCK↑ delay time Symbol tSCYC tSLOVI tIVSHI tSHIXI tSOVHI Pin name SCK SCK, SOT Internal clock SCK, SIN operating output pin : CL = 80 pF + 1 TTL. SCK, SIN t Condition Value Min 5 tMCLK*3 − 95 MCLK 3 Max ⎯ +95 ⎯ ⎯ 4 tMCLK*3 Unit ns ns ns ns ns * + 190 0 ⎯ SCK, SOT *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. tSCYC SCK tSOVHI 2.4 V 0.8 V tSLOVI 2.4 V 0.8 V tIVSHI tSHIXI 0.8 VCC 0.2 VCC 2.4 V 0.8 V 2.4 V SOT SIN 0.8 VCC 0.2 VCC 50 MB95130MB Series (8) Low voltage Detection (AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Release voltage Detection voltage Hysteresis width Power-supply start voltage Power-supply end voltage Power-supply voltage change time (at power supply rise) Symbol VDL+ VDL− VHYS Voff Von Value Min 2.52 2.42 70 ⎯ 4.9 0.3 tr ⎯ 300 tf ⎯ td1 td2 ILVD ⎯ ⎯ ⎯ 300 ⎯ ⎯ 38 ⎯ 400 30 50 µs µs µs µA Consumption current of low voltage detection circuit only 3000 ⎯ ⎯ ⎯ µs µs Typ 2.70 2.60 100 ⎯ ⎯ ⎯ Max 2.88 2.78 ⎯ 2.3 ⎯ ⎯ Unit V V mV V V µs Slope of power supply that reset release signal generates Slope of power supply that reset release signal generates within rating (VDL+) Slope of power supply that reset detection signal generates Slope of power supply that reset detection signal generates within rating (VDL-) Remarks At power-supply rise At power-supply fall Power-supply voltage change time (at power supply fall) Reset release delay time Reset detection delay time Consumption current 51 MB95130MB Series VCC Von Voff Time VCC tf tr VDL+ VHYS VDL- Internal reset signal Time td2 td1 52 MB95130MB Series (9) Clock Supervisor Clock (VCC = AVCC = 5 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Oscillation frequency Oscillation start time Current consumption Symbol fOUT twk ICSV Value Min 50 ⎯ ⎯ Typ 100 ⎯ 20 Max 200 10 36 Unit kHz µs µA Current consumption of built-in CR oscillator at 100 kHz oscillation Remarks 53 MB95130MB Series 5. A/D Converter (1) A/D Converter Electrical Characteristics (AVCC = VCC = 4.0 V to 5.5 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Resolution Total error Linearity error Differential linear error Zero transition voltage Full-scale transition voltage Compare time VOT VFST ⎯ ⎯ Symbol Value Min ⎯ − 3.0 − 2.5 − 1.9 Typ ⎯ ⎯ ⎯ ⎯ Max 10 + 3.0 + 2.5 + 1.9 Unit bit LSB LSB LSB V V µs µs µs 4.5 V ≤ AVCC ≤ 5.5 V 4.0 V ≤ AVCC < 4.5 V 4.5 V ≤ AVcc ≤ 5.5 V, At external impedance < at 5.4 kΩ 4.0 V ≤ AVcc ≤ 4.5 V, At external impedance < at 2.4 kΩ Remarks AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB AVCC − 4.5 LSB AVCC − 1.5 LSB AVCC + 0.5 LSB 0.9 1.8 0.6 ⎯ ⎯ ⎯ 16500 16500 ∞ ∞ + 0.3 AVCC Sampling time ⎯ 1.2 ⎯ ⎯ ⎯ µs µA V Analog input current Analog input voltage IAIN VAIN − 0.3 AVSS 54 MB95130MB Series (2) Notes on Using A/D Converter • External impedance of analog input and its sampling time • A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. Therefore to satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. • Analog input equivalent circuit R Analog input C Comparator During sampling : ON 4.5 V ≤ AVCC ≤ 5.5 V 4.0 V ≤ AVCC < 4.5 V Note : The values are reference values. R 2.0 kΩ (Max) 8.2 kΩ (Max) C 16 pF (Max) 16 pF (Max) • The relationship between external impedance and minimum sampling time (External impedance = at 0 kΩ to 100 kΩ) 100 90 80 70 60 50 40 30 20 10 0 0 2 (External impedance = at 0 kΩ to 20 kΩ) 20 18 16 14 12 10 8 6 4 2 0 0 External impedance [kΩ] AVCC ≥ 4.0 V External impedance [kΩ] AVCC ≥ 4.5 V AVCC ≥ 4.5 V AVCC ≥ 4.0 V 4 6 8 10 12 14 1 2 3 4 Minimum sampling time [µs] Minimum sampling time [µs] • Errors As |AVCC − AVSS| becomes smaller, values of relative errors grow larger. 55 MB95130MB Series (3) Definition of A/D Converter Terms • Resolution The level of analog variation that can be distinguished by the A/D converter. When the number of bits is 10, analog voltage can be divided into 210 = 1024. • Linearity error (unit : LSB) The deviation between the value along a straight line connecting the zero transition point (“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point (“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained. • Differential linear error (Unit : LSB) Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. • Total error (unit: LSB) Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error, linearity error, quantum error, and noise. Ideal I/O characteristics VFST Total error 3FFH 3FEH 3FFH 3FEH 1.5 LSB Actual conversion characteristic {1 LSB × (N − 1) + 0.5 LSB} Digital output Digital output 3FDH 3FDH 004H 003H 002H 001H 0.5 LSB AVSS AVCC VOT 1 LSB 004H 003H 002H 001H AVSS AVCC VNT Actual conversion characteristic Ideal characteristics Analog input 1 LSB = AVCC − AVSS 1024 (V) Analog input Total error of VNT − {1 LSB × (N − 1) + 0.5 LSB} = [LSB] digital output N 1 LSB N : A/D converter digital output value VNT : Voltage at which digital output transits from (N-1) H to NH. (Continued) 56 MB95130MB Series (Continued) Zero transition error 004H Actual conversion characteristics 3FFH Full-scale transition error Ideal characteristics Actual conversion characteristics Digital output 003H Ideal characteristics Digital output 3FEH 002H Actual conversion characteristics VFST (Actual value) 3FDH 001H VOT (Actual value) 3FCH Actual conversion characteristics AVSS AVCC AVSS AVCC Analog input Analog input Linearity error 3FFH 3FEH Actual conversion characteristics Differential linear error Ideal characteristics (N+1)H {1 LSB × N + VOT} VFST (Actual value) Digital output Digital output 3FDH Actual conversion characteristics V (N+1)T NH VNT 004H 003H 002H 001H AVSS Actual conversion characteristics Ideal characteristics (N-1)H VNT Actual conversion characteristics (N-2)H VOT (Actual value) Analog input AVCC AVSS Analog input AVCC Linear error of = VNT − {1 LSB × N + VOT} 1 LSB digital output N Differential linear error = of digital output N V (N + 1) T − VNT 1 LSB −1 N : A/D converter digital output value VNT : Voltage at which digital output transits from (N - 1)H to NH. VOT (Ideal value) = AVSS + 0.5 LSB [V] VFST (Ideal value) = AVCC − 1.5 LSB [V] 57 MB95130MB Series 6. Flash Memory Program/Erase Characteristics Parameter Chip erase time Byte programming time Erase/program cycle Power supply voltage at erase/ program Flash memory data retention time Value Min ⎯ ⎯ 10000 4.5 20*3 Typ 1.0*1 32 ⎯ ⎯ ⎯ Max 15.0*2 3600 ⎯ 5.5 ⎯ Unit s µs cycle V year Average TA = +85 °C Remarks Excludes 00H programming prior erasure. Excludes system-level overhead. *1 : TA = + 25 °C, VCC = 5.0 V, 10000 cycles *2 : TA = + 85 °C, VCC = 4.5 V, 10000 cycles *3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at +85 °C) . 58 MB95130MB Series ■ MASK OPTION MB95F133MBS MB95F133NBS MB95F133JBS MB95F134MBS MB95F134NBS MB95F134JBS MB95F136MBS MB95F136NBS MB95F136JBS Setting disabled MB95F133MBW MB95F133NBW MB95F133JBW MB95F134MBW MB95F134NBW MB95F134JBW MB95F136MBW MB95F136NBW MB95F136JBW Setting disabled Part number No. MB95136MB MB95FV100D-103 Specifying procedure Specify when ordering MASK selectable Setting disabled Clock mode select 1 • Single-system clock mode • Dual-system clock mode Single-system clock mode Dual-system clock Changing by the mode switch on MCU board Low voltage detection reset* • With low voltage detection Specify when 2 reset ordering • Without low voltage MASK detection reset Clock supervisor* 3 • With clock supervisor • Without clock supervisor Reset output* 4 • With reset output • Without reset output Specify when ordering MASK Specified by part number Specified by part number Change by the switch on MCU board Specified by part number Specified by part number Change by the switch on MCU board Specify when ordering MASK Specified by part number MCU board switch set as following ; Specified by part • With supervisor : number Without reset output • Without supervisor : With reset output Fixed to oscillation Fixed to oscillation stabilization wait stabilization wait time time of of (214 − 2) /FCH (214 − 2) /FCH Oscillation stabilization 5 wait time Fixed to oscillation stabilization wait time of (214 − 2) /FCH Fixed to oscillation stabilization wait time of (214 − 2) /FCH *: Refer to table below about clock mode select, low voltage detection reset, clock supervisor select and reset output. 59 MB95130MB Series Low-voltage detection reset No Single - system MB95136MB Dual - system MB95F133MBS MB95F133NBS MB95F133JBS MB95F134MBS MB95F134NBS MB95F134JBS MB95F136MBS MB95F136NBS MB95F136JBS MB95F133MBW MB95F133NBW MB95F133JBW MB95F134MBW MB95F134NBW MB95F134JBW MB95F136MBW MB95F136NBW MB95F136JBW Single - system MB95FV100D-103 Dual - system Dual - system Single - system Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes Yes Part number Clock mode select Clock supervisor No No Yes No No Yes No No Yes No No Yes No No Yes No No Yes No No Yes No No Yes No No Yes No No Yes Reset output Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes Yes No 60 MB95130MB Series ■ ORDERING INFORMATION Part number MB95136MBPF MB95F133MBSPF MB95F133NBSPF MB95F133JBSPF MB95F134MBSPF MB95F134NBSPF MB95F134JBSPF MB95F136MBSPF MB95F136NBSPF MB95F136JBSPF MB95F133MBWPF MB95F133NBWPF MB95F133JBWPF MB95F134MBWPF MB95F134NBWPF MB95F134JBWPF MB95F136MBWPF MB95F136NBWPF MB95F136JBWPF MB95136MBPFV MB95F133MBSPFV MB95F133NBSPFV MB95F133JBSPFV MB95F134MBSPFV MB95F134NBSPFV MB95F134JBSPFV MB95F136MBSPFV MB95F136NBSPFV MB95F136JBSPFV MB95F133MBWPFV MB95F133NBWPFV MB95F133JBWPFV MB95F134MBWPFV MB95F134NBWPFV MB95F134JBWPFV MB95F136MBWPFV MB95F136NBWPFV MB95F136JBWPFV MB2146-303A (MB95FV100D-103PBT) Package 28-pin plastic SOP (FPT-28P-M17) 30-pin plastic SSOP (FPT-30P-M02) ( MCU board 224-pin plastic PFBGA (BGA-224P-M08) ) 61 MB95130MB Series ■ PACKAGE DIMENSION 28-pin plastic SOP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 1.27 mm 8.6 × 17.75 mm Gullwing Plastic mold 2.80 mm MAX 0.82 g P-SOP28-8.6×17.75-1.27 (FPT-28P-M17) Code (Reference) 28-pin plastic SOP (FPT-28P-M17) +0.25 +.010 Note 1) *1 : These dimensions include resin protrusion. Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. 0.17 –0.04 15 +0.03 +.001 *1 17.75 –0.20 .699 –.008 28 .007 –.002 11.80±0.30 (.465±.012) INDEX *2 8.60±0.20 (.339±.008) Details of "A" part 2.65±0.15 (Mounting height) (.104±.006) 0.25(.010) 1 14 "A" 0~8˚ 1.27(.050) 0.47±0.08 (.019±.003) 0.13(.005) M 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.20±0.15 (.008±.006) (Stand off) 0.10(.004) C 2002 FUJITSU LIMITED F28048S-c-3-4 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html (Continued) 62 MB95130MB Series (Continued) 30-pin plastic SSOP Lead pitch Package width × package length Lead shape Sealing method Mounting height Code (Reference) 0.65 mm 5.60 × 9.70 mm Gullwing Plastic mold 1.45 mm MAX P-SSOP30-5.6×9.7-0.65 (FPT-30P-M02) 30-pin plastic SSOP (FPT-30P-M02) *1 9.70±0.10(.382±.004) 30 16 Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max). Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. 0.17±0.03 (.007±.001) INDEX *2 5.60±0.10 (.220±.004) 7.60±0.20 (.299±.008) Details of "A" part 1.25 –0.10 1 15 +0.20 +.008 .049 –.004 "A" (Mounting height) 0.65(.026) 0.24 –0.07 .009 +0.08 +.003 –.003 0.25(.010) 0~8˚ 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10(.004) 0.10±0.10 (.004±.004) (Stand off) C 2003 FUJITSU LIMITED F30003S-c-3-4 Dimensions in mm (inches). Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 63 MB95130MB Series The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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