MB95F168M

FUJITSU SEMICONDUCTOR DATA SHEET DS07-12609-3E 8-bit Microcontroller CMOS F2MC-8FX MB95160M Series MB95F168M/F168N/F168J/FV100D-103 ■ DESCRIPTION The MB95160M series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions. Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller. ■ FEATURE • F2MC-8FX CPU core Instruction set optimized for controllers • Multiplication and division instructions • 16-bit arithmetic operations • Bit test branch instruction • Bit manipulation instructions etc. • Clock • Main clock • Main PLL clock • Sub clock • Sub PLL clock (Continued) Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development. Copyright©2007 FUJITSU LIMITED All rights reserved MB95160M Series (Continued) • Timer • 8/16-bit compound timer × 2 channels Can be used to interval timer, PWC timer, PWM timer and input capture. • 8/16-bit PPG × 2 channels • 16-bit PPG × 1 channel • Time-base timer × 1 channel • Watch prescaler × 1 channel • LIN-UART × 1 channel • LIN function, clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable • Full duplex double buffer • UART/SIO × 1 channel • Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable • Full duplex double buffer • I2C* × 1 channel Built-in wake-up function • External interrupt × 8 channels • Interrupt by edge detection (rising, falling, or both edges can be selected) • Can be used to recover from low-power consumption (standby) modes. • 8/10-bit A/D converter × 8 channels 8-bit or 10-bit resolution can be selected. • LCD controller (LCDC) • 32 SEG × 4 COM (Max 128 pixels) • With blinking function • Low-power consumption (standby) mode • Stop mode • Sleep mode • Watch mode • Time-base timer mode • I/O port • The number of maximum ports : Max 53 • Port configuration - General-purpose I/O ports (N-ch open drain) : 2 ports - General-purpose I/O ports (CMOS) : 51 ports • Programmable input voltage levels of port Automotive input level / CMOS input level / hysteresis input level • Flash memory security function Protects the content of Flash memory * : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. 2 MB95160M Series ■ PRODUCT LINEUP Part number*1 Parameter Type ROM capacity RAM capacity Reset output Option*2 Clock system Low voltage detection reset Clock supervisor No No Yes Dual clock Yes Yes MB95F168M MB95F168N Flash memory product 60 Kbytes 2 Kbytes No MB95F168J CPU functions Number of basic instructions : 136 Instruction bit length : 8 bits Instruction length : 1 to 3 bytes Data bit length : 1, 8, and 16 bits Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 MHz) Interrupt processing time : 0.6 µs (at machine clock frequency 16.25 MHz) General-purpose I/O port (N-ch open drain) : 2 ports General-purpose I/O port (CMOS) : 51 ports Programmable input voltage levels of port : Automotive input level / CMOS input level / hysteresis input level Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz) Reset generated cycle At main oscillation clock 10 MHz : Min 105 ms At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms Capable of replacing 3 bytes of ROM data Master/slave sending and receiving Bus error function and arbitration function Detecting transmitting direction function Start condition repeated generation and detection functions Built-in wake-up function Data transfer capable in UART/SIO Full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate generator NRZ type transfer format, error detected function LSB-first or MSB-first can be selected. Clock synchronous (SIO) or clock asynchronous (UART) serial data transfer capable Dedicated reload timer allowing a wide range of communication speeds to be set. Full duplex double buffer. Capable of serial data transfer synchronous or asynchronous to clock signal. LIN functions available as the LIN master or LIN slave. Ports (Max 53 ports) Time-base timer (1 channel) Watchdog timer Wild register Peripheral functions I2C (1 channel) UART/SIO (1 channel) LIN-UART (1 channel) 8/10-bit A/D converter 8-bit or 10-bit resolution can be selected. (8 channels) (Continued) 3 MB95160M Series (Continued) Part number*1 Parameter MB95F168M MB95F168N MB95F168J LCD controller (LCDC) COM output : 4 (Max) SEG output : 32 (Max) LCD drive power supply (bias) pin :4 32 SEG × 4 COM : 128 pixels can be displayed. Duty LCD mode Operable in LCD standby mode With blinking function Built-in division resistance for LCD drive Each channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit timer × 1 channel”. Built-in timer function, PWC function, PWM function, capture function, and square wave form output Count clock : 7 internal clocks and external clock can be selected. PWM mode or one-shot mode can be selected. Counter operating clock : Eight selectable clock sources Support for external trigger start Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG × 1 channel”. Counter operating clock : Eight selectable clock sources Count clock : Four selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s) Counter value can be set from 0 to 63. (Capable of counting for 1 minute when selecting clock source 1 second and setting counter value to 60) 4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s) Interrupt by edge detection (rising, falling, or both edges can be selected.) Can be used to recover from standby modes. Supports automatic programming, Embedded Algorithm Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of write/erase cycles (Minimum) : 10000 times Data retention time: 20 years Erase can be performed on each block Block protection with external programming voltage Flash Security Feature for protecting the content of the Flash Sleep, stop, watch, and time-base timer Peripheral functions 4 8/16-bit compound timer (2 channels) 16-bit PPG (1 channel) 8/16-bit PPG (2 channels) Watch counter Watch prescaler (1 channel) External interrupt (8 channels) Flash memory Standby mode *1 : MASK ROM products are currently under consideration. *2 : For details of option, refer to “■ MASK OPTION”. Note : Part number of evaluation product in MB95160M series is MB95FV100D-103. When using it, the MCU board (MB2146-303A) is required. MB95160M Series ■ OSCILLATION STABILIZATION WAIT TIME The initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. The maximum value is shown as follows. Oscillation stabilization wait time Remarks (214-2) /FCH Approx. 4.10 ms (at main oscillation clock 4 MHz) ■ PACKAGES AND CORRESPONDING PRODUCTS Part number Package FPT-64P-M23 FPT-64P-M24 BGA-224P-M08 : Available : Unavailable MB95F168M/F168N/F168J MB95FV100D-103 5 MB95160M Series ■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS • Notes on Using Evaluation Products The evaluation product has not only the functions of the MB95160M series but also those of other products to support software development for multiple series and models of the F2MC-8FX family. The I/O addresses for peripheral resources not used by the MB95160M series are therefore access-barred. Read/write access to these access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting in unexpected malfunctions of hardware or software. Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are used, the address may be read or written unexpectedly). Also, as the read values of prohibited addresses on the evaluation product are different to the values on the Flash memory products, do not use these values in the program. The functions corresponding to certain bits in single-byte registers may not be supported on some Flash memory products. However, reading or writing to these bits will not cause malfunction of the hardware. Also, as the evaluation and Flash memory products are designed to have identical software operation, no particular precautions are required. • Difference of Memory Spaces If the amount of memory on the evaluation product is different from that of the Flash memory products, carefully check the difference in the amount of memory from the model to be actually used when developing software. For details of memory space, refer to “■ CPU CORE”. • Current Consumption For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”. • Package For details of information on each package, refer to “■ PACKAGES AND CORRESPONDING PRODUCTS” and “■ PACKAGE DIMENSIONS”. • Operating voltage The operating voltage is different among the evaluation and Flash memory products. For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS” 6 ■ PIN ASSIGNMENT AVR P14/PPG0 P13/TRG0/ADTG P12/UCK0 P11/UO0 P10/UI0 P24/EC0/SDA0 P23/TO01/SCL0 P22/TO00 P21/PPG01 P20/PPG00 MOD X0 X1 VSS AVCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VCC (TOP VIEW) LQFP-64 (FPT-64P-M23,FPT-64P-M24) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P60/SEG16/PPG10 PC7/SEG15 PC6/SEG14 PC5/SEG13 PC4/SEG12 PC3/SEG11 PC2/SEG10 PC1/SEG09 PC0/SEG08 PB7/SEG07 PB6/SEG06 PB5/SEG05 PB4/SEG04 PB3/SEG03 PB2/SEG02 PB1/SEG01 C X1A X0A RST P90/V3 P91/V2 P92/V1 P93/V0 P94 P95 PA0/COM0 PA1/COM1 PA2/COM2 PA3/COM3 PB0/SEG00 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVSS P00/INT00/AN00/SEG31 P01/INT01/AN01/SEG30 P02/INT02/AN02/SEG29 P03/INT03/AN03/SEG28 P04/INT04/AN04/SEG27 P05/INT05/AN05/SEG26 P06/INT06/AN06/SEG25 P07/INT07/AN07/SEG24 P67/SEG23/SIN P66/SEG22/SOT P65/SEG21/SCK P64/SEG20/EC1 P63/SEG19/TO11 P62/SEG18/TO10 P61/SEG17/PPG11 MB95160M Series 7 MB95160M Series ■ PIN DESCRIPTION Pin no. 1 2 3 Pin name AVCC AVR P14/PPG0 P13/TRG0/ ADTG P12/UCK0 P11/UO0 P10/UI0 P24/EC0/ SDA0 I 9 P23/TO01/ SCL0 P22/TO00 P21/PPG01 P20/PPG00 MOD X0 X1 VSS VCC C X1A X0A RST P90/V3 P91/V2 P92/V1 P93/V0 (Continued) R General-purpose I/O port. The pins are shared with power supply pin for LCDC drive. B A ⎯ ⎯ ⎯ A B’ H G I/O circuit type* ⎯ ⎯ Function A/D converter power supply pin A/D converter reference input pin General-purpose I/O port. The pin is shared with 16-bit PPG ch.0 output. General-purpose I/O port. The pin is shared with 16-bit PPG ch.0 trigger input (TRG0) and A/D converter trigger input (ADTG) . General-purpose I/O port. The pin is shared with UART/SIO ch.0 clock I/O. General-purpose I/O port. The pin is shared with UART/SIO ch.0 data output. General-purpose I/O port. The pin is shared with UART/SIO ch.0 data input. General-purpose I/O port. The pin is shared with 8/16-bit compound timer ch.0 clock input (EC0) and I2C ch.0 data I/O (SDA0) . General-purpose I/O port. The pin is shared with 8/16-bit compound timer ch.0 output (TO01) and I2C ch.0 clock I/O (SCL0) . General-purpose I/O port. The pin is shared with 8/16-bit compound timer ch.0 output. General-purpose I/O port. The pin is shared with 8/16-bit PPG ch.0 output. General-purpose I/O port. The pin is shared with 8/16-bit PPG ch.0 output. Operating mode designation pin Main clock oscillation pin Power supply pin (GND) Power supply pin Capacitor connection pin Sub clock oscillation pins (32 kHz) Reset pin 4 H 5 6 7 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 8 MB95160M Series Pin no. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Pin name P94 P95 PA0/COM0 PA1/COM1 PA2/COM2 PA3/COM3 PB0/SEG00 PB1/SEG01 PB2/SEG02 PB3/SEG03 PB4/SEG04 PB5/SEG05 PB6/SEG06 PB7/SEG07 PC0/SEG08 PC1/SEG09 PC2/SEG10 PC3/SEG11 PC4/SEG12 PC5/SEG13 PC6/SEG14 PC7/SEG15 P60/SEG16/ PPG10 P61/SEG17/ PPG11 P62/SEG18/ TO10 I/O circuit type* S General-purpose I/O port. Function M General-purpose I/O port. The pins are shared with LCDC COM output (COM0 to COM3). M General-purpose I/O port. The pins are shared with LCDC SEG output (SEG00 to SEG07). M General-purpose I/O port. The pins are shared with LCDC SEG output (SEG08 to SEG15). M General-purpose I/O port. The pins are shared with LCDC SEG output (SEG16, SEG17) and 8/16-bit PPG ch.1 output (PPG10, PPG11) . General-purpose I/O port. The pin is shared with LCDC SEG output (SEG18) and 8/16-bit compound timer ch.1 output (TO10) . (Continued) 50 9 MB95160M Series (Continued) Pin no. Pin name P63/SEG19/ TO11 P64/SEG20/ EC1 M 53 P65/SEG21/ SCK P66/SEG22/ SOT P67/SEG23/ SIN P07/INT07/ AN07/SEG24 P06/INT06/ AN06/SEG25 P05/INT05/ AN05/SEG26 P04/INT04/ AN04/SEG27 P03/INT03/ AN03/SEG28 P02/INT02/ AN02/SEG29 P01/INT01/ AN01/SEG30 P00/INT00/ AN00/SEG31 AVSS ⎯ Power supply pin (GND) of A/D converter General-purpose I/O port. The pins are shared with external interrupt input (INT00 to INT07) , A/D analog input (AN00 to AN07) and LCDC SEG output (SEG24 to SEG31) . I/O circuit type* Function General-purpose I/O port. The pin is shared with LCDC SEG output (SEG19) and 8/16-bit compound timer ch.1 output (TO11) . General-purpose I/O port. The pin is shared with LCDC SEG output (SEG20) and 8/16-bit compound timer ch.1 clock input (EC1) . General-purpose I/O port. The pin is shared with LCDC SEG output (SEG21) and LIN-UART clock I/O (SCK) . General-purpose I/O port. The pin is shared with LCDC SEG output (SEG22) and LIN-UART data output (SOT) . N General-purpose I/O port. The pin is shared with LCDC SEG output (SEG23) and LIN-UART data input (SIN) . 51 52 54 55 56 57 58 59 60 61 62 63 64 F * : Refer to “■ I/O CIRCUIT TYPE” for details on the I/O circuit types. 10 MB95160M Series ■ I/O CIRCUIT TYPE Type A X1 (X1A) X 0 (X0A) Circuit Remarks • Oscillation circuit • High-speed side Feedback resistance : approx. 1 MΩ • Low-speed side Feedback resistance : approx. 10 MΩ Clock input N-ch Standby control B Mode input • Only for input • Hysteresis input B’ Reset output Reset input N-ch • Hysteresis input • Reset output F P-ch Digital output Digital output N-ch • • • • • CMOS output LCD output Hysteresis input Analog input Automotive input Analog input LCD output Hysteresis input A/D control LCD control Standby control External interrupt control Automotive input G R P-ch P-ch Pull-up control Digital output Digital output CMOS input Hysteresis input Automotive input • • • • • CMOS output CMOS input Hysteresis input With pull-up control Automotive input N-ch Standby control (Continued) 11 MB95160M Series Type H R P-ch Circuit Pull-up control P-ch Remarks • • • • CMOS output Hysteresis input With pull-up control Automotive input Digital output Digital output N-ch Hysteresis input Standby control I Digital output N-ch Automotive input • • • • N-ch open drain output CMOS input Hysteresis input Automotive input CMOS input Standby control M P-ch Hysteresis input Automotive input • • • • CMOS output LCD output Hysteresis input Automotive input Digital output Digital output N-ch LCD output Hysteresis input Automotive input • • • • • CMOS output LCD output CMOS input Hysteresis input Automotive input LCD control Standby control N P-ch Digital output Digital output N-ch LCD output CMOS input LCD control Standby control Hysteresis input Automotive input (Continued) 12 MB95160M Series (Continued) Type R P-ch Circuit Digital output Digital output N-ch Remarks • • • • CMOS output LCD power supply Hysteresis input Automotive input LCD built-in internal split resistor I/O Standby control LCD control S P-ch Hysteresis input Automotive input • • • • CMOS output LCD power supply Hysteresis input Automotive input Digital output Digital output N-ch Standby control Hysteresis input Automotive input 13 MB95160M Series ■ HANDLING DEVICES • Preventing Latch-up Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used. Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC pin and VSS pin. When latch-up occurs, power supply current increases rapidly and might thermally damage elements. • Stable Supply Voltage Supply voltage should be stabilized. A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range of the Vcc power-supply voltage. For stabilization, in principle, keep the variation in Vcc ripple (p-p value) in a commercial frequency range (50/60 Hz) not to exceed 10% of the standard Vcc value and suppress the voltage variation so that the transient variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched. • Precautions for Use of External Clock Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from sub clock mode or stop mode. PIN CONNECTION • Treatment of Unused Pin Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. If there is unused output pin, make it to open. • Power Supply Pins In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS pins near this device. 14 MB95160M Series • Mode Pin (MOD) Connect the MOD pin directly to VCC or VSS. To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the MOD pin to VCC or VSS and to provide a low-impedance connection. Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC pin must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the diagram below. • C pin connection diagram C CS • Analog Power Supply Always set the same potential to AVCC and VCC pins. When VCC > AVCC, the current may flow through the AN00 to AN07 pins. • Treatment of Power Supply Pins on A/D Converter Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D converter is not in use. Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 µF ceramic capacitor as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device. 15 MB95160M Series ■ PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL PROGRAMMER • Supported Parallel Programmers and Adapters The following table lists supported parallel programmers and adapters. Package Applicable adapter model FPT-64P-M23 FPT-64P-M24 TEF110-95F168HPMC TEF110-95F168HPMC1 Parallel programmers AF9708 (Ver 02.35G or more) AF9709/B (Ver 02.35G or more) AF9723+AF9834 (Ver 02.08E or more) Note : For information on applicable adapter models and parallel programmers, contact the following: Flash Support Group, Inc. TEL: +81-53-428-8380 • Sector Configuration The individual sectors of Flash memory correspond to addresses used for CPU access and programming by the parallel programmer as follows: Flash memory 60 Kbytes FFFFH 1FFFFH CPU address 1000H Programmer address* 11000H *: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer programs data into Flash memory. These programmer addresses are used for the parallel programmer to program or erase data in Flash memory. • Programming Method 1) Set the type code of the parallel programmer to 17222. 2) Load program data to programmer addresses 11000H to 1FFFFH. 3) Programmed by parallel programmer 16 MB95160M Series ■ BLOCK DIAGRAM F2MC-8FX CPU RST X0/X1 X0A/X1A Reset control Clock control Watch prescaler Watch counter P00/INT00 to P07/INT07 P10/UI0 P11/UO0 P12/UCK0 P13/TRG0/ADTG P14/PPG0 P20/PPG00 P21/PPG01 P22/TO00 P23/TO01/SCL0 P24/EC0/SDA0 (P00/AN00 to P07/AN07) AVCC AVSS AVR Port Other pins MOD, VSS, VCC, C Port 8/10-bit A/D converter P94/P95 8/16-bit compound timer ch.0 LCDC I2C 16-bit PPG Internal bus UART/SIO 8/16-bit compound timer ch.1 External interrupt 8/16-bit PPG ch.1 P60/SEG16/PPG10 P61/SEG17/PPG11 P62/SEG18/TO10 P63/SEG19/TO11 P64/SEG20/EC1 P65/SEG21/SCK LIN-UART P66/SEG22/SOT P67/SEG23/SIN P90/V3 to P93/V0 PA0/COM0 to PA3/COM3 PB0/SEG00 to PB7/SEG07 PC0/SEG08 to PC7/SEG15 (P00/SEG31 to P07/SEG24) ROM RAM Interrupt control Wild register 8/16-bit PPG ch.0 17 MB95160M Series ■ CPU CORE 1. Memory space Memory space of the MB95160M series is 64 Kbytes and consists of I/O area, data area, and program area. The memory space includes special-purpose areas such as the general-purpose registers and vector table. Memory map of the MB95160M series is shown below. • Memory Map MB95F168M MB95F168N MB95F168J 0000H I/O 0080H RAM 2Kbytes 0100H Register 0200H 0880H Access prohibited 0F80H Exterded I/O 1000H 1000H 0F80H 0080H 0000H MB95FV100D-103 I/O RAM 3.75Kbytes 0100H Register 0200H Exterded I/O Flash memory 60Kbytes Flash memory 60Kbytes FFFFH FFFFH 18 MB95160M Series 2. Register The MB95160M series has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The dedicated registers are as follows: Program counter (PC) : A 16-bit register to indicate locations where instructions are stored. Accumulator (A) : A 16-bit register for temporary storage of arithmetic operations. In the case of an 8-bit data processing instruction, the lower 1 byte is used. Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator. In the case of an 8-bit data processing instruction, the lower 1 byte is used. Index register (IX) : A 16-bit register for index modification. Extra pointer (EP) : A 16-bit pointer to point to a memory address. Stack pointer (SP) : A 16-bit register to indicate a stack area. Program status (PS) : A 16-bit register for storing a register bank pointer, a direct bank pointer, and a condition code register. 16-bit PC AH TH IX EP SP PS AL TL Initial Value : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status FFFDH 0000H 0000H 0000H 0000H 0000H 0030H The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer (DP) and the lower 8 bits for use as a condition code register (CCR). (Refer to the diagram below.) • Structure of the Program Status bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 PS R4 R3 R2 R1 R0 DP2 DP1 bit 8 DP0 bit 7 H bit 6 I bit 5 IL1 bit 4 IL0 bit 3 N bit 2 Z bit 1 V bit 0 C RP DP CCR 19 MB95160M Series The RP indicates the address of the register bank currently being used. The relationship between the content of RP and the real address conforms to the conversion rule illustrated below: • Rule for Conversion of Actual Addresses in the General-purpose Register Area RP upper "0" "0" "0" "0" "0" "0" "0" "1" A8 R4 A7 R3 A6 R2 A5 R1 A4 R0 A3 OP code lower b2 A2 b1 A1 b0 A0 Generated address A15 A14 A13 A12 A11 A10 A9 The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct addresses to 0080H to 00FFH. Direct bank pointer (DP2 to DP0) Specified address area Mapping area XXXB (no effect to mapping) 000B (initial value) 001B 010B 011B 100B 101B 110B 111B 0080H to 00FFH 0000H to 007FH 0000H to 007FH (without mapping) 0080H to 00FFH (without mapping) 0100H to 017FH 0180H to 01FFH 0200H to 027FH 0280H to 02FFH 0300H to 037FH 0380H to 03FFH 0400H to 047FH The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that control CPU operations at interrupt. : Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. This flag is for decimal adjustment instructions. I flag : Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”. The flag is set to “0” when reset. IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level is higher than the value indicated by these bits. IL1 0 0 1 1 N flag Z flag V flag C flag IL0 0 1 0 1 Interrupt level 0 1 2 3 Low (no interruption) Priority High H flag : Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the bit is set to “0”. : Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise. : Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0” otherwise. : Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. Set to the shift-out value in the case of a shift instruction. 20 MB95160M Series The following general-purpose registers are provided: General-purpose registers: 8-bit data storage registers The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8-register. Up to a total of 32 banks can be used on the MB95160M series. The bank currently in use is specified by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0) to general-purpose register 7 (R7). • Register Bank Configuration 8-bit 1F8H This address = 0100H + 8 × (RP) Address 100H R0 R1 R2 R3 R4 R5 107H R6 R7 Bank 0 R0 R0 R1 R2 R3 R4 R5 R6 R7 R1 R2 R3 R4 R5 R6 1FFH R7 Bank 31 32 banks 32 banks (RAM area) The number of banks is limited by the usable RAM capacitance. Memory area 21 MB95160M Series ■ I/O MAP Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H to 0015H 0016H 0017H 0018H to 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H 0023H 0024H to 002CH Register abbreviation PDR0 DDR0 PDR1 DDR1 ⎯ WATR PLLC SYCC STBC RSRR TBTC WPCR WDTC ⎯ PDR2 DDR2 ⎯ PDR6 DDR6 ⎯ PDR9 DDR9 PDRA DDRA PDRB DDRB PDRC DDRC ⎯ Register name Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register (Disabled) Oscillation stabilization wait time setting register PLL control register System clock control register Standby control register Reset factor register Time-base timer control register Watch prescaler control register Watchdog timer control register (Disabled) Port 2 data register Port 2 direction register (Disabled) Port 6 data register Port 6 direction register (Disabled) Port 9 data register Port 9 direction register Port A data register Port A direction register Port B data register Port B direction register Port C data register Port C direction register (Disabled) R/W R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W R/W R/W ⎯ R/W R/W ⎯ R/W R/W ⎯ R/W R/W R/W R/W R/W R/W R/W R/W ⎯ Initial value 00000000B 00000000B 00000000B 00000000B ⎯ 11111111B 00000000B 1010X011B 00000000B XXXXXXXXB 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B ⎯ 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ (Continued) 22 MB95160M Series Address 002DH 002EH 002FH to 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH to 0041H 0042H 0043H 0044H to 0047H 0048H 0049H 004AH 004BH 004CH to 004FH 0050H 0051H 0052H 0053H 0054H 0055H 0056H 0057H 0058H Register abbreviation PUL1 PUL2 ⎯ T01CR1 T00CR1 T11CR1 T10CR1 PC01 PC00 PC11 PC10 ⎯ PCNTH0 PCNTL0 ⎯ EIC00 EIC10 EIC20 EIC30 ⎯ SCR SMR SSR RDR/TDR ESCR ECCR SMC10 SMC20 SSR0 Register name Port 1 pull-up register Port 2 pull-up register (Disabled) 8/16-bit compound timer 01 control status register 1 ch.0 8/16-bit compound timer 00 control status register 1 ch.0 8/16-bit compound timer 11 control status register 1 ch.1 8/16-bit compound timer 10 control status register 1 ch.1 8/16-bit PPG1 control register ch.0 8/16-bit PPG0 control register ch.0 8/16-bit PPG1 control register ch.1 8/16-bit PPG0 control register ch.1 (Disabled) 16-bit PPG status control register (upper byte) ch.0 16-bit PPG status control register (lower byte) ch.0 (Disabled) External interrupt circuit control register ch.0/ch.1 External interrupt circuit control register ch.2/ch.3 External interrupt circuit control register ch.4/ch.5 External interrupt circuit control register ch.6/ch.7 (Disabled) LIN-UART serial control register LIN-UART serial mode register LIN-UART serial status register LIN-UART reception/transmission data register LIN-UART extended status control register LIN-UART extended communication control register UART/SIO serial mode control register 1 ch.0 UART/SIO serial mode control register 2 ch.0 UART/SIO serial status register ch.0 R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W R/W R/W ⎯ R/W R/W ⎯ R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00001000B 00000000B 00000100B 000000XXB 00000000B 00100000B 00000001B (Continued) 23 MB95160M Series Address 0059H 005AH 005BH to 005FH 0060H 0061H 0062H 0063H 0064H 0065H 0066H to 006BH 006CH 006DH 006EH 006FH 0070H 0071H 0072H 0073H 0074H 0075H 0076H 0077H 0078H 0079H 007AH 007BH 007CH 007DH 007EH 007FH 0F80H Register abbreviation TDR0 RDR0 ⎯ IBCR00 IBCR10 IBSR0 IDDR0 IAAR0 ICCR0 ⎯ ADC1 ADC2 ADDH ADDL WCSR ⎯ FSR SWRE0 SWRE1 ⎯ WREN WROR ⎯ ILR0 ILR1 ILR2 ILR3 ILR4 ILR5 ⎯ WRARH0 2 Register name UART/SIO serial output data register ch. 0 UART/SIO serial input data register ch.0 (Disabled) I2C bus control register 0 ch.0 I C bus control register 1 ch.0 I C bus status register ch.0 I2C data register ch.0 I2C address register ch.0 I C clock control register ch.0 (Disabled) 8/10-bit A/D converter control register 1 8/10-bit A/D converter control register 2 8/10-bit A/D converter data register (upper byte) 8/10-bit A/D converter data register (lower byte) Watch counter status register (Disabled) Flash memory status register Flash memory sector writing control register 0 Flash memory sector writing control register 1 (Disabled) Wild register address compare enable register Wild register data test setting register Register bank pointer (RP) , Mirror of direct bank pointer (DP) Interrupt level setting register 0 Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt level setting register 4 Interrupt level setting register 5 (Disabled) Wild register address setting register (upper byte) ch.0 2 2 R/W R/W R ⎯ R/W R/W R R/W R/W R/W ⎯ R/W R/W R/W R/W R/W ⎯ R/W R/W R/W ⎯ R/W R/W ⎯ R/W R/W R/W R/W R/W R/W ⎯ R/W Initial value 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ 000X0000B 00000000B 00000000B ⎯ 00000000B 00000000B ⎯ 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B ⎯ 00000000B (Continued) 24 MB95160M Series Address 0F81H 0F82H 0F83H 0F84H 0F85H 0F86H 0F87H 0F88H 0F89H to 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H 0F98H 0F99H 0F9AH 0F9BH 0F9CH 0F9DH 0F9EH 0F9FH 0FA0H 0FA1H 0FA2H 0FA3H 0FA4H 0FA5H 0FA6H to 0FA9H Register abbreviation WRARL0 WRDR0 WRARH1 WRARL1 WRDR1 WRARH2 WRARL2 WRDR2 ⎯ T01CR0 T00CR0 T01DR T00DR TMCR0 T11CR0 T10CR0 T11DR T10DR TMCR1 PPS01 PPS00 PDS01 PDS00 PPS11 PPS10 PDS11 PDS10 PPGS REVC ⎯ Register name Wild register address setting register (lower byte) ch.0 Wild register data setting register ch.0 Wild register address setting register (upper byte) ch.1 Wild register address setting register (lower byte) ch.1 Wild register data setting register ch.1 Wild register address setting register (upper byte) ch.2 Wild register address setting register (lower byte) ch.2 Wild register data setting register ch.2 (Disabled) 8/16-bit compound timer 01 control status register 0 ch.0 8/16-bit compound timer 00 control status register 0 ch.0 8/16-bit compound timer 01 data register ch.0 8/16-bit compound timer 00 data register ch.0 8/16-bit compound timer 00/01 timer mode control register ch.0 8/16-bit compound timer 11 control status register 0 ch.1 8/16-bit compound timer 10 control status register 0 ch.1 8/16-bit compound timer 11 data register ch.1 8/16-bit compound timer 10 data register ch.1 8/16-bit compound timer 10/11 timer mode control register ch.1 8/16-bit PPG1 cycle setting buffer register ch.0 8/16-bit PPG0 cycle setting buffer register ch.0 8/16-bit PPG1 duty setting buffer register ch.0 8/16-bit PPG0 duty setting buffer register ch.0 8/16-bit PPG1 cycle setting buffer register ch.1 8/16-bit PPG0 cycle setting buffer register ch.1 8/16-bit PPG1 duty setting buffer register ch.1 8/16-bit PPG0 duty setting buffer register ch.1 8/16-bit PPG start register 8/16-bit PPG output inversion register (Disabled) R/W R/W R/W R/W R/W R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ⎯ Initial value 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B ⎯ (Continued) 25 MB95160M Series Address 0FAAH 0FABH 0FACH 0FADH 0FAEH 0FAFH 0FB0H to 0FBBH 0FBCH 0FBDH 0FBEH 0FBFH 0FC0H to 0FC2H 0FC3H 0FC4H 0FC5H 0FC6H 0FC7H 0FC8H 0FC9H 0FCAH 0FCBH 0FCCH 0FCDH to 0FDCH 0FDDH to 0FE2H 0FE3H Register abbreviation PDCRH0 PDCRL0 PCSRH0 PCSRL0 PDUTH0 PDUTL0 ⎯ BGR1 BGR0 PSSR0 BRSR0 ⎯ AIDRL LCDCC LCDCE1 LCDCE2 LCDCE3 LCDCE4 LCDCE5 ⎯ LCDCB1 LCDCB2 LCDRAM Register name 16-bit PPG down counter register (upper byte) ch.0 16-bit PPG down counter register (lower byte) ch.0 16-bit PPG cycle setting buffer register (upper byte) ch.0 16-bit PPG cycle setting buffer register (lower byte) ch.0 16-bit PPG duty setting buffer register (upper byte) ch.0 16-bit PPG duty setting buffer register (lower byte) ch.0 (Disabled) LIN-UART baud rate generator register 1 LIN-UART baud rate generator register 0 UART/SIO dedicated baud rate generator prescaler selecting register ch.0 UART/SIO dedicated baud rate generator setting register ch.0 (Disabled) A/D input disable register (lower byte) LCDC control register LCDC enable register 1 LCDC enable register 2 LCDC enable register 3 LCDC enable register 4 LCDC enable register 5 (Disabled) LCDC blinking setting register 1 LCDC blinking setting register 2 LCDC display RAM R/W R R R/W R/W R/W R/W ⎯ R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W R/W ⎯ R/W R/W R/W Initial value 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B ⎯ 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00010000B 00110000B 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B ⎯ WCDR (Disabled) Watch counter data register ⎯ R/W ⎯ 00111111B (Continued) 26 MB95160M Series (Continued) Address 0FE4H to 0FE6H 0FE7H 0FE8H, 0FE9H 0FEAH 0FEBH to 0FEDH 0FEEH 0FEFH 0FF0H to 0FFFH Register abbreviation ⎯ ILSR2 ⎯ CSVCR ⎯ ILSR WICR ⎯ Register name R/W ⎯ R/W ⎯ R/W ⎯ R/W R/W ⎯ Initial value ⎯ 00000000B ⎯ 00011100B ⎯ 00000000B 01000000B ⎯ (Disabled) Input level select register 2 (Disabled) Clock supervisor control register (Disabled) Input level selecting register Interrupt pin control register (Disabled) • R/W access symbols R/W : Readable/Writable R : Read only W : Write only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value. 27 MB95160M Series ■ INTERRUPT SOURCE TABLE Interrupt source External interrupt ch.0 External interrupt ch.4 External interrupt ch.1 External interrupt ch.5 External interrupt ch.2 External interrupt ch.6 External interrupt ch.3 External interrupt ch.7 UART/SIO ch.0 8/16-bit compound timer ch.0 (Lower) 8/16-bit compound timer ch.0 (Upper) LIN-UART (reception) LIN-UART (transmission) 8/16-bit PPG ch.1 (Lower) 8/16-bit PPG ch.1 (Upper) (Unused) 8/16-bit PPG ch.0 (Upper) 8/16-bit PPG ch.0 (Lower) 8/16-bit compound timer ch.1 (Upper) 16-bit PPG ch.0 I2C ch.0 (Unused) 8/10-bit A/D converter Time-base timer Watch prescaler/Watch counter (Unused) 8/16-bit compound timer ch.1 (Lower) Flash memory Interrupt request number IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 IRQ20 IRQ21 IRQ22 IRQ23 Vector table address Upper FFFAH FFF8H FFF6H FFF4H FFF2H FFF0H FFEEH FFECH FFEAH FFE8H FFE6H FFE4H FFE2H FFE0H FFDEH FFDCH FFDAH FFD8H FFD6H FFD4H FFD2H FFD0H FFCEH FFCCH Lower FFFBH FFF9H FFF7H FFF5H FFF3H FFF1H FFEFH FFEDH FFEBH FFE9H FFE7H FFE5H FFE3H FFE1H FFDFH FFDDH FFDBH FFD9H FFD7H FFD5H FFD3H FFD1H FFCFH FFCDH Same level Bit name of priority order interrupt level (at simultaneous setting register occurrence) L00 [1 : 0] L01 [1 : 0] L02 [1 : 0] L03 [1 : 0] L04 [1 : 0] L05 [1 : 0] L06 [1 : 0] L07 [1 : 0] L08 [1 : 0] L09 [1 : 0] L10 [1 : 0] L11 [1 : 0] L12 [1 : 0] L13 [1 : 0] L14 [1 : 0] L15 [1 : 0] L16 [1 : 0] L17 [1 : 0] L18 [1 : 0] L19 [1 : 0] L20 [1 : 0] L21 [1 : 0] L22 [1 : 0] L23 [1 : 0] Low High 28 MB95160M Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol VCC, AVCC AVR Power supply voltage for LCD Input voltage*1 Output voltage*1 Maximum clamp current Total maximum clamp current “L” level maximum output current “L” level average current “L” level total maximum output current “L” level total average output current “H” level maximum output current “H” level average current “H” level total maximum output current “H” level total average output current Power consumption Operating temperature Storage temperature V0 to V3 VI VO ICLAMP Σ|ICLAMP| IOL Rating Min Vss − 0.3 Vss − 0.3 Vss − 0.3 Vss − 0.3 Vss − 0.3 − 2.0 ⎯ ⎯ Max Vss + 6.0 Vss + 6.0 Vss + 6.0 Vss + 6.0 Vss + 6.0 + 2.0 20 15 V V V mA mA mA Unit *2 *2 *3 *4 *4 Applicable to pins*5 Applicable to pins*5 Applicable to pins*5 Applicable to pins*5 Average output current = operating current × operating ratio (1 pin) Remarks Power supply voltage* 1 V IOLAV ⎯ 4 mA ΣIOL ΣIOLAV IOH ⎯ ⎯ ⎯ 100 mA Total average output current = operating current × operating ratio (Total of pins) Applicable to pins*5 Applicable to pins*5 Average output current = operating current × operating ratio (1 pin) 50 − 15 mA mA IOHAV ⎯ −4 mA ΣIOH ΣIOHAV Pd TA Tstg ⎯ ⎯ ⎯ − 10 − 55 − 100 − 50 320 + 85 + 150 mA Total average output current = operating current × operating ratio (Total of pins) mA mW °C °C (Continued) 29 MB95160M Series (Continued) *1 : The parameter is based on VSS = 0.0 V. *2 : Apply equal potential to AVCC and VCC. AVR should not exceed AVCC + 0.3 V. *3 : V0 to V3 should not exceed VCC + 0.3 V. *4 : VI and Vo should not exceed VCC + 0.3 V. VI must not exceed the rating voltage. However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *5 : Applicable to pins : P00 to P07, P10 to P14, P20 to P22,P60 to P67, P90 to P95, PA0 to PA3, PB0 to PB7, PC0 to PC7 • Use within recommended operating conditions. • Use at DC voltage (current). • + B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting resistance placed between the + B signal and the microcontroller. • The value of the limiting resistance should be set so that when the + B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this affects other devices. • Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. • Note that if the + B input is applied during power-on, the power supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. • Care must be taken not to leave the + B input pin open. • Note that analog system input/output pins other than the A/D input pins (LCD drive pins, etc.) cannot accept + B signal input. • Sample recommended circuits : • Input/Output Equivalent circuits Protective diode Limiting resistance Vcc P-ch N-ch R + B input (0 V to 16 V) WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 30 MB95160M Series 2. Recommended Operating Conditions (Vss = 0.0 V) Parameter Symbol Conditions Value Min 2.42*1,*2 Power supply voltage VCC, AVCC 2.3 2.7 2.3 V0 to V3 AVR CS TA ⎯ Max 5.5*1 5.5 5.5 5.5 V Unit Remarks In normal operating Other than Hold condition in STOP MB95FV100D103 mode MB95FV100DHold condition in STOP 103 mode The range of liquid crystal power supply: without up-conversion (The optimal value depends on liquid crystal display elements used.) In normal operating Power supply voltage for LCD A/D converter reference input voltage Smoothing capacitor Operating temperature VSS VCC V 4.0 0.1 − 10 +5 AVCC 1.0 + 85 +35 V µF °C °C *3 Other than MB95FV100D-103 MB95FV100D-103 *1 : The values vary with the operating frequency, machine clock or analog guarantee range. *2 : The value is 2.88 V when the low voltage detection reset is used. The device operates normally during the time between 2.88 V and low voltage detection, and between release voltage and 2.88 V. (Continued) 31 MB95160M Series (Continued) *3 : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC pin must have a capacitor value higher than CS. For connection of smoothing capacitor CS, refer to the diagram below. • C pin connection diagram C CS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 32 MB95160M Series 3. DC Characteristics (Vcc = 5.0 V ± 10%, Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Symbol VIH1 VIH2 Pin name P10, P67 P23, P24 P00 to P07, P10 to P14, P20 to P22, P60 to P67, P90 to P95, PA0 to PA3, PB0 to PB7, PC0 to PC7 P00 to P07, P10 to P14, P20 to P22, P60 to P67, P90 to P95, PA0 to PA3, PB0 to PB7, PC0 to PC7 Conditions *1 *1 Value Min 0.7 VCC 0.7 VCC Typ ⎯ ⎯ Max VCC + 0.3 VSS + 5.5 Unit V V Remarks When selecting CMOS input level VIHA ⎯ 0.8 VCC ⎯ VCC + 0.3 V Port inputs if Automotive input levels are selected “H” level input voltage VIHS1 *1 0.8 VCC ⎯ VCC + 0.3 V Hysteresis input VIHS2 P23, P24 VIHM RST, MOD VIL P10,P23, P24,P67 P00 to P07, P10 to P14, P20 to P24, P60 to P67, P90 to P95, PA0 to PA3, PB0 to PB7, PC0 to PC7 P00 to P07, P10 to P14, P20 to P24, P60 to P67, P90 to P95, PA0 to PA3, PB0 to PB7, PC0 to PC7 Output pins other than P00 to P07 *1 ⎯ *1 0.8 VCC 0.7 VCC VSS − 0.3 ⎯ ⎯ ⎯ VSS + 5.5 VCC + 0.3 0.3 VCC V V V CMOS input Hysteresis input (When selecting CMOS input level) VILA “L” level input voltage ⎯ VSS − 0.3 ⎯ 0.5 VCC V Port inputs if Automotive input levels are selected VILS *1 VSS − 0.3 ⎯ 0.2 VCC V Hysteresis input VILM RST, MOD “H” level output voltage VOH ⎯ IOH = − 4.0 mA VSS − 0.3 Vcc − 0.5 ⎯ ⎯ 0.3 VCC ⎯ V V Hysteresis input (Continued) 33 MB95160M Series (Vcc = 5.0 V ± 10%, Vss = 0.0 V, TA = − 40 °C to + 85 °C) Value Conditions Unit Remarks Min Typ Max IOL = 4.0 mA ⎯ ⎯ 0.4 V Parameter “L” level output voltage Input leakage current (Hi-Z output leakage current) Symbol VOL Pin name Output pins other than P00 to P07, RST*2 Ports other than P23, P24 P10 to P14, P20 to P22 ILI 0.0 V < VI < VCC −5 ⎯ +5 µA When the pull-up prohibition setting When the pull-up permission setting Pull-up resistor RPULL Input capacitance CIN VI = 0.0 V 25 ⎯ ⎯ ⎯ ⎯ ⎯ 50 5 9.5 30.0 15.2 35.7 100 15 12.5 35.0 20.0 42.5 kΩ pF Other than AVCC, f = 1 MHz AVSS, AVR, VCC, VSS FCH = 20 MHz FMP = 10 MHz Main clock mode (divided by 2) At other than Flash mA memory writing and erasing mA At Flash memory writing and erasing ICC FCH = 32 MHz FMP = 16 MHz Main clock mode (divided by 2) FCH = 20 MHz FMP = 10 MHz Main Sleep mode (divided by 2) VCC (External clock operation) FCH = 32 MHz FMP = 16 MHz Main Sleep mode (divided by 2) FCL = 32 kHz FMPL = 16 kHz Sub clock mode (divided by 2) TA = + 25 °C FCL = 32 kHz FMPL = 16 kHz Sub sleep mode (divided by 2) TA = + 25 °C FCL = 32 kHz Watch mode Main stop mode TA = + 25 °C At other than Flash mA memory writing and erasing mA At Flash memory writing and erasing ⎯ 4.5 7.5 mA ICCS Power supply current*3 ⎯ 7.2 12.0 mA ICCL ⎯ 45 100 µA ICCLS ⎯ 10 81 µA ICCT ⎯ 4.6 27.0 µA (Continued) 34 MB95160M Series (Continued) Symbol (Vcc = 5.0 V ± 10%, Vss = 0.0 V, TA = − 40 °C to + 85 °C) Pin name Conditions FCH = 4 MHz FMP = 10 MHz Main PLL mode (multiplied by 2.5) FCH = 6.4 MHz FMP = 16 MHz Main PLL mode (multiplied by 2.5) VCC (External clock operation) FCL = 32 kHz FMPL = 128 kHz Sub PLL mode (multiplied by 4) , TA = + 25 °C FCH = 10 MHz Time-base timer mode TA = + 25 °C Sub stop mode TA = + 25 °C FCH = 16 MHz At operating of A/D conversion AVCC IAH LCD internal division resistance COM0 to COM3 output impedance SEG00 to SEG31 output impedance LCD leak current FCH = 16 MHz At stopping of A/D conversion TA = + 25 °C ⎯ COM0 to COM3 V1 to V3 = 5.0 V RVSEG SEG00 to SEG31 ILCDL V0 to V3, COM0 to COM3 SEG00 to SEG31 ⎯ ⎯ −1 ⎯ ⎯ 7 +1 kΩ µA Between V3 and VSS Value Min ⎯ Typ 9.3 Max 12.5 Unit Remarks Parameter mA ICCMPLL ⎯ 14.9 20.0 mA ICCSPLL Power supply current*3 ICTS ⎯ 160 400 µA ⎯ 0.15 1.10 mA ICCH IA ⎯ ⎯ 5 2.4 20 4.7 µA mA ⎯ 1 5 µA RLCD RVCOM ⎯ ⎯ 300 ⎯ ⎯ 5 kΩ kΩ *1 : The value is 2.88 V when the low voltage detection reset is used. *2 : Product without clock supervisor only *3 : • The power-supply current is determined by the external clock. When both low voltage detection option and clock supervisor option are selected, the power-supply current will be a value of adding current consumption of the low voltage detection circuit (ILVD) and current consumption of built-in CR oscillator (ICSV) to the specified value. • Refer to “4. AC Characteristics (1) Clock Timing” for FCH and FCL. • Refer to “4. AC Characteristics (2) Source Clock/Machine Clock” for FMP and FMPL. 35 MB95160M Series 4. AC Characteristics (1) Clock Timing (Vcc = 2.42 V to 5.5 V, Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter SymPin name Conditions bol Value Min 1.00 1.00 FCH Clock frequency X0, X1 3.00 3.00 3.00 3.00 FCL X0A, X1A ⎯ tHCYL tLCYL Input clock pulse width Input clock rise time and fall time tWH1 tWL1 tWH2 tWL2 tCR tCF X0, X1 X0A, X1A X0 X0A X0, X0A ⎯ ⎯ 61.5 30.8 ⎯ 61.5 ⎯ ⎯ Typ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 32.768 32.768 ⎯ ⎯ 30.5 ⎯ 15.2 ⎯ Max 16.25 32.50 10.00 8.13 6.50 4.06 ⎯ ⎯ 1000 1000 ⎯ ⎯ ⎯ 5 Unit MHz Remarks When using main oscillation circuit MHz When using external clock MHz Main PLL multiplied by 1 MHz Main PLL multiplied by 2 MHz Main PLL multiplied by 2.5 MHz Main PLL multiplied by 4 kHz kHz ns ns µs ns µs ns When using sub oscillation circuit When using sub PLL When using oscillation circuit When using external clock When using sub clock When using external clock Duty ratio is about 30% to 70%. When using external clock Clock cycle time 36 MB95160M Series • Input wave form for using external clock (main clock) tHCYL tWH1 tCR tCF 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC tWL1 X0 • Figure of Main Clock Input Port External Connection When using a crystal or ceramic oscillator Microcontroller X0 X1 FCH C1 C2 When using external clock Microcontroller X0 X1 Open FCH • Input wave form for using external clock (sub clock) tLCYL tWH2 tCR tCF 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC tWL2 X0A • Figure of Sub clock Input Port External Connection When using a crystal or ceramic oscillator Microcontroller X0A X1A FCL C1 C2 When using external clock Microcontroller X0A X1A Open FCL 37 MB95160M Series (2) Source Clock/Machine Clock (Vcc = 5.0 V ± 10%, Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Sym- Condibol tions Value Min 61.5 Typ ⎯ Max 2000 Unit Remarks When using main clock Min : FCH = 8.125 MHz, PLL multiplied by 2 Max : FCH = 1 MHz, divided by 2 When using sub clock Min : FCL = 32 kHz, PLL multiplied by 4 Max : FCL = 32 kHz, divided by 2 Source clock cycle time*1 (Clock before setting tSCLK division) ns 7.6 FSP FSPL ⎯ 0.50 16.384 61.5 tMCLK 7.6 FMP FMPL 0.031 1.024 ⎯ ⎯ ⎯ ⎯ 61.0 16.25 µs Source clock frequency MHz When using main clock When using main clock Min : FSP = 16.25 MHz, no division Max : FSP = 0.5 MHz, divided by 16 When using sub clock Min : FSPL = 131 kHz, no division Max : FSPL = 16 kHz, divided by 16 131.072 kHz When using sub clock 32000 ns Machine clock cycle time*2 (Minimum instruction execution time) Machine clock frequency ⎯ ⎯ ⎯ 976.5 16.250 µs MHz When using main clock 131.072 kHz When using sub clock *1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes the machine clock. Further, the source clock can be selected as follows. • Main clock divided by 2 • PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication) • Sub clock divided by 2 • PLL multiplication of sub clock (select from 2, 3, 4 multiplication) *2 : Operation clock of the microcontroller. Machine clock can be selected as follows. • Source clock (no division) • Source clock divided by 4 • Source clock divided by 8 • Source clock divided by 16 38 MB95160M Series • Outline of clock generation block FCH (main oscillation) Divided by 2 Main PLL ×1 ×2 × 2.5 ×4 SCLK ( source clock ) FCL (sub oscillation) Divided by 2 Clock mode select bit ( SYCC : SCS1, SCS0 ) Division circuit ×1 × 1/4 × 1/8 × 1/16 MCLK ( machine clock ) Sub PLL ×2 ×3 ×4 39 MB95160M Series • Operating voltage - Operating frequency (When TA = − 40 °C to + 85 °C) • MB95F168M/F168N/F168J Sub PLL, sub clock mode and watch mode operation guarantee range 5.5 5.5 Main clock mode and main PLL mode operation guarantee range Operating voltage (V) Operating voltage (V) 3.5 2.42 2.42 16.384 kHz 32 kHz 131.072 kHz 0.5 MHz 3 MHz 10 MHz 16.25 MHz PLL operation guarantee range PLL operation guarantee range Main clock operation guarantee range Source clock frequency (FSPL) Source clock frequency (FSP) • Operating voltage - Operating frequency (When TA = + 5 °C to + 35 °C) • MB95FV100D-103 Sub PLL, sub clock mode and watch mode operation guarantee range 5.5 5.5 Main clock mode and main PLL mode operation guarantee range Operating voltage (V) Operating voltage (V) 3.5 2.7 2.7 16.384 kHz 32 kHz 131.072 kHz 0.5MHz 3 MHz 10 MHz 16.25 MHz PLL operation guarantee range PLL operation guarantee range Main clock operation guarantee range Source clock frequency (FSP) Source clock frequency (FSP) 40 MB95160M Series • Main PLL operation frequency [MHz] 16.25 16 15 ×4 12 × 2.5 10 Source clock frequency (FSP) ×2 ×1 7.5 6 5 3 0 3 4 4.062 5 6.4 6.5 8 8.125 10 [MHz] Main clock frequency (FMP) 41 MB95160M Series (3) External Reset (Vcc = 5.0 V ± 10%, Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Symbol Pin name Conditions Value Min 2 tMCLK*1 Oscillation time of oscillator*2 + 100 100 *1 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. *2 : Oscillation time of oscillator is the time that the amplitude reaches 90%. In the crystal oscillator, the oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of µs and several ms. In the external clock, the oscillation time is 0 ms. • At normal operating Max ⎯ ⎯ Unit ns µs Remarks At normal operating At stop mode, sub clock mode, sub sleep mode, and watch mode At time-base timer mode RST “L” level pulse width tRSTL RST ⎯ ⎯ µs tRSTL RST 0.2 VCC 0.2 VCC • At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on tRSTL 0.2 VCC 0.2 VCC RST 90% of amplitude X0 Internal operating clock Oscillation time of oscillator Internal reset 100 µs Oscillation stabilization wait time Execute instruction 42 MB95160M Series (4) Power-on Reset (Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Power supply rising time Power supply cutoff time Symbol tR VCC tOFF ⎯ 1 ⎯ ms Pin name Conditions Value Min ⎯ Max 50 Unit ms Waiting time until power-on Remarks tR 2.5 V tOFF VCC 0.2 V 0.2 V 0.2 V Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power supply voltages during operation, set the slope of rising within 30 mV/ms as shown below. VCC 2.3 V Limiting the slope of rising within 30 mV/ms is recommended. Hold condition in stop mode VSS 43 MB95160M Series (5) Peripheral Input Timing (Vcc = 5.0 V ± 10%, Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Peripheral input “H” pulse width Peripheral input “L” pulse width Symbol tILIH tIHIL Pin name Conditions Value Min 2 tMCLK* ⎯ 2 tMCLK* ⎯ ns Max ⎯ Unit ns INT00 to INT07, EC0, EC1, TRG0/ADTG * : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. tILIH tIHIL INT00 to INT07, EC0, EC1, TRG0/ADTG 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 44 MB95160M Series (6) UART/SIO, Serial I/O Timing (Vcc = 5.0 V ± 10%, Vss = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Serial clock cycle time UCK ↓ → UO time Valid UI → UCK ↑ UCK ↑ → valid UI hold time Serial clock “H” pulse width Serial clock “L” pulse width UCK ↓ → UO time Valid UI → UCK ↑ UCK ↑ → valid UI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name UCK0 UCK0, UO0 UCK0, UI0 UCK0, UI0 UCK0 UCK0 UCK0, UO0 UCK0, UI0 UCK0, UI0 External clock operation output pin : CL = 80 pF + 1TTL. Conditions Internal clock operation output pin : CL = 80 pF + 1TTL. Value Min 4 tMCLK* − 190 2 tMCLK* 2 tMCLK* 4 tMCLK* 4 tMCLK* ⎯ 2 tMCLK* 2 tMCLK* Max ⎯ + 190 ⎯ ⎯ ⎯ ⎯ 190 ⎯ ⎯ Unit ns ns ns ns ns ns ns ns ns * : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. • Internal shift clock mode tSCYC UCK0 2.4 V 0.8 V tSLOV 0.8 V UO0 2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC UI0 0.8 VCC 0.2 VCC • External shift clock mode tSLSH tSHSL 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tSLOV UCK0 UO0 2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC UI0 0.8 VCC 0.2 VCC 45 MB95160M Series (7) LIN-UART Timing Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2 (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0) (Vcc = 5.0 V ± 10%, Vss = 0.0 V, TA = −40 °C to + 85 °C) Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time Serial clock “L” pulse width Serial clock “H” pulse width SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time SCK fall time SCK rise time SymPin name bol tSCYC tSLOVI tIVSHI tSHIXI tSLSH tSHSL tIVSHE tSHIXE tF tR SCK Conditions Value Min 5 tMCLK*3 Max ⎯ + 95 ⎯ ⎯ ⎯ ⎯ 2t MCLK 3 Unit ns ns ns ns ns ns ns ns ns ns ns Internal clock SCK, SOT −95 operation output pin : SCK, SIN CL = 80 pF + 1 TTL. tMCLK*3 + 190 SCK, SIN 0 SCK SCK SCK, SIN SCK, SIN SCK SCK External clock operation output pin : CL = 80 pF + 1 TTL. 3 tMCLK*3 − tR t MCLK 3 * + 95 tSLOVE SCK, SOT ⎯ 190 tMCLK*3 + 95 ⎯ ⎯ * + 95 ⎯ ⎯ 10 10 *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. 46 MB95160M Series • Internal shift clock mode tSCYC 2.4 V 0.8 V tSLOVI 2.4 V 0.8 V tIVSHI tSHIXI 0.8 V SCK SOT SIN 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSLSH tSHSL 0.8 VCC 0.2 VCC tF tSLOVE 2.4 V 0.8 V tIVSHE tSHIXE 0.2 VCC tR 0.8 VCC SCK SOT SIN 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 47 MB95160M Series Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2 (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0) (VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = −40 °C to + 85 °C) Parameter Serial clock cycle time SCK↑→ SOT delay time Valid SIN→SCK↓ SCK↓→ valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK↑ →SOT delay time Valid SIN→SCK↓ SCK↓→ valid SIN hold time SCK fall time SCK rise time Symbol tSCYC tSHOVI tIVSLI tSLIXI tSHSL tSLSH tSHOVE tIVSLE tSLIXE tF tR Pin name SCK SCK, SOT Internal clock operation output pin : SCK, SIN CL = 80 pF + 1 TTL. SCK, SIN SCK SCK SCK, SOT External clock SCK, SIN operation output pin : SCK, SIN CL = 80 pF + 1 TTL. SCK SCK t Conditions Value Min 5 tMCLK*3 −95 MCLK 3 Max ⎯ + 95 ⎯ ⎯ ⎯ ⎯ 2t MCLK 3 Unit ns ns ns ns ns ns ns ns ns ns ns * + 190 0 3 tMCLK*3 − tR tMCLK*3 + 95 ⎯ 190 tMCLK*3 + 95 ⎯ ⎯ * + 95 ⎯ ⎯ 10 10 *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. 48 MB95160M Series • Internal shift clock mode tSCYC SCK 2.4 V 0.8 V tSHOVI 2.4 V 0.8 V tIVSLI tSLIXI 2.4 V SOT SIN 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSHSL tSLSH 0.8 VCC 0.2 VCC tSHOVE 2.4 V 0.8 V tIVSLE tSLIXE tF 0.2 VCC SCK 0.2 VCC tR 0.8 VCC SOT SIN 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 49 MB95160M Series Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2 (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1) (VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = −40 °C to + 85 °C) Parameter Serial clock cycle time SCK↑→ SOT delay time Valid SIN→SCK↓ SCK↓→ valid SIN hold time SOT→SCK↓ delay time Symbol tSCYC tSHOVI tIVSLI tSLIXI tSOVLI Pin name SCK SCK, SOT SCK, SIN SCK, SIN SCK, SOT Internal clock operation output pin : CL = 80 pF + 1 TTL. t Conditions Value Min 5 tMCLK*3 −95 MCLK 3 Max ⎯ + 95 ⎯ ⎯ 4 tMCLK*3 Unit ns ns ns ns ns * + 190 0 ⎯ *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. tSCYC SCK 0.8 V tSOVLI 2.4 V 0.8 V tIVSLI 2.4 V tSHOVI 2.4 V 0.8 V tSLIXI 0.8 VCC 0.2 VCC 0.8 V SOT SIN 0.8 VCC 0.2 VCC 50 MB95160M Series Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2 (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1) (VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = −40 °C to + 85 °C) Parameter Serial clock cycle time SCK↓→SOT delay time Valid SIN→SCK↑ SCK↑ → valid SIN hold time SOT→SCK↑ delay time Symbol tSCYC tSLOVI tIVSHI tSHIXI tSOVHI Pin name SCK SCK, SOT Internal clock SCK, SIN operation output pin : CL = 80 pF + 1 TTL. SCK, SIN t Conditions Value Min 5 tMCLK*3 −95 MCLK 3 Max ⎯ + 95 ⎯ ⎯ 4 tMCLK*3 Unit ns ns ns ns ns * + 190 0 ⎯ SCK, SOT *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. tSCYC SCK tSOVHI 2.4 V 0.8 V tSLOVI 2.4 V 0.8 V tIVSHI tSHIXI 0.8 VCC 0.2 VCC 2.4 V 0.8 V 2.4 V SOT SIN 0.8 VCC 0.2 VCC 51 MB95160M Series (8) I2C Timing (VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Value Parameter SCL clock frequency (Repeat) Start condition hold time SDA ↓ → SCL ↓ SCL clock “L” width SCL clock “H” width (Repeat) Start condition setup time SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓ ↑ Data setup time SDA ↓ ↑ → SCL ↑ Stop condition setup time SCL ↑ → SDA ↑ Bus free time between stop condition and start condition Symbol fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF Pin name SCL0 SCL0 SDA0 SCL0 SCL0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 R = 1.7 kΩ, C = 50 pF*1 Conditions Standard-mode Min 0 4.0 4.7 4.0 4.7 0 0.25*4 4.0 4.7 Max 100 ⎯ ⎯ ⎯ ⎯ 3.45*2 ⎯ ⎯ ⎯ Fast-mode Min 0 0.6 1.3 0.6 0.6 0 0.1*4 0.6 1.3 Max 400 ⎯ ⎯ ⎯ ⎯ 0.9*3 ⎯ ⎯ ⎯ kHz µs µs µs µs µs µs µs µs Unit *1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : The maximum tHD;DAT have only to be met if the device dose not stretch the “L” width (tLOW) of the SCL signal. *3 : A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. *4 : Refer to “ • Note of SDA and SCL set-up time”. • Note of SDA and SCL set-up time SDA0 Input data set-up time SCL0 6 tcp Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending on the load capacitance or pull-up resistor. Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be satisfied. 52 MB95160M Series tWAKEUP SDA0 tLOW SCL0 tHD;STA tSU;DAT tSU;STA tSU;STO tHD;DAT tHIGH tHD;STA tBUF 53 MB95160M Series (VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C) Parameter SCL clock “L” width SCL clock “H” width Sym- Pin bol name tLOW tHIGH SCL0 SCL0 Conditions Value*2 Min (2 + nm / 2) tMCLK − 20 (nm / 2) tMCLK − 20 Max ⎯ (nm / 2 ) tMCLK + 20 Unit ns ns Remarks Master mode Master mode Master mode Maximum value is applied when m, n = 1, 8. Otherwise, the minimum value is applied. Master mode Master mode Start condition SCL0 tHD;STA hold time SDA0 (−1 + nm / 2) tMCLK − 20 (−1 + nm) tMCLK + 20 ns Stop condition SCL0 tSU;STO setup time SDA0 Start condition SCL0 tSU;STA setup time SDA0 Bus free time between stop condition and start condition tBUF SCL0 SDA0 SCL0 SDA0 R = 1.7 kΩ, C = 50 pF*1 (1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20 (1 + nm / 2) tMCLK + 20 ns ns (2 nm + 4) tMCLK − 20 ⎯ ns Data hold time tHD;DAT 3 tMCLK − 20 ⎯ ns Master mode Master mode When assuming that “L” of SCL is not extended, the minimum value is applied to first bit of continuous data. Otherwise, the maximum value is applied. Minimum value is applied to interrupt at 9th SCL↓. Maximum value is applied to interrupt at 8th SCL↓. At reception At reception Undetected when 1 tMCLK is used at reception (Continued) Data setup time tSU;DAT SCL0 SDA0 (−2 + nm / 2) tMCLK − 20 (−1 + nm / 2) tMCLK + 20 ns Setup time between clearing interrupt and SCL rising SCL clock “L” width SCL clock “H” width tSU;INT SCL0 (nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20 ns tLOW tHIGH SCL0 SCL0 4 tMCLK − 20 4 tMCLK − 20 2 tMCLK − 20 ⎯ ⎯ ⎯ ns ns ns SCL0 Start condition tHD;STA SDA0 detection 54 MB95160M Series (Continued) Sym- Pin bol name tSU;STO SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 R = 1.7 kΩ, 1 SCL0 C = 50 pF* SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 (VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C) Conditions Value*2 Min 2 tMCLK − 20 Parameter Stop condition detection Restart condition detection condition Bus free time Data hold time Data setup time Data hold time Data setup time SDA↓→SCL↑ (at wakeup function) Max ⎯ Unit Remarks Undetected when 1 tMCLK is used at reception Undetected when 1 tMCLK is used at reception At reception At slave transmission mode At slave transmission mode At reception At reception ns tSU;STA 2 tMCLK − 20 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ns tBUF tHD;DAT tSU;DAT tHD;DAT tSU;DAT tWAKEUP 2 tMCLK − 20 2 tMCLK − 20 tLOW − 3 tMCLK − 20 0 tMCLK − 20 Oscillation stabilization wait time + 2 tMCLK − 20 ns ns ns ns ns ⎯ ns *1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : • • • • Refer to “ (2) Source Clock/Machine Clock” for tMCLK. m is CS4 bit and CS3 bit (bit 4 and bit 3) of I2C clock control register (ICCR) . n is CS2 bit to CS0 bit (bit 2 to bit 0) of I2C clock control register (ICCR) . Actual timing of I2C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of ICCR0 register. • Standard-mode : m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz. Setting of m and n determines the machine clock that can be used below. (m, n) = (1, 8) : 0.9 MHz < tMCLK ≤ 1 MHz (m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz (m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz (m, n) = (1, 98) : 0.9 MHz < tMCLK ≤ 10 MHz • Fast-mode : m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz. Setting of m and n determines the machine clock that can be used below. (m, n) = (1, 8) : 3.3 MHz < tMCLK ≤ 4 MHz (m, n) = (1, 22) , (5, 4) : 3.3 MHz < tMCLK ≤ 8 MHz (m, n) = (6, 4) : 3.3 MHz < tMCLK ≤ 10 MHz 55 MB95160M Series (9) Low Voltage Detection (Vss = 0.0 V, TA = −10 °C to + 85 °C) Parameter Release voltage Detection voltage Hysteresis width Power-supply start voltage Power-supply end voltage Power-supply voltage change time (at power supply rise) Symbol VDL+ VDLVHYS Voff Von Conditions Value Min 2.52 2.42 70 ⎯ 4.9 0.3 tr ⎯ Power-supply voltage change time (at power supply fall) Reset release delay time Reset detection delay time Current consumption ⎯ 300 tf ⎯ td1 td2 ILVD ⎯ ⎯ ⎯ 300 ⎯ ⎯ 38 ⎯ 400 30 50 µs µs µs µA Current consumption of low voltage detection circuit only 3000 ⎯ ⎯ ⎯ µs µs Typ 2.70 2.60 100 ⎯ ⎯ ⎯ Max 2.88 2.78 ⎯ 2.3 ⎯ ⎯ Unit V V mV V V µs Slope of power supply that reset release signal generates Slope of power supply that reset release signal generates within rating (VDL+) Slope of power supply that reset detection signal generates Slope of power supply that reset detection signal generates within rating (VDL-) Remarks At power-supply rise At power-supply fall Vcc Von Voff Time Vcc tf tr VDL+ VDL- VHYS Internal reset signal Time td2 td1 56 MB95160M Series (10) Clock Supervisor Clock (Vcc = 5.0 V ± 10%, Vss = 0.0 V, TA = −40 °C to + 85 °C) Parameter Oscillation frequency Oscillation start time Current consumption Symbol fOUT twk ⎯ ICSV Conditions Value Min 50 ⎯ ⎯ Typ 100 ⎯ 20 Max 200 10 36 Unit kHz µs µA Current consumption of built-in CR oscillator, at 100 kHz oscillation Remarks 57 MB95160M Series 5. A/D Converter (1) A/D Converter Electrical Characteristics (AVCC = VCC = 4.0 V to 5.5 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C) Parameter Resolution Total error Linearity error Differential linear error Zero transition voltage Full-scale transition voltage Compare time VOT ⎯ Sym- Condibol tions Value Min ⎯ − 3.0 − 2.5 − 1.9 Typ ⎯ ⎯ ⎯ ⎯ Max 10 + 3.0 + 2.5 + 1.9 Unit bit LSB LSB LSB Remarks AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB V VFST AVR − 3.5 LSB AVR − 1.5 LSB AVR + 0.5 LSB 0.9 1.8 ⎯ 0.6 ⎯ ⎯ ⎯ 16500 16500 ∞ V µs µs µs 4.5 V ≤ AVcc ≤ 5.5 V 4.0 V ≤ AVcc < 4.5 V 4.5 V ≤ AVcc ≤ 5.5 V, At external impedance < 5.4 kΩ 4.0 V ≤ AVcc < 4.5 V, At external impedance < 2.4 kΩ ⎯ Sampling time ⎯ 1.2 ⎯ ⎯ ⎯ ⎯ 600 ⎯ ∞ + 0.3 AVR AVCC 900 5 µs µA V V µA µA Analog input current Analog input voltage Reference voltage Reference voltage supply current IAIN VAIN ⎯ IR IRH − 0.3 AVSS AVSS + 4.0 ⎯ ⎯ AVR pin AVR pin, during A/D operation AVR pin, at stop mode 58 MB95160M Series (2) Notes on Using A/D Converter • About the external impedance of analog input and its sampling time A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/ D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. • Analog input equivalent circuit R Analog input C Comparator During sampling : ON 4.5 V ≤ VCC ≤ 5.5 V 4.0 V ≤ VCC < 4.5 V Note : The values are reference values. R 2.0 kΩ (Max) 8.2 kΩ (Max) C 16 pF (Max) 16 pF (Max) • The relationship between external impedance and minimum sampling time (External impedance = 0 kΩ to 100 kΩ) 100 90 80 70 60 50 40 30 20 10 0 0 2 4 (External impedance = 0 kΩ to 20 kΩ) 20 18 16 14 12 10 8 6 4 2 0 0 External impedance [kΩ] External impedance [kΩ] VCC ≥ 4.5 V VCC ≥ 4.5 V VCC ≥ 4.0 V VCC ≥ 4.0 V 6 8 10 12 14 1 2 3 4 Minimum sampling time [µs] Minimum sampling time [µs] • About errors As |VCC − VSS| becomes smaller, values of relative errors grow larger. 59 MB95160M Series (3) Definition of A/D Converter Terms • Resolution The level of analog variation that can be distinguished by the A/D converter. When the number of bits is 10, analog voltage can be divided into 210 = 1024. • Linearity error (unit : LSB) The deviation between the value along a straight line connecting the zero transition point (“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point (“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained. • Differential linear error (Unit : LSB) Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. • Total error (unit: LSB) Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error, linearity error, quantum error, and noise. Ideal I/O characteristics VFST Total error 3FFH 3FEH 3FFH 3FEH 1.5 LSB Actual conversion characteristic {1 LSB × (N − 1) + 0.5 LSB} Digital output Digital output 3FDH 3FDH 004H 003H 002H 001H 0.5 LSB VSS VCC VOT 1 LSB 004H 003H 002H 001H VSS VCC VNT Actual conversion characteristic Ideal characteristics Analog input 1 LSB = VCC − Vss 1024 (V) Analog input Total error of VNT − {1 LSB × (N − 1) + 0.5 LSB} = [LSB] digital output N 1 LSB N : A/D converter digital output value VNT : A voltage at which digital output transits from (N − 1) H to NH (Continued) 60 MB95160M Series (Continued) Zero transition error 004H Actual conversion characteristic Full-scale transition error Ideal characteristics 3FFH Digital output 003H Ideal characteristics Digital output Actual conversion characteristic 3FEH VFST 002H Actual conversion characteristic 3FDH (measurement value) 001H VOT (measurement value) Actual conversion characteristic 3FCH VSS VCC VSS VCC Analog input Analog input Linearity error 3FFH 3FEH Actual conversion characteristic Differential linear error Ideal characteristics (N+1)H {1 LSB × N + VOT} VFST (measurement value) Digital output Digital output 3FDH Actual conversion characteristic V (N+1)T NH VNT 004H 003H 002H 001H VSS Actual conversion characteristic Ideal characteristics (N-1)H VNT Actual conversion characteristic (N-2)H VOT (measurement value) Analog input VCC VSS Analog input VCC Linearity error in = VNT − {1 LSB × N + VOT} 1 LSB digital output N Differential linear error = in digital output N V (N + 1) T − VNT 1 LSB −1 N : A/D converter digital output value VNT : A voltage at which digital output transits from (N − 1) H to NH VOT (Ideal value) = VSS + 0.5 LSB [V] VFST (Ideal value) = VCC − 1.5 LSB [V] 61 MB95160M Series 6. Flash Memory Program/Erase Characteristics Parameter Chip erase time Byte programming time Erase/program cycle Power supply voltage at erase/program Flash memory data retention time *1 : TA = + 25 °C, VCC = 5.0 V, 10000 cycles *2 : TA = + 85 °C, VCC = 4.5 V, 10000 cycles *3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at +85 °C) . ⎯ Conditions Value Min ⎯ ⎯ 10000 4.5 20*3 Typ 1*1 32 ⎯ ⎯ ⎯ Max 15*2 3600 ⎯ 5.5 ⎯ Unit s µs cycle V year Average TA = + 85 °C Remarks Excludes 00H programming prior erasure. Excludes system-level overhead. 62 MB95160M Series ■ EXAMPLE CHARACTERISTICS • Power supply current temperature ICC − VCC TA = + 25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2) Main clock mode, at external clock operating 20 ICC − TA VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2) Main clock mode, at external clock operating 20 15 15 FMP = 16 MHz FMP = 16 MHz ICC [mA] ICC [mA] 10 10 FMP = 10 MHz FMP = 10 MHz FMP = 8 MHz 5 5 FMP = 4 MHz FMP = 2 MHz 0 2 3 4 5 6 7 0 -50 0 +50 TA [°C] +100 +150 VCC [V] ICCS − VCC TA = + 25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2) Main sleep mode, at external clock operating 20 ICCS − TA VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2) Main sleep mode, at external clock operating 20 15 15 ICCS [mA] ICCS [mA] 10 10 FMP =16 MHz 5 5 FMP = 16 MHz FMP = 10 MHz FMP =10 MHz FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz 2 3 4 5 6 7 0 0 -50 0 +50 TA [°C] +100 +150 VCC [V] ICCMPLL − VCC TA = + 25 °C, FMP = 2, 4, 8, 10, 16 MHz (Main PLL multiplied by 2.5) Main PLL mode, at external clock operating 20 ICCMPLL − TA VCC = 5.5 V, FMP = 10, 16 MHz (Main PLL multiplied by 2.5) Main PLL mode, at external clock operating 20 15 15 ICCMPLL [mA] ICCMPLL [mA] FMP = 16 MHz 10 FMP = 16 MHz 10 FMP = 10 MHz FMP = 8 MHz 5 FMP = 10 MHz 5 FMP = 4 MHz FMP = 2 MHz 0 2 3 4 5 6 7 0 -50 0 +50 +100 +150 VCC [V] TA [°C] (Continued) 63 MB95160M Series ICCL − VCC TA = + 25 °C, FMPL = 16 kHz (divided by 2) Sub clock mode, at external clock operating 100 ICCL − TA VCC = 5.5 V, FMPL = 16 kHz (divided by 2) Sub clock mode, at external clock operating 100 75 ICCL [µA] ICCL [µA] 75 50 50 25 25 0 2 3 4 VCC [V] 5 6 7 0 −50 0 +50 TA [°C] +100 +150 ICCLS − VCC TA = + 25 °C, FMPL = 16 kHz (divided by 2) Sub sleep mode, at external clock operating 100 ICCLS − TA VCC = 5.5 V, FMPL = 16 kHz (divided by 2) Sub sleep mode, at external clock operating 100 75 ICCLS [µA] ICCLS [µA] 75 50 50 25 25 0 2 3 4 VCC [V] 5 6 7 0 −50 0 +50 TA [°C] +100 +150 ICCT − VCC TA = + 25 °C, FMPL = 16 kHz (divided by 2) Clock mode, at external clock operating 100 ICCT − TA VCC = 5.5 V, FMPL = 16 kHz (divided by 2) Clock mode, at external clock operating 100 75 ICCT [µA] 75 ICCT [µA] 50 50 25 25 0 2 3 4 VCC [V] 5 6 7 0 −50 0 +50 TA [°C] +100 +150 (Continued) 64 MB95160M Series ICCSPLL − VCC TA = + 25 °C, FMPL = 128 kHz (Main PLL multiplied by 4) Sub PLL mode, at external clock operating 200 175 150 ICCSPLL [µA] ICCSPLL − TA VCC = 5.5 V, FMPL = 128 kHz (Main PLL multiplied by 4) Sub PLL mode, at external clock operating 200 175 150 ICCSPLL [µA] 125 100 75 50 25 0 2 3 4 VCC [V] 5 6 7 125 100 75 50 25 0 −50 0 +50 TA [°C] +100 +150 ICTS − VCC TA = + 25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2) Time-base timer mode, at external clock operating 2.0 ICTS − TA VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2) Time-base timer mode, at external clock operating 2.0 1.5 1.5 ICTS [mA] ICTS [mA] FMP = 16 MHz 1.0 FMP = 10 MHz FMP = 8 MHz 0.5 FMP = 4 MHz FMP = 2 MHz FMP = 16 MHz 1.0 FMP = 10 MHz 0.5 0.0 2 3 4 VCC [V] 5 6 7 0.0 −50 0 +50 TA [°C] +100 +150 ICCH − VCC TA = + 25 °C, FMPL = (stop) Sub stop mode, at external clock stopping 20 ICCH − TA VCC = 5.5 V, FMPL = (stop) Sub stop mode, at external clock stopping 20 15 ICCH [µA] ICCH [µA] 15 10 10 5 5 0 2 3 4 VCC [V] 5 6 7 0 −50 0 +50 TA [°C] +100 +150 (Continued) 65 MB95160M Series (Continued) IA − AVCC TA = + 25 °C, FMP = 16 MHz (divided by 2) Main clock mode, at external clock operating 4 IA − TA VCC = 5.5 V, FMP = 16 MHz (divided by 2) Main clock mode, at external clock operating 4 3 3 IA [mA] 2 IA [mA] 2 3 4 AVCC [V] 5 6 7 2 1 1 0 0 −50 0 +50 TA [°C] +100 +150 IR − AVCC TA = + 25 °C, FMP = 16 MHz (divided by 2) Main clock mode, at external clock operating 4 IR − TA VCC = 5.5 V, FMP = 16 MHz (divided by 2) Main clock mode, at external clock operating 4 3 3 IR [mA] 2 IR [mA] 2 3 4 AVCC [V] 5 6 7 2 1 1 0 0 −50 0 +50 TA [°C] +100 +150 66 MB95160M Series • Input voltage VIH1 − VCC and VIL − VCC TA = + 25 °C 5 5 VIHS1 − VCC and VILS − VCC TA = + 25 °C 4 4 VIHS1 3 VIL 2 VIHS1 / VILS [V] VIH1 VIH1 / VIL [V] 3 VILS 2 1 1 0 2 3 4 VCC [V] 5 6 7 0 2 3 4 VCC [V] 5 6 7 VIH2 − VCC and VIL − VCC TA = + 25 °C 5 VIHS2 − VCC and VILS − VCC TA = + 25 °C 5 4 VIH2 VIL 2 4 VIHS2 VIHS2 / VILS [V] VIH2 / VIL [V] 3 3 VILS 2 1 1 0 2 3 4 VCC [V] 5 6 7 0 2 3 4 VCC [V] 5 6 7 VIHA − VCC and VILA − VCC TA = + 25 °C 5 VIHA 4 VILA 3 4 5 VIHM − VCC and VILM − VCC TA = + 25 °C VIHM / VILM [V] VIHA / VILA [V] 3 VIHM 2 VILM 2 1 1 0 2 3 4 VCC [V] 5 6 7 0 2 3 4 VCC [V] 5 6 7 67 MB95160M Series • Output voltage VOH1 − IOH TA = + 25 °C 2.5 V 2.7 V 1.0 0.8 VCC - VOH1 [V] 3.5 V 3.3 V 3V VCC = 4 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V VCC = 2.45 V 0.6 0.4 0.2 0.0 0 -2 -4 -6 IOH [mA] -8 -10 VOL1 − IOL TA = + 25 °C 2.7 V 1.0 0.8 0.6 VCC = 2.45 V 0.4 0.2 0.0 0 2 4 IOL [mA] 6 8 10 VOL2 − IOL TA = + 25 °C VCC = 3.3 V VCC = 3.5 V 2.45 V VCC = 2.5 V VCC = 2.7 V VCC = 3.0 V VCC = 3.3 V VCC = 3.5 V VCC = 4.0 V VCC = 5.0 V VCC = 2.5 V 2.0 4.0 6.0 IOL [mA] 8.0 10.0 3V 1.0 0.8 0.6 0.4 0.2 0.0 0.0 VCC = 2.5 V VOL1 [V] • Pull-up RPULL − VCC TA = + 25 °C 250 200 RPULL [kΩ] 150 100 50 0 2 3 4 VCC [V] 5 6 68 VOL2 [V] VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V MB95160M Series ■ MASK OPTION No. Part number Specifying procedure Clock mode select* • Single-system clock mode • Dual-system clock mode Low voltage detection reset* • With low voltage detection reset • Without low voltage detection reset Clock supervisor* • With clock supervisor • Without clock supervisor Reset output* • With reset output • Without reset output Oscillation stabilization wait time MB95F168M/F168N/F168J Setting disabled Dual-system clock mode MB95FV100D-103 Setting disabled Changing by the switch on MCU board 1 2 Specified by part number Changing by the switch on MCU board 3 Specified by part number Changing by the switch on MCU board MCU board switch sets as follows; • With clock supervisor: Without reset output • Without clock supervisor: With reset output 4 Specified by part number 5 Fixed to oscillation stabilization Fixed to oscillation stabilization wait wait time of (214 − 2) /FCH time of (214 − 2) /FCH * : Refer to table below about clock mode select, low voltage detection reset, clock supervisor select and reset output. Part number MB95F168M MB95F168N MB95F168J Single-system MB95FV100D-103 Dual-system Dual-system Clock mode select Low voltage detection reset Clock supervisor Reset output No Yes Yes No Yes Yes No Yes Yes No No Yes No No Yes No No Yes Yes Yes No Yes Yes No Yes Yes No 69 MB95160M Series ■ ORDERING INFORMATION Part number MB95F168MPMC MB95F168NPMC MB95F168JPMC MB95F168MPMC1 MB95F168NPMC1 MB95F168JPMC1 MB2146-303A (MB95FV100D-103PBT) Package 64-pin plastic LQFP (FPT-64P-M23) 64-pin plastic LQFP (FPT-64P-M024) MCU board 224-pin plastic PFBGA (BGA-224P-M08) ( ) 70 MB95160M Series ■ PACKAGE DIMENSIONS 64-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Code (Reference) 0.65 mm 12.0 × 12.0 mm Gullwing Plastic mold 1.70 mm MAX P-LFQFP64-12×12-0.65 (FPT-64P-M23) 64-pin plastic LQFP (FPT-64P-M23) 14.00±0.20(.551±.008)SQ *12.00±0.10(.472±.004)SQ 48 33 Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 0.145±0.055 (.0057±.0022) 49 32 0.10(.004) Details of "A" part 1.50 –0.10 .059 –.004 +0.20 +.008 (Mounting height) 0.25(.010) INDEX 0~8˚ 64 17 1 16 "A" 0.65(.026) 0.32±0.05 (.013±.002) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (.004±.004) (Stand off) 0.13(.005) M C 2003 FUJITSU LIMITED F64034S-c-1-1 Dimensions in mm (inches). Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html (Continued) 71 MB95160M Series (Continued) 64-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.50 mm 10.0 × 10.0 mm Gullwing Plastic mold 1.70 mm MAX 0.32g P-LFQFP64-10×10-0.50 (FPT-64P-M24) Code (Reference) 64-pin plastic LQFP (FPT-64P-M24) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 12.00±0.20(.472±.008)SQ * 10.00±0.10(.394±.004)SQ 48 33 0.145±0.055 (.006±.002) 49 32 Details of "A" part 0.08(.003) 1.50 –0.10 .059 –.004 +0.20 +.008 (Mounting height) INDEX 64 17 0˚~8˚ "A" 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) LEAD No. 1 16 0.50(.020) 0.20±0.05 (.008±.002) 0.08(.003) M C 2005 FUJITSU LIMITED F64036S-c-1-1 Dimensions in mm (inches). Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 72 MB95160M Series ■ MAIN CHANGES (The Main Changes from the First Edition to This Edition) Page ⎯ 22 29 ■ I/O MAP ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Section ⎯ Change Results Preliminary Data Sheet → Data Sheet Changed as follows for R/W of Reset factor register R → R/W The Min value in the row of “Operating temperature” is changed as follows; − 40 → − 10 31 ■ ELECTRICAL CHARACTERISTICS The Min value in the row of “Operating temperature” is 2. Recommended Operating Conditions changed as follows; − 40 → − 10 4. AC Characteristics (1) Clock Timing (2) Source Clock/Machine Clock Added “Main PLL multiplied by 4” in the Clock frequency • Changed in the remarks of source clock cycle time (when using main clock) Min : FCH = 16.25 MHz, PLL multiplied by 1 → Min : FCH = 8.125 MHz, PLL multiplied by 2 • Changed the footnote of *1; PLL multiplication of main clock (select from 1, 2, 2.5 multiplication) → PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication) • Added “ × 4” in the Main PLL of “• Outline of clock generation block” Changed the figure of “• Main PLL operation frequency” (8) I2C Timing ■ EXAMPLE CHARACTERISTICS Added the characteristics Added the ■ EXAMPLE CHARACTERISTICS 36 38 39 41 52 to 55 63 to 68 The vertical lines marked in the left side of the page show the changes. 73 MB95160M Series The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html FUJITSU LIMITED All Rights Reserved. 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