MB95F394K

FUJITSU SEMICONDUCTOR DATA SHEET DS07–12632–2E 8-bit Microcontrollers CMOS F2MC-8FX MB95390H Series MB95F394H/F396K/F398H/F394K/F396H/F398K ■ DESCRIPTION MB95390H is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers of this series contain a variety of peripheral resources. Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller. ■ FEATURES • F2MC-8FX CPU core Instruction set optimized for controllers • Multiplication and division instructions • 16-bit arithmetic operations • Bit test branch instructions • Bit manipulation instructions, etc. • Clock • Selectable main clock source Main OSC clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz) External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz) Main CR clock (1/8/10/12.5 MHz ±2% or ±2.5%*, maximum machine clock frequency: 12.5 MHz) *: The main CR clock oscillation accuracy of a product in LQFP package (FPT-48P-M49 or FPT-52P-M02) is ±2% and that of a product in QFN package (LCC-48P-M11) is ±2.5%. • Selectable subclock source Sub-OSC clock (32.768 kHz) External clock (32.768 kHz) Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 200 kHz) • Timer • 8/16-bit composite timer × 2 channels • 8/16-bit PPG × 3 channels • 16-bit PPG × 1 channel (can work independently or together with the multi-pulse generator) • 16-bit reload timer × 1 channel (can work independently or together with the multi-pulse generator) • Time-base timer × 1 channel • Watch prescaler × 1 channel (Continued) For the information for microcontroller supports, see the following website. http://edevice.fujitsu.com/micom/en-support/ Copyright©2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2010.11 MB95390H Series (Continued) • UART/SIO × 1 channel • Full duplex double buffer • Capable of clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data transfer • I2C × 1 channel • Built-in wake-up function • Multi-pulse generator (MPG) (for DC motor control) × 1 channel • 16-bit reload timer × 1 channel • 16-bit PPG timer × 1 channel • Waveform sequencer (including a 16-bit timer equipped with a buffer and a compare clear function) • LIN-UART • Full duplex double buffer • Capable of clock-synchronous serial data transfer and clock-asynchronous serial data transfer • External interrupt × 8 channels • Interrupt by edge detection (rising edge, falling edge, and both edges can be selected) • Can be used to wake up the device from different low power consumption (standby) modes • 8/10-bit A/D converter × 12 channels • 8-bit and 10-bit resolution can be chosen. • Low power consumption (standby) modes • Stop mode • Sleep mode • Watch mode • Time-base timer mode • I/O port • MB95F394H/F396H/F398H (maximum no. of I/O ports: 44) General-purpose I/O ports (N-ch open drain) :3 General-purpose I/O ports (CMOS I/O) : 41 • MB95F394K/F396K/F398K (maximum no. of I/O ports: 45) General-purpose I/O ports (N-ch open drain) :4 General-purpose I/O ports (CMOS I/O) : 41 • On-chip debug • 1-wire serial control • Serial writing supported (asynchronous mode) • Hardware/software watchdog timer • Built-in hardware watchdog timer • Built-in software watchdog timer • Low-voltage detection reset circuit • Built-in low-voltage detector • Clock supervisor counter • Built-in clock supervisor counter function • Programmable port input voltage level • CMOS input level / hysteresis input level • Dual operation Flash memory • The erase/write operation and the read operation can be executed in different banks (upper bank/lower bank) simultaneously. • Flash memory security function • Protects the content of the Flash memory 2 DS07–12632–2E MB95390H Series ■ PRODUCT LINE-UP Part number MB95F394H Parameter MB95F396H MB95F398H MB95F394K MB95F396K MB95F398K Type Flash memory product Clock supervisor It supervises the main clock oscillation. counter Program ROM 20 Kbyte 36 Kbyte 60 Kbyte 20 Kbyte 36 Kbyte 60 Kbyte capacity RAM capacity 496 bytes 1008 bytes 2032 bytes 496 bytes 1008 bytes 2032 bytes Low-voltage No Yes detection reset Reset input Dedicated Selected through software • Number of basic instructions : 136 • Instruction bit length : 8 bits • Instruction length : 1 to 3 bytes CPU functions • Data bit length : 1, 8 and 16 bits • Minimum instruction execution time : 61.5 ns (with machine clock frequency = 16.25 MHz) • Interrupt processing time : 0.6 µs (with machine clock frequency = 16.25 MHz) • I/O ports (Max) : 45 • I/O ports (Max) : 44 General• CMOS I/O : 41 • CMOS I/O : 41 purpose I/O • N-ch open drain: 4 • N-ch open drain: 3 Time-base timer Interval time: 0.256 ms to 8.3 s (with external clock frequency = 4 MHz) • Reset generation cycle Hardware/ software - Main oscillation clock at 10 MHz: 105 ms (Min) watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer. Wild register It can be used to replace three bytes of data. • A wide range of communication speeds can be selected by a dedicated reload timer. • Clock-synchronous serial data transfer and clock-asynchronous serial data transfer is enLIN-UART abled. • The LIN function can be used as a LIN master or a LIN slave. 12 channels 8/10-bit A/D converter 8-bit resolution and 10-bit resolution can be chosen. 2 channels • The timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel". 8/16-bit • It has the following functions: timer function, PWC function, PWM function and input capture composite timer function. • Count clock: it can be selected from internal clocks (seven types) and external clocks. • It can output square wave. 8 channels External • Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.) interrupt • It can be used to wake up the device from different standby modes. • 1-wire serial control On-chip debug • It supports serial writing. (asynchronous mode) (Continued) DS07–12632–2E 3 MB95390H Series (Continued) Part number MB95F394H Parameter MB95F396H MB95F398H MB95F394K MB95F396K MB95F398K 1 channel • Data transfer with UART/SIO is enabled. • It has a full duplex double buffer, variable data length (5/6/7/8 bits), a built-in baud rate generator and an error detection function. UART/SIO • It uses the NRZ type transfer format. • LSB-first data transfer and MSB-first data transfer are available to use. • Clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data transfer is enabled. 1 channel • Master/slave transmission and receiving I2C • It has the following functions: bus error function, arbitration function, transmission direction detection function, wake-up function, and functions of generating and detecting repeated START conditions. 3 channels 8/16-bit PPG • Each channel of PPG can be used as two 8-bit PPG channels or a single 16-bit PPG channel. • The counter operating clock can be selected from eight clock sources. • PWM mode and one-shot mode are available to use. • The counter operating clock can be selected from eight clock sources. 16-bit PPG • It supports external trigger start. • It can work independently or together with the multi-pulse generator. • Two clock modes and two counter operating modes are available to use. • It can output square waveform. 16-bit reload • Count clock: it can be selected from internal clocks (seven types) and external clocks. timer • Two counter operating modes: reload mode and one-shot mode • It can work independently or together with the multi-pulse generator. • 16-bit PPG timer: 1 channel Multi-pulse • 16-bit reload timer operations: toggle output, one-shot output generator (for • Event counter: 1 channel DC motor • Waveform sequencer (including a 16-bit timer equipped with a buffer and a compare clear control) function) Watch prescaler Eight different time intervals can be selected. • It supports automatic programming, Embedded Algorithm, and write/erase/erase-suspend/ erase-resume commands. • It has a flag indicating the completion of the operation of Embedded Algorithm. Flash memory • Number of write/erase cycles: 100000 • Data retention time: 20 years • Flash security feature for protecting the content of the Flash memory Standby mode Sleep mode, stop mode, watch mode, time-base timer mode FPT-48P-M49 Package FPT-52P-M02 LCC-48P-M11 4 DS07–12632–2E MB95390H Series ■ PACKAGES AND CORRESPONDING PRODUCTS Part number MB95F394H Package MB95F396H MB95F398H MB95F394K MB95F396K MB95F398K FPT-48P-M49 FPT-52P-M02 LCC-48P-M11 O: Available O O O O O O O O O O O O O O O O O O DS07–12632–2E 5 MB95390H Series ■ DIFFERENCES AMONG PRODUCTS AND NOTES ON PRODUCT SELECTION • Current consumption When using the on-chip debug function, take account of the current consumption of flash erase/write. For details of current consumption, see “■ ELECTRICAL CHARACTERISTICS”. • Package For details of information on each package, see “■ PACKAGES AND CORRESPONDING PRODUCTS” and “■ PACKAGE DIMENSIONS”. • Operating voltage The operating voltage varies, depending on whether the on-chip debug function is used or not. For details of the operating voltage, see “■ ELECTRICAL CHARACTERISTICS”. • On-chip debug function The on-chip debug function requires that VCC, VSS and one serial wire be connected to an evaluation tool. For details of the connection method, refer to “CHAPTER 29 EXAMPLE OF SERIAL PROGRAMMING CONNECTION” in the hardware manual of the MB95390H Series. 6 DS07–12632–2E MB95390H Series ■ PIN ASSIGNMENT Vss PF1/X1 PF0/X0 PF2/RST P07/INT07/AN07 P06/INT06/AN06 P05/INT05/AN05 P04/INT04/AN04 P02/INT02/AN02 39 P01/INT01/AN01 38 P00/INT00/AN00 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 P03/INT03/AN03 40 PG2/X1A/SNI2 PG1/X0A/SNI1 Vcc C P40/AN08 P41/AN09 P42/AN10 P43/AN11 P44/TO1 P45/SCK P46/SOT P47/SIN 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 (TOP VIEW) LQFP48 FPT-48P-M49 P67*/OPT5/PPG21/TRG1 P66*/OPT4/PPG20/PPG1 P65*/OPT3/PPG11 P64*/OPT2/PPG10/EC1 P63*/OPT1/PPG01/TO11 P62*/OPT0/PPG00/TO10 P61/TI1 P60/DTTI P77/UI0 P76/UO0 P75/UCK0 P74/EC0 P10/PPG10 P11/PPG11 P12/DBG P13/PPG00 P14/PPG01 P15/PPG20 P16/PPG21 P17/SNI0 P70/TO00 *: High-current pin (8 mA/12 mA) (Continued) DS07–12632–2E P71/TO01 P73/SDA P72/SCL 7 MB95390H Series Vss PF1/X1 PF0/X0 PF2/RST P07/INT07/AN07 P06/INT06/AN06 NC P05/INT05/AN05 P04/INT04/AN04 P02/INT02/AN02 P01/INT01/AN01 52 51 50 49 48 47 46 45 44 PG2/X1A/SNI2 PG1/X0A/SNI1 Vcc C P40/AN08 P41/AN09 NC P42/AN10 P43/AN11 P44/TO1 P45/SCK P46/SOT P47/SIN 41 40 39 38 37 36 43 42 P00/INT00/AN00 P03/INT03/AN03 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 20 P67*/OPT5/PPG21/TRG1 P66*/OPT4/PPG20/PPG1 P65*/OPT3/PPG11 P64*/OPT2/PPG10/EC1 P63*/OPT1/PPG01/TO11 P62*/OPT0/PPG00/TO10 NC P61/TI1 P60/DTTI P77/UI0 P76/UO0 P75/UCK0 P74/EC0 (TOP VIEW) LQFP52 FPT-52P-M02 35 34 33 32 31 30 29 28 27 P17/SNI0 P10/PPG10 P11/PPG11 P12/DBG P13/PPG00 P14/PPG01 P15/PPG20 NC P16/PPG21 P70/TO00 *: High-current pin (8 mA/12 mA) (Continued) 8 P71/TO01 P73/SDA P72/SCL DS07–12632–2E MB95390H Series (Continued) PF2/RST P07/INT07/AN07 P06/INT06/AN06 P05/INT05/AN05 P04/INT04/AN04 P03/INT03/AN03 P02/INT02/AN02 39 P01/INT01/AN01 38 P00/INT00/AN00 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 PF1/X1 PF0/X0 Vss PG2/X1A/SNI2 PG1/X0A/SNI1 Vcc C P40/AN08 P41/AN09 P42/AN10 P43/AN11 P44/TO1 P45/SCK P46/SOT P47/SIN 43 42 41 40 48 47 46 45 44 1 2 3 4 5 6 7 8 9 10 11 12 (TOP VIEW) QFN48 LCC-48P-M11 P67*/OPT5/PPG21/TRG1 P66*/OPT4/PPG20/PPG1 P65*/OPT3/PPG11 P64*/OPT2/PPG10/EC1 P63*/OPT1/PPG01/TO11 P62*/OPT0/PPG00/TO10 P61/TI1 P60/DTTI P77/UI0 P76/UO0 P75/UCK0 P74/EC0 P10/PPG10 P11/PPG11 P12/DBG P13/PPG00 P14/PPG01 P15/PPG20 P16/PPG21 P17/SNI0 P70/TO00 *: High-current pin (8 mA/12 mA) DS07–12632–2E P71/TO01 P73/SDA P72/SCL 9 MB95390H Series ■ PIN FUNCTIONS Pin no. LQFP48*1 QFN48*2 LQFP52*3 Pin name PG2 1 1 1 X1A SNI2 PG1 2 2 2 X0A SNI1 3 4 5 6 — 7 8 9 10 11 12 13 14 15 16 3 4 5 6 — 7 8 9 10 11 12 13 14 15 16 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 VCC C P40 AN08 P41 AN09 NC P42 AN10 P43 AN11 P44 TO1 P45 SCK P46 SOT P47 SIN P10 PPG10 P11 PPG11 P12 DBG P13 PPG00 — — K K — K K G G G J G G H G C C I/O circuit type*4 Function General-purpose I/O port Subclock I/O oscillation pin Trigger input pin for the position detection function of the MPG waveform sequencer General-purpose I/O port Subclock input oscillation pin Trigger input pin for the position detection function of the MPG waveform sequencer Power supply pin Capacitor connection pin General-purpose I/O port A/D converter analog input pin General-purpose I/O port A/D converter analog input pin It is an internally connected pin. Always leave it unconnected. General-purpose I/O port A/D converter analog input pin General-purpose I/O port A/D converter analog input pin General-purpose I/O port 16-bit reload timer ch. 0 output pin General-purpose I/O port LIN-UART clock I/O pin General-purpose I/O port LIN-UART data output pin General-purpose I/O port LIN-UART data input pin General-purpose I/O port 8/16-bit PPG ch. 1 output pin General-purpose I/O port 8/16-bit PPG ch. 1 output pin General-purpose I/O port DBG input pin General-purpose I/O port 8/16-bit PPG ch. 0 output pin (Continued) 10 DS07–12632–2E MB95390H Series Pin no. LQFP48*1 17 18 — 19 QFN48*2 17 18 — 19 LQFP52*3 18 19 20 21 I/O circuit type*4 G G — G Pin name P14 PPG01 P15 PPG20 NC P16 PPG21 P17 Function General-purpose I/O port 8/16-bit PPG ch. 0 output pin General-purpose I/O port 8/16-bit PPG ch. 2 output pin It is an internally connected pin. Always leave it unconnected. General-purpose I/O port 8/16-bit PPG ch. 2 output pin General-purpose I/O port Trigger input pin for the position detection function of the MPG waveform sequencer General-purpose I/O port 8/16-bit composite timer ch. 0 output pin General-purpose I/O port 8/16-bit composite timer ch. 0 output pin General-purpose I/O port I2C clock I/O pin General-purpose I/O port I2C data I/O pin General-purpose I/O port 8/16-bit composite timer ch. 0 clock input pin General-purpose I/O port UART/SIO ch. 0 clock I/O pin General-purpose I/O port UART/SIO ch. 0 data output pin General-purpose I/O port UART/SIO ch. 0 data input pin General-purpose I/O port MPG waveform sequencer input pin General-purpose I/O port 16-bit reload timer ch. 0 input pin It is an internally connected pin. Always leave it unconnected. General-purpose I/O port High-current pin 20 20 22 SNI0 P70 TO00 P71 TO01 P72 SCL P73 SDA P74 EC0 P75 UCK0 P76 UO0 P77 UI0 P60 DTTI P61 TI1 NC P62 G 21 22 23 24 25 26 27 28 29 30 — 21 22 23 24 25 26 27 28 29 30 — 23 24 25 26 27 28 29 30 31 32 33 G G I I G G G J G G — 31 31 34 OPT0 PPG00 TO10 D MPG waveform sequencer output pin 8/16-bit PPG ch. 0 output pin 8/16-bit composite timer ch. 1 output pin (Continued) DS07–12632–2E 11 MB95390H Series Pin no. LQFP48*1 QFN48*2 LQFP52*3 I/O circuit type*4 Pin name P63 Function General-purpose I/O port High-current pin 32 32 35 OPT1 PPG01 TO11 P64 D MPG waveform sequencer output pin 8/16-bit PPG ch. 0 output pin 8/16-bit composite timer ch. 1 output pin General-purpose I/O port High-current pin 33 33 36 OPT2 PPG10 EC1 P65 D MPG waveform sequencer output pin 8/16-bit PPG ch. 1 output pin 8/16-bit composite timer ch. 1 clock input pin General-purpose I/O port High-current pin 34 34 37 OPT3 PPG11 P66 D MPG waveform sequencer output pin 8/16-bit PPG ch. 1 output pin General-purpose I/O port High-current pin 35 35 38 OPT4 PPG20 PPG1 P67 D MPG waveform sequencer output pin 8/16-bit PPG ch. 2 output pin 16-bit PPG ch. 1 output pin General-purpose I/O port High-current pin 36 36 39 OPT5 PPG21 TRG1 P00 D MPG waveform sequencer output pin 8/16-bit PPG ch. 2 output pin 16-bit PPG ch. 1 trigger input pin General-purpose I/O port 37 37 40 INT00 AN00 P01 E External interrupt input pin A/D converter analog input pin General-purpose I/O port 38 38 41 INT01 AN01 P02 E External interrupt input pin A/D converter analog input pin General-purpose I/O port 39 39 42 INT02 AN02 P03 E External interrupt input pin A/D converter analog input pin General-purpose I/O port 40 40 43 INT03 AN03 E External interrupt input pin A/D converter analog input pin (Continued) 12 DS07–12632–2E MB95390H Series (Continued) Pin no. LQFP48*1 QFN48*2 LQFP52*3 Pin name P04 41 41 44 INT04 AN04 P05 42 42 45 INT05 AN05 — — 46 NC P06 43 43 47 INT06 AN06 P07 44 44 48 INT07 AN07 PF2 45 45 49 RST PF0 X0 PF1 X1 VSS A E E — E E I/O circuit type*4 Function General-purpose I/O port External interrupt input pin A/D converter analog input pin General-purpose I/O port External interrupt input pin A/D converter analog input pin It is an internally connected pin. Always leave it unconnected. General-purpose I/O port External interrupt input pin A/D converter analog input pin General-purpose I/O port External interrupt input pin A/D converter analog input pin General-purpose I/O port Reset pin Dedicated reset pin in MB95F394H/F396H/F398H General-purpose I/O port Main clock I/O oscillation pin General-purpose I/O port Main clock I/O oscillation pin Power supply pin (GND) 46 47 48 46 47 48 50 51 52 B B — *1: Package code: FPT-48P-M49 *2: Package code: LCC-48P-M11 *3: Package code: FPT-52P-M02 *4: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”. DS07–12632–2E 13 MB95390H Series ■ I/O CIRCUIT TYPE Type A Circuit Reset input / Hysteresis input Reset output / Digital output N-ch Remarks • N-ch open drain output • Hysteresis input • Reset output • Oscillation circuit • High-speed side Feedback resistance: approx. 1 MΩ • CMOS output • Hysteresis input B P-ch Port select Digital output N-ch Digital output Standby control Hysteresis input Clock input X1 X0 Standby control / Port select P-ch Port select Digital output N-ch Digital output Standby control Hysteresis input C R P-ch P-ch N-ch Port select Pull-up control Digital output Digital output Standby control Hysteresis input Clock input X1A • Oscillation circuit • Low-speed side Feedback resistance: approx.10 MΩ • CMOS output • Hysteresis input • Pull-up control available X0A Standby control / Port select Port select R Pull-up control Digital output Digital output N-ch P-ch Digital output Standby control Hysteresis input (Continued) 14 DS07–12632–2E MB95390H Series Type D P-ch Digital output Digital output N-ch Standby control Hysteresis input Circuit Remarks • CMOS output • Hysteresis input • High-current output E R P-ch P-ch N-ch Pull-up control Digital output Digital output • • • • CMOS output Hysteresis input Pull-up control available Analog input Analog input A/D control Standby control Hysteresis input F R P-ch P-ch N-ch Pull-up control Digital output Digital output • • • • • CMOS output Hysteresis input CMOS input Pull-up control available Analog input Analog input A/D control Standby control Hysteresis input CMOS input G R P-ch P-ch N-ch Pull-up control • CMOS output • Hysteresis input • Pull-up control available Digital output Digital output Standby control Hysteresis input H Standby control Hysteresis input Digital output N-ch • N-ch open drain output • Hysteresis input (Continued) DS07–12632–2E 15 MB95390H Series (Continued) Type I Digital output N-ch Standby control Hysteresis input CMOS input Circuit Remarks • N-ch open drain output • Hysteresis input • CMOS input J R P-ch P-ch N-ch Pull-up control Digital output Digital output Standby control Hysteresis input CMOS input • • • • CMOS output Hysteresis input CMOS input Pull-up control available K R P-ch P-ch N-ch Pull-up control Digital output Digital output Standby control Hysteresis input Analog input • • • • Hysteresis input CMOS output Pull-up control available Analog input 16 DS07–12632–2E MB95390H Series ■ NOTES ON DEVICE HANDLING • Preventing latch-ups When using the device, ensure that the voltage applied does not exceed the maximum voltage rating. In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned in "1. Absolute Maximum Ratings" of “■ ELECTRICAL CHARACTERISTICS” is applied to the VCC pin or the VSS pin, a latch-up may occur. When a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed. • Stabilizing supply voltage Supply voltage must be stabilized. A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply. • Notes on using the external clock When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from subclock mode or stop mode. ■ PIN CONNECTION • Treatment of unused pins If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions or latch-ups. Always pull up or pull down an unused input pin through a resistor of at least 2 kΩ. Set an unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it the same as an unused input pin. If there is an unused output pin, leave it unconnected. • Power supply pins To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase in the ground level, and conform to the total output current standard, always connect the VCC pin and the VSS pin to the power supply and ground outside the device. In addition, connect the current supply source to the VCC pin and the VSS pin with low impedance. It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between the VCC pin and the VSS pin at a location close to this device. • DBG pin Connect the DBG pin directly to an external pull-up resistor. To prevent the device from unintentionally entering the debug mode due to noise, minimize the distance between the DBG pin and the VCC or VSS pin when designing the layout of the printed circuit board. The DBG pin should not stay at “L” level after power-on until the reset output is released. • RST pin Connect the RST pin directly to an external pull-up resistor. To prevent the device from unintentionally entering the reset mode due to noise, minimize the distance between the RST pin and the VCC or VSS pin when designing the layout of the printed circuit board. The RST/PF2 pin functions as the reset input/output pin after power-on. In addition, the reset output of the RST/PF2 pin can be enabled by the RSTOE bit in the SYSC register, and the reset input function and the general purpose I/O function can be selected by the RSTEN bit in the SYSC register. DS07–12632–2E 17 MB95390H Series • C pin Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for the VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see the diagram below. To prevent the device from unintentionally entering a mode to which the device is not set to transit due to noise, minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed circuit board. • DBG/RST/C pins connection diagram DBG C RST Cs 18 DS07–12632–2E MB95390H Series ■ BLOCK DIAGRAM F2MC-8FX CPU PF2*1/RST*2 PF1/X1*2 PF0/X0*2 PG2/X1A*2 PG1/X0A*2 (P04) (P05) P12/DBG*1 Reset with LVD Dual operation Flash with security function (60 Kbyte) Oscillator circuit CR oscillator RAM (496/1008/2032 bytes) Clock control 8/16-bit composite timer ch. 0 On-chip debug Wild register 8/10-bit A/D converter P70/TO00 P71/TO01 P74/EC0 (P00/AN00 to P07/AN07) P40/AN08 to P43/AN11 (P62/TO10) 8/16-bit composite timer ch. 1 (P63/TO11) (P64/EC1) MPG 16-bit reload timer (P61/TI1) P44/TO1 P62/OPT0 to P67/OPT5*3 Waveform sequencer P17/SNI0, PG1/SNI1, PG2/SNI2 P60/DTTI P61/TI1 (P67/TRG1) (P66/PPG1) P10/PPG10, (P64/PPG10*3) P11/PPG11, (P65/PPG11*3) P00/INT00 to P07/INT07 External interrupt C P45/SCK P46/SOT P47/SIN P75/UCK0 P76/UO0 P77/UI0 P72/SCL*1 P73/SDA*1 (P62/PPG00*3), P13/PPG00 (P63/PPG01*3), P14/PPG01 (P66/PPG20*3), P15/PPG20 (P67/PPG21*3), P16/PPG21 Interrupt controller LIN-UART UART/SIO Internal bus 16-bit PPG timer IC 2 8/16-bit PPG ch. 1 8/16-bit PPG ch. 0 8/16-bit PPG ch. 2 Port Vcc Vss *1: PF2, P12, P72 and P73 are N-ch open drain pins. *2: Software option *3: P62 to P67 are high-current pins. Port Note: Pins in parentheses indicate that functions of those pins are shared among different resources. DS07–12632–2E 19 MB95390H Series ■ CPU CORE • Memory Space The memory space of the MB95390H Series is 64 Kbyte in size, and consists of an I/O area, a data area, and a program area. The memory space includes areas intended for specific purposes such as general-purpose registers and a vector table. The memory maps of the MB95390H Series are shown below. • Memory Maps MB95F394H/F394K 0000H I/O 0080H 0090H 0100H 0200H 0280H Access prohibited 0F80H Extended I/O 1000H 2000H Flash 4 Kbyte 1000H 2000H Access prohibited RAM 496 bytes Registers 0200H 0480H Access prohibited 0F80H Extended I/O Flash 4 Kbyte 1000H 0880H 0F80H Access prohibited Extended I/O 0080H 0090H 0100H 0000H I/O Access prohibited RAM 1008 bytes Registers 0200H 0080H 0090H 0100H MB95F396H/F396K 0000H MB95F398H/F398K I/O Access prohibited RAM 2032 bytes Registers Vacant Vacant 7FFFH Flash 60 Kbyte BFFFH Flash 16 Kbyte FFFFH FFFFH Flash 32 Kbyte FFFFH 20 DS07–12632–2E MB95390H Series ■ I/O MAP Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH to 0011H 0012H 0013H 0014H, 0015H 0016H 0017H 0018H 0019H 001AH to 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH, 002FH 0030H 0031H 0032H 0033H, 0034H 0035H Register abbreviation PDR0 DDR0 PDR1 DDR1 — WATR — SYCC STBC RSRR TBTC WPCR WDTC SYCC2 — PDR4 PDR4 — PDR6 DDR6 DDR7 DDR7 — PDRF DDRF PDRG DDRG PUL0 PUL1 — PUL4 PUL6 PUL7 — PULG Port G pull-up register Port 4 pull-up register Port 6 pull-up register Port 7 pull-up register (Disabled) Port F data register Port F direction register Port G data register Port G direction register Port 0 pull-up register Port 1 pull-up register (Disabled) Port 6 data register Port 6 direction register Port 7 data register Port 7 direction register (Disabled) Port 4 data register Port 4 direction register (Disabled) Standby control register Reset source register Time-base timer control register Watch prescaler control register Watchdog timer control register System clock control register 2 (Disabled) Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register (Disabled) Oscillation stabilization wait time setting register (Disabled) System clock control register Register name R/W Initial value R/W R/W R/W R/W — R/W — R/W R/W R/W R/W R/W R/W — R/W R/W — R/W R/W R/W R/W — R/W R/W R/W R/W R/W R/W — R/W R/W R/W — R/W 00000000B 00000000B 00000000B 00000000B — 11111111B — 0000X011B 00000XXXB 00000000B 00000000B 00XX0000B XX100011B — 00000000B 00000000B — 00000000B 00000000B 00000000B 00000000B — 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B — 00000000B 00000000B 00000000B — 00000000B (Continued) DS07–12632–2E 21 R/W XXXXXXXXB MB95390H Series Register abbreviation T01CR1 T00CR1 T11CR1 T10CR1 PC01 PC00 PC11 PC10 PC21 PC20 TMCSRH1 TMCSRL1 — PCNTH1 PCNTL1 — EIC00 EIC10 EIC20 EIC30 — SCR SMR SSR RDR/TDR ESCR ECCR SMC10 SMC20 SSR0 TDR0 RDR0 — Address 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH 0040H 0041H 0042H, 0043H 0044H 0045H 0046H, 0047H 0048H 0049H 004AH 004BH 004CH to 004FH 0050H 0051H 0052H 0053H 0054H 0055H 0056H 0057H 0058H 0059H 005AH 005BH to 005FH Register name 8/16-bit composite timer 01 status control register 1 8/16-bit composite timer 00 status control register 1 8/16-bit composite timer 11 status control register 1 8/16-bit composite timer 10 status control register 1 8/16-bit PPG timer 01 control register 8/16-bit PPG timer 00 control register 8/16-bit PPG timer 11 control register 8/16-bit PPG timer 10 control register 8/16-bit PPG timer 21 control register 8/16-bit PPG timer 20 control register 16-bit reload timer control status register upper 16-bit reload timer control status register lower (Disabled) 16-bit PPG status control register upper 16-bit PPG status control register lower (Disabled) External interrupt circuit control register ch. 0/ch. 1 External interrupt circuit control register ch. 2/ch. 3 External interrupt circuit control register ch. 4/ch. 5 External interrupt circuit control register ch. 6/ch. 7 (Disabled) LIN-UART serial control register LIN-UART serial mode register LIN-UART serial status register LIN-UART receive/transmit data register LIN-UART extended status control register LIN-UART extended communication control register UART/SIO serial mode control register 1 UART/SIO serial mode control register 2 UART/SIO serial status and data register UART/SIO serial output data register UART/SIO serial input data register (Disabled) R/W Initial value R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W — R/W R/W — R/W R/W R/W R/W — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R — 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B — 00000000B 00000000B — 00000000B 00000000B 00000000B 00000000B — 00000000B 00000000B 00001000B 00000000B 00000100B 000000XXB 00000000B 00100000B 00000001B 00000000B 00000000B — (Continued) 22 DS07–12632–2E MB95390H Series Register abbreviation IBCR00 IBCR10 IBCR0 IDDR0 IAAR0 ICCR0 OPCUR OPCLR IPCUR IPCLR NCCR TCSR ADC1 ADC2 ADDH ADDL — FSR2 FSR SWRE0 FSR3 — WREN WROR — ILR0 ILR1 ILR2 ILR3 ILR4 ILR5 — WRARH0 WRARL0 WRDR0 2 Address 0060H 0061H 0062H 0063H 0064H 0065H 0066H 0067H 0068H 0069H 006AH 006BH 006CH 006DH 006EH 006FH 0070H 0071H 0072H 0073H 0074H 0075H 0076H 0077H 0078H 0079H 007AH 007BH 007CH 007DH 007EH 007FH 0F80H 0F81H 0F82H Register name I2C bus control register 0 I C bus control register 1 I2C bus status register I2C data register I C address register I C clock control register Output control register (upper) Output control register (lower) Input control register (upper) Input control register (lower) Noise cancellation control register Timer control status register 8/10-bit A/D converter control register 1 8/10-bit A/D converter control register 2 8/10-bit A/D converter data register (upper) 8/10-bit A/D converter data register (lower) (Disabled) Flash memory status register 2 Flash memory status register Flash memory sector write control register 0 Flash memory status register 3 (Disabled) Wild register address compare enable register Wild register data test setting register Mirror of register bank pointer (RP) and mirror of direct bank pointer (DP) Interrupt level setting register 0 Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt level setting register 4 Interrupt level setting register 5 (Disabled) Wild register address setting register (upper) ch. 0 Wild register address setting register (lower) ch. 0 Wild register data setting register ch. 0 2 2 R/W Initial value R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W — R/W R/W R/W R — R/W R/W — R/W R/W R/W R/W R/W R/W — R/W R/W R/W 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B — 00000000B 000X0000B 00000000B 00000000B — 00000000B 00000000B — 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B — 00000000B 00000000B 00000000B (Continued) DS07–12632–2E 23 MB95390H Series Register abbreviation WRARH1 WRARL1 WRDR1 WRARH2 WRARL2 WRDR2 — T01CR0 T00CR0 T01DR T00DR TMCR0 T11CR0 T10CR0 T11DR T10DR TMCR1 PPS01 PPS00 PDS01 PDS00 PPS11 PPS10 PDS11 PDS10 PPGS REVC PPS21 PPS20 TMRH1 TMRLRH1 TMRL1 TMRLRL1 PDS21 PDS20 Address 0F83H 0F84H 0F85H 0F86H 0F87H 0F88H 0F89H to 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H 0F98H 0F99H 0F9AH 0F9BH 0F9CH 0F9DH 0F9EH 0F9FH 0FA0H 0FA1H 0FA2H 0FA3H 0FA4H 0FA5H 0FA6H 0FA7H 0FA8H 0FA9H 0FAAH 0FABH Register name Wild register address setting register (upper) ch. 1 Wild register address setting register (lower) ch. 1 Wild register data setting register ch. 1 Wild register address setting register (upper) ch. 2 Wild register address setting register (lower) ch. 2 Wild register data setting register ch. 2 (Disabled) 8/16-bit composite timer 01 status control register 0 8/16-bit composite timer 00 status control register 0 8/16-bit composite timer 01 data register 8/16-bit composite timer 00 data register 8/16-bit composite timer 00/01 timer mode control register 8/16-bit composite timer 11 status control register 0 8/16-bit composite timer 10 status control register 0 8/16-bit composite timer 11 data register 8/16-bit composite timer 10 data register 8/16-bit composite timer 10/11 timer mode control register 8/16-bit PPG01 cycle setting buffer register 8/16-bit PPG00 cycle setting buffer register 8/16-bit PPG01 duty setting buffer register 8/16-bit PPG00 duty setting buffer register 8/16-bit PPG11 cycle setting buffer register 8/16-bit PPG10 cycle setting buffer register 8/16-bit PPG11 duty setting buffer register 8/16-bit PPG10 duty setting buffer register 8/16-bit PPG startup register 8/16-bit PPG output reverse register 8/16-bit PPG21 cycle setting buffer register 8/16-bit PPG20 cycle setting buffer register 16-bit reload timer timer register (upper) 16-bit reload timer reload register (upper) 16-bit reload timer timer register (lower) 16-bit reload timer reload register (lower) 8/16-bit PPG21 duty setting buffer register 8/16-bit PPG20 duty setting buffer register R/W Initial value R/W R/W R/W R/W R/W R/W — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B — 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B 11111111B 11111111B 00000000B 00000000B 11111111B 11111111B (Continued) 24 DS07–12632–2E MB95390H Series Register abbreviation — PDCRH1 PDCRL1 PCSRH1 PCSRL1 PDUTH1 PDUTL1 — BGR1 BGR0 PSSR0 BRSR0 — AIDRH AIDRL OPDBRH0 OPDBRL0 OPDBRH1 OPDBRL1 OPDBRH2 OPDBRL2 OPDBRH3 OPDBRL3 OPDBRH4 OPDBRL4 OPDBRH5 OPDBRL5 OPDBRH6 OPDBRL6 OPDBRH7 OPDBRL7 OPDBRH8 OPDBRL8 OPDBRH9 OPDBRL9 OPDBRHA OPDBRLA Address 0FACH to 0FAFH 0FB0H 0FB1H 0FB2H 0FB3H 0FB4H 0FB5H 0FB6H to 0FBBH 0FBCH 0FBDH 0FBEH 0FBFH 0FC0H, 0FC1H 0FC2H 0FC3H 0FC4H 0FC5H 0FC6H 0FC7H 0FC8H 0FC9H 0FCAH 0FCBH 0FCCH 0FCDH 0FCEH 0FCFH 0FD0H 0FD1H 0FD2H 0FD3H 0FD4H 0FD5H 0FD6H 0FD7H 0FD8H 0FD9H Register name (Disabled) 16-bit PPG down counter register (upper) 16-bit PPG down counter register (lower) 16-bit PPG cycle setting buffer register (upper) 16-bit PPG cycle setting buffer register (lower) 16-bit PPG duty setting buffer register (upper) 16-bit PPG duty setting buffer register (lower) (Disabled) LIN-UART baud rate generator register 1 LIN-UART baud rate generator register 0 UART/SIO prescaler select register UART/SIO baud rate setting register (Disabled) A/D input disable register (upper) A/D input disable register (lower) Output data buffer register (upper) ch. 0 Output data buffer register (lower) ch. 0 Output data buffer register (upper) ch. 1 Output data buffer register (lower) ch. 1 Output data buffer register (upper) ch. 2 Output data buffer register (lower) ch. 2 Output data buffer register (upper) ch. 3 Output data buffer register (lower) ch. 3 Output data buffer register (upper) ch. 4 Output data buffer register (lower) ch. 4 Output data buffer register (upper) ch. 5 Output data buffer register (lower) ch. 5 Output data buffer register (upper) ch. 6 Output data buffer register (lower) ch. 6 Output data buffer register (upper) ch. 7 Output data buffer register (lower) ch. 7 Output data buffer register (upper) ch. 8 Output data buffer register (lower) ch. 8 Output data buffer register (upper) ch. 9 Output data buffer register (lower) ch. 9 Output data buffer register (upper) ch. A Output data buffer register (lower) ch. A R/W Initial value — R R R/W R/W R/W R/W — R/W R/W R/W R/W — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W — 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B — 00000000B 00000000B 00000000B 00000000B — 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued) DS07–12632–2E 25 MB95390H Series (Continued) Address 0FDAH 0FDBH 0FDCH 0FDDH 0FDEH 0FDFH 0FE0H, 0FE1H 0FE2H 0FE3H 0FE4H 0FE5H 0FE6H, 0FE7H 0FE8H 0FE9H 0FEAH 0FEBH 0FECH 0FEDH 0FEEH 0FEFH 0FF0H to 0FFFH Register abbreviation OPDBRHB OPDBRLB OPDUR OPDLR CPCUR CPCLR — TMBUR TMBLR CRTH CRTL — SYSC CMCR CMDR WDTH WDTL — ILSR WICR — Input level select register Interrupt pin control register (Disabled) Register name Output data buffer register (upper) ch. B Output data buffer register (lower) ch. B Output data register (upper) Output data register (lower) Compare clear register (upper) Compare clear register (lower) (Disabled) Timer buffer register (upper) Timer buffer register (lower) Main CR clock trimming register (upper) Main CR clock trimming register (lower) (Disabled) System configuration register Clock monitoring control register Clock monitoring data register Watchdog timer selection ID register (upper) Watchdog timer selection ID register (lower) (Disabled) R/W Initial value R/W R/W R R 00000000B 00000000B 0000XXXXB XXXXXXXXB R/W XXXXXXXXB R/W XXXXXXXXB — R R — XXXXXXXXB XXXXXXXXB R/W 0XXXXXXXB R/W 00XXXXXXB — R/W R/W R R R — R/W R/W — — 11000011B 00000000B 00000000B XXXXXXXXB XXXXXXXXB — 00000000B 01000000B — • R/W access symbols R/W : Readable / Writable R : Read only W : Write only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is indeterminate. Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned. 26 DS07–12632–2E MB95390H Series ■ INTERRUPT SOURCE TABLE Vector table address Interrupt source Interrupt request number IRQ00 IRQ01 IRQ02 IRQ03 IRQ04 IRQ05 IRQ06 IRQ07 IRQ08 IRQ09 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 Priority order of interrupt Bit name of sources of the interrupt level same level setting register (occurring simultaneously) L00 [1:0] L01 [1:0] L02 [1:0] L03 [1:0] L04 [1:0] L05 [1:0] L06 [1:0] L07 [1:0] L08 [1:0] L09 [1:0] L10 [1:0] L11 [1:0] L12 [1:0] L13 [1:0] L14 [1:0] L15 [1:0] L16 [1:0] High Upper Lower External interrupt ch. 0, ch. 4 External interrupt ch. 1, ch. 5 External interrupt ch. 2, ch. 6 External interrupt ch. 3, ch. 7 UART/SIO ch. 0, MPG (DTTI) 8/16-bit composite timer ch. 0 (lower) 8/16-bit composite timer ch. 0 (upper) LIN-UART (reception) LIN-UART (transmission) 8/16-bit PPG ch. 1 (lower) 8/16-bit PPG ch. 1 (upper) 8/16-bit PPG ch. 2 (upper) 8/16-bit PPG ch. 0 (upper) 8/16-bit PPG ch. 0 (lower) 8/16-bit composite timer ch. 1 (upper) 8/16-bit PPG ch. 2 (lower) 16-bit reload timer ch. 1, MPG (write timing/compare clear), I2C 16-bit PPG timer ch. 1, MPG (position detection/compare match) 8/10-bit A/D converter Time-base timer Watch prescaler — 8/16-bit composite timer ch. 1 (lower) Flash memory FFFAH FFF8H FFF6H FFF4H FFF2H FFF0H FFEEH FFECH FFEAH FFE8H FFE6H FFE4H FFE2H FFE0H FFDEH FFDCH FFDAH FFFBH FFF9H FFF7H FFF5H FFF3H FFF1H FFEFH FFEDH FFEBH FFE9H FFE7H FFE5H FFE3H FFE1H FFDFH FFDDH FFDBH IRQ17 IRQ18 IRQ19 IRQ20 IRQ21 IRQ22 IRQ23 FFD8H FFD6H FFD4H FFD2H FFD0H FFCEH FFCCH FFD9H FFD7H FFD5H FFD3H FFD1H FFCFH FFCDH L17 [1:0] L18 [1:0] L19 [1:0] L20 [1:0] L21 [1:0] L22 [1:0] L23 [1:0] Low DS07–12632–2E 27 MB95390H Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Power supply voltage*1 Input voltage*1 Output voltage* 1 Symbol VCC VI VO ICLAMP Σ|ICLAMP| IOL1 IOL2 Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 −2 — — — Max VSS + 6 VSS + 6 VSS + 6 +2 20 15 15 Unit V V V mA mA mA *2 *2 Remarks Maximum clamp current Total maximum clamp current “L” level maximum output current Applicable to specific pins*3 Applicable to specific pins*3 Other than P62 to P67 P62 to P67 Other than P62 to P67 Average output current = operating current × operating ratio (1 pin) P62 to P67 Average output current = operating current × operating ratio (1 pin) IOLAV1 “L” level average current IOLAV2 — 4 mA — 12 “L” level total maximum output current “L” level total average output current “H” level maximum output current ΣIOL ΣIOLAV IOH1 IOH2 — 100 mA Total average output current = operating current × operating ratio (Total number of pins) Other than P12, P62 to P67, P72, P73 and PF2 P12, P62 to P67, P72, P73 and PF2 Other than P12, P62 to P67, P72, P73 and PF2 Average output current = operating current × operating ratio (1 pin) P12, P62 to P67, P72, P73 and PF2 Average output current = operating current × operating ratio (1 pin) mA Total average output current = operating current × operating ratio (Total number of pins) — 50 −15 −15 mA — — mA IOHAV1 “H” level average current IOHAV2 — −4 mA — −8 “H” level total maximum output current “H” level total average output current Power consumption Operating temperature Storage temperature ΣIOH ΣIOHAV Pd TA Tstg — −100 −50 320 +85 +150 — — −40 −55 mA mW °C °C (Continued) 28 DS07–12632–2E MB95390H Series (Continued) *1: The parameter is based on VSS = 0.0 V. *2: VI and VO must not exceed VCC + 0.3 V. VI must not exceed the rated voltage. However, if the maximum current to/from an input is limited by means of an external component, the ICLAMP rating is used instead of the VI rating. *3: Applicable to the following pins: P00 to P07, P10, P11, P13 to P17, P40 to P47, P60 to P67, P70, P71, P74 to P77, PF0, PF1, PG1 and PG2 • Use under recommended operating conditions. • Use with DC voltage (current). • The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor between the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal. • The value of the limiting resistor should be set to a value at which the current to be input to the microcontroller pin when the HV (High Voltage) signal is input is below the standard value, irrespective of whether the current is transient current or stationary current. • When the microcontroller drive current is low, such as in low power consumption modes, the HV (High Voltage) input potential may pass through the protective diode to increase the potential of the VCC pin, affecting other devices. • If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since power is supplied from the pins, incomplete operations may be executed. • If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage of power supply may not be sufficient to enable a power-on reset. • Do not leave the HV (High Voltage) input pin unconnected. • Example of a recommended circuit • Input/Output equivalent circuit Protective diode VCC Limiting resistor P-ch N-ch R HV(High Voltage) input (0 V to 16 V) WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. DS07–12632–2E 29 MB95390H Series 2. Recommended Operating Conditions (VSS = 0.0 V) Parameter Symbol Value Min 2.4*1*2 Power supply voltage VCC 2.3 2.9 2.3 Smoothing capacitor Operating temperature CS TA 0.022 −40 +5 Max 5.5*1 5.5 5.5 5.5 1 +85 +35 V Unit In normal operation In normal operation Hold condition in stop mode µF *3 °C Other than on-chip debug mode On-chip debug mode Remarks Other than on-chip debug Hold condition in stop mode mode On-chip debug mode *1: The value varies depending on the operating frequency, the machine clock and the analog guaranteed range. *2: This value becomes 2.88 V when the low-voltage detection reset is used. *3: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for the VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see the diagram below. To prevent the device from unintentionally entering an unknown mode due to noise, minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed circuit board. • DBG / RST / C pins connection diagram * DBG C RST Cs *: Since the DBG pin becomes a communication pin in on-chip debug mode, set a pull-up resistor value suiting the input/output specifications of P12/DBG. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. 30 DS07–12632–2E MB95390H Series 3. DC Characteristics (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C) Parameter Symbol Pin name P47, P72, P73, P77 P00 to P07, P10 to P17, P40 to P47, P60 to P67, P70 to P77, PF0, PF1, PG1, PG2 PF2 P47, P72, P73, P77 P00 to P07, P10 to P17, P40 to P47, P60 to P67, P70 to P77, PF0, PF1, PG1, PG2 PF2 P12, P72, P73, PF2 Condition Value Min 0.7 VCC Typ*3 — Max VCC + 0.3 Unit Remarks When CMOS input level (hysteresis input) is selected VIHI *1 V "H" level input voltage VIHS *1 0.8 VCC — VCC + 0.3 V Hysteresis input VIHM VIL — *1 0.7 VCC VSS − 0.3 — — VCC + 0.3 0.3 VCC V V Hysteresis input When CMOS input level (hysteresis input) is selected “L” level input voltage VILS *1 VSS − 0.3 — 0.2 VCC V Hysteresis input VILM Open-drain output application voltage “H” level output voltage VD — — VSS − 0.3 VSS − 0.3 — — 0.3 VCC VSS + 5.5 V V Hysteresis input VOH1 VOH2 Output pins other than P12, IOH = −4 mA P62 to P67, P72, P73, PF2 P62 to P67 Output pins other than P62 to P67 P62 to P67 All input pins P00 to P07, P10, P11, P13 to P17, P40 to P47, P60, P61, P70, P71, P74 to P76, PG1, PG2 IOH = −8 mA IOL = 4 mA IOL = 12 mA 0.0 V < VI < VCC VCC − 0.5 VCC − 0.5 — — −5 — — — — — — — 0.4 0.4 +5 V V V V When pull-up µA resistance is disabled “L” level output voltage Input leak current (Hi-Z output leak current) VOL1 VOL2 ILI Pull-up resistance RPULL VI = 0 V 25 50 100 When pull-up kΩ resistance is enabled (Continued) DS07–12632–2E 31 MB95390H Series (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C) Parameter Symbol Input capacitance CIN Pin name Condition Value Min — — Typ*3 5 14.8 Max 15 17 Unit pF Except during Flash mA memory writing and erasing During Flash mA memory writing and erasing mA At A/D conversion Remarks Other than VCC f = 1 MHz and VSS VCC = 5.5 V FCH = 32 MHz FMP = 16 MHz Main clock mode (divided by 2) VCC = 5.5 V FCH = 32 MHz FMP = 16 MHz Main sleep mode (divided by 2) VCC = 5.5 V VCC (External clock FCL = 32 kHz FMPL = 16 kHz operation) Subclock mode (divided by 2) TA = +25°C VCC = 5.5 V FCL = 32 kHz FMPL = 16 kHz Subsleep mode (divided by 2) TA = +25°C VCC = 5.5 V FCL = 32 kHz Watch mode Main stop mode TA = +25°C VCC = 5.5 V FCRH = 12.5 MHz FMP = 12.5 MHz Main CR clock mode VCC = 5.5 V Sub-CR clock mode (divided by 2) TA = +25°C ICC — — 33.5 16.6 39.5 21 ICCS — 7 9 mA ICCL — 60 153 µA Power supply current*2 ICCLS — 9.4 84 µA ICCT — 4.3 30 µA ICCMCR VCC ICCSCR — 11.8 13.2 mA — 113 410 µA (Continued) 32 DS07–12632–2E MB95390H Series (Continued) Parameter Symbol Pin name (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C) Value Condition Unit Remarks Min Typ*3 Max ICCTS ICCH VCC = 5.5 V FCH = 32 MHz Time-base timer VCC mode (External clock TA = +25°C operation) VCC = 5.5 V Substop mode TA = +25°C Current consumption for low-voltage detection circuit only Current consumption for the main CR oscillator Current consumption for the sub-CR oscillator oscillating at 100 kHz — 0.9 3 mA — 3.4 22.5 µA Power supply current*2 ILVD — 31 54 µA ICRH VCC — 0.5 0.6 mA ICRL — 20 72 µA *1: The input levels of P47, P72, P73 and P77 can be switched between “CMOS input level” and “hysteresis input level”. The input level selection register (ILSR) is used to switch between the two input levels. *2: • The power supply current is determined by the external clock. When the low-voltage detection option is selected, the power-supply current will be the sum of adding the current consumption of the low-voltage detection circuit (ILVD) to one of the value from ICC to ICCH. In addition, when both the low-voltage detection option and the CR oscillator are selected, the power supply current will be the sum of adding up the current consumption of the low-voltage detection circuit, the current consumption of the CR oscillators (ICRH, ICRL) and a specified value. In on-chip debug mode, the CR oscillator (ICRH) and the low-voltage detection circuit are always enabled, and current consumption therefore increases accordingly. • See "4. AC Characteristics: (1) Clock Timing" for FCH and FCL. • See "4. AC Characteristics: (2) Source Clock/Machine Clock" for FMP and FMPL. *3: VCC = 5.0 V, TA = 25°C DS07–12632–2E 33 MB95390H Series 4. AC Characteristics (1) Clock Timing (VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = −40°C to +85°C) Parameter Symbol Pin name Condition X0, X1 FCH X0 X0, X1 — X1: open *1 Value Min 1 1 1 12.25 9.80 7.84 Clock frequency FCRH — — 0.98 12.18 9.75 7.80 0.97 — FCL X0A, X1A — — FCRL — X0, X1 Clock cycle time tHCYL X0 X0, X1 tLCYL Input clock pulse width Input clock rise time and fall time CR oscillation start time tWH1 tWL1 tWH2 tWL2 tCR tCF tCRHWK tCRLWK X0A, X1A X0 X0, X1 X0A X0 X0, X1 — — — — X1: open *1 — X1: open *1 — X1: open *1 — — 50 61.5 83.4 30.8 — 33.4 12.4 — — — — — 32.768 100 — — — 30.5 — — 15.2 — — — — — 200 1000 1000 1000 — — — — 5 5 80 10 kHz kHz ns ns ns µs ns ns µs ns ns µs µs Typ — — — 12.5 10 8 1 12.5 10 8 1 32.768 Max Unit Remarks When the main oscillation circuit is used 16.25 MHz 12 32.5 MHz When the main external MHz clock is used 12.75 MHz 10.20 MHz When the main CR clock is *2 8.16 MHz used 1.02 MHz 12.82 MHz 10.25 MHz When the main CR clock is *3 8.20 MHz used 1.03 — MHz kHz When the sub-oscillation circuit is used When the sub-external clock is used When the sub-CR clock is used When the main oscillation circuit is used When the external clock is used When the subclock is used When the external clock is used, the duty ratio should range between 40% and 60%. When the external clock is used When the main CR clock is used When the sub-CR clock is used *1: The external clock signal is input to X0 and the inverted external clock signal to X1. *2: These specifications are only applicable to a product in LQFP package (FPT-48P-M49 or FPT-52P-M02). *3: These specifications are only applicable to a product in QFN package (LCC-48P-M11). 34 DS07–12632–2E MB95390H Series • Input waveform generated when an external clock (main clock) is used tHCYL tWH1 tCR 0.8 VCC 0.8 VCC X0, X1 0.2 VCC 0.2 VCC 0.2 VCC tCF tWL1 • Figure of main clock input port external connection When a crystal oscillator or a ceramic oscillator is used When the external clock is used When the external clock (X1 is open) is used X0 X1 FCH X0 X1 Open FCH X0 X1 FCH • Input waveform generated when an external clock (subclock) is used tLCYL tWH2 tCR 0.8 VCC 0.8 VCC X0A 0.2 VCC 0.2 VCC 0.2 VCC tCF tWL2 • Figure of subclock input port external connection When a crystal oscillator or a ceramic oscillator is used When the external clock is used X0A X1A FCL X0A X1A Open FCL DS07–12632–2E 35 MB95390H Series (2) Source Clock/Machine Clock (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C) Parameter Symbol Pin name Value Min 61.5 Typ — Max 2000 Unit Remarks When the main external clock is used Min: FCH = 32.5 MHz, divided by 2 Max: FCH = 1 MHz, divided by 2 When the main CR clock is used Min: FCRH = 12.5 MHz Max: FCRH = 1 MHz When the sub-oscillation clock is used FCL = 32.768 kHz, divided by 2 When the sub-CR clock is used FCRL = 100 kHz, divided by 2 ns Source clock cycle time*1 tSCLK — 80 — 1000 ns — — FSP Source clock frequency FSPL — 0.5 1 — — 61 20 — — 16.384 50 — — 16.25 12.5 — — µs µs MHz When the main oscillation clock is used MHz When the main CR clock is used kHz When the sub-oscillation clock is used kHz When the sub-CR clock is used FCRL = 100 kHz, divided by 2 When the main oscillation clock is used Min: FSP = 16.25 MHz, no division Max: FSP = 0.5 MHz, divided by 16 When the main CR clock is used Min: FSP = 12.5 MHz Max: FSP = 1 MHz, divided by 16 When the sub-oscillation clock is used Min: FSPL = 16.384 kHz, no division Max: FSPL = 16.384 kHz, divided by 16 When the sub-CR clock is used Min: FSPL = 50 kHz, no division Max: FSPL = 50 kHz, divided by 16 61.5 Machine clock cycle time*2 (minimum instruction execution time) — 32000 ns 80 tMCLK — 61 — 16000 ns — 976.5 µs 20 0.031 0.0625 — FMPL 1.024 3.125 — — — — — 320 16.25 12.5 16.384 50 µs FMP Machine clock frequency MHz When the main oscillation clock is used MHz When the main CR clock is used kHz When the sub-oscillation clock is used kHz When the sub-CR clock is used FCRL = 100 kHz *1: This is the clock before it is divided according to the division ratio set by the machine clock divide ratio select bits (SYCC:DIV1, DIV0). This source clock is divided to become a machine clock according to the divide ratio set by the machine clock divide ratio select bits (SYCC:DIV1, DIV0). In addition, a source clock can be selected from the following. • Main clock divided by 2 • Main CR clock • Subclock divided by 2 • Sub-CR clock divided by 2 *2: This is the operating clock of the microcontroller. A machine clock can be selected from the following. • Source clock (no division) • Source clock divided by 4 • Source clock divided by 8 • Source clock divided by 16 36 DS07–12632–2E MB95390H Series • Schematic diagram of the clock generation block FCH (Main oscillation) FCRH (Main CR clock) FCL (Sub-oscillation) Divided by 2 Divided by 2 SCLK (Source clock) FCRL (Sub-CR clock) Divided by 2 Division circuit ×1 × 1/4 × 1/8 ×1/16 MCLK (Machine clock) Clock mode select bits (SYCC2: RCS1, RCS0) Machine clock divide ratio select bits (SYCC:DIV1, DIV0) • Operating voltage - Operating frequency (When TA = −40°C to +85°C) MB95390H (without the on-chip debug function) 5.5 5.0 Operating voltage (V) A/D converter operation range 4.0 3.5 3.0 2.4 16 kHz 3 MHz 10 MHz 16.25 MHz Source clock frequency (FSP/FSPL) • Operating voltage - Operating frequency (When TA = −40°C to +85°C) MB95390H (with the on-chip debug function) 5.5 5.0 Operating voltage (V) A/D converter operation range 4.0 3.5 3.0 2.9 16 kHz 3 MHz 12.5 MHz 16.25 MHz Source clock frequency (FSP) DS07–12632–2E 37 MB95390H Series (3) External Reset (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C) Parameter Symbol Value Min 2 tMCLK*1 RST “L” level pulse width tRSTL Oscillation time of the oscillator*2 + 100 100 *1: See “(2) Source Clock/Machine Clock” for tMCLK. *2: The oscillation time of an oscillator is the time for it to reach 90% of its amplitude. The crystal oscillator has an oscillation time of between several ms and tens of ms. The ceramic oscillator has an oscillation time of between hundreds of µs and several ms. The external clock has an oscillation time of 0 ms. The CR oscillator clock has an oscillation time of between several µs and several ms. • In normal operation tRSTL RST 0.2 VCC 0.2 VCC Max — — — Unit ns µs µs Remarks In normal operation In stop mode, subclock mode, subsleep mode, watch mode, and power-on In time-base timer mode • In stop mode, subclock mode, subsleep mode, watch mode and power-on RST tRSTL 0.2 VCC 90% of amplitude 0.2 VCC X0 Internal operating clock Oscillation time of oscillator Internal reset 100 μs Oscillation stabilization wait time Execute instruction 38 DS07–12632–2E MB95390H Series (4) Power-on Reset (VSS = 0.0 V, TA = −40°C to +85°C) Parameter Power supply rising time Power supply cutoff time Symbol tR tOFF Condition — — Value Min — 1 Max 50 — Unit ms ms Wait time until power-on Remarks tR 2.5 V tOFF VCC 0.2 V 0.2 V 0.2 V Note: A sudden change of power supply voltage may activate the power-on reset function. When changing the power supply voltage during the operation, set the slope of rising to a value below within 30 mV/ms as shown below. VCC Set the slope of rising to a value below 30 mV/ms. Hold condition in stop mode 2.3 V VSS DS07–12632–2E 39 MB95390H Series (5) Peripheral Input Timing (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C) Parameter Peripheral input “H” pulse width Peripheral input “L” pulse width Symbol tILIH tIHIL Pin name INT00 to INT07, EC0, EC1,TI1, TRG1 Value Min 2 tMCLK* 2 tMCLK* Max — — Unit ns ns *: See “(2) Source Clock/Machine Clock” for tMCLK. tILIH tIHIL INT00 to INT07, EC0, EC1, TI1, TRG1 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 40 DS07–12632–2E MB95390H Series (6) LIN-UART Timing Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is disabled*2. (ESCR register: SCES bit = 0, ECCR register: SCDE bit = 0) (VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C) Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time Serial clock “L” pulse width Serial clock “H” pulse width SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time SCK fall time SCK rise time Symbol Pin name tSCYC tSLOVI tIVSHI tSHIXI tSLSH tSHSL tSLOVE tIVSHE tSHIXE tF tR SCK Condition Value Min 5 tMCLK*3 Max — +95 — — — — 2 tMCLK*3 + 95 — — 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns SCK, SOT Internal clock −95 operation output pin: SCK, SIN CL = 80 pF + 1 TTL tMCLK*3 + 190 SCK, SIN 0 SCK SCK SCK, SOT SCK, SIN SCK, SIN SCK SCK External clock operation output pin: CL = 80 pF + 1 TTL 3t MCLK 3 * − tR tMCLK*3 + 95 — 190 t MCLK 3 * + 95 — — *1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock. *3: See “(2) Source Clock/Machine Clock” for tMCLK. DS07–12632–2E 41 MB95390H Series • Internal shift clock mode tSCYC 2.4 V SCK 0.8 V tSLOVI 2.4 V SOT 0.8 V tIVSHI SIN 0.2 VCC 0.2 VCC tSHIXI 0.8 V 0.8 VCC 0.8 VCC • External shift clock mode tSLSH 0.8 VCC SCK 0.2 VCC tF SOT 0.8 V tIVSHE SIN 0.2 VCC 0.2 VCC tSHIXE tSLOVE 2.4 V 0.2 VCC tR 0.8 VCC tSHSL 0.8 VCC 0.8 VCC 0.8 VCC 42 DS07–12632–2E MB95390H Series Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is disabled*2. (ESCR register: SCES bit = 1, ECCR register: SCDE bit = 0) (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C) Parameter Serial clock cycle time SCK ↑ → SOT delay time Valid SIN → SCK ↓ SCK ↓ → valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↑ → SOT delay time Valid SIN → SCK ↓ SCK ↓ → valid SIN hold time SCK fall time SCK rise time Symbol Pin name tSCYC tSHOVI tIVSLI tSLIXI tSHSL tSLSH tSHOVE tIVSLE tSLIXE tF tR SCK Condition Value Min 5 tMCLK*3 Max — +95 — — — — 2 tMCLK*3 + 95 — — 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns SCK, SOT Internal clock −95 operation output pin: SCK, SIN CL = 80 pF + 1 TTL tMCLK*3 + 190 SCK, SIN 0 SCK SCK SCK, SOT SCK, SIN SCK, SIN SCK SCK External clock operation output pin: CL = 80 pF + 1 TTL 3t MCLK 3 * − tR tMCLK*3 + 95 — 190 t MCLK 3 * + 95 — — *1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock. *3: See “(2) Source Clock/Machine Clock” for tMCLK. DS07–12632–2E 43 MB95390H Series • Internal shift clock mode tSCYC 2.4 V SCK 0.8 V tSHOVI 2.4 V SOT 0.8 V tIVSLI SIN 0.2 VCC 0.2 VCC tSLIXI 2.4 V 0.8 VCC 0.8 VCC • External shift clock mode tSHSL 0.8 VCC SCK 0.2 VCC tR SOT 0.8 V tIVSLE SIN 0.2 VCC 0.2 VCC tSLIXE tSHOVE 2.4 V tF 0.2 VCC 0.2 VCC 0.8 VCC tSLSH 0.8 VCC 0.8 VCC 44 DS07–12632–2E MB95390H Series Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is enabled*2. (ESCR register: SCES bit = 0, ECCR register: SCDE bit = 1) (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C) Parameter Serial clock cycle time SCK ↑ → SOT delay time Valid SIN → SCK ↓ SCK ↓ → valid SIN hold time SOT → SCK ↓ delay time Symbol Pin name tSCYC tSHOVI tIVSLI tSLIXI tSOVLI SCK SCK, SOT SCK, SIN SCK, SIN SCK, SOT Condition Value Min 5 tMCLK*3 −95 Internal clock operation output pin: tMCLK*3 + 190 CL = 80 pF + 1 TTL 0 — Max — +95 — — 4 tMCLK*3 Unit ns ns ns ns ns *1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock. *3: See “(2) Source Clock/Machine Clock” for tMCLK. tSCYC SCK tSOVLI 2.4 V 0.8 V 2.4 V 0.8 V tIVSLI tSLIXI 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSHOVI 2.4 V 0.8 V 0.8 V SOT SIN DS07–12632–2E 45 MB95390H Series Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is enabled*2. (ESCR register: SCES bit = 1, ECCR register: SCDE bit = 1) (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C) Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time SOT → SCK ↑ delay time Symbol Pin name tSCYC tSLOVI tIVSHI tSHIXI tSOVHI SCK Condition Value Min 5 tMCLK*3 Max — +95 — — 4t MCLK 3 Unit ns ns ns ns * ns SCK, SOT Internal clock −95 SCK, SIN operation output pin: tMCLK*3 + 190 CL = 80 pF + 1 TTL SCK, SIN 0 SCK, SOT — *1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock. *3: See “(2) Source Clock/Machine Clock” for tMCLK. tSCYC SCK tSOVHI 2.4 V 0.8 V tSLOVI 2.4 V 0.8 V tIVSHI tSHIXI 0.8 VCC 0.2 VCC 2.4 V 0.8 V 0.8 VCC 0.2 VCC 2.4 V SOT SIN 46 DS07–12632–2E MB95390H Series (7) Low-voltage Detection (VSS = 0.0 V, TA = −40°C to +85°C) Parameter Release voltage Detection voltage Hysteresis width Power supply start voltage Power supply end voltage Power supply voltage change time (at power supply rise) Power supply voltage change time (at power supply fall) Reset release delay time Reset detection delay time Symbol VDL+ VDLVHYS Voff Von tr Value Min 2.52 2.42 70 — 4.9 3000 Typ 2.7 2.6 100 — — — Max 2.88 2.78 — 2.3 — — Unit V V mV V V µs Slope of power supply that the reset release signal generates within the rating (VDL+) Slope of power supply that the reset detection signal generates within the rating (VDL-) Remarks At power supply rise At power supply fall tf td1 td2 300 — — — — — — 300 20 µs µs µs VCC Von Voff time tf tr VDL+ VHYS VDL- Internal reset signal time td2 td1 DS07–12632–2E 47 MB95390H Series (8) I2C Timing (VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C) Value Parameter Symbol Pin name Condition Standardmode Min SCL clock frequency (Repeated) START condition hold time SDA ↓ → SCL ↓ SCL clock “L” width SCL clock “H” width (Repeated) START condition setup time SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓↑ Data setup time SDA ↓↑ → SCL ↑ STOP condition setup time SCL ↑ → SDA ↑ Bus free time between STOP condition and START condition fSCL tHD;STA tLOW tHIGH tSU;STA SCL SCL, SDA SCL SCL SCL, SDA R = 1.7 kΩ, C = 50 pF*1 tHD;DAT tSU;DAT tSU;STO tBUF SCL, SDA SCL, SDA SCL, SDA SCL, SDA 0 0.25 4 4.7 3.45*2 — — — 0 0.1 0.6 1.3 0.9*3 — — — µs µs µs µs 0 4.0 4.7 4.0 4.7 Max 100 — — — — Fast-mode Unit Min 0 0.6 1.3 0.6 0.6 Max 400 — — — — kHz µs µs µs µs *1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines. *2: The maximum tHD;DAT in the Standard-mode is applicable only when the time during which the device is holding the SCL signal at “L” (tLOW) does not extend. *3: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, provided that the condition of tSU;DAT ≥ 250 ns is fulfilled. tWAKEUP SDA tLOW SCL tHD;STA tSU;DAT fSCL tSU;STA tSU;STO tHD;DAT tHIGH tHD;STA tBUF (Continued) 48 DS07–12632–2E MB95390H Series (VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C) Parameter SCL clock “L” width SCL clock “H” width Sym- Pin Condition bol name tLOW SCL tHIGH SCL Value*2 Min (2 + nm/2)tMCLK − 20 (nm/2)tMCLK − 20 Max — (nm/2)tMCLK + 20 Unit ns ns Remarks Master mode Master mode Master mode Maximum value is applied when m, n = 1, 8. Otherwise, the minimum value is applied. Master mode START SCL, condition hold tHD;STA SDA time (−1 + nm/2)tMCLK − 20 (−1 + nm)tMCLK + 20 ns STOP condition setup time START condition setup time Bus free time between STOP condition and START condition Data hold time tSU;STO SCL, SDA SCL, SDA (1 + nm/2)tMCLK − 20 (1 + nm/2)tMCLK + 20 ns tSU;STA (1 + nm/2)tMCLK − 20 (1 + nm/2)tMCLK + 20 ns Master mode tBUF SCL, SDA R = 1.7 kΩ, C = 50 pF*1 (2 nm + 4)tMCLK − 20 — ns tHD;DAT SCL, SDA 3 tMCLK − 20 — ns Master mode Master mode When assuming that “L” of SCL is not extended, the minimum value is applied to first bit of continuous data. Otherwise, the maximum value is applied. Minimum value is applied to interrupt at 9th SCL↓. Maximum value is applied to the interrupt at the 8th SCL↓. (Continued) Data setup time tSU;DAT SCL, SDA (−2 + nm/2)tMCLK − 20 (−1 + nm/2)tMCLK + 20 ns Setup time between clearing inter- tSU;INT SCL rupt and SCL rising (nm/2)tMCLK − 20 (1 + nm/2)tMCLK + 20 ns DS07–12632–2E 49 MB95390H Series (Continued) Parameter SCL clock “L” width SCL clock “H” width START condition detection STOP condition detection (VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C) Value*2 Sym- Pin Unit Remarks Condition bol name Min Max tLOW tHIGH tHD;STA SCL SCL SCL, SDA SCL, SDA 4 tMCLK − 20 4 tMCLK − 20 2 tMCLK − 20 — — — ns ns ns At reception At reception Not detected when 1 tMCLK is used at reception Not detected when 1 tMCLK is used at reception Not detected when 1 tMCLK is used at reception At reception At slave transmission mode At slave transmission mode At reception At reception tSU;STO 2 tMCLK − 20 — ns RESTART condition SCL, tSU;STA detection condition SDA Bus free time Data hold time Data setup time Data hold time Data setup time tBUF tHD;DAT tSU;DAT tHD;DAT tSU;DAT SCL, SDA SCL, SDA SCL, SDA SCL, SDA SCL, SDA R = 1.7 kΩ, C = 50 pF*1 2 tMCLK − 20 — ns 2 tMCLK − 20 2 tMCLK − 20 tLOW − 3 tMCLK − 20 0 tMCLK − 20 Oscillation stabilization wait time +2 tMCLK − 20 — — — — — ns ns ns ns ns SCL, SDA↓ → SCL↑ tWAKEUP SDA (at wakeup function) — ns *1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines. *2: • • • • See “(2) Source Clock/Machine Clock” for tMCLK. m represents the CS4 bit and CS3 bit (bit4 and bit3) in the I2C clock control register (ICCR0). n represents the CS2 bit to CS0 bit (bit2 to bit0) in the I2C clock control register (ICCR0). The actual timing of I2C is determined by the values of m and n set by the machine clock (tMCLK) and the CS4 to CS0 bits in the ICCR0 register. • Standard-mode: m and n can be set to values in the following range: 0.9 MHz < tMCLK (machine clock) < 10 MHz. The usable frequencies of the machine clock are determined by the settings of m and n as shown below. (m, n) = (1, 8) : 0.9 MHz < tMCLK ≤ 1 MHz (m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz (m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz (m, n) = (1, 98) : 0.9 MHz < tMCLK ≤ 10 MHz • Fast-mode: m and n can be set to values in the following range: 3.3 MHz < tMCLK (machine clock) < 10 MHz. The usable frequencies of the machine clock are determined by the settings of m and n as shown below. (m, n) = (1, 8) : 3.3 MHz < tMCLK ≤ 4 MHz (m, n) = (1, 22), (5, 4) : 3.3 MHz < tMCLK ≤ 8 MHz (m, n) = (6, 4) : 3.3 MHz < tMCLK ≤ 10 MHz 50 DS07–12632–2E MB95390H Series (9) UART/SIO, Serial I/O Timing (VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C) Value Pin name Condition Unit Min Max UCK0 UCK0, UO0 UCK0, UI0 UCK, UI0 UCK0 UCK0 UCK0, UO0 UCK0, UI0 UCK0, UI0 External clock operation Internal clock operation 4 tMCLK* −190 2 tMCLK* 2 tMCLK* 4 tMCLK* 4 tMCLK* — 2 tMCLK* 2 tMCLK* — +190 — — — — 190 — — ns ns ns ns ns ns ns ns ns Parameter Serial clock cycle time UCK ↓ → UO time Valid UI → UCK ↑ UCK ↑ → valid UI hold time Serial clock “H” pulse width Serial clock “L” pulse width UCK ↓ → UO time Valid UI → UCK ↑ UCK ↑ → valid UI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX *: See “(2) Source Clock/Machine Clock” for tMCLK. • Internal shift clock mode tSCYC 2.4 V UCK0 0.8 V tSLOV 2.4 V UC0 0.8 V tIVSH UI0 0.2 VCC 0.2 VCC tSHIX 0.8 V 0.8 VCC 0.8 VCC • External shift clock mode tSLSH 0.8 VCC UCK0 0.2 VCC tSLOV 2.4 V UC0 0.8 V tIVSH UI0 0.2 VCC 0.2 VCC tSHIX 0.2 VCC tSHSL 0.8 VCC 0.8 VCC 0.8 VCC DS07–12632–2E 51 MB95390H Series (10) MPG Input Timing (VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C) Value Pin name Condition Unit Remarks Min Max SNI0 to SNI2, DTTI — 4 tMCLK — ns Parameter Input pulse width Symbol tTIWH tTIWL SNI0 to SNI2, DTTI 0.8 VCC 0.8 VCC 0.2 VCC tTIWH tTIWL 0.2 VCC 52 DS07–12632–2E MB95390H Series 5. A/D Converter (1) A/D Converter Electrical Characteristics (VCC = 4.0 V to 5.5 V, VSS = 0.0 V, TA = −40°C to +85°C) Parameter Resolution Total error Linearity error Differential linear error Zero transition voltage Full-scale transition voltage Compare time VOT VFST — — Symbol Value Min — −3 −2.5 −1.9 Typ — — — — Max 10 +3 +2.5 +1.9 Unit bit LSB LSB LSB V V µs µs µs 4.5 V ≤ VCC ≤ 5.5 V 4.0 V ≤ VCC < 4.5 V 4.5 V ≤ VCC ≤ 5.5 V, with external impedance < 5.4 kΩ 4.0 V ≤ VCC < 4.5 V, with external impedance < 2.4 kΩ Remarks VSS − 1.5 LSB VSS + 0.5 LSB VSS + 2.5 LSB VCC − 4.5 LSB 0.9 1.8 0.6 VCC − 2 LSB — — — VCC + 0.5 LSB 16500 16500 ∞ Sampling time — 1.2 — — — ∞ +0.3 VCC µs µA V Analog input current Analog input voltage IAIN VAIN −0.3 VSS DS07–12632–2E 53 MB95390H Series (2) Notes on Using the A/D Converter • External impedance of analog input and its sampling time • The A/D converter has a sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, considering the relationship between the external impedance and minimum sampling time, either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. In addition, if sufficient sampling time cannot be secured, connect a capacitor of about 0.1 µF to the analog input pin. • Analog input equivalent circuit Analog input R C Comparator During sampling: ON VCC 4.5 V ≤ VCC ≤ 5.5 V 4.0 V ≤ VCC < 4.5 V R 1.95 kΩ (Max) 8.98 kΩ (Max) C 17 pF (Max) 17 pF (Max) Note: The values are reference values. • Relationship between external impedance and minimum sampling time [External impedance = 0 kΩ to 100 kΩ] 100 20 [External impedance = 0 kΩ to 20 kΩ] External impedance [kΩ] 18 16 14 12 10 8 6 4 2 0 External impedance [kΩ] 90 80 70 60 50 40 30 20 10 0 0 2 4 6 8 10 12 14 (VCC ≥ 4.5 V) (VCC ≥ 4.0 V) (VCC ≥ 4.5 V) (VCC ≥ 4.0 V) 0 1 2 3 4 Minimum sampling time [μs] Minimum sampling time [μs] • A/D conversion error As |VCC−VSS| decreases, the A/D conversion error increases proportionately. 54 DS07–12632–2E MB95390H Series (3) Definitions of A/D Converter Terms • Resolution It indicates the level of analog variation that can be distinguished by the A/D converter. When the number of bits is 10, analog voltage can be divided into 210 = 1024. • Linearity error (unit: LSB) It indicates how much an actual conversion value deviates from the straight line connecting the zero transition point (“00 0000 0000” ← → “00 0000 0001”) of a device to the full-scale transition point (“11 1111 1111” ← → “11 1111 1110”) of the same device. • Differential linear error (unit: LSB) It indicates how much the input voltage required to change the output code by 1 LSB deviates from an ideal value. • Total error (unit: LSB) It indicates the difference between an actual value and a theoretical value. The error can be caused by a zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise. Ideal I/O characteristics 3FFH 3FEH 3FDH 2 LSB Total error 3FFH 3FEH 3FDH Actual conversion characteristic {1 LSB × (N-1) + 0.5 LSB} VFST Digital output Digital output 004H 003H 002H 001H 0.5 LSB 004H 003H VOT 1 LSB VNT Actual conversion characteristic Ideal characteristic 002H 001H VSS Analog input 1 LSB = VCC - VSS (V) 1024 VCC VSS Analog input VCC VNT - {1 LSB × (N - 1) + 0.5 LSB} Total error of = [LSB] digital output N 1 LSB N : A/D converter digital output value VNT : Voltage at which the digital output transits from (N - 1)H to NH (Continued) DS07–12632–2E 55 MB95390H Series (Continued) Zero transition error 004H Actual conversion characteristic 003H 3FFH Actual conversion characteristic Full-scale transition error Ideal characteristic Digital output Digital output 3FEH 002H Ideal characteristic 001H VFST 3FDH (measurement value) Actual conversion characteristic Actual conversion characteristic VOT (measurement value) VSS Analog input VCC 3FCH VSS Analog input VCC Linearity error 3FFH 3FEH 3FDH Actual conversion characteristic Differential linearity error Ideal characteristic (N+1)H Actual conversion characteristic {1 LSB × N + VOT} Digital output VFST (measurement value) NH V(N+1)T Digital output VNT 004H 003H 002H 001H Actual conversion characteristic Ideal characteristic (N-1)H VNT Actual conversion characteristic (N-2)H VOT (measurement value) VSS Analog input VCC VSS Analog input VCC VNT - {1 LSB × N + VOT} Linearity error = of digital output N 1 LSB V(N+1)T - VNT Differential linear error = -1 of digital output N 1 LSB N : A/D converter digital output value VNT : Voltage at which the digital output transits from (N - 1)H to NH VOT (ideal value) = VSS + 0.5 LSB [V] VFST (ideal value) = VCC - 2 LSB [V] 56 DS07–12632–2E MB95390H Series 6. Flash Memory Write/Erase Characteristics Parameter Sector erase time (2 Kbyte sector) Sector erase time (16 Kbyte sector) Byte writing time Erase/write cycle Power supply voltage at erase/ write Flash memory data retention time Value Min — — — 100000 3.0 20*3 Typ 0.2*1 0.5*1 21 — — — Max 0.5*2 7.5*2 6100*2 — 5.5 — Unit s s µs cycle V year Average TA = +85°C Remarks The time of writing 00H prior to erasure is excluded. The time of writing 00H prior to erasure is excluded. System-level overhead is excluded. *1: TA = +25°C, VCC = 5.0 V, 100000 cycles *2: TA = +85°C, VCC = 3.0 V, 100000 cycles *3: This value is converted from the result of a technology reliability assessment. (The value is converted from the result of a high temperature accelerated test using the Arrhenius equation with the average temperature being +85°C). DS07–12632–2E 57 MB95390H Series ■ SAMPLE CHARACTERISTICS • Power supply current temperature characteristics ICC − VCC TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2) Main clock mode with the external clock operating 20 ICC − TA VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2) Main clock mode with the external clock operating 20 15 FMP = 16 MHz 15 FMP = 16 MHz ICC[mA] ICC[mA] 10 FMP = 10 MHz FMP = 8 MHz 10 FMP = 10 MHz 5 FMP = 4 MHz FMP = 2 MHz 0 2 3 4 VCC[V] 5 6 7 5 0 −50 0 +50 TA[°C] +100 +150 ICCS − VCC TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2) Main sleep mode with the external clock operating 8 7 6 5 ICCS − TA VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2) Main sleep mode with the external clock operating 8 7 6 5 ICCS[mA] FMP = 16 MHz FMP = 16 MHz ICCS[mA] FMP = 10 MHz 4 FMP = 8 MHz 3 2 1 0 2 3 4 VCC[V] 5 6 7 FMP = 4 MHz FMP = 2 MHz FMP = 10 MHz 4 3 2 1 0 −50 0 +50 TA[°C] +100 +150 ICCL − VCC TA = +25°C, FMPL = 16 kHz (divided by 2) Subclock mode with the external clock operating 100 ICCL − TA VCC = 5.5 V, FMPL = 16 kHz (divided by 2) Subclock mode with the external clock operating 100 75 75 ICCL[μA] 50 ICCL[μA] 50 25 25 0 2 3 4 VCC[V] 5 6 7 0 −50 0 +50 TA[°C] +100 +150 (Continued) 58 DS07–12632–2E MB95390H Series ICCLS − VCC TA = +25°C, FMPL = 16 kHz (divided by 2) Subsleep mode with the external clock operating 14 12 10 ICCLS[μA] ICCLS[μA] 8 6 4 2 0 2 3 4 VCC[V] 5 6 7 ICCLS − TA VCC = 5.5 V, FMPL = 16 kHz (divided by 2) Subsleep mode with the external clock operating 16 14 12 10 8 6 4 2 0 −50 0 +50 TA[°C] +100 +150 ICCT − VCC TA = +25°C, FMPL = 16 kHz (divided by 2) Watch mode with the external clock operating 50 ICCT − TA VCC = 5.5 V, FMPL = 16 kHz (divided by 2) Watch mode with the external clock operating 50 40 40 ICCT[μA] 20 ICCT[μA] 30 30 20 10 10 0 2 3 4 VCC[V] 5 6 7 0 −50 0 +50 TA[°C] +100 +150 ICTS − VCC TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2) Time-base timer mode with the external clock operating 1.5 ICTS − TA VCC = 5.5 V, FMPL = 10, 16 kHz (divided by 2) Time-base timer mode with the external clock operating 1.5 1.0 ICTS[mA] ICTS[mA] FMP = 16 MHz 1.0 FMP = 16 MHz FMP = 10 MHz 0.5 FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz 0.0 2 3 4 VCC[V] 5 6 7 0.5 FMP = 10 MHz 0.0 −50 0 +50 TA[°C] +100 +150 (Continued) DS07–12632–2E 59 MB95390H Series (Continued) ICCH − VCC TA = +25°C, FMPL = (stop) Substop mode with the external clock stopping 4.5 4.0 3.5 3.0 ICCH[μA] 2.5 2.0 1.5 1.0 0.5 0.0 2 3 4 VCC[V] 5 6 7 ICCH[μA] ICCH − TA VCC = 5.5 V, FMPL = (stop) Substop mode with the external clock stopping 9 8 7 6 5 4 3 2 1 0 −50 0 +50 TA[°C] +100 +150 ICCMCR − VCC TA = +25°C, FMP = 1, 8, 10, 12.5 MHz (no division) Main clock mode with the main CR clock operating 20 ICCMCR − TA VCC = 5.5 V, FMP = 1, 8, 10, 12.5 MHz (no division) Main clock mode with the main CR clock operating 20 15 15 ICCMCR[mA] FMP = 12.5 MHz 10 FMP = 10 MHz FMP = 8 MHz 5 ICCMCR[mA] FMP = 12.5 MHz 10 FMP = 10 MHz FMP = 8 MHz 5 FMP = 1 MHz 0 2 3 4 VCC[V] 5 6 7 0 −50 0 +50 TA[°C] FMP = 1 MHz +100 +150 ICCSCR − VCC TA = +25°C, FMPL = 50 kHz (divided by 2) Subclock mode with the sub-CR clock operating 140 120 100 ICCSCR[μA] 80 60 40 20 0 2 3 4 VCC[V] 5 6 7 ICCSCR − TA VCC = 5.5 V, FMPL = 50 kHz (divided by 2) Subclock mode with the sub-CR clock operating 140 120 100 ICCSCR[μA] 80 60 40 20 0 −50 0 +50 TA[°C] +100 +150 60 DS07–12632–2E MB95390H Series • Input voltage characteristics VIHI − VCC and VILI − VCC TA = +25°C 4 4 VIHS − VCC and VILS − VCC TA = +25°C 3 VIHI 2 VILI VIHS/VILS[V] VIHI/VILI[V] 3 VIHS 2 VILS 1 1 0 2 3 4 VCC[V] 5 6 0 2 3 4 VCC[V] 5 6 VIHM − VCC and VILM − VCC TA = +25°C 4 3 VIHM/VILM[V] VIHM 2 VILM 1 0 2 3 4 VCC[V] 5 6 DS07–12632–2E 61 MB95390H Series • Output voltage characteristics (VCC − VOH1) − IOH TA = +25°C 2.0 1.8 1.6 1.4 VCC − VOH1 [V] 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 −2 −4 IOH [mA] VCC = 2.4 V VCC = 2.7 V VCC = 3.5 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V −6 −8 −10 VCC − VOH2 [V] 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 −2 −4 IOH [mA] VCC = 2.4 V VCC = 2.7 V VCC = 3.5 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V −6 −8 −10 (VCC − VOH2) − IOH TA = +25°C VOL1 − IOL TA = +25°C 2.0 1.8 1.6 1.4 1.2 VOL1 [V] 1.0 0.8 0.6 0.4 0.2 0.0 0 2 4 IOL [mA] VCC = 2.4 V VCC = 2.7 V VCC = 3.5 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V 6 8 10 VOL2 [V] 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 2 VOL2 − IOL TA = +25°C 4 IOL [mA] 6 8 10 VCC = 2.4 V VCC = 2.7 V VCC = 3.5 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V 62 DS07–12632–2E MB95390H Series • Pull-up characteristics RPULL − VCC TA = +25°C 350 300 250 RPULL[kΩ] 200 150 100 50 0 1 2 3 4 VCC[V] 5 6 7 DS07–12632–2E 63 MB95390H Series ■ MASK OPTIONS Part Number Selectable/Fixed 1 2 Reset With dedicated reset input MB95F394H MB95F396H MB95F398H Fixed Without dedicated reset input MB95F394K MB95F396K MB95F398K No. Low-voltage detection reset Without low-voltage detection reset With low-voltage detection reset 64 DS07–12632–2E MB95390H Series ■ ORDERING INFORMATION Part Number MB95F394HPMC-G-SNE2 MB95F394KPMC-G-SNE2 MB95F396HPMC-G-SNE2 MB95F396KPMC-G-SNE2 MB95F398HPMC-G-SNE2 MB95F398KPMC-G-SNE2 MB95F394HPMC1-G-SNE2 MB95F394KPMC1-G-SNE2 MB95F396HPMC1-G-SNE2 MB95F396KPMC1-G-SNE2 MB95F398HPMC1-G-SNE2 MB95F398KPMC1-G-SNE2 MB95F394HWQN-G-SNE1 MB95F394HWQN-G-SNERE1 MB95F394KWQN-G-SNE1 MB95F394KWQN-G-SNERE1 MB95F396HWQN-G-SNE1 MB95F396HWQN-G-SNERE1 MB95F396KWQN-G-SNE1 MB95F396KWQN-G-SNERE1 MB95F398HWQN-G-SNE1 MB95F398HWQN-G-SNERE1 MB95F398KWQN-G-SNE1 MB95F398KWQN-G-SNERE1 Package 48-pin plastic LQFP (FPT-48P-M49) 52-pin plastic LQFP (FPT-52P-M02) 48-pin plastic QFN (LCC-48P-M11) DS07–12632–2E 65 MB95390H Series ■ PACKAGE DIMENSION 48-pin plastic LQFP Lead pitch Package width × package length Lead shape Lead bend direction Sealing method Mounting height Weight 0.50 mm 7.00 mm × 7.00 mm Gullwing Normal bend Plastic mold 1.70 mm MAX 0.17 g (FPT-48P-M49) 48-pin plastic LQFP (FPT-48P-M49) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 9.00±0.20(.354±.008)SQ *7.00±0.10(.276±.004)SQ 36 25 0.145±0.055 (.006±.002) 37 24 0.08(.003) INDEX Details of "A" part 1.50 –0.10 .059 –.004 +0.20 +.008 (Mounting height) 48 13 "A" 0°~8° 1 12 0.10±0.10 (.004±.004) (Stand off) 0.50(.020) 0.22±0.05 (.008±.002) 0.08(.003) M 0.25(.010) 0.60±0.15 (.024±.006) C 2010 FUJITSU SEMICONDUCTOR LIMITED HMbF48-49Sc-1-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 66 DS07–12632–2E MB95390H Series 52-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.65 mm 10.00 × 10.00 mm Gullwing Plastic mold 1.70 mm MAX 0.32 g P-LFQFP52-10× 10-0.65 (FPT-52P-M02) Code (Reference) 52-pin plastic LQFP (FPT-52P-M02) 12.00±0.20(.472±.008)SQ *10.00±0.10(.394±.004)SQ 39 27 Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 0.145±0.055 (.006±.002) 40 Details of "A" part 26 1.50 –0.10 .059 –.004 +0.20 +.008 (Mounting height) 0.25(.010) INDEX 0.10(.004) 52 14 0~8˚ "A" 0.50±0.20 (.020±.008) 1 13 0.10±0.10 (.004±.004) (Stand off) 0.65(.026) 0.30 –0.035 .012 +0.065 +.0026 –.0014 0.13(.005) M 0.60±0.15 (.024±.006) C 2010 FUJITSU SEMICONDUCTOR LIMITED F52002Sc-2-1 Dimensions in mm (inches). Note: The values in parentheses are reference values Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) DS07–12632–2E 67 MB95390H Series (Continued) 48-pin plastic QFN Lead pitch Package width × package length Sealing method Mounting height Weight 0.50 mm 7.00 mm × 7.00 mm Plastic mold 0.80 mm MAX 0.12 g (LCC-48P-M11) 48-pin plastic QFN (LCC-48P-M11) 7.00±0.10 (.276±.004) 4.40±0.15 (.173±.006) 7.00±0.10 (.276±.004) 4.40±0.15 (.173±.006) INDEX AREA 0.25 –0.07 +.002 (.010 –.003 ) +0.05 0.50(.020) (TYP) 0.50±0.05 (.020±.002) 1PIN CORNER (C0.30(C.012)) 0.75±0.05 (.030±.002) 0.02 (.001 +0.03 –0.02 +.001 –.001 (0.20(.008)) ) C 2009-2010 FUJITSU SEMICONDUCTOR LIMITED C48064S-c-1-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 68 DS07–12632–2E MB95390H Series ■ MAJOR CHANGES IN THIS EDITION Page 1 ■ FEATURES Section Details Changed the main CR clock oscillation accuracy. ±2% → ±2% or ±2.5% Added a remark about the main CR clock accuracy. 4 5 6 ■ PRODUCT LINE-UP ■ PACKAGES AND CORRESPONDING PRODUCTS ■ DIFFERENCES AMONG PRODUCTS AND NOTES ON PRODUCT SELECTION ■ PIN ASSIGNMENT ■ ELECTRICAL CHARACTERISTICS 4. AC Characteristics (1) Clock Timing Added FPT-52P-M02. Added FPT-52P-M02. Added a reference for the connection method in “• Onchip debug function”. Added the pin assignment diagram of FPT-52P-M02. Added the pin numbers of FPT-52P-M02. Changed the values of clock frequency (FCRH). Added conditions related to the LQFP package and the QFN package for the values of clock frequency (FCRH). Added footnotes *2 and *3. 58 to 63 ■ SAMPLE CHARACTERISTICS 65 67 ■ ORDERING INFORMATION ■ PACKAGE DIMENSION Added “■ SAMPLE CHARACTERISTICS”. Added the part numbers of FPT-52P-M02. Added the package diagram of FPT-52P-M02. 8 34 10 to 13 ■ PIN FUNCTIONS The vertical lines marked on the left side of the page indicate the changes. DS07–12632–2E 69 MB95390H Series MEMO 70 DS07–12632–2E MB95390H Series MEMO DS07–12632–2E 71 MB95390H Series FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fss/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fsp/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department