FUJITSU SEMICONDUCTOR DATA SHEET
DS702-00003-1v0-E
8-bit Microcontrollers
CMOS
New-8FX MB95560H/570H/580H Series
MB95F562H/F562K/F563H/F563K/F564H/F564K MB95F572H/F572K/F573H/F573K/F574H/F574K MB95F582H/F582K/F583H/F583K/F584H/F584K
■ DESCRIPTION
MB95560H/570H/580H is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers of these series contain a variety of peripheral resources.
■ FEATURES
• New-8FX CPU core Instruction set optimized for controllers • Multiplication and division instructions • 16-bit arithmetic operations • Bit test branch instructions • Bit manipulation instructions, etc. • Clock • Selectable main clock source Main oscillation clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz) External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz) Main CR clock (4 MHz ± 2%) The main CR clock frequency becomes 8 MHz when the PLL multiplier is 2. The main CR clock frequency becomes 10 MHz when the PLL multiplier is 2.5. The main CR clock frequency becomes 12 MHz when the PLL multiplier is 3. The main CR clock frequency becomes 16 MHz when the PLL multiplier is 4. • Selectable subclock source Sub-oscillation clock (32.768 kHz) External clock (32.768 kHz) Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz) • Timer • 8/16-bit composite timer × 2 channels • Time-base timer × 1 channel • Watch prescaler × 1 channel • LIN-UART (available only on MB95F562H/F562K/F563H/F563K/F564H/F564K/F582H/F582K/F583H/ F583K/F584H/F584K) • Full duplex double buffer • Capable of clock-synchronized serial data transfer and clock-asynchronized serial data transfer (Continued)
For the information for microcontroller supports, see the following website.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2010.12
MB95560H/570H/580H Series
(Continued) • External interrupt • Interrupt by edge detection (rising edge, falling edge, and both edges can be selected) • Can be used to wake up the device from different low power consumption (standby) modes • 8/10-bit A/D converter • 8-bit or 10-bit resolution can be selected. • Low power consumption (standby) modes • Stop mode • Sleep mode • Watch mode • Time-base timer mode • I/O port • MB95F562H/F563H/F564H (maximum no. of I/O ports: 16) General-purpose I/O ports (N-ch open drain) :1 General-purpose I/O ports (CMOS I/O) : 15 • MB95F562K/F563K/F564K (maximum no. of I/O ports: 17) General-purpose I/O ports (N-ch open drain) :2 General-purpose I/O ports (CMOS I/O) : 15 • MB95F572H/F573H/F574H (maximum no. of I/O ports: 4) General-purpose I/O ports (N-ch open drain) :1 General-purpose I/O ports (CMOS I/O) :3 • MB95F572K/F573K/F574K (maximum no. of I/O ports: 5) General-purpose I/O ports (N-ch open drain) :2 General-purpose I/O ports (CMOS I/O) :3 • MB95F582H/F583H/F584H (maximum no. of I/O ports: 12) General-purpose I/O ports (N-ch open drain) :1 General-purpose I/O ports (CMOS I/O) : 11 • MB95F582K/F583K/F584K (maximum no. of I/O ports: 13) General-purpose I/O ports (N-ch open drain) :2 General-purpose I/O ports (CMOS I/O) : 11 • On-chip debug • 1-wire serial control • Serial writing supported (asynchronous mode) • Hardware/software watchdog timer • Built-in hardware watchdog timer • Built-in software watchdog timer • Low-voltage detection reset circuit (available only on MB95F562K/F563K/F564K/F572K/F573K/F574K/ F582K/F583K/F584K) • Built-in low-voltage detector • Clock supervisor counter • Built-in clock supervisor counter function • Dual operation Flash memory • The erase/write operation and the read operation can be executed in different banks (upper bank/lower bank) simultaneously. • Flash memory security function • Protects the content of the Flash memory
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DS702-00003-1v0-E
MB95560H/570H/580H Series
■ PRODUCT LINE-UP
• MB95560H Series
Part number MB95F562H Parameter MB95F563H MB95F564H MB95F562K MB95F563K MB95F564K
Type Flash memory product Clock supervisor It supervises the main clock oscillation. counter Flash memory 8 Kbyte 12 Kbyte 20 Kbyte 8 Kbyte 12 Kbyte 20 Kbyte capacity RAM capacity 240 bytes 496 bytes 496 bytes 240 bytes 496 bytes 496 bytes Low-voltage No Yes detection reset Reset input Dedicated Selected through software • Number of basic instructions : 136 • Instruction bit length : 8 bits • Instruction length : 1 to 3 bytes CPU functions • Data bit length : 1, 8 and 16 bits • Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz) • Interrupt processing time : 0.6 µs (machine clock frequency = 16.25 MHz) • I/O ports (Max) : 17 • I/O ports (Max) : 16 General• CMOS I/O : 15 • CMOS I/O : 15 purpose I/O • N-ch open drain: 2 • N-ch open drain: 1 Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz) • Reset generation cycle Hardware/ software - Main oscillation clock at 10 MHz: 105 ms (Min) watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer. Wild register It can be used to replace 3 bytes of data. • A wide range of communication speed can be selected by a dedicated reload timer. • It has a full duplex double buffer. LIN-UART • Clock-synchronized serial data transfer and clock-asynchronized serial data transfer is enabled. • The LIN function can be used as a LIN master or a LIN slave. 6 channels 8/10-bit A/D converter 8-bit or 10-bit resolution can be selected. 2 channels • The timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel". 8/16-bit • It has built-in timer function, PWC function, PWM function and input capture function. composite timer • Count clock: it can be selected from internal clocks (seven types) and external clocks. • It can output square wave. 6 channels External • Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.) interrupt • It can be used to wake up the device from the standby mode. • 1-wire serial control On-chip debug • It supports serial writing (asynchronous mode). (Continued)
DS702-00003-1v0-E
3
MB95560H/570H/580H Series
(Continued)
Part number MB95F562H Parameter MB95F563H MB95F564H MB95F562K MB95F563K MB95F564K
Watch prescaler Eight different time intervals can be selected. • It supports automatic programming (Embedded Algorithm) and write/erase/erase-suspend/ erase-resume commands. • It has a flag indicating the completion of the operation of Embedded Algorithm. Flash memory • Flash security feature for protecting the content of the Flash memory Number of program/erase cycles Data retention time 1000 20 years 10000 10 years 100000 5 years
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode LCC-32P-M19 Package FPT-20P-M09 FPT-20P-M10
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MB95560H/570H/580H Series
• MB95570H Series
Part number MB95F572H Parameter MB95F573H MB95F574H MB95F572K MB95F573K MB95F574K
Type Flash memory product Clock supervisor It supervises the main clock oscillation. counter Flash memory 8 Kbyte 12 Kbyte 20 Kbyte 8 Kbyte 12 Kbyte 20 Kbyte capacity RAM capacity 240 bytes 496 bytes 496 bytes 240 bytes 496 bytes 496 bytes Low-voltage No Yes detection reset Reset input Dedicated Selected through software • Number of basic instructions : 136 • Instruction bit length : 8 bits • Instruction length : 1 to 3 bytes CPU functions • Data bit length : 1, 8 and 16 bits • Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz) • Interrupt processing time : 0.6 µs (machine clock frequency = 16.25 MHz) • I/O ports (Max) : 5 • I/O ports (Max) : 4 General• CMOS I/O :3 • CMOS I/O :3 purpose I/O • N-ch open drain: 2 • N-ch open drain: 1 Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz) • Reset generation cycle Hardware/ - Main oscillation clock at 10 MHz: 105 ms (Min) software watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer. Wild register It can be used to replace 3 bytes of data. LIN-UART No LIN-UART 2 channels 8/10-bit A/D converter 8-bit or 10-bit resolution can be selected. 1 channel • The timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel". 8/16-bit • It has built-in timer function, PWC function, PWM function and input capture function. composite timer • Count clock: it can be selected from internal clocks (seven types) and external clocks. • It can output square wave. 2 channels External • Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.) interrupt • It can be used to wake up the device from standby modes. • 1-wire serial control On-chip debug • It supports serial writing (asynchronous mode). Watch prescaler Eight different time intervals can be selected. • It supports automatic programming (Embedded Algorithm) and write/erase/erase-suspend/ erase-resume commands. • It has a flag indicating the completion of the operation of Embedded Algorithm. Flash memory • Flash security feature for protecting the content of the Flash memory Number of program/erase cycles Data retention time 1000 20 years 10000 10 years 100000 5 years
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode Package FPT-8P-M08
DS702-00003-1v0-E
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MB95560H/570H/580H Series
• MB95580H Series
Part number MB95F582H Parameter MB95F583H MB95F584H MB95F582K MB95F583K MB95F584K
Type Flash memory product Clock supervisor It supervises the main clock oscillation. counter Flash memory 8 Kbyte 12 Kbyte 20 Kbyte 8 Kbyte 12 Kbyte 20 Kbyte capacity RAM capacity 240 bytes 496 bytes 496 bytes 240 bytes 496 bytes 496 bytes Low-voltage No Yes detection reset Reset input Dedicated Selected through software • Number of basic instructions : 136 • Instruction bit length : 8 bits • Instruction length : 1 to 3 bytes CPU functions • Data bit length : 1, 8 and 16 bits • Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz) • Interrupt processing time : 0.6 µs (machine clock frequency = 16.25 MHz) • I/O ports (Max) : 13 • I/O ports (Max) : 12 General• CMOS I/O : 11 • CMOS I/O : 11 purpose I/O • N-ch open drain: 2 • N-ch open drain: 1 Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz) • Reset generation cycle Hardware/ - Main oscillation clock at 10 MHz: 105 ms (Min) software watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer. Wild register It can be used to replace 3 bytes of data. • A wide range of communication speed can be selected by a dedicated reload timer. • It has a full duplex double buffer. LIN-UART • Clock-synchronized serial data transfer and clock-asynchronized serial data transfer is enabled. • The LIN function can be used as a LIN master or a LIN slave. 5 channels 8/10-bit A/D converter 8-bit or 10-bit resolution can be selected. 1 channel • The timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel". 8/16-bit • It has built-in timer function, PWC function, PWM function and input capture function. composite timer • Count clock: it can be selected from internal clocks (seven types) and external clocks. • It can output square wave. 6 channels External • Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.) interrupt • It can be used to wake up the device from standby modes. • 1-wire serial control On-chip debug • It supports serial writing (asynchronous mode). (Continued)
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DS702-00003-1v0-E
MB95560H/570H/580H Series
(Continued)
Part number MB95F582H Parameter MB95F583H MB95F584H MB95F582K MB95F583K MB95F584K
Watch prescaler Eight different time intervals can be selected. • It supports automatic programming (Embedded Algorithm) and write/erase/erase-suspend/ erase-resume commands. • It has a flag indicating the completion of the operation of Embedded Algorithm. Flash memory • Flash security feature for protecting the content of the Flash memory Number of program/erase cycles Data retention time 1000 20 years 10000 10 years 100000 5 years
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode LCC-32P-M19 Package FPT-16P-M08 FPT-16P-M23
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MB95560H/570H/580H Series
■ PACKAGES AND CORRESPONDING PRODUCTS
• MB95560H Series
Part number MB95F562H Package LCC-32P-M19 FPT-20P-M09 FPT-20P-M10 FPT-16P-M08 FPT-16P-M23 FPT-8P-M08 O O O X X X O O O X X X O O O X X X O O O X X X O O O X X X O O O X X X MB95F562K MB95F563H MB95F563K MB95F564H MB95F564K
• MB95570H Series
Part number MB95F572H Package LCC-32P-M19 FPT-20P-M09 FPT-20P-M10 FPT-16P-M08 FPT-16P-M23 FPT-8P-M08 X X X X X O X X X X X O X X X X X O X X X X X O X X X X X O X X X X X O MB95F572K MB95F573H MB95F573K MB95F574H MB95F574K
• MB95580H Series
Part number MB95F582H Package LCC-32P-M19 FPT-20P-M09 FPT-20P-M10 FPT-16P-M08 FPT-16P-M23 FPT-8P-M08 O X X O O X O X X O O X O X X O O X O X X O O X O X X O O X O X X O O X MB95F582K MB95F583H MB95F583K MB95F584H MB95F584K
O: Available X: Unavailable
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DS702-00003-1v0-E
MB95560H/570H/580H Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON PRODUCT SELECTION
• Current consumption When using the on-chip debug function, take account of the current consumption of flash erase/write. For details of current consumption, see “■ ELECTRICAL CHARACTERISTICS”. • Package For details of information on each package, see “■ PACKAGES AND CORRESPONDING PRODUCTS” and “■ PACKAGE DIMENSION”. • Operating voltage The operating voltage varies, depending on whether the on-chip debug function is used or not. For details of the operating voltage, see “■ ELECTRICAL CHARACTERISTICS”. • On-chip debug function The on-chip debug function requires that VCC, VSS and 1 serial-wire be connected to an evaluation tool. For details of the connection method, refer to “CHAPTER 21 EXAMPLE OF SERIAL PROGRAMMING CONNECTION” in the hardware manual of the MB95560H/570H/580H Series.
DS702-00003-1v0-E
9
MB95560H/570H/580H Series
■ PIN ASSIGNMENT
NC NC NC NC NC NC NC NC X1/PF1 X0/PF0 VSS X1A/PG2 X0A/PG1 Vcc C RST/PF2 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18
* The number of usable pins is 20.
1 2 3 4 5 6 7 8
(TOP VIEW)
P07/INT07 P12/EC0/DBG P06/INT06/TO01 P05/INT05/AN05/TO00 P04/INT04/AN04/SIN/EC0 P03/INT03/AN03/SOT P02/INT02/AN02/SCK P01/AN01
LCC-32P-M19 (MB95560H Series)
17
9 10 11 12 13
14 15 NC P00/AN00
X0/PF0 X1/PF1 Vss X1A/PG2 X0A/PG1 Vcc C RST/PF2 TO10/P62 TO11/P63
1 2 3 4 5 6 7 8 9 10
TO11/P63 TO10/P62 NC NC NC
P64/EC1 20 19 18 17
16
(TOP VIEW)
P12/EC0/DBG P07/INT07 P06/INT06/TO01 P05/INT05/AN05/TO00 P04/INT04/AN04/SIN/EC0 P03/INT03/AN03/SOT P02/INT02/AN02/SCK P01/AN01 P00/AN00 P64/EC1
FPT-20P-M09 FPT-20P-M10 (MB95560H Series)
16 15 14 13 12 11
(Continued)
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MB95560H/570H/580H Series
(Continued)
NC NC NC NC NC NC NC 32 31 30 29 28 27 26 X1/PF1 X0/PF0 VSS X1A/PG2 X0A/PG1 Vcc C RST/PF2 NC 25 24 23 22
1 2 3 4 6 7 8
(TOP VIEW)
P07/INT07 P12/EC0/DBG P06/INT06/TO01 P05/INT05/AN05/TO00 P04/INT04/AN04/SIN/EC0 P03/INT03/AN03/SOT P02/INT02/AN02/SCK P01/AN01
21 LCC-32P-M19 5 (MB95580H Series) 20 19
* The number of usable pins is 16.
18 17
9 10 11 12 13 NC NC NC NC NC X0/PF0 X1/PF1 Vss X1A/PG2 X0A/PG1 Vcc RST/PF2 C 1 2 3 4 5 6 7 8
14 NC
NC NC 16 15 14
15 16
(TOP VIEW)
P12/EC0/DBG P07/INT07 P06/INT06/TO01 P05/INT05/AN05/TO00 P04/INT04/AN04/SIN/EC0 P03/INT03/AN03/SOT P01/AN01 P02/INT02/AN02/SCK
FPT-16P-M08 FPT-16P-M23 (MB95580H Series)
13 12 11 10 9
Vss Vcc C RST/PF2
1 2 3 4
(TOP VIEW) FPT-8P-M08 (MB95570H Series)
8 7 6 5
P12/EC0/DBG P06/INT06/TO01 P05/AN05/TO00 P04/INT04/AN04/EC0
DS702-00003-1v0-E
11
MB95560H/570H/580H Series
■ PIN FUNCTIONS (MB95560H Series, 32 pins)
Pin no. Pin name PF1 X1 PF0 X0 VSS PG2 X1A PG1 X0A VCC C PF2 8 RST P63 TO11 10 11 12 13 14 15 P62 TO10 NC NC NC NC P00 AN00 16 P64 EC1 17 P01 AN01 P02 18 INT02 AN02 SCK D D E ⎯ ⎯ ⎯ ⎯ D E A I/O circuit type* B B ⎯ C C ⎯ ⎯ General-purpose I/O port Main clock I/O oscillation pin General-purpose I/O port Main clock input oscillation pin Power supply pin (GND) General-purpose I/O port Subclock I/O oscillation pin General-purpose I/O port Subclock input oscillation pin Power supply pin Capacitor connection pin General-purpose I/O port Reset pin Dedicated reset pin in MB95F562H/F563H/F564H General-purpose I/O port High-current pin 8/16-bit composite timer ch. 1 output pin General-purpose I/O port High-current pin 8/16-bit composite timer ch. 1 output pin It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. General-purpose I/O port High-current pin A/D converter analog input pin General-purpose I/O port High-current pin 8/16-bit composite timer ch. 1 clock input pin General-purpose I/O port High-current pin A/D converter analog input pin General-purpose I/O port High-current pin External interrupt input pin A/D converter analog input pin LIN-UART clock I/O pin (Continued) Function
1 2 3 4 5 6 7
9
E
12
DS702-00003-1v0-E
MB95560H/570H/580H Series
(Continued) Pin no. Pin name P03 19 INT03 AN03 SOT P04 INT04 20 AN04 SIN EC0 P05 21 INT05 AN05 TO00 P06 22 INT06 TO01 P12 23 EC0 DBG 24 25 26 27 28 29 30 31 32 P07 INT07 NC NC NC NC NC NC NC NC ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ E F E D D D I/O circuit type* General-purpose I/O port High-current pin External interrupt input pin A/D converter analog input pin LIN-UART data output pin General-purpose I/O port External interrupt input pin A/D converter analog input pin LIN-UART data input pin 8/16-bit composite timer ch. 0 clock input pin General-purpose I/O port High-current pin External interrupt input pin A/D converter analog input pin 8/16-bit composite timer ch. 0 output pin General-purpose I/O port High-current pin External interrupt input pin 8/16-bit composite timer ch. 0 output pin General-purpose I/O port 8/16-bit composite timer ch. 0 clock input pin DBG input pin General-purpose I/O port High-current pin External interrupt input pin It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. Function
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
DS702-00003-1v0-E
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MB95560H/570H/580H Series
■ PIN FUNCTIONS (MB95560H Series, 20 pins)
Pin no. Pin name PF0 X0 PF1 X1 VSS PG2 X1A PG1 X0A VCC C PF2 8 RST P62 TO10 10 P63 TO11 11 P64 EC1 12 P00 AN00 13 P01 AN01 P02 14 INT02 AN02 SCK P03 15 INT03 AN03 SOT D D D D E E A I/O circuit type* B B — C C — — General-purpose I/O port Main clock input oscillation pin General-purpose I/O port Main clock I/O oscillation pin Power supply pin (GND) General-purpose I/O port Subclock I/O oscillation pin General-purpose I/O port Subclock input oscillation pin Power supply pin Capacitor connection pin General-purpose I/O port Reset pin Dedicated reset pin in MB95F562H/F563H/F564H General-purpose I/O port High-current pin 8/16-bit composite timer ch. 1 output pin General-purpose I/O port High-current pin 8/16-bit composite timer ch. 1 output pin General-purpose I/O port High-current pin 8/16-bit composite timer ch. 1 clock input pin General-purpose I/O port High-current pin A/D converter analog input pin General-purpose I/O port High-current pin A/D converter analog input pin General-purpose I/O port High-current pin External interrupt input pin A/D converter analog input pin LIN-UART clock I/O pin General-purpose I/O port High-current pin External interrupt input pin A/D converter analog input pin LIN-UART data output pin (Continued) Function
1 2 3 4 5 6 7
9
E
14
DS702-00003-1v0-E
MB95560H/570H/580H Series
(Continued) Pin no. Pin name P04 INT04 16 AN04 SIN EC0 P05 17 INT05 AN05 TO00 P06 18 INT06 TO01 19 P07 INT07 P12 20 EC0 DBG F E E D D I/O circuit type* General-purpose I/O port External interrupt input pin A/D converter analog input pin LIN-UART data input pin 8/16-bit composite timer ch. 0 clock input pin General-purpose I/O port High-current pin External interrupt input pin A/D converter analog input pin 8/16-bit composite timer ch. 0 output pin General-purpose I/O port High-current pin External interrupt input pin 8/16-bit composite timer ch. 0 output pin General-purpose I/O port High-current pin External interrupt input pin General-purpose I/O port 8/16-bit composite timer ch. 0 clock input pin DBG input pin Function
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
DS702-00003-1v0-E
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MB95560H/570H/580H Series
■ PIN FUNCTIONS (MB95570H Series, 8 pins)
s
Pin no. 1 2 3 4
Pin name VSS VCC C PF2 RST P04
I/O circuit type* — — — A Power supply pin (GND) Power supply pin Capacitor connection pin General-purpose I/O port
Function
Reset pin Dedicated reset pin in MB95F572H/F573H/F574H General-purpose I/O port External interrupt input pin A/D converter analog input pin 8/16-bit composite timer ch. 0 clock input pin General-purpose I/O port High-current pin
5
INT04 AN04 EC0 P05
D
6
AN05 TO00 P06
D
A/D converter analog input pin 8/16-bit composite timer ch. 0 output pin General-purpose I/O port High-current pin
7
INT06 TO01 P12
E
External interrupt input pin 8/16-bit composite timer ch. 0 output pin General-purpose I/O port
8
EC0 DBG
F
8/16-bit composite timer ch. 0 clock input pin DBG input pin
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
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DS702-00003-1v0-E
MB95560H/570H/580H Series
■ PIN FUNCTIONS (MB95580H Series, 32 pins)
Pin no. Pin name PF1 X1 PF0 X0 VSS PG2 X1A PG1 X0A VCC C PF2 8 9 10 11 12 13 14 15 16 17 RST NC NC NC NC NC NC NC NC P01 AN01 P02 18 INT02 AN02 SCK P03 19 INT03 AN03 SOT D D A ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ D I/O circuit type* B B ⎯ C C ⎯ ⎯ General-purpose I/O port Main clock I/O oscillation pin General-purpose I/O port Main clock input oscillation pin Power supply pin (GND) General-purpose I/O port Subclock I/O oscillation pin General-purpose I/O port Subclock input oscillation pin Power supply pin Capacitor connection pin General-purpose I/O port Reset pin Dedicated reset pin in MB95F582H/F583H/F584H It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. General-purpose I/O port High-current pin A/D converter analog input pin General-purpose I/O port High-current pin External interrupt input pin A/D converter analog input pin LIN-UART clock I/O pin General-purpose I/O port High-current pin External interrupt input pin A/D converter analog input pin LIN-UART data output pin (Continued) Function
1 2 3 4 5 6 7
DS702-00003-1v0-E
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MB95560H/570H/580H Series
(Continued) Pin no. Pin name P04 INT04 20 AN04 SIN EC0 P05 21 INT05 AN05 TO00 P06 22 INT06 TO01 P12 23 EC0 DBG 24 25 26 27 28 29 30 31 32 P07 INT07 NC NC NC NC NC NC NC NC ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ E F E D D I/O circuit type* General-purpose I/O port External interrupt input pin A/D converter analog input pin LIN-UART data input pin 8/16-bit composite timer ch. 0 clock input pin General-purpose I/O port High-current pin External interrupt input pin A/D converter analog input pin 8/16-bit composite timer ch. 0 output pin General-purpose I/O port High-current pin External interrupt input pin 8/16-bit composite timer ch. 0 output pin General-purpose I/O port 8/16-bit composite timer ch. 0 clock input pin DBG input pin General-purpose I/O port High-current pin External interrupt input pin It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. It is an internally connected pin. Always leave it unconnected. Function
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
18
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ PIN FUNCTIONS (MB95580H Series, 16 pins)
Pin no. Pin name PF0 X0 PF1 X1 VSS PG2 X1A PG1 X0A VCC PF2 7 8 RST C P02 9 INT02 AN02 SCK 10 P01 AN01 P03 11 INT03 AN03 SOT P04 INT04 12 AN04 SIN EC0 D D D D A — I/O circuit type* B B — C C — General-purpose I/O port Main clock input oscillation pin General-purpose I/O port Main clock I/O oscillation pin Power supply pin (GND) General-purpose I/O port Subclock I/O oscillation pin General-purpose I/O port Subclock input oscillation pin Power supply pin General-purpose I/O port Reset pin Dedicated reset pin in MB95F582H/F583H/F584H Capacitor connection pin General-purpose I/O port High-current pin External interrupt input pin A/D converter analog input pin LIN-UART clock I/O pin General-purpose I/O port High-current pin A/D converter analog input pin General-purpose I/O port High-current pin External interrupt input pin A/D converter analog input pin LIN-UART data output pin General-purpose I/O port External interrupt input pin A/D converter analog input pin LIN-UART data input pin 8/16-bit composite timer ch. 0 clock input pin (Continued) Function
1 2 3 4 5 6
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19
MB95560H/570H/580H Series
(Continued) Pin no. Pin name P05 13 INT05 AN05 TO00 P06 14 INT06 TO01 15 P07 INT07 P12 16 EC0 DBG F E E D I/O circuit type* General-purpose I/O port High-current pin External interrupt input pin A/D converter analog input pin 8/16-bit composite timer ch. 0 clock input pin General-purpose I/O port High-current pin External interrupt input pin 8/16-bit composite timer ch. 0 clock input pin General-purpose I/O port High-current pin External interrupt input pin General-purpose I/O port 8/16-bit composite timer ch. 0 clock input pin DBG input pin Function
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
20
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ I/O CIRCUIT TYPE
Type A Circuit
Reset input / Hysteresis input Reset output / Digital output N-ch
Remarks • N-ch open drain output • Hysteresis input • Reset output • Oscillation circuit • High-speed side Feedback resistance: approx. 1 MΩ • CMOS output • Hysteresis input
B
P-ch
Port select Digital output
N-ch
Digital output Standby control Hysteresis input Clock input
X1
X0 Standby control / Port select
P-ch
Port select Digital output
N-ch
Digital output Standby control Hysteresis input
C
R P-ch P-ch N-ch
Port select Pull-up control Digital output Digital output Standby control Hysteresis input Clock input X1A
• Oscillation circuit • Low-speed side Feedback resistance: approx.10 MΩ • CMOS output • Hysteresis input • Pull-up control available
X0A Standby control / Port select Port select
R
Pull-up control Digital output Digital output
N-ch
P-ch
Digital output Standby control Hysteresis input
(Continued)
DS702-00003-1v0-E
21
MB95560H/570H/580H Series
(Continued) Type D
R P-ch P-ch N-ch Analog input A/D control Standby control Hysteresis input Digital output Digital output Pull-up control
Circuit • • • •
Remarks CMOS output Hysteresis input Pull-up control available Analog input
E
R P-ch P-ch N-ch Standby control Hysteresis input Digital output Digital output Pull-up control
• CMOS output • Hysteresis input • Pull-up control available
F
Standby control Hysteresis input Digital output N-ch
• N-ch open drain output • Hysteresis input
22
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ NOTES ON DEVICE HANDLING
• Preventing latch-ups When using the device, ensure that the voltage applied does not exceed the maximum voltage rating. In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned in "1. Absolute Maximum Ratings" of "■ ELECTRICAL CHARACTERISTICS" is applied to the VCC pin or the VSS pin, a latch-up may occur. When a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed. • Stabilizing supply voltage Supply voltage must be stabilized. A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply. • Notes on using the external clock When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from subclock mode or stop mode.
■ PIN CONNECTION
• Treatment of unused pins If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions or latch-ups. Always pull up or pull down an unused input pin through a resistor of at least 2 kΩ. Set an unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it the same as an unused input pin. If there is an unused output pin, leave it unconnected. • Power supply pins To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase in the ground level, and conform to the total output current standard, always connect the VCC pin and the VSS pin to the power supply and ground outside the device. In addition, connect the current supply source to the VCC pin and the VSS pin with low impedance. It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between the VCC pin and the VSS pin at a location close to this device. • DBG pin Connect the DBG pin directly to an external pull-up resistor. To prevent the device from unintentionally entering the debug mode due to noise, minimize the distance between the DBG pin and the VCC or VSS pin when designing the layout of the printed circuit board. The DBG pin should not stay at “L” level after power-on until the reset output is released. • RST pin Connect the RST pin directly to an external pull-up resistor. To prevent the device from unintentionally entering the reset mode due to noise, minimize the distance between the RST pin and the VCC or VSS pin when designing the layout of the printed circuit board. The RST/PF2 pin functions as the reset input/output pin after power-on. In addition, the reset output of the RST/PF2 pin can be enabled by the RSTOE bit in the SYSC register, and the reset input function and the general purpose I/O function can be selected by the RSTEN bit in the SYSC register.
DS702-00003-1v0-E
23
MB95560H/570H/580H Series
• C pin Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for the VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see the diagram below. To prevent the device from unintentionally entering a mode to which the device is not set to transit due to noise, minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed circuit board. • DBG/RST/C pins connection diagram
DBG C RST Cs
24
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ BLOCK DIAGRAM (MB95560H Series)
New-8FX CPU
PF2*1/RST*2 PF1/X1*2 PF0/X0*2 PG2/X1A*2 PG1/X0A*2
Reset with LVD
Dual operation Flash with security function (8/12/20 Kbyte) RAM (240/496 bytes) Interrupt controller
Oscillator circuit
CR oscillator
Clock control
(P05*3/TO00)
Internal bus
8/16-bit composite timer ch. 0
(P06*3/TO01) P12*1/EC0, (P04/EC0)
(P12*1/DBG)
On-chip debug Wild register
8/10-bit A/D converter
(P00*3/AN00 to P05*3/AN05)
P02*3/INT02 to P07*3/INT07 (P02*3/SCK) (P03*3/SOT) (P04/SIN) C
External interrupt (P62*3/TO10) 8/16-bit composite timer ch. 1 LIN-UART (P63*3/TO11) P64*3/EC1
Port Vcc Vss *1: PF2 and P12 are N-ch open drain pins. *2: Software option
Port
*3: P00 to P03, P05 to P07 and P62 to P64 are high-current pins. Note: Pins in parentheses indicate that functions of those pins are shared among different resources.
DS702-00003-1v0-E
25
MB95560H/570H/580H Series
■ BLOCK DIAGRAM (MB95570H Series)
New-8FX CPU
PF2*1/RST*2
Reset with LVD
Dual operation Flash with security function (8/12/20 Kbyte) RAM (240/496 bytes) Interrupt controller
CR oscillator
Clock control (P12*1/DBG) On-chip debug Wild register
Internal bus
(P05*3/TO00) 8/16-bit composite timer ch. 0 (P06*3/TO01) P12*1/EC0, (P04/EC0)
8/10-bit A/D converter P04/INT04, P06*3/INT06 C Port Vcc Vss *1: PF2 and P12 are N-ch open drain pins. *2: Software option *3: P05 and P06 are high-current pins. Note: Pins in parentheses indicate that functions of those pins are shared among different resources. Port External interrupt
P05*3/AN05, (P04/AN04)
26
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ BLOCK DIAGRAM (MB95580H Series)
New-8FX CPU
PF2*1/RST*2 PF1/X1*2 PF0/X0*2 PG2/X1A*2 PG1/X0A*2
Reset with LVD
Dual operation Flash with security function (8/12/20 Kbyte) RAM (240/496 bytes) Interrupt controller
Oscillator circuit
CR oscillator
Clock control
(P05*3/TO00)
Internal bus
8/16-bit composite timer ch. 0
(P06*3/TO01) P12*1/EC0, (P04/EC0)
(P12*1/DBG)
On-chip debug Wild register
8/10-bit A/D converter
(P01*3/AN01 to P05*3/AN05)
P02*3/INT02 to P07*3/INT07 (P02*3/SCK) (P03*3/SOT) (P04/SIN) C
External interrupt
LIN-UART
Port Vcc Vss *1: PF2 and P12 are N-ch open drain pins. *2: Software option *3: P01 to P03 and P05 to P07 are high-current pins.
Port
Note: Pins in parentheses indicate that functions of those pins are shared among different resources.
DS702-00003-1v0-E
27
MB95560H/570H/580H Series
■ CPU CORE
• Memory Space The memory space of the MB95560H/570H/580H Series is 64 Kbyte in size, and consists of an I/O area, a data area, and a program area. The memory space includes areas intended for specific purposes such as general-purpose registers and a vector table. The memory maps of the MB95560H/570H/580H Series are shown below. • Memory Maps
MB95F562H/F562K/F572H/ F572K/F582H/F582K
0000H I/O 0080H 0090H 0100H 0180H Access prohibited RAM 240 bytes Register Access prohibited 0F80H Extension I/O 1000H Access prohibited B000H C000H Flash 4 Kbyte B000H C000H 1000H Access prohibited Flash 4 Kbyte Access prohibited E000H Flash 8 Kbyte FFFFH FFFFH B000H 0080H 0090H 0100H 0200H 0280H 0F80H
MB95F563H/F563K/F573H/ F573K/F583H/F583K
0000H I/O Access prohibited RAM 496 bytes Register
MB95F564H/F564K/F574H/ F574K/F584H/F584K
0000H I/O 0080H 0090H 0100H 0200H 0280H 0F80H 1000H Access prohibited Access prohibited RAM 496 bytes Register
Access prohibited Extension I/O
Access prohibited Extension I/O
Access prohibited F000H FFFFH
Flash 20 Kbyte
Flash 4 Kbyte
28
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ I/O MAP (MB95560H Series)
Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH to 0015H 0016H 0017H 0018H to 0027H 0028H 0029H 002AH 002BH 002CH 002DH to 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH to 0048H Register abbreviation PDR0 DDR0 PDR1 DDR1 — WATR PLLC SYCC STBC RSRR TBTC WPCR WDTC SYCC2 STBC2 — PDR6 DDR6 — PDRF DDRF PDRG DDRG PUL0 — PUL6 — PULG T01CR1 T00CR1 T11CR1 T10CR1 — Port G pull-up register 8/16-bit composite timer 01 status control register 1 8/16-bit composite timer 00 status control register 1 8/16-bit composite timer 11 status control register 1 8/16-bit composite timer 10 status control register 1 (Disabled) Port 6 pull-up register (Disabled) Port F data register Port F direction register Port G data register Port G direction register Port 0 pull-up register (Disabled) Port 6 data register Port 6 direction register (Disabled) PLL control register System clock control register Standby control register Reset source register Time-base timer control register Watch prescaler control register Watchdog timer control register System clock control register 2 Standby control register 2 (Disabled) Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register (Disabled) Oscillation stabilization wait time setting register Register name R/W Initial value R/W R/W R/W R/W — R/W R/W R/W R/W R/W R/W R/W R/W — R/W R/W — R/W R/W R/W R/W R/W — R/W — R/W R/W R/W R/W R/W — 00000000B 00000000B 00000000B 00000000B — 11111111B 00000000B XXX11011B 00000000B 00000000B 00000000B 00XX0000B 00000000B — 00000000B 00000000B — 00000000B 00000000B 00000000B 00000000B 00000000B — 00000000B — 00000000B 00000000B 00000000B 00000000B 00000000B — (Continued)
R/W XXXXXXXXB
R/W XXXX0011B
DS702-00003-1v0-E
29
MB95560H/570H/580H Series
Register abbreviation EIC10 EIC20 EIC30 — LVDR — SCR SMR SSR RDR/TDR ESCR ECCR — ADC1 ADC2 ADDH ADDL — FSR2 FSR SWRE0 FSR3 FSR4 WREN WROR — ILR0 ILR1 ILR2 ILR3 ILR4 ILR5 — WRARH0 WRARL0 WRDR0
Address 0049H 004AH 004BH 004CH, 004DH 004EH 004FH 0050H 0051H 0052H 0053H 0054H 0055H 0056H to 006BH 006CH 006DH 006EH 006FH 0070H 0071H 0072H 0073H 0074H 0075H 0076H 0077H 0078H 0079H 007AH 007BH 007CH 007DH 007EH 007FH 0F80H 0F81H 0F82H
Register name External interrupt circuit control register ch. 2/ch. 3 External interrupt circuit control register ch. 4/ch. 5 External interrupt circuit control register ch. 6/ch. 7 (Disabled) LVDR reset voltage selection ID register (Disabled) LIN-UART serial control register LIN-UART serial mode register LIN-UART serial status register LIN-UART receive/transmit data register LIN-UART extended status control register LIN-UART extended communication control register (Disabled) 8/10-bit A/D converter control register 1 8/10-bit A/D converter control register 2 8/10-bit A/D converter data register upper 8/10-bit A/D converter data register lower (Disabled) Flash memory status register 2 Flash memory status register Flash memory sector write control register 0 Flash memory status register 3 Flash memory status register 4 Wild register address compare enable register Wild register data test setting register Mirror of register bank pointer (RP) and direct bank pointer (DP) Interrupt level setting register 0 Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt level setting register 4 Interrupt level setting register 5 (Disabled) Wild register address setting register (upper) ch. 0 Wild register address setting register (lower) ch. 0 Wild register data setting register ch. 0
R/W Initial value R/W R/W R/W — R/W — R/W R/W R/W R/W R/W R/W — R/W R/W R/W R/W — R/W R/W R/W R R/W R/W R/W — R/W R/W R/W R/W R/W R/W — R/W R/W R/W 00000000B 00000000B 00000000B — 00000000B — 00000000B 00000000B 00001000B 00000000B 00000100B 000000XXB — 00000000B 00000000B 00000000B 00000000B — 00000000B 000X0000B 00000000B 000XXXXXB 00000000B 00000000B 00000000B — 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B — 00000000B 00000000B 00000000B (Continued)
30
DS702-00003-1v0-E
MB95560H/570H/580H Series
Register abbreviation WRARH1 WRARL1 WRDR1 WRARH2 WRARL2 WRDR2 — T01CR0 T00CR0 T01DR T00DR TMCR0 T11CR0 T10CR0 T11DR T10DR TMCR1 — BGR1 BGR0 — AIDRL — CRTH CRTL — CRTDA SYSC CMCR CMDR
Address 0F83H 0F84H 0F85H 0F86H 0F87H 0F88H 0F89H to 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H 0F98H 0F99H 0F9AH 0F9BH 0F9CH to 0FBBH 0FBCH 0FBDH 0FBEH to 0FC2H 0FC3H 0FC4H to 0FE3H 0FE4H 0FE5H 0FE6H 0FE7H 0FE8H 0FE9H 0FEAH
Register name Wild register address setting register (upper) ch. 1 Wild register address setting register (lower) ch. 1 Wild register data setting register ch. 1 Wild register address setting register (upper) ch. 2 Wild register address setting register (lower) ch. 2 Wild register data setting register ch. 2 (Disabled) 8/16-bit composite timer 01 status control register 0 8/16-bit composite timer 00 status control register 0 8/16-bit composite timer 01 data register 8/16-bit composite timer 00 data register 8/16-bit composite timer 00/01 timer mode control register 8/16-bit composite timer 11 status control register 0 8/16-bit composite timer 10 status control register 0 8/16-bit composite timer 11 data register 8/16-bit composite timer 10 data register 8/16-bit composite timer 10/11 timer mode control register (Disabled) LIN-UART baud rate generator register 1 LIN-UART baud rate generator register 0 (Disabled) A/D input disable register (Lower) (Disabled) Main CR clock trimming register (upper) Main CR clock trimming register (lower) (Disabled) Main CR clock temperature dependent adjustment register System configuration register Clock monitoring control register Clock monitoring data register
R/W Initial value R/W R/W R/W R/W R/W R/W — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W — R/W R/W — R/W — 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B — 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B — 00000000B 00000000B — 00000000B —
R/W 000XXXXXB R/W 000XXXXXB — R/W R/W R/W R/W — 00011111B 11000011B 00000000B 00000000B (Continued)
DS702-00003-1v0-E
31
MB95560H/570H/580H Series
(Continued) Address 0FEBH 0FECH 0FEDH to 0FFFH Register abbreviation WDTH WDTL — Register name Watchdog timer selection ID register (upper) Watchdog timer selection ID register (lower) (Disabled) R/W Initial value R/W XXXXXXXXB R/W XXXXXXXXB — —
• R/W access symbols R/W : Readable / Writable R : Read only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned.
32
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ I/O MAP (MB95570H Series)
Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH to 0027H 0028H 0029H 002AH, 002BH 002CH 002DH to 0032H 0033H 0034H, 0035H 0036H 0037H 0038H to 0049H 004AH 004BH 004CH, 004DH 004EH 004FH to 006BH Register abbreviation PDR0 DDR0 PDR1 DDR1 — WATR PLLC SYCC STBC RSRR TBTC WPCR WDTC SYCC2 STBC2 — PDRF DDRF — PUL0 — PUL6 — T01CR1 T00CR1 — EIC20 EIC30 — LVDR — Port 6 pull-up register (Disabled) 8/16-bit composite timer 01 status control register 1 8/16-bit composite timer 00 status control register 1 (Disabled) External interrupt circuit control register ch. 4 External interrupt circuit control register ch. 6 (Disabled) LVDR reset voltage selection ID register (Disabled) Port 0 pull-up register (Disabled) Port F data register Port F direction register (Disabled) PLL control register System clock control register Standby control register Reset source register Time-base timer control register Watch prescaler control register Watchdog timer control register System clock control register 2 Standby control register 2 (Disabled) Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register (Disabled) Oscillation stabilization wait time setting register Register name R/W Initial value R/W R/W R/W R/W — R/W R/W R/W R/W R/W R/W R/W R/W — R/W R/W — R/W — R/W — R/W R/W — R/W R/W — R/W — 00000000B 00000000B 00000000B 00000000B — 11111111B 00000000B XXX11011B 00000000B 00000000B 00000000B 00XX0000B 00000000B — 00000000B 00000000B — 00000000B — 00000000B — 00000000B 00000000B — 00000000B 00000000B — 00000000B — (Continued) DS702-00003-1v0-E 33
R/W XXXXXXXXB
R/W XXXX0011B
MB95560H/570H/580H Series
Register abbreviation ADC1 ADC2 ADDH ADDL — FSR2 FSR SWRE0 FSR3 FSR4 WREN WROR — ILR0 ILR1 — ILR4 ILR5 — WRARH0 WRARL0 WRDR0 WRARH1 WRARL1 WRDR1 WRARH2 WRARL2 WRDR2 — T01CR0 T00CR0 T01DR T00DR TMCR0 —
Address 006CH 006DH 006EH 006FH 0070H 0071H 0072H 0073H 0074H 0075H 0076H 0077H 0078H 0079H 007AH 007BH, 007CH 007DH 007EH 007FH 0F80H 0F81H 0F82H 0F83H 0F84H 0F85H 0F86H 0F87H 0F88H 0F89H to 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H to 0FC2H
Register name 8/10-bit A/D converter control register 1 8/10-bit A/D converter control register 2 8/10-bit A/D converter data register upper 8/10-bit A/D converter data register lower (Disabled) Flash memory status register 2 Flash memory status register Flash memory sector write control register 0 Flash memory status register 3 Flash memory status register 4 Wild register address compare enable register Wild register data test setting register Mirror of register bank pointer (RP) and direct bank pointer (DP) Interrupt level setting register 0 Interrupt level setting register 1 (Disabled) Interrupt level setting register 4 Interrupt level setting register 5 (Disabled) Wild register address setting register (upper) ch. 0 Wild register address setting register (lower) ch. 0 Wild register data setting register ch. 0 Wild register address setting register (upper) ch. 1 Wild register address setting register (lower) ch. 1 Wild register data setting register ch. 1 Wild register address setting register (upper) ch. 2 Wild register address setting register (lower) ch. 2 Wild register data setting register ch. 2 (Disabled) 8/16-bit composite timer 01 status control register 0 8/16-bit composite timer 00 status control register 0 8/16-bit composite timer 01 data register 8/16-bit composite timer 00 data register 8/16-bit composite timer 00/01 timer mode control register (Disabled)
R/W Initial value R/W R/W R/W R/W — R/W R/W R/W R R/W R/W R/W — R/W R/W — R/W R/W — R/W R/W R/W R/W R/W R/W R/W R/W R/W — R/W R/W R/W R/W R/W — 00000000B 00000000B 00000000B 00000000B — 00000000B 000X0000B 00000000B 000XXXXXB 00000000B 00000000B 00000000B — 11111111B 11111111B — 11111111B 11111111B — 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B — 00000000B 00000000B 00000000B 00000000B 00000000B — (Continued)
34
DS702-00003-1v0-E
MB95560H/570H/580H Series
(Continued) Address 0FC3H 0FC4H to 0FE3H 0FE4H 0FE5H 0FE6H 0FE7H 0FE8H 0FE9H 0FEAH 0FEBH 0FECH 0FEDH to 0FFFH Register abbreviation AIDRL — CRTH CRTL — CRTDA SYSC CMCR CMDR WDTH WDTL — Register name A/D input disable register (lower) (Disabled) Main CR clock trimming register (upper) Main CR clock trimming register (lower) (Disabled) Main CR clock temperature dependent adjustment register System configuration register Clock monitoring control register Clock monitoring data register Watchdog timer selection ID register (upper) Watchdog timer selection ID register (lower) (Disabled) R/W Initial value R/W — 00000000B —
R/W 000XXXXXB R/W 000XXXXXB — R/W R/W R/W R/W — 00011111B 11000011B 00000000B 00000000B
R/W XXXXXXXXB R/W XXXXXXXXB — —
• R/W access symbols R/W : Readable / Writable R : Read only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned.
DS702-00003-1v0-E
35
MB95560H/570H/580H Series
■ I/O MAP (MB95580H Series)
Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH to 0027H 0028H 0029H 002AH 002BH 002CH 002DH to 0032H 0033H 0034H 0035H 0036H 0037H 0038H to 0048H 0049H 004AH 004BH 004CH, 004DH 004EH 004FH Register abbreviation PDR0 DDR0 PDR1 DDR1 — WATR PLLC SYCC STBC RSRR TBTC WPCR WDTC SYCC2 STBC2 — PDRF DDRF PDRG DDRG PUL0 — PUL6 — PULG T01CR1 T00CR1 — EIC10 EIC20 EIC30 — LVDR — Port G pull-up register 8/16-bit composite timer 01 status control register 1 8/16-bit composite timer 00 status control register 1 (Disabled) External interrupt circuit control register ch. 2/ch. 3 External interrupt circuit control register ch. 4/ch. 5 External interrupt circuit control register ch. 6/ch. 7 (Disabled) LVDR reset voltage selection ID register (Disabled) Port 6 pull-up register (Disabled) Port F data register Port F direction register Port G data register Port G direction register Port 0 pull-up register (Disabled) PLL control register System clock control register Standby control register Reset source register Time-base timer control register Watch prescaler control register Watchdog timer control register System clock control register 2 Standby control register 2 (Disabled) Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register (Disabled) Oscillation stabilization wait time setting register Register name R/W Initial value R/W R/W R/W R/W — R/W R/W R/W R/W R/W R/W R/W R/W — R/W R/W R/W R/W R/W — R/W — R/W R/W R/W — R/W R/W R/W — R/W — 00000000B 00000000B 00000000B 00000000B — 11111111B 00000000B XXX11011B 00000000B 00000000B 00000000B 00XX0000B 00000000B — 00000000B 00000000B 00000000B 00000000B 00000000B — 00000000B — 00000000B 00000000B 00000000B — 00000000B 00000000B 00000000B — 00000000B — (Continued) 36 DS702-00003-1v0-E
R/W XXXXXXXXB
R/W XXXX0011B
MB95560H/570H/580H Series
Register abbreviation SCR SMR SSR RDR/TDR ESCR ECCR — ADC1 ADC2 ADDH ADDL — FSR2 FSR SWRE0 FSR3 FSR4 WREN WROR — ILR0 ILR1 ILR2 — ILR4 ILR5 — WRARH0 WRARL0 WRDR0 WRARH1 WRARL1 WRDR1 WRARH2 WRARL2 WRDR2
Address 0050H 0051H 0052H 0053H 0054H 0055H 0056H to 006BH 006CH 006DH 006EH 006FH 0070H 0071H 0072H 0073H 0074H 0075H 0076H 0077H 0078H 0079H 007AH 007BH 007CH 007DH 007EH 007FH 0F80H 0F81H 0F82H 0F83H 0F84H 0F85H 0F86H 0F87H 0F88H
Register name LIN-UART serial control register LIN-UART serial mode register LIN-UART serial status register LIN-UART receive/transmit data register LIN-UART extended status control register LIN-UART extended communication control register (Disabled) 8/10-bit A/D converter control register 1 8/10-bit A/D converter control register 2 8/10-bit A/D converter data register upper 8/10-bit A/D converter data register lower (Disabled) Flash memory status register 2 Flash memory status register Flash memory sector write control register 0 Flash memory status register 3 Flash memory status register 4 Wild register address compare enable register Wild register data test setting register Mirror of register bank pointer (RP) and direct bank pointer (DP) Interrupt level setting register 0 Interrupt level setting register 1 Interrupt level setting register 2 (Disabled) Interrupt level setting register 4 Interrupt level setting register 5 (Disabled) Wild register address setting register (upper) ch. 0 Wild register address setting register (lower) ch. 0 Wild register data setting register ch. 0 Wild register address setting register (upper) ch. 1 Wild register address setting register (lower) ch. 1 Wild register data setting register ch. 1 Wild register address setting register (upper) ch. 2 Wild register address setting register (lower) ch. 2 Wild register data setting register ch. 2
R/W Initial value R/W R/W R/W R/W R/W R/W — R/W R/W R/W R/W — R/W R/W R/W R R/W R/W R/W ⎯ R/W R/W R/W — R/W R/W — R/W R/W R/W R/W R/W R/W R/W R/W R/W 00000000B 00000000B 00001000B 00000000B 00000100B 000000XXB — 00000000B 00000000B 00000000B 00000000B — 00000000B 000X0000B 00000000B 000XXXXXB 00000000B 00000000B 00000000B — 11111111B 11111111B 11111111B — 11111111B 11111111B — 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued)
DS702-00003-1v0-E
37
MB95560H/570H/580H Series
(Continued) Address 0F89H to 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H to 0FBBH 0FBCH 0FBDH 0FBEH to 0FC2H 0FC3H 0FC4H to 0FE3H 0FE4H 0FE5H 0FE6H 0FE7H 0FE8H 0FE9H 0FEAH 0FEBH 0FECH 0FEDH to 0FFFH Register abbreviation — T01CR0 T00CR0 T01DR T00DR TMCR0 — BGR1 BGR0 — AIDRL — CRTH CRTL — CRTDA SYSC CMCR CMDR WDTH WDTL — Register name (Disabled) 8/16-bit composite timer 01 status control register 0 8/16-bit composite timer 00 status control register 0 8/16-bit composite timer 01 data register 8/16-bit composite timer 00 data register 8/16-bit composite timer 00/01 timer mode control register (Disabled) LIN-UART baud rate generator register 1 LIN-UART baud rate generator register 0 (Disabled) A/D input disable register (Lower) (Disabled) Main CR clock trimming register (upper) Main CR clock trimming register (lower) (Disabled) Main CR clock temperature dependent adjustment System configuration register Clock monitoring control register Clock monitoring data register Watchdog timer selection ID register (upper) Watchdog timer selection ID register (lower) (Disabled) R/W Initial value — R/W R/W R/W R/W R/W — R/W R/W — R/W — — 00000000B 00000000B 00000000B 00000000B 00000000B — 00000000B 00000000B — 00000000B —
R/W 000XXXXXB R/W 000XXXXXB — R/W R/W R/W R/W — 00011111B 11000011B 00000000B 00000000B
R/W XXXXXXXXB R/W XXXXXXXXB — —
• R/W access symbols R/W : Readable / Writable R : Read only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned.
38
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■ INTERRUPT SOURCE TABLE (MB95560H Series)
Vector table address Interrupt source Interrupt request number IRQ00 IRQ01 IRQ02 IRQ03 IRQ04 IRQ05 IRQ06 IRQ07 IRQ08 IRQ09 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 IRQ20 IRQ21 IRQ22 IRQ23 Upper FFFAH FFF8H FFF6H FFF4H FFF2H FFF0H FFEEH FFECH FFEAH FFE8H FFE6H FFE4H FFE2H FFE0H FFDEH FFDCH FFDAH FFD8H FFD6H FFD4H FFD2H FFD0H FFCEH FFCCH Lower FFFBH FFF9H FFF7H FFF5H FFF3H FFF1H FFEFH FFEDH FFEBH FFE9H FFE7H FFE5H FFE3H FFE1H FFDFH FFDDH FFDBH FFD9H FFD7H FFD5H FFD3H FFD1H FFCFH FFCDH Priority order of Bit name of interrupt sources interrupt level of the same level (occurring setting register simultaneously) L00 [1:0] L01 [1:0] L02 [1:0] L03 [1:0] L04 [1:0] L05 [1:0] L06 [1:0] L07 [1:0] L08 [1:0] L09 [1:0] L10 [1:0] L11 [1:0] L12 [1:0] L13 [1:0] L14 [1:0] L15 [1:0] L16 [1:0] L17 [1:0] L18 [1:0] L19 [1:0] L20 [1:0] L21 [1:0] L22 [1:0] L23 [1:0] Low High
External interrupt ch. 4 External interrupt ch. 5 External interrupt ch. 2 External interrupt ch. 6 External interrupt ch. 3 External interrupt ch. 7 — 8/16-bit composite timer ch. 0 (lower) 8/16-bit composite timer ch. 0 (upper) LIN-UART (reception) LIN-UART (transmission) — — — — — 8/16-bit composite timer ch. 1 (upper) — — — 8/10-bit A/D converter Time-base timer Watch prescaler — 8/16-bit composite timer ch. 1 (lower) Flash memory
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MB95560H/570H/580H Series
■ INTERRUPT SOURCE TABLE (MB95570H Series)
Vector table address Interrupt source Interrupt request number IRQ00 IRQ01 IRQ02 IRQ03 IRQ04 IRQ05 IRQ06 IRQ07 IRQ08 IRQ09 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 IRQ20 IRQ21 IRQ22 IRQ23 Upper FFFAH FFF8H FFF6H FFF4H FFF2H FFF0H FFEEH FFECH FFEAH FFE8H FFE6H FFE4H FFE2H FFE0H FFDEH FFDCH FFDAH FFD8H FFD6H FFD4H FFD2H FFD0H FFCEH FFCCH Lower FFFBH FFF9H FFF7H FFF5H FFF3H FFF1H FFEFH FFEDH FFEBH FFE9H FFE7H FFE5H FFE3H FFE1H FFDFH FFDDH FFDBH FFD9H FFD7H FFD5H FFD3H FFD1H FFCFH FFCDH Priority order of Bit name of interrupt sources interrupt level of the same level (occurring setting register simultaneously) L00 [1:0] L01 [1:0] L02 [1:0] L03 [1:0] L04 [1:0] L05 [1:0] L06 [1:0] L07 [1:0] L08 [1:0] L09 [1:0] L10 [1:0] L11 [1:0] L12 [1:0] L13 [1:0] L14 [1:0] L15 [1:0] L16 [1:0] L17 [1:0] L18 [1:0] L19 [1:0] L20 [1:0] L21 [1:0] L22 [1:0] L23 [1:0] Low High
External interrupt ch. 4 — — External interrupt ch. 6 — — — 8/16-bit composite timer ch. 0 (lower) 8/16-bit composite timer ch. 0 (upper) — — — — — — — — — — — 8/10-bit A/D converter Time-base timer Watch prescaler — — Flash memory
40
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MB95560H/570H/580H Series
■ INTERRUPT SOURCE TABLE (MB95580H Series)
Vector table address Interrupt source Interrupt request number IRQ00 IRQ01 IRQ02 IRQ03 IRQ04 IRQ05 IRQ06 IRQ07 IRQ08 IRQ09 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 IRQ20 IRQ21 IRQ22 IRQ23 Upper FFFAH FFF8H FFF6H FFF4H FFF2H FFF0H FFEEH FFECH FFEAH FFE8H FFE6H FFE4H FFE2H FFE0H FFDEH FFDCH FFDAH FFD8H FFD6H FFD4H FFD2H FFD0H FFCEH FFCCH Lower FFFBH FFF9H FFF7H FFF5H FFF3H FFF1H FFEFH FFEDH FFEBH FFE9H FFE7H FFE5H FFE3H FFE1H FFDFH FFDDH FFDBH FFD9H FFD7H FFD5H FFD3H FFD1H FFCFH FFCDH Priority order of Bit name of interrupt sources interrupt level of the same level (occurring setting register simultaneously) L00 [1:0] L01 [1:0] L02 [1:0] L03 [1:0] L04 [1:0] L05 [1:0] L06 [1:0] L07 [1:0] L08 [1:0] L09 [1:0] L10 [1:0] L11 [1:0] L12 [1:0] L13 [1:0] L14 [1:0] L15 [1:0] L16 [1:0] L17 [1:0] L18 [1:0] L19 [1:0] L20 [1:0] L21 [1:0] L22 [1:0] L23 [1:0] Low High
External interrupt ch. 4 External interrupt ch. 5 External interrupt ch. 2 External interrupt ch. 6 External interrupt ch. 3 External interrupt ch. 7 — 8/16-bit composite timer ch. 0 (lower) 8/16-bit composite timer ch. 0 (upper) LIN-UART (reception) LIN-UART (transmission) — — — — — — — — — 8/10-bit A/D converter Time-base timer Watch prescaler — — Flash memory
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MB95560H/570H/580H Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Power supply voltage*1 Input voltage*
1 1
Symbol VCC VI VO ICLAMP Σ|ICLAMP| IOL1 IOL2 IOLAV1
Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 −2 — — Max VSS + 6 VSS + 6 VSS + 6 +2 20 15 15 4 —
Unit V V V mA mA mA *2 *2
Remarks
Output voltage*
Maximum clamp current Total maximum clamp current “L” level maximum output current
Applicable to specific pins*3 Applicable to specific pins*3 Other than P05, P06, P62 and P63*4 P05, P06, P62 and P63*4 Other than P05, P06, P62 and P63*4 Average output current= operating current × operating ratio (1 pin) P05, P06, P62 and P63*4 Average output current= operating current × operating ratio (1 pin)
“L” level average current IOLAV2 “L” level total maximum output current “L” level total average output current “H” level maximum output current
mA 12
ΣIOL ΣIOLAV IOH1 IOH2 IOHAV1
— —
48 50 − 15 − 15 −4
mA mA Total average output current= operating current × operating ratio (Total number of pins) Other than P05, P06, P62 and P63*4 P05, P06, P62 and P63*4 Other than P05, P06, P62 and P63*4 Average output current= operating current × operating ratio (1 pin) P05, P06, P62 and P63*4 Average output current= operating current × operating ratio (1 pin)
—
mA
“H” level average current IOHAV2 “H” level total maximum output current “H” level total average output current Power consumption Operating temperature Storage temperature
— −8
mA
ΣIOH ΣIOHAV Pd TA Tstg
— — — − 40 − 55
48 − 50 320 + 85 + 150
mA mA mW °C °C (Continued) Total average output current= operating current × operating ratio (Total number of pins)
42
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(Continued) *1: The parameter is based on VSS = 0.0 V. *2: VI and VO must not exceed VCC + 0.3 V. VI must not exceed the rated voltage. However, if the maximum current to/from an input is limited by means of an external component, the ICLAMP rating is used instead of the VI rating. *3: Applicable to the following pins: P00 to P07, P62 to P64, PF0, PF1, PG1, PG2 (P00, and P62 to P64 are only available on MB95F562H/F562K/F563H/F563K/F564H/F564K. P01, P02, P03, P07, PF0. PF1, PG1 and PG2 are only available on MB95F562H/F562K/F563H/F563K/F564H/F564K/F582H/F582K/F583H/ F583K/F584H/F584K.) • Use under recommended operating conditions. • Use with DC voltage (current). • The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor between the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal. • The value of the limiting resistor should be set to a value at which the current to be input to the microcontroller pin when the HV (High Voltage) signal is input is below the standard value, irrespective of whether the current is transient current or stationary current. • When the microcontroller drive current is low, such as in low power consumption modes, the HV (High Voltage) input potential may pass through the protective diode to increase the potential of the VCC pin, affecting other devices. • If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since power is supplied from the pins, incomplete operations may be executed. • If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage of power supply may not be sufficient to enable a power-on reset. • Do not leave the HV (High Voltage) input pin unconnected. • Example of a recommended circuit: • Input/Output equivalent circuit
Protective diode VCC Limiting resistor HV(High Voltage) input (0 V to 16 V) N-ch R P-ch
*4: P62 and P63 are only available on MB95F562H/F562K/F563H/F563K/F564H/F564K. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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MB95560H/570H/580H Series
2. Recommended Operating Conditions
(VSS = 0.0 V) Parameter Symbol Value Min 2.4*1*2 Power supply voltage Smoothing capacitor Operating temperature VCC 2.3 2.9 2.3 CS TA 0.022 − 40 +5 Max 5.5*1 5.5 5.5 5.5 1 + 85 + 35 V Unit In normal operation In normal operation Hold condition in stop mode µF *3 °C Other than on-chip debug mode On-chip debug mode Remarks Other than on-chip debug Hold condition in stop mode mode On-chip debug mode
*1: The value varies depending on the operating frequency, the machine clock and the analog guaranteed range. *2: The value is 2.88 V when the low-voltage detection reset is used. *3: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for the VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see the diagram below. To prevent the device from unintentionally entering an unknown mode due to noise, minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed circuit board. • DBG / RST / C pins connection diagram
*
DBG C RST Cs
*: Since the DBG pin becomes a communication pin in on-chip debug mode, set a pull-up resistor value suiting the input/output specifications of P12/EC0/DBG.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand.
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3. DC Characteristics
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = − 40°C to + 85°C) Parameter Symbol VIH Pin name P04 P00 to P03 , P05 to P07*4, P12, P62 to P64*3, PF0*4, PF1*4, PG1*4, PG2*4 PF2 P04 P00 to P03 , P05 to P07*4, P12, P62 to P64*3, PF0*4, PF1*4, PG1*4, PG2*4 PF2 P12, PF2 P04, PF0*4, PF1*4, PG1*4, PG2*4 P00*3 to P03*4, P05 to P07*4, P62 to P64*3 P04, P12 PF0 to PF2*4, PG1*4, PG2*4 P00*3 to P03*4, P05 to P07*4, P12, P62 to P64*3 All input pins P00*3 to P07*4, P62 to P64*3, PG1*4, PG2*4*5
*3 *4 *3 *4
Condition —
Value Min 0.7 VCC Typ*1 — Max*2 VCC + 0.3
Unit V
Remarks Hysteresis input
"H" level input voltage
VIHS
—
0.8 VCC
—
VCC + 0.3
V
Hysteresis input
VIHM VIL
— —
0.8 VCC VSS − 0.3
— —
VCC + 0.3 0.3 VCC
V V
Hysteresis input Hysteresis input
“L” level input voltage
VILS
—
VSS − 0.3
—
0.2 VCC
V
Hysteresis input
VILM Open-drain output application voltage VD
— —
VSS − 0.3 VSS − 0.3
— —
0.2 VCC Vss + 5.5
V V
Hysteresis input
“H” level output voltage
VOH1
IOH = −4 mA
VCC − 0.5
—
—
V
VOH2
IOH = −8 mA
VCC − 0.5
—
—
V
VOL1 “L” level output voltage
IOL = 4 mA
—
—
0.4
V
VOL2
IOL = 12 mA
—
—
0.4
V
Input leak current (Hi-Z output leak current) Pull-up resistance Input capacitance
ILI
0.0 V < VI < VCC
−5
—
+5
When pull-up µA resistance is disabled When pull-up kΩ resistance is enabled pF (Continued)
RPULL CIN
VI = 0 V
25 —
50 5
100 15
Other than VCC f = 1 MHz and VSS
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MB95560H/570H/580H Series
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = − 40°C to + 85°C) Parameter Symbol Pin name Condition Value Min — ICC FCH = 32 MHz FMP = 16 MHz Main clock mode (divided by 2) Typ*1 Max*2 3.6 5.8 Unit Remarks
Except during mA Flash memory writing and erasing During Flash mA memory writing and erasing mA At A/D conversion mA
— —
7.5 4.1 1.3
13.8 9.1 3
ICCS
FCH = 32 MHz FMP = 16 MHz Main sleep mode (divided by 2) VCC FCL = 32 kHz (External clock FMPL = 16 kHz operation) Subclock mode (divided by 2) TA = + 25°C FCL = 32 kHz FMPL = 16 kHz Subsleep mode (divided by 2) TA = + 25°C FCL = 32 kHz Watch mode Main stop mode TA = + 25°C FCRH = 4 MHz FMP = 4 MHz Main CR clock mode Sub-CR clock mode (divided by 2) TA = + 25°C FCH = 32 MHz Time-base timer mode TA = + 25°C Substop mode TA = + 25°C
—
ICCL
—
49
145
µA
Power supply current*5
ICCLS*6
—
6
10
µA
I
CCT*6
—
5
9
µA
ICCMCR VCC ICCSCR
—
1.1
4.6
mA
—
58.1
230
µA
ICCTS VCC (External clock operation) ICCH
—
330
370
µA Main stop mode for a single µA external clock product (Continued)
—
4
15
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MB95560H/570H/580H Series
(Continued) Parameter Symbol Pin name
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = − 40°C to + 85°C) Value Condition Unit Remarks Min Typ*1 Max*2 Current consumption for low-voltage detection circuit only — 4 7 µA
ILVD
Power supply current*5
ICRH
VCC
Current consumption for the main CR oscillator Current consumption for the sub-CR oscillator oscillating at 100 kHz
—
240
320
µA
ICRL
—
7
20
µA
*1: VCC = 5.0 V, TA = + 25°C *2: VCC = 5.5 V, TA = + 25°C *3: P00, P62, P63 and P64 are available only on MB95F562H/F562K/F563H/F563K/F564H/F564K. *4: P01, P02, P03, P07, PF0, PF1, PG1 and PG2 are available only on MB95F562H/F562K/F563H/F563K/ F564H/F564K/F582H/F582K/F583H/F583K/F584H/F584K. *5: • The power supply current is determined by the external clock. When the low-voltage detection option is selected, the power-supply current will be the sum of adding the current consumption of the low-voltage detection circuit (ILVD) to one of the value from ICC to ICCH. In addition, when both the low-voltage detection option and the CR oscillator are selected, the power supply current will be the sum of adding up the current consumption of the low-voltage detection circuit, the current consumption of the CR oscillators (ICRH, ICRL) and a specified value. In on-chip debug mode, the CR oscillator (ICRH) and the low-voltage detection circuit are always enabled, and current consumption therefore increases accordingly. • See "4. AC Characteristics: (1) Clock Timing" for FCH and FCL. • See "4. AC Characteristics: (2) Source Clock / Machine Clock" for FMP and FMPL. *6: In sub-CR clock mode, the power supply current value will become the sum of adding ICRL to ICCLS or ICCT. In addition, when the sub-CR clock mode is selected with FMPL being 50 kHz, the current consumption will increase accordingly.
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MB95560H/570H/580H Series
4. AC Characteristics
(1) Clock Timing (VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = − 40°C to + 85°C) Parameter Symbol Pin name Condition X0, X1 FCH X0 X0, X1 — X1 : open * Min 1 1 1 3.92 Value Typ — — — Max Unit Remarks When the main oscillation circuit is used
16.25 MHz 12 32.5
3.8
7.84
7.6
9.8 Clock frequency FCRH ⎯ — 9.5
11.76
11.4
15.68
15.2
— FCL X0A, X1A — — FCRL ⎯ — 50
MHz When the main external clock MHz is used Operating conditions 4 4.08 MHz • The main CR clock is used. • 0°C < TA < +70°C Operating conditions • The main CR clock is used. 4 4.2 MHz • − 40 °C ≤ TA < 0 °C, + 70 °C < TA ≤ + 85 °C Operating conditions 8 8.16 MHz • PLL multiplier: 2 • 0°C < TA < +70°C Operating conditions • PLL multiplier: 2 8 8.4 MHz • − 40 °C ≤ TA < 0 °C, + 70 °C < TA ≤ + 85 °C Operating conditions 10 10.2 MHz • PLL multiplier: 2.5 • 0°C < TA < +70°C Operating conditions • PLL multiplier: 2.5 10 10.5 MHz • − 40 °C ≤ TA < 0 °C, + 70 °C < TA ≤ + 85 °C Operating conditions 12 12.24 MHz • PLL multiplier: 3 • 0°C < TA < +70°C Operating conditions • PLL multiplier: 3 12 12.6 MHz • − 40 °C ≤ TA < 0 °C, + 70 °C < TA ≤ + 85 °C Operating conditions 16 16.32 MHz • PLL multiplier: 4 • 0°C < TA < +70°C Operating conditions • PLL multiplier: 4 16 16.8 MHz • − 40 °C ≤ TA < 0 °C, + 70 °C < TA ≤ + 85 °C When the sub-oscillation 32.768 — kHz circuit is used When the sub-external clock is 32.768 — kHz used When the sub-CR clock is 100 150 kHz used (Continued)
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(Continued) Parameter Symbol Pin name Condition X0, X1 Clock cycle time tHCYL tLCYL Input clock pulse width Input clock rise time and fall time CR oscillation start time tWH1 tWL1 tWH2 tWL2 tCR tCF tCRHWK tCRLWK —
(VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = − 40°C to + 85°C) Min 61.5 83.4 30.8 — 33.4 14.4 — — — — — Value Typ — — — 30.5 — — 15.2 — — — — Max 1000 1000 1000 — — — — 5 5 50 30 Unit ns ns ns µs ns ns Remarks When the main oscillation circuit is used When an external clock is used When the subclock is used
X0 X1 : open X0, X1 * X0A, X1A — X0 X1 : open X0, X1 * X0A X0 X0, X1 — — — X1 : open * — —
When an external clock is used, the duty ratio should µs range between 40% and 60%. ns
When an external clock is ns used When the main CR clock is used When the sub-CR clock is µs used µs
*: The external clock signal is input to X0 and the inverted external clock signal to X1.
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MB95560H/570H/580H Series
• Input waveform generated when an external clock (main clock) is used
tHCYL tWH1 tCR X0, X1 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC tCF tWL1
• Figure of main clock input port external connection
When a crystal oscillator or a ceramic oscillator is used When an external clock is used When an external clock (X1 is open) is used
X0
X1 FCH
X0
X1 Open FCH
X0
X1
FCH
• Input waveform generated when an external clock (subclock) is used
tLCYL tWH2 tCR X0A 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC tCF tWL2
• Figure of subclock input port external connection
When a crystal oscillator or a ceramic oscillator is used When an external clock is used
X0A
X1A FCL
X0A
X1A Open FCL
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(2) Source Clock / Machine Clock (VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = − 40°C to + 85°C) Parameter Symbol Pin name Value Min 61.5 Typ — Max 2000 Unit Remarks When the main external clock is used Min: FCH = 32.5 MHz, divided by 2 Max: FCH = 1 MHz, divided by 2 When the main CR clock is used Min: FCRH = 4 MHz, multiplied by 4 Max: FCRH = 4 MHz, divided by 4 When the sub-oscillation clock is used FCL = 32.768 kHz, divided by 2 When the sub-CR clock is used FCRL = 100 kHz, divided by 2
ns
Source clock cycle time*1
tSCLK
—
62.5 — —
— 61 20 — 4 16.384 50 —
1000 — — 16.25 — — — 32000
ns µs µs
FSP Source clock frequency FSPL —
0.5 — — — 61.5
MHz When the main oscillation clock is used MHz When the main CR clock is used kHz When the sub-oscillation clock is used kHz ns When the sub-CR clock is used FCRL = 100 kHz, divided by 2 When the main oscillation clock is used Min: FSP = 16.25 MHz, no division Max: FSP = 0.5 MHz, divided by 16 When the main CR clock is used Min: FSP = 4 MHz, no division Max: FSP = 4 MHz, divided by 4 When the sub-oscillation clock is used Min: FSPL = 16.384 kHz, no division Max: FSPL = 16.384 kHz, divided by 16 When the sub-CR clock is used Min: FSPL = 50 kHz, no division Max: FSPL = 50 kHz, divided by 16
Machine clock cycle time*2 (minimum instruction execution time)
250 tMCLK — 61
—
1000
ns
—
976.5
µs
20 0.031 0.25 — FMPL 1.024 3.125
— — — — —
320 16.25 16 16.384 50
µs
FMP Machine clock frequency
MHz When the main oscillation clock is used MHz When the main CR clock is used kHz When the sub-oscillation clock is used kHz When the sub-CR clock is used FCRL = 100 kHz
*1: This is the clock before it is divided according to the division ratio set by the machine clock division ratio select bits (SYCC:DIV1, DIV0). This source clock is divided to become a machine clock according to the division ratio set by the machine clock division ratio select bits (SYCC:DIV1, DIV0). In addition, a source clock can be selected from the following. • Main clock divided by 2 • PLL multiplication of main clock (Select a multiplier from 2, 2.5, 3 and 4.) • Main CR clock • Subclock divided by 2 • Sub-CR clock divided by 2 *2: This is the operating clock of the microcontroller. A machine clock can be selected from the following. • Source clock (no division) • Source clock divided by 4 • Source clock divided by 8 • Source clock divided by 16
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MB95560H/570H/580H Series
• Schematic diagram of the clock generation block
FCH (Main oscillation clock)
Divided by 2
FMPLL (Main CR PLL) SCLK (Source clock) Division circuit × 1 × 1/4 × 1/8 × 1/16
FCRH (Main CR clock)
MCLK (Machine clock)
FCL (Sub-oscillation clock)
Divided by 2
Machine clock divide ratio select bits (SYCC:DIV1, DIV0) FCRL (Sub-CR clock)
Divided by 2
Clock mode select bits (SYCC2: RCS1, RCS0)
• Operating voltage - Operating frequency (When TA = − 40°C to + 85°C) MB95560H/570H/580H (without the on-chip debug function)
5.5 5.0
Operating voltage (V)
4.0 3.5 3.0 2.7 2.4
A/D converter operation range
16 kHz
3 MHz
10 MHz
16.25 MHz
Source clock frequency (FSP/FSPL)
• Operating voltage - Operating frequency (When TA = − 40°C to + 85°C) MB95560H/570H/580H (with the on-chip debug function)
5.5 5.0
Operating voltage (V)
A/D converter operation range 4.0 3.5 3.0
2.9
16 kHz
3 MHz
12.5 MHz
16.25 MHz
Source clock frequency (FSP)
52
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(3) External Reset (VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = − 40°C to + 85°C) Parameter Symbol Value Min 2 tMCLK*1 RST “L” level pulse width tRSTL Oscillation time of the oscillator*2 + 200 200 *1: See “(2) Source Clock / Machine Clock” for tMCLK. *2: The oscillation time of an oscillator is the time for it to reach 90% of its amplitude. The crystal oscillator has an oscillation time of between several ms and tens of ms. The ceramic oscillator has an oscillation time of between hundreds of µs and several ms. The external clock has an oscillation time of 0 ms. The CR oscillator clock has an oscillation time of between several µs and several ms. • In normal operation
tRSTL RST 0.2 VCC 0.2 VCC
Max — — —
Unit ns µs µs
Remarks In normal operation In stop mode, subclock mode, subsleep mode, watch mode, and power-on In time-base timer mode
• In stop mode, subclock mode, subsleep mode, watch mode and power-on
RST tRSTL 0.2 VCC 90% of amplitude 0.2 VCC
X0
Internal operating clock Oscillation time of oscillator Internal reset
200 μs
Oscillation stabilization wait time Execute instruction
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MB95560H/570H/580H Series
(4) Power-on Reset (VSS = 0.0 V, TA = − 40°C to + 85°C) Parameter Power supply rising time Power supply cutoff time Symbol tR tOFF Condition — — Value Min — 1 Max 50 — Unit ms ms Wait time until power-on Remarks
tR 2.5 V
tOFF
VCC
0.2 V
0.2 V
0.2 V
Note: A sudden change of power supply voltage may activate the power-on reset function. When changing the power supply voltage during the operation, set the slope of rising to a value below within 30 mV/ms as shown below.
VCC Set the slope of rising to a value below 30 mV/ms. Hold condition in stop mode
2.3 V VSS
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(5) Peripheral Input Timing (VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = − 40°C to + 85°C) Parameter Peripheral input “H” pulse width Peripheral input “L” pulse width Symbol tILIH tIHIL Pin name INT02 to INT07*2,*3, EC0*2, EC1*4 Value Min 2 tMCLK*1 2t
MCLK*1
Max — —
Unit ns ns
tILIH
tIHIL
0.8 VCC
0.8 VCC 0.2 VCC 0.2 VCC
INT02 to INT07*2, *3, EC0*2, EC1*4
*1: See “(2) Source Clock / Machine Clock” for tMCLK. *2: INT04, INT06 and EC0 are available on all products. *3: INT02, INT03, INT05 and INT07 are available only on MB95F562H/F562K/F563H/F563K/F564H/F564K/ F582H/F582K/F583H/F583K/F584H/F584K. *4: EC1 is available only on MB95F562H/F562K/F563H/F563K/F564H/F564K.
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(6) LIN-UART Timing (available only on MB95F562H/F562K/F563H/F563K/F564H/F564K/F582H/F582K/ F583H/F583K/F584H/F584K) Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is disabled*2. (ESCR register: SCES bit = 0, ECCR register: SCDE bit = 0) (VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40°C to + 85°C) Parameter Serial clock cycle time SCK ↓→ SOT delay time Valid SIN → SCK ↑ SCK ↑→ valid SIN hold time Serial clock “L” pulse width Serial clock “H” pulse width SCK ↓→ SOT delay time Valid SIN → SCK ↑ SCK ↑→ valid SIN hold time SCK fall time SCK rise time Symbol Pin name tSCYC tSLOVI tIVSHI tSHIXI tSLSH tSHSL tSLOVE tIVSHE tSHIXE tF tR SCK SCK, SOT Internal clock operation output pin: SCK, SIN CL = 80 pF + 1 TTL SCK, SIN SCK SCK SCK, SOT External clock SCK, SIN operation output pin: SCK, SIN CL = 80 pF + 1 TTL SCK SCK t Condition Value Min 5 tMCLK*3 − 50
MCLK 3
Max — + 50 — — — — 2t
MCLK 3
Unit ns ns ns ns ns ns ns ns ns ns ns
* + 80 0 * − tR
3t t
MCLK 3
MCLK 3
* + 10
— 30 t
MCLK 3
* + 60
— — 10 10
* + 30
— —
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock. *3: See “(2) Source Clock / Machine Clock” for tMCLK.
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• Internal shift clock mode
tSCYC 0.8 VCC SCK 0.2 VCC tSLOVI 0.8 VCC SOT 0.2 VCC tIVSHI SIN 0.3 VCC 0.3 VCC tSHIXI 0.2 VCC
0.7 VCC 0.7 VCC
• External shift clock mode
tSLSH 0.8 VCC SCK 0.2 VCC tF SOT 0.2 VCC tIVSHE SIN 0.3 VCC 0.3 VCC tSHIXE tSLOVE 0.8 VCC 0.2 VCC tR 0.8 VCC tSHSL 0.8 VCC
0.7 VCC 0.7 VCC
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Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is disabled*2. (ESCR register: SCES bit = 1, ECCR register: SCDE bit = 0) (VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = − 40°C to + 85°C) Parameter Serial clock cycle time SCK ↑→ SOT delay time Valid SIN → SCK ↓ SCK ↓→ valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↑→ SOT delay time Valid SIN → SCK ↓ SCK ↓→ valid SIN hold time SCK fall time SCK rise time Symbol Pin name tSCYC tSHOVI tIVSLI tSLIXI tSHSL tSLSH tSHOVE tIVSLE tSLIXE tF tR SCK SCK, SOT Internal clock operation output pin: SCK, SIN CL = 80 pF + 1 TTL SCK, SIN SCK SCK SCK, SOT External clock SCK, SIN operation output pin: SCK, SIN CL = 80 pF + 1 TTL SCK SCK t Condition Value Min 5 tMCLK*3 − 50
MCLK 3
Max — + 50 — — — — 2t
MCLK 3
Unit ns ns ns ns ns ns ns ns ns ns ns
* + 80 0 * − tR
3t t
MCLK 3
MCLK 3
* + 10
— 30 t
MCLK 3
* + 60
— — 10 10
* + 30
— —
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock. *3: See “(2) Source Clock / Machine Clock” for tMCLK.
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• Internal shift clock mode
tSCYC 0.8 VCC SCK 0.2 VCC tSHOVI 0.8 VCC SOT 0.2 VCC tIVSLI SIN 0.3 VCC 0.3 VCC tSLIXI 0.8 VCC
0.7 VCC 0.7 VCC
• External shift clock mode
tSHSL 0.8 VCC SCK 0.2 VCC tR SOT 0.2 VCC tIVSLE SIN 0.3 VCC 0.3 VCC tSLIXE tSHOVE 0.8 VCC tF 0.2 VCC 0.2 VCC 0.8 VCC tSLSH
0.7 VCC 0.7 VCC
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Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is enabled*2. (ESCR register: SCES bit = 0, ECCR register: SCDE bit = 1) (VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = − 40°C to + 85°C) Parameter Serial clock cycle time SCK ↑→ SOT delay time Valid SIN → SCK ↓ SCK ↓→ valid SIN hold time SOT → SCK ↓ delay time Symbol Pin name tSCYC tSHOVI tIVSLI tSLIXI tSOVLI SCK SCK, SOT Internal clock SCK, SIN operation output pin: SCK, SIN CL = 80 pF + 1 TTL SCK, SOT t Condition Value Min 5 tMCLK*3 − 50
MCLK 3
Max — + 50 — — —
Unit ns ns ns ns ns
* + 80 0 * − 70
3t
MCLK 3
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock. *3: See “(2) Source Clock / Machine Clock” for tMCLK.
tSCYC
SCK
tSOVLI
0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tIVSLI tSLIXI 0.7 VCC 0.3 VCC 0.7 VCC 0.3 VCC tSHOVI 0.8 VCC 0.2 VCC 0.2 VCC
SOT
SIN
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Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is enabled*2. (ESCR register: SCES bit = 1, ECCR register: SCDE bit = 1) (VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = − 40°C to + 85°C) Parameter Serial clock cycle time SCK ↓→ SOT delay time Valid SIN → SCK ↑ SCK ↑→ valid SIN hold time SOT → SCK ↑ delay time Symbol Pin name tSCYC tSLOVI tIVSHI tSHIXI tSOVHI SCK SCK, SOT Internal clock SCK, SIN operating output pin: SCK, SIN CL = 80 pF + 1 TTL SCK, SOT t Condition Value Min 5 tMCLK*3 − 50
MCLK 3
Max — + 50 — — —
Unit ns ns ns ns ns
* + 80 0 * − 70
3t
MCLK 3
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock. *3: See “(2) Source Clock / Machine Clock” for tMCLK.
tSCYC
SCK
tSOVHI
0.8 VCC 0.2 VCC tSLOVI 0.8 VCC 0.2 VCC tIVSHI tSHIXI 0.7 VCC 0.3 VCC 0.8 VCC 0.2 VCC 0.7 VCC 0.3 VCC
0.8 VCC
SOT
SIN
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(7) Low-voltage Detection (VSS = 0.0 V, TA = − 40°C to + 85°C) Parameter Symbol Value Min 2.52 Release voltage* VDL+ 2.61 2.89 3.08 2.43 Detection voltage* VDL− 2.52 2.80 2.99 Hysteresis width Power supply start voltage Power supply end voltage Power supply voltage change time (at power supply rise) Power supply voltage change time (at power supply fall) Reset release delay time Reset detection delay time LVD threshold voltage transition stabilization time VHYS Voff Von tr — — 4.9 650 Typ 2.7 2.8 3.1 3.3 2.6 2.7 3 3.2 — — — — Max 2.88 2.99 3.31 3.52 2.77 2.88 3.20 3.41 100 2.3 — — mV V V µs Slope of power supply that the reset release signal generates within the rating (VDL+) Slope of power supply that the reset detection signal generates within the rating (VDL-) V At power supply fall V At power supply rise Unit Remarks
tf td1 td2 tstb
650 — — 10
— — — —
— 30 30 —
µs µs µs µs
*: The release voltage and the detection voltage can be selected by using the LVD reset voltage selection ID register (LVDR) in the low-voltage detection reset circuit. For details of the LVDR register, refer to “CHAPTER 18 LOW-VOLTAGE DETECTION RESET CIRCUIT” in the hardware manual of the MB95560H/ 570H/580H Series.
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VCC
Von
Voff
time tf tr
VDL+ VHYS VDL-
Internal reset signal time td2 td1
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5. A/D Converter (1) A/D Converter Electrical Characteristics
(VCC = 2.7 V to 5.5 V, VSS = 0.0 V, TA = − 40°C to + 85°C) Parameter Resolution Total error Linearity error Differential linear error Zero transition voltage Full-scale transition voltage Compare time Sampling time Analog input current Analog input voltage VOT VFST — — IAIN VAIN — Symbol Value Min — −3 − 2.5 − 1.9 Typ — — — — Max 10 +3 + 2.5 + 1.9 Unit bit LSB LSB LSB V V µs µs µA V 2.7 V ≤ VCC ≤ 5.5 V 2.7 V ≤ VCC ≤ 5.5 V, with external impedance < 3.3 kΩ Remarks
VSS − 7.2 LSB VSS + 0.5 LSB VSS + 8.2 LSB VCC − 6.2 LSB VCC − 1.5 LSB VCC + 9.2 LSB 3 0.517 − 0.3 VSS — — — — 10 ∞ + 0.3 VCC
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(2) Notes on Using the A/D Converter • External impedance of analog input and its sampling time • The A/D converter has a sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, considering the relationship between the external impedance and minimum sampling time, either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. In addition, if sufficient sampling time cannot be secured, connect a capacitor of about 0.1 µF to the analog input pin. • Analog input equivalent circuit
Analog input R C
Comparator
During sampling: ON
VCC 4.5 V ≤ VCC ≤ 5.5 V 2.7 V ≤ VCC < 5.5 V R 3.3 kΩ (Max) 15.7 kΩ (Max) C 14.89 pF (Max) 14.89 pF (Max)
Note: The values are reference values.
• Relationship between external impedance and minimum sampling time
[External impedance = 0 kΩ to 100 kΩ] 100000 20000 [External impedance = 0 kΩ to 20 kΩ]
80000 External impedance [kΩ] External impedance [kΩ] 15000
60000
10000
40000
5000
20000
0 0 2 4 6 8 10 12 Minimum sampling time [μs]
0 0 0.5 1 1.5 2 2.5 Minimum sampling time [μs] Minimum sampling time with VCC > 2.7 V Minimum sampling time with VCC > 2.4 V
• A/D conversion error As |VCC − VSS| decreases, the A/D conversion error increases proportionately.
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(3) Definitions of A/D Converter Terms • Resolution It indicates the level of analog variation that can be distinguished by the A/D converter. When the number of bits is 10, analog voltage can be divided into 210 = 1024. • Linearity error (unit: LSB) It indicates how much an actual conversion value deviates from the straight line connecting the zero transition point (“00 0000 0000” ← → “00 0000 0001”) of a device to the full-scale transition point (“11 1111 1111” ← → “11 1111 1110”) of the same device. • Differential linear error (unit: LSB) It indicates how much the input voltage required to change the output code by 1 LSB deviates from an ideal value. • Total error (unit: LSB) It indicates the difference between an actual value and a theoretical value. The error can be caused by a zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise.
Ideal I/O characteristics
3FFH 3FEH 3FDH 2 LSB
Total error
3FFH 3FEH 3FDH Actual conversion characteristic
{1 LSB × (N-1) + 0.5 LSB}
VFST
Digital output
Digital output
004H 003H 002H 001H 0.5 LSB
004H 003H
VOT
1 LSB
VNT
Actual conversion characteristic Ideal characteristic
002H 001H
VSS
Analog input 1 LSB = VCC - VSS (V) 1024
VCC
VSS
Analog input
VCC
VNT - {1 LSB × (N - 1) + 0.5 LSB} Total error of = [LSB] digital output N 1 LSB
N
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N - 1)H to NH
(Continued)
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(Continued)
Zero transition error
004H Actual conversion characteristic 003H 3FFH Actual conversion characteristic
Full-scale transition error
Ideal characteristic
Digital output
Digital output
3FEH
002H Ideal characteristic 001H
VFST
3FDH (measurement value) Actual conversion characteristic
Actual conversion characteristic
VOT (measurement value) VSS Analog input VCC
3FCH
VSS
Analog input
VCC
Linearity error
3FFH 3FEH 3FDH Actual conversion characteristic
Differential linearity error
Ideal characteristic (N+1)H Actual conversion characteristic
{1 LSB × N + VOT} Digital output VFST
(measurement value) NH
V(N+1)T
Digital output
VNT
004H 003H 002H 001H Actual conversion characteristic Ideal characteristic
(N-1)H
VNT
Actual conversion characteristic
(N-2)H
VOT (measurement value) VSS Analog input VCC VSS Analog input VCC
VNT - {1 LSB × N + VOT} Linearity error = of digital output N 1 LSB
V(N+1)T - VNT Differential linear error = -1 of digital output N 1 LSB
N
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N - 1)H to NH VOT (ideal value) = VSS + 0.5 LSB [V] VFST (ideal value) = VCC - 2 LSB [V]
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6. Flash Memory Program/Erase Characteristics
Parameter Sector erase time (2 Kbyte sector) Sector erase time (16 Kbyte sector) Byte writing time Program/erase cycle Power supply voltage at program/erase Flash memory data retention time *1: VCC = 5.5 V, TA = + 25°C, 0 cycle *2: This value is converted from the result of a technology reliability assessment. (The value is converted from the result of a high temperature accelerated test using the Arrhenius equation with the average temperature being + 85°C). Value Min — — — 100000 2.4 5*2 Typ 0.3*1 0.6*1 17 — — — Max 1.6 3.1 272 — 5.5 — Unit s s µs cycle V year Average TA = + 85°C Remarks The time of writing 00H prior to erasure is excluded. The time of writing 00H prior to erasure is excluded. System-level overhead is excluded.
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■ SAMPLE CHARACTERISTICS
• Power supply current temperature characteristics ICC − VCC TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2) Main clock mode with the external clock operating
20
FMP = 16 MHz FMP = 10 MHz FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz
ICC − TA VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2) Main clock mode with the external clock operating
20
FMP = 16 MHz FMP = 10 MHz
15
15
ICC[mA]
ICC[mA]
10
10
5
5
0 2 3 4 VCC[V] 5 6 7
0 −50
0
+50 TA[°C]
+100
+150
ICCS − VCC TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2) Main sleep mode with the external clock operating
10
FMP = 16 MHz FMP = 10 MHz FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz
ICCS − TA VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2) Main sleep mode with the external clock operating
10
FMP = 16 MHz FMP = 10 MHz
8
8
ICCS[mA]
ICCS[mA]
6
6
4
4
2
2
0 2 3 4 VCC[V] 5 6 7
0 −50
0
+50 TA[°C]
+100
+150
ICCL − VCC TA = +25°C, FMPL = 16 kHz (divided by 2) Subclock mode with the external clock operating
100
ICCL − TA VCC = 5.5 V, FMPL = 16 kHz (divided by 2) Subclock mode with the external clock operating
100
75
75
ICCL[μA]
50
ICCL[μA]
50
25
25
0 2 3 4 VCC[V] 5 6 7
0 −50
0
+50 TA[°C]
+100
+150
(Continued) DS702-00003-1v0-E 69
MB95560H/570H/580H Series
ICCLS − VCC TA = +25°C, FMPL = 16 kHz (divided by 2) Subsleep mode with the external clock operating
80 70 60 50 ICCLS[μA] ICCLS[μA] 40 30 20 10 0 2 3 4 VCC[V] 5 6 7
ICCLS − TA VCC = 5.5 V, FMPL = 16 kHz (divided by 2) Subsleep mode with the external clock operating
80 70 60 50 40 30 20 10 0 −50 0 +50 TA[°C] +100 +150
ICCT − VCC TA = +25°C, FMPL = 16 kHz (divided by 2) Watch mode with the external clock operating
20
ICCT − TA VCC = 5.5 V, FMPL = 16 kHz (divided by 2) Watch mode with the external clock operating
20
16
16
ICCT[μA]
8
ICCT[μA]
12
12
8
4
4
0 2 3 4 VCC[V] 5 6 7
0 −50 0 +50 TA[°C] +100 +150
ICTS − VCC TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2) Time-base timer mode with the external clock operating
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2 3 4 VCC[V] 5 6 7
FMP = 16 MHz FMP = 10 MHz FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz
ICTS − TA VCC = 5.5 V, FMP = 10, 16 kHz (divided by 2) Time-base timer mode with the external clock operating
1.4
FMP = 16 MHz FMP = 10 MHz
1.2 1.0 0.8 0.6 0.4 0.2 0.0 −50
ICTS[mA]
ICTS[mA]
0
+50 TA[°C]
+100
+150
(Continued)
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(Continued) ICCH − VCC TA = +25°C, FMPL = (stop) Substop mode with the external clock stopping
20
ICCH − TA VCC = 5.5 V, FMPL = (stop) Substop mode with the external clock stopping
20
15
15
ICCH[μA]
10
ICCH[μA] 2 3 4 VCC[V] 5 6 7
10
5
5
0
0 −50 0 +50 TA[°C] +100 +150
ICCMCR − VCC TA = +25°C, FMP = 4 MHz (no division) Main clock mode with the main CR clock operating
20
ICCMCR − TA VCC = 5.5 V, FMP = 4 MHz (no division) Main clock mode with the main CR clock operating
20
15
15
ICCMCR[mA]
10
ICCMCR[mA]
10
5
5
0 2 3 4 VCC[V] 5 6 7
0 −50 0 +50 TA[°C] +100 +150
ICCSCR − VCC TA = +25°C, FMPL = 50 kHz (divided by 2) Subclock mode with the sub-CR clock operating
200
ICCSCR − TA VCC = 5.5 V, FMPL = 50 kHz (divided by 2) Subclock mode with the sub-CR clock operating
200
150
150
ICCSCR[μA]
100
ICCSCR[μA]
100
50
50
0 2 3 4 VCC[V] 5 6 7
0 −50 0 +50 TA[°C] +100 +150
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• Input voltage characteristics VIHI − VCC and VILI − VCC TA = +25°C
5
VIHI VILI
VIHS − VCC and VILS − VCC TA = +25°C
5
VIHS VILS
4
4
VIHI/VILI[V]
2
VIHS/VILS[V] 2 3 4 VCC[V] 5 6 7
3
3
2
1
1
0
0 2 3 4 VCC[V] 5 6 7
VIHM − VCC and VILM − VCC TA = +25°C
5
VIHM VILM
4
VIHM/VILM[V]
3
2
1
0 2 3 4 VCC[V] 5 6 7
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• Output voltage characteristics (VCC − VOH1) − IOH TA = +25°C
1.0 1.0
(VCC − VOH2) − IOH TA = +25°C
0.8
0.8
VCC − VOH1[V]
0.6
VCC − VOH2[V] −6 IOH [mA] VCC = 2.4 V VCC = 2.7 V VCC = 3.5 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V −8 −10
0.6
0.4
0.4
0.2
0.2
0.0 0 −2 −4
0.0 0 −2 −4 IOH [mA] VCC = 2.4 V VCC = 2.7 V VCC = 3.5 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V −6 −8 −10
VOL1 − IOL TA = +25°C
1.0 0.6
VOL2 − IOL TA = +25°C
0.8
0.4 0.6 VOL1[V]
VOL2[V]
0.4 0.2
0.2
0.0 0 2 4 IOL [mA] VCC = 2.4 V VCC = 2.7 V VCC = 3.5 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V 6 8 10
0.0 0 2 4 IOL [mA] VCC = 2.4 V VCC = 2.7 V VCC = 3.5 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V 6 8 10
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• Pull-up characteristics RPULL − VCC TA = +25°C
250
200
RPULL[kΩ]
150
100
50
0 2 3 4 VCC[V] 5 6
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■ MASK OPTIONS
MB95F562H MB95F563H MB95F564H MB95F572H MB95F573H MB95F574H MB95F582H MB95F583H MB95F584H Fixed With dedicated reset input Without dedicated reset input MB95F562K MB95F563K MB95F564K MB95F572K MB95F573K MB95F574K MB95F582K MB95F583K MB95F584K
No.
Part Number
Selectable/Fixed 1 2 Reset
Low-voltage detection reset Without low-voltage detection reset With low-voltage detection reset
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MB95560H/570H/580H Series
■ ORDERING INFORMATION
Part Number MB95F562HWQN-G-JNE1 MB95F562HWQN-G-JNERE1 MB95F562KWQN-G-JNE1 MB95F562KWQN-G-JNERE1 MB95F563HWQN-G-JNE1 MB95F563HWQN-G-JNERE1 MB95F563KWQN-G-JNE1 MB95F563KWQN-G-JNERE1 MB95F564HWQN-G-JNE1 MB95F564HWQN-G-JNERE1 MB95F564KWQN-G-JNE1 MB95F564KWQN-G-JNERE1 MB95F562HPF-G-JNE2 MB95F562KPF-G-JNE2 MB95F563HPF-G-JNE2 MB95F563KPF-G-JNE2 MB95F564HPF-G-JNE2 MB95F564KPF-G-JNE2 MB95F562HPFT-G-JNE2 MB95F562KPFT-G-JNE2 MB95F563HPFT-G-JNE2 MB95F563KPFT-G-JNE2 MB95F564HPFT-G-JNE2 MB95F564KPFT-G-JNE2 MB95F582HWQN-G-JNE1 MB95F582HWQN-G-JNERE1 MB95F582KWQN-G-JNE1 MB95F582KWQN-G-JNERE1 MB95F583HWQN-G-JNE1 MB95F583HWQN-G-JNERE1 MB95F583KWQN-G-JNE1 MB95F583KWQN-G-JNERE1 MB95F584HWQN-G-JNE1 MB95F584HWQN-G-JNERE1 MB95F584KWQN-G-JNE1 MB95F584KWQN-G-JNERE1 MB95F582HPFT-G-JNE2 MB95F582KPFT-G-JNE2 MB95F583HPFT-G-JNE2 MB95F583KPFT-G-JNE2 MB95F584HPFT-G-JNE2 MB95F584KPFT-G-JNE2 MB95F582HPF-G-JNE2 MB95F582KPF-G-JNE2 MB95F583HPF-G-JNE2 MB95F583KPF-G-JNE2 MB95F584HPF-G-JNE2 MB95F584KPF-G-JNE2 MB95F572HPF-G-JNE2 MB95F572KPF-G-JNE2 MB95F573HPF-G-JNE2 MB95F573KPF-G-JNE2 MB95F574HPF-G-JNE2 MB95F574KPF-G-JNE2 76 Package
32-pin plastic QFN (LCC-32P-M19)
20-pin plastic SOP (FPT-20P-M09)
20-pin plastic TSSOP (FPT-20P-M10)
32-pin plastic QFN (LCC-32P-M19)
16-pin plastic TSSOP (FPT-16P-M08)
16-pin plastic SOP (FPT-16P-M23)
8-pin plastic SOP (FPT-8P-M08)
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ PACKAGE DIMENSION
32-pin plastic QFN Lead pitch Package width × package length Sealing method Mounting height Weight 0.50 mm 5.00 mm × 5.00 mm Plastic mold 0.80 mm MAX 0.06 g
(LCC-32P-M19)
32-pin plastic QFN (LCC-32P-M19)
5.00±0.10 (.197±.004)
3.50±0.10 (.138±.004)
5.00±0.10 (.197±.004)
INDEX AREA
3.50±0.10 (.138±.004) 0.25 (.010
+0.05 –0.07 +.002 –.003
)
(3-R0.20) ((3-R.008)) 0.50(.020) (TYP)
0.40±0.05 (.016±.002) 1PIN CORNER (C0.30(C.012))
0.75±0.05 (.030±.002) 0.02 (.001
+0.03 –0.02 +.001 –.001
(0.20(.008)) )
C
2009-2010 FUJITSU SEMICONDUCTOR LIMITED C32071S-c-1-2
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued)
DS702-00003-1v0-E
77
MB95560H/570H/580H Series
20-pin plastic SOP
Lead pitch Package width × package length Lead shape Lead bend direction Sealing method Mounting height
1.27 mm 7.50 mm × 12.70 mm Gullwing Normal bend Plastic mold 2.65 mm Max
(FPT-20P-M09)
20-pin plastic SOP (FPT-20P-M09)
#12.70±0.10(.500±.004)
20 11
Note 1) Pins width and pins thickness include plating thickness. Note 2) Pins width do not include tie bar cutting remainder. Note 3) # : These dimensions do not include resin protrusion.
0.25 .010 –.001
+0.07 –0.02 +.003
BTM E-MARK
#7.50±0.10 10.2 –0.20 (.295±.004) .402 +.016 –.008 INDEX Details of "A" part +0.13 2.52 –0.17 (Mounting height) +.005 .099 –.007
+0.40
1
10
+0.09 –0.05 +.004 –.002
"A" 0~8°
1.27(.050)
0.40 .016
0.25(.010)
M
0.80 –0.30
+0.47 +.019
.031 –.012
0.20±0.10 (.008±.004) (Stand off)
0.10(.004)
C
2008-2010 FUJITSU SEMICONDUCTOR LIMITED F20030S-c-1-2
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued)
78
DS702-00003-1v0-E
MB95560H/570H/580H Series
20-pin plastic TSSOP
Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight
0.65 mm 4.40 mm × 6.50 mm Gullwing Plastic mold 1.20 mm MAX 0.08 g
(FPT-20P-M10)
20-pin plastic TSSOP (FPT-20P-M10)
#6.50±0.10(.256±.004)
20 11
Note 1) Pins width and pins thickness include plating thickness. Note 2) Pins width do not include tie bar cutting remainder. Note 3) # : These dimensions do not include resin protrusion.
0.14 –0.04
+0.05 +.002
.006 –.002
BTM E-MARK #4.40±0.10 6.40±0.20 (.173±.004) (.252±.008)
INDEX
Details of "A" part 1.20(.047) (Mounting height) MAX "A" 0.24±0.04 (.009±.002) 0~8°
LEAD No.
1
10
0.65(.026)
0.60±0.15 (.024±.006) 0.10(.004)
0.10±0.05 (.004±.002) (Stand off)
C
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F20031S-c-1-2
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued)
DS702-00003-1v0-E
79
MB95560H/570H/580H Series
16-pin plastic TSSOP
Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight
0.65 mm 4.40 mm × 4.96 mm Gullwing Plastic mold 1.20 mm Max 0.06 g
(FPT-16P-M08)
16-pin plastic TSSOP (FPT-16P-M08)
*4.96±0.10(.195±.004)
16 9
Note 1) Pins width and pins thickness include plating thickness. Note 2) Pins width do not include tie bar cutting remainder. Note 3) * : These dimensions do not include resin protrusion.
0.145±0.045 (.0057±.0018)
INDEX
*4.40±0.10 6.40±0.20 (.173±.004) (.252±.008)
Details of "A" part
+0.10
1.10 –0.15 (Mounting height) +0.04 .043 –0.06 LEAD No.
1 8
0.65(.026)
"A" 0.24±0.08 (.009±.003) 0.13(.005)
M
0~8°
0.60±0.15 (.024±.006) 0.10(.004)
0.10±0.05 (.004±.002) (Stand off)
C
2007-2010 FUJITSU SEMICONDUCTOR LIMITED F16021S-c-1-5
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued)
80
DS702-00003-1v0-E
MB95560H/570H/580H Series
16-pin plastic SOP
Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight
1.27 mm 3.90 mm × 9.96 mm Gullwing Plastic mold 1.75 mm MAX 0.12 g
(FPT-16P-M23)
16-pin plastic SOP (FPT-16P-M23)
#9.96±0.10(.392±.004)
16 9
Note 1) Pins width and pins thickness include plating thickness. Note 2) Pins width do not include tie bar cutting remainder. Note 3) #: These dimensions do not include resin protrusion.
0.60 –0.15 +0.08 .024 –0.06
+0.20
8 ±2 BTM E-MARK INDEX #3.90±0.10 6.00±0.20 (.154±.004) (.236±.008) 0.40±0.10 (.016±.004)
8 ±2
(1.04 (.041))
1
8
0.40±0.10 (.016±.004) 0.65±0.10 (.026±.004) 1.45±0.20 (.057±.008)
1.60 –0.25 .063 –0.10
+0.15 +0.06
1.27(.050) 7 ±2
0.40 –0.04 (.016 +.004 ) –.002
+0.11
0.25(.010)
M
7 ±2
C
0.10(.004)
0.15 –0.05 .006 –0.02
+0.10
+0.04
2010 FUJITSU SEMICONDUCTOR LIMITED HMbF16-23Sc-1-1
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued)
DS702-00003-1v0-E
81
MB95560H/570H/580H Series
(Continued)
8-pin plastic SOP Lead pitch Package width × package length Lead shape Lead bend direction Sealing method Mounting height 1.27 mm 5.30 mm × 5.24 mm Gullwing Normal bend Plastic mold 2.10 mm Max
(FPT-8P-M08)
8-pin plastic SOP (FPT-8P-M08)
#5.24±0.10 (.206±.004)
8 5
Note 1) Pins width and pins thickness include plating thickness. Note 2) Pins width do not include tie bar cutting remainder. Note 3) # : These dimensions do not include resin protrusion.
"A" BTM E-MARK
INDEX
#5.30±0.10 (.209±.004)
7.80 .307
+0.45 –0.10 +.018 –.004
Details of "A" part 2.10(.083) MAX (Mounting height)
1 4
1.27(.050)
0.43±0.05 (.017±.002)
0.20±0.05 (.008±.002) 0~8°
0.10 –0.05
+0.15 +.006
0.75 –0.20
+0.10 +.004
.004 –.002 (Stand off)
.030 –.008
C
2008-2010 FUJITSU SEMICONDUCTOR LIMITED F08016S-c-1-2
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/
82
DS702-00003-1v0-E
MB95560H/570H/580H Series
MEMO
DS702-00003-1v0-E
83
MB95560H/570H/580H Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fss/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fsp/
Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department
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