MB95R203A

FUJITSU SEMICONDUCTOR DATA SHEET DS07-12630-2E 8-bit Proprietary Microcontrollers CMOS F2MC-8FX MB95R203A MB95R203A ■ DESCRIPTION The MB95R203A is general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions. Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller. ■ FEATURES • F2MC-8FX CPU core Instruction set optimized for controllers • Multiplication and division instructions • 16-bit arithmetic operations • Bit test branch instruction • Bit manipulation instructions etc. • Clock • Selectable Main clock source Main OSC clock (Up to 10 MHz, Maximum Machine clock frequency is 5 MHz) External clock (Up to 20 MHz, Maximum Machine clock frequency is 10 MHz) Internal main CR clock (Typ 1/8 MHz, Maximum Machine clock frequency is 8 MHz) • Selectable Sub clock source Sub OSC clock (32 kHz) Sub internal CR clock (Typ : 100 kHz, Min : 50 kHz, Max : 200 kHz) (Continued) Copyright©2010-2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2011.3 MB95R203A (Continued) • Timer • 8/16-bit compound timer • Time-base timer • Watch prescaler • UART/SIO • Offers clock asynchronous (UART) or clock synchronous (SIO) serial data transfer • Full duplex double buffer 2C •I • Built-in wake-up function • External interrupt • Interrupt by the edge detection (Select rising edge/falling edge/both edges) • Can be used to recover from low-power consumption modes (also called standby mode) • 8/10-bit A/D converter • 8-bit or 10-bit resolutions can be selected • Low-power consumption (standby) mode • Stop mode • Sleep mode • Watch mode • Time-base timer mode • I/O port : 16 • General-purpose I/O ports : CMOS I/O : 12, N-ch open drain : 4 • On-chip debug • 1 wire serial control • Support serial writing. (Asynchronous mode) • Hardware/Software watch dog timer • Built-in Hardware watchdog timer • Low voltage detection circuit (LVD) • Low voltage detection reset circuit • Low voltage detection interrupt circuit • Circuit to monitor FRAM power supply • Clock supervisor counter (CSV) • Built-in Clock supervise function • Programmable input voltage levels of port • CMOS input level / hysteresis input level • FRAM • Non-volatile memory • 8 Kbytes of FRAM integrated on-chip • FRAM memory security function • Protects the content of FRAM memory 2 DS07-12630-2E MB95R203A ■ PRODUCT OVERVIEW Part number Parameter ROM (FRAM) capacity RAM capacity Reset output Low voltage detection reset Number of basic instructions Instruction bit length Instruction length Data bit length Minimum instruction execution time Interrupt processing time General-purpose I/O ports : 16 CMOS I/O : 12, N-ch open drain : 4 Interrupt cycle : 0.256 ms to 8.3 s (at external 4 MHz) Reset generation cycle Main clock at 10 MHz : 105 ms (Min) Sub clock CR can be used as the Watch dog source clock. It can be used to replace three bytes of data. Able to transfer data using UART/SIO Variable data length (5/6/7/8-bit) , built-in baud rate generator Transfer rate (2400 bps to 125000 bps at 10 MHz) , full-duplex transfers with built-in double buffers NRZ type transfer format, error detection function LSB-first or MSB-first can be selected Capable of clock synchronous (SIO) or clock asynchronous (UART) serial data transfer Transmit and receive master/slave Bus function, arbitration function, transfer direction detection function Start condition repeated generation and detection functions Built-in timeout detection function 6 ch 8-bit or 10-bit resolution can be selected 2 ch 8/16-bit compound timer Can be configured as a 2 ch × 8-bit timer or 1 ch × 16-bit timer Built-in timer function, PWC function, PWM function and capture function Count clock : available from internal clocks (7 types) or external clocks With square wave output 6 ch External interrupt Interrupt by edge detection (Select rising edge/falling edge/both edges) Can be used to recover from standby modes Selectable from 4 kinds of low voltage detection levels Usable as a release function from standby mode (Continued) MB95R203A 8 Kbytes 496 bytes Yes Yes : 136 instructions : 8 bits : 1 to 3 bytes : 1, 8, and 16 bits : 100 ns (at machine clock 10 MHz) : 0.9 μs (at machine clock 10 MHz) CPU function Port Time-base timer Hardware/software Watchdog timer Wild registers UART/SIO I2C bus 8/10-bit A/D converter Low voltage interrupt DS07-12630-2E 3 MB95R203A (Continued) Part number Parameter On-chip debug Watch prescaler MB95R203A 1 wire serial control Support serial writing. (Asynchronous mode) Eight different time intervals can be selected. Non-volatile memory Number of read/write cycles : 1015 times Data retention characteristics : 10 years ( + 55 °C) Read security function Function to monitor FRAM power supply Sleep mode, Stop mode, Watch mode, time-base timer mode DIP-24, SOP-20 FRAM Standby Mode Package 4 DS07-12630-2E MB95R203A ■ PIN ASSIGNMENT (TOP VIEW) X0 NC X1 Vss X1A/PG2 X0A/PG1 Vcc SCL/P65 RST/PF2 TO10/P62 NC TO11/P63 1 2 3 4 5 6 7 8 9 10 11 12 24pin (DIP-24) *The number of usable pins is 20. 24 23 22 21 20 19 18 17 16 15 14 13 P12/EC0/DBG NC P07/INT07 P06/INT06/TO01 P05/INT05/AN05/TO00/HCLK2 P04/INT04/AN04/UI/HCLK1/EC0 P03/INT03/AN03/UO P02/INT02/AN02/UCK P01/AN01 P00/AN00 NC P64/EC1/SDA (DIP-24P-M07) (TOP VIEW) X0 X1 Vss X1A/PG2 X0A/PG1 Vcc SCL/P65 RST/PF2 TO10/P62 TO11/P63 1 2 3 4 5 6 7 8 9 10 20pin (SOP-20) 20 19 18 17 16 15 14 13 12 11 P12/EC0/DBG P07/INT07 P06/INT06/TO01 P05/INT05/AN05/TO00/HCLK2 P04/INT04/AN04/UI/HCLK1/EC0 P03/INT03/AN03/UO P02/INT02/AN02/UCK P01/AN01 P00/AN00 P64/EC1/SDA (FPT-20P-M09) DS07-12630-2E 5 MB95R203A ■ PIN DESCRIPTION Pin no. DIP24 SOP20 1 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 Pin name X0 X1 Vss PG2/X1A PG1/X0A Vcc P65/SCL PF2/RST I/O Circuit type* B B ⎯ C C ⎯ I A Function Main clock input oscillation pin Main clock input/output oscillation pin Power supply pin (GND) General-purpose I/O port This pin is also used as Sub clock input/output oscillation pin. General-purpose I/O port This pin is also used as Sub clock input oscillation pin. Power supply pin General-purpose I/O port This pin is also used as I2C clock I/O. General-purpose I/O port This pin is also used as reset pin General-purpose I/O port High current port This pin is also used as 8/16-bit compound timer ch.1 output. General-purpose I/O port High current port This pin is also used as 8/16-bit compound timer ch.1 output. General-purpose I/O port This pin is also used as I2C data I/O. This pin is also used as 8/16-bit compound timer ch.1 clock input. General-purpose I/O port This pin is also used as A/D converter analog input. General-purpose I/O port This pin is also used as A/D converter analog input. General-purpose I/O port This pin is also used as external interrupt input. This pin is also used as A/D converter analog input. This pin is also used as UART/SIO clock I/O. General-purpose I/O port This pin is also used as external interrupt input. This pin is also used as A/D converter analog input. This pin is also used as UART/SIO data output. General-purpose I/O port This pin is also used as external interrupt input. This pin is also used as A/D converter analog input. This pin is also used as UART/SIO data input. This pin is also used as 8/16-bit compound timer ch.0 clock input. (Continued) 10 9 P62/TO10 D 12 10 P63/TO11 D 13 11 P64/SDA/EC1 I 15 16 12 13 P00/AN00 P01/AN01 E E 17 14 P02/INT02/AN02/ UCK E 18 15 P03/INT03/AN03/ UO E 19 16 P04/INT04/AN04/ UI/HCLK1/EC0 F 6 DS07-12630-2E MB95R203A (Continued) Pin no. DIP24 SOP20 Pin name I/O Circuit type* Function General-purpose I/O port High current port This pin is also used as external interrupt input. This pin is also used as A/D converter analog input. The pins are also used as 8/16-bit compound timer ch.0 output. This pin is also used as the external clock input. General-purpose I/O port High current port This pin is also used as external interrupt input. This pin is also used as 8/16-bit compound timer ch.0 output. General-purpose I/O port This pin is also used as external interrupt input. General-purpose I/O port This pin is also used as DBG input pin. This pin is also used as 8/16-bit compound timer ch.0 clock input. Internal connect pin. Be sure this pin is left open. 20 17 P05/INT05/AN05/ TO00/HCLK2 E 21 18 P06/INT06/TO01 G 22 19 P07/INT07 G 24 20 P12/EC0/DBG H 2, 11, 14, 23 ⎯ NC ⎯ * : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”. DS07-12630-2E 7 MB95R203A ■ I/O CIRCUIT TYPE Type A Circuit Reset input / Hysteresis input Reset output / Digital output N-ch Remarks • N-ch open drain output • Hysteresis input • Reset output B X1 X0 Clock input • Oscillation circuit • High-speed side Feedback resistance : approx. 1 MΩ • Hysteresis input Standby control C R P-ch P-ch Port select Pull-up control Digital output N-ch Digital output Standby control Hysteresis input Clock input • Oscillation circuit • Low-speed side Feedback resistance : approx. 10 MΩ • CMOS output • Hysteresis input • With pull-up control X1A X0A Standby control / Port select Clock input Port select R Digital output P-ch N-ch Pull-up control Digital output Digital output Standby control Hysteresis input D P-ch Digital output Digital output • CMOS output • Hysteresis input N-ch Standby control Hysteresis input (Continued) 8 DS07-12630-2E MB95R203A (Continued) Type E R P-ch P-ch N-ch Circuit Pull-up control Digital output Digital output Remarks • CMOS output • Hysteresis input • With pull-up control Analog input A/D control Standby control Hysteresis input F R P-ch P-ch N-ch Pull-up control Digital output Digital output • • • • CMOS output Hysteresis input CMOS input With pull-up control Analog input A/D control Standby control Hysteresis input CMOS input G R P-ch P-ch N-ch Pull-up control Digital output Digital output Standby control Hysteresis input • CMOS output • Hysteresis input • With pull-up control H Hysteresis input Digital output N-ch • N-ch open drain output • Hysteresis input I Digital output N-ch • N-ch open drain output • CMOS input • Hysteresis input CMOS input Standby control Hysteresis input DS07-12630-2E 9 MB95R203A ■ NOTES ON DEVICE HANDLING • Preventing Latch-up Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used. Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC pin and VSS pin. When latch-up occurs, power supply current increases rapidly and might thermally damage elements. • Stable Supply Voltage Supply voltage should be stabilized. A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range of the Vcc power-supply voltage. For stabilization, in principle, keep the variation in Vcc ripple (p-p value) in a commercial frequency range (50 Hz / 60 Hz) not to exceed 10% of the standard Vcc value and suppress the voltage variation so that the transient variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched. • Precautions for Use of External Clock Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wakeup from sub clock mode or stop mode. • Do not use a sample used in program development as mass-produced product. 10 DS07-12630-2E MB95R203A ■ PIN CONNECTION • Treatment of Unused Input Pin Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. If there is unused output pin, make it to open. • Power Supply Pins In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 μF between VCC and VSS near this device. • DBG Pin Connect the DBG pin directly to external Pull-up. To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the DBG pin to VCC or VSS pins. The DBG pin should not stay at “L” level after power-on until the reset output is released. • RST Pin Connect the RST pin directly to Pull-up. To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the RST pin to VCC or VSS pins. The RST/PF2 pin functions as the reset input/output pin after power-on. In addition, the reset output can be enabled by the RSTOE bit of the SYSC register, and the reset input function or the general purpose I/O function can be selected by the RSTEN bit of the SYSC register. • Example of DBG / RST connection diagram R DBG R RST Pull-up resistor recommended resistance For DBG pin : R = 4.7 kΩ For RST pin : R = 10 kΩ DS07-12630-2E 11 MB95R203A ■ NOTES ON ON-CHIP DEBUG • Although the [Upload Flash Memory] button on SOFTUNETM* Workbench is enabled, clicking it does not start the actual processing. • When you click on the [Erase Flash Memory] button on SOFTUNE Workbench, data is overwritten into the FRAM area, as shown below. Address Data to be overwritten F554H FAAAH FFBCH FFBDH Entire FRAM except the above 55H A0H Indeterminate Indeterminate FFH • When you click on the [Erase Flash Memory] and the [Target load] button on SOFTUNE Workbench, data in the I/O area described below is undefined. Address Data to be overwritten 0070H 0071H Indeterminate Indeterminate • Be very careful not to apply voltages to the pins PF2/RST in excess of the absolute maximum ratings. Especially when handling devices in the environment compatible to the package, such as MB95200H/ 210H and so on, the voltage may be erroneously applied to the pins PF2/RST in excess of the maximum rating and it may cause thermal breakdown of the device. * : SOFTUNE is a trademark of Fujitsu Semiconductor Limited, Japan. 12 DS07-12630-2E MB95R203A ■ BLOCK DIAGRAM F2MC-8FX CPU PF2*1/RST*2 X1 X0 PG2/X1A*2 PG1/X0A*2 Reset LVD FRAM (8 Kbytes) with security RAM (496 bytes) Oscillator circuit CR Oscillator Clock control P12*1/DBG On-chip debug Wild register P02/INT02 to P07/INT07 P65*1/SCL*1 P64*1/SDA*1 (P02/UCK) (P04/UI) (P03/UO) External interrupt I 2C 8/10-bit A/D converter UART/SIO 8/16-bit compound timer (1) 8/16-bit compound timer (0) (P05*3/TO00) (P06*3/TO01) P12/EC0(P04/EC0) P62*3/TO10 P63*3/TO11 (P64/EC1) (P00/AN00 to P05/AN05) Port VCC VSS *1 : P12, P64, P65 and PF2 are N-ch open drain. *2 : Software option *3 : P05, P06, P62 and P63 are high current ports. Port DS07-12630-2E 13 MB95R203A ■ CPU CORE Memory space Memory space of the MB95R203A is 64 Kbytes and consists of I/O area, data area, and program area. The memory space includes special-purpose areas such as the general-purpose registers and vector table. Memory map of the MB95R203A shown below. • Memory Map MB95R203A 0000H I/O 0080H 0090H RAM 496 Byte 0100H Register 0200H 0280H 0F80H 1000H Extension I/O - E000H FRAM 8 KB FFFFH 14 DS07-12630-2E MB95R203A ■ I/O MAP Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH to 0015H 0016H 0017H 0018H to 0027H 0028H 0029H 002AH 002BH 002CH 002DH to 0034H 0035H 0036H 0037H 0038H 0039H Register abbreviation PDR0 DDR0 PDR1 DDR1 ⎯ WATR ⎯ SYCC STBC RSRR TBTC WPCR WDTC SYCC2 ⎯ PDR6 DDR6 ⎯ PDRF DDRF PDRG DDRG PUL0 ⎯ PULG T01CR1 T00CR1 T11CR1 T10CR1 Register name Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register (Disabled) Oscillation stabilization wait time setting register (Disabled) System clock control register Standby control register Reset source register Time-base timer control register Watch timer control register Watchdog timer control register System clock control register 2 (Disabled) Port 6 data register Port 6 direction register (Disabled) Port F data register Port F direction register Port G data register Port G direction register Port 0 pull-up register (Disabled) Port G pull-up register 8/16-bit compound timer 01 control status register 1 ch.0 8/16-bit compound timer 00 control status register 1 ch.0 8/16-bit compound timer 11 control status register 1 ch.1 8/16-bit compound timer 10 control status register 1 ch.1 R/W R/W R/W R/W R/W ⎯ R/W ⎯ R/W R/W R R/W R/W R/W R/W ⎯ R/W R/W ⎯ R/W R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W Initial value 00000000B 00000000B 00000000B 00000000B ⎯ 11111111B ⎯ XXXXXX11B 00000XXXB XXXXXXXXB 00000000B 00000000B 00000000B XX100011B ⎯ 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B (Continued) DS07-12630-2E 15 MB95R203A Address 003AH to 0046H 0047H 0048H 0049H 004AH 004BH 004CH to 0055H 0056H 0057H 0058H 0059H 005AH 005BH to 005FH 0060H 0061H 0062H 0063H 0064H 0065H 0066H 0067H 0068H 0069H 006AH 006BH 006CH 006DH 006EH 006FH 0070H 0071H Register abbreviation ⎯ LVDCR ⎯ EIC10 EIC20 EIC30 ⎯ SMC10 SMC20 SSR0 TDR0 TDR0 ⎯ IBCR00 IBCR10 IBSR0 IDDR0 IAAR0 ICCR0 FSCR FRAC FABH FABL FASH FASL ADC1 ADC2 ADDH ADDL FVAH FVAL 2 2 Register name (Disabled) Low voltage detection interrupt control register (Disabled) External interrupt circuit control register ch.2/ch.3 External interrupt circuit control register ch.4/ch.5 External interrupt circuit control register ch.6/ch.7 (Disabled) UART/SIO serial mode control register 1 UART/SIO serial mode control register 2 UART/SIO serial status and data register UART/SIO serial output data register UART/SIO serial input data register (Disabled) I2C bus control register 0 I C bus control register 1 I C bus status register I C data register I C address register I C clock control register FRAM status/control register FRAM register access control register FRAM write permit start address register (H) FRAM write permit start address register (L) FRAM write permit area size register (H) FRAM write permit area size register (L) 8/10-bit A/D converter control register 1 8/10-bit A/D converter control register 2 8/10-bit A/D converter data register (upper byte) 8/10-bit A/D converter data register (lower byte) FRAM violation address register (H) FRAM violation address register (L) 2 2 2 R/W ⎯ R/W ⎯ R/W R/W R/W ⎯ R/W R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R Initial value ⎯ 00000000B ⎯ 00000000B 00000000B 00000000B ⎯ 00000000B 00100000B 00000001B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 11111111B 11111111B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B XXXXXXXXB XXXXXXXXB (Continued) 16 DS07-12630-2E MB95R203A Address 0072H to 0075H 0076H 0077H 0078H 0079H 007AH 007BH 007CH 007DH 007EH 007FH 0F80H 0F81H 0F82H 0F83H 0F84H 0F85H 0F86H 0F87H 0F88H 0F89H to 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H 0F98H Register abbreviation ⎯ WREN WROR ⎯ ILR0 ILR1 ILR2 ILR3 ILR4 ILR5 ⎯ WRARH0 WRARL0 WRDR0 WRARH1 WRARL1 WRDR1 WRARH2 WRARL2 WRDR2 ⎯ T01CR0 T00CR0 T01DR T00DR TMCR0 T11CR0 T10CR0 Register name (Disabled) Wild register address compare enable register Wild register data test setting register Register bank pointer (RP) , Mirror of direct bank pointer (DP) Interrupt level setting register 0 Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt level setting register 4 Interrupt level setting register 5 (Disabled) Wild register address setting register (upper byte) ch.0 Wild register address setting register (lower byte) ch.0 Wild register data setting register ch.0 Wild register address setting register (upper byte) ch.1 Wild register address setting register (lower byte) ch.1 Wild register data setting register ch.1 Wild register address setting register (upper byte) ch.2 Wild register address setting register (lower byte) ch.2 Wild register data setting register ch.2 (Disabled) 8/16-bit compound timer 01 control status register 0 ch.0 8/16-bit compound timer 00 control status register 0 ch.0 8/16-bit compound timer 01 data register ch.0 8/16-bit compound timer 00 data register ch.0 8/16-bit compound timer 00/01 timer mode control register ch.0 8/16-bit compound timer 11 control status register 0 ch.1 8/16-bit compound timer 10 control status register 0 ch.1 R/W ⎯ R/W R/W ⎯ R/W R/W R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W R/W R/W R/W ⎯ R/W R/W R/W R/W R/W R/W R/W Initial value ⎯ 00000000B 00000000B ⎯ 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued) DS07-12630-2E 17 MB95R203A (Continued) Address 0F99H 0F9AH 0F9BH 0F9CH to 0FBDH 0FBEH 0FBFH 0FC0H to 0FC2H 0FC3H 0FC4H to 0FE3H 0FE4H 0FE5H 0FE6H 0FE7H 0FE8H 0FE9H 0FEAH 0FEBH 0FECH 0FEDH 0FEEH 0FEFH to 0FFFH Register abbreviation T11DR T10DR TMCR1 ⎯ PSSR0 BRSR0 ⎯ AIDRL ⎯ CRTH CRTL LVDCR2 ⎯ SYSC CMCR CMDR WDTH WDTL ⎯ ILSR ⎯ Register name 8/16-bit compound timer 11 data register ch.1 8/16-bit compound timer 10 data register ch.1 8/16-bit compound timer 10/11 timer mode control register ch.1 (Disabled) UART/SIO prescaler select register UART/SIO baud rate setting register (Disabled) A/D input disable register lower (Disabled) CR-trimming register upper CR-trimming register lower Low voltage detection control register (Disabled) System control register Clock monitor control register Clock monitor data register Watchdog ID register upper Watchdog ID register lower (Disabled) Input level select register (Disabled) R/W R/W R/W R/W ⎯ R/W R/W ⎯ R/W ⎯ R/W R/W R/W ⎯ R/W R/W R/W R/W R/W ⎯ R/W ⎯ Initial value 00000000B 00000000B 00000000B ⎯ 00000000B 00000000B ⎯ 00000000B ⎯ 1XXXXXXXB 000XXXXXB 00000010B ⎯ 11000-11B --000000B 00000000B XXXXXXXXB XXXXXXXXB ⎯ --00-0--B ⎯ • R/W access symbols R/W : Readable / Writable R : Read only W : Write only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value. 18 DS07-12630-2E MB95R203A ■ INTERRUPT SOURCE TABLE Interrupt source External interrupt ch.4 External interrupt ch.5 External interrupt ch.2 External interrupt ch.6 External interrupt ch.3 External interrupt ch.7 UART/SIO (transmit) UART/SIO (receive) 8/16-bit compound timer ch.0 (Lower) 8/16-bit compound timer ch.0 (Upper) ⎯ ⎯ FRAM (UDEF, PROT) ⎯ ⎯ ⎯ ⎯ 8/16-bit compound timer ch.1 (Upper) ⎯ I2C complete/error I2C stop/AL/wakeup Low voltage detection interrupt 8/10-bit A/D converter Time-base timer Watch prescaler ⎯ 8/16-bit compound timer ch.1 (Lower) FRAM (AREA) Interrupt request number IRQ00 IRQ01 IRQ02 IRQ03 IRQ04 IRQ05 IRQ06 IRQ07 RQ08 IRQ09 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 IRQ20 IRQ21 IRQ22 IRQ23 Vector table address Upper FFFAH FFF8H FFF6H FFF4H FFF2H FFF0H FFEEH FFECH FFEAH FFE8H FFE6H FFE4H FFE2H FFE0H FFDEH FFDCH FFDAH FFD8H FFD6H FFD4H FFD2H FFD0H FFCEH FFCCH Lower FFFBH FFF9H FFF7H FFF5H FFF3H FFF1H FFEFH FFEDH FFEBH FFE9H FFE7H FFE5H FFE3H FFE1H FFDFH FFDDH FFDBH FFD9H FFD7H FFD5H FFD3H FFD1H FFCFH FFCDH Bit name of interrupt level setting register L00 [1 : 0] L01 [1 : 0] L02 [1 : 0] L03 [1 : 0] L04 [1 : 0] L05 [1 : 0] L06 [1 : 0] L07 [1 : 0] L08 [1 : 0] L09 [1 : 0] L10 [1 : 0] L11 [1 : 0] L12 [1 : 0] L13 [1 : 0] L14 [1 : 0] L15 [1 : 0] L16 [1 : 0] L17 [1 : 0] L18 [1 : 0] L19 [1 : 0] L20 [1 : 0] L21 [1 : 0] L22 [1 : 0] L23 [1 : 0] Low Priority order of interrupt sources of the same level (occurring simultaneously) High DS07-12630-2E 19 MB95R203A ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Power supply voltage*1 Input voltage*1 Output voltage* 1 Symbol Vcc VI VO IOL1 IOL2 Rating Min Max Vss − 0.3 Vss + 4.0 Vss − 0.3 Vss + 4.0 Vss − 0.3 Vss + 4.0 ⎯ 15 15 Unit V V V mA *2 *2 Remarks “L” level maximum output current Other than P05, P06, P62 and P63 P05, P06, P62 and P63 Other than P05, P06, P62 and P63 Average output current = operating current × operating ratio (1pin) P05, P06, P62 and P63 Average output current = operating current × operating ratio (1pin) IOLAV1 “L” level average current IOLAV2 ⎯ 4 mA 12 “L” level total maximum output current “L” level total average output current “H” level maximum output current ΣIOL ΣIOLAV IOH1 IOH2 ⎯ ⎯ ⎯ 100 mA Total average output current = mA operating current × operating ratio (Total of pins) mA Other than P05, P06, P62 and P63 P05, P06, P62 and P63 Other than P05, P06, P62 and P63 Average output current = operating current × operating ratio (1pin) P05, P06, P62 and P63 Average output current = operating current × operating ratio (1pin) 50 −15 −15 −4 IOHAV1 “H” level average current IOHAV2 ⎯ mA −8 “H” level total maximum output current “H” level total average output current Power consumption Operating temperature Storage temperature ΣIOH ΣIOHAV Pd TA Tstg ⎯ ⎯ ⎯ −40 −40 −100 −50 320 + 85 + 85 mA Total average output current = mA operating current × operating ratio (Total of pins) mW °C °C *1 : The parameter is based on VSS = 0.0 V. *2 : VI and Vo should not exceed VCC + 0.3 V. VI must not exceed the rating voltage. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 20 DS07-12630-2E MB95R203A 2. Recommended Operating Conditions (VSS = 0.0 V) Parameter Symbol Value Min 1.8* Power supply voltage Vcc 2.7 2.7 Operating temperature TA −40 +5 Max 3.6 3.6 3.6 +85 +35 °C °C V Unit Remarks In normal operating In A/D converter operating On-chip debug mode Other than on-chip debug mode On-chip debug mode * : The normal operation is performed from 1.8 V to the low voltage detection of the FRAM power supply monitor, or from the release voltage of the FRAM power supply monitor to 1.8 V. Reset is generated during the period that the low voltage detection reset has been detected. As for the low voltage detection, see “(8) Low Voltage Detection” in “4. AC Characteristics”. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. DS07-12630-2E 21 MB95R203A 3. DC Characteristics (Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Condition Value Min 0.7 VCC Typ ⎯ Max VCC + 0.3 Unit Remarks When CMOS input level (Hysteresis input) is selected When CMOS input level (Hysteresis input) is selected VIH1 P04 *1 V VIH2 “H” level input voltage VIHS1 P64, P65 P00 to P07, P12, P62, P63, PG1, PG2 P64, P65 PF2 P04, P64, P65 P00 to P07, P12, P62 to P65, PG1, PG2 PF2 P12, P64, P65, PF2 *1 0.7 VCC ⎯ VCC + 0.3 V *1 0.8 VCC ⎯ ⎯ ⎯ ⎯ VCC + 0.3 VCC + 0.3 VCC + 0.3 0.3 VCC V Hysteresis input VIHS2 VIHM VIL “L” level input voltage *1 ⎯ *1 0.8 VCC 0.8 VCC VSS − 0.3 V V V Hysteresis input Hysteresis input When CMOS input level (Hysteresis input) is selected VILS *1 ⎯ ⎯ VSS − 0.3 VSS − 0.3 VSS − 0.3 ⎯ ⎯ ⎯ 0.2 VCC V Hysteresis input VILM Open-drain output application voltage 0.2 VCC VCC + 0.3 V Hysteresis input VD V “H” level output voltage VOH1 Output pins other than P05, P06, IOH = −4.0 mA P62 to P65, PF2, P12 P05, P06, P62, P63 Output pins other than P05, P06, P62, P63 P05, P06, P62, P63 IOH = −8.0 mA 2.4 ⎯ ⎯ V VOH2 2.4 ⎯ ⎯ V “L” level output voltage VOL1 IOL = 4.0 mA ⎯ ⎯ 0.4 V VOL2 IOL = 12.0 mA ⎯ ⎯ 0.4 V (Continued) 22 DS07-12630-2E MB95R203A (Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to +85 °C) Parameter Input leak current (Hi-Z output leak current) Open-drain output leak current Pull-up resistance Input capacitance Symbol Pin name Other than ports P64, P65 Condition Value Min −5 Typ ⎯ Max +5 Unit Remarks When pull-up resistance is disabled ILI 0.0 V < VI < VCC μA ILIOD P64, P65 0.0 V < VI < VCC VI = 0.0 V f = 1 MHz FCH = 20 MHz, FMP = 10 MHz Main clock mode (divided by 2) FCH = 20 MHz, FMP = 10 MHz Main sleep mode (divided by 2) TA = +25 °C −4 ⎯ + 10 μA When pull-up resistance is enabled RPULL P00 to P07, PG1, PG2 Other than Vcc, Vss 16.5 ⎯ ⎯ ⎯ 33 80 kΩ pF mA mA CIN 5 2.3 4.5 15 3.1 6 ICC At A/D conversion ICCS*3 ⎯ 1.1 1.7 mA ICCL Vcc (External clock operation) FCL = 32 kHz, FMPL = 16 kHz Sub clock mode (divided by 2) TA = +25 °C FCL = 32 kHz, FMPL = 16 kHz Sub sleep mode (divided by 2) TA = +25 °C FCL = 32 kHz, Watch mode Main stop mode TA = +25 °C FCRH = 1 MHz, FMP = 1 MHz Main CR clock mode Sub CR clock mode (divided by 2) TA = +25 °C ⎯ 52 280 μA Power supply current*2 ICCLS*3 ⎯ 15 260 μA ICCT*3 ⎯ 15 240 μA ICCMCR Vcc ICCSCR ⎯ 0.55 ⎯ mA ⎯ 62 320 μA (Continued) DS07-12630-2E 23 MB95R203A (Continued) (Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name Condition FCH = 10 MHz, Time-base timer mode TA = +25 °C Sub stop mode TA = +25 °C Consumption current using a low voltage interrupt circuit only Current consumption using a low voltage detection reset circuit and an FRAM power supply monitor circuit only Current consumption of internal main CR oscillator At oscillating 100 kHz current consumption of internal sub CR oscillator Value Min ⎯ Typ Max Unit Remarks Parameter ICCTS*3 ICCH*3 Vcc (External clock operation) 0.5 0.9 mA ⎯ 11 110 μA ILVD1 ⎯ 5 10 μA Power supply current*2 ILVD2 VCC ⎯ 25 50 μA ICRH ⎯ 70 100 μA ICRL ⎯ 9 20 μA *1 : P04, P64, P65 can switch the input level to either the “CMOS input level” or “hysteresis input level”. The switching of the input level can be set by the input level selection register (ILSR) . *2 : • The power-supply current is determined by the external clock. when Internal CR are selected, the powersupply current will be a value of adding current consumption of internal CR oscillator (ICRH, ICRL) to the specified value. In on-chip debug mode, the CR oscillator (ICRH) and the low-voltage detection circuit are always enabled, and current consumption therefore increases accordingly. • Refer to “(1) Clock Timing” in “4. AC Characteristics” for FCH and FCL. • Refer to “(2) Source Clock/Machine Clock” in “4. AC Characteristics” for FMP and FMPL. *3 : When a low voltage detection circuit stop bit (LVDCR2: LVDSTP set) is not set to “1”, the power supply current will be the sum of the current consumption value for a low voltage detection circuit (ILVD2) and the specified value. 24 DS07-12630-2E MB95R203A 4. AC Characteristics (1) Clock Timing (Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to +85 °C) Parameter SymCondiPin name bol tion X0, X1 FCH X0, X1, HCLK1, HCLK2 ⎯ Value Min 1 Typ ⎯ ⎯ 1 ⎯ 32.768 32.768 100 ⎯ ⎯ 30.5 ⎯ Max 10 Unit MHz Remarks When the main oscillation circuit is used When the main external clock is used 1 0.96 20 1.04 8.8 (TBD) ⎯ ⎯ 200 1000 MHz Clock frequency FCRH 7.2 (TBD) ⎯ When the main internal MHz CR clock is used ( + 5 °C ≤ TA ≤ + 35 °C) MHz kHz kHz ns When the sub oscillation circuit is used When the sub external clock is used When the sub internal CR clock is used When the main oscillation circuit is used When the main external clock is used When using sub clock When the external clock is used, the duty ratio should range between 40% and 60% When the external clock is used When the main internal CR clock is used When the sub internal CR clock is used FCL X0A, X1A ⎯ FCRL ⎯ X0, X1 50 100 ⎯ 50 ⎯ 20 Clock cycle time tHCYL X0, X1, HCLK1, HCLK2 X0A, X1A X0, HCLK1, HCLK2 X0A X0, X0A, HCLK1, HCLK2 ⎯ ⎯ 1000 ⎯ ⎯ ⎯ ns μs ns tLCYL tWH1 Input clock pulse width tWL1 tWH2 tWL2 Input clock rise time and fall time tCR tCF tCRHWK tCRLWK ⎯ ⎯ ⎯ ⎯ 15.2 μs ⎯ ⎯ ⎯ 5 ns μs μs Internal CR oscillation start time 10 50 DS07-12630-2E 25 MB95R203A tHCYL tWH1 tCR tCF 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC tWL1 X0, HCLK1, HCLK2 • Figure of main clock input port external connection When using a crystal or Ceramic oscillator When using external clock X0 X1 FCH X0 X1 Open FCH tLCYL tWH2 tCR tCF 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC tWL2 X0A • Figure of sub clock input port external connection When using a crystal or Ceramic oscillator When using external clock X0A X1A FCL X0A X1A Open FCL 26 DS07-12630-2E MB95R203A (2) Source Clock/Machine Clock (Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Value Min 100 Source clock cycle time*1 (Clock before division) Typ ⎯ Max 2000 Unit Remarks When using main external clock Min : FCH = 20 MHz, divided by 2 Max : FCH = 1 MHz, divided by 2 When using main CR oscillation clock Min : FCRH = 8 MHz Max : FCRH = 1 MHz When using sub oscillation clock FCL = 32.768 kHz, divided by 2 When using sub oscillation clock FCRL = 100 kHz, divided by 2 ns tSCLK ⎯ 125 ⎯ ⎯ ⎯ 61 20 ⎯ ⎯ 16.384 50 ⎯ 1000 ⎯ ⎯ 10 8 ⎯ ⎯ 32000 ns μs μs FSP Source clock frequency FSPL ⎯ 0.5 1 ⎯ ⎯ 100 MHz When using main oscillation clock MHz When using main CR oscillation clock kHz When using sub oscillation clock kHz When using sub CR clock ns When using main oscillation clock Min : FSP = 10 MHz, no division Max : FSP = 0.5 MHz, divided by 16 When using main CR clock Min : FSP = 10 MHz, no division Max : FSP = 1 MHz, divided by 16 When using sub oscillation clock Min : FSPL = 16.384 kHz, no division Max : FSPL = 16.384 kHz, divided by 16 When using sub CR clock Min : FSPL = 50 kHz, no division Max : FSPL = 50 kHz, divided by 16 Machine clock cycle time*2 (Minimum instruction execution time) 100 tMCLK ⎯ 61 ⎯ 16000 ns ⎯ 976.5 μs 20 0.031 ⎯ FMPL 0.0625 1.024 3.125 ⎯ ⎯ ⎯ ⎯ ⎯ 320 10 8 50 μs FMP Machine clock frequency MHz When using main oscillation clock MHz When using main CR clock kHz When using sub CR clock 16.384 kHz When using sub oscillation clock *1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes the machine clock. Further, the source clock can be selected as follows. • Main clock divided by 2 • Main CR clock • Sub clock divided by 2 • Sub CR clock divided by 2 *2 : Operation clock of the microcontroller. Machine clock can be selected as follows. • Source clock (no division) • Source clock divided by 4 • Source clock divided by 8 • Source clock divided by 16 DS07-12630-2E 27 MB95R203A • Outline of clock generation block FCH (main oscillation) FCRH (Internal main CR clock) FCL (sub oscillation) Divided by 2 Division Circuit x1 x 1/4 x 1/8 x 1/16 Divided by 2 Divided by 2 SCLK (source clock) MCLK (machine clock) FCRL (Internal sub CR clock) Clock mode select bit (SYCC2:RCS1, RCS0) • Operating voltage - Operating frequency (When TA = − 40 °C to + 85 °C) (Without on chip debug function) 3.6 Operating voltage (V) A/D converter operation range 2.7 1.8 16 kHz 10 MHz Source clock frequency (FSP/FSPL) • Operating voltage - Operating frequency ( TA = + 5 °C to + 35 °C) (With on chip debug function) 3.6 Operating voltage (V) A/D converter operation range 2.7 16 kHz 10 MHz Source clock frequency (FSP) 28 DS07-12630-2E MB95R203A (3) External Reset (Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Value Min 2 tMCLK*1 RST “L” level pulse width tRSTL Oscillation time of oscillator*2 + 100 100 *1 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. *2 : Oscillation time of oscillator is the time that the amplitude reaches 90%. In the crystal oscillator, the oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of μs and several ms. In the external clock, the oscillation time is 0 ms. Max ⎯ ⎯ ⎯ Unit ns μs μs Remarks At normal operating At stop mode, sub clock mode, sub sleep mode, and watch mode At time-base timer mode • At normal operating tRSTL RST 0.2 VCC 0.2 VCC • At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on RST 90% of amplitude X0 Internal operating clock tRSTL 0.2 VCC 0.2 VCC 100 μs Oscillation time of Oscillation stabilization wait time oscillator Internal reset Execute instruction DS07-12630-2E 29 MB95R203A (4) Power-on Reset (Vss = 0.0 V, TA = −40 °C to +85 °C) Parameter Power supply rising time Power supply cutoff time Symbol tR tOFF Conditions ⎯ ⎯ Value Min 0.1 1 Max 50 ⎯ Unit ms ms Waiting time until power-on Remarks tR 1.6 V tOFF VCC 0.2 V 0.2 V 0.2 V Note: A sudden change the power supply voltage may activate the power-on reset function. When changing power supply voltages during operation, set the slope of rising within 30 mV/ms. • Time from Power-on to User programing operation (reset release) Parameter Reset release time Symbol TRST Conditions ⎯ Value Min ⎯ Typ 21 Max ⎯ Unit ms Low voltage detection reset release voltage VDL+ VCC Instruction execution Internal reset Power-on reset Reset release time TRST 30 DS07-12630-2E MB95R203A (5) Peripheral Input Timing (Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to +85 °C) Parameter Peripheral input “H” pulse Peripheral input “L” pulse Symbol tILIH tIHIL Pin name INT02 to INT07, EC0, EC1 Value Min 2 tMCLK* 2 tMCLK* Max ⎯ ⎯ Unit ns ns * : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. tILIH tIHIL 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC INT02 to INT07, EC0, EC1 DS07-12630-2E 31 MB95R203A (6) UART/SIO, Serial I/O Timing (Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to +85 °C) Parameter Serial clock cycle time UCK ↓ → UO time Valid UI → UCK ↑ UCK ↑→ valid UI hold time Serial clock “H” pulse width Serial clock “L” pulse width UCK ↓ → UO time Valid UI → UCK ↑ UCK ↑→ valid UI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name UCK UCK, UO UCK,UI UCK, UI UCK UCK UCK, UO UCK, UI UCK, UI External clock operation output pin : CL = 80 pF + 1 TTL. Internal clock operation output pin : CL = 80 pF + 1 TTL. Conditions Value Min 4 tMCLK* −190 2 tMCLK* 2 tMCLK* 4 tMCLK* 4 tMCLK* 0 2 tMCLK* 2 tMCLK* Max ⎯ +190 ⎯ ⎯ ⎯ ⎯ 190 ⎯ ⎯ Unit ns ns ns ns ns ns ns ns ns * : Refer to “ (2) Source Clock/Machine Clock” for details on tMCLK. • Internal shift clock mode tSCYC UCK 2.4 V 0.8 V tSLOV 0.8 V UO 2.4 V 0.8 V tIVSH tSHIX UI 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSLSH tSHSL 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tSLOV UCK UO 2.4 V 0.8 V tIVSH tSHIX UI 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 32 DS07-12630-2E MB95R203A (7) I2C Timing (Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to +85 °C) Value Parameter Symbol Pin name SCL SCL SDA SCL SCL SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA R = 1.7 kΩ, C = 50 pF*1 Conditions Standardmode Min SCL clock frequency (Repeat) Start condition hold time SDA ↓ → SCL ↓ SCL clock “L” width SCL clock “H” width (Repeat) Start condition setup time SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓ ↑ Data setup time SDA ↓ ↑ → SCL ↑ Stop condition setup time SCL ↑ → SDA ↓ Bus free time between stop condition and start condition tSCYC tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF 0 4.0 4.7 4.0 4.7 0 0.25 4.0 4.7 Max 100 ⎯ ⎯ ⎯ ⎯ 3.45*2 ⎯ ⎯ ⎯ Fast-mode Min 0 0.6 1.3 0.6 0.6 0 0.1 0.6 1.3 Max 400 ⎯ ⎯ ⎯ ⎯ 0.9*2 ⎯ ⎯ ⎯ kHz μs μs μs μs μs μs μs μs Unit *1 : R, C : Pull-up resistance and load capacitance of the SCL and SDA lines. *2 : The maximum value of tHD;DAT is applicable only if the device does not extend the “L” width (tLOW) of the SCL signal. *3 : A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. tWAKEUP SDA tLOW SCL tHD;STA tSU;DAT tSU;STA tSU;STO tHD;DAT tHIGH tHD;STA tBUF DS07-12630-2E 33 MB95R203A (Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to +85 °C) Parameter SCL clock “L” width SCL clock “H” width Symbol tLOW tHIGH Pin name SCL SCL Conditions Value*2 Min (2 + nm / 2) tMCLK − 20 (nm / 2) tMCLK − 20 Max ⎯ (nm / 2) tMCLK + 20 Unit ns ns Remarks Master mode Master mode Master mode maximum value is applied when m, n = 1, 8. Otherwise, the minimum value is applied. Master mode Master mode Start condition hold time tHD;STA SCL SDA (−1 + nm / 2) tMCLK − 20 (−1 + nm / 2) tMCLK + 20 ns Stop condition setup time Start condition setup time Bus free time between stop condition and start condition Data hold time tSU;STO tSU;STA SCL SDA SCL SDA SCL SDA SCL SDA (1 + nm / 2) tMCLK (1 + nm / 2) tMCLK − 20 + 20 (1 + nm / 2) tMCLK (1 + nm / 2) tMCLK − 20 + 20 (2 nm + 4) tMCLK − 20 3 tMCLK − 20 R = 1.7 kΩ, C = 50 pF*1 ⎯ ns ns tBUF ns tHD;DAT ⎯ ns Master mode Master mode When assuming that “L” of SCL is not extended, the minimum value is applied to first bit of continuous data. Otherwise, the maximum value is applied. Minimum value is applied to interrupt at 9th SCL↓. Maximum value is applied to interrupt at 8th SCL↓. At reception At reception Undetected when 1 tMCLK is used at reception (Continued) Data setup time tSU;DAT SCL SDA (−2 + nm / 2) tMCLK − 20 (−1 + nm / 2) tMCLK + 20 ns Setup time between cleaning interrupt and SCL rising SCL clock “L” width SCL clock “H” width Start condition detection tSU;INT SCL (nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20 ns tLOW tHIGH SCL SCL SCL SDA 4 tMCLK − 20 4 tMCLK − 20 4 tMCLK − 20 ⎯ ⎯ ⎯ ns ns tHD;STA ns 34 DS07-12630-2E MB95R203A (Continued) Pin name SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA R = 1.7 kΩ, C = 50 pF*1 Conditions (Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to +85 °C) Symbol Value*2 Min 4 tMCLK − 20 Max ⎯ Unit Remarks Undetected when 1 tMCLK is used at reception Undetected when 1 tMCLK is used at reception During reception In slave transmission mode In slave transmission mode During reception During reception Parameter Stop condition detection Restart condition detection condition Bus free time Data hold time Data setup time Data hold time Data setup time SDA ↓ → SCL ↑ (when using wakeup function) tSU;STO ns tSU;STA 2 tMCLK − 20 2 tMCLK − 20 2 tMCLK − 20 tLOW − 3 tMCLK − 20 0 tMCLK − 20 Oscillation stabilization wait time + 2 tMCLK − 20 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ns tBUF tHD;DAT tSU;DAT tHD;DAT tSU;DAT ns ns ns ns ns tWAKEUP ⎯ ns *1 : R, C : Pull-up resistance and load capacitance of the SCL and SDA lines. *2 : • Refer to “ (2) Source Clock/Machine Clock” for details on tMCLK. • m is the CS4 and CS3 bits (bit4 and bit3) of the I2C clock control register (ICCR0) . • n is the CS2 to CS0 bits (bit2 to bit0) of the I2C clock control register (ICCR0) . • The actual I2C timing is determined by the machine (tMCLK) and the values of m and n configured in bits CS4 to CS0 of the I2C clock control register (ICCR0) . • Standard-mode : m and n can be set in the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz. The machine clock to be used is determined by the settings of m and n as follows. (m, n) = (1, 8) : 0.9 MHz < tMCLK ≤ 1 MHz (m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) , : 0.9 MHz < tMCLK ≤ 2 MHz (m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) , : 0.9 MHz < tMCLK ≤ 4 MHz (m, n) = (1, 98) : 0.9 MHz < tMCLK ≤ 1 MHz • Fast-mode : m and n can be set in the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz. The machine clock to be used is determined by the settings of m and n as follows. (m, n) = (1, 8) : 3.3 MHz < tMCLK ≤ 4 MHz (m, n) = (1, 22) , (5, 4) : 3.3 MHz < tMCLK ≤ 8 MHz (m, n) = (6, 4) : 3.3 MHz < tMCLK ≤ 10 MHz DS07-12630-2E 35 MB95R203A (8) Low Voltage Detection (VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Release voltage Low voltage detection reset Detection voltage Hysteresis width Release voltage FRAM power supply monitor Detection voltage Hysteresis width Symbol VDL+ VDL− VHYS VDL+ VDL− VHYS Value Min 1.75 1.65 70 1.8 1.7 70 2.2 2.4 Release voltage VDL+ 2.6 2.8 Low voltage detection interrupt 2.1 2.3 Detection voltage VDL− 2.5 2.7 Hysteresis width Power-supply start voltage Power-supply end voltage Power-supply voltage change time (at power supply rise) VHYS Voff Von 70 ⎯ 2.0 0.3 tr ⎯ 0.3 tf ⎯ td1 td2 ⎯ ⎯ 200 ⎯ ⎯ ⎯ 300 20 μs μs μs 200 ⎯ ⎯ ⎯ μs μs 2.6 2.8 100 ⎯ ⎯ ⎯ 2.7 2.9 ⎯ 1.2 ⎯ ⎯ V V mV V V μs Slope of power supply that reset release signal generates Slope of power supply that reset release signal generates within rating (V1DL+, V2DL+) Slope of power supply that reset detection signal generates Slope of power supply that reset detection signal generates within rating (V1DL−, V2DL−) 2.7 2.9 2.2 2.4 2.8 3.0 2.3 2.5 V V V V Typ 1.85 1.75 100 1.9 1.8 100 2.3 2.5 Max 1.95 1.85 ⎯ 2.0 1.9 ⎯ 2.4 2.6 Unit V V mV V V mV V V At LS1 = 0, LS0 = 0, powersupply rise* At LS1 = 0, LS0 = 1, powersupply rise* At LS1 = 1, LS0 = 0, powersupply rise* At LS1 = 1, LS0 = 1, powersupply rise* At LS1 = 0, LS0 = 0, powersupply fall* At LS1 = 0, LS0 = 1, powersupply fall* At LS1 = 1, LS0 = 0, powersupply fall* At LS1 = 1, LS0 = 1, powersupply fall* At power-supply rise At power-supply fall Remarks At power-supply rise At power-supply fall Power-supply voltage change time (at power supply fall) Reset release delay time Reset detection delay time * : LS1 and LS0 mean the LS1 bit and the LS0 bit (bit1 and bit0) for the low voltage detection interrupt control register (LVDCR) respectively. 36 DS07-12630-2E MB95R203A VCC Von Voff time tf tr VDL+ VHYS VDL- Internal reset signal time td2 td1 DS07-12630-2E 37 MB95R203A 5. A/D Converter (1) A/D Converter Electrical Characteristics (Vcc = 2.7 V to 3.6 V, Vss = 0.0 V, TA = −40 °C to +85 °C) Parameter Resolution Total error Linearity error Differential linear error Zero transition voltage Full-scale transition voltage Compare time Sampling time Analog input voltage VOT VFST ⎯ ⎯ VAIN ⎯ Symbol Value Min ⎯ − 5.0 − 3.5 − 3.0 Typ ⎯ ⎯ ⎯ ⎯ Max 10 + 5.0 + 3.5 + 3.0 Unit bit LSB LSB LSB V V μs μs V 2.7 V ≤ Vcc ≤ 3.6 V At external impedance < 1.8 kΩ Remarks VSS − 1.5 LSB VSS + 0.5 LSB VSS + 4.0 LSB VCC − 4.0 LSB VCC − 1.5 LSB VCC + 0.5 LSB 1.1 0.4 VSS ⎯ ⎯ ⎯ 27.5 ∞ VCC 38 DS07-12630-2E MB95R203A (2) Notes on Using A/D Converter • About the external impedance of analog input and its sampling time A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin. • Analog input equivalent circuit Analog input R C Comparator During sampling : ON 2.7 V ≤ Vcc ≤ 3.6 V : R = 5.3 kΩ (Max) , C = 8.5 pF (Max) : : Note : The values are reference values. • The relationship between external impedance and minimum sampling time. [External impedance = 0 kΩ to 100 kΩ] External impedance [kΩ] External impedance [kΩ] 100 90 80 70 60 50 40 30 20 10 0 0 [External impedance = 0 kΩ to 20 kΩ] 20 18 16 14 12 10 8 6 4 2 0 0 Minimum sampling time [μs] 5 10 15 20 25 30 35 40 Minimum sampling time [μs] 1 2 3 4 • About errors |VCC − VSS| becomes smaller, values of relative errors grow larger. DS07-12630-2E 39 MB95R203A (3) Definition of A/D Converter Terms • Resolution The level of analog variation that can be distinguished by the A/D converter. When the number of bits is 10, analog voltage can be divided into 210 = 1024. • Linearity error (unit : LSB) The deviation between the value along a straight line connecting the zero transition point (“00 0000 0000” ←→ “00 0000 0001”) of a device and the full-scale transition point (“11 1111 1111” ←→ “11 1111 1110”) compared with the actual conversion values obtained. • Differential linear error (Unit : LSB) Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. • Total error (unit : LSB) Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error, linearity error, quantum error, and noise. Ideal I/O characteristics VFST Total error 3FF 3FE 3FF 3FE 1.5 LSB Actual conversion characteristic {1 LSB × (N − 1) + 0.5 LSB} Digital output Digital output 3FD 3FD 004 003 002 001 0.5 LSB VSS VCC VOT 1 LSB 004 003 002 001 VSS VCC VNT Actual conversion characteristic Ideal characteristics Analog input VCC − VSS 1024 (V) Analog input 1 LSB = Total error of VNT − {1 LSB × (N − 1) + 0.5 LSB} = [LSB] digital output N 1 LSB N : A/D converter digital output value VNT : A voltage at which digital output transits from (N - 1) to N (Continued) 40 DS07-12630-2E MB95R203A (Continued) Zero transition error 004 Actual conversion characteristic 3FF Full-scale transition error Ideal characteristics Actual conversion characteristic Digital output 003 Ideal characteristics Digital output 3FE 002 Actual conversion characteristic VFST 3FD (measurement value) 001 VOT (measurement value) 3FC Actual conversion characteristic VSS VCC VSS VCC Analog input Analog input Linearity error 3FF 3FE Actual conversion characteristic Differential linear error Ideal characteristics N+1 {1 LSB × N + VOT} VFST (measurement value) VNT Digital output Digital output 3FD Actual conversion characteristic V (N+1) T N 004 003 002 001 VSS Actual conversion characteristic Ideal characteristics N-1 VNT Actual conversion characteristic N-2 VOT (measurement value) Analog input VCC VSS Analog input VCC Linearity error in = VNT − {1 LSB × N + VOT} 1 LSB digital output N Differential linear error = V (N + 1) T − VNT 1 LSB In digital output N −1 N : A/D converter digital output value VNT : A voltage at which digital output transits from (N - 1) to N. VOT (Ideal value) = VSS + 0.5 LSB [V] VFST (Ideal value) = VCC − 2.0 LSB [V] DS07-12630-2E 41 MB95R203A 6. FRAM Characteristics Parameter Number of read/write cycle *: TA = +25 °C Value Min ⎯ Typ 1015* Max ⎯ Unit cycle Remarks 42 DS07-12630-2E MB95R203A ■ EXAMPLE CHARACTERISTICS • Power supply current and temperature characteristics ICC-VCC TA = + 25 °C, FMP = 2, 4, 8, 10 MHz (divided by 2) Main clock mode with external clock operating 5 4 ICC [mA] ICC [mA] 3 2 1 0 1.5 2 2.5 3 VCC [V] 3.5 4 10 MHz 8 MHz 4 MHz 2 MHz ICC-TA VCC = 3.6 V, FMP = 10 MHz (divided by 2) Main clock mode with external clock operating 5 4 3 2 1 0 -50 0 TA [°C] +50 +100 ICCS-VCC TA = + 25 °C, FMP = 2, 4, 8, 10 MHz (divided by 2) Main sleep mode with the external clock operating 5 4 ICCS [mA] ICCS-TA VCC = 3.6V, FMP = 10 MHz (divided by 2) Main sleep mode with the external clock operating 5 4 ICCS [mA] 3 2 1 0 -50 0 TA [°C] +50 +100 3 2 1 0 1.5 10MHz 8MHz 4MHz 2MHz 2 2.5 3 VCC [V] 3.5 4 ICCL-VCC TA = + 25 °C, FMPL = 16 kHz (divided by 2) Sub clock mode with the external clock operating 200 ICCL-TA VCC = 3.6 V,FMPL = 16kHz (divided by 2) Sub clock mode with the external clock operating 200 150 ICCL [μA] ICCL [μA] 150 100 100 50 50 0 1.5 2 2.5 3 VCC [V] 3.5 4 0 -50 0 TA [°C] +50 +100 (Continued) DS07-12630-2E 43 MB95R203A ICCLS-VCC TA = + 25 °C, FMP = 16 kHz (divided by 2) Sub sleep mode with external clock operating 200 ICCLS-TA VCC = 3.6 V,FMPL = 16 kHz (divided by 2) Sub sleep mode with external clock operating 200 150 ICCLS [μA] ICCLS [μA] 1.5 2 2.5 3 VCC [V] 3.5 4 150 100 100 50 50 0 0 -50 0 TA [°C] +50 +100 ICCT-VCC TA = + 25 °C, FMPL = 16 kHz (divided by 2) Watch mode with external clock operating 200 ICCT-TA VCC = 3.6 V,FMPL = 16 kHz (divided by 2) Watch mode with external clock operating 200 150 ICCT [μA] ICCT [μA] 1.5 2 2.5 3 VCC [V] 3.5 4 150 100 100 50 50 0 0 -50 0 TA [°C] +50 +100 ICTS-VCC TA = + 25 °C, FMP = 16 kHz (divided by 2) Timebase timer mode with external clock operating 2 ICTS-TA VCC = 3.6 V,FMP = 10MHz (divided by 2) Timebase timer mode with external clock operating 2 1.5 ICTS [μA] 1.5 1 ICTS [μA] 10MHz 8MHz 4MHz 2MHz 2 2.5 3 VCC [V] 3.5 4 1 0.5 0.5 0 1.5 0 -50 0 TA [°C] +50 +100 (Continued) 44 DS07-12630-2E MB95R203A (Continued) ICCH-VCC TA = + 25 °C, FMP = (stop) Sub stop mode with the external clock operating 200 150 100 50 0 1.5 2 2.5 3 VCC [V] 3.5 4 ICCHN [μA] ICCH [μA] ICCH-TA VCC = 3.6 V,FMPL = (stop) Sub stop mode with the external clock stopping 200 150 100 50 0 -50 0 TA [°C] +50 +100 ICCMCR-VCC TA = + 25 °C, FMP = 1 MHz (no division) Main clock mode with internal main CR clock operating 5 4 ICCMCR [μA] 3 2 1 0 1.5 2 2.5 3 VCC [V] 3.5 4 ICCMCR [μA] 5 4 3 2 1 0 ICCMCR-TA VCC = 3.6 V,FMP = 1 MHz (no division) Main clock mode with internal main CR clock operating -50 0 TA [°C] +50 +100 ICCSCR-VCC TA = + 25 °C, FMP = 50 kHz (divided by 2) Sub clock mode with internal main CR clock operating 200 ICCSCR-TA VCC=3.6V,FMPL = 50 kHz (divided by 2) Sub clock mode with internal sub CR clock operating 200 150 ICCSCR [μA] ICCSCR [μA] 1.5 2 2.5 3 VCC [V] 3.5 4 150 100 100 50 50 0 0 -50 0 TA [°C] +50 +100 DS07-12630-2E 45 MB95R203A • Input voltage characteristics VIHS-VCC and VILS-VCC TA = + 25 °C 2.5 2 VIHS/VILS [V] VIHI/VILI [V] 1.5 1 0.5 0.5 0 1.5 2 2.5 3 VCC [V] 3.5 4 0 1.5 2.5 2 1.5 1 VIHI-VCC and VILI-VCC T A = + 25 ° C 2 2.5 3 VCC [V] 3.5 4 46 DS07-12630-2E MB95R203A • Output voltage characteristics (VCC-VOH1)-IOH TA = + 25 °C 1 0.8 VCC-VOH1 [V] 0.6 0.4 0.2 0 0 -2 -4 -6 IOH [μA] -8 -10 1 0.8 (VCC-VOH2)-IOH TA = + 25 °C VCC-VOH2 [V] 0.6 0.4 0.2 0 0 -2 -4 -6 IOH [μA] -8 -10 VCC 1.8V 2.0V 2.7V 3.0V 3.6V VCC 1.8V 2.0V 2.7V 3V 3.6V VOL1-IOL TA = + 25 °C 1 0.8 VOL1 [V] VOL2 [V] 0.6 0.4 0.2 0 0 2 4 6 8 IOL [μA] 10 12 1 0.8 0.6 0.4 0.2 0 0 VOL2-IOL TA = + 25 °C 2 4 6 8 IOL [μA] 10 12 VCC 1.8V 2.0V 2.7V 3.0V 3.6V VCC 1.8V 2.0V 2.7V 3.0V 3.6V DS07-12630-2E 47 MB95R203A • Pull-up characteristics RPULL-VCC TA = + 25 °C 100 80 RPULL [kΩ] 60 40 20 0 1.5 2 2.5 3 VCC [V] 3.5 4 48 DS07-12630-2E MB95R203A ■ ORDERING INFORMATION Part number MB95R203AP-G-SH-JNE2 MB95R203APF-G-JNE2 Package 24-pin plastic DIP (DIP-24P-M07) 20-pin plastic SOP (FPT-20P-M09) Remarks DS07-12630-2E 49 MB95R203A ■ PACKAGE DIMENSIONS 24-pin plastic SDIP Lead pitch Package width × package length Sealing method Mounting height 1.778 mm 6.40 mm × 22.86 mm Plastic mold 4.80 mm Max (DIP-24P-M07) 24-pin plastic SDIP (DIP-24P-M07) #22.86±0.10(.900±.004) 24 Note 1) Pins width and pins thickness include plating thickness. Note 2) Pins width do not include tie bar cutting remainder. Note 3) # : These dimensions do not include resin protrusion. 13 INDEX BTM E-MARK 6.40±0.10 (.252±.004) 1 12 7.62(.300) TYP. 4.80(.189)MAX 0.50(.020) MIN +0.10 3.00 –0.30 .118 –.012 +0.20 +.008 0.25 –0.04 .010 –.002 1.00±0.10 (.039±.004) 0.43 –0.04 .017 –.002 +0.09 +.004 1.778(.070) +.004 C 2008-2010 FUJITSU SEMICONDUCTOR LIMITED D24066S-c-1-2 Dimensions in mm (inches). Note: The values in parentheses are reference values Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 50 DS07-12630-2E MB95R203A (Continued) 20-pin plastic SOP Lead pitch Package width × package length Lead shape Lead bend direction Sealing method Mounting height 1.27 mm 7.50 mm × 12.70 mm Gullwing Normal bend Plastic mold 2.65 mm Max (FPT-20P-M09) 20-pin plastic SOP (FPT-20P-M09) #12.70±0.10(.500±.004) 20 11 Note 1) Pins width and pins thickness include plating thickness. Note 2) Pins width do not include tie bar cutting remainder. Note 3) # : These dimensions do not include resin protrusion. 0.25 .010 –.001 +0.07 –0.02 +.003 BTM E-MARK #7.50±0.10 10.2 –0.20 (.295±.004) .402 +.016 –.008 INDEX Details of "A" part +0.13 2.52 –0.17 (Mounting height) +.005 .099 –.007 +0.40 1 10 +0.09 –0.05 +.004 –.002 "A" 0~8° 1.27(.050) 0.40 .016 0.25(.010) M 0.80 –0.30 +0.47 +.019 .031 –.012 0.20±0.10 (.008±.004) (Stand off) 0.10(.004) C 2008-2010 FUJITSU SEMICONDUCTOR LIMITED F20030S-c-1-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ DS07-12630-2E 51 MB95R203A ■ MAJOR CHANGES IN THIS EDITION Page Section ■ NOTES ON ON-CHIP DEBUG Change Results Corrected the title. DEBUG → ON-CHIP DEBUG Added the sentence as follows. “When you click on the [Erase Flash Memory] and the [Target load] button on SOFTUNE Workbench,data in the I/O area described below is undefined.”. Added the table of address 0070H, 0071H. Corrected the condition and the value of “Open-drain output leak current”. Corrected the maximum value of “Pull-up resistance”. 66 → 80 Corrected the power supply current. 4. AC Characteristics (4) Power-on Reset 5. A/D Converter (1) A/D Converter Electrical Characteristics Added “• Time from Power-on to User programing operation (reset release)”. Corrected the value of Total error. Min : − 3.0→ − 5.0 Max : + 3.0→ + 5.0 Corrected the value of Linearity error. Min : − 2.5→ − 3.5 Max : + 2.5→ + 3.5 Corrected the value of Differential linear error. Min : − 1.9→ − 3.0 Max : + 1.9→ + 3.0 Corrected the maximum value of Zero transition voltage. VSS + 2.5 LSB → VSS + 4.0 LSB Corrected the minimum value of Full-scale transition voltage. VCC − 3.5 LSB → VCC − 4.0 LSB Corrected the value of Compare time. Min : 0.6 → 1.1 Max : 140 → 27.5 Deleted the item of Analog input current. Corrected the value. Min:1015 → “ − ” Typ: “ − ”→ 1015 Added the footnote. Added a new section. 12 23 ■ ELECTRICAL CHARACTERISTICS 3. DC Characteristics 23, 24 30 38 6. FRAM Characteristics 42 43 to 48 ■ EXAMPLE CHARACTERISTICS The vertical lines drawn on the left side of the page indicate the changes. 52 DS07-12630-2E MB95R203A MEMO DS07-12630-2E 53 MB95R203A MEMO 54 DS07-12630-2E MB95R203A MEMO DS07-12630-2E 55 MB95R203A FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fss/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fsp/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. 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Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department