MB96300 PRELIMININARY SPECIFICATION
FME-MB96300 rev 19
16-bit Proprietary Microcontroller
CMOS
F2MC-16FX MB96300 Series
MB96300 series is based on Fujitsu’s advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance). The CPU uses the same instruction set as the established 16LX series - thus allowing for easy migration of 16LX Software to the new 16FX products. 16FX improvements compared to the previous generation include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time.
s PACKAGES
• 48-pin
PR
FME/EMDC- 2007-02-12
EL IM
48-pin Plastic LQFP
(FPT-48P-M26)
IN
For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 56MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction cycle time of 17.8ns going together with excellent EMI behavior. An on-chip clock modulation circuit significantly reduces emission peaks in the frequency spectrum. The emitted power is minimised by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows to select suitable operation frequencies for peripheral resources independent of the CPU speed.
AR
s DESCRIPTION
MB96300_shortspec.fm
Y
MB96300 Series
• 64-pin 64-pin Plastic LQFP
Preliminary Specification
64-pin Plastic LQFP
(FPT-64P-M23)
• 80-pin
80-pin Plastic LQFP
• 100-pin
PR EL
100-pin Plastic QFP (FPT-100P-M22)
IM
2 FME/EMDC- 2007-02-12
(FPT-80P-M21)
IN
100-pin Plastic LQFP
(FPT 100P M05)
AR
(FPT-100P-M20) MB96300_shortspec.fm
Y
(FPT-64P-M24)
Preliminary Specification
• 120-pin 120-pin Plastic LQFP
MB96300
(FPT 100P M05)
(FPT-120P-M21)
FME/EMDC- 2007-02-12
PR
EL IM
MB96300_shortspec.fm
IN
AR
3
Y
MB96300 Series
s FEATURES
Preliminary Specification
• 16-bit core CPU, up to 56 MHz internal, 17.8 ns instruction cycle time • 0.18µm CMOS Process Technology • Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety of pointers) • 8-byte instruction execution queue • Signed multiply (16 bit × 16 bit) and divide (32 bit/16 bit) instructions available • Internal voltage regulator supports reduced internal MCU voltage, offering low EMI and low power consumption figures • Code Security Feature • Up to 5 FULL-CAN interfaces; conforming to Version 2.0 Part A and Part B, ISO16845 certified • Powerful interrupt functions (8 progr. priority levels; up to 16 external interrupts) • Fast Interrupt processing • Up to 16 channels DMA - Automatic transfer function independent of CPU, can be assigned freely to resources • Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer) • Up to 10 channels full duplex USARTs (SCI/LIN) • Up to 2 channels I2C with 400 kbit/s • Up to 6 channels16-bit reload timer • Watchdog Timer
• Up to 40 channels analog inputs for A/D Converter (Resolution 10 bits or 8 bits) • Up to 12 channels ICU (Input capture unit) 16 bit • Up to 4 channels 16-bit free running timer
• Up to 12 channels OCU (Output compare unit) 16 bit
• Up to 20 channels × 16-bit Programmable Pulse Generator • Up to 6 channels Stepper Motor Controller with integrated high current output drivers • LCD controller with up to 4 COM × 72 SEG, internal or external voltage generation • Memory Patch Function, can also be used to implement embedded debug support • Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes, Stop mode) • 3-32 MHz external clock, on-chip PLL with programmable multiplication factor 1 ... 16 • 32 kHz Subsystem Clock • 100kHz/2MHz internal RC clock
• External bus interface with up to 6 Chip select signals, 8bit or 16bit data, 24bit address, multiplexed or nonmultiplexed, programmable timing • Up to 2 channels Alarm comparators • Programmable input levels (Automotive / CMOS-Schmitt trigger / TTL) for all ports • Programmable Pull-up resistors for all ports • Programmable output driving strength for EMI optimization • Package : 48-pin / 64-pin / 80-pin /100-pin / 120-pin plastic QFP and LQFP 4 FME/EMDC- 2007-02-12 MB96300_shortspec.fm
PR EL
IM
IN
AR
Y
Preliminary Specification
• Controller Area Network (CAN) - License of Robert Bosch GmbH
MB96300
FME/EMDC- 2007-02-12
PR
EL IM
MB96300_shortspec.fm
IN
AR
5
Y
MB96300 Series
s PRODUCT LINEUP
Preliminary Specification
Features Product type CPU
MB96V300 Evaluation sample
MB9632x
MB9634x
MB9635x
MB9636x
MB9638x
Flash product: MB96F3xx Mask ROM product: MB963xx F2MC-16FX CPU
System clock
RAM 6kB 6kB 12kB ROM/Flash memory emulation by external RAM, 92kB internal RAM MB96F326R, MB96F326Y
128kB 160kB 288kB
MB96344R, MB96344Y
AR
Flash/ ROM
Y
On-chip PLL clock multiplier (x1..16, 1/2 when PLL stop) Minimum instruction execution time: 17.8 ns (56MHz) Clock source selectable from main- and subclock oscillator (partnumber suffix “W”), on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals
MB96384R, MB96384Y MB96F365R, MB96F365Y MB96385R, MB96385Y
IN
MB96F346R, MB96346R, MB96F346Y, MB96346Y MB96F347R, MB96347R, MB96F347Y, MB96347Y MB96F348R, MB96F348Y MB96F348C, MB96F348H, MB96F348T FPT-100PM20 FPT-100PM22 6 channels
MB96F356R, MB96F356Y MB96F386R, MB96386R, MB96F386Y, MB96386Y MB96F387R, MB96387R, MB96F387Y, MB96387Y
288kB
16kB
416kB
16kB
544kB Main: 544kB, Sat.: 32kB
24kB
24kB
Technology
PR EL
0.18mm CMOS with on-chip voltage regulator for internal power supply FPT-64P-M23 FPT-64P-M24 4 channels FPT-120PM21 7 channels
Package
BGA416
FPT-80P-M21
IM
4 channels
FPT-48P-M26
DMA
16 channels
3 channels
6
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
Features MB96V300 MB9632x MB9634x MB96F348H/ T: 4 channels others: 7 channels MB9635x
MB96300
MB9636x MB9638x
10 channels USART
4 channels
4 channels
2 channels
5 channels
Wide range of baud rate settings using a dedicated reload timer Special synchronous options for adapting to different synchronous serial protocols LIN functionality working either as master or slave LIN device I2C 40 channels A/D Converter 18 channels 24 channels
Master and Slave functionality, 8-bit and 10-bit addressing 15 channels 16 channels
SAR-type, 10bit resolution, signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion mode, activation by software, external trigger or reload timer MB96384R/Y, MB96385R/Y: no others: yes 4 channels
A/D Converter Reference Voltage switch
yes
no
yes
AR
no 4 channels 2 channels 4 channels 6 channels 20 channels
Y
2 channels
1 channel
2 channel
1 channel
1 channel
no
16-bit Reload Timer
6 channels
4 channels
IN
4 channels 2 channels 8 channels 8 channels 16 channels
3 channels
Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency, event count function 4 channels 4 channels 1 channel 2 channels
16-bit FreeRunning Timer
Signals an interrupt on overflow, supports timer clear upon match with Output Compare (0, 4), Prescaler with 1/22, 1/24, 1/26, 1/28 of peripheral clockfrequency I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1/2/3, OCU 0/1/2/3 I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7 I/O Timer 2 (clock input FRCK2) corresponds to ICU 8/9 I/O Timer 3 (clock input FRCK3) corresponds to ICU 10/11 12 channels 6 channels 4 channels
16-bit Output Compare
Signals an interrupt when a match with 16-bit I/O Timer A pair of compare registers can be used to generate an output signal. 12 channels 12 channels 4 channels 8 channels
20 channels
PR
16-bit Input Capture
Signals an interrupt upon external event Rising edge, falling edge or rising & falling edge sensitive 20 channels 8 channels
16-bit Programmable Pulse Generator
16 bit down counter, cycle and duty setting registers Interrupt at triggering, cycle or duty match PWM operation and one-shot operation Internal prescaler allows 1/2, 1/4, 1/8, 1/16 of peripheral clock as counter clock and Reload timer overflow as clock input Can be triggered by software or reload timer Synchronous trigger of up to 4 PPG channels
FME/EMDC- 2007-02-12
EL IM
MB96300_shortspec.fm
7
MB96300 Series
Features MB96V300 MB9632x
Preliminary Specification
MB9634x MB9635x MB9636x MB9638x MB96384R/Y, MB96385R/Y: 1 channel others: 2 channels
5 channels
2 channels
2 channels
2 channels
1 channel
CAN Interface (not available on MB963xxA, MB963xxC)
6 channels Stepping Motor Controller
AR
1 channel
Supports CAN protocol version 2.0 part A and B ISO16845 certified Bit rates up to 1 Mbit/s 32 message objects Each message object has its own identifier mask Programmable FIFO mode (concatenation of message objects) Maskable interrupt Disabled Automatic Retransmission mode for Time Triggered CAN applications Programmable loop-back mode for self-test operation
Y
5 channels
Four high current outputs for each channel Two synchronized 8/10-bit PWMs per channel Internal prescaling for PMW clock: 1, 1/2, 1/4, 1/5, 1/6, 1/8, 1/10, 1/12, 1/16 of peripheral clock
External Interrupts
Edge sensitive or level sensitive Interrupt mask and pending bit per channel Each available CAN channel RX has an external interrupt for wake-up Selected USART channels SIN have an external interrupt for wake-up
Non-Maskable Interrupt
Disabled after reset Once enabled, can not be disabled other than by reset. Level high or level low sensitive Pin shared with external interrupt 0.
PR EL
1channel
IM
IN
16 channels
15 channels
16 channels
13 channels
10 channels
8 channels
2 channels
Sound Generator
8-bit PWM signal is mixed with tone frequency from 16-bit reload counter PWM clock by internal prescaler: 1, 1/2, 1/4, 1/8, 1/16 of peripheral clock Tone frequency: PWM frequency / 2 / (reload value + 1) 4 COM x 72 SEG 4 COM x 65 SEG
LCD Controller
Display up to 288 segments Duty cycle: Selectable from options: 1/2, 1/3 and 1/4 Bias: Fixed at 1/3 Frame period: Selectable from three options. (for clock, peripheral clock, subclock or RC oscillator clock is selectable) Driver: Built-in (for internal divider resistors), or external divider resistors Data memory: Built-in 16-byte data memory for display Stop mode: Enable LCD display in the sub-stop mode Blank display: Selectable Pin: All SEG and COM pins can be switched between general and specialized purposes Others: External divided resistors can be also used to shut off the current when LCD is deactivated
8
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
Features MB96V300 MB9632x MB9634x MB9635x
MB96300
MB9636x MB9638x 1
MB96F348H/T: no others: 1
Real Time Clock
Can be clocked either from sub oscillator (devices with partnumber suffix “W”), main oscillator or from the RC oscillator Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration) Read/write accessible second/minute/ hour registers Can signal interrupts every halfsecond/second/ minute/hour/day Internal clock divider and prescaler provide exact 1s clock based on a 4 MHz or a 32 kHz clock input (devices with partnumber suffix “W”)
Y
136
I/O Ports
2 channels
2 channels
IN
6 signals 2 channels
Virtually all external pins can be used as general purpose I/O All push-pull outputs (except when used as I2C SDA/SCL line) Bit-wise programmable input enable Bit-wise programmable Pull-up resistor Bit-wise programmable as input/output or peripheral signal Bit-wise programmable as CMOS schmitt trigger/ automotive / TTL input Bit-wise programmable output driving strength MB96384R/Y, MB96385R/Y: 1 channel others: 2 channels
Alarm comparator
Monitors an external voltage and generates an interrupt in case of a voltage lower or higher than the defined thresholds Threshold voltages defined externally or generated internally Status is readable, interrupts can be masked separately Yes Yes
External bus interface
Chip select
PR
Multiplexed address/data lines Non-multiplexed address/data lines (MB96V300 and MB9638x only) 16-bit bidirectional data bus 24-bit address lines (MB9635x: 22-bit address lines) Wait state request External bus master possible Timing programmable 6 signals 6 signals 6 signals 2 channels 2 channels 6 signals 2 channels
2 channels
Clock output function
Output any on-chip clock Inverted and non-inverted clock (MB9636x,MB9635x has only non-inverted clock output) Prescaler: 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128 of selected clock Synchronous or asynchronous start/stop Reset is generated when supply voltage is below minimum.
Low voltage reset
FME/EMDC- 2007-02-12
EL IM
2 channels
AR
64 for part number with suffix "W", 66 for part number with suffix "S"
80 for part number with suffix "W", 82 for part number with suffix "S"
49 for part number with suffix "W", 51 for part number with suffix "S"
34 for part number with suffix "W", 36 for part number with suffix "S"
94 for part number with suffix "W", 96 for part number with suffix "S
MB96300_shortspec.fm
9
MB96300 Series
Features On-chip RCoscillator MB96V300 MB9632x
Preliminary Specification
MB9634x MB9635x MB9636x MB9638x
For quick and save startup, oscillator stop detection, watchdog operation, normal clock source 2 frequencies selectable (100kHz, 2MHz) Supports automatic programming, Embedded AlgorithmTM*1 Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of erase cycles : 10,000 times Data retention time : 20 years Erase can be performed on each sector individually Sector protection Flash Security feature to protect the content of the Flash Low voltage detection during Flash erase
Flash Memory
*1
: Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
10
FME/EMDC- 2007-02-12
PR EL
MB96300_shortspec.fm
IM
IN
AR
Y
Preliminary Specification
s PIN ASSIGNMENTS
MB96300
Pin assignment of MB96(F)32x
P01_5/AD13/SIN2_R/INT7_R/PPG17_R
Vcc C P17_2 /FRCK3/TTG17 P13_5 /PPG17 P02_5 /A21/IN1/TTG1/TTG9/ADTG_R P04_4 /SDA0/FRCK0/TIN0_R P04_5 /SCL0/FRCK1/TIN2_R P03_0 /ALE/IN4/TTG4/TTG12/TOT0_R P03_1 /RDX/IN5/TTG5 /TTG13/TOT2_R P03_2 /WRLX/INT10_R /RX2 P03_3 /WRHX /TX2 P03_4 /HRQ/OUT4 P03_5 /HAKX/OUT5 P03_6 /RDY/OUT6 P03_7/CLK /OUT7 P13_6 /PPG18/IN8 P13_7 /PPG19/IN9 P06_0 /AN0/PPG0/CS0_R P06_1/AN /PPG1/CS1_R AVcc
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
IN
P05_6/AN14/INT4_R P05_7/AN15/INT5_R/OUT10_R P05_3/AN11/TIN3/WOT P05_4/AN12/TOT3/INT2_R P05_1/AN9/SOT2 P05_2/AN10/SCK2 P04_2/IN6/RX1/INT9_R/TTG6/TTG14 P17_6/OUT11/IN10/TTG18/INT3_R P05_5/AN13/ INT0_R/NMI_R P07_0/AN16/INT0/NMI
LQFP-80
FPT-80P-M21
Package code(mold)
EL IM
1 2 3 4 5 6 78 AVRH P06_2 /AN2/PPG2/CS2_R P07_1/AN17/INT1 AVss P05_0/AN8/SIN2 /INT3_R1 P06_3/AN3/PPG3/CS3_R P06_4/AN4/PPG4/CS4_R P06_5/AN5/PPG5/CS5_R P06_6/AN6/PPG6 P06_7/AN7/PPG7
9 10 11 12 13 14 15 16 17 18 19 20
1) Devices with suffix W: X0A/X1A Devices with suffix S: P04_0, P04_1
PR
(FPT-80P-M21)
FME/EMDC- 2007-02-12
AR
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 MD_0 MD_1 MD_2 Vss Vcc
P01_1/AD09/TOT1/CKOTX1/TTG17_R
P01_2/AD10/SIN3/INT11_R/TTG18_R
P01_6/AD14/SOT2_R/PPG18_R
P01_7/AD15/SCK2_R/PPG19_R
P02_7 /A23/IN3/TTG3/ TTG11
P09_3/PPG11/CS4/FRCK2_R
P02_2/A18/PPG14/CKOT0_R
P02_0/A16/PPG12/CKOT1_R
P01_4/AD12/SCK3/PPG16_R
P02_6/A22/IN2/TTG2/ TTG10
P01_3/AD11/SOT3/TTG19_R
P02_4/A20/IN0/TTG0/TTG8
P09_2/PPG10/CS5
P02_3/A19/PPG15
P02_1/A17/PPG13
RSTX
Vss
X0
X1
Y
P01_0/AD08/TIN1/CKOT1/TTG16_R P09_1 /PPG9/LBX P09_0 /PPG8/UBX P00_7 /AD07/INT15/PPG11_R P00_6 /AD06/INT14/PPG10_R P00_5/AD05/NT13/SIN8_R/PPG9_R P00_4/AD04/INT12/SOT8_R/PPG8_R P00_3/AD03/INT11/SCK8_R/TTG11_R P00_2/AD02/INT10/SIN7_R/TTG10_R P00_1 /AD01/INT9/SOT7_R/TTG9_R P00_0/AD00/INT8/SCK7_R/TTG8_R P17_7/TX3/IN11/TTG19 X1A*/P04_1* X0A*/P04_0* P04_3/IN7/TX1/TTG7/TTG15
MB96300_shortspec.fm
11
MB96300 Series
Preliminary Specification
Pin assignment of MB96(F)34x (QFP package)
P08_0/TIN0/CKOTX0/ADTG/INT12_R P08_1/TOT0/CKOT0/INT13_R P00_3/AD03/INT11/SCK8_R2)
P00_2/AD02/INT10/SIN7_R2)
P00_1/AD01/INT9/SOT7_R2)
P00_0/AD00/INT8/SCK7_R2)
P07_6/AN22/INT6/SOT9_R2)
P07_7/AN23/INT7/SIN9_R2)
P08_2/SIN0/TIN2/INT14_R
P08_4/SCK0/INT15_R
P08_5/SIN1/INT1_R
P10_0/RX0/INT8_R
P09_3/PPG11/CS4
P09_2/PPG10/CS5
P08_3/SOT0/TOT2
P09_0/PPG8/UBX
P09_7/OUT3/CS0
P09_6/OUT2/CS1
P09_5/OUT1/CS2
P09_4/OUT0/CS3
P09_1/PPG9/LBX
P08_7/SCK1
P08_6/SOT1
P10_1/TX0
RSTX
MD0
MD1
P00_4/AD04/INT12/SOT8_R2) P00_5/AD05/INT13/SIN8_R2) P00_6/AD06/INT14 P00_7/AD07/INT15 P01_0/AD08/CKOT1/TIN1 P01_1/AD09/CKOTX1/TOT1 P01_2/AD10/INT11_R/SIN3 P01_3/AD11/SOT3 P01_4/AD12/SCK3 Vcc Vss X1 X0 P01_5/AD13/INT7_R/SIN2_R P01_6/AD14/SOT2_R P01_7/AD15/SCK2_R P02_0/A16/PPG12 P02_1/A17/PPG13 P02_2/A18/PPG14 P02_3/A19/PPG15
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8
Y
P05_4/AN12/TOT3/INT2_R P04_6/SDA1 P05_1/AN9/ALARM1/SOT2 P05_0/AN8/ALARM0/SIN2/INT3_R1 P05_2/AN10/SCK2 P04_7/SCL1 P05_3/AN11/TIN3/WOT P05_5/AN13/INT0_R/NMI_R
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P07_5/AN21/INT5/SCK9_R2) P07_4/AN20/INT4 P07_3/AN19/INT3 P07_2/AN18/INT2 P07_1/AN17/INT1 P07_0/AN16/INT0/NMI Vss P06_7/AN7/PPG7 P06_6/AN6/PPG6 P06_5/AN5/PPG5 P06_4/AN4/PPG4 P06_3/AN3/PPG3 P06_2/AN2/PPG2 P06_1/AN1/PPG1 P06_0/AN0/PPG0 AVss AVRL AVRH AVcc P05_7/AN15/INT5_R
QFP - 100
Package code (mold) FPT-100P-M22
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
IM
P03_3/WRHX P03_4/HRQ/OUT4 P03_5/HAKX/OUT5 P03_6/RDY/OUT6 Vcc P03_7/CLK/OUT7 P03_2/WRLX/WRX/INT10_R
1)
IN
Vss
P02_5/A21/TTG9/TTG1/IN1/ADTG_R
P03_1/RDX/IN5/TTG5/TTG13
P03_0/ALE/IN4/TTG4/TTG12
P04_5/SCL0/FRCK1
AR
P04_2/IN6/RX1/INT9_R/TTG6/TTG14 P04_3/IN7/TX1/TTG7/TTG15 P04_4/SDA0/FRCK0 C
P02_4/A20/TTG8/TTG0/IN0
P02_6/A22/IN2/TTG2/TTG10
P02_7/A23/IN3/TTG3/TTG11
Devices with suffix W: X0A/X1A Devices with suffix S: P04_0, P04_1 2) SIN7_R, SOT7_R, SCK7_R, SIN8_R, SOT8_R, SCK8_R, SIN9_R, SOT9_R, SCK9_R only available on MB96F348R/Y
1)
PR EL
(FPT-100P-M22)
Remark:
MB96(F)34x products are pin-compatible to F2MC-16LX family MB90340 series.
12
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
P05_6/AN14/INT4_R
X0A /P04_0
X1A /P04_1
1)
1)
1)
MD2
Vss
Vcc
Preliminary Specification
Pin assignment of MB96(F)34x (LQFP package)
P08_0/TIN0/CKOTX0/ADTG/INT12_R P07_6/AN22/INT6/AIN2/SOT9_R2) P07_7/AN23/INT7/AIN3/SIN9_R2) P08_1/TOT0/CKOT0/INT13_R
MB96300
P00_0/AD00/INT8/SCK7_R2)
P08_2/SIN0/TIN2/INT14_R
P08_4/SCK0/INT15_R
P08_5/SIN1/INT1_R
P10_0/RX0/INT8_R
P09_3/PPG11/CS4
P09_2/PPG10/CS5
P08_3/SOT0/TOT2
P09_0/PPG8/UBX
P09_7/OUT3/CS0
P09_6/OUT2/CS1
P09_5/OUT1/CS2
P09_4/OUT0/CS3
P09_1/PPG9/LBX
P08_7/SCK1
P08_6/SOT1
P10_1/TX0
RSTX
P00_1AD01/INT9/SOT7_R2) P00_2/AD02/INT10/SIN7_R2) P00_3/AD03/INT11/SCK8_R2) P00_4/AD04/INT12/SOT8_R2) P00_5/AD05/INT13/SIN8_R2) P00_6/AD06/INT14 P00_7/AD07/INT15 P01_0/AD08/CKOT1/TIN1 P01_1/AD09/CKOTX1/TOT1 P01_2/AD10/INT11_R/SIN3 P01_3/AD11/SOT3 P01_4/AD12/SCK3 Vcc Vss X1 X0 P01_5/AD13/INT7_R/SIN2_R P01_6/AD14/SOT2_R P01_7/AD15/SCK2_R P02_0/A16/PPG12 P02_1/A17/PPG13 P02_2/A18/PPG14 P02_3/A19/PPG15 P02_4/A20/TTG8/TTG0/IN0 P02_5/A21/TTG9/TTG1/IN1/ADTG_R
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
MD0
Vss
Vcc
MD1 MD2 P07_5/AN21/INT5/SCK9_R2)
AR
P04_4/SDA0/FRCK0 P04_6/SDA1 P05_1/AN9/ALARM1/SOT2 C P04_3/IN7/TX1/TTG7/TTG15 P04_2/IN6/RX1/INT9_R/TTG6/TTG14 P05_0/AN8/ALARM0/SIN2/INT3_R1 P04_5/SCL0/FRCK1 P05_2/AN10/SCK2 P04_7/SCL1
LQFP - 100
Package code (mold) FPT-100P-M20
IN
1 2 3 4 5 6 78 P03_6/RDY/OUT6 Vcc P02_6/A22/IN2/TTG2/TTG10 P02_7/A23/IN3/TTG3/TTG11 P03_1/RDX/IN5/TTG5/TTG13 P03_2/WRLX/WRX/INT10_R P03_0/ALE/IN4/TTG4/TTG12 P03_5/HAKX/OUT5 P03_4/HRQ/OUT4 P03_7/CLK/OUT7 P03_3/WRHX X0A1)/P04_01)
EL IM
100 X1A1)/P04_11)
26 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P05_3/AN11/TIN3/WOT Vss
PR
Devices with suffix W: X0A/X1A Devices with suffix S: P04_0, P04_1 2) SIN7_R, SOT7_R, SCK7_R, SIN8_R, SOT8_R, SCK8_R, SIN9_R, SOT9_R, SCK9_R only available on MB96F348R/Y
1)
(FPT-100P-M20)
Remark:
MB96(F)34x products are pin-compatible to F2MC-16LX family MB90340 series.
FME/EMDC- 2007-02-12
Y
P07_4/AN20/INT4 P07_3/AN19/INT3 P07_2/AN18/INT2 P07_1/AN17/INT1 P07_0/AN16/INT0/NMI Vss P06_7/AN7/PPG7 P06_6/AN6/PPG6 P06_5/AN5/PPG5 P06_4/AN4/PPG4 P06_3/AN3/PPG3 P06_2/AN2/PPG2 P06_1/AN1/PPG1 P06_0/AN0/PPG0 AVss AVRL AVRH AVcc P05_7/AN15/INT5_R P05_6/AN14/INT4_R P05_5/AN13/INT0_R/NMI_R P05_4/AN12/TOT3/INT2_R
MB96300_shortspec.fm
13
MB96300 Series
Pin assignment of MB96(F)35x
Preliminary Specification
P01_5/AD13/SIN2_R/INT7_R/PPG17_R
Vcc C P02_5/A21/TTG9/TTG1/IN1/ADTG_R P04_4/SDA0/FRCK0/TIN0_R P04_5/SCL0/FRCK1/TIN2_R P03_0/ALE/IN4/TTG4/TTG12/TOT0_R P03_1/RDX/IN5/TTG5/TTG13/TOT2_R P03_2/WRLX/WRX/RX2/INT10_R P03_3/TX2/WRHX P03_4/HRQ/OUT4 P03_5/HAKX/OUT5 P03_6/RDY/OUT6 P03_7/CLK/OUT7 P06_0/AN0/PPG0/CS0_R P06_1/AN1/PPG1/CS1_R AVcc
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 AVss 2 AVRH 3 P06_2/AN2/PPG2/CS2_R 4 P06_3/AN3/PPG3/CS3_R 31 30 29 28 27 26 25 24 23 22 21 20 19 18
LQFP - 64
Package code (mold) FPT-64P-M23/M24
IN
5 6 7 8 P05_1/AN9/SOT2 P06_4/AN4/PPG4/CS4_R P06_5/AN5/PPG5/CS5_R P06_6/AN6/PPG6 P06_7/AN7/PPG7 P05_4/AN12/TOT3/INT2_R P05_0/AN8/SIN2/INT3_R1 P05_3/AN11/TIN3/WOT P05_2/AN10/SCK2
P05_5/AN13/INT0_R/NMI_R
P05_6/AN14/INT4_R
1) Devices with suffix W: X0A/X1A Devices with suffix S: P04_0, P04_1
Remark:
MB96(F)35x products are pin-compatible to F2MC-16LX family MB90350 series.
14
FME/EMDC- 2007-02-12
PR EL
(FPT-64P-M23/M24)
P04_2/IN6/RX1/INT9_R/TTG6/TTG14
IM
AR
17 9 10 11 12 13 14 15 16
Y
MD0 MD1 MD2 X1A*/P04_1* X0A*/P04_0* Vss
P01_1/AD09/CKOTX1/TOT1/TTG17_R
P01_2/AD10/INT11_R/SIN3/TTG18_R
P01_6/AD14/SOT2_R/PPG18_R
P01_7/AD15/SCK2_R/PPG19_R
P02_2/A18/PPG14/CKOT0_R
P02_0/A16/PPG12/CKOT1_R
P01_4/AD12/SCK3/PPG16_R
P01_3/AD11/SOT3/TTG19_R
P02_4/A20/TTG8/TTG0/IN0
P02_3/A19/PPG15
P02_1/A17/PPG13
RSTX
Vss
X0
X1
P01_0/AD08/CKOT1/TIN1/TTG16_R P00_7/AD07/INT15/PPG11_R P00_6/AD06/INT14/PPG10_R P00_5/AD05/INT13/SIN8_R/PPG9_R P00_4/AD04/INT12/SOT8_R/PPG8_R P00_3/AD03/INT11/SCK8_R/TTG11_R P00_2/AD02/INT10/SIN7_R/TTG10_R P00_1/AD01/INT9/SOT7_R/TTG9_R P00_0/AD00/INT8/SCK7_R/TTG8_R
P04_3/IN7/TX1/TTG7/TTG15
MB96300_shortspec.fm
Preliminary Specification
Pin assignment of MB96(F)36x
P02_5/TTG9/TTG1/IN1/ADTG_R
MB96300
P02_0/PPG12/CKOT1_R
P02_2/PPG14/CKOT0_R
P02_6/IN2/TTG2/TTG10
P02_7/IN3/TTG3/TTG11
P02_4/TTG8/TTG0/IN0
P02_1/PPG13
P02_3/PPG15
36 35 34 33 32 31 30 29 28 27 26 25 P08_5/SIN1/INT1_R P08_7/SCK1 P08_6/SOT1 P04_3/TX1/TTG7/TTG15 P04_2/RX1/INT9_R/TTG6/TTG14 P08_3/SOT0/TOT2 P08_4/SCK0/INT15_R P08_2/SIN0/TIN2/INT14_R P04_4/FRCK0 X0A*/P04_0* X1A*/P04_1* AVss 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 15 14 Vcc
C Vss
X1
X0
LQFP-48
Package code (mold) FPT-48P-M26
P06_4/AN4/PPG4
P06_7/AN7/PPG7
P06_0/AN0
P06_1/AN1
P06_2/AN2
P06_3/AN3
P08_0/ADTG/CKOTX0/INT12_R
P06_5/AN5/PPG5
P06_6/AN6/PPG6
* Devices with suffix W: X0A/X1A Devices with suffix S: P04_0, P04_1
Remark:
MB96(F)36x products are pin-compatible to F2MC-16LX family MB90360 series
FME/EMDC- 2007-02-12
PR
EL IM
(FPT-48P-M26)
IN
MB96300_shortspec.fm
P05_0/AN8/SIN2/INT3_R1
AR
P05_2/AN10 P05_1/AN9 13 9 10 11 12
AVRH
AVcc
Y
MD0 MD1 MD2 P05_7/AN15/INT5_R P05_6/AN14/INT4_R P05_5/AN13/INT0_R/NMI_R P05_4/AN12/TOT3/INT2_R P05_3/AN11/TIN3
RSTX
15
MB96300 Series
Pin assignment of MB96(F)38x
Preliminary Specification
Y
114 115 116 117 118 119 120 1 2 3 4 5 6
IM
8
Vss P00_3/INT6_R/A00/CS3_R/SEG15 P00_4/INT7_R/ALE/SEG16 P00_5/TTG2/IN6/RDX/SEG17 P00_6/TTG3/IN7/WRLX/WRX/SEG18 P00_7/SGO0/CLK/SEG19 P01_0/SGA0/AD00/SEG20 P01_1/OUT0/CKOT1/AD01/SEG21 P01_2/OUT1/CKOTX1/AD02/SEG22 P01_3/PPG5/AD03/SEG23 P01_4/AD04/SIN4/SEG24 P01_5/AD05/SOT4/SEG25 P01_6/AD06/SCK4/SEG26 P01_7/CKOTX1_R/AD07/SEG27 P02_0/CKOT1_R/AD08/SEG28 P02_1/IN6_R/AD09/SEG29 P02_2/IN7_R/AD10/SEG30 P02_3/SGO0_R/AD11/SEG31 P02_4/SGA0_R/AD12/SEG32 P02_5/OUT0_R/AD13/SEG33 P02_6/OUT1_R/AD14/SEG34 P02_7/PPG5_R/AD15/SEG35 P03_0/V0/A16/SEG36 P03_1/V1/A17/SEG37 P03_2/V2/A18/SEG38 P03_3/V3/A19/SEG39 P03_4/INT4/RX0 P03_5/TX0 P03_6/NMI/INT0 Vcc
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Vcc P00_2/INT5_R/RDY/SEG14 P00_1/INT4_R/WRHX/SEG13 P00_0/INT3_R/HAKX/SEG12 P12_7/INT1_R/HRQ/SEG11 P12_6/TOT2_R/A15/SEG10 P12_5/TIN2_R/A14/SEG9 P12_4/OUT3_R/A13/SEG8 P12_3/OUT2_R/A12/SEG7 P12_2/TOT1_R/A11/SEG6 P12_1/TIN1_R/A10/SEG5 P12_0/IN1_R/A09/SEG4 P11_7/IN0_R/A08/SEG3 P11_6/FRCK0_R/A07/SEG2 P11_5/PPG4_R/A06/SEG1 P11_4/PPG3_R/A05/SEG0 P11_3/PPG2_R/A04/COM3 P11_2/PPG1_R/A03/COM2 P11_1/PPG0_R/A02/COM1 P11_0/A01/COM0/CS5 RSTX X1A/P04_1 1) X0A/P04_0 1) Vss X1 X0 MD2 MD1 MD0 Vss
LQFP - 120
Package code (mold) FPT-120P-M21
7
31 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Vcc P10_3/PWM2M4/PPG7 P10_2/PWM2P4/SCK2/PPG6 P10_1/PWM1M4/SOT2/TOT3 P10_0/PWM1P4/SIN2/TIN3 P09_7/PWM2M3 DVss DVcc P09_6/PWM2P3 P09_5/PWM1M3 P09_4/PWM1P3 P09_3/PWM2M2 P09_2/PWM2P2 P09_1/PWM1M2 P09_0/PWM1P2 P08_7/PWM2M1 P08_6/PWM2P1 P08_5/PWM1M1 DVss DVcc P08_4/PWM1P1 P08_3/PWM2M0 P08_2/PWM2P0 P08_1/PWM1M0 P08_0/PWM1P0 P05_7/AN15/TOT2/SGA1_R/SEG64 P05_6/AN14/TIN2/SGO1_R/SEG63 P05_5/AN13/TX1/SEG62 3) P05_4/AN12/RX1/INT2_R/SEG61 3) Vss
1) Devices with suffix W: X0A/X1A Devices with suffix S: P04_0, P04_1 2) MB96384/5: Alarm1 not available 3) MB96384/5: TX1 resp. RX1 not available
16
FME/EMDC- 2007-02-12
PR EL
Vss C P03_7/INT1/SIN1/CS0/A20/SEG40 P13_0/INT2/SOT1/CS1/A21/SEG41 P13_1/INT3/SCK1/CS2/A22/SEG42 P13_2/PPG0/TIN0/FRCK1/CS3/A23/SEG43 P13_3/PPG1/TOT0/WOT/UBX/SEG44 P13_4/SIN0/INT6/SEG45 P13_5/SOT0/ADTG/INT7/SEG46 P13_6/SCK0/CKOTX0/LBX/SEG47 P13_7/PPG2/CKOT0/CS4/SEG48 P04_4/PPG3/SDA0 P04_5/PPG4/SCL0 P06_0/AN0/SCK5/IN2_R/SEG49 P06_1/AN1/SOT5/IN3_R/SEG50 P06_2/AN2/INT5/SIN5/SEG51 P06_3/AN3/FRCK0/SEG52 P06_4/AN4/IN0/TTG0/TTG4/SEG53 P06_5/AN5/IN1/TTG1/TTG5/SEG54 P06_6/AN6/TIN1/IN4_R/SEG55 P06_7/AN7/TOT1//IN5_R/SEG56 AVcc AVRH AVRL/AVRH2 AVss P05_0/AN8/ALARM0/SEG57 2) P05_1/AN9/ALARM1/SEG58 P05_2/AN10/OUT2/SGO1/SEG59 P05_3/AN11/OUT3/SGA1/SEG60 Vcc
(FPT-120P-M21)
IN
AR
MB96300_shortspec.fm
Preliminary Specification
MB96300
s PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x Pin no. MB9632 x
LQFP80*5
MB9634x
LQFP100*2
MB9635 x
LQFP64*3
MB9636 x
LQFP48*4
Pin name
Circuit type
Function
QFP100*1
58 59 55
90 91 52
92 93 54
46 47 45
28 27 23
X1 A X0 RSTX P00_0
Oscillation output
AR
AD00
75 30
77 24
IN
INT8 INT9
SCK7_R TTG8_R P00_1
EL IM
25
AD01
76 31
78
PR
SOT7_R TTG9_R
FME/EMDC- 2007-02-12
Y
E H H
Oscillation input Reset input
General purpose I/O External bus interface (nonmultiplexed mode) data line External bus interface (multiplexed mode) address/ data line External interrupt request input pin for INT8 Relocated USART7 serial clock I/O (not available on MB96F348H/T) Relocated PPG8 trigger General purpose I/O External bus interface (nonmultiplexed mode) data line External bus interface (multiplexed mode) address/ data line External interrupt request input pin for INT9 Relocated USART 7 serial data output (not available on MB96F348H/T) Relocated PPG9 trigger
MB96300_shortspec.fm
17
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x Pin no. MB9632 x
LQFP80*5
MB9634x
LQFP100*2
MB9635 x
LQFP64*3
MB9636 x
LQFP48*4
Pin name
Circuit type
Function
QFP100*1
P00_2
General purpose I/O External bus interface (nonmultiplexed mode) data line External bus interface (multiplexed mode) address/ data line External interrupt request input pin for INT10 Relocated USART 7 serial data input (not available on MB96F348H/T) Relocated PPG10 trigger General purpose I/O External bus interface (nonmultiplexed mode) data line External bus interface (multiplexed mode) address/ data line H External interrupt request input pin for INT11 Relocated USART8 serial clock I/O (not available on MB96F348H/T) Relocated PPG11 trigger
AD02 77 32 79 26
IM
78 33
80
27
PR EL
18 FME/EMDC- 2007-02-12
IN
AR
H INT10 SIN7_R TTG10_R P00_3 AD03 INT11 SCK8_R TTG11_R
Y
MB96300_shortspec.fm
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x Pin no. MB9632 x
LQFP80*5
MB96300
MB9634x
LQFP100*2
MB9635 x
LQFP64*3
MB9636 x
LQFP48*4
Pin name
Circuit type
Function
QFP100*1
P00_4
General purpose I/O External bus interface (nonmultiplexed mode) data line External bus interface (multiplexed mode) address/ data line External interrupt request input pin for INT12 Relocated USART 8 serial data output (not available on MB96F348H/T) Relocated Programmable Pulse Generator outputs General purpose I/O External bus interface (nonmultiplexed mode) data line External bus interface (multiplexed mode) address/ data line H External interrupt request input pin for INT13 Relocated USART8 serial clock I/O (not available on MB96F348H/T) Relocated Programmable Pulse Generator outputs
AD04 79 34 81 28
EL IM
29
80 35
82
FME/EMDC- 2007-02-12
PR
IN
AR
INT12 H SOT8_R PPG8_R P00_5 AD05 INT13 SCK8_R PPG9_R
Y
MB96300_shortspec.fm
19
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x Pin no. MB9632 x
LQFP80*5
MB9634x
LQFP100*2
MB9635 x
LQFP64*3
MB9636 x
LQFP48*4
Pin name
Circuit type
Function
QFP100*1
P00_6 to P00_7
General purpose I/O External bus interface (nonmultiplexed mode) data lines External bus interface (multiplexed mode) address/ data lines External interrupt request input pins for INT14 to INT15 Relocated Programmable Pulse Generator outputs General purpose I/O External bus interface (nonmultiplexed mode) data line External bus interface (multiplexed mode) address/ data line Reload Timer 1 event input pin Clock Output Function 1 clock output Relocated PPG16 trigger input General purpose I/O External bus interface (nonmultiplexed mode) data line External bus interface (multiplexed mode) address/ data line Reload Timer 1 output Clock Output Function 1 inverted Clock Output Relocated PPG17 trigger
81 to 82 36 to 37
83 to 84 30 to 31
83 40
85
IM
IN
32
PR EL
86 33
84 41
20
FME/EMDC- 2007-02-12
AR
H INT14 to INT15 PPG10_R to PPG11_R P01_0 AD08 H TIN1 CKOT1 TTG16_R P01_1 AD09 H TOT1 CKOTX1 TTG17_R
AD06 to AD07
Y
MB96300_shortspec.fm
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x Pin no. MB9632 x
LQFP80*5
MB96300
MB9634x
LQFP100*2
MB9635 x
LQFP64*3
MB9636 x
LQFP48*4
Pin name
Circuit type
Function
QFP100*1
P01_2
General purpose I/O External bus interface (nonmultiplexed mode) data line External bus interface (multiplexed mode) address/ data line USART 3 serial data input Relocated external interrupt request input for INT11 Relocated PPG18 trigger General purpose I/O External bus interface (nonmultiplexed mode) data line External bus interface (multiplexed mode) address/ data line USART 3 serial data output Relocated PPG19 trigger General purpose IO External bus interface (nonmultiplexed mode) data line External bus interface (multiplexed mode) address/ data line USART 3 clock I/O Relocated Pulse Programable output
AD10 85 42 87 34 SIN3
86 43
88 35
IN
EL IM
36
87 44
89
PR
FME/EMDC- 2007-02-12
AR
INT11_R TTG18_R P01_3 AD11 H SOT3 TTG19_R P01_4 AD12 H SCK3 PPG16_R
Y
H
MB96300_shortspec.fm
21
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x Pin no. MB9632 x
LQFP80*5
MB9634x
LQFP100*2
MB9635 x
LQFP64*3
MB9636 x
LQFP48*4
Pin name
Circuit type
Function
QFP100*1
P01_5
General purpose IO External bus interface (nonmultiplexed mode) data line External bus interface (multiplexed mode) address/ data line Relocated external interrupt request pin for INT7 Relocated USART 2 serial data input Relocated Pulse Programable output General purpose IO External bus interface (nonmultiplexed mode) data line External bus interface (multiplexed mode) address/ data line Relocated USART2 serial data output Relocated Pulse Programable output General purpose IO External bus interface (nonmultiplexed mode) data line External bus interface (multiplexed mode) address/ data line Relocated USART2 clock I/O Relocated Pulse Programable output
AD13 92 45 94 37
IM
93 46
95
38
IN PR EL
96 39 94 47 22 FME/EMDC- 2007-02-12
AR
H INT7_R SIN2_R PPG17_R P01_6 AD14 H SOT2_R PPG18_R P01_7 AD15 H SCK2_R PPG19_R
Y
MB96300_shortspec.fm
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x Pin no. MB9632 x
LQFP80*5
MB96300
MB9634x
LQFP100*2
MB9635 x
LQFP64*3
MB9636 x
LQFP48*4
Pin name
Circuit type
Function
QFP100*1
P02_0 36 95 50 97 40 A16 36 CKOT1_R P02_1 PPG12 H
General purpose IO Programmable Pulse Generator outputs External bus interface address output Relocated Clock Output Function 1 clock output General purpose IO Programmable Pulse Generator output External bus interface address output General purpose IO Programmable Pulse Generator output H External bus interface address output Relocated Clock Output Function 0 clock output General purpose IO H Programmable Pulse Generator output External bus interface address output General purpose IO Input Capture Unit 0 data sample input H Programmable Pulse Generator PPG0 and PPG8 trigger input External bus interface address output
35 51 96 98 41
52
EL IM
42 34 43 33 32 44
97
99
53
98
100
PR
1
54
99
FME/EMDC- 2007-02-12
IN
A17 34 A18 A19 IN0 A20
AR
H PPG13 P02_2 PPG14 CKOT0_R P02_3 PPG15 P02_4 TTG0/ TTG8
Y
MB96300_shortspec.fm
23
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x Pin no. MB9632 x
LQFP80*5
MB9634x
LQFP100*2
MB9635 x
LQFP64*3
MB9636 x
LQFP48*4
Pin name
Circuit type
Function
QFP100*1
P02_5 31 ADTG_R IN1 65 100 1 51 TTG1/ TTG9 A21
General purpose IO
AR IN
30, 29 P02_6, P02_7 IN2, IN3 TTG2/ TTG10, TTG3/ TTG11 H A22, A23 P03_0 IN4 ALE H TTG4/ TTG12 TOT0_R
IM
54
56, 57
1, 2
3, 4
PR EL
5
3 68
24
FME/EMDC- 2007-02-12
Y
H
Relocated A/D converter trigger input Input Capture Unit ICU 1 data sample input Programmable Pulse Generator PPG1 and PPG9 trigger External bus interface address output General purpose IO Input Capture Unit ICU2 to ICU3 data sample input Programmable Pulse Generator PPG2 and PPG10 trigger, Programmable Pulse Generator PPG3 and PPG11 trigger External bus interface address outputs General purpose IO Input Capture Unit 4 data sample input External bus interface address latch enable output pin Programmable Pulse Generator PPG4 and PPG12 trigger Reload Timer 0 relocated output
MB96300_shortspec.fm
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x Pin no. MB9632 x
LQFP80*5
MB96300
MB9634x
LQFP100*2
MB9635 x
LQFP64*3
MB9636 x
LQFP48*4
Pin name
Circuit type
Function
QFP100*1
P03_1 RDX 4 69 6 55 IN5 TTG5/ TTG13
General purpose IO External bus interface read strobe output Input Capture Unit ICU 5 data sample input Programmable Pulse Generator PPG5 and PPG13 trigger Reload Timer 2 relocated output General purpose IO External bus (16-bit data mode) interface low byte write strobe output pin External bus (8-bit data mode) interface write strobe output pin Relocated external interrupt request input for INT10 CAN2 interface RX input (not available on MB96F3xxA, MB96F3xxC) General purpose IO External bus interface write strobe output pin for the 8 higher bits of the data bus CAN2 interface TX output pin (not available on MB96F3xxA, MB96F3xxC) General purpose IO H External bus interface hold request input Output Compare Unit OCU4 waveform output
5 70
7 56
EL IM
57 58
IN
RX2 TX2 HRQ
6 71
8
PR
7 9
72
FME/EMDC- 2007-02-12
AR
TOT2_R P03_2 WRLX / WRX H INT10_R P03_3 WRHX H P03_4 OUT4
Y
H
MB96300_shortspec.fm
25
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x Pin no. MB9632 x
LQFP80*5
MB9634x
LQFP100*2
MB9635 x
LQFP64*3
MB9636 x
LQFP48*4
Pin name
Circuit type
Function
QFP100*1
P03_5 73 8 10 59 HAKX OUT5 P03_6 RDY H
General purpose IO
AR
H OUT6
74
9
11
60
IN
46, 47 41
P03_7 CLK H
75
10
12
61
IM
OUT7 P04_0, P04_1 X0A, X1A P04_2 IN6 H
24,25
11, 12
13, 14
19, 20
PR EL
18 16
RX1 H INT9_R TTG6/ TTG14
19
16
26
FME/EMDC- 2007-02-12
Y
B
External bus interface hold acknowledge output Output Compare Unit OCU5 waveform output General purpose IO External bus interface external wait state request Output Compare Unit OCU6 waveform output General purpose IO External bus interface clock output pin Output Compare Unit OCU7 waveform output pin
General purpose IO (only for devices with S-suffix) Oscillator input pins for subclock (only for devices without S-suffix) General purpose IO Input Capture Unit ICU6 data sample input CAN1 Interface RX input (not available on MB96F3xxA, MB96F3xxC) Relocated external interrupt request input pin for INT9 Programmable Pulse Generators PPG6 and PPG14 trigger
MB96300_shortspec.fm
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x Pin no. MB9632 x
LQFP80*5
MB96300
MB9634x
LQFP100*2
MB9635 x
LQFP64*3
MB9636 x
LQFP48*4
Pin name
Circuit type
Function
QFP100*1
P04_3 IN7 TTG7/ TTG15
General purpose IO Input Capture Unit ICU7 data sample input Programmable Pulse Generators PPG7 and PPG15 trigger CAN1 Interface TX Output pin (not available on MB96F3xxA, MB96F3xxC) General purpose IO Free Running Timer 0 input N I2C 0 interface serial data I/O Reload Timer 0 event relocated input pin General purpose IO I2C 0 interface serial clock I/ O Free Running Timer 1 input Reload Timer 2 event relocated input pin General purpose IO N I2C 1 interface serial data I/O General purpose IO N I2C 1 interface serial clock I/ O
21
17
19
17
40
18 66
20 52
EL IM
35 53
19 67
21
IN
45
20
22
PR
23
21
FME/EMDC- 2007-02-12
AR
TX1 P04_4 FRCK0 SDA0 TIN0_R P04_5 SCL0 N FRCK1 TIN2_R P04_6 SDA1 P04_7 SCL1
Y
H
MB96300_shortspec.fm
27
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x Pin no. MB9632 x
LQFP80*5
MB9634x
LQFP100*2
MB9635 x
LQFP64*3
MB9636 x
LQFP48*4
Pin name
Circuit type
Function
QFP100*1
P05_0 AN8 10 22 24 9 12 SIN2
General purpose IO
AR
INT3_R1 ALARM0 P05_1 AN9 I SOT2 ALARM1 P05_2 AN10 SCK2 P05_3 AN11 TIN3 WOT P05_4 AN12 I I TOT3 INT2_R P05_5 AN13 I I INT0_R NMI_R
13 11 23 25 10
IN
11
12
24
26
IM
15 16 17
14
13
25
PR EL
27 12 28 13 29 14
14
26
15
27
28
FME/EMDC- 2007-02-12
Y
I
A/D converter analog input pin USART2 serial data input
Relocated input of external interrupt INT3 Alarm Comparator 0 input General purpose IO A/D converter analog input USART 2 serial data output Alarm Comparator 1 input General purpose IO A/D converter analog input USART 2 clock I/O General purpose IO A/D converter analog input Reload Timer 3 event input Real Timer clock output General purpose IO A/D converter analog input Output pin for the reload timer 3 Relocated input of external interrupt INT2 General purpose IO A/D converter analog input Relocated External interrupt INT0 input Relocated Non-Maskable Interrupt NMI MB96300_shortspec.fm
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x Pin no. MB9632 x
LQFP80*5
MB96300
MB9634x
LQFP100*2
MB9635 x
LQFP64*3
MB9636 x
LQFP48*4
Pin name
Circuit type
Function
QFP100*1
P05_6 16 28 30 15 18 AN14 INT4_R P05_7 AN15 I
General purpose IO A/D converter analog input Relocated External Interrupt INT4 input General purpose IO A/D converter analog input Relocated External Interrupt INT5 input Output Compare Unit OCU10 waveform reloacted output pin General purpose IO A/D converter analog input I Programmable Pulse Generator outputs External Chip selects relocated output General purpose IO A/D converter analog input I Programmable Pulse Generator outputs External Chip select relocated output General purpose IO I A/D converter analog input Programmable Pulse Generator outputs
29 17
31
19
78,79, 3 to 5
EL IM
62, 63, 3 to 5 6 6 7 7
34 to 38
36 to 40
62, 63, 3 to 5
39 6
41
PR
42
7
40
FME/EMDC- 2007-02-12
IN
AN5 AN6
AR
I INT5_R OUT10_R P06_0 to P06_4 AN0 to AN4 PPG0 to PPG4 CS0_R to CS4_R P06_5 PPG5 CS5_R P06_6 PPG6
Y
MB96300_shortspec.fm
29
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x Pin no. MB9632 x
LQFP80*5
MB9634x
LQFP100*2
MB9635 x
LQFP64*3
MB9636 x
LQFP48*4
Pin name
Circuit type
Function
QFP100*1
P06_7 10 8 41 43 8 AN7 PPG7 P07_0 AN16 INT0 NMI I
General purpose IO
AR
I
18
43
45
IN IM
P07_1 I
9
44
46
AN17 to AN20 INT1 to INT4
P07_2 to P07_4 AN18to AN20 INT2 to INT4 P07_5 AN21 INT5
PR EL
47 to 49 50
45 to 47
48
SCK9_R
30
FME/EMDC- 2007-02-12
Y
I I
A/D converter analog input
Programmable Pulse Generator output General purpose IO A/D converter analog input External interrupt INT0 request input Non-Maskable Interrupt NMI input
General purpose IO A/D converter analog input External interrupt INT1 to INT4 request input General purpose IO A/D converter analog input External interrupt INT2 to INT4 request input General purpose IO A/D converter analog input External interrupt INT5 request input Relocated USART9 serial clock I/O (not available on MB96F348H/T)
MB96300_shortspec.fm
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x Pin no. MB9632 x
LQFP80*5
MB96300
MB9634x
LQFP100*2
MB9635 x
LQFP64*3
MB9636 x
LQFP48*4
Pin name
Circuit type
Function
QFP100*1
P07_6 AN22 53 55 INT6 I
General purpose IO A/D converter analog input
AR
SOT9_R P07_7 AN23 INT7
IN EL IM
11 44 TIN0 SIN0 TIN2
54
56
SIN9_R P08_0
CKOTX0 ADTG INT12_R H
55
57
P08_1 TOT0 CKOT0 INT13_R P08_2 H
56
PR
58
57
59
INT14_R
FME/EMDC- 2007-02-12
Y
I H
External interrupt INT6 request input Relocated USART 9 serial data output (not available on MB96F348H/T) General purpose IO A/D converter analog input External interrupt INT7 request input Relocated USART 9 serial data input (not available on MB96F348H/T) General purpose IO Clock Output Function 0 inverted output A/D converter trigger input Relocated external interrupt INT12 request input Reload Timer 0 event input General purpose IO Reload Timer 0 output Clock output function 0 output Relocated external interrupt INT13 request input General purpose IO USART 0 serial data input Reload Timer 2 event input Relocated external interrupt INT14 request input MB96300_shortspec.fm 31
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x Pin no. MB9632 x
LQFP80*5
MB9634x
LQFP100*2
MB9635 x
LQFP64*3
MB9636 x
LQFP48*4
Pin name
Circuit type
Function
QFP100*1
P08_3 58 60 42 SOT0 TOT2 P08_4 59 61 43 SCK0 H
General purpose IO
AR
H INT15_R P08_5 SIN1 H INT1_R P08_6 H SOT1 P08_7 H SCK1 P09_0 PPG8 UBX P09_1 PPG9 LBX P09_2 PPG10 CS5 H H H
IN IM
38 39
60
62
37
61
63
62
64
PR EL
67 68 69
38
65
39
66
48
67
32
FME/EMDC- 2007-02-12
Y
USART0 serial data output Reload timer 2 output
General purpose IO USART0 clock I/O Relocated external interrupt INT15 request input General purpose IO USART1 serial data input
Relocated external interrupt INT1 request input General purpose IO USART1 serial data output General purpose IO USART1 clock I/O General purpose IO Programmable Pulse Generator 8 output External Bus Interface Upper Byte select strobe General purpose IO Output pin for PPG 9 External Bus Interface Lower Byte select strobe General purpose IO Programmable Pulse Generator 10 output External Bus Interface Chip Select 5
MB96300_shortspec.fm
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x Pin no. MB9632 x
LQFP80*5
MB96300
MB9634x
LQFP100*2
MB9635 x
LQFP64*3
MB9636 x
LQFP48*4
Pin name
Circuit type
Function
QFP100*1
P09_3 49 68 70 PPG11 CS4 P09_4 to P09_7 OUT0 to OUT3 CS3 to CS0 P10_0 RX0 H
General purpose IO Programmable Pulse Generator 11 output External Bus Interface Chip Select 4 General purpose IO Output Compare Unit OCU0 to OCU3 waveform output External Bus Interface Chip Select 3 to 0 General purpose IO CAN0 interface RX input (not available on MB96F3xxA, MB96F3xxC) Relocated external interrupt INT8 request input General purpose IO H CAN0 interface TX output (not available on MB96F3xxA, MB96F3xxC) General purpose IO I Programmable Pulse Generator17 output General purpose IO Programmable Pulse Generator output Input Capture Unit ICU8, ICU9 data sample input
69 to 72
71 to 74
73
75
IN EL IM
TX0
74
76
64
PR
76,77
FME/EMDC- 2007-02-12
AR
H H INT8_R P10_1 P13_5 PPG17 P13_6 , P13_7 PPG18,P PG19 IN8,IN9 I
Y
MB96300_shortspec.fm
33
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x Pin no. MB9632 x
LQFP80*5
MB9634x
LQFP100*2
MB9635 x
LQFP64*3
MB9636 x
LQFP48*4
Pin name
Circuit type
Function
QFP100*1
P17_2 63 FRCK3 I
General purpose IO
TTG17 P17_6
AR
OCU11 IN10 I
20
IN IM PR EL
32 64 33 2 34 35 1 30 1 31 2 32 1 33 48 29 80 2 34 FME/EMDC- 2007-02-12
TTG18
INT3_R P17_7 IN11 TTG19 AVCC F I
AVRH
AVRL AVSS
Y
G F F
Free Running Timer3 input
Programmable Pulse Generators PPG17 trigger General purpose IO Output Compare Unit OCU11 waveform output pin Input Capture Unit ICU10 data sample input Programmable Pulse Generators PPG18 trigger Relocated input of external interrupt INT3 General purpose IO Input Capture Unit ICU11 data sample input Programmable Pulse Generators PPG19 trigger Analog circuits VCC power supply A/D converter upper reference voltage Supply voltage to AVCC pin must be kept higher than or equal to AVRH pin voltage specially when the supply voltage to AVRH is turned on or off A/D converter lower reference voltage Analog circuits VSS power supply
MB96300_shortspec.fm
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x Pin no. MB9632 x
LQFP80*5
MB96300
MB9634x
LQFP100*2
MB9635 x
LQFP64*3
MB9636 x
LQFP48*4
Pin name
Circuit type
Function
QFP100*1
26, 27, 28
49, 50, 51 13, 63, 88 13, 42, 64, 89
51, 52, 53 15, 65, 90 16, 44, 66, 91
21, 22, 23
20, 21, 22
MD2, MD1, MD0
C
22,61 23,60
49 18, 48
24 25
VCC VSS
AR
C F
62
15
17
50
26
FME/EMDC- 2007-02-12
PR
EL IM
MB96300_shortspec.fm
*1: FPT-100P-M22 *2: FPT-100P-M20 *3: FPT-64P-M23/M24 *4: FPT-48P-M26 *5: FPT-80P-M21
IN
Y
Input pins for specifying the operating mode The pins must be directly connected to VCC or VSS Power supply Power supply Internally regulated power supply stabilization capacitor pin. Please refer to the datasheet for recommended capacitor values.
35
MB96300 Series
s PIN DESCRIPTION FOR MB96(F)38X
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)38X Pin no. MB96(F)38x LQFP120*1 65 66 68 X0 X1 X0A P04_0 69 X1A P04_1 70 71 RSTX P11_0 A01 COM0 CS5 72 to 74 P11_1 to P11_3 A02 to A04 COM1 to COM3 J A A B H B H E J Oscillation input Oscillation output Pin name Circuit type Function
Oscillation input (only for devices without S-suffix) General purpose I/O (only for devices with S-suffix) Oscillation output (only for devices without S-suffix) General purpose I/O (only for devices with S-suffix)
General purpose I/O
External bus (non-multiplexed mode) address line LCD controller/driver common output pin
PPG0_R to PPG2_R 75, 76 P11_4, P11_5
A05, A06
SEG0, SEG1 PPG3_R, PPG4_R 77 P11_6 FRCK0_R A07 SEG2 36
FME/EMDC- 2007-02-12
PR EL
J J
IM
External bus chip select 5
General purpose I/O External bus (non-multiplexed mode) address lines
LCD controller/driver common output pins Relocated Programmable Pulse Generator 0 to 2 outputs General purpose I/O External bus (non-multiplexed mode) address lines LCD controller / driver segment outputs
Relocated Programmable Pulse Generator 3 and 4 outputs General purpose I/O Relocated Free-Running Timer 0 clock input External bus (non-multiplexed mode) address line LCD controller / driver segment output MB96300_shortspec.fm
IN
Reset input
AR
Y
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)38X Pin no. MB96(F)38x LQFP120*1 78, 79 P11_7, P12_0 IN0_R,IN1_R A08, A09 SEG3, SEG4 80 P12_1 TIN1_R A10 SEG5 81 P12_2 TOT1_R A11 SEG6 82, 83 P12_3, P12_4 OUT2_R, TOT2_R A12, A13 SEG7, SEG8 84 P12_5 TIN2_R A14 J J J General purpose I/O Input Capture Unit relocated input pin Pin name Circuit type Function
MB96300
External bus (non-multiplexed mode) address lines LCD controller / driver segment output General purpose I/O
Relocated event input pin for Reload Timer 1 External bus (non-multiplexed mode) address line LCD controller / driver segment output
Relocated output pin for Reload Timer 1 External bus (non-multiplexed mode) address line
PR
J
SEG9 85
P12_6
TOT2_R A15 SEG10
FME/EMDC- 2007-02-12
EL IM
J J
LCD controller / driver segment output
General purpose I/O Relocated waveform output pins of Output Compare Units External bus (non-multiplexed mode) address lines LCD controller / driver segment outputs
General purpose I/O Relocated event input pin for Reload Timer 2
External bus (non-multiplexed mode) address line LCD controller / driver segment output General purpose I/O Relocated output pin for Reload Timer 2 External bus (non-multiplexed mode) address line LCD controller / driver segment output
IN
General purpose I/O
AR
Y
MB96300_shortspec.fm
37
MB96300 Series
PIN DESCRIPTION FOR MB96(F)38X Pin no. MB96(F)38x LQFP120*1 86 P12_7 INT1_R HRQ SEG11 87 P00_0 INT3_R HAKX SEG12 88 P00_1 INT4_R WRHX SEG13 89 P00_2 INT5_R RDY SEG14 92 P00_3 J J J J Pin name Circuit type
Preliminary Specification
Function
General purpose I/O Relocated external interrupt 1 External bus Hold Request
LCD controller / driver segment output
Relocated external interrupt 3
External bus Hold Acknowlegde
LCD controller / driver segment output General purpose I/O
Relocated external interrupt 4 External bus High byte Write strobe LCD controller / driver segment output
INT6_R A00
CS3_R
SEG15 93 P00_4
INT7_R ALE
SEG16
38
FME/EMDC- 2007-02-12
PR EL
J J
IM
General purpose I/O Relocated external interrupt 5
External bus external wait state request LCD controller / driver segment output
General purpose I/O Relocated external interrupt 6
External bus (non-multiplexed mode) address line External bus relocated Chip Select 3
LCD controller / driver segment output
General purpose I/O Relocated external interrupt 7
External bus Address Latch Enable signal LCD controller / driver segment output
IN
AR
General purpose I/O
Y
MB96300_shortspec.fm
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)38X Pin no. MB96(F)38x LQFP120*1 94 P00_5 TTG2 IN6 RDX SEG17 95 P00_6 TTG3 IN7 WRLX WRX SEG18 96 P00_7 SGO0 CLK SEG19 97 P01_0 SGA0 AD00 SEG20 98 P01_1 OUT0 J J J General purpose I/O Programmable Pulse Generator 2 trigger Pin name Circuit type Function
MB96300
External bus Read Strobe
General purpose I/O
Trigger for Programmable Pulse Generator 3 Input Capture Unit ICU7 data sample input External bus (16-bit data mode) low byte write strobe External bus (8-bit data mode) write strobe LCD controller / driver segment output General purpose I/O
PR
J
CKOT1 AD01
SEG21
FME/EMDC- 2007-02-12
EL IM
J
SGO output of Sound Generator 0 External bus clock LCD controller / driver segment output
General purpose I/O SGA output of Sound Generator 0
External bus (non-multiplexed mode) data line and External bus (multiplexed mode) address/data line LCD controller / driver segment output
General purpose I/O Output Compare Unit OCU0 waveform output Output of Clock Output function 1 External bus (non-multiplexed mode) data line and External bus (multiplexed mode) address/data line LCD controller / driver segment output
IN
AR
LCD controller / driver segment output
Y
Input Capture Unit ICU 6 data sample input
MB96300_shortspec.fm
39
MB96300 Series
PIN DESCRIPTION FOR MB96(F)38X Pin no. MB96(F)38x LQFP120*1 99 P01_2 OUT1 CKOTX1 AD02 SEG22 100 P01_3 PPG5 AD03 SEG23 101 P01_4 AD04 SIN4 SEG24 102 P01_5 AD05 J J J J Pin name Circuit type
Preliminary Specification
Function
General purpose I/O Waveform output pin for Output Compare Unit 1 Clock Output function 1 inverted output
LCD controller / driver segment output General purpose I/O
Programmable Pulse Generator 5 output External bus (non-multiplexed mode) data line and External bus (multiplexed mode) address/data line LCD controller / driver segment output General purpose I/O
SOT4
SEG25 103 P01_6 AD06
SCK4
SEG26
40
FME/EMDC- 2007-02-12
PR EL
J
IM
External bus (non-multiplexed mode) data lines and External bus (multiplexed mode) address/data lines USART 4 serial data input LCD controller / driver segment outputs General purpose I/O
External bus (non-multiplexed mode) data lines and External bus (multiplexed mode) address/data lines
USART 4 serial data output LCD controller / driver segment outputs General purpose I/O
External bus (non-multiplexed mode) data lines and External bus (multiplexed mode) address/data lines USART 1 serial clock LCD controller / driver segment outputs
IN
AR
External bus (non-multiplexed mode) data line and External bus (multiplexed mode) address/data line
Y
MB96300_shortspec.fm
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)38X Pin no. MB96(F)38x LQFP120*1 104 P01_7 CKOTX1_R AD07 SEG27 105 P02_0 CKOT1_R AD08 SEG28 106, 107 P02_1, P02_2 IN6_R, IN7_R AD09, AD10 SEG29, SEG30 108 P02_3 SGO0_R AD11 SEG31 109 P02_4 J J J General purpose I/O Pin name Circuit type Function
MB96300
Relocated Clock Output function 1 inverted output
LCD controller / driver segment output General purpose I/O
Relocated clock output function 1 output External bus (non-multiplexed mode) data line and External bus (multiplexed mode) address/data line LCD controller / driver segment output General purpose I/O
Relocated Input Capture Units 6 and 7 data sample input pins
PR
J
SGA0_R AD12
SEG32
FME/EMDC- 2007-02-12
EL IM
J
External bus (non-multiplexed mode) data line and External bus (multiplexed mode) address/data line LCD controller / driver segment output General purpose I/O Relocated Sound Generator 0 SGO output
External bus (non-multiplexed mode) data line and External bus (multiplexed mode) address/data line LCD controller / driver segment output General purpose I/O Relocated Sound generator 0 SGA output External bus (non-multiplexed mode) data line and External bus (multiplexed mode) address/data line LCD controller / driver segment output
IN
AR
Y
External bus (non-multiplexed mode) data line and External bus (multiplexed mode) address/data line
MB96300_shortspec.fm
41
MB96300 Series
PIN DESCRIPTION FOR MB96(F)38X Pin no. MB96(F)38x LQFP120*1 110,111 P02_5, P02_6 OUT0_R, OUT1_R AD13, AD14 SEG33, SEG34 112 P02_7 PPG5_R AD15 SEG35 113 to 116 P03_0 to P03_3 V0 to V3 A16 to A19 SEG36 to SEG39 117 P03_4 INT4 RX0 118 J J J Pin name Circuit type
Preliminary Specification
Function
General purpose I/O Relocated Output Compare Units OCU 0 and OCU 1 waveform outputs External bus (non-multiplexed mode) data line and External bus (multiplexed mode) address/data lines LCD controller / driver segment outputs General purpose I/O
Relocated Programmable Pulse Generator 5 output
LCD controller / driver segment output General purpose I/O
P03_5 TX0
119
P03_6 NMI
INT0
42
FME/EMDC- 2007-02-12
PR EL
J J J
IM
LCD controller / driver reference voltage pins (when reference voltage is externally supplied) External bus (non-multiplexed mode) data line and External bus (multiplexed mode) address/data lines LCD controller / driver segment outputs (when reference voltage is internally supplied) General purpose I/O
External Interrupt 4 CAN0 interface RX input General purpose I/O
CAN0 Interface TX output General purpose I/O
Non-Maskable Interrupt input External interrupt 0 input
IN
External bus (non-multiplexed mode) data line and External bus (multiplexed mode) address/data line
AR
Y
MB96300_shortspec.fm
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)38X Pin no. MB96(F)38x LQFP120*1 3 P03_7 INT1 SIN1 CS0 A20 SEG40 4 P13_0 INT2 SOT1 CS1 A21 SEG41 5 P13_1 INT3 SCK1 CS2 A22 SEG42 6 P13_2 PPG0 TIN0 J J J General purpose I/O External Interrupt 1 input Pin name Circuit type Function
MB96300
External bus Chip Select 0 External bus address line
LCD controller / driver segment output General purpose I/O
External Interrupt 2 input
USART 1 serial data output External bus Chip Select 1 External bus address line
LCD controller / driver segment output
PR
FRCK1 CS3 A23
SEG43
FME/EMDC- 2007-02-12
EL IM
J
General purpose I/O
External Interrupt 3 input
USART 1 serial clock External bus Chip Select 1 External bus address line LCD controller / driver segment output
General purpose I/O Output pin for Programmable Pulse Generator 0 Reload Timer 0 input pin Free Running Timer 1 input pin External bus Chip Select 3 External bus address line LCD controller / driver segment output
IN
AR
Y
MB96300_shortspec.fm 43
USART 1 serial data input
MB96300 Series
PIN DESCRIPTION FOR MB96(F)38X Pin no. MB96(F)38x LQFP120*1 7 P13_3 PPG1 TOT0 WOT UBX SEG44 8 P13_4 SIN0 INT6 SEG45 9 P13_5 SOT0 ATDG INT7 SEG46 10 P13_6 SCK0 J J J J Pin name Circuit type
Preliminary Specification
Function
General purpose I/O Output pin for Programmable Pulse Generator 1 Reload Timer 0 output Real Time Clock output
LCD controller / driver segment output General purpose I/O USART 0 data input
External interrupt 1 input
LCD controller / driver segment output General purpose I/O USART 0 data input
CKOTX0 LBX
SEG47 11 P13_7 PPG2
CKOT0 CS4
SEG48 12 P04_4 PPG3 SDA0 44 FME/EMDC- 2007-02-12 J
PR EL
J
IM
A/D converter trigger input External interrupt 7 input LCD controller / driver segment output
General purpose I/O
USART 0 clock Clock Output function 0 inverted output
External bus interface low byte strobe LCD controller / driver segment output
General purpose I/O Programmable Pulse Generator 2 output
Clock Output function 0 output External bus interface Chip Select 4 LCD controller / driver segment output General purpose I/O Programmable Pulse Generator 3 output
I2C interface 0 data I/O MB96300_shortspec.fm
IN
AR
External bus Upper Byte Strobe
Y
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)38X Pin no. MB96(F)38x LQFP120*1 13 P04_5 PPG4 SCL0 14 P06_0 AN0 SCK5 IN2_R SEG49 15 P06_1 AN1 SOT5 IN3_R SEG50 16 P06_2 AN2 INT5 SIN5 SEG51 17 P06_3 AN3 K K J General purpose I/O Programmable Pulse Generator 4 output Pin name Circuit type Function
MB96300
General purpose I/O A/D converter inputs
USART 5 Serial clock
Input Capture Unit relocated input pin LCD controller / driver segment outputs General purpose I/O A/D converter inputs
USART 5 Serial data output Input Capture Unit relocated input pin
FRCK0 SEG52
PR
FME/EMDC- 2007-02-12
EL IM
K K
LCD controller / driver segment outputs
General purpose I/O A/D converter input External interrupt input USART 5 Serial input data LCD controller / driver segment output
General purpose I/O A/D converter input Free Running Timer 0 clock input LCD controller / driver segment output
IN
AR
Y
MB96300_shortspec.fm 45
I2C interface 0 clock I/O
MB96300 Series
PIN DESCRIPTION FOR MB96(F)38X Pin no. MB96(F)38x LQFP120*1 18, 19 P06_4, P06_5 AN4, AN5 IN0, IN1 TTG0/TTG4, TTG1/TTG5 SEG53, SEG54 20 P06_6 AN6 TIN1 IN4_R SEG55 21 P06_7 AN7 TOT1 IN5_R K K K Pin name Circuit type
Preliminary Specification
Function
General purpose I/O A/D converter inputs
Input Capture Unit input pin
LCD controller / driver segment outputs General purpose I/O A/D converter input
Reload Timer 1 input
Input Capture Unit relocated input pin LCD controller / driver segment output
SEG56 22 23 AVCC AVRH
24 25
AVRL
AVSS
46
FME/EMDC- 2007-02-12
PR EL
F G F F
IM
General purpose I/O A/D converter input
Reload Timer 1 output Input Capture Unit relocated input pin LCD controller / driver segment output
Analogue circuits power supply
A/D converter high reference voltage Supply voltage to AVCC pin must be kept higher than or equal to AVRH pin voltage especially when the supply voltage to AVRH is turned on or off A/D converter low reference voltage Analogue circuits power supply
IN
AR
Programmable Pulse Generator 0 and 4 external trigger, Programmable Pulse Generator 1 and 5 external trigger
Y
MB96300_shortspec.fm
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)38X Pin no. MB96(F)38x LQFP120*1 26, 27 P05_0, P05_1 AN8, AN9 ALARM0, ALARM1 SEG57, SEG58 28 P05_2 AN10 OUT2 SGO1 SEG59 29 P05_3 AN11 OUT3 SGA1 SEG60 32 P05_4 AN12 RX1 INT2_R SEG61 33 P05_5 AN13 TX1 K K K General purpose I/O A/D converter inputs Alarm comparator 0, 1 inputs Pin name Circuit type Function
MB96300
General purpose I/O A/D converter inputs
Output Compare Unit 2 and 3 waveform output pins
LCD controller / driver segment outputs General purpose I/O A/D converter inputs
PR
K
SEG62
FME/EMDC- 2007-02-12
EL IM
K
Output Compare Unit 2 and 3 waveform output pins SGA output of Sound Generator 1 LCD controller / driver segment outputs
General purpose I/O A/D converter input CAN controller 1 data receive Relocated External Interrupt 2 input
LCD controller / driver segment output General purpose I/O A/D converter input CAN controller 1 data transmit LCD controller / driver segment output
IN
SGO output of Sound Generator 1
AR
LCD controller / driver segment outputs
Y
MB96300_shortspec.fm 47
MB96300 Series
PIN DESCRIPTION FOR MB96(F)38X Pin no. MB96(F)38x LQFP120*1 34 P05_6 AN14 TIN2 SGO1_R SEG63 35 P05_7 AN15 TOT2 SGA1_R SEG64 36 to 39 GP08_0 to GP08_3 PWM1P0 PWM1M0 PWM2P0 PWM2M0 40, 43 to 45 GP08_4 to GP08_7 PWM1P1 PWM1M1 PWM2P1 PWM2M1 46 to 49 M M K K Pin name Circuit type
Preliminary Specification
Function
General purpose I/O A/D converter input Reload Timer 2 event input
Relocated SGO output of Sound Generator 1
General purpose I/O A/D converter input
Reload Timer 2 output
Relocated SGA output of Sound Generator 1 LCD controller / driver segment output General purpose I/O
GP09_0 to GP09_3 PWM1P2 PWM1M2 PWM2P2 PWM2M2
50 to 52, 55
GP09_4 to GP09_7 PWM1P3 PWM1M3 PWM2P3 PWM2M3
48
FME/EMDC- 2007-02-12
PR EL
M M
IM
Stepper Motor Controller 0 outputs
General purpose I/O Stepper Motor Controller 1 outputs
General purpose I/O Stepper Motor Controller 2 outputs
General purpose I/O Stepper Motor Controller 3 outputs
IN
AR
LCD controller / driver segment output
Y
MB96300_shortspec.fm
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)38X Pin no. MB96(F)38x LQFP120*1 56 GP10_0 PWM1P4 SIN2 TIN3 57 GP10_1 PWM1M4 SOT2 TOT3 58 GP10_2 PWM2P4 SCK2 PPG6 59 GP10_3 PWM2M4 PPG7 62, 63, 64 30, 60, 90, 120 1, 31, 61, 91 41, 53, 42, 54 2 MD0, MD1, MD2 VCC VSS DVCC DVSS C M M M M General purpose I/O Stepper Motor Controller 4 output Pin name Circuit type Function
MB96300
Reload Timer 3 event input General purpose I/O
Stepper Motor Controller 4 output USART 2 Serial data output Reload Timer 3 output General purpose I/O
Stepper Motor Controller 4 output USART 2 clock
Programmable Pulse Generator 6 output
PR
F
*1: FPT-120P-M21
FME/EMDC- 2007-02-12
EL IM
C Power supply Power supply
General purpose I/O
Stepper Motor Controller 4 output
Programmable Pulse Generator 7 output
Input pins for specifying the operating mode The pins must be directly connected to VCC or VSS
High current I/O power supply
High current I/O power supply Internally regulated power supply stabilization capacitor pin. Please refer to the datasheet for recommended capacitor values.
IN
AR
MB96300_shortspec.fm 49
Y
USART 2 Serial data input
MB96300 Series
s I/O CIRCUIT TYPE
Preliminary Specification
Type A
X1
Circuit
Remarks Oscillation circuit High-speed oscillation feedback resistor = approx. 1 MΩ
Xout
B
X1A Xout
X0A
Standby control signal
C
R
E
IM
R
PR EL
Pull-up Resistor
F
50
FME/EMDC- 2007-02-12
IN
Hysteresis inputs Hysteresis inputs
AR
Standby control signal
Oscillation circuit Low-speed oscillation feedback resistor = approx. 10 MΩ
Mask ROM and EVA device: CMOS Hysteresis input pin Flash device: CMOS input pin CMOS Hysteresis input pin Pull-up resistor value: approx. 50 kΩ
Power supply input protection circuit
Y
MB96300_shortspec.fm
X0
Preliminary Specification
Type G
ANE AVR ANE
MB96300
Remarks A/D converter ref+ (AVRH) power supply input pin, With the protection circuit Flash devices do not have a protection circuit against VCC for pin AVRH
Circuit
pull-up control
Pout
Nout R Hysteresis input
Hysteresis input
Automotive inputs
FME/EMDC- 2007-02-12
PR
EL IM
TTL input Standby control for input shutdown
IN
MB96300_shortspec.fm
AR
Y
H
CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up registor:50kΩ approx.
51
MB96300 Series
Type I
pull-up control
Preliminary Specification
Remarks CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function) TTL input with input shutdown function Programmable pull-up registor: 50kΩ approx. Analogue input
Circuit
Pout
Nout R Hysteresis input
Hysteresis input
Automotive inputs
TTL input
Analog input
J
pull-up control
Pout
52
FME/EMDC- 2007-02-12
PR EL
Nout R TTL input
IM
Hysteresis input Hysteresis input Automotive inputs Standby control for input shutdown SEG, COM output
IN
Standby control for input shutdown
AR
CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function) TTL input with input shutdown function Programmable pull-up registor: 50kΩ approx. SEG or COM output MB96300_shortspec.fm
Y
Preliminary Specification
Type K
pull-up control
MB96300
Remarks CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function) TTL input with input shutdown function Programmable pull-up registor: 50kΩ approx. Analogue input SEG output
Circuit
Pout
Nout R Hysteresis input
Automotive inputs
TTL input Standby control for input shutdown Analog input SEG output
R
PR
FME/EMDC- 2007-02-12
EL IM
pull-up control Pout Nout Hysteresis input Hysteresis input Automotive inputs TTL input Standby control for input shutdown Analog input SEG output V input
L
IN
AR
CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function) TTL input with input shutdown function Programmable pull-up registor:50kΩ approx. Analogue input MB96300_shortspec.fm 53
Hysteresis input
Y
MB96300 Series
Type M
pull-up control
Preliminary Specification
Remarks CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA, IOL = 30mA, IOH = -30mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up registor:50kΩ approx.
Circuit
Pout
Nout R Hysteresis input
Hysteresis input
Automotive inputs
TTL input
N
pull-up control
Pout
Nout R
54
FME/EMDC- 2007-02-12
PR EL
TTL input
IM
Hysteresis input Hysteresis input Automotive inputs Standby control for input shutdown
IN
Standby control for input shutdown
AR
CMOS level output (IOL = 3mA, IOH = -3mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up registor:50kΩ approx. MB96300_shortspec.fm
Y
Preliminary Specification
s HANDLING DEVICES Special care is required for the following when handling the device:
• • • • • • • • • • • Preventing latch-up Treatment of unused pins Using external clock Precautions for when not using a sub clock signal Notes on during operation of PLL clock mode Power supply pins (VCC/VSS) Crystal Oscillator Circuit Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Connection of Unused Pins of A/D Converter Notes on Energization Stabilization of power supply voltage
MB96300
• CMOS IC chips may suffer latch-up under the following conditions:
• A voltage higher than VCC or lower than VSS is applied to an input or output pin. • A voltage higher than the rated voltage is applied between VCC and VSS. • The AVCC power supply is applied before the VCC voltage.
• For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage.
2. Treatment of unused pins
• Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device. Therefore they must be pulled up or pulled down through resistors. To prevent latchup, those resistors should be more than 2 kOhm. • Unused bidirectional pins should be set to the output state and can be left open, or the input state with either input disabled or external pull-up/pull-down resistor as described above.
3. Using external clock
• To use external clock, drive the X0 pin and leave X1 pin open.
• If you do not connect pins X0A and X1A to an oscillator, use a pull-down resistor on the X0A pin, and • leave the X1A pin open.
5. Notes on during operation of PLL clock mode
• If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the microcontroller attempts to be working with the freely oscillating PLL. Performance of this operation, however, cannot be guaranteed.
6. Power supply pins (VCC/VSS)
• Ensure that all VCC-level power supply pins are at the same potential. In addition, ensure the same for all VSS-level power supply pins. If there are more than one VCC or VSS system, the device may operate incorrectly even within the guaranteed operating range. FME/EMDC- 2007-02-12 MB96300_shortspec.fm 55
PR
4. Precautions for when not using a sub clock signal
EL IM
• Unused input pins may be left open when the input is disabled (corresponding bit of Port Input Enable register PIER = 0).
IN
• Latch-up may increase the power supply current drastically, causing thermal damage to the device.
AR
1. Preventing latch-up
Y
MB96300 Series
Preliminary Specification
• Connect VCC and VSS to the device from the power supply with lowest possible impedance. • As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between VCC and VSS as close as possible to VCC and VSS pins.
7. Crystal Oscillator Circuit
• Noise at X0 or X1 pins may possibly cause abnormal operation. Make sure to provide bypass capacitors with shortest distance to X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. • It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground area for stabilizing the operation.
8. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
• Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable).
9. Connection of Unused Pins of A/D Converter 10. Notes on Energization
• Connect unused pins of A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS.
• To prevent malfunction of the internal voltage regulator, supply voltage profile while turning on the power supply should be slower than 50us from 0.2 V to 2.7 V.
56
FME/EMDC- 2007-02-12
PR EL
• If the power supply voltage varies acutely even within the operation assurance range of the Vcc power supply voltage, a malfunction may occur. The Vcc power supply voltage must therefore be stabilized. As stabilization guidelines, stabilize the power supply voltage so that Vcc ripple fluctuations (peak to peak value) in the commercial frequencies (50 to 60 Hz) fall within 10% of the standard Vcc power supply voltage and the transient fluctuation rate becomes 0.1V/µs or less in instantaneous fluctuation for power supply switching.
IM
11. Stabilization of power supply voltage
IN
AR
• Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) after turning-on the digital power supply (VCC).
Y
MB96300_shortspec.fm
Preliminary Specification
s BLOCK DIAGRAMS
MB96300
FME/EMDC- 2007-02-12
PR
EL IM
MB96300_shortspec.fm
IN
AR
57
Y
MB96300 Series
Block Diagram of MB96V300
AD00 ... AD15 A00 ... A23 ALE RDX WRLX, WRHX HRQ HAKX RDY CLK LBX, UBX CS0 ... CS5
External Bus Interface
16FX CPU
Preliminary Specification
NMI
X0, X1 X0A, X1A RSTX MD0...MD2
Interrupt Controller
Debug Support Unit Interface
16FX Core Bus (CLKB)
AR
88kB RAM
Y
Boot ROM Voltage Regulator
Emulation Memory Interface
Memory Patch Unit
Clock & Mode Controller
DMA Controller
Watchdog
Peripheral Bus Bridge
Peripheral Bus Bridge
Peripheral Bus 1 (CLKP1)
Peripheral Bus 2 (CLKP2)
SCL0 ... SCL1 AVCC AVSS AVRH AVRL AN0 ... AN39 ADTG TIN0 ... TIN5 TOT0 ... TOT5 FRCK0 IN0 ... IN3 OUT0 ... OUT3 FRCK1 IN4 ... IN7 OUT4 ... OUT7 FRCK2 IN8, IN9 OUT8 ... OUT9 FRCK3 IN10,IN11 OUT10 ... OUT11
IN
USART 10 ch. Alarm Comparator 2 ch. 16-bit PPG 20 ch. Stepper Motor Controller 6 ch. Real Time Clock Clock Output Function 2 ch.
SDA0 ... SDA1
I2C 2 ch.
VCC VSS C TX0 ... TX4 RX0 ... RX4 SGO0 SGA0
10-bit ADC 40 ch.
CAN Interface 5 ch.
16-bit Reload Timer 6 ch. I/O Timer 0 ICU 0/1/2/3 OCU 0/1/2/3
IM
Sound Generator
PR EL
I/O Timer 1 ICU 4/5/6/7 OCU 4/5/6/7 I/O Timer 2 ICU 8/9 OCU 8/9 I/O Timer 3 ICU 10/11 OCU 10/11 External Interrupt LCD controller/ driver
SIN0 ... SIN9 SOT0 ... SOT9 SCK0 ... SCK9 ALARM0 ALARM1 TTG0 ... TTG19 PPG0 ... PPG19 PWM1M0 ... PWM1M5 PWM1P0 ... PWM1P5 PWM2M0 ... PWM2M5 PWM2P0 ... PWM2P5 DVDD DVSS WOT
INT0 ... INT15
V0 ... V3 COM0 ... COM3 SEG0 ... SEG71
CKOT0, CKOT1 CKOTX0, CKOTX1
58
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
Block Diagram of MB96F3xx
AD00 ... AD15 A00 ... A23 ALE RDX WRLX, WRHX HRQ HAKX RDY CLK LBX, UBX CS0 ... CS5
External Bus Interface
16FX CPU
MB96300
NMI
X0, X1 X0A, X1A RSTX MD0...MD2
Interrupt Controller
Main Flash Memory
Satellite Flash Memory
Memory Patch Unit
Clock & Mode Controller
16FX Core Bus (CLKB)
AR
RAM
Y
Boot ROM Voltage Regulator
DMA Controller
Watchdog
Peripheral Bus Bridge
Peripheral Bus Bridge
Peripheral Bus 1 (CLKP1)
Peripheral Bus 2 (CLKP2)
SDA0 ... SDAn SCL0 ... SCLn AVCC AVSS AVRH AVRL AN0 ... ANn ADTG TIN0 ... TINn TOT0 ... TOTn FRCK0 IN0 ... INn OUT0 ... OUTn FRCK1 INm ... INn OUTm ... OUTn FRCK2 IN8, IN9 OUT8, OUT9 FRCK3 IN10,IN11 OUT10, OUT11
IN
USART n ch. Alarm Comparator n ch. 16-bit PPG n ch. Stepper Motor Controller n ch. Real Time Clock Clock Output Function n ch.
I2C n ch.
VCC VSS C TX0 ... TXn RX0 ... RXn SGOn SGAn
10-bit ADC n ch.
CAN Interface n ch.
16-bit Reload Timer n ch. I/O Timer 0 ICU 0/1/2/3 OCU 0/1/2/3
EL IM
Sound Generator n ch.
SIN0 ... SINn SOT0 ... SOTn SCK0 ... SCKn ALARM0 ALARM1 TTG0 ... TTG19 PPG0 ... PPG19 PWM1M0 ... PWM1Mn PWM1P0 ... PWM1Pn PWM2M0 ... PWM2Mn PWM2P0 ... PWM2Pn DVDD DVSS WOT
I/O Timer 1 ICU 4/5/6/7 OCU 4/5/6/7 I/O Timer 2 ICU 8/9 OCU 8/9
INT0 ... INTn
PR
I/O Timer 3 ICU 10/11 OCU 10/11 External Interrupt
not available on all products Suffix "n" denotes variable number of instances in different products. Please refer to product lineup.
V0 ... V3 COM0 ... COM3 SEG0 ... SEG71
LCD controller/ driver
CKOT0, CKOT1 CKOTX0, CKOTX1
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
59
MB96300 Series
Block Diagram of MB963xx
AD00 ... AD15 A00 ... A23 ALE RDX WRLX, WRHX HRQ HAKX RDY CLK LBX, UBX CS0 ... CS5
External Bus Interface
16FX CPU
Preliminary Specification
NMI
X0, X1 X0A, X1A RSTX MD0...MD2
Interrupt Controller
ROM
Memory Patch Unit
Clock & Mode Controller
16FX Core Bus (CLKB)
AR
RAM
Y
Boot ROM Voltage Regulator
DMA Controller
Watchdog
Peripheral Bus Bridge
Peripheral Bus Bridge
Peripheral Bus 1 (CLKP1)
Peripheral Bus 2 (CLKP2)
SCL0 ... SCLn AVCC AVSS AVRH AVRL AN0 ... ANn ADTG TIN0 ... TINn TOT0 ... TOTn FRCK0 IN0 ... INn OUT0 ... OUTn FRCK1 INm ... INn OUTm ... OUTn FRCK2 IN8, IN9 OUT8/OUT9 FRCK3 IN10,IN11 OUT10/OUT11
IN
USART n ch. Alarm Comparator n ch. 16-bit PPG n ch. Stepper Motor Controller n ch. Real Time Clock Clock Output Function n ch.
SDA0 ... SDAn
I2C n ch.
VCC VSS C TX0 ... TXn RX0 ... RXn SGOn SGAn
10-bit ADC n ch.
CAN Interface n ch.
16-bit Reload Timer n ch. I/O Timer 0 ICU 0/1/2/3 OCU 0/1/2/3
IM
Sound Generator n ch.
PR EL
I/O Timer 1 ICU 4/5/6/7 OCU 4/5/6/7 I/O Timer 2 ICU 8/9 OCU 8/9 I/O Timer 3 ICU 10/11 OCU 10/11 External Interrupt
SIN0 ... SINn SOT0 ... SOTn SCK0 ... SCKn ALARM0 ALARM1 TTG0 ... TTG19 PPG0 ... PPG19 PWM1M0 ... PWM1Mn PWM1P0 ... PWM1Pn PWM2M0 ... PWM2Mn PWM2P0 ... PWM2Pn DVDD DVSS WOT
INT0 ... INTn
not available on all products Suffix "n" denotes variable number of instances in different products. Please refer to product lineup.
V0 ... V3 COM0 ... COM3 SEG0 ... SEG71
LCD controller/ driver
CKOT0, CKOT1 CKOTX0, CKOTX1
60
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
s MEMORY MAP
MB96V300
ff.ffff
MB96300
MB96(F)3xx User ROM
Emulation ROM
df.007f df.0000 de.0000 de.002f de.0000
Small Sectors Main RCB *** Sat RCB ***
Main Flash
Start address of User ROM area and number of small sector depends on the device
Satellite Flash Satellite Flash is not available on all devices
external Bus
10.0000 0f.e000
external Bus
Boot-ROM
DSU area
0f.0000
external RAM
02.0000
internal RAM
01.0000 00.8000
ROM/RAM -Mirror
internal RAM
00.1200 00.0c00
PR
Peripheral GPR* DMA ext. bus Peripheral
ext. bus
00.0380 00.0180 00.0100 00.00f0 00.0000
* Unused GPR banks can be used as RAM area. ** Please refer to the table “RAMSTART for different RAM sizes” on the next page *** ROM Configuration Block (RCB) must not be used for other purposes than described in the manual The external Bus area DMA area are only available if the device contains the corresponding resource. The available RAM and ROM area depends on the device configuration.
FME/EMDC- 2007-02-12
EL IM
RAMSTART**
IN
internal RAM ROM/RAM -Mirror
internal RAM
0e.0000
ext. bus
Peripheral GPR* DMA ext. bus Peripheral
AR
MB96300_shortspec.fm 61
Y
MB96300 Series
s RAMSTART for different RAM sizes
Devices
Preliminary Specification
RAM size 1 kB 2 kB 3 kB 4 kB 5 kB
RAMSTART 7E40 7A40 7640 7240 6E40
MB96344, MB96F365, MB96384, MB96385
6 kB 7 kB 8 kB 9 kB
Y
6A40 6640 6240 5E40 5A40 5640 5240 4E40 4A40 4640 4240 3E40 3A40 3640 3240 2E40 2A40 2640 2240 1E40 1A40 1640 1240
MB96F326, MB96F356
MB96(F)346, MB96(F)347, MB96(F)386, MB96(F)387
IM PR EL
MB96F348 62 FME/EMDC- 2007-02-12
IN
14 kB 15 kB 16 kB 17 kB 18 kB 19 kB 20 kB 21 kB 22 kB 23 kB 24 kB 25 kB 26 kB 27 kB 28 kB
AR
10 kB 11 kB 13 kB 12 kB
MB96300_shortspec.fm
Preliminary Specification
s I/O MAP
Table 0-1 I/O map (1 / 53) Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H 00000AH 00000BH 00000CH 00000DH 00000EH 00000FH 000010H 000011H 000018H 000019H 00001AH 00001BH 00001CH 00001DH 00001EH 000020H 000021H 000022H Register I/O Port - Port Data Register Port 00 I/O Port - Port Data Register Port 01 I/O Port - Port Data Register Port 02 I/O Port - Port Data Register Port 03 I/O Port - Port Data Register Port 04 I/O Port - Port Data Register Port 05 I/O Port - Port Data Register Port 06 I/O Port - Port Data Register Port 07 I/O Port - Port Data Register Port 08 I/O Port - Port Data Register Port 09 I/O Port - Port Data Register Port 10 I/O Port - Port Data Register Port 11 I/O Port - Port Data Register Port 12 I/O Port - Port Data Register Port 13 I/O Port - Port Data Register Port 14 I/O Port - Port Data Register Port 15 I/O Port - Port Data Register Port 16 I/O Port - Port Data Register Port 17 Abbreviation 8-bit access PDR00 PDR01 PDR02 PDR03 PDR04 PDR05 PDR06 PDR07 PDR08 PDR09 PDR10 PDR11 PDR12 PDR13 PDR14 PDR15 PDR16 PDR17 ADCSL ADCSH ADCRL ADCRH ADSRL ADSRH ADECR TCDT0 ADSR ADCR ADCS
MB96300
Abbreviation 16-bit access
Access RW RW RW
Y
TCCS0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R RW RW RW RW RW RW
ADC - Control Status Register 0 Low
ADC - Control Status Register 0 High
ADC - Data register 0 High ADC - Setting Register 0 Low ADC - Setting Register 0 High ADC - Extended configuration register FRT - Data register of free-running timer 0 FRT - Data register of free-running timer 0 FRT - Control status register of freerunning timer 0
PR
ADC - Data register 0 Low
EL IM
IN
AR
TCCSL0
RW
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
63
MB96300 Series
Table 0-1 I/O map (2 / 53) Address 000023H 000024H 000025H 000026H 000027H 000028H 000029H 00002AH 00002BH 00002CH 00002DH 00002EH 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH 64 Register FRT - Control status register of freerunning timer 0
Preliminary Specification
Abbreviation 8-bit access TCCSH0
Abbreviation 16-bit access
Access RW
FRT - Data register of free-running timer 1 FRT - Data register of free-running timer 1
TCDT1
RW RW
OCU - Output Compare Control Status 0 OCU - Output Compare Control Status 1 OCU - Compare Register 0 OCU - Compare Register 0 OCU - Compare Register 1 OCU - Compare Register 1
AR
OCS0 OCS1 OCS2 OCS3 OCS4 OCS5 OCS6 OCS7
FRT - Control status register of freerunning timer 1
TCCSH1
Y
FRT - Control status register of freerunning timer 1
TCCSL1
TCCS1
RW RW RW RW
OCCP0
RW RW
IN
OCCP1
RW RW RW RW
OCU - Output Compare Control Status 2 OCU - Output Compare Control Status 3 OCU - Compare Register 2 OCU - Compare Register 2 OCU - Compare Register 3 OCU - Compare Register 3
IM
OCCP2
RW RW
PR EL
OCCP3
RW RW RW RW
OCU - Output Compare Control Status 4 OCU - Output Compare Control Status 5 OCU - Compare Register 4 OCU - Compare Register 4 OCU - Compare Register 5 OCU - Compare Register 5
OCCP4
RW RW
OCCP5
RW RW RW RW
OCU - Output Compare Control Status 6 OCU - Output Compare Control Status 7 OCU - Compare Register 6 OCU - Compare Register 6 OCU - Compare Register 7
OCCP6
RW RW
OCCP7
RW
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (3 / 53) Address 00003FH 000040H 000041H 000042H 000043H 000044H 000045H 000046H 000047H 000048H 000049H 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000058H 000059H 00005AH 00005BH Register OCU - Compare Register 7 ICU - Control Status Register 0/1 ICU - Edge register 0/1 ICU - Capture Register 0 ICU - Capture Register 0 ICU - Capture Register 1 ICU - Capture Register 1 ICU - Control Status Register 2/3 ICU - Edge register 2/3 ICU - Capture Register 2 ICU - Capture Register 2 ICU - Capture Register 3 ICU - Capture Register 3 ICS01 ICE01 IPCPL0 IPCPH0 IPCPL1 IPCP0 Abbreviation 8-bit access
MB96300
Abbreviation 16-bit access
Access RW RW RW R R R R RW RW
AR
ICS23 ICE23 IPCPL2 IPCPH2 IPCPL3 IPCPH3 ICS45 ICE45 IPCPL4 IPCPH4 IPCPL5 IPCPH5 ICS67 ICE67 IPCPL6 IPCPH6 IPCPL7 IPCPH7 ENIR0 EIRR0 ELVRL0 ELVRH0
IPCPH1
Y
IPCP1
IPCP2
R R
IN
IPCP3
R R RW RW
ICU - Control Status Register 4/5 ICU - Edge register 4/5
ICU - Capture Register 4 ICU - Capture Register 4
EL IM
IPCP4
R R
ICU - Capture Register 5 ICU - Capture Register 5
IPCP5
R R RW RW
ICU - Control Status Register 6/7 ICU - Edge register 6/7
ICU - Capture Register 6 ICU - Capture Register 7 ICU - Capture Register 7 External Interrupt - Enable Register 0 External Interrupt - Interrupt request Register 0 External Interrupt - Level Select 0 External Interrupt - Level Select 0
PR
ICU - Capture Register 6
IPCP6
R R
IPCP7
R R RW RW
ELVR0
RW RW
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
65
MB96300 Series
Table 0-1 I/O map (4 / 53) Address 00005CH 00005DH 00005EH 00005FH 000060H 000061H 000062H 000062H 000063H 000063H 000064H 000065H 000066H 000066H 000067H 000067H 000068H 000069H 00006AH 00006AH 00006BH 00006BH 00006CH 00006DH 00006EH 00006EH 00006FH 66 Register External Interrupt - Enable Register 1 External Interrupt - Interrupt request Register 1 External Interrupt - Level Select 1 External Interrupt - Level Select 1
Preliminary Specification
Abbreviation 8-bit access ENIR1 EIRR1 ELVRL1 ELVRH1
Abbreviation 16-bit access
Access RW RW
ELVR1
RW RW RW RW W R W R
RLT - Timer Control Status Register 0 Low RLT - Timer Control Status Register 0 High
TMCSRL0
RLT - Reload Register 0 Low - for writing
AR
TMCSRL1 TMCSRH1 TMCSRL2 TMCSRH2 TMCSRL3 TMCSRH3
TMCSRH0
RLT - Reload Register 0 Low - for reading RLT - Reload Register 0 High - for writing
RLT - Timer Control Status Register 1 Low RLT - Timer Control Status Register 1 High
IN
RLT - Reload Register 0 High - for reading
Y
TMCSR0
TMRLR0 TMR0
TMCSR1
RW RW
RLT - Reload Register 1 Low - for writing RLT - Reload Register 1 Low - for reading RLT - Reload Register 1 High - for writing
IM
TMRLR1 TMR1
W R W R
RLT - Timer Control Status Register 2 Low RLT - Timer Control Status Register 2 High RLT - Reload Register 2 - for writing RLT - Reload Register 2 - for reading RLT - Reload Register 2 - for writing RLT - Reload Register 2 - for reading RLT - Timer Control Status Register 3 Low RLT - Timer Control Status Register 3 High RLT - Reload Register 3 - for writing RLT - Reload Register 3 - for reading RLT - Reload Register 3 - for writing
PR EL
RLT - Reload Register 1 High - for reading TMCSR2
RW RW
TMRLR2 TMR2
W R W R
TMCSR3
RW RW
TMRLR3 TMR3
W R W
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (5 / 53) Address 00006FH 000070H 000071H 000072H 000072H 000073H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH 00007FH 000080H 000081H 000082H 000083H 000084H Register RLT - Reload Register 3 - for reading RLT - Timer Control Status Register 6 Low (dedic. RLT for PPG) - for writing RLT - Timer Control Status Register 6 High (dedic. RLT for PPG) RLT - Reload Register 6 Low (dedic. RLT for PPG) - for writing RLT - Reload Register 6 Low (dedic. RLT for PPG) - for reading TMCSRL6 TMCSRH6 TMCSR6 Abbreviation 8-bit access
MB96300
Abbreviation 16-bit access R
Access
RW RW
Y AR
GCN1L0 GCN1H0 GCN2L0 GCN2H0 PCNL0 PCNH0
TMRLR6 TMR6
W R W R
RLT - Reload Register 6 High (dedic. RLT for PPG) - for writing RLT - Reload Register 6 High (dedic. RLT for PPG) - for reading PPG - General Control rgister 1 PPG 3-0 Low PPG - General Control rgister 1 PPG 3-0 High PPG - General Control rgister 2 PPG 3-0 Low PPG - General Control rgister 2 PPG 3-0 High PPG - Timer register 0 PPG - Timer register 0
IN
GCN10
RW RW
EL IM
GCN20
RW RW
PTMR0
R R
PPG - Period setting register 0 PPG - Period setting register 0
PCSR0
W W
PPG - Duty cycle register 0 PPG - Control status register 0 PPG - Control status register 0 PPG - Timer register 1 PPG - Timer register 1 PPG - Period setting register 1 PPG - Period setting register 1 PPG - Duty cycle register 1 PDUT1 PCSR1 PCN0
PR
PPG - Duty cycle register 0
PDUT0
W W RW RW
PTMR1
R R W W W 67
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
MB96300 Series
Table 0-1 I/O map (6 / 53) Address 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH 000090H 000091H 000092H 000093H 000094H 000095H 000096H 000097H 000098H 000099H 00009AH 00009BH 00009CH 00009DH 00009EH 00009FH 68 Register PPG - Duty cycle register 1 PPG - Control status register 1 PPG - Control status register 1 PPG - Timer register 2 PPG - Timer register 2 PPG - Period setting register 2 PPG - Period setting register 2 PPG - Duty cycle register 2 PPG - Duty cycle register 2 PPG - Control status register 2 PPG - Control status register 2 PPG - Timer register 3 PPG - Timer register 3 PPG - Period setting register 3 PPG - Period setting register 3 PPG - Duty cycle register 3 PPG - Duty cycle register 3
Preliminary Specification
Abbreviation 8-bit access PDUTH1 PCNL1 PCNH1
Abbreviation 16-bit access W PCN1
Access
RW RW
PTMR2
R R W W
AR
PCNL2
Y IN
PCNH2 PCNL3 PCNH3 GCN1L1 GCN1H1 GCN2L1 GCN2H1
PCSR2
PDUT2
W W
PCN2
RW RW
PTMR3
R R
PCSR3
W W
IM
PDUT3
W W
PPG - Control status register 3 PPG - Control status register 3
PR EL
PCN3
RW RW
PPG - General Control rgister 1 PPG 7-4 Low PPG - General Control rgister 1 PPG 7-4 High PPG - General Control rgister 2 PPG 7-4 Low PPG - General Control rgister 2 PPG 7-4 High PPG - Timer register 4 PPG - Timer register 4 PPG - Period setting register 4 PPG - Period setting register 4
GCN11
RW RW
GCN21
RW RW
PTMR4
R R
PCSR4
W W
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (7 / 53) Address 0000A0H 0000A1H 0000A2H 0000A3H 0000A4H 0000A5H 0000A6H 0000A7H 0000A8H 0000A9H 0000AAH 0000ABH 0000ACH 0000ADH 0000AEH 0000AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H Register PPG - Duty cycle register 4 PPG - Duty cycle register 4 PPG - Control status register 4 PPG - Control status register 4 PPG - Timer register 5 PPG - Timer register 5 PPG - Period setting register 5 PPG - Period setting register 5 PPG - Duty cycle register 5 PPG - Duty cycle register 5 PPG - Control status register 5 PPG - Control status register 5 I2C - Bus Status Register 0 I2C - Bus Control Register 0 PCNL4 PCNH4 PCN4 Abbreviation 8-bit access
MB96300
Abbreviation 16-bit access PDUT4 W W
Access
RW RW
Y AR
PCNL5
PTMR5
R R W W
PCSR5
PDUT5
W W
PCN5
RW RW R RW
I2C - Ten bit Slave address Register 0 Low I2C - Ten bit Slave address Register 0 High
EL IM
IN
PCNH5
IBSR0 IBCR0 ITBA0
ITBAL0 ITBAH0 ITMKL0 ITMKH0 ISBA0 ISMK0 IDAR0 ICCR0 IBSR1 IBCR1 ITBAL1 ITBAH1
RW RW
I2C - Ten bit Address mask Register 0 Low I2C - Ten bit Address mask Register 0 High
ITMK0
RW RW RW RW RW RW R RW
I2C - Seven bit Slave address Register 0
I2C - Seven bit Address mask Register 0 I2C - Data Register 0
I2C - Clock Control Register 0 I2C - Bus Status Register 1 I2C - Bus Control Register 1 I2C - Ten bit Slave address Register 1 Low I2C - Ten bit Slave address Register 1 High
PR
ITBA1
RW RW
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
69
MB96300 Series
Table 0-1 I/O map (8 / 53) Address 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H 0000C1H 0000C2H 0000C2H 0000C3H 0000C4H 0000C5H 0000C6H 0000C7H 0000CAH 0000CBH 0000CCH 0000CCH 0000CDH 0000CEH 0000CFH 0000D0H 0000D1H 0000D4H 70 Register I2C - Ten bit Address mask Register 1 Low I2C - Ten bit Address mask Register 1 High
Preliminary Specification
Abbreviation 8-bit access ITMKL1 ITMKH1 ISBA1 ISMK1 IDAR1
Abbreviation 16-bit access ITMK1
Access RW RW RW RW RW RW RW RW W R RW RW RW
I2C - Seven bit Slave address Register 1 I2C - Seven bit Address mask Register 1 I2C - Data Register 1 I2C - Clock Control Register 1 LIN USART USART - Serial Mode Register 0 LIN USART - Serial Control Register 0 LIN USART - TX Register 0 LIN USART - RX Register 0 LIN USART - Serial Status 0
LIN USART - Control/Com. Register 0 LIN USART - Ext. Status Register 0 LIN USART - Baud Rate Generator Register 0 Low
IM
IN
AR
ICCR1 SMR0 SCR0 TDR0 RDR0 SSR0 ECCR0 ESCR0 BGRL0 BGRH0 SMR1 SCR1 TDR1 RDR1 SSR1 ECCR1 ESCR1 BGRL1 BGRH1 SMR2 BGR1 BGR0
Y
RW RW RW RW W R RW RW RW RW RW RW
LIN USART - Serial Mode Register 1 LIN USART - Serial Control Register 1 LIN USART - TX Register 1
LIN USART - RX Register 1
LIN USART - Serial Status 1
LIN USART - Control/Com. Register 1 LIN USART - Ext. Status Register 1 LIN USART - Baud Rate Generator Register 1 Low LIN USART - Baud Rate Generator Register 1 High LIN USART - Serial Mode Register 2
FME/EMDC- 2007-02-12
PR EL
LIN USART - Baud Rate Generator Register 0 High
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (9 / 53) Address 0000D5H 0000D6H 0000D6H 0000D7H 0000D8H 0000D9H 0000DAH 0000DBH 0000DEH 0000DFH 0000E0H 0000E0H 0000E1H 0000E2H 0000E3H 0000E4H 0000E5H 0000F0H 000100H 000101H 000102H 000103H 000104H 000105H 000106H 000107H Register LIN USART - Serial Control Register 2 LIN USART - TX Register 2 LIN USART - RX Register 2 LIN USART - Serial Status 2 LIN USART - Control/Com. Register 2 LIN USART - Ext. Status Register 2 LIN USART - Baud Rate Generator Register 2 Low LIN USART - Baud Rate Generator Register 2 High LIN USART - Serial Mode Register 3 LIN USART - Serial Control Register 3 LIN USART - TX Register 3 LIN USART - RX Register 3 LIN USART - Serial Status 3 Abbreviation 8-bit access SCR2 TDR2 RDR2 SSR2
MB96300
Abbreviation 16-bit access
Access RW W R RW
ESCR2 BGRL2
Y
IOA0
ECCR2
RW RW RW RW RW RW W R RW RW RW
LIN USART - Control/Com. Register 3 LIN USART - Ext. Status Register 3 LIN USART - Baud Rate Generator Register 3 Low LIN USART - Baud Rate Generator Register 3 High external bus
EL IM
IN
AR
BGRH2 SMR3 SCR3 TDR3 RDR3 SSR3 ECCR3 ESCR3 BGRL3 BGRH3 EXTBUS0 BAPL0 BAPM0 BAPH0 DMACS0 IOAL0 IOAH0 DCTL0 DCTH0
BGR2
BGR3
RW RW RW RW RW RW RW RW RW
DMA - Buffer address pointer low byte
DMA - Buffer address pointer middle byte DMA - Buffer address pointer high byte DMA - DMA control register DMA - I/O register address pointer low byte DMA - I/O register address pointer high byte DMA - Data counter low byte DMA - Data counter high byte
PR
DCT0
RW RW
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
71
MB96300 Series
Table 0-1 I/O map (10 / 53) Address 000108H 000109H 00010AH 00010BH 00010CH 00010DH 00010EH 00010FH 000110H 000111H 000112H 000113H 000114H 000115H 000116H 000117H 000118H 000119H 00011AH 00011BH 00011CH 00011DH 00011EH 00011FH 000120H 000121H 72 Register DMA - Buffer address pointer low byte
Preliminary Specification
Abbreviation 8-bit access BAPL1 BAPM1 BAPH1 DMACS1 IOAL1
Abbreviation 16-bit access
Access RW RW RW RW
DMA - Buffer address pointer middle byte DMA - Buffer address pointer high byte DMA - DMA control register DMA - I/O register address pointer low byte DMA - I/O register address pointer high byte DMA - Data counter low byte DMA - Data counter high byte DMA - Buffer address pointer low byte
Y
IOA1
RW RW RW RW RW RW RW RW
AR
DCTL1 DCTH1 BAPL2 BAPM2 BAPH2 DMACS2 IOAL2 IOAH2 DCTL2 DCTH2 BAPL3 BAPM3 BAPH3 DMACS3 IOAL3 IOAH3 DCTL3 DCTH3 BAPL4 BAPM4
IOAH1
DCT1
DMA - Buffer address pointer high byte DMA - DMA control register
DMA - I/O register address pointer high byte DMA - Data counter low byte
IM
DMA - I/O register address pointer low byte
IN
DMA - Buffer address pointer middle byte
IOA2
RW RW
DCT2
RW RW RW RW RW RW
DMA - Data counter high byte
DMA - Buffer address pointer low byte DMA - Buffer address pointer middle byte DMA - Buffer address pointer high byte DMA - DMA control register
DMA - I/O register address pointer low byte DMA - I/O register address pointer high byte DMA - Data counter low byte DMA - Data counter high byte DMA - Buffer address pointer low byte DMA - Buffer address pointer middle byte
PR EL
IOA3
RW RW
DCT3
RW RW RW RW
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (11 / 53) Address 000122H 000123H 000124H 000125H 000126H 000127H 000128H 000129H 00012AH 00012BH 00012CH 00012DH 00012EH 00012FH 000130H 000131H 000132H 000133H 000134H 000135H 000136H 000137H 000138H 000139H 00013AH 00013BH Register DMA - Buffer address pointer high byte DMA - DMA control register DMA - I/O register address pointer low byte DMA - I/O register address pointer high byte DMA - Data counter low byte DMA - Data counter high byte DMA - Buffer address pointer low byte Abbreviation 8-bit access BAPH4 DMACS4 IOAL4 IOAH4 DCTL4 DCTH4 BAPL5 IOA4
MB96300
Abbreviation 16-bit access
Access RW RW RW RW
Y
IOA5 IOA6
DCT4
RW RW RW RW RW RW RW RW
DMA - Buffer address pointer middle byte DMA - Buffer address pointer high byte DMA - DMA control register DMA - I/O register address pointer low byte
DMA - Data counter low byte
EL IM
DMA - I/O register address pointer high byte
IN
AR
BAPM5 BAPH5 DMACS5 IOAL5 IOAH5 DCTL5 DCTH5 BAPL6 BAPM6 BAPH6 DMACS6 IOAL6 IOAH6 DCTL6 DCTH6 BAPL7 BAPM7 BAPH7 DMACS7 DCT6 DCT5
RW RW RW RW RW RW RW RW RW RW RW RW RW RW
DMA - Data counter high byte
DMA - Buffer address pointer low byte
DMA - Buffer address pointer middle byte DMA - Buffer address pointer high byte DMA - DMA control register
DMA - I/O register address pointer high byte DMA - Data counter low byte DMA - Data counter high byte Buffer address pointer low byte Buffer address pointer middle byte Buffer address pointer high byte DMA control register
FME/EMDC- 2007-02-12
PR
DMA - I/O register address pointer low byte
MB96300_shortspec.fm
73
MB96300 Series
Table 0-1 I/O map (12 / 53) Address 00013CH 00013DH 00013EH 00013FH 000140H 000141H 000142H 000143H 000144H 000145H 000146H 000147H 000148H 000149H 00014AH 00014BH 00014CH 00014DH 00014EH 00014FH 000150H 000151H 000152H 000153H 000154H 000155H Register I/O register address pointer low byte I/O register address pointer high byte Data counter low byte Data counter high byte DMA - Buffer address pointer low byte
Preliminary Specification
Abbreviation 8-bit access IOAL7 IOAH7 DCTL7 DCTH7 BAPL8
Abbreviation 16-bit access IOA7
Access RW RW
DCT7
RW RW RW RW RW RW
DMA - Buffer address pointer middle byte DMA - Buffer address pointer high byte DMA - DMA control register DMA - I/O register address pointer low byte
BAPM8 BAPH8
AR
DMACS8 IOAL8 IOAH8 DCTL8 DCTH8 BAPL9 BAPM9 BAPH9 DMACS9 IOAL9 IOAH9 DCTL9 DCTH9 BAPL10 BAPM10 BAPH10 DMACS10 IOAL10 IOAH10
Y
IOA8 DCT8 IOA9 DCT9 IOA10
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
DMA - Data counter low byte DMA - Data counter high byte
DMA - Buffer address pointer middle byte DMA - Buffer address pointer high byte DMA - DMA control register
DMA - I/O register address pointer low byte DMA - I/O register address pointer high byte DMA - Data counter low byte
DMA - Data counter high byte
DMA - Buffer address pointer low byte DMA - Buffer address pointer middle byte DMA - Buffer address pointer high byte DMA - DMA control register DMA - I/O register address pointer low byte DMA - I/O register address pointer high byte
74
FME/EMDC- 2007-02-12
PR EL
IM
DMA - Buffer address pointer low byte
IN
DMA - I/O register address pointer high byte
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (13 / 53) Address 000156H 000157H 000158H 000159H 00015AH 00015BH 00015CH 00015DH 00015EH 00015FH 000160H 000161H 000162H 000163H 000164H 000165H 000166H 000167H 000168H 000169H 00016AH 00016BH 00016CH 00016DH 00016EH 00016FH Register DMA - Data counter low byte DMA - Data counter high byte DMA - Buffer address pointer low byte DMA - Buffer address pointer middle byte DMA - Buffer address pointer high byte DMA - DMA control register DMA - I/O register address pointer low byte DMA - I/O register address pointer high byte DMA - Data counter low byte DMA - Data counter high byte DMA - Buffer address pointer low byte Abbreviation 8-bit access DCTL10 DCTH10 BAPL11 BAPM11
MB96300
Abbreviation 16-bit access DCT10
Access RW RW RW RW RW RW RW RW
DMACS11 IOAL11
AR
IOAH11 DCTL11 DCTH11 BAPL12 BAPM12 BAPH12 DMACS12 IOAL12 IOAH12 DCTL12 DCTH12 BAPL13 BAPM13 BAPH13 DMACS13 IOAL13 IOAH13 DCTL13 DCTH13
Y
BAPH11
IOA11
DCT11
RW RW RW RW RW RW
DMA - Buffer address pointer middle byte DMA - Buffer address pointer high byte DMA - DMA control register
DMA - I/O register address pointer low byte
EL IM
IN
IOA12
RW RW
DMA - I/O register address pointer high byte DMA - Data counter low byte
DCT12
RW RW RW RW RW RW
DMA - Data counter high byte
DMA - Buffer address pointer low byte
DMA - Buffer address pointer middle byte DMA - Buffer address pointer high byte DMA - DMA control register DMA - I/O register address pointer low byte DMA - I/O register address pointer high byte DMA - Data counter low byte DMA - Data counter high byte
PR
IOA13
RW RW
DCT13
RW RW
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
75
MB96300 Series
Table 0-1 I/O map (14 / 53) Address 000170H 000171H 000172H 000173H 000174H 000175H 000176H 000177H 000178H 000179H 00017AH 00017BH 00017CH 00017DH 00017EH 00017FH 000180H 000380H 000381H 000382H 000383H 000384H 000385H 000386H 000387H 000388H 000389H 76 Register DMA - Buffer address pointer low byte
Preliminary Specification
Abbreviation 8-bit access BAPL14 BAPM14 BAPH14 DMACS14 IOAL14
Abbreviation 16-bit access
Access RW RW RW RW
DMA - Buffer address pointer middle byte DMA - Buffer address pointer high byte DMA - DMA control register DMA - I/O register address pointer low byte DMA - I/O register address pointer high byte DMA - Data counter low byte DMA - Data counter high byte DMA - Buffer address pointer low byte
Y
IOA14
RW RW RW RW RW RW RW RW
AR
DCTL14 DCTH14 BAPL15 BAPM15 BAPH15 DMACS15 IOAL15 IOAH15 DCTL15 DCTH15 GPR_RAM DISEL0 DISEL1 DISEL2 DISEL3 DISEL4 DISEL5 DISEL6 DISEL7 DISEL8 DISEL9
IOAH14
DCT14
DMA - Buffer address pointer high byte DMA - DMA control register
DMA - I/O register address pointer high byte DMA - Data counter low byte
IM
DMA - I/O register address pointer low byte
IN
DMA - Buffer address pointer middle byte
IOA15
RW RW
DCT15
RW RW RW RW RW RW RW RW RW RW RW RW RW
DMA - Data counter high byte
CPU - General Purpose registers (RAM access) DMA - Interrupt select for DMA channel 0 DMA - Interrupt select for DMA channel 1 DMA - Interrupt select for DMA channel 2 DMA - Interrupt select for DMA channel 3 DMA - Interrupt select for DMA channel 4 DMA - Interrupt select for DMA channel 5 DMA - Interrupt select for DMA channel 6 DMA - Interrupt select for DMA channel 7 DMA - Interrupt select for DMA channel 8 DMA - Interrupt select for DMA channel 9
FME/EMDC- 2007-02-12
PR EL
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (15 / 53) Address 00038AH 00038BH 00038CH 00038DH 00038EH 00038FH 000390H 000391H 000392H 000393H 000394H 000395H 0003A0H 0003A1H 0003A2H 0003A3H 0003A4H 0003A5H 0003AEH 0003AFH 0003B0H 0003B1H 0003B2H 0003B3H Register DMA - Interrupt select for DMA channel 10 DMA - Interrupt select for DMA channel 11 DMA - Interrupt select for DMA channel 12 DMA - Interrupt select for DMA channel 13 DMA - Interrupt select for DMA channel 14 DMA - Interrupt select for DMA channel 15 DMA status register for DMA channels 7 0 DMA status register for DMA channels 15 -8 DMA stop status register for DMA channels 7 - 0 DMA stop status register for DMA channels 15 - 8 Abbreviation 8-bit access DISEL10 DISEL11 DISEL12 DISEL13
MB96300
Abbreviation 16-bit access
Access RW RW RW RW RW RW RW RW
DISEL15 DSRL
AR
DSRH DSSRL DSSRH DERL DERH ILR IDX TBRL TBRH DIRR NMI ROMM EDSU
Y
DSR DSSR DER ICR TBR PFCS0 PFCS1
DISEL14
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
DMA enable register for DMA channels 7 0 DMA enable register for DMA channels 15 -8 Interrupt level register
Interrupt Index register
Interrupt vector Table base register Interrupt vector Table base register Delayed Interrupt register
Non maskable Interrupt register ROM mirror control register EDSU configuration register
Memory patch control/status register ch 0/ 1 Memory patch control/status register ch 0/ 1 Memory patch control/status register ch 2/ 3 Memory patch control/status register ch 2/ 3
FME/EMDC- 2007-02-12
PR
EL IM
IN
MB96300_shortspec.fm
77
MB96300 Series
Table 0-1 I/O map (16 / 53) Address 0003B4H 0003B5H 0003B6H 0003B7H 0003B8H 0003B9H 0003BAH 0003BBH 0003BCH 0003BDH 0003BEH 0003BFH 0003C0H 0003C1H 0003C2H 0003C3H 0003C4H 0003C5H Register
Preliminary Specification
Abbreviation 8-bit access
Abbreviation 16-bit access PFCS2
Access RW RW
Memory patch control/status register ch 4/ 5 Memory patch control/status register ch 4/ 5
Memory patch control/status register ch 6/ 7 Memory Patch function - Patch address 0 low Memory Patch function - Patch address 0 middle Memory Patch function - Patch address 0 high Memory Patch function - Patch address 1 low
Y
PFAL0 PFAM0 PFAH0 PFAL1 PFAM1 PFAH1 PFAL2 PFAM2 PFAH2 PFAL3 PFAM3 PFAH3 PFAL4 PFAM4
Memory patch control/status register ch 6/ 7
PFCS3
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Memory Patch function - Patch address 1 high Memory Patch function - Patch address 2 low Memory Patch function - Patch address 2 middle Memory Patch function - Patch address 2 high Memory Patch function - Patch address 3 low Memory Patch function - Patch address 3 middle Memory Patch function - Patch address 3 high Memory Patch function - Patch address 4 low Memory Patch function - Patch address 4 middle
78
FME/EMDC- 2007-02-12
PR EL
IM
Memory Patch function - Patch address 1 middle
IN
AR
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (17 / 53) Address 0003C6H 0003C7H 0003C8H 0003C9H 0003CAH 0003CBH 0003CCH 0003CDH 0003CEH 0003CFH 0003D0H 0003D1H 0003D2H 0003D3H 0003D4H 0003D5H 0003D6H 0003D7H 0003D8H 0003D9H 0003DAH 0003DBH 0003DCH 0003DDH Register Memory Patch function - Patch address 4 high Memory Patch function - Patch address 5 low Memory Patch function - Patch address 5 middle Memory Patch function - Patch address 5 high Memory Patch function - Patch address 6 low Memory Patch function - Patch address 6 middle Memory Patch function - Patch address 6 high Memory Patch function - Patch address 7 low Memory Patch function - Patch address 7 middle Memory Patch function - Patch address 7 high Memory Patch function - Patch data 0 Memory Patch function - Patch data 0 Memory Patch function - Patch data 1 Memory Patch function - Patch data 1 Memory Patch function - Patch data 2 Abbreviation 8-bit access PFAH4 PFAL5 PFAM5 PFAH5 PFAL6
MB96300
Abbreviation 16-bit access
Access RW RW RW
Y
PFD0 PFD1 PFD2 PFD3 PFD4 PFD5 PFD6
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
EL IM
Memory Patch function - Patch data 3 Memory Patch function - Patch data 3 Memory Patch function - Patch data 4 Memory Patch function - Patch data 4 Memory Patch function - Patch data 5 Memory Patch function - Patch data 5 Memory Patch function - Patch data 6 Memory Patch function - Patch data 6
PR
Memory Patch function - Patch data 2
FME/EMDC- 2007-02-12
IN
AR
PFAM6 PFAH6 PFAL7 PFAM7 PFAH7 PFDL0 PFDH0 PFDL1 PFDH1 PFDL2 PFDH2 PFDL3 PFDH3 PFDL4 PFDH4 PFDL5 PFDH5 PFDL6 PFDH6
MB96300_shortspec.fm
79
MB96300 Series
Table 0-1 I/O map (18 / 53) Address 0003DEH 0003DFH 0003F1H 0003F2H 0003F6H 000400H 000401H 000402H 000403H 000404H 000405H 000406H 000407H 000408H 000409H 00040AH 00040BH 00040CH 00040DH 00040EH 00040FH 000415H 000416H 000417H 000418H 00041AH 00041BH 80 Register Memory Patch function - Patch data 7 Memory Patch function - Patch data 7 Flash Memory Configuration register (Main Flash) + EVA Flash Memory Timing Configuration register 0 (Main Flash) + EVA Flash Memory Timing Configuration register 0 (Sat Flash) + EVA Standby Mode control register Clock select register Clock Stabilisation select register Clock monitor register Clock Frequncy control register Low
Preliminary Specification
Abbreviation 8-bit access PFDL7 PFDH7 MFMCS MFMTCL SFMTCL SMCR
Abbreviation 16-bit access PFD7
Access RW RW RW
Y
MFMTC SFMTC
RW RW RW RW RW R
IN
AR
CKSR CKSSR CKMR CKFCRL CKFCRH PLLCR CKFCR PLLCRL PLLCRH RCTCR MCTCR SCTCR RCCSRC RCR RCCSR WDTC WDTCP COAR COCR0 COCR1 CMCR CMPRL CMPRH CMPR
RW RW RW RW RW RW RW R RW R RW W RW RW RW RW RW RW
Clock Frequncy control register High PLL Control register Low PLL Control register High
RC clock timer control register
Main clock timer control register Sub clock timer control register
Reset cause and clock status register with clear function Reset configuration register
Reset cause and clock status register Watch dog timer configuration register Watch dog timer clear pattern register Clock output activation register
Clock output configuration register 0 Clock output configuration register 1 Clock Modulator control register Clock Modulator Parameter register Low Clock Modulator Parameter register High
FME/EMDC- 2007-02-12
PR EL
IM
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (19 / 53) Address 000430H 000431H 000432H 000433H 000434H 000435H 000436H 000437H 000438H 000439H 00043AH 00043BH 00043CH 00043DH 00043EH 00043FH 000440H 000441H 000444H 000445H 000446H 000447H 000448H 000449H 00044AH Register I/O Port - Data Direction Register Port 00 I/O Port - Data Direction Register Port 01 I/O Port - Data Direction Register Port 02 I/O Port - Data Direction Register Port 03 I/O Port - Data Direction Register Port 04 I/O Port - Data Direction Register Port 05 I/O Port - Data Direction Register Port 06 I/O Port - Data Direction Register Port 07 I/O Port - Data Direction Register Port 08 I/O Port - Data Direction Register Port 09 I/O Port - Data Direction Register Port 10 I/O Port - Data Direction Register Port 11 I/O Port - Data Direction Register Port 12 I/O Port - Data Direction Register Port 13 I/O Port - Data Direction Register Port 14 I/O Port - Data Direction Register Port 15 Abbreviation 8-bit access DDR00 DDR01 DDR02 DDR03
MB96300
Abbreviation 16-bit access
Access RW RW RW RW
DDR05 DDR06 DDR07 DDR08 DDR09
Y
DDR04
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
EL IM
I/O Port - Data Direction Register Port 16 I/O Port - Data Direction Register Port 17 I/O Port - Port Input Enable Register I/O Port - Port 00 I/O Port - Port Input Enable Register I/O Port - Port 01
I/O Port - Port Input Enable Register I/O Port - Port 03 I/O Port - Port Input Enable Register I/O Port - Port 04 I/O Port - Port Input Enable Register I/O Port - Port 05 I/O Port - Port Input Enable Register I/O Port - Port 06
PR
I/O Port - Port Input Enable Register I/O Port - Port 02
FME/EMDC- 2007-02-12
IN
AR
DDR10 DDR11 DDR12 DDR13 DDR14 DDR15 DDR16 DDR17 PIER00 PIER01 PIER02 PIER03 PIER04 PIER05 PIER06
MB96300_shortspec.fm
81
MB96300 Series
Table 0-1 I/O map (20 / 53) Address 00044BH 00044CH 00044DH 00044EH 00044FH 000450H 000451H 000452H 000453H 000454H 000455H 000458H 000459H 00045AH 00045BH 00045CH 00045DH 00045EH Register
Preliminary Specification
Abbreviation 8-bit access PIER07 PIER08 PIER09 PIER10 PIER11 PIER12 PIER13 PIER14 PIER15 PIER16 PIER17 PILR00 PILR01 PILR02 PILR03 PILR04 PILR05 PILR06
Abbreviation 16-bit access
Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
I/O Port - Port Input Enable Register I/O Port - Port 07 I/O Port - Port Input Enable Register I/O Port - Port 08 I/O Port - Port Input Enable Register I/O Port - Port 09 I/O Port - Port Input Enable Register I/O Port - Port 10 I/O Port - Port Input Enable Register I/O Port - Port 11 I/O Port - Port Input Enable Register I/O Port - Port 12 I/O Port - Port Input Enable Register I/O Port - Port 13 I/O Port - Port Input Enable Register I/O Port - Port 14
I/O Port - Port Input Enable Register I/O Port - Port 16 I/O Port - Port Input Enable Register I/O Port - Port 17 I/O Port - Port Input Level Register I/O Port - Port 00 I/O Port - Port Input Level Register I/O Port - Port 01 I/O Port - Port Input Level Register I/O Port - Port 02 I/O Port - Port Input Level Register I/O Port - Port 03 I/O Port - Port Input Level Register I/O Port - Port 04 I/O Port - Port Input Level Register I/O Port - Port 05 I/O Port - Port Input Level Register I/O Port - Port 06
82
FME/EMDC- 2007-02-12
PR EL
IM
I/O Port - Port Input Enable Register I/O Port - Port 15
IN
AR
Y
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (21 / 53) Address 00045FH 000460H 000461H 000462H 000463H 000464H 000465H 000466H 000467H 000468H 000469H 00046CH 00046DH 00046EH 00046FH 000470H 000471H 000472H Register I/O Port - Port Input Level Register I/O Port - Port 07 I/O Port - Port Input Level Register I/O Port - Port 08 I/O Port - Port Input Level Register I/O Port - Port 09 I/O Port - Port Input Level Register I/O Port - Port 10 I/O Port - Port Input Level Register I/O Port - Port 11 I/O Port - Port Input Level Register I/O Port - Port 12 I/O Port - Port Input Level Register I/O Port - Port 13 I/O Port - Port Input Level Register I/O Port - Port 14 I/O Port - Port Input Level Register I/O Port - Port 15 I/O Port - Port Input Level Register I/O Port - Port 16 I/O Port - Port Input Level Register I/O Port - Port 17 I/O Port - Extended Port Input Level Register Port 00 I/O Port - Extended Port Input Level Register Port 01 Abbreviation 8-bit access PILR07 PILR08 PILR09 PILR10 PILR11 PILR12 PILR13 PILR14 PILR15 PILR16 PILR17 EPILR00 EPILR01 EPILR02 EPILR03 EPILR04 EPILR05 EPILR06
MB96300
Abbreviation 16-bit access
Access RW RW RW
Y
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
I/O Port - Extended Port Input Level Register Port 03 I/O Port - Extended Port Input Level Register Port 04 I/O Port - Extended Port Input Level Register Port 05 I/O Port - Extended Port Input Level Register Port 06
FME/EMDC- 2007-02-12
PR
I/O Port - Extended Port Input Level Register Port 02
EL IM
IN
AR
MB96300_shortspec.fm
83
MB96300 Series
Table 0-1 I/O map (22 / 53) Address 000473H 000474H 000475H 000476H 000477H 000478H 000479H 00047AH 00047BH 00047CH 00047DH 000480H 000481H 000482H 000483H 000484H 000485H 000486H Register I/O Port - Extended Port Input Level Register Port 07 I/O Port - Extended Port Input Level Register Port 08 I/O Port - Extended Port Input Level Register Port 09 I/O Port - Extended Port Input Level Register Port 10 I/O Port - Extended Port Input Level Register Port 11 I/O Port - Extended Port Input Level Register Port 12 I/O Port - Extended Port Input Level Register Port 13 I/O Port - Extended Port Input Level Register Port 14 I/O Port - Extended Port Input Level Register Port 15 I/O Port - Extended Port Input Level Register Port 16 I/O Port - Extended Port Input Level Register Port 17
Preliminary Specification
Abbreviation 8-bit access EPILR07 EPILR08 EPILR09 EPILR10 EPILR11 EPILR12 EPILR13 EPILR14 EPILR15 EPILR16 EPILR17 PODR00 PODR01 PODR02 PODR03 PODR04 PODR05 PODR06
Abbreviation 16-bit access
Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
I/O Port - Port Output Drive Register Port 00 I/O Port - Port Output Drive Register Port 01 I/O Port - Port Output Drive Register Port 02 I/O Port - Port Output Drive Register Port 03 I/O Port - Port Output Drive Register Port 04 I/O Port - Port Output Drive Register Port 05 I/O Port - Port Output Drive Register Port 06
84
FME/EMDC- 2007-02-12
PR EL
IM
IN
AR
Y
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (23 / 53) Address 000487H 000488H 000489H 00048AH 00048BH 00048CH 00048DH 00048EH 00048FH 000490H 000491H 00049CH 00049DH 00049EH 0004A8H 0004A9H 0004AAH 0004ABH 0004ACH Register I/O Port - Port Output Drive Register Port 07 I/O Port - Port Output Drive Register Port 08 I/O Port - Port Output Drive Register Port 09 I/O Port - Port Output Drive Register Port 10 I/O Port - Port Output Drive Register Port 11 I/O Port - Port Output Drive Register Port 12 I/O Port - Port Output Drive Register Port 13 I/O Port - Port Output Drive Register Port 14 I/O Port - Port Output Drive Register Port 15 Abbreviation 8-bit access PODR07 PODR08 PODR09 PODR10 PODR11 PODR12 PODR13 PODR14 PODR15 PODR16 PODR17 PHDR08 PHDR09 PHDR10 PUCR00 PUCR01 PUCR02 PUCR03 PUCR04
MB96300
Abbreviation 16-bit access
Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
I/O Port - Port Output Drive Register Port 16 I/O Port - Port Output Drive Register Port 17
I/O Port - Port High Drive Register Port 08 I/O Port - Port High Drive Register Port 09 I/O Port - Port High Drive Register Port 10
I/O Port - Pull-Up resistor Control Register Port 01 I/O Port - Pull-Up resistor Control Register Port 02 I/O Port - Pull-Up resistor Control Register Port 03 I/O Port - Pull-Up resistor Control Register Port 04
FME/EMDC- 2007-02-12
PR
I/O Port - Pull-Up resistor Control Register Port 00
EL IM
IN
AR
Y
MB96300_shortspec.fm
85
MB96300 Series
Table 0-1 I/O map (24 / 53) Address 0004ADH 0004AEH 0004AFH 0004B0H 0004B1H 0004B2H 0004B3H 0004B4H 0004B5H 0004B6H 0004B7H 0004B8H 0004B9H 0004BCH 0004BDH 0004BEH 0004BFH 0004C0H Register
Preliminary Specification
Abbreviation 8-bit access PUCR05 PUCR06 PUCR07 PUCR08 PUCR09 PUCR10 PUCR11 PUCR12 PUCR13 PUCR14 PUCR15 PUCR16 PUCR17 EPSR00 EPSR01 EPSR02 EPSR03 EPSR04
Abbreviation 16-bit access
Access RW RW RW RW RW RW RW RW RW RW RW RW RW R R R R R
I/O Port - Pull-Up resistor Control Register Port 05 I/O Port - Pull-Up resistor Control Register Port 06 I/O Port - Pull-Up resistor Control Register Port 07 I/O Port - Pull-Up resistor Control Register Port 08 I/O Port - Pull-Up resistor Control Register Port 09 I/O Port - Pull-Up resistor Control Register Port 10 I/O Port - Pull-Up resistor Control Register Port 11 I/O Port - Pull-Up resistor Control Register Port 12
I/O Port - Pull-Up resistor Control Register Port 14 I/O Port - Pull-Up resistor Control Register Port 15 I/O Port - Pull-Up resistor Control Register Port 16 I/O Port - Pull-Up resistor Control Register Port 17 I/O Port - External Pin State Register Port 00 I/O Port - External Pin State Register Port 01 I/O Port - External Pin State Register Port 02 I/O Port - External Pin State Register Port 03 I/O Port - External Pin State Register Port 04
86
FME/EMDC- 2007-02-12
PR EL
IM
I/O Port - Pull-Up resistor Control Register Port 13
IN
AR
Y
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (25 / 53) Address 0004C1H 0004C2H 0004C3H 0004C4H 0004C5H 0004C6H 0004C7H 0004C8H 0004C9H 0004CAH 0004CBH 0004CCH 0004CDH 0004D0H 0004D1H 0004D2H 0004D3H 0004D4H 0004D6H 0004D7H Register I/O Port - External Pin State Register Port 05 I/O Port - External Pin State Register Port 06 I/O Port - External Pin State Register Port 07 I/O Port - External Pin State Register Port 08 I/O Port - External Pin State Register Port 09 I/O Port - External Pin State Register Port 10 I/O Port - External Pin State Register Port 11 I/O Port - External Pin State Register Port 12 I/O Port - External Pin State Register Port 13 I/O Port - External Pin State Register Port 14 I/O Port - External Pin State Register Port 15 I/O Port - External Pin State Register Port 16 I/O Port - External Pin State Register Port 17 ADC analog input enable register 0 ADC analog input enable register 1 ADC analog input enable register 2 ADC analog input enable register 3 ADC analog input enable register 4 Peripheral Resource Relocation Register 0 Peripheral Resource Relocation Register 1 Abbreviation 8-bit access EPSR05 EPSR06 EPSR07 EPSR08 EPSR09 EPSR10 EPSR11 EPSR12 EPSR13 EPSR14 EPSR15 EPSR16 EPSR17 ADER0 ADER1 ADER2 ADER3 ADER4 PRRR0 PRRR1
MB96300
Abbreviation 16-bit access R R R R R R R R R R R R R
Access
EL IM
IN
AR
Y
RW RW RW RW RW RW RW
FME/EMDC- 2007-02-12
PR
MB96300_shortspec.fm
87
MB96300 Series
Table 0-1 I/O map (26 / 53) Address 0004D8H 0004D9H 0004DAH 0004DBH 0004DCH 0004DDH 0004DEH 0004DFH 0004E0H 0004E1H 0004E2H 0004E3H 0004E4H 0004E5H 0004E6H 0004E7H 0004E8H 0004E9H 0004EAH 0004ECH 0004EDH 0004EEH 0004EFH 0004F0H 0004F1H 88 Register
Preliminary Specification
Abbreviation 8-bit access PRRR2 PRRR3 PRRR4 PRRR5 PRRR6 PRRR7 PRRR8 PRRR9 WTBRL0 WTBRH0 WTBR1 WTSR WTMR WTHR WTCER WTCKSR WTCRL WTCRH CUCR CUTDL CUTDH CUTR2L CUTR2H CUTR1L CUTR1H
Abbreviation 16-bit access
Access RW RW RW RW RW RW RW RW
Peripheral Resource Relocation Register 2 Peripheral Resource Relocation Register 3 Peripheral Resource Relocation Register 4 Peripheral Resource Relocation Register 5 Peripheral Resource Relocation Register 6 Peripheral Resource Relocation Register 7 Peripheral Resource Relocation Register 8 Peripheral Resource Relocation Register 9 RTC - Sub Second Register L RTC - Sub Second Register M RTC - Sub-Second Register H RTC - Second Register RTC - Minutes RTC - Hour
IN
AR
WTBR0 CUTD CUTR2 CUTR1
Y
RW RW RW RW RW RW RW RW RW RW RW RW RW R R R R
RTC - Timer Control Extended Register RTC - Clock select register
RTC - Timer Control Register L
RTC - Timer Control Register H
CAL - Calibration unit Control register CAL - Sub/RC-clock timer data register L CAL - Sub/RC-clock timer data register H CAL - Main clock timer data register 2 L CAL - Main clock timer data register 2 H CAL - Main clock timer data register 1 L CAL - Main clock timer data register 1 H
FME/EMDC- 2007-02-12
PR EL
IM
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (27 / 53) Address 0004F2H 0004F3H 0004F4H 0004F4H 0004F5H 0004F5H 0004F6H 0004F7H 0004F8H 0004F8H 0004F9H 0004F9H 0004FAH 000500H 000501H 000502H 000503H 000504H 000505H 000506H 000507H 000508H 000509H 00050AH 00050BH 00050CH Register RLT - Timer Control Status Register 4 Low RLT - Timer Control Status Register 4 High RLT - Reload Register 4 - for writing RLT - Reload Register 4 - for reading RLT - Reload Register 4 - for writing RLT - Reload Register 4 - for reading RLT - Timer Control Status Register 5 Low RLT - Timer Control Status Register 5 High RLT - Reload Register 5 - for writing RLT - Reload Register 5 - for reading RLT - Reload Register 5 - for writing Abbreviation 8-bit access TMCSRL4 TMCSRH4 TMRLR4 TMR4
MB96300
Abbreviation 16-bit access TMCSR4
Access RW RW W R W R RW RW
AR
TMCSRL5 TMCSRH5 TMISR TCCSL2 TCCSH2 TCCSL3 TCCSH3 OCS8 OCS9
Y
TMCSR5 TMRLR5 TMR5 TCDT2 TCCS2 TCDT3 TCCS3 OCCP8 OCCP9
W R W R RW RW RW RW RW RW RW RW RW RW RW RW RW RW 89
RLT - Reload Register 5 - for reading
RLT - Timer input select (for Cascading)
FRT - Data register of free-running timer 2 FRT - Data register of free-running timer 2 FRT - Control status register of freerunning timer 2 FRT - Control status register of freerunning timer 2
FRT - Data register of free-running timer 3 FRT - Data register of free-running timer 3 FRT - Control status register of freerunning timer 3 FRT - Control status register of freerunning timer 3 OCU - Output Compare Control Status 8 OCU - Output Compare Control Status 9 OCU - Compare Register 8 OCU - Compare Register 8 OCU - Compare Register 9
FME/EMDC- 2007-02-12
PR
EL IM
IN
MB96300_shortspec.fm
MB96300 Series
Table 0-1 I/O map (28 / 53) Address 00050DH 00050EH 00050FH 000510H 000511H 000512H 000513H 000514H 000515H 000516H 000517H 000518H 000519H 00051AH 00051BH 00051CH 00051DH 00051EH 00051FH 000520H 000521H 000522H 000522H 000523H 000524H 000525H 000526H 000527H Register OCU - Compare Register 9
Preliminary Specification
Abbreviation 8-bit access
Abbreviation 16-bit access
Access RW
OCU - Output Compare Control Status 10 OCU - Output Compare Control Status 11 OCU - Compare Register 10 OCU - Compare Register 10 OCU - Compare Register 11 OCU - Compare Register 11 ICU - Control Status Register 8/9 ICU - Edge register 8/9 ICU - Capture Register 8 ICU - Capture Register 8 ICU - Capture Register 9 ICU - Capture Register 9
OCS10 OCS11 OCCP10
RW RW RW RW RW RW RW RW IPCP8 R R IPCP9 R R RW RW IPCP10 R R IPCP11 R R RW RW W R RW RW RW BGR4 RW RW
ICU - Control Status Register 10/11 ICU - Edge register 10/11
IM
ICU - Capture Register 10 ICU - Capture Register 10 ICU - Capture Register 11 ICU - Capture Register 11
PR EL
LIN USART - Serial Mode Register 4 LIN USART - Serial Control Register 4 LIN USART - TX Register 4
LIN USART - RX Register 4
LIN USART - Serial Status 4
LIN USART - Control/Com. Register 4 LIN USART - Ext. Status Register 4 LIN USART - Baud Rate Generator Register 4 Low LIN USART - Baud Rate Generator Register 4 High
90
FME/EMDC- 2007-02-12
IN
AR
ICS89 ICE89 IPCPL8 IPCPH8 IPCPL9 IPCPH9 ICS1011 ICE1011 IPCPL10 IPCPH10 IPCPL11 IPCPH11 SMR4 SCR4 TDR4 RDR4 SSR4 ECCR4 ESCR4 BGRL4 BGRH4
Y
OCCP11
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (29 / 53) Address 00052AH 00052BH 00052CH 00052CH 00052DH 00052EH 00052FH 000530H 000531H 000534H 000535H 000536H 000536H 000537H 000538H 000539H 00053AH 00053BH 00053EH 00053FH 000540H 000540H 000541H 000542H 000543H 000544H Register LIN USART - Serial Mode Register 5 LIN USART - Serial Control Register 5 LIN USART - RX Register 5 LIN USART - TX Register 5 LIN USART - Serial Status 5 LIN USART - Control/Com. Register 5 LIN USART - Ext. Status Register 5 LIN USART - Baud Rate Generator Register 5 Low LIN USART - Baud Rate Generator Register 5 High LIN USART - Serial Mode Register 6 LIN USART - Serial Control Register 6 LIN USART - Serial TX Register 6 Abbreviation 8-bit access SMR5 SCR5 TDR5 RDR5
MB96300
Abbreviation 16-bit access
Access RW RW W R
ECCR5 ESCR5
Y
BGR5 BGR6 BGR7
SSR5
RW RW RW RW RW RW RW W R RW RW RW RW RW RW RW W R RW RW RW RW
LIN USART - Serial RX Register 6
LIN USART - Serial Status Register 6
EL IM
LIN USART - Ext. Control/Com. Register 6 LIN USART - Ext. Status Com. Register 6 LIN USART - Baud Rate Generator Register 6 LIN USART - Baud Rate Generator Register 6
LIN USART - Serial Mode Register 7
LIN USART - Serial Control Register 7 LIN USART - Serial TX Register 7 LIN USART - Serial RX Register 7 LIN USART - Serial Status Register 7 LIN USART - Ext. Control/Com. Register 7 LIN USART - Ext. Status Com. Register 7 LIN USART - Baud Rate Generator Register 7
PR
FME/EMDC- 2007-02-12
IN
AR
BGRL5 BGRH5 SMR6 SCR6 TDR6 RDR6 SSR6 ECCR6 ESCR6 BGRL6 BGRH6 SMR7 SCR7 TDR7 RDR7 SSR7 ECCR7 ESCR7 BGRL7
MB96300_shortspec.fm
91
MB96300 Series
Table 0-1 I/O map (30 / 53) Address 000545H 000548H 000549H 00054AH 00054AH 00054BH 00054CH 00054DH 00054EH 00054FH 000552H 000553H 000554H 000554H 000555H 000556H 000557H 000558H 000559H 000560H 000561H 000562H 000563H 000564H 000565H 000566H 000567H 92 Register LIN USART - Baud Rate Generator Register 7 LIN USART - Serial Mode Register 8
Preliminary Specification
Abbreviation 8-bit access BGRH7 SMR8 SCR8
Abbreviation 16-bit access
Access RW RW RW
LIN USART - Serial Control Register 8 LIN USART - Serial TX Register 8 LIN USART - Serial RX Register 8 LIN USART - Serial Status Register 8
RDR8 SSR8
Y
BGR8 BGR9 PTMR6 PCSR6
TDR8
W R RW RW RW RW RW RW RW W R RW RW RW RW RW RW RW RW RW R R W W MB96300_shortspec.fm
LIN USART - Ext. Control/Com. Register 8 LIN USART - Ext. Status Com. Register 8 LIN USART - Baud Rate Generator Register 8 LIN USART - Baud Rate Generator Register 8
LIN USART - Serial Mode Register 9
LIN USART - Serial Control Register 9 LIN USART - Serial TX Register 9
IM
LIN USART - Serial RX Register 9
LIN USART - Serial Status Register 9
LIN USART - Ext. Status Com. Register 9 LIN USART - Baud Rate Generator Register 9 LIN USART - Baud Rate Generator Register 9 Alarm Comparator 0 Alarm Comparator 0 Alarm Comparator 1 Alarm Comparator 1
PR EL
LIN USART - Ext. Control/Com. Register 9
PPG - Timer register 6 PPG - Timer register 6 PPG - Period setting register 6 PPG - Period setting register 6
FME/EMDC- 2007-02-12
IN
AR
ECCR8 ESCR8 BGRL8 BGRH8 SMR9 SCR9 TDR9 RDR9 SSR9 ECCR9 ESCR9 BGRL9 BGRH9 ACSR0 AECSR0 ACSR1 AECSR1
Preliminary Specification
Table 0-1 I/O map (31 / 53) Address 000568H 000569H 00056AH 00056BH 00056CH 00056DH 00056EH 00056FH 000570H 000571H 000572H 000573H 000574H 000575H 000576H 000577H 000578H 000579H 00057AH 00057BH 00057CH 00057DH 00057EH 00057FH 000580H 000581H 000582H Register PPG - Duty cycle register 6 PPG - Duty cycle register 6 PPG - Control status register 6 PPG - Control status register 6 PPG - Timer register 7 PPG - Timer register 7 PPG - Period setting register 7 PPG - Period setting register 7 PPG - Duty cycle register 7 PPG - Duty cycle register 7 PPG - Control status register 7 PPG - Control status register 7 PCNL6 PCNH6 PCN6 Abbreviation 8-bit access
MB96300
Abbreviation 16-bit access PDUT6 W W
Access
RW RW
Y AR
PCNL7
PTMR7
R R W W
PCSR7
PDUT7
W W
PCN7
RW RW
PPG - General Control register 1 PPG 118 Low
IN
PCNH7 GCN12
GCN1L2 GCN1H2 GCN2L2 GCN2H2
RW RW
PPG - General Control register 2 PPG 118 Low PPG - General Control register 2 PPG 118 High PPG - Timer register 8 PPG - Timer register 8
EL IM
PPG - General Control register 1 PPG 118 High
GCN22
RW RW
PTMR8
R R
PPG - Period setting register 8 PPG - Period setting register 8 PPG - Duty cycle register 8 PPG - Duty cycle register 8
PCSR8
W W
PR
PDUT8
W W
PPG - Control status register 8 PPG - Control status register 8 PPG - Timer register 9 PPG - Timer register 9 PPG - Period setting register 9
PCNL8 PCNH8
PCN8
RW RW
PTMR9
R R
PCSR9
W 93
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
MB96300 Series
Table 0-1 I/O map (32 / 53) Address 000583H 000584H 000585H 000586H 000587H 000588H 000589H 00058AH 00058BH 00058CH 00058DH 00058EH 00058FH 000590H 000591H 000592H 000593H 000594H 000595H 000596H 000597H 000598H 000599H 00059AH 00059BH 00059CH 00059DH 94 Register PPG - Period setting register 9 PPG - Duty cycle register 9 PPG - Duty cycle register 9 PPG - Control status register 9 PPG - Control status register 9 PPG - Timer register 10 PPG - Timer register 10 PPG - Period setting register 10 PPG - Period setting register 10 PPG - Duty cycle register 10 PPG - Duty cycle register 10
Preliminary Specification
Abbreviation 8-bit access
Abbreviation 16-bit access W PDUT9 W W
Access
PCNL9 PCNH9
PCN9
RW RW R R
AR
PCNL10 PCNH10 PCNL11 PCNH11 GCN1L3 GCN1H3 GCN2L3 GCN2H3
Y
PTMR10
PCSR10
W W
PDUT10
W W
PPG - Control status register 10 PPG - Control status register 10 PPG - Timer register 11 PPG - Timer register 11
IN
PCN10
RW RW
PTMR11
R R
PPG - Period setting register 11 PPG - Period setting register 11 PPG - Duty cycle register 11 PPG - Duty cycle register 11
IM
PCSR11
W W
PR EL
PDUT11
W W
PPG - Control status register 11 PPG - Control status register 11
PCN11
RW RW
PPG - General Control rgister 1 PPG 1512 Low PPG - General Control rgister 1 PPG 1512 High PPG - General Control rgister 2 PPG 1512 Low PPG - General Control rgister 2 PPG 1512 High PPG - Timer register 12 PPG - Timer register 12
GCN13
RW RW
GCN23
RW RW
PTMR12
R R
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (33 / 53) Address 00059EH 00059FH 0005A0H 0005A1H 0005A2H 0005A3H 0005A4H 0005A5H 0005A6H 0005A7H 0005A8H 0005A9H 0005AAH 0005ABH 0005ACH 0005ADH 0005AEH 0005AFH 0005B0H 0005B1H 0005B2H 0005B3H 0005B4H 0005B5H 0005B6H 0005B7H 0005B8H 0005B9H 0005BAH 0005BBH Register PPG - Period setting register 12 PPG - Period setting register 12 PPG - Duty cycle register 12 PPG - Duty cycle register 12 PDUT12 Abbreviation 8-bit access
MB96300
Abbreviation 16-bit access PCSR12 W W W W
Access
PPG - Control status register 12 PPG - Timer register 13 PPG - Timer register 13 PPG - Period setting register 13 PPG - Period setting register 13 PPG - Duty cycle register 13 PPG - Duty cycle register 13 PPG - Control status register 13 PPG - Control status register 13 PPG - Timer register 14
PCNH12
Y
PPG - Control status register 12
PCNL12
PCN12
RW RW R R
AR IN
PCNL13 PCNH13 PCNL14 PCNH14 PCNL15 PCNH15
PTMR13
PCSR13
W W
PDUT13
W W
PCN13
RW RW
EL IM
PTMR14
R R
PPG - Timer register 14
PPG - Period setting register 14 PPG - Period setting register 14 PPG - Duty cycle register 14 PPG - Duty cycle register 14
PCSR14
W W
PDUT14
W W
PPG - Control status register 14
PCN14
RW RW
PPG - Timer register 15 PPG - Timer register 15 PPG - Period setting register 15 PPG - Period setting register 15 PPG - Duty cycle register 15 PPG - Duty cycle register 15 PPG - Control status register 15 PPG - Control status register 15
PR
PPG - Control status register 14
PTMR15
R R
PCSR15
W W
PDUT15
W W
PCN15
RW RW
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
95
MB96300 Series
Table 0-1 I/O map (34 / 53) Address 0005BCH 0005BDH 0005BEH 0005BFH 0005C0H 0005C1H 0005C2H 0005C3H 0005C4H 0005C5H 0005C6H 0005C7H 0005C8H 0005C9H 0005CAH 0005CBH 0005CCH 0005CDH 0005CEH 0005CFH 0005D0H 0005D1H 0005D2H 0005D3H 0005D4H 0005D5H 0005D6H 96 Register
Preliminary Specification
Abbreviation 8-bit access GCN1L4 GCN1H4 GCN2L4 GCN2H4
Abbreviation 16-bit access GCN14
Access RW RW
PPG - General Control rgister 1 PPG 1916 Low PPG - General Control rgister 1 PPG 1916 High PPG - General Control rgister 2 PPG 1916 Low PPG - General Control rgister 2 PPG 1916 High PPG - Timer register 16 PPG - Timer register 16 PPG - Period setting register 16 PPG - Period setting register 16 PPG - Duty cycle register 16 PPG - Duty cycle register 16
GCN24
RW RW R R
AR
PCNL16 PCNH16 PCNL17 PCNH17 PCNL18
Y
PTMR16 PCSR16 PDUT16 PCN16 PTMR17 PCSR17 PDUT17 PCN17 PTMR18 PCSR18 PDUT18 PCN18
W W W W RW RW R R W W W W RW RW R R W W W W RW
PPG - Control status register 16 PPG - Control status register 16 PPG - Timer register 17 PPG - Timer register 17
PPG - Period setting register 17 PPG - Period setting register 17 PPG - Duty cycle register 17 PPG - Duty cycle register 17
PPG - Control status register 17 PPG - Control status register 17 PPG - Timer register 18 PPG - Timer register 18
PPG - Period setting register 18 PPG - Period setting register 18 PPG - Duty cycle register 18 PPG - Duty cycle register 18
PPG - Control status register 18
FME/EMDC- 2007-02-12
PR EL
IM
IN
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (35 / 53) Address 0005D7H 0005D8H 0005D9H 0005DAH 0005DBH 0005DCH 0005DDH 0005DEH 0005DFH 0005E0H 0005E1H 0005E2H 0005E3H 0005E4H 0005E5H 0005E6H 0005E7H 0005EAH 0005EBH 0005ECH 0005EDH 0005EEH 0005EFH 0005F0H 0005F1H 0005F4H 0005F5H 0005F6H Register PPG - Control status register 18 PPG - Timer register 19 PPG - Timer register 19 PPG - Period setting register 19 PPG - Period setting register 19 PPG - Duty cycle register 19 PPG - Duty cycle register 19 PPG - Control status register 19 PPG - Control status register 19 SMC 0 - PWM control register PCSR19 Abbreviation 8-bit access PCNH18 PTMR19
MB96300
Abbreviation 16-bit access
Access RW R R W W W W RW RW RW RW
AR
PCNL19 PCNH19 PWC0 PWEC0 PWS10 PWS20 PWC1 PWEC1 PWS11 PWS21 PWC2 PWEC2
SMC 0 - PWM control register PWM 1 SMC 0 - PWM control register PWM 1 SMC 0 - PWM control register PWM 2 SMC 0 - PWM control register PWM 2 SMC 0 - PWM Select register SMC 0 - PWM Select register
IN
SMC 0 - extended control register (Output enable)
Y
PDUT19
PCN19
PWC10
RW RW
EL IM
PWC20
RW RW RW RW RW RW
SMC 1 - PWM control register
SMC 1 - extended control register (Output enable) SMC 1 - PWM control register PWM 1
PWC11
RW RW
SMC 1 - PWM control register PWM 2 SMC 1 - PWM control register PWM 2 SMC 1 - PWM Select register SMC 1 - PWM Select register SMC 2 - PWM control register SMC 2 - extended control register (Output enable) SMC 2 - PWM control register PWM 1
PR
SMC 1 - PWM control register PWM 1
PWC21
RW RW RW RW RW RW
PWC12
RW 97
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
MB96300 Series
Table 0-1 I/O map (36 / 53) Address 0005F7H 0005F8H 0005F9H 0005FAH 0005FBH 0005FEH 0005FFH 000600H 000601H 000602H 000603H 000604H 000605H 000608H 000609H 00060AH 00060BH 00060CH 00060DH 00060EH 00060FH 000612H 000613H 000614H 000615H 000616H 000617H 000618H 98 Register SMC 2 - PWM control register PWM 1 SMC 2 - PWM control register PWM 2 SMC 2 - PWM control register PWM 2 SMC 2 - PWM Select register SMC 2 - PWM Select register SMC 3 - PWM control register
Preliminary Specification
Abbreviation 8-bit access
Abbreviation 16-bit access
Access RW
PWC22
RW RW
PWS12 PWS22 PWC3
RW RW RW RW PWC13 RW RW PWC23 RW RW RW RW RW RW PWC14 RW RW PWC24 RW RW
SMC 3 - extended control register (Output enable) SMC 3 - PWM control register PWM 1 SMC 3 - PWM control register PWM 1 SMC 3 - PWM control register PWM 2 SMC 3 - PWM control register PWM 2 SMC 3 - PWM Select register SMC 3 - PWM Select register SMC 4 - PWM control register
IM
SMC 4 - extended control register (Output enable) SMC 4 - PWM control register PWM 1 SMC 4 - PWM control register PWM 1 SMC 4 - PWM control register PWM 2 SMC 4 - PWM control register PWM 2 SMC 4 - PWM Select register SMC 4 - PWM Select register
PR EL
IN
AR
PWEC3 PWS13 PWS23 PWC4 PWEC4 PWS14 PWS24 PWC5 PWEC5 PWS15
Y
PWC15 PWC25
RW RW RW RW RW RW RW RW RW MB96300_shortspec.fm
SMC 5 - PWM control register
SMC 5 - extended control register (Output enable) SMC 5 - PWM control register PWM 1 SMC 5 - PWM control register PWM 1 SMC 5 - PWM control register PWM 2 SMC 5 - PWM control register PWM 2 SMC 5 - PWM Select register
FME/EMDC- 2007-02-12
Preliminary Specification
Table 0-1 I/O map (37 / 53) Address 000619H 00061CH 00061DH 00061EH 00061FH 000620H 000621H 000622H 000623H 000624H 000626H 000627H 000628H 000629H 00062AH 00062BH 00062CH 00062DH 00062EH 00062FH 000630H 000631H 000632H 000633H 000634H Register SMC 5 - PWM Select register LCD - Output Enable Register 0 (Seg 7-0) LCD - Output Enable Register 1 (Seq 158) LCD - Output Enable Register 2 (Seq 2316) LCD - Output Enable Register 3 (Seq 3124) Abbreviation 8-bit access PWS25 LCDER0 LCDER1 LCDER2 LCDER3 LCDER4 LCDER5 LCDER6 LCDER7 LCDER8 LCDVER LECR LCDCMR LCR VRAM0 VRAM1 VRAM2 VRAM3 VRAM4 VRAM5 VRAM6 VRAM7 VRAM8 VRAM9 VRAM10
MB96300
Abbreviation 16-bit access
Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
LCD - Output Enable Register 4 (Seq 3932) LCD - Output Enable Register 5 (Seq 4740) LCD - Output Enable Register 6 (Seq 5548) LCD - Output Enable Register 7 (Seq 6356) LCD - Output Enable Register 8 (Seq 7164) LCD - Output Enable Register 10 (Vx) LCD - Extended Control Register
LCD - Common pin switching register LCD - Control Register
LCD - Data register for Segment 0-1 LCD - Data register for Segment 3-2 LCD - Data register for Segment 5-4 LCD - Data register for Segment LCD - Data register for Segment
LCD - Data register for Segment 11-10 LCD - Data register for Segment LCD - Data register for Segment LCD - Data register for Segment LCD - Data register for Segment LCD - Data register for Segment 21-20
FME/EMDC- 2007-02-12
PR
EL IM
IN
AR
Y
MB96300_shortspec.fm
99
MB96300 Series
Table 0-1 I/O map (38 / 53) Address 000635H 000636H 000637H 000638H 000639H 00063AH 00063BH 00063CH 00063DH 00063EH 00063FH 000640H 000641H 000642H 000643H 000644H 000645H 000646H 000647H 000648H 000649H 00064AH 00064BH 00064CH 00064DH 0006E0H 0006E1H 0006E2H 0006E3H 0006E4H 100 Register LCD - Data register for Segment LCD - Data register for Segment LCD - Data register for Segment LCD - Data register for Segment
Preliminary Specification
Abbreviation 8-bit access VRAM11 VRAM12 VRAM13 VRAM14 VRAM15 VRAM16 VRAM17 VRAM18 VRAM19
Abbreviation 16-bit access
Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
LCD - Data register for Segment 31-30 LCD - Data register for Segment LCD - Data register for Segment LCD - Data register for Segment LCD - Data register for Segment LCD - Data register for Segment 41-40 LCD - Data register for Segment
LCD - Data register for Segment LCD - Data register for Segment LCD - Data register for Segment
LCD - Data register for Segment 51-50 LCD - Data register for Segment LCD - Data register for Segment LCD - Data register for Segment LCD - Data register for Segment LCD - Data register for Segment 61-60 LCD - Data register for Segment LCD - Data register for Segment LCD - Data register for Segment LCD - Data register for Segment LCD - Data register for Segment 71-70
IM
PR EL
External bus Area configuration register 0 External bus Area configuration register 0 External bus Area configuration register 1 External bus Area configuration register 1 External bus Area configuration register 2
IN
AR
VRAM20 VRAM21 VRAM22 VRAM23 VRAM24 VRAM25 VRAM26 VRAM27 VRAM28 VRAM29 VRAM30 VRAM31 VRAM32 VRAM33 VRAM34 VRAM35 EACL0 EACH0 EACL1 EACH1 EACL2 EAC2 EAC1 EAC0
Y
RW RW RW RW RW
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (39 / 53) Address 0006E5H 0006E6H 0006E7H 0006E8H 0006E9H 0006EAH 0006EBH 0006ECH 0006EDH 0006EEH 0006EFH 0006F0H 0006F1H 0006F2H 0006F3H 0006F4H 0006F5H 000700H 000701H 000702H 000703H 000704H 000705H 000706H 000707H 000708H 000709H 00070AH Register External bus Area configuration register 2 External bus Area configuration register 3 External bus Area configuration register 3 External bus Area configuration register 4 External bus Area configuration register 4 External bus Area configuration register 5 External bus Area configuration register 5 External bus Area select register 2 External bus Area select register 3 External bus Area select register 4 External bus Area select register 5 External bus Mode register Abbreviation 8-bit access EACH2 EACL3 EACH3 EACL4 EACH4 EACL5 EACH5 EAS2 EAS3 EAS4 EAS5 EAC4 EAC3
MB96300
Abbreviation 16-bit access
Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
External bus Clock and Function register External bus Address output enable register 0 External bus Address output enable register 1 External bus Address output enable register 2 External bus Control signal register CAN 0 - Control register
EL IM
IN
EBM
AR
EBCF EBAE0 EBAE1 EBAE2 EBCS CTRLRL0 CTRLRH0 STATRL0 STATRH0 ERRCNTL0 ERRCNTH0 BTRL0 BTRH0 INTRL0 INTRH0 TESTRL0 TESTR0 INTR0 BTR0 ERRCNT0 STATR0 CTRLR0
Y
EAC5
RW R RW R R R RW RW R R RW 101
CAN 0 - Control register (reserved) CAN 0 - Status register
CAN 0 - Status register (reserved) CAN 0 - Error Counter (Transmit) CAN 0 - Error Counter (Receive) CAN 0 - Bit Timing Register CAN 0 - Bit Timing Register CAN 0 - Interrupt Register CAN 0 - Interrupt Register CAN 0 - Test Register
FME/EMDC- 2007-02-12
PR
MB96300_shortspec.fm
MB96300 Series
Table 0-1 I/O map (40 / 53) Address 00070BH 00070CH 00070DH 000710H 000711H 000712H 000713H 000714H 000715H 000716H 000717H 000718H 000719H 00071AH 00071BH 00071CH 00071DH 00071EH 00071FH 000720H 000721H 000722H 000723H 000724H 000725H 000740H 000741H 000742H 102 Register CAN 0 - Test Register (reserved) CAN 0 - BRP Extension register CAN 0 - BRP Extension register (reserved)
Preliminary Specification
Abbreviation 8-bit access TESTRH0 BRPERL0 BRPERH0 IF1CREQL0
Abbreviation 16-bit access R BRPER0
Access
RW R
CAN 0 - IF1 Command request register CAN 0 - IF1 Command Mask register CAN 0 - IF1 Command Mask register (reserved) CAN 0 - IF1 Mask Register CAN 0 - IF1 Mask Register CAN 0 - IF1 Mask Register CAN 0 - IF1 Mask Register CAN 0 - IF1 Arbitration register CAN 0 - IF1 Arbitration register CAN 0 - IF1 Arbitration register CAN 0 - IF1 Arbitration register
IF1CREQH0 IF1CMSKL0
Y
CAN 0 - IF1 Command request register
IF1CREQ0
RW RW RW R
AR
IF1CMSKH0 IF1MSK1L0 IF1MSK1H0 IF1MSK2L0 IF1MSK2H0 IF1ARB1L0 IF1ARB1H0 IF1ARB2L0 IF1ARB2H0 IF1MCTRL0 IF1MCTRH0 IF1DTA1L0 IF1DTA1H0 IF1DTA2L0 IF1DTA2H0 IF1DTB1L0 IF1DTB1H0 IF1DTB2L0 IF1DTB2H0 IF2CREQL0 IF2CREQH0 IF2CMSKL0
IF1CMSK0
IF1MSK10
RW RW
IN
IF1MSK20
RW RW
IF1ARB10
RW RW
IM
IF1ARB20
RW RW
CAN 0 - IF1 Message Control Register CAN 0 - IF1 Message Control Register CAN 0 - IF1 Data A1 CAN 0 - IF1 Data A1
IF1MCTR0
RW RW
PR EL
IF1DTA10
RW RW
CAN 0 - IF1 Data A2 CAN 0 - IF1 Data A2 CAN 0 - IF1 Data B1 CAN 0 - IF1 Data B1 CAN 0 - IF1 Data B2 CAN 0 - IF1 Data B2
IF1DTA20
RW RW
IF1DTB10
RW RW
IF1DTB20
RW RW
CAN 0 - IF2 Command request register CAN 0 - IF2 Command request register CAN 0 - IF2 Command Mask register
IF2CREQ0
RW RW
IF2CMSK0
RW
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (41 / 53) Address 000743H 000744H 000745H 000746H 000747H 000748H 000749H 00074AH 00074BH 00074CH 00074DH 00074EH 00074FH 000750H 000751H 000752H 000753H 000754H 000755H 000780H 000781H 000782H 000783H 000790H 000791H 000792H 000793H 0007A0H 0007A1H Register CAN 0 - IF2 Command Mask register (reserved CAN 0 - IF2 Mask Register CAN 0 - IF2 Mask Register CAN 0 - IF2 Mask Register CAN 0 - IF2 Mask Register CAN 0 - IF2 Arbitration register CAN 0 - IF2 Arbitration register CAN 0 - IF2 Arbitration register CAN 0 - IF2 Arbitration register CAN 0 - IF2 Message Control Register CAN 0 - IF2 Message Control Register CAN 0 - IF2 Data A1 CAN 0 - IF2 Data A1 CAN 0 - IF2 Data A2 CAN 0 - IF2 Data A2 CAN 0 - IF2 Data B1 CAN 0 - IF2 Data B1 CAN 0 - IF2 Data B2 CAN 0 - IF2 Data B2 Abbreviation 8-bit access IF2CMSKH0 IF2MSK1L0 IF2MSK1H0 IF2MSK2L0 IF2MSK2H0 IF2ARB1L0 IF2MSK20 IF2MSK10
MB96300
Abbreviation 16-bit access R
Access
RW RW RW RW RW RW
AR
IF2ARB1H0 IF2ARB2L0 IF2ARB2H0 IF2MCTRL0 IF2MCTRH0 IF2DTA1L0 IF2DTA1H0 IF2DTA2L0 IF2DTA2H0 IF2DTB1L0 IF2DTB1H0 IF2DTB2L0 IF2DTB2H0 TREQR1L0 TREQR1H0 TREQR2L0 TREQR2H0 NEWDT1L0 NEWDT1H0 NEWDT2L0 NEWDT2H0 INTPND1L0 INTPND1H0
Y
IF2ARB10
IF2ARB20
RW RW
IF2MCTR0
RW RW
IN
IF2DTA10
RW RW
EL IM
IF2DTA20
RW RW
IF2DTB10
RW RW
IF2DTB20
RW RW
CAN 0 - Transmission Request Register CAN 0 - Transmission Request Register CAN 0 - Transmission Request Register CAN 0 - Transmission Request Register CAN 0 - New Data Register CAN 0 - New Data Register CAN 0 - New Data Register CAN 0 - New Data Register CAN 0 - Interrupt Pending Register CAN 0 - Interrupt Pending Register
TREQR10
R R
PR
TREQR20
R R
NEWDT10
R R
NEWDT20
R R
INTPND10
R R
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
103
MB96300 Series
Table 0-1 I/O map (42 / 53) Address 0007A2H 0007A3H 0007B0H 0007B1H 0007B2H 0007B3H 0007CEH 0007D0H 0007D1H 0007D2H 0007D3H 0007D4H 0007D5H 0007D6H 0007D7H 0007D8H 0007D9H 0007DAH 0007DBH 000800H 000801H 000802H 000803H 000804H 000805H 000806H 000807H 000808H 104 Register CAN 0 - Interrupt Pending Register CAN 0 - Interrupt Pending Register CAN 0 - Message Valid Register CAN 0 - Message Valid Register CAN 0 - Message Valid Register CAN 0 - Message Valid Register CAN 0 - Output enable register
Preliminary Specification
Abbreviation 8-bit access INTPND2L0 INTPND2H0 MSGVAL1L0 MSGVAL1H0 MSGVAL2L0
Abbreviation 16-bit access INTPND20 R R MSGVAL10 R R MSGVAL20 R R
Access
MSGVAL2H0 COER0
AR
SGCRL0 SGCRH0 SGFR0 SGAR0 SGDR0 SGTR0 SGCRL1 SGCRH1 SGFR1 SGAR1 SGDR1 SGTR1 CTRLRL1 CTRLRH1 STATRL1 STATRH1 ERRCNTL1 ERRCNTH1 BTRL1 BTRH1 INTRL1
Y
RW SGCR0 RW RW RW RW RW RW SGCR1 RW RW RW RW RW RW CTRLR1 RW R STATR1 RW R ERRCNT1 R R BTR1 RW RW INTR1 R
Sound Generator 0 - Control Register Low Sound Generator 0 - Control Register High
Sound Generator 0 - Frequency Register Sound Generator 0 - Amplitude Register
Sound Generator 0 - Decrement Register Sound Generator 0 - Tone Register
Sound Generator 1 - Control Register Low Sound Generator 1 - Control Register High
Sound Generator 1 - Frequency Register Sound Generator 1 - Amplitude Register Sound Generator 1 - Decrement Register Sound Generator 1 - Tone Register CAN 1 - Control register
CAN 1 - Control register (reserved) CAN 1 - Status register
CAN 1 - Status register (reserved) CAN 1 - Error Counter (Transmit) CAN 1 - Error Counter (Receive) CAN 1 - Bit Timing Register CAN 1 - Bit Timing Register CAN 1 - Interrupt Register
FME/EMDC- 2007-02-12
PR EL
IM
IN
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (43 / 53) Address 000809H 00080AH 00080BH 00080CH 00080DH 000810H 000811H 000812H 000813H 000814H 000815H 000816H 000817H 000818H 000819H 00081AH 00081BH 00081CH 00081DH 00081EH 00081FH 000820H 000821H 000822H 000823H 000824H 000825H 000840H Register CAN 1 - Interrupt Register CAN 1 - Test Register CAN 1 - Test Register (reserved) CAN 1 - BRP Extension register CAN 1 - BRP Extension register (reserved) CAN 1 - IF1 Command request register CAN 1 - IF1 Command request register CAN 1 - IF1 Command Mask register CAN 1 - IF1 Command Mask register (reserved) CAN 1 - IF1 Mask Register CAN 1 - IF1 Mask Register CAN 1 - IF1 Mask Register CAN 1 - IF1 Mask Register CAN 1 - IF1 Arbitration register CAN 1 - IF1 Arbitration register CAN 1 - IF1 Arbitration register CAN 1 - IF1 Arbitration register Abbreviation 8-bit access INTRH1 TESTRL1 TESTRH1 BRPERL1 BRPERH1 BRPER1 TESTR1
MB96300
Abbreviation 16-bit access R
Access
RW R RW R RW RW
IF1CREQL1
AR
IF1CREQH1 IF1CMSKL1 IF1CMSKH1 IF1MSK1L1 IF1MSK1H1 IF1MSK2L1 IF1MSK2H1 IF1ARB1L1 IF1ARB1H1 IF1ARB2L1 IF1ARB2H1 IF1MCTRL1 IF1MCTRH1 IF1DTA1L1 IF1DTA1H1 IF1DTA2L1 IF1DTA2H1 IF1DTB1L1 IF1DTB1H1 IF1DTB2L1 IF1DTB2H1 IF2CREQL1
Y
IF1CREQ1
IF1CMSK1
RW R
IF1MSK11
RW RW
IN
IF1MSK21
RW RW
EL IM
IF1ARB11
RW RW
IF1ARB21
RW RW
CAN 1 - IF1 Message Control Register CAN 1 - IF1 Message Control Register CAN 1 - IF1 Data A1 CAN 1 - IF1 Data A1
IF1MCTR1
RW RW
IF1DTA11
RW RW
CAN 1 - IF1 Data A2 CAN 1 - IF1 Data A2 CAN 1 - IF1 Data B1 CAN 1 - IF1 Data B1 CAN 1 - IF1 Data B2 CAN 1 - IF1 Data B2
PR
IF1DTA21
RW RW
IF1DTB11
RW RW
IF1DTB21
RW RW
CAN 1 - IF2 Command request register
IF2CREQ1
RW
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
105
MB96300 Series
Table 0-1 I/O map (44 / 53) Address 000841H 000842H 000843H 000844H 000845H 000846H 000847H 000848H 000849H 00084AH 00084BH 00084CH 00084DH 00084EH 00084FH 000850H 000851H 000852H 000853H 000854H 000855H 000880H 000881H 000882H 000883H 000890H 000891H 000892H 000893H 106 Register
Preliminary Specification
Abbreviation 8-bit access IF2CREQH1 IF2CMSKL1 IF2CMSKH1 IF2MSK1L1
Abbreviation 16-bit access
Access RW
CAN 1 - IF2 Command request register CAN 1 - IF2 Command Mask register CAN 1 - IF2 Command Mask register (reserved CAN 1 - IF2 Mask Register CAN 1 - IF2 Mask Register CAN 1 - IF2 Mask Register CAN 1 - IF2 Mask Register CAN 1 - IF2 Arbitration register CAN 1 - IF2 Arbitration register CAN 1 - IF2 Arbitration register CAN 1 - IF2 Arbitration register
IF2CMSK1
RW R
IF2MSK1H1 IF2MSK2L1
Y
IF2MSK11
RW RW RW RW
AR
IF2MSK2H1 IF2ARB1L1 IF2ARB1H1 IF2ARB2L1
IF2MSK21
IF2ARB11
RW RW
IF2ARB21
RW RW
CAN 1 - IF2 Message Control Register CAN 1 - IF2 Message Control Register CAN 1 - IF2 Data A1 CAN 1 - IF2 Data A1 CAN 1 - IF2 Data A2 CAN 1 - IF2 Data A2 CAN 1 - IF2 Data B1 CAN 1 - IF2 Data B1 CAN 1 - IF2 Data B2 CAN 1 - IF2 Data B2
IN
IF2ARB2H1 IF2MCTRL1 IF2MCTRH1 IF2DTA11 IF2MCTR1
RW RW RW RW
IM
IF2DTA1L1 IF2DTA1H1 IF2DTA2L1 IF2DTA2H1 IF2DTB1L1 IF2DTB1H1 IF2DTB2L1 IF2DTB2H1 TREQR1L1 TREQR1H1 TREQR2L1 TREQR2H1 NEWDT1L1 NEWDT1H1 NEWDT2L1 NEWDT2H1
IF2DTA21
RW RW
PR EL
IF2DTB11
RW RW
IF2DTB21
RW RW
CAN 1 - Transmission Request Register CAN 1 - Transmission Request Register CAN 1 - Transmission Request Register CAN 1 - Transmission Request Register CAN 1 - New Data Register CAN 1 - New Data Register CAN 1 - New Data Register CAN 1 - New Data Register
TREQR11
R R
TREQR21
R R
NEWDT11
R R
NEWDT21
R R
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (45 / 53) Address 0008A0H 0008A1H 0008A2H 0008A3H 0008B0H 0008B1H 0008B2H 0008B3H 0008CEH 000900H 000901H 000902H 000903H 000904H 000905H 000906H 000907H 000908H 000909H 00090AH 00090BH 00090CH 00090DH 000910H 000911H 000912H 000913H 000914H Register CAN 1 - Interrupt Pending Register CAN 1 - Interrupt Pending Register CAN 1 - Interrupt Pending Register CAN 1 - Interrupt Pending Register CAN 1 - Message Valid Register CAN 1 - Message Valid Register CAN 1 - Message Valid Register CAN 1 - Message Valid Register CAN 1 - Output enable register CAN 2 - Control register CAN 2 - Control register (reserved) CAN 2 - Status register Abbreviation 8-bit access INTPND1L1 INTPND1H1 INTPND2L1 INTPND2H1 INTPND21
MB96300
Abbreviation 16-bit access INTPND11 R R R R MSGVAL11 R R R R
Access
MSGVAL1H1 MSGVAL2L1
AR
MSGVAL2H1 COER1 CTRLRL2 CTRLRH2 STATRL2 STATRH2 ERRCNTL2 ERRCNTH2 BTRL2 BTRH2 INTRL2 INTRH2 TESTRL2 TESTRH2 BRPERL2 BRPERH2 IF1CREQL2 IF1CREQH2 IF1CMSKL2 IF1CMSKH2 IF1MSK1L2
Y
MSGVAL1L1
MSGVAL21
RW CTRLR2 RW R STATR2 RW R ERRCNT2 R R BTR2 RW RW INTR2 R R TESTR2 RW R BRPER2 RW R IF1CREQ2 RW RW IF1CMSK2 RW R IF1MSK12 RW
CAN 2 - Status register (reserved) CAN 2 - Error Counter (Transmit) CAN 2 - Error Counter (Receive) CAN 2 - Bit Timing Register CAN 2 - Bit Timing Register CAN 2 - Interrupt Register CAN 2 - Interrupt Register CAN 2 - Test Register
CAN 2 - Test Register (reserved)
CAN 2 - BRP Extension register (reserved) CAN 2 - IF1 Command request register CAN 2 - IF1 Command request register CAN 2 - IF1 Command Mask register CAN 2 - IF1 Command Mask register (reserved) CAN 2 - IF1 Mask Register
FME/EMDC- 2007-02-12
PR
CAN 2 - BRP Extension register
EL IM
IN
MB96300_shortspec.fm
107
MB96300 Series
Table 0-1 I/O map (46 / 53) Address 000915H 000916H 000917H 000918H 000919H 00091AH 00091BH 00091CH 00091DH 00091EH 00091FH 000920H 000921H 000922H 000923H 000924H 000925H 000940H 000941H 000942H 000943H 000944H 000945H 000946H 000947H 000948H 000949H 00094AH 00094BH 108 Register CAN 2 - IF1 Mask Register CAN 2 - IF1 Mask Register CAN 2 - IF1 Mask Register CAN 2 - IF1 Arbitration register CAN 2 - IF1 Arbitration register CAN 2 - IF1 Arbitration register CAN 2 - IF1 Arbitration register
Preliminary Specification
Abbreviation 8-bit access IF1MSK1H2 IF1MSK2L2 IF1MSK2H2 IF1ARB1L2 IF1ARB1H2 IF1ARB2L2
Abbreviation 16-bit access
Access RW
IF1MSK22
RW RW
IF1ARB12
RW RW RW RW
CAN 2 - IF1 Message Control Register CAN 2 - IF1 Message Control Register CAN 2 - IF1 Data A1 CAN 2 - IF1 Data A1 CAN 2 - IF1 Data A2 CAN 2 - IF1 Data A2 CAN 2 - IF1 Data B1 CAN 2 - IF1 Data B1 CAN 2 - IF1 Data B2 CAN 2 - IF1 Data B2
AR
IF1ARB2H2 IF1MCTRL2 IF1MCTRH2 IF1DTA1L2 IF1DTA1H2 IF1DTA2L2 IF1DTA2H2 IF1DTB1L2 IF1DTB1H2 IF1DTB2L2 IF1DTB2H2 IF2CREQL2 IF2CREQH2 IF2CMSKL2 IF2CMSKH2 IF2MSK1L2 IF2MSK1H2 IF2MSK2L2 IF2MSK2H2 IF2ARB1L2 IF2ARB1H2 IF2ARB2L2 IF2ARB2H2
Y
IF1ARB22
IF1MCTR2
RW RW
IF1DTA12
RW RW
IN IM
IF1DTA22
RW RW
IF1DTB12
RW RW
IF1DTB22
RW RW
CAN 2 - IF2 Command request register CAN 2 - IF2 Command request register CAN 2 - IF2 Command Mask register CAN 2 - IF2 Command Mask register (reserved CAN 2 - IF2 Mask Register CAN 2 - IF2 Mask Register CAN 2 - IF2 Mask Register CAN 2 - IF2 Mask Register
PR EL
IF2CREQ2
RW RW
IF2CMSK2
RW R
IF2MSK12
RW RW
IF2MSK22
RW RW
CAN 2 - IF2 Arbitration register CAN 2 - IF2 Arbitration register CAN 2 - IF2 Arbitration register CAN 2 - IF2 Arbitration register
IF2ARB12
RW RW
IF2ARB22
RW RW
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (47 / 53) Address 00094CH 00094DH 00094EH 00094FH 000950H 000951H 000952H 000953H 000954H 000955H 000980H 000981H 000982H 000983H 000990H 000991H 000992H 000993H 0009A0H 0009A1H 0009A2H 0009A3H 0009B0H 0009B1H 0009B2H 0009B3H 0009CEH 000A00H 000A01H 000A02H Register CAN 2 - IF2 Message Control Register CAN 2 - IF2 Message Control Register CAN 2 - IF2 Data A1 CAN 2 - IF2 Data A1 CAN 2 - IF2 Data A2 CAN 2 - IF2 Data A2 CAN 2 - IF2 Data B1 CAN 2 - IF2 Data B1 CAN 2 - IF2 Data B2 CAN 2 - IF2 Data B2 CAN 2 - Transmission Request Register CAN 2 - Transmission Request Register CAN 2 - Transmission Request Register CAN 2 - Transmission Request Register CAN 2 - New Data Register CAN 2 - New Data Register CAN 2 - New Data Register CAN 2 - New Data Register Abbreviation 8-bit access IF2MCTRL2 IF2MCTRH2 IF2DTA1L2 IF2DTA1H2 IF2DTA12
MB96300
Abbreviation 16-bit access IF2MCTR2
Access RW RW RW RW
IF2DTA2H2 IF2DTB1L2
Y
IF2DTA2L2
IF2DTA22
RW RW RW RW
AR
IF2DTB1H2 IF2DTB2L2 IF2DTB2H2 TREQR1L2 TREQR1H2 TREQR2L2 TREQR2H2 NEWDT1L2 NEWDT1H2 NEWDT2L2 NEWDT2H2 INTPND1L2 INTPND1H2 INTPND2L2 INTPND2H2 MSGVAL1L2 MSGVAL1H2 MSGVAL2L2 MSGVAL2H2 COER2 CTRLRL3 CTRLRH3 STATRL3
IF2DTB12
IF2DTB22
RW RW
TREQR12
R R
IN
TREQR22
R R
EL IM
NEWDT12
R R
NEWDT22
R R
CAN 2 - Interrupt Pending Register CAN 2 - Interrupt Pending Register CAN 2 - Interrupt Pending Register
INTPND12
R R
INTPND22
R R
CAN 2 - Message Valid Register CAN 2 - Message Valid Register CAN 2 - Message Valid Register CAN 2 - Message Valid Register CAN 2 - Output enable register CAN 3 - Control register CAN 3 - Control register (reserved) CAN 3 - Status register
PR
CAN 2 - Interrupt Pending Register
MSGVAL12
R R
MSGVAL22
R R RW
CTRLR3
RW R
STATR3
RW 109
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
MB96300 Series
Table 0-1 I/O map (48 / 53) Address 000A03H 000A04H 000A05H 000A06H 000A07H 000A08H 000A09H 000A0AH 000A0BH 000A0CH 000A0DH 000A10H 000A11H 000A12H 000A13H 000A14H 000A15H 000A16H 000A17H 000A18H 000A19H 000A1AH 000A1BH 000A1CH 000A1DH 000A1EH 000A1FH 000A20H 110 Register CAN 3 - Status register (reserved) CAN 3 - Error Counter (Transmit) CAN 3 - Error Counter (Receive) CAN 3 - Bit Timing Register CAN 3 - Bit Timing Register CAN 3 - Interrupt Register CAN 3 - Interrupt Register CAN 3 - Test Register CAN 3 - Test Register (reserved) CAN 3 - BRP Extension register CAN 3 - BRP Extension register (reserved)
Preliminary Specification
Abbreviation 8-bit access STATRH3 ERRCNTL3 ERRCNTH3 BTRL3 BTRH3
Abbreviation 16-bit access R ERRCNT3 R R BTR3
Access
RW RW R R
INTRL3
AR
INTRH3 TESTRL3 TESTRH3 BRPERL3 BRPERH3 IF1CREQL3 IF1CREQH3 IF1CMSKL3 IF1CMSKH3 IF1MSK1L3 IF1MSK1H3 IF1MSK2L3 IF1MSK2H3 IF1ARB1L3 IF1ARB1H3 IF1ARB2L3 IF1ARB2H3 IF1MCTRL3 IF1MCTRH3 IF1DTA1L3 IF1DTA1H3 IF1DTA2L3
Y
INTR3
TESTR3
RW R
BRPER3
RW R
CAN 3 - IF1 Command request register CAN 3 - IF1 Command request register CAN 3 - IF1 Command Mask register CAN 3 - IF1 Command Mask register (reserved) CAN 3 - IF1 Mask Register CAN 3 - IF1 Mask Register CAN 3 - IF1 Mask Register CAN 3 - IF1 Mask Register
IN
IF1CREQ3
RW RW
IM
IF1CMSK3
RW R
IF1MSK13
RW RW
PR EL
IF1MSK23
RW RW
CAN 3 - IF1 Arbitration register CAN 3 - IF1 Arbitration register
IF1ARB13
RW RW
CAN 3 - IF1 Arbitration register CAN 3 - IF1 Arbitration register
IF1ARB23
RW RW
CAN 3 - IF1 Message Control Register CAN 3 - IF1 Message Control Register CAN 3 - IF1 Data A1 CAN 3 - IF1 Data A1 CAN 3 - IF1 Data A2
IF1MCTR3
RW RW
IF1DTA13
RW RW
IF1DTA23
RW
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (49 / 53) Address 000A21H 000A22H 000A23H 000A24H 000A25H 000A40H 000A41H 000A42H 000A43H 000A44H 000A45H 000A46H 000A47H 000A48H 000A49H 000A4AH 000A4BH 000A4CH 000A4DH 000A4EH 000A4FH 000A50H 000A51H 000A52H 000A53H 000A54H 000A55H 000A80H 000A81H Register CAN 3 - IF1 Data A2 CAN 3 - IF1 Data B1 CAN 3 - IF1 Data B1 CAN 3 - IF1 Data B2 CAN 3 - IF1 Data B2 CAN 3 - IF2 Command request register CAN 3 - IF2 Command request register CAN 3 - IF2 Command Mask register CAN 3 - IF2 Command Mask register (reserved CAN 3 - IF2 Mask Register CAN 3 - IF2 Mask Register CAN 3 - IF2 Mask Register CAN 3 - IF2 Mask Register CAN 3 - IF2 Arbitration register CAN 3 - IF2 Arbitration register Abbreviation 8-bit access IF1DTA2H3 IF1DTB1L3 IF1DTB1H3 IF1DTB2L3 IF1DTB2H3 IF1DTB23 IF1DTB13
MB96300
Abbreviation 16-bit access
Access RW RW RW RW RW RW RW RW R
IF2CREQL3
AR
IF2CMSKL3 IF2CMSKH3 IF2MSK1L3 IF2MSK1H3 IF2MSK2L3 IF2MSK2H3 IF2ARB1L3 IF2ARB1H3 IF2ARB2L3 IF2ARB2H3 IF2MCTRL3 IF2MCTRH3 IF2DTA1L3 IF2DTA1H3 IF2DTA2L3 IF2DTA2H3 IF2DTB1L3 IF2DTB1H3 IF2DTB2L3 IF2DTB2H3 TREQR1L3 TREQR1H3
IF2CREQH3
Y
IF2CREQ3
IF2CMSK3
IF2MSK13
RW RW
IN
IF2MSK23
RW RW
EL IM
IF2ARB13
RW RW
CAN 3 - IF2 Arbitration register CAN 3 - IF2 Arbitration register
IF2ARB23
RW RW
CAN 3 - IF2 Message Control Register CAN 3 - IF2 Message Control Register CAN 3 - IF2 Data A1 CAN 3 - IF2 Data A1 CAN 3 - IF2 Data A2 CAN 3 - IF2 Data A2 CAN 3 - IF2 Data B1 CAN 3 - IF2 Data B1 CAN 3 - IF2 Data B2 CAN 3 - IF2 Data B2
IF2MCTR3
RW RW
IF2DTA13
RW RW
PR
IF2DTA23
RW RW
IF2DTB13
RW RW
IF2DTB23
RW RW
CAN 3 - Transmission Request Register CAN 3 - Transmission Request Register
TREQR13
R R
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
111
MB96300 Series
Table 0-1 I/O map (50 / 53) Address 000A82H 000A83H 000A90H 000A91H 000A92H 000A93H 000AA0H 000AA1H 000AA2H 000AA3H 000AB0H 000AB1H 000AB2H 000AB3H 000ABEH 000B00H 000B01H 000B02H 000B03H 000B04H 000B05H 000B06H 000B07H 000B08H 000B09H 000B0AH 000B0BH 000B0CH 000B0DH Register
Preliminary Specification
Abbreviation 8-bit access TREQR2L3 TREQR2H3 NEWDT1L3 NEWDT1H3 NEWDT2L3
Abbreviation 16-bit access TREQR23 R R NEWDT13 R R NEWDT23 R R R R INTPND23 R R MSGVAL13 R R MSGVAL23 R R
Access
CAN 3 - Transmission Request Register CAN 3 - Transmission Request Register CAN 3 - New Data Register CAN 3 - New Data Register CAN 3 - New Data Register CAN 3 - New Data Register CAN 3 - Interrupt Pending Register CAN 3 - Interrupt Pending Register CAN 3 - Interrupt Pending Register CAN 3 - Interrupt Pending Register CAN 3 - Message Valid Register CAN 3 - Message Valid Register CAN 3 - Message Valid Register CAN 3 - Message Valid Register CAN 3 - Output enable register CAN 4 - Control register
NEWDT2H3 INTPND1L3
AR
INTPND1H3 INTPND2L3 INTPND2H3 MSGVAL1L3 MSGVAL1H3 MSGVAL2L3 MSGVAL2H3 COER3 CTRLRL4 CTRLRH4 STATRL4 STATRH4 ERRCNTL4 ERRCNTH4 BTRL4 BTRH4 INTRL4 INTRH4 TESTRL4 TESTRH4 BRPERL4 BRPERH4
IM
IN
Y
INTPND13
RW CTRLR4 RW R STATR4 RW R ERRCNT4 R R BTR4 RW RW INTR4 R R TESTR4 RW R BRPER4 RW R
CAN 4 - Control register (reserved) CAN 4 - Status register
CAN 4 - Status register (reserved) CAN 4 - Error Counter (Transmit) CAN 4 - Error Counter (Receive) CAN 4 - Bit Timing Register CAN 4 - Bit Timing Register CAN 4 - Interrupt Register CAN 4 - Interrupt Register CAN 4 - Test Register
CAN 4 - Test Register (reserved) CAN 4 - BRP Extension register CAN 4 - BRP Extension register (reserved)
112
FME/EMDC- 2007-02-12
PR EL
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (51 / 53) Address 000B10H 000B11H 000B12H 000B13H 000B14H 000B15H 000B16H 000B17H 000B18H 000B19H 000B1AH 000B1BH 000B1CH 000B1DH 000B1EH 000B1FH 000B20H 000B21H 000B22H 000B23H 000B24H 000B25H 000B40H 000B41H 000B42H 000B43H 000B44H 000B45H Register CAN 4 - IF1 Command request register CAN 4 - IF1 Command request register CAN 4 - IF1 Command Mask register CAN 4 - IF1 Command Mask register (reserved) CAN 4 - IF1 Mask Register CAN 4 - IF1 Mask Register CAN 4 - IF1 Mask Register CAN 4 - IF1 Mask Register CAN 4 - IF1 Arbitration register CAN 4 - IF1 Arbitration register CAN 4 - IF1 Arbitration register CAN 4 - IF1 Arbitration register Abbreviation 8-bit access IF1CREQL4 IF1CREQH4 IF1CMSKL4 IF1CMSKH4 IF1MSK1L4 IF1CMSK4
MB96300
Abbreviation 16-bit access IF1CREQ4
Access RW RW RW R
Y
IF1MSK14
RW RW RW RW
IF1MSK1H4 IF1MSK2L4
AR
IF1MSK2H4 IF1ARB1L4 IF1ARB1H4 IF1ARB2L4
IF1MSK24
IF1ARB14
RW RW
IN
IF1ARB24
RW RW
IF1ARB2H4 IF1MCTRL4 IF1MCTRH4 IF1DTA14 IF1MCTR4
CAN 4 - IF1 Message Control Register CAN 4 - IF1 Message Control Register CAN 4 - IF1 Data A1 CAN 4 - IF1 Data A1 CAN 4 - IF1 Data A2 CAN 4 - IF1 Data A2 CAN 4 - IF1 Data B1 CAN 4 - IF1 Data B1 CAN 4 - IF1 Data B2 CAN 4 - IF1 Data B2
RW RW RW RW
EL IM
IF1DTA1L4 IF1DTA1H4 IF1DTA2L4 IF1DTA2H4 IF1DTB1L4 IF1DTB1H4 IF1DTB2L4 IF1DTB2H4 IF2CREQL4 IF2CREQH4 IF2CMSKL4 IF2CMSKH4 IF2MSK1L4 IF2MSK1H4
IF1DTA24
RW RW
IF1DTB14
RW RW
IF1DTB24
RW RW
CAN 4 - IF2 Command request register CAN 4 - IF2 Command request register CAN 4 - IF2 Command Mask register CAN 4 - IF2 Command Mask register (reserved CAN 4 - IF2 Mask Register CAN 4 - IF2 Mask Register
PR
IF2CREQ4
RW RW
IF2CMSK4
RW R
IF2MSK14
RW RW
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
113
MB96300 Series
Table 0-1 I/O map (52 / 53) Address 000B46H 000B47H 000B48H 000B49H 000B4AH 000B4BH 000B4CH 000B4DH 000B4EH 000B4FH 000B50H 000B51H 000B52H 000B53H 000B54H 000B55H 000B80H 000B81H 000B82H 000B83H 000B90H 000B91H 000B92H 000B93H 000BA0H 000BA1H 000BA2H 000BA3H 000BB0H 000BB1H 114 Register CAN 4 - IF2 Mask Register CAN 4 - IF2 Mask Register CAN 4 - IF2 Arbitration register CAN 4 - IF2 Arbitration register CAN 4 - IF2 Arbitration register CAN 4 - IF2 Arbitration register
Preliminary Specification
Abbreviation 8-bit access IF2MSK2L4 IF2MSK2H4 IF2ARB1L4 IF2ARB1H4 IF2ARB2L4
Abbreviation 16-bit access IF2MSK24
Access RW RW
IF2ARB14
RW RW
Y
IF2ARB24
RW RW RW RW
IF2ARB2H4
CAN 4 - IF2 Message Control Register CAN 4 - IF2 Message Control Register CAN 4 - IF2 Data A1 CAN 4 - IF2 Data A1 CAN 4 - IF2 Data A2 CAN 4 - IF2 Data A2 CAN 4 - IF2 Data B1 CAN 4 - IF2 Data B1 CAN 4 - IF2 Data B2 CAN 4 - IF2 Data B2
AR
IF2MCTRL4 IF2MCTRH4 IF2DTA1L4 IF2DTA1H4 IF2DTA2L4 IF2DTA2H4 IF2DTB1L4 IF2DTB1H4 IF2DTB2L4 IF2DTB2H4 TREQR1L4 TREQR1H4 TREQR2L4 TREQR2H4 NEWDT1L4 NEWDT1H4 NEWDT2L4 NEWDT2H4 INTPND1L4 INTPND1H4 INTPND2L4 INTPND2H4 MSGVAL1L4 MSGVAL1H4
IF2MCTR4
IF2DTA14
RW RW
IN IM
IF2DTA24
RW RW
IF2DTB14
RW RW
IF2DTB24
RW RW
CAN 4 - Transmission Request Register CAN 4 - Transmission Request Register CAN 4 - Transmission Request Register CAN 4 - Transmission Request Register CAN 4 - New Data Register CAN 4 - New Data Register CAN 4 - New Data Register CAN 4 - New Data Register
TREQR14
R R
PR EL
TREQR24
R R
NEWDT14
R R
NEWDT24
R R
CAN 4 - Interrupt Pending Register CAN 4 - Interrupt Pending Register CAN 4 - Interrupt Pending Register CAN 4 - Interrupt Pending Register CAN 4 - Message Valid Register CAN 4 - Message Valid Register
INTPND14
R R
INTPND24
R R
MSGVAL14
R R
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
Table 0-1 I/O map (53 / 53) Address 000BB2H 000BB3H 000BCEH 000C00H Register CAN 4 - Message Valid Register CAN 4 - Message Valid Register CAN 4 - Output enable register External bus area (16-bit address up to 000FFFH) Abbreviation 8-bit access MSGVAL2L4 MSGVAL2H4 COER4 EXTBUS1
MB96300
Abbreviation 16-bit access MSGVAL24 R R
Access
RW RW
FME/EMDC- 2007-02-12
PR
EL IM
MB96300_shortspec.fm
IN
AR
115
Y
MB96300 Series
s INTERRUPT VECTOR TABLE MB96V300
Offset in vector table 3FC 3F8 3F4 3F0 3EC 3E8 3E4 3E0 3DC 3D8 3D4 3D0 3CC 3C8 3C4 3C0 3BC 3B8 3B4 3B0 3A8 3A4 3A0 398 394 390 388 384 380 37C
Preliminary Specification
Vector number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 116
Vector name CALLV0 CALLV1 CALLV2 CALLV3 CALLV4 CALLV5 CALLV6 CALLV7 RESET INT9 EXCEPTION NMI DLY RC_TIMER MC_TIMER SC_TIMER EXTINT0 EXTINT1 EXTINT2 EXTINT4 EXTINT5 EXTINT6 EXTINT8 EXTINT9
DMA can clear No No No No No No No No No No No No No
Index in ICR to program IL -
Description
IN
12 No No No 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
IM
RESERVED
PR EL
EXTINT3 EXTINT7 EXTINT10 EXTINT11 EXTINT12 EXTINT13 EXTINT14 EXTINT15
3AC
39C
38C
FME/EMDC- 2007-02-12
AR
Non-Maskable Interrupt Delayed Interrupt RC Timer Main Clock Timer Sub Clock Timer Reserved External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 External Interrupt 8 External Interrupt 9 External Interrupt 10 External Interrupt 11 External Interrupt 12 External Interrupt 13 External Interrupt 14 External Interrupt 15 MB96300_shortspec.fm
Y
Preliminary Specification
Offset in vector table 378 374 370 36C 368 364 360 35C 358 354 350 34C 348 344 340 33C 338 334 330 32C 328 324 320 31C 318 314 310 308 304 300 Index in ICR to program IL 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
MB96300
Vector number 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67
Vector name CAN0 CAN1 CAN2 CAN3 CAN4 PPG0 PPG1 PPG2 PPG3 PPG4 PPG5 PPG6 PPG7 PPG8 PPG9 PPG10 PPG11 PPG12 PPG13 PPG14 PPG15 PPG16 PPG17 PPG18 RLT0 RLT1 RLT3 RLT4 RLT5 ICU0 ICU1 ICU2 PPG19
DMA can clear No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Description CAN Controller 0 CAN Controller 1 CAN Controller 2 CAN Controller 3 CAN Controller 4 Programmable Pulse Generator 1 Programmable Pulse Generator 2 Programmable Pulse Generator 3 Programmable Pulse Generator 4 Programmable Pulse Generator 5 Programmable Pulse Generator 6 Programmable Pulse Generator 7 Programmable Pulse Generator 8 Programmable Pulse Generator 9 Programmable Pulse Generator 10 Programmable Pulse Generator 11 Programmable Pulse Generator 12 Programmable Pulse Generator 13 Programmable Pulse Generator 14 Programmable Pulse Generator 15 Programmable Pulse Generator 16 Programmable Pulse Generator 17 Programmable Pulse Generator 18 Programmable Pulse Generator 19 Reload Timer 0 Reload Timer 1 Reload Timer 2 Reload Timer 3 Reload Timer 4 Reload Timer 5 Reload Timer 6 - dedicated for PPG Input Capture Unit 0 Input Capture Unit 1 Input Capture Unit 2 MB96300_shortspec.fm 117 Programmable Pulse Generator 0
Yes
EL IM
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes RLT2
Yes
PR
PPGRLT
30C
2FC 2F8 2F4 2F0
FME/EMDC- 2007-02-12
IN
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67
AR
Y
MB96300 Series
Offset in vector table 2EC 2E8 2E4 2E0 2DC 2D8 2D4 2D0 2CC 2C8 2C4 2C0 2BC 2B8 2B4 2B0 2AC 2A8 2A4 2A0 29C 298 294 290 288 284 280 278 274 270 26C 268 264
Preliminary Specification
Index in ICR to program IL 68 69 70 71 72 73 74 75 76 77 78 79 81 82 83 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102
Vector number 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 118
Vector name ICU3 ICU4 ICU5 ICU6 ICU7 ICU8 ICU9 ICU10 ICU11 OCU0 OCU1 OCU2 OCU3 OCU4 OCU5 OCU6 OCU7 OCU8 OCU9 OCU10 OCU11 FRT0 FRT1 FRT2
DMA can clear Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Description Input Capture Unit 3 Input Capture Unit 4 Input Capture Unit 5 Input Capture Unit 6 Input Capture Unit 7
IN
84 No No No No No
IM
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
PR EL
FRT3 RTC0 CAL0 SG0 IIC0 IIC1 ADC0 ALARM0 ALARM1 LINR0 LINT0
28C
27C
FME/EMDC- 2007-02-12
AR
80
Y
I2C interface I2C interface
Input Capture Unit 8 Input Capture Unit 9 Input Capture Unit 10 Input Capture Unit 11 Output Compare Unit 0 Output Compare Unit 1 Output Compare Unit 2 Output Compare Unit 4 Output Compare Unit 5 Output Compare Unit 6
Output Compare Unit 3
Output Compare Unit 7 Output Compare Unit 8 Output Compare Unit 9 Output Compare Unit 10 Output Compare Unit 11 Free Running Timer 0 Free Running Timer 1 Free Running Timer 2 Free Running Timer 3 Real Timer Clock Clock Calibration Unit Sound Generator
A/D Converter Alarm Comparator 0 Alarm Comparator 1 LIN USART 0 RX LIN USART 0 TX MB96300_shortspec.fm
Preliminary Specification
Offset in vector table 260 25C 258 254 250 24C 248 244 240 23C 238 234 230 22C 228 224 220 21C Index in ICR to program IL 103 104 105 106 107 108 109 110 112 114 116 118 120 111 113 115 117 119
MB96300
Vector number 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Vector name LINR1 LINT1 LINR2 LINT2 LINR3 LINT3 LINR4 LINT4 LINR5 LINT5 LINR6 LINT6 LINR7 LINT7 LINR8 LINT8 LINR9 LINT9
DMA can clear Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Description LIN USART 1 RX LIN USART 1 TX LIN USART 2 RX LIN USART 2 TX LIN USART 3 RX LIN USART 4 RX LIN USART 4 TX LIN USART 5 TX LIN USART 6 TX LIN USART 7 TX LIN USART 8 RX LIN USART 8 TX LIN USART 9 RX LIN USART 9 TX LIN USART 5 RX LIN USART 6 RX LIN USART 7 RX LIN USART 3 TX
FME/EMDC- 2007-02-12
PR
EL IM
IN
AR
Y
MB96300_shortspec.fm
119
MB96300 Series
s INTERRUPT VECTOR TABLE MB96(F)32x
Vector number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 120 Offset in vector table 3FC 3F8 3F4 3F0 3EC 3E8 3E4 3E0 3DC 3D8 3D4 3D0 3CC 3C8 3C4 3C0 3BC 3B8 3B4 3B0 3A8 3A4 3A0 398 394 390 388 384 380 37C 378 3AC
Preliminary Specification
Vector name CALLV0 CALLV1 CALLV2 CALLV3 CALLV4 CALLV5 CALLV6 CALLV7 RESET INT9 EXCEPTION NMI DLY RC_TIMER MC_TIMER SC_TIMER EXTINT0 EXINT1 EXTINT2 EXTINT4 EXTINT5 EXTINT7 EXTINT9 EXTINT3 PLL_UNLOCK
Index in Cleared by ICR to proDMA gram No No No No No No No No No No No No No -
Description
AR
12 13 14 15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 16
IN
No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No
Y
Non-Maskable Interrupt Delayed Interrupt RC Timer Main Clock Timer Sub Clock Timer Reserved External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 7 External Interrupt 8 External Interrupt 9 External Interrupt 10 External Interrupt 11 External Interrupt 12 External Interrupt 13 External Interrupt 14 External Interrupt 15 CAN Controller 1 CAN Controller 2 MB96300_shortspec.fm
39C
38C
FME/EMDC- 2007-02-12
PR EL
EXTINT8 EXTINT10 EXTINT11 EXTINT12 EXTINT13 EXTINT14 EXTINT15 CAN1 CAN2
IM
Preliminary Specification
Vector number 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 Offset in vector table 374 370 36C 368 364 360 35C 358 354 350 34C 348 344 340 33C 338 334 330 32C 328 324 320 31C 318 314 310 30C 308 304 300 Index in Cleared by ICR to proDMA gram Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 34 35 36 37 38 39 40 41 42 43
MB96300
Vector name PPG0 PPG1 PPG2 PPG3 PPG4 PPG5 PPG6 PPG7 PPG8 PPG9 PPG10 PPG11 PPG12 PPG13 PPG14 PPG15 PPG16 PPG17 PPG18 RLT0 RLT1 RLT3 ICU0 ICU1 ICU2 ICU3 ICU4 ICU6 ICU7 ICU8 ICU9 ICU10 PPG19
Description Programmable Pulse Generator 0 Programmable Pulse Generator 1 Programmable Pulse Generator 2 Programmable Pulse Generator 3 Programmable Pulse Generator 4 Programmable Pulse Generator 5
IN
48 49 50 51 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 52
EL IM
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes RLT2 Yes ICU5
AR
44 45 46 47
PPGRLT
PR
2FC 2F8 2F4 2F0
2EC 2E8
FME/EMDC- 2007-02-12
Y
Programmable Pulse Generator 6 Programmable Pulse Generator 7 Programmable Pulse Generator 8 Programmable Pulse Generator 9
Programmable Pulse Generator 10 Programmable Pulse Generator 11 Programmable Pulse Generator 12 Programmable Pulse Generator 13 Programmable Pulse Generator 15 Programmable Pulse Generator 16 Programmable Pulse Generator 17 Programmable Pulse Generator 18 Programmable Pulse Generator 19 Reload Timer 0 Reload Timer 1 Reload Timer 2 Reload Timer 3
Programmable Pulse Generator 14
Reload Timer 6 - dedicated for PPG Input Capture Unit 0 Input Capture Unit 1 Input Capture Unit 2 Input Capture Unit 3 Input Capture Unit 4 Input Capture Unit 5 Input Capture Unit 6 Input Capture Unit 7 Input Capture Unit 8 Input Capture Unit 9 Input Capture Unit 10 MB96300_shortspec.fm 121
MB96300 Series
Vector number 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 Offset in vector table 2E4 2E0 2DC 2D8 2D4 2D0 2CC 2C8 2C4 2C0 2BC 2B8 2B4 2B0 2AC 2A8 2A4 2A0 29C 298 294 290 288 28C
Preliminary Specification
Index in Cleared by ICR to proDMA gram Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No 70 71 72 73 74 75 76 77 78 79 80
Vector name ICU11 OCU4 OCU5 OCU6 OCU7 OCU10 OCU11 FRT0 FRT1 FRT2 FRT3 RTC0 CAL0 IIC0 ADC0 LINR2 LINT2 LINR3 LINT3 LINR7 LINT7 LINR8 LINT8
Description Input Capture Unit 11 Output Compare Unit 4 Output Compare Unit 5 Output Compare Unit 6 Output Compare Unit 7 Output Compare Unit 10 Output Compare Unit 11 Free Running Timer 0 Free Running Timer 1 Free Running Timer 2 Free Running Timer 3 Real Timer Clock Clock Calibration Unit I2C interface A/D Converter LIN USART 2 RX LIN USART 2 TX LIN USART 3 RX LIN USART 3 TX LIN USART 7 RX LIN USART 7 TX LIN USART 8 RX LIN USART 8 TX Main Flash memory interrupt
IM
PR EL
MAIN_FLASH
122
FME/EMDC- 2007-02-12
IN
84 85 86 87 88 89 90 91 92 93
AR
81 82 83
Y
MB96300_shortspec.fm
Preliminary Specification
s INTERRUPT VECTOR TABLE MB96(F)34x
MB96300
Vector number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Offset in vector table 3FC 3F8 3F4 3F0 3EC 3E8 3E4 3E0 3DC 3D8 3D4 3D0 3CC 3C8 3C4 3C0 3BC 3B8 3B4 3B0 3AC 3A8 3A4 3A0 398 394 390 388 384 380 37C 39C
Vector name CALLV0 CALLV1 CALLV2 CALLV3 CALLV4 CALLV5 CALLV6 CALLV7 RESET INT9 EXCEPTION NMI DLY RC_TIMER MC_TIMER SC_TIMER EXTINT0 EXTINT1 EXTINT2 EXTINT3 EXTINT4 EXTINT5 EXTINT6 EXTINT8 EXTINT9 EXTINT7 RESERVED
Cleared by DMA No No No No No No No No No No No No No
Index in ICR to program -
Description
IN
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
No No No No
EL IM
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
PR
EXTINT10 EXTINT11 EXTINT12 EXTINT13 EXTINT14 EXTINT15
38C
FME/EMDC- 2007-02-12
AR
-
Non-Maskable Interrupt Delayed Interrupt RC Timer Main Clock Timer Sub Clock Timer Reserved External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 External Interrupt 8 External Interrupt 9 External Interrupt 10 External Interrupt 11 External Interrupt 12 External Interrupt 13 External Interrupt 14 External Interrupt 15 MB96300_shortspec.fm 123
Y
MB96300 Series
Vector number 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 124 Offset in vector table 378 374 370 36C 368 364 360 35C 358 354 350 34C 348 344 340 33C 338 334 330 32C 328 324 320 318 314 310 308 304 300 Cleared by DMA No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Preliminary Specification
Index in ICR to program 33 34 35 36 37 38 39 40 41 42 43 44
Vector name CAN0 CAN1 PPG0 PPG1 PPG2 PPG3 PPG4 PPG5 PPG6 PPG7 PPG8 PPG9 PPG10 PPG11 PPG12 PPG13 PPG14 PPG15 RLT0 RLT1 RLT2 RLT3 ICU0 ICU1 ICU2 ICU3 ICU4 ICU5 ICU6 ICU7 PPGRLT
Description CAN Controller 0 CAN Controller 1 Programmable Pulse Generator 0 Programmable Pulse Generator 1 Programmable Pulse Generator 2 Programmable Pulse Generator 3 Programmable Pulse Generator 4 Programmable Pulse Generator 5 Programmable Pulse Generator 6 Programmable Pulse Generator 7 Programmable Pulse Generator 8 Programmable Pulse Generator 9 Programmable Pulse Generator 10 Programmable Pulse Generator 11 Programmable Pulse Generator 12 Programmable Pulse Generator 13 Programmable Pulse Generator 14 Programmable Pulse Generator 15 Reload Timer 0 Reload Timer 1 Reload Timer 2 Reload Timer 3 Reload Timer 6 - dedicated for PPG Input Capture Unit 0 Input Capture Unit 1 Input Capture Unit 2 Input Capture Unit 3 Input Capture Unit 4 Input Capture Unit 5 Input Capture Unit 6 Input Capture Unit 7 Output Compare Unit 0 Output Compare Unit 1 Output Compare Unit 2 Output Compare Unit 3 Output Compare Unit 4 MB96300_shortspec.fm
IM
PR EL
OCU0 OCU1 OCU2 OCU3 OCU4
31C
30C
2FC 2F8 2F4 2F0 2EC
FME/EMDC- 2007-02-12
IN
47 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 48
AR
45 46
Y
Preliminary Specification
Vector number 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Offset in vector table 2E8 2E4 2E0 2DC 2D8 2D4 2D0 2CC 2C8 2C4 2C0 2BC 2B8 2B4 2B0 2AC 2A8 2A4 2A0 29C 298 294 290 28C 288 284 280 27C Cleared by DMA Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes Yes Yes Yes Yes Yes Yes No No Index in ICR to program 69 70 71 72 73 74 75 76 77 78
MB96300
Vector name OCU5 OCU6 OCU7 FRT0 FRT1 IIC0 IIC1 ADC0 ALARM0 ALARM1 LINR0 LINT0 LINR1 LINT1 LINR2 LINT2 LINR3 LINT3 MAIN_FLASH SAT_FLASH LINR7 LINT7
Description Output Compare Unit 5 Output Compare Unit 6 Output Compare Unit 7 Free Running Timer 0 Free Running Timer 1 I2C interface I2C interface A/D Converter
IN
83 84 85 86 87 88 89 90 91 92 93 94 95 96
EL IM
Yes Yes Yes Yes Yes Yes No No RTC0 CAL0
LINR8 LINT8
PR
LINR9 LINT9
FME/EMDC- 2007-02-12
AR
79 80 81 82
Alarm Comparator 0 Alarm Comparator 1 LIN USART 0 RX LIN USART 0 TX LIN USART 1 RX LIN USART 1 TX LIN USART 2 RX LIN USART 2 TX LIN USART 3 RX LIN USART 3 TX Main Flash memory
Satellite Flash memory (only MB96F348H/T) LIN USART 7 RX (only MB96F34(6/7/8)R/Y) LIN USART 7 TX (only MB96F34(6/7/8)R/Y) LIN USART 8 RX (only MB96F34(6/7/8)R/Y) LIN USART 8 TX (only MB96F34(6/7/8)R/Y) LIN USART 9 RX (only MB96F34(6/7/8)R/Y) LIN USART 9 TX (only MB96F34(6/7/8)R/Y) Real Timer Clock (only MB96F34(6/7/8)R/Y) Clock Calibration Unit (only MB96F34(6/7/8)R/Y)
Y
MB96300_shortspec.fm
125
MB96300 Series
Preliminary Specification
126
FME/EMDC- 2007-02-12
PR EL
MB96300_shortspec.fm
IM
IN
AR
Y
Preliminary Specification
s INTERRUPT VECTOR TABLE MB96(F)35x
MB96300
Vector number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 19 21 23 24 25 26 27 28 29 30 31 32
Offset in vector table 3FC 3F8 3F4 3F0 3EC 3E8 3E4 3E0 3DC 3D8 3D4 3D0 3CC 3C8 3C4 3C0 3BC 3B8 3B0 3A8 3A0 398 394 390 388 384 380 37C
Vector name CALLV0 CALLV1 CALLV2 CALLV3 CALLV4 CALLV5 CALLV6 CALLV7 RESET INT9 EXCEPTION NMI DLY RC_TIMER MC_TIMER SC_TIMER EXTINT0 EXTINT2 EXTINT4 EXTINT7 EXTINT9 PLL_UNLOCK
Index in Cleared by ICR to proDMA gram No No No No No No No No No No No No No -
Description
IN
12 13 14 15 16 17 19 21 23 24 25 26 27 28 29 30 31 32
AR
-
No No No
Y
Non-Maskable Interrupt Delayed Interrupt RC Timer Main Clock Timer Sub Clock Timer Reserved External Interrupt 0 External Interrupt 2 External Interrupt 4 External Interrupt 7 External Interrupt 8 External Interrupt 9 External Interrupt 10 External Interrupt 11 External Interrupt 12 External Interrupt 13 External Interrupt 14 External Interrupt 15 CAN Controller 1 MB96300_shortspec.fm 127
39C
PR
EXTINT8 EXTINT10 EXTINT11 EXTINT12 EXTINT13 EXTINT14 EXTINT15 CAN1
38C
FME/EMDC- 2007-02-12
EL IM
No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No
MB96300 Series
Vector number 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Offset in vector table 378 374 370 36C 368 364 360 35C 358 354 350 34C 348 344 340 33C 338 334 330 32C 328 324 320 318 314 310
Preliminary Specification
Index in Cleared by ICR to proDMA gram No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 33 34 35 36 37 38 39 40 41 42 43
Vector name CAN2 PPG0 PPG1 PPG2 PPG3 PPG4 PPG5 PPG6 PPG7 PPG8 PPG9 PPG10 PPG11 PPG12 PPG13 PPG14 PPG15 PPG16 PPG17 PPG18 PPG19 RLT0 RLT1 RLT3 ICU0 ICU1
Description CAN Controller 2 Programmable Pulse Generator 0 Programmable Pulse Generator 1 Programmable Pulse Generator 2 Programmable Pulse Generator 3 Programmable Pulse Generator 4 Programmable Pulse Generator 5 Programmable Pulse Generator 6 Programmable Pulse Generator 7 Programmable Pulse Generator 8 Programmable Pulse Generator 9
IN
47 49 50 51 52 53 54 55 56 57 58 59 60 48 63 64 65 66
IM
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
PR EL
RLT2 PPGRLT ICU4 ICU6 ICU7 ICU5
AR
44 45 46
31C
30C
63 64 65 66
300
2FC 2F8 2F4
128
FME/EMDC- 2007-02-12
Y
Programmable Pulse Generator 10 Programmable Pulse Generator 11 Programmable Pulse Generator 12 Programmable Pulse Generator 13 Programmable Pulse Generator 14 Programmable Pulse Generator 15 Programmable Pulse Generator 16 Programmable Pulse Generator 17 Programmable Pulse Generator 18 Programmable Pulse Generator 19 Reload Timer 0 Reload Timer 1 Reload Timer 2 Reload Timer 3
Reload Timer 6 - dedicated for PPG Input Capture Unit 0 Input Capture Unit 1
Input Capture Unit 4 Input Capture Unit 5 Input Capture Unit 6 Input Capture Unit 7
MB96300_shortspec.fm
Preliminary Specification
Vector number Offset in vector table Index in Cleared by ICR to proDMA gram
MB96300
Vector name
Description
71 72 73 74
2E0 2DC 2D8 2D4
OCU4 OCU5 OCU6 OCU7
Yes Yes Yes Yes
71 72 73 74
Output Compare Unit 4 Output Compare Unit 5 Output Compare Unit 6 Output Compare Unit 7
78
2C4
FRT1
Yes
AR
78 81 82 83 85 86 87 88 89 90 91 92 93 84
77
2C8
FRT0
Yes
77
81 82 83 84 85 86 87 88 89 90 91 92 93
2B8 2B4 2B0 2AC 2A8 2A4 2A0 29C 298 294 290 28C 288
RTC0 CAL0 IIC0 ADC0 LINR2 LINT2 LINT3 LINT7 LINT8 LINR3
No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No
IN
EL IM
LINR7 LINR8
MAIN_FLASH
FME/EMDC- 2007-02-12
PR
Y
Free Running Timer 0 Free Running Timer 1
Real Timer Clock Clock Calibration Unit I2C interface A/D Converter LIN USART 2 RX LIN USART 2 TX LIN USART 3 RX LIN USART 3 TX LIN USART 7 RX LIN USART 7 TX LIN USART 8 RX LIN USART 8 TX
Main Flash memory interrupt
MB96300_shortspec.fm
129
MB96300 Series
s INTERRUPT VECTOR TABLE MB96(F)36x
Preliminary Specification
Vector number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 130
Offset in vector table 3FC 3F8 3F4 3F0 3EC 3E8 3E4 3E0 3DC 3D8 3D4 3D0 3CC 3C8 3C4 3C0 3BC 3B8 3B4 3B0 3A8 3A4 3A0 398 394 390 388 384 380 37C
Vector name CALLV0 CALLV1 CALLV2 CALLV3 CALLV4 CALLV5 CALLV6 CALLV7 RESET INT9 EXCEPTION NMI DLY RC_TIMER MC_TIMER SC_TIMER EXTINT0 EXTINT1 EXTINT2 EXTINT4 EXTINT5 EXTINT9
Cleared by DMA No No No No No No No No No No No No No
Index in ICR to program IL -
Description
IN
12 No No No 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 No Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes
IM
RESERVED
PR EL
EXTINT3 EXTINT12 EXTINT14 CAN1 PPG4 PPG5 PPG6 PPG7 PPG12 PPG13
3AC
39C
38C
FME/EMDC- 2007-02-12
AR
Non-Maskable Interrupt Delayed Interrupt RC Timer Main Clock Timer Sub Clock Timer Reserved External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 9 External Interrupt 12 External Interrupt 14 CAN Controller 1 Programmable Pulse Generator 4 Programmable Pulse Generator 5 Programmable Pulse Generator 6 Programmable Pulse Generator 7 Programmable Pulse Generator 12 Programmable Pulse Generator 13 MB96300_shortspec.fm
Y
Preliminary Specification
Offset in vector table 378 374 370 36C 368 364 360 35C 358 354 350 34C 348 344 340 33C Index in ICR to program IL 33 34 35 36 37 38 39 40 41 43
MB96300
Vector number 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Vector name PPG14 PPG15 RLT2 RLT3 PPGRLT ICU0 ICU1 ICU2 ICU3 FRT0 ADC0 LINR0 LINT0 LINR1 LINT1 MAIN_FLASH
Cleared by DMA Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No
Description Programmable Pulse Generator 14 Programmable Pulse Generator 15 Reload Timer 2 Reload Timer 3 Reload Timer 6 - dedicated for PPG Input Capture Unit 1 Input Capture Unit 2 Input Capture Unit 3 A/D Converter Input Capture Unit 0
IN
46 47 48
No
FME/EMDC- 2007-02-12
PR
EL IM
MB96300_shortspec.fm
AR
42 44 45
Free Running Timer 0
LIN USART 0 RX LIN USART 0 TX LIN USART 1 RX LIN USART 1 TX Main Flash memory
Y
131
MB96300 Series
s INTERRUPT VECTOR TABLE MB96(F)38x
Preliminary Specification
Vector number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 132
Offset in vector table 3FC 3F8 3F4 3F0 3EC 3E8 3E4 3E0 3DC 3D8 3D4 3D0 3CC 3C8 3C4 3C0 3BC 3B8 3B4 3B0 3A8 3A4 3A0 398 394 390 388 384 380 37C
Vector name CALLV0 CALLV1 CALLV2 CALLV3 CALLV4 CALLV5 CALLV6 CALLV7 RESET INT9 EXCEPTION NMI DLY RC_TIMER MC_TIMER SC_TIMER EXTINT0 EXTINT1 EXTINT2 EXTINT4 EXTINT5 EXTINT6 CAN0 CAN1
Index in Cleared by ICR to proDMA gram No No No No No No No No No No No No No -
Description
IN
12 No No No 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 No Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes Yes Yes Yes Yes
IM
RESERVED
PR EL
EXTINT3 EXTINT7 PPG0 PPG1 PPG2 PPG3 PPG4 PPG5
3AC
39C
38C
FME/EMDC- 2007-02-12
AR
Non-Maskable Interrupt Delayed Interrupt RC Timer Main Clock Timer Sub Clock Timer Reserved External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 CAN Controller 0 CAN Controller 1 Programmable Pulse Generator 0 Programmable Pulse Generator 1 Programmable Pulse Generator 2 Programmable Pulse Generator 3 Programmable Pulse Generator 4 Programmable Pulse Generator 5 MB96300_shortspec.fm
Y
Preliminary Specification
Vector number 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Offset in vector table 378 374 370 36C 368 364 360 35C 358 354 350 34C 348 344 340 33C 338 334 330 32C 328 324 320 31C 318 314 310 308 304 300 30C Index in Cleared by ICR to proDMA gram Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
MB96300
Vector name PPG6 PPG7 RLT0 RLT1 RLT2 RLT3 PPGRLT ICU0 ICU1 ICU2 ICU3 ICU4 ICU5 ICU6 ICU7 OCU0 OCU1 OCU2 OCU3 FRT0 FRT1
Description Programmable Pulse Generator 6 Programmable Pulse Generator 7 Reload Timer 0 Reload Timer 1 Reload Timer 2 Reload Timer 3 Reload Timer 6 - dedicated for PPG Input Capture Unit 0 Input Capture Unit 1 Input Capture Unit 2 Input Capture Unit 3 Input Capture Unit 4 Input Capture Unit 5 Input Capture Unit 6 Input Capture Unit 7 Output Compare Unit 0 Output Compare Unit 1 Output Compare Unit 2 Output Compare Unit 3 Free Running Timer 0 Free Running Timer 1 Real Timer Clock Clock Calibration Unit Sound Generator 0 Sound Generator 1 I2C interface A/D Converter Alarm Comparator 0 Alarm Comparator 1 LIN USART 0 RX LIN USART 0 TX LIN USART 1 RX LIN USART 1 TX LIN USART 2 RX LIN USART 2 TX LIN USART 4 RX MB96300_shortspec.fm 133
PR
ADC0 ALARM0 ALARM1 LINR0 LINT0 LINT1 LINR2 LINT2 LINR4 LINR1
2FC 2F8 2F4 2F0 2EC
FME/EMDC- 2007-02-12
EL IM
Yes Yes No No No No RTC0 CAL0 SG0 SG1 IIC0 Yes Yes No No Yes Yes Yes Yes Yes Yes Yes
IN
AR
Y
MB96300 Series
Vector number 69 70 71 72 Offset in vector table 2E8 2E4 2E0 2DC
Preliminary Specification
Index in Cleared by ICR to proDMA gram Yes Yes Yes No 69 70 71 72
Vector name LINT4 LINR5 LINT5 MAIN_FLASH
Description LIN USART 4 TX LIN USART 5 RX LIN USART 5 TX Main Flash memory interrupt
134
FME/EMDC- 2007-02-12
PR EL
MB96300_shortspec.fm
IM
IN
AR
Y
Preliminary Specification
s ELECTRICAL CHARACTERISTICS
MB96300
1. Absolute Maximum Ratings
Parameter Symbol VCC AVCC Power supply voltage Rating Min VSS - 0.3 VSS - 0.3 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 +4.0 40 Unit V V V V V V VCC = AVCC *1 AVCC ≥ AVRH, AVCC ≥ AVRL, AVRH > ΑVRL, AVRL ≥ ΑVSS *2 ≤ (D)VCC + 0.3V *3 ≤ (D)VCC + 0.3V *3 Remarks
AVRH, AVRL VSS - 0.3 DVCC VSS - 0.3 VSS - 0.3 VSS - 0.3 -4.0 -
Input voltage Output voltage Maximum Clamp Current Total Maximum Clamp Current “L” level maximum output current “L” level average output current “L” level maximum output current “L” level average output current “L” level maximum overall output current “L” level maximum overall output current “L” level average overall output current “L” level average overall output current “H” level maximum output current “H” level average output current “H” level average output current “H” level maximum output current
VI VO ICLAMP Σ|ICLAMP| IOL1 IOLAV1 IOL2 IOLAV2 ΣIOL1 ΣIOL2
AR
0 15 5 40 30 100 330 50 250 -15 -5 -40 -30 -100 -330 -50 -250 600 +70 +105 +125 +105 +150
Y
mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mW C C C C C
Applicable to general purpose I/O pins *4 Applicable to general purpose I/O pins *4 Normal outputs Normal outputs High current outputs High current outputs Normal outputs High current outputs Normal outputs High current outputs Normal outputs Normal outputs High current outputs High current outputs Normal outputs High current outputs Normal outputs High current outputs MB96F348H/T MB96V300 MB96F348H/T other devices
“H” level maximum overall output current “H” level maximum overall output current “H” level average overall output current “H” level average overall output current Power consumption
PR
Operating temperature
Operating temperature at Flash erase/ write Storage temperature
FME/EMDC- 2007-02-12
EL IM
ΣIOLAV1 ΣIOLAV2 IOH1 IOH2 IOHAV1 IOHAV2 ΣIOH1 ΣIOH2 ΣIOHAV1 ΣIOHAV2 PD TA TAF TSTG
IN
-40 -40 -40 -55
MB96300_shortspec.fm
135
MB96300 Series
Preliminary Specification
*1: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on. *2: If DVCC is powered before VCC, then SMC I/O pin state is undefined. To avoid this, we recommend to always power VCC before DVCC. It is not necessary to set VCC and DVCC to the same value. *3: VI and VO should not exceed (D)VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximun current to/from a input is limited by some means with external components, the ICLAMP rating supercedes the VI rating. Input/output voltages of high current ports depend on DVCC, of other ports on VCC. *4: • Applicable to all general purpose I/O pins (GP00_0 to GP17_7) • Use within recommended operating conditions. • Use at DC voltage (current) • The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the Power reset (except devices with persitant low voltage reset in internal vector mode). • When using the LCD controller, No +B signal must be applied to any LCD I/O pin (including unused SEG/COM pins). • Sample recommended circuits:
IM
IN
Limiting resistance +B input (0V to 16V)
PR EL
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
136
FME/EMDC- 2007-02-12
AR
Protective Diode
VCC R
Y
P-ch N-ch
MB96300_shortspec.fm
Preliminary Specification
2. Recommended Conditions
Value Min 3.0 4.7 0 TA -40 -40 Typ Max 5.5 10 +70 +105 +125
MB96300
Parameter Power supply voltage Smoothing capacitor at C pin Operating temperature
Symbol VCC CS
Unit V µF C
Remarks
Use a X7R Ceramic Capacitor MB96V300 MB96F348H/T MB96F3xx, MB963xx
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the devices electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure.
FME/EMDC- 2007-02-12
PR
EL IM
MB96300_shortspec.fm
IN
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
AR
Y
C
C
137
MB96300 Series
Preliminary Specification
3. DC characteristics
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Pin Condition Value Min 0.8 VCC 0.7 VCC 0.8 VCC 2.0 Typ Max (D)VCC + 0.3 (D)VCC + 0.3 (D)VCC + 0.3 (D)VCC + 0.3 VCC + 0.3 VCC + 0.3 0.2 (D)VCC 0.3 (D)VCC 0.5 (D)VCC 0.8 0.2 VCC VSS + 0.3 Unit Remarks Port inputs if CMOS Hysteresis 0.8/0.2 input is selected Port inputs if CMOS Hysteresis 0.7/0.3 input is selected Port inputs if AUTOMOTIVE Hysteresis input is selected Port inputs if TTL input is selected RSTX input pin (CMOS Hysteresis) MD input pin Port inputs if CMOS Hysteresis 0.8/0.2 input is selected Port inputs if CMOS Hysteresis 0.7/0.3 input is selected Port inputs if AUTOMOTIVE Hysteresis input is selected Port inputs if TTL input is selected RSTX input pin (CMOS Hysteresis) MD input pin
VIHS08
-
-
V
VIHS07
Y
-
V
Input “H” voltage
VIHSA VIHTTL VIHR VIHM VILS08
AR
0.8 VCC VCC 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3
V V V V V
VILS07
IM
-
IN
V
Input “L” voltage
VILSA VILTTL VILR
-
V V V V
138
FME/EMDC- 2007-02-12
PR EL
VILM
MB96300_shortspec.fm
Preliminary Specification
MB96300
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Pin Normal and High Current outputs Normal and High Current outputs Condition
4.5V ≤ (D)VCC ≤ 5.5V (D)VCC 3.0V ≤ (D)VCC < 4.5V - 0.5 IOH = -1.6mA 4.5V ≤ (D)VCC ≤ 5.5V IOH = -5mA 3.0V ≤ (D)VCC < 4.5V IOH = -3mA 4.5V ≤ DVCC ≤ 5.5V IOH = -2mA
Value Min Typ Max
Unit
Remarks
VOH2
-
-
V
Driving strength set to 2mA
Output “H” voltage VOH30 High current outputs
DVCC 0.5 3.0V ≤ DVCC < 4.5V IOH = -20mA 4.5V ≤ VCC ≤ 5.5V
IOH = -30mA
AR
VCC 0.5 -1 25 50
Y
0.4 0.4 0.4 0.4 +1 100
VOH5
(D)VCC - 0.5
-
-
V
Driving strength set to 5mA
V
Driving strength set to 30mA
VOH3
I2C outputs
IOH = -3mA
IOH = -2mA
VOL2
EL IM
Normal and High Current outputs
IOL = +5mA IOL = +3mA
Normal and High Current outputs
4.5V ≤ (D)VCC ≤ 5.5V IOL = +2mA 3.0V ≤ (D)VCC < 4.5V IOL = +1.6mA 4.5V ≤ (D)VCC ≤ 5.5V 3.0V ≤ (D)VCC < 4.5V 4.5V ≤ DVCC ≤ 5.5V IOL = +30mA 3.0V ≤ DVCC < 4.5V IOL = +20mA 4.5V ≤ VCC ≤ 5.5V IOL = +3mA 3.0V ≤ VCC < 4.5V IOL = +2mA
IN
-
3.0V ≤ VCC < 4.5V
V
V
Driving strength set to 2mA
VOL5 Output “L” voltage
V
Driving strength set to 5mA
VOL30
High current outputs
V
Driving strength set to 30mA
PR
VOL3
I2C outputs
V
Input leak current Pull-up resistance
IIL
GPnn_m
DVCC = VCC = 5.5V VSS < VI < VCC
µA kΩ
RUP
GPnn_m, RSTX
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
139
MB96300 Series
Preliminary Specification
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Pin Condition PLL Run mode with CLKB = CLKP1 = 56MHz, CLKP2 = 28MHz PLL Run mode with CLKB = CLKP1 = CLKP2 = 24MHz Writing/erasing FLASH memory in PLL Run mode with CLKB = CLKP1 = 56MHz, CLKP2 = 28MHz Main Run mode with CLKB = CLKP1 = CLKP2 = 4MHz ICCMAIN Value Min Typ 45 Max 60 Unit Remarks
mA
CLKMC, CLKRC and CLKSC active
-
20
26
mA
Y
60 100 5 8 20 48 3 6 18 46 0.5 3.5 15.5 43.5 0.15 2.5
ICCPLL
CLKMC, CLKRC and CLKSC active
AR
CLKMC, CLKRC and CLKSC active, promA gramming of one Flash macro at a time only CLKPLL and CLKRC stopped
mA
Power supply current in Run modes*
VCC
IM
Writing/erasing FLASH memory in Main Run mode with CLKB = CLKP1 = CLKP2 = 4MHz RC Run mode with CLKB = CLKP1 = CLKP2 = 2MHz Writing/erasing FLASH memory in RC Run mode with CLKB = CLKP1 = CLKP2 = 2MHz RC Run mode with CLKB = CLKP1 = CLKP2 = 100kHz Writing/erasing FLASH memory in RC Run mode with CLKB = CLKP1 = CLKP2 = 100kHz Sub Run mode with CLKB = CLKP1 = CLKP2 = 32kHz
IN
CLKPLL and CLKRC stopped, programmA ming of one Flash macro at a time only
mA
CLKMC, CLKPLL and CLKSC stopped
PR EL
ICCRCH
CLKMC, CLKPLL and CLKSC stopped, mA programming of one Flash macro at a time only CLKMC, CLKPLL and CLKSC stopped
mA
ICCRCL
CLKMC, CLKPLL and CLKSC stopped, mA programming of one Flash macro at a time only CLKMC, CLKPLL and CLKRC stopped, mA no Flash programming/erasing allowed.
ICCSUB
140
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Pin Condition PLL Sleep mode with CLKP1 = 56MHz, CLKP2 = 28MHz, TA=+25˚C Main Sleep mode with CLKP1 = CLKP2 = 4MHz, TA=+25˚C VCC RC Sleep mode with CLKP1 = CLKP2 = 2MHz, TA=+25˚C Value Min Typ 10 Max 15 Unit Remarks
ICCSPLL
mA
CLKRC and CLKSC stopped
ICCSMAIN
-
1.1
2
mA
CLKPLL CLKRC and CLKSC stopped
ICCSRCL
RC Sleep mode with CLKP1 = CLKP2 = 100kHz, TA=+25˚C Sub Sleep mode with CLKP1 = CLKP2 = 32kHz, TA=+25˚C
AR
0.35 0.08 1.5 0.35 0.35 0.3 0.05 0.04 5
Power supply current in Sleep modes*
Y
0.8 1.5 0.7 0.2 2.5 0.6 0.6 0.55 0.15 0.1 15
ICCSRCH
-
mA
CLKMC, CLKPLL and CLKSC stopped
mA
CLKMC, CLKPLL and CLKSC stopped
ICCTPLL
EL IM
VCC VCC Other than C, AVCC, AVSS, AVRH, AVRL, VCC, VSS, DVCC, DVSS -
PLL Timer mode with CLKMC = 4MHz, CLKPLL = 56MHz, TA=+25˚C Main Timer mode with CLKMC = 4MHz, TA=+25˚C RC Timer mode with CLKRC = 2MHz, TA=+25˚C RC Timer mode with CLKRC = 100kHz, TA=+25˚C
IN
ICCSSUB
mA
CLKMC, CLKPLL and CLKRC stopped
mA
CLKRC and CLKSC stopped CLKPLL CLKRC and CLKSC stopped CLKMC, CLKPLL and CLKSC stopped CLKMC, CLKPLL and CLKSC stopped CLKMC, CLKPLL and CLKRC stopped
ICCTMAIN Power supply current in Timer modes*
mA
ICCTRCH
mA
ICCTRCL
mA
PR
ICCTSUB
Sub Timer mode with CLKSC = 32kHz, TA=+25˚C At Stop Mode, TA=+25˚C
mA
Power supply current in Stop mode*
ICCH
mA
Input capacitance
CIN
pF
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
141
MB96300 Series
Preliminary Specification
* The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock connected to the Sub oscillator, low voltage detector disabled. Input/output voltages of high current ports depend on DVCC, of other ports on VCC. Note: Certain devices of MB96F348 have a higher current consumption than stated in the table above: • MB96F348HSA and MB96F348TWA: additional ~140 µA in all operation modes • MB96F348HWA: additional ~280 µA in all operation modes
(1) Clock timing
Parameter Symbol Pin
AR
Value Typ 3 16 16 3 32 32 50 1 10 5 32.768 100 2 4 5 56 32 -
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Unit MHz MHz MHz MHz kHz kHz MHz ns µs ns When using external clock When using slow frequency of RC oscillator When using fast frequency of RC oscillator Duty ratio is about 30% to 70% Remarks When using an oscillation circuit, PLL off When using an oscillation circuit, PLL on When using an external clock, PLL off When using an external clock, PLL on
Min
X0, X1 fC
3.5
Clock frequency fCL
X0, X1
IM
X0A, X1A X0 X0A X0 -
IN
3.5 16.125
fCR
Input clock pulse width
Input clock rise and falltime
Internal CPU clock frequency (Clock CLKB), internal peripheral clock frequency (Clock CLKP1)
PR EL
PWH, PWL PWHL, PWLL tCR, tCF fCLKB, fCLKP1 fCLKP2 tCP
Internal peripheral clock frequency (Clock CLKP2) Internal operating clock cycle time
(2) External Reset timing
TBD 142 FME/EMDC- 2007-02-12 MB96300_shortspec.fm
Y
Max 100 200
4. AC Characteristics
MHz
MHz ns
Preliminary Specification
(3) Power On Reset timing
TBD
MB96300
(4) Clock Output timing
(5) External Bus timing
TBD
(6) USART timing
TBD
(7) External Interrupt timing
TBD
TBD
(9) Timer related resource output timing
TBD
FME/EMDC- 2007-02-12
PR
(8) Timer related resource input timing
EL IM
MB96300_shortspec.fm
IN
AR
143
Y
TBD
MB96300 Series
(10) I2C Timing
TBD
Preliminary Specification
144
FME/EMDC- 2007-02-12
PR EL
MB96300_shortspec.fm
IM
IN
AR
Y
Preliminary Specification
5. A/D Converter
MB96300
(TA = -40 ˚C to +125 ˚C, 3.0 V ≤ AVRH - AVRL, VCC = AVCC = 3.0V - 5.5V, VSS = AVSS = 0V) Value Parameter Symbol Pin Unit Remarks Min Typ Max Resolution Total error Nonlinearity error Differential nonlinearity error Zero reading voltage Full scale reading voltage Compare time Sampling time Analog port input current Analog input voltage range Reference voltage range VOT VFST ANn ANn -3 -2.5 -1.9 AVRL 1.5 AVRH 3.5 1.0 2.0 0.5 1.2 -1 -3 AVRL+ 0.5 10 +3 +2.5 +1.9 bit LSB LSB LSB
AVRL + LSB 2.5
AR
16,500 +1 +3 AVRH AVcc 0.25 AVCC 5 5 1 5 TBD 2.5 0.7 -
AVRH - AVRH + LSB 1.5 0.5 µs µs µs µs
IAIN VAIN AVRH AVRL IA
ANn ANn AVRH/ AVRH2 AVRL AVcc AVcc
IN
-
AVRL 0.75 AVcc AVSS
EL IM
AVRH AVRH ANn
Power supply current
IAH IR IRH -
Reference voltage current Offset between input channels
PR
FME/EMDC- 2007-02-12
Y
4.5V ≤ ΑVCC ≤ 5.5V 3.0V ≤ ΑVCC < 4.5V 4.5V ≤ ΑVCC ≤ 5.5V 3.0V ≤ ΑVCC < 4.5V
µA TA = 25 ˚C
µA TA = 125 ˚C V V V mA AC Converter active µA AD Converter not operated AD Converter not operated
mA AC Converter active µA LSB
MB96300_shortspec.fm
145
MB96300 Series
6. Low Voltage Detector
(TA = -40 ˚C to +125 ˚C, VCC = 3.0V - 5.5V, VSS = 0V) Parameter Symbol Pin
Preliminary Specification
Value Min Typ 70 Max 100
Unit µA
Remarks Low voltage detector enabled (RCR:LVDE=’1’)
Power supply current
ICCLVD
VCC
7. Alarm Comparator
Y
Unit µA 70 10 5 µA µA
(TA = -40 ˚C to +125 ˚C, VCC = AVCC = 3.0V - 5.5V, VSS = AVSS = 0V) Value Parameter Symbol Pin Min Typ Max IA5ALMF Power supply current AVCC 20
Remarks
AR
3 -
Alarm comparator enabled in fast mode (one channel) Alarm comparator enabled in slow mode (one channel) Alarm comparator disabled
IA5ALMS IA5ALMH
-
8. LCD
TBD
146
FME/EMDC- 2007-02-12
PR EL
MB96300_shortspec.fm
IM
IN
Preliminary Specification
s EXAMPLE CHARACTERISTICS
MB96300
TBD
FME/EMDC- 2007-02-12
PR
EL IM
MB96300_shortspec.fm
IN
AR
147
Y
MB96300 Series
s ORDERING INFORMATION
Preliminary Specification
MCU with CAN controller
Part number MB96F326YSA PMC-G(S)E2 MB96F326RSA PMC-G(S)E2 MB96F326YWA PMC-G(S)E2 MB96F326RWA PMC-G(S)E2 MB96F346YSA PQC-G(S)E2 MB96F346RSA PQC-G(S)E2 MB96F346YWA PQC-G(S)E2 MB96F346RWA PQC-G(S)E2 MB96F346YSA PMC-G(S)E2 MB96F346RSA PMC-G(S)E2 MB96F346YWA PMC-G(S)E2 MB96F346RWA PMC-G(S)E2 MB96F347YSA PQC-G(S)E2 MB96F347RSA PQC-G(S)E2 MB96F347YWA PQC-G(S)E2 MB96F347RWA PQC-G(S)E2 MB96F347YSA PMC-G(S)E2 MB96F347RSA PMC-G(S)E2 MB96F347YWA PMC-G(S)E2 MB96F348YSA PQC-G(S)E2 No No Yes No No Yes No Yes Satellite flash memory Subclock Persistant Low Voltage Reset Yes No Yes No Yes No Package Remarks
No
IM
Yes No Yes No Yes No Yes
IN
No No
PR EL
MB96F347RWA PMC-G(S)E2 MB96F348RSA PQC-G(S)E2
MB96F348YWA PQC-G(S)E2 MB96F348YSA PMC-G(S)E2
MB96F348RWA PQC-G(S)E2 MB96F348RSA PMC-G(S)E2
MB96F348YWA PMC-G(S)E2
MB96F348RWA PMC-G(S)E2
148
FME/EMDC- 2007-02-12
AR
Yes No No No No Yes No Yes No Yes No Yes No Yes No Yes No Yes No Yes Yes Yes
Y
80 pin Plastic LQFP (FPT-80P-M21)
100 pin Plastic QFP (FPT-100P-M22)
100 pin Plastic LQFP (FPT-100P-M20)
100 pin Plastic QFP (FPT-100P-M22)
100 pin Plastic LQFP (FPT-100P-M20)
100 pin Plastic QFP (FPT-100P-M22)
100 pin Plastic LQFP (FPT-100P-M20)
MB96300_shortspec.fm
Preliminary Specification
Satellite flash memory Persistant Low Voltage Reset Yes No Yes No Yes No Yes No Yes No
MB96300
Part number MB96F348TSA PQC-G(S)E2 MB96F348HSA PQC-G(S)E2 MB96F348TWA PQC-G(S)E2 MB96F348HWA PQC-G(S)E2 MB96F348TSA PMC-G(S)E2 MB96F348HSA PMC-G(S)E2 MB96F348TWA PMC-G(S)E2 MB96F348HWA PMC-G(S)E2 MB96F356YSA PMC-G(S)E2 MB96F356RSA PMC-G(S)E2 MB96F356YWA PMC-G(S)E2 MB96F356RWA PMC-G(S)E2 MB96F356YSA PMC1-G(S)E2 MB96F356RSA PMC1-G(S)E2 MB96F356YWA PMC1-G(S)E2 MB96F356RWA PMC1-G(S)E2 MB96F386YSA PMC-G(S)E2 MB96F386RSA PMC-G(S)E2 MB96F386YWA PMC-G(S)E2 MB96F386RWA PMC-G(S)E2 MB96F387YSA PMC-G(S)E2 MB96F387RSA PMC-G(S)E2 MB96F387YWA PMC-G(S)E2 MB96F387RWA PMC-G(S)E2 MB96V300RB-ES
Subclock
Package
Remarks
No Yes Yes No Yes No Yes No No Yes No
100 pin Plastic QFP (FPT-100P-M22)
EL IM
Yes No No Yes Emulated by ext. RAM Yes
IN
No No No No No No
FME/EMDC- 2007-02-12
PR
AR
Yes No Yes No Yes Yes Yes Yes Yes
Y
100 pin Plastic LQFP (FPT-100P-M20)
64 pin Plastic LQFP (FPT-64P-M23)
64 pin Plastic LQFP (FPT-64P-M24)
120 pin Plastic LQFP (FPT-120P-M21)
416 pin Plastic BGA For evalua(BGA416-M02) tion
MB96300_shortspec.fm
149
MB96300 Series
MCU without CAN controller
Part number MB96F326ASA PMC-G(S)E2 MB96F326AWA PMC-G(S)E2 MB96F346ASA PQC-G(S)E2 MB96F346AWA PQC-G(S)E2 MB96F346ASA PMC-G(S)E2 MB96F346AWA PMC-G(S)E2 MB96F347ASA PQC-G(S)E2 MB96F347AWA PQC-G(S)E2 MB96F347ASA PMC-G(S)E2 MB96F347AWA PMC-G(S)E2 MB96F348ASA PQC-G(S)E2 MB96F348AWA PQC-G(S)E2 MB96F348ASA PMC-G(S)E2 MB96F348AWA PMC-G(S)E2 MB96F348CSA PQC-G(S)E2 MB96F348CWA PQC-G(S)E2 MB96F348CSA PMC-G(S)E2 MB96F348CWA PMC-G(S)E2 MB96F356ASA PMC-G(S)E2 MB96F356AWA PMC-G(S)E2 MB96F356ASA PMC1-G(S)E2 Yes No No No Satellite flash memory No
Preliminary Specification
Subclock No Yes No Yes No Yes No Yes No Yes No Yes No Yes No Yes No Yes No
Package 80 pin Plastic LQFP (FPT-80P-M21) 100 pin Plastic QFP (FPT-100P-M22) 100 pin Plastic LQFP (FPT-100P-M20)
Remarks
IM
Yes No Yes
PR EL
No
MB96F356AWA PMC1-G(S)E2
150
FME/EMDC- 2007-02-12
IN
AR
100 pin Plastic QFP (FPT-100P-M22)
100 pin Plastic LQFP (FPT-100P-M20) 100 pin Plastic QFP (FPT-100P-M22)
100 pin Plastic LQFP (FPT-100P-M20) 100 pin Plastic QFP (FPT-100P-M22)
100 pin Plastic LQFP (FPT-100P-M20) 64 pin Plastic QFP (FPT-64P-M23) 64 pin Plastic LQFP (FPT-64P-M24)
Y
MB96300_shortspec.fm
Preliminary Specification
s Package dimensions of MB96(F)32x LQFP 80P
80-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight
MB96300
0.50 mm 12 mm × 12 mm Gullwing Plastic mold 1.70 mm Max 0.47 g P-LFQFP80-12×12-0.50
(FPT-80P-M21) 80-pin plastic LQFP (FPT-80P-M21)
14.00±0.20(.551±.008)SQ
* 12.00±0.10(.472±.004)SQ
60 41
IN
40 21
61
EL IM
"A"
20
AR
Code (Reference)
0.145±0.055 (.006±.002) 0.08(.003) 1.50 –0.10 .059 –.004
+0.20 +.008
Y
Details of "A" part 0˚~8˚ 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006)
(Mounting height)
INDEX
80
0.10±0.05 (.004±.002) (Stand off)
PR
0.25(.010)
LEAD No.
1
0.50(.020)
0.20±0.05 (.008±.002)
0.08(.003)
M
Dimensions in mm (inches). Note: The values in parentheses are reference values.
C
2006 FUJITSU LIMITED F80035S c 2 2
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
151
MB96300 Series
Preliminary Specification
s PACKAGE DIMENSION MB96(F)34x LQFP 100P
100-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.50 mm 14.0 mm × 14.0 mm Gullwing Plastic mold 1.70 mm Max
AR
Code (Reference)
51
(FPT-100P-M20)
100-pin plastic LQFP (FPT-100P-M20)
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
75
76
IM
50
PR EL
IN
0.08(.003) Details of "A" part 1.50 –0.10 .059 –.004 (Mounting height)
+0.20 +.008
INDEX
Y
0˚~8˚
0.65 g P-LFQFP100-14×14-0.50
100
26
0.10±0.10 (.004±.004) (Stand off) 0.25(.010)
"A"
(0.50(.020)) 0.60±0.15 (.024±.006)
1
25
0.50(.020)
0.20±0.05 (.008±.002)
0.08(.003)
M
0.145±0.055 (.0057±.0022)
C
2005 FUJITSU LIMITED F100031S-c-2-1
Dimensions in mm (inches). Note: The values in parentheses are reference values
• •
152
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
s PACKAGE DIMENSION MB96(F)34x QFP 100P
100-pin plastic QFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Code (Reference) 0.65 mm
MB96300
14.00 × 20.00 mm Gullwing Plastic mold 3.35 mm MAX
(FPT-100P-M22) (FPT-100P-M06) 100-pin plastic QFP (FPT-100P-M22)
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80 51
81
EL IM
31 30
IN
50
17.90±0.40 (.705±.016)
*14.00±0.20 (.551±.008)
INDEX
100
1
0.65(.026)
PR
0.32±0.05 (.013±.002)
0.13(.005)
M
AR
0.17±0.06 (.007±.002)
Y
P-QFP100-14×20-0.65
0.10(.004)
Details of "A" part 0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8˚
"A"
0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006)
0.25±0.20 (.010±.008) (Stand off)
C
2002 FUJITSU LIMITED F100008S-c-5-5
Dimensions in mm (inches). Note: The values in parentheses are reference values.
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
153
MB96300 Series
Preliminary Specification
s PACKAGE DIMENSION MB96(F)35x LQFP 64P - M23
64-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Code (Reference) 0.65 mm 12 × 12 mm Gullwing Plastic mold 1.70 mm MAX
(FPT-64P-M23) (FPT-64P-M09) 64-pin plastic LQFP (FPT-64P-M23)
14.00±0.20(.551±.008)SQ
* 12.00±0.10(.472±.004)SQ
48 33
49
IM
32
IN
17
AR
0.145±0.055 (.0057±.0022) 0.10(.004)
16
Y
P-LQFP64-12×12-0.65
Details of "A" part 1.50 –0.10 .059 –.004
+0.20 +.008
PR EL
(Mounting height)
0.25(.010) 0~8˚
INDEX
64
1
"A"
0.65(.026)
0.32±0.05 (.013±.002)
0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006)
0.10±0.10 (.004±.004) (Stand off)
0.13(.005)
M
C
2003 FUJITSU LIMITED F64018S-c-3-5
Dimensions in mm (inches). Note: The values in parentheses are reference values.
154
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
s PACKAGE DIMENSION MB96(F)35x LQFP 64P- M24
64-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight
MB96300
0.50 mm 10.0 × 10.0 mm Gullwing Plastic mold 1.70 mm MAX 0.32 g P-LFQFP64-10×10-0.50
(FPT-64P-M24) 64-pin plastic LQFP (FPT-64P-M24)
12.00±0.20(.472±.008)SQ
* 10.00±0.10(.394±.004)SQ
48 33
49
EL IM
32 17 16
IN
"A" 0.08(.003)
M
AR
Code (Reference)
0.145±0.055 (.006±.002) 0.08(.003) 1.50 –0.10 .059 –.004
+0.20 +.008
INDEX
64
Y
Details of "A" part 0˚~8˚ 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006)
(Mounting height)
0.10±0.10 (.004±.004) (Stand off)
PR
0.25(.010)
LEAD No.
1
0.50(.020)
0.20±0.05 (.008±.002)
C
2005 FUJITSU LIMITED F64036S-c-1-1
Dimensions in mm (inches). Note: The values in parentheses are reference values
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
155
MB96300 Series
Preliminary Specification
s PACKAGE DIMENSION MB96(F)36x LQFP 48P
48-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.50 mm 7 × 7 mm Gullwing Plastic mold 1.70 mm MAX
AR
Code (Reference)
(FPT-48P-M26)
48-pin plastic LQFP (FPT-48P-M26)
9.00±0.20(.354±.008)SQ
* 7.00 –0.10 .276 –.004 SQ
36 25
+0.40
+.016
37
IM
24 13
IN
"A" 0.08(.003)
M
0.145±0.055 (.006±.002)
PR EL
INDEX
0.08(.003)
Y
0.17 g P-LFQFP48-7×7-0.50
Details of "A" part 1.50 –0.10 .059 –.004
+0.20 +.008
(Mounting height)
48
0˚~8˚
0.10±0.10 (.004±.004) (Stand off)
LEAD No. 0.50(.020)
1
12
0.20±0.05 (.008±.002)
0.25(.010) 0.60±0.15 (.024±.006)
C
2003 FUJITSU LIMITED F48040S-c-2-2
Dimensions in mm (inches). Note: The values in parentheses are reference values.
156
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
s PACKAGE DIMENSION MB96(F)38x LQFP 120P
120-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.50 mm
MB96300
16.0 × 16.0 mm Gullwing Plastic mold 1.70 mm MAX
AR
Code (Reference)
61 60
(FPT-120P-M21) 120-pin plastic LQFP (FPT-120P-M21)
18.00±0.20(.709±.008)SQ
* 16.00 –0.10 .630 +.016 SQ –.004
90
+0.40
91
EL IM
31 30
IN
0.08(.003)
Details of "A" part 1.50 –0.10 .059 –.004
+0.20 +.008
Y
0~8˚ 0.60±0.15 (.024±.006)
0.88 g
P-LFQFP120-16×16-0.50
(Mounting height)
INDEX
120
"A" 0.10±0.05 (.004±.002) (Stand off) 0.25(.010)
PR
0.50(.020)
LEAD No.
1
0.22±0.05 (.009±.002)
0.08(.003)
M
0.145 .006
+0.05 –0.03 +.002 –.001
C
2002 FUJITSU LIMITED F120033S-c-4-4
Dimensions in mm (inches). Note: The values in parentheses are reference values.
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
157
MB96300 Series
s Revision History
Preliminary Specification
Revision 11 11 11 11 11 11 12 12 12 13 13 13 13 13 13 13 14 15 15
Date 2006-09-27 2006-09-27 2006-09-27 2006-09-29 2006-10-01 2006-10-04 2006-11-01 2006-11-01 2006-11-15 2006-11-29 2006-12-07 2006-12-11 2006-12-11 2006-12-11 2006-12-11 2006-12-11 2006-12-12 2006-12-13 2006-12-13
Modification “Description” and “Features”: “64MHz” replaced by “up to 64MHz” “Pin Description”: New circuit type “N” for I2C pins added. Cicruit types I, J, K and L: driving strength corrected from 4mA to 5/2mA “AD Converter”: Conversion and Sampling time definitions added Electrical characteristics updated
In Memory map: bank configuration record are added
MB96(F)38X pin description: Pin 93 and pin 103 corrected INT3_R1 function added, INTxR function renamed to INTx_R Electrical characteristics for RC clock modes updated (reduced values). Note for additional current of certain MB96F348 devices added
Made PLL unlock interrupt RESERVED. C-Pin Capacitor spec added (4.7-10uF X7R cap); Bank0/1 Flash -> Main/Sat Flash, ICC values slightly modified after corner sample review. F35X: 2 -> 4 UARTS, 0 -> 1 Real time clock IAIN=3uA max at high temp Max operating temperature for Flash erase/write 105 deg, 10.000 cycles 64 pin package is “FPT-64P-M09” (wrong package was stated in lineup) All reloacated pin functions renamed from xxxR to xxx_R Removed small RAM size devices from RAMSTART table. Ordering information: All part numbers changed from “-HE2” to “E2”
16 17 17 18
2007-01-22 2007-01-23 2007-01-26 2007-01-29
158
FME/EMDC- 2007-02-12
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Block diagrams corrected: External bus pin names corrected, mode pins added, clock output pin names corrected. External bus address name changed: A0-A23 -> A00 - A23, AD0 - AD7 -> AD00 - AD07. Added MB96320. Modified pin-out and interrupt vector table of MB9635x. Modified pin out of MB9636x. Added package dimension MB96(F)356 LQFP 64P - M24
Updated product line-up. Added MB96F326 and MB96F356 ordering information Corrected ordering information: MB96F326 PQC -> MB96F326 PMC
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changed max. frequence on cover page and feature list from 64MHz/15.6ns to 56MHz / 17.8ns to avoid confusion
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MB96300_shortspec.fm
Preliminary Specification
Revision 19 Date 2007-02-07 Modification added MB96384, MB96385 to product lineup added line for ADC-Reference switch to product line up Pinout MB96(F)38x: added exception for MB96384/5 Features: added 80-pin Product line up: removed MB96xxxA fixed formating for RTC Pin description MB96(F)326...: TTG10_R -> TTG11_R IO-Map: removed DMA-Turbo Register
MB96300
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2007-02-12
FME/EMDC- 2007-02-12
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MB96300_shortspec.fm
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