GM3845AS8T

Description GM384XA series is high performance with fixed-frequency current mode PWM controllers. They are specially designed for off-Line and DC-to-DC converter applications. They require minimal external components to precisely tailor performance in a wide variety of applications. GM384XA series includes a trimmed oscillator for precise duty cycle control, a temperature-compensated reference, high gain error amplifier, a current-sensing comparator, and a high-current totem pole output for driving a power MOSFET. On-chip protection features include undervoltage lockouts with hysteresis for both input and reference, cycle-by-cycle current limiting, programmable output deadtime, and a latch for single pulse metering. All these are in a simple DIP-8 or SOP-8 package! GM3842A and GM3844A have UVLO thresholds of 16V (on)/10V(off); GM3843A and GM3845A have UVLO thresholds of 8.4V (on)/ 7.6V (off). GM3842A and GM3843A operate within 100% duty cycle; GM3844A and GM3845A operate within 50% duty cycle. Features Low Start-Up and Operating Current Automatic Feed Forward Compensation Current Mode Operating Frequency up to 500kHz Trimmed Oscillator Discharge Current for Precise Duty Cycle Control Latching PWM for Cycle-By-Cycle Current Limiting Undervoltage Lockout with Hysteresis High Current Totem Pole Output The GM384XA Have Start-up Current 0.17mA SIMPLIFIED BLOCK DIAGRAM VCC 7 Vref 8 R R VREF Undervoltage LOCKOUT OSCILLATOR Error Amplifier + Latching PWM 5 Power Ground 3 Current Sense Input 5 GND 5.0V REFERENCE VCC Undervoltage LOCKOUT 7 VC RT/ CT 4 6 Output Voltage Feedback Input 2 Output Compensation 1 GM3842A, GM3843A, GM3844A, GM3845A 1 w ww.gammamicro.com GM 431 V1.0 MARKING INFORMATION & PIN CONFIGURATIONS (TOP VIEW) SOP - 8 VCC VREF 8765 DIP - 8 OUTPUT GND VCC VREF 8765 GM384X Ayww OUTPUT GND GM384X Ayww 1234 1234 COMP FB RT / C T ISENSE COMP FB RT / C T ISENSE A = Assembly Location Y = Year W W = Weekly ORDERING INFORMATION (Green Package Products are available now!) GM3842A, GM3843A, GM3844A, GM3845A O rdering Number GM3842AS8T GM3842AS8R GM3842AD8T GM3843AS8T GM3843AS8R GM3843AD8T GM3844AS8T GM3844AS8R GM3844AD8T GM3845AS8T GM3845AS8R GM3845AD8T Package SOP - 8 SOP - 8 DIP-8 SOP - 8 SOP - 8 DIP-8 SOP - 8 SOP - 8 DIP-8 SOP - 8 SOP - 8 DIP-8 Shipping 100 Units/ Tube 2,500 Units/ Tape & Reel 60 Units/ Tube 100 Units/ Tube 2,500 Units/ Tape & Reel 60 Units/ Tube 100 Units/ Tube 2,500 Units/ Tape & Reel 60 Units/ Tube 100 Units/ Tube 2,500 Units/ Tape & Reel 60 Units/ Tube * For detail ordering number identification, please see last page. ** For green package products, please add " G" at the end of each part number. 2 ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage (low impedance source) Output Current, Source or Sink * Input Voltage (analog inputs pins 2) Maximum Power Dissipation (TA= 25°C) Error Amp Output Sink Current Storage Temperature Range Lead Temperature (soldering 5 sec.) * Note: Maximum Package Power Dissipation Limits must be observed. SYMBOL VCC IO VI PD ISINK(E.A) Tstg TL VALUE 30 ±1.0 - 0.3 to + 5.5 1.0 10 - 65 to + 150 260 UNIT V A V W mA °C °C PACKAGE PIN DESCRIPTION 1 2 COMP VFB ISENSE RT/ CT GND Output VCC VREF This pin is Error Amplifier output and is made available for loop compensation. This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider. A voltage proportional to inductor current connected to this input. The PWM uses this information to terminate the output switch conduction. Oscillator frequency and maximum Output cycle are programmed by connecting resistor RT to VREF and capacitor CT to ground. This pin is the combined control circuitry and power ground. This output directly drives the gate of a power MOSFET. Peak current up to 1.0A are sourced and sunk by this pin. This pin is the positive supply of the control integrated circuit (IC) This is the reference output. It provides charging current for capacitor CT through resistor RT. 3 4 5 6 7 8 GM3842A, GM3843A, GM3844A, GM3845A 3 PIN lead FUNCTION FUNCTION P ower Management REPRESENTATIVE BLOCK DIAGRAM VCC VIN VCC 7 8 Vref R 2.5V RT R Internal Baias Reference Regulator + VCC UVLO + 36V VC 7 + 3.6V + Vref UVLO 4 Oscillator (Toggle flip flop used only in GM3844A, GM3845A) Output 6 Q1 CT + 1/2 Vref 1.0mA TQ S 2R R 1.0V R Current Sense Comparator 5 GND + PWM Latch 3 Current Sense Input Q Power Ground 5 GM3842A, GM3843A, GM3844A, GM3845A + 2 Voltage Feedback Input 1 Output Compensation Error Amplifier + + - = Sink Only Positive True Logic RS TIMING DIAGRAM Capacitor CT Latch "Set" Input Output/ Compensation Current Sense Input Latch "Reset" Input Output Latch RT/ Small CT Small RT/ Latch CT 4 ELECTRICAL CHARACTERISTICS (TA = 0°C to 70°C, *VCC=15V, CT=3.3nF, RT=10kW, unless otherwise specified ) CHARACTERISTICS Reference Section Reference Output Voltage Line Regulation Load Regulation Short Circuit Output Current Oscillator Section Oscillation Frequency Frequency Change with Voltage Oscillator Amplitude Error Amplifier Section Input Bias Current Input Voltage Open Loop Voltage Gain Power Supply Rejection Ratio Output Sink Current Output Source Current High Output Voltage Low Output Voltage Current Sense Section Current Sense Input Voltage Gain Maximum Input Signal Supply Voltage Rejection Input Bias Current Output Section Low Output Voltage SYMBOL TEST CONDITIONS MIN TYP MAX UNIT VREF DVREF DVREF ISC TJ= 25°C, IREF= 1mA 12V 1mA VCC 25V IREF 20mA TA=25°C TJ= 25°C 12V VCC 25V (Peak to Peak) 4.9 5.0 6.0 6.0 -100 5.1 20 25 -180 V mV mV mA f Df/ DVCC V(OSC) IBIAS VI(EA) AVOL PSRR ISINK ISOURCE VOH VOL GV VI(MAX) SVR IBIAS 12V 47 52 0.05 1.6 57 1.0 kHz % V VFB= 3V VPIN1=2.5V 2V 12V VO 4V VCC 25V 2.42 65 60 2 -0.5 5.0 -0.1 2.5 90 70 7 -1.0 6.0 0.8 -2 2.58 µA V dB dB mA mA V VPIN2=2.7V, VPIN1=1.1V VPIN2=2.3V, VPIN1=5V VPIN2=2.3V, RL=15kW to GND VPIN2=2.7V, RL=15kW to PIN8 (Note 1 and 2) VPIN1=5V (Note 1) VCC 25V (Note 1) VPIN3=3V ISINK= 20mA ISINK= 200mA ISOURCE= 20mA ISOURCE= 200mA TJ= 25°C, CL= 1nF(Note 3) TJ= 25°C, CL= 1nF(Note 3) 1.1 V 2.85 0.9 3.0 1.0 70 -3.0 3.15 1.1 V/ V dB -10 µA VOL VOH tR tF 0.08 1.4 13 12 13.5 13 45 35 0.4 2.2 V High Output Voltage Rise Time Fall Time Undervoltage Lockout Section Start Threshold Minimum Operating Voltage (after tum ON) V 150 150 nS nS VTH(ST) VOPR(MIN) GM3842A, GM3844A GM3843A, GM3845A GM3842A, GM3844A GM3843A, GM3845A 14.5 7.8 8.5 7.0 16.0 8.4 10 7.6 17.5 9.0 11.5 8.2 V V GM3842A, GM3843A, GM3844A, GM3845A 5 V ELECTRICAL CHARACTERISTICS (Continued) (TA = 0°C to 70°C, *VCC=15V, CT=3.3nF, RT=10kW, unless otherwise specified ) CHARACTERISTICS PWM Section Maximum Duty Cycle Minimum Duty Cycle Total Standby Current Start-Up Current Operating Supply Current Zener Voltage IST ICC(OPR) VZ GM3842A/ 43A/ 44A/ 45A VPIN3= VPIN2=0V ICC= 25mA 30 0.17 13 38 0.3 17 mA mA V D(MAX) D(MIN) GM3842A, GM3843A GM3844A, GM3845A 95 47 97 48 100 50 0 % % % SYMBOL TEST CONDITIONS MIN TYP MAX UNIT * Adjust VCC above the Startup threshold before setting to 15 V. Note1: Parameter measured at trip point of latch with VPIN2 = 0. Note2: Gain defined as A=DVPIN1 / DVPIN3 ; 0 VPIN3 0.8V Note3: These parameters, although guaranteed, are not 100% tested in production GM3842A, GM3843A, GM3844A, GM3845A TYPICAL PERFORMANCE CHARACTERISTICS RT (KW) 50 CT= 1000pF CT= 200pF 20 10 CT= 2nF 5 CT= 5nF CT= 10pF 2 VCC= 15V 1 TA=25°C 10 20 30 50 100 200 300 500 CT= 1nF CT= 500pF % 50 30 20 10 VCC= 15V TA=25°C CT= 5nF CT= 10pF CT= 2nF CT= 1nF CT= 500pF CT= 200pF CT= 1000pF 5 3 2 1 fosc (kHz) 10 20 30 50 100 200 300 500 fosc (kHz) Figure 1. Timing Resistor vs. Oscillator Frequency Figure 2. Output Dead-Time vs. Oscillator Frequency 6 TYPICAL PERFORMANCE CHARACTERISTICS Dmax (%) 90 80 70 60 50 40 VCC= 15V CT= 3.3nF TA=25°C (dB) 80 60 40 20 0 -20 10 VCC= 15V VO= 2V to 4V RL= 100K TA= 25°C 1 2 3 5 RT (kW) 100 1k 10k 100k 1M f (Hz) Figure 3. Maximum Output Duty Cycle vs. Timing Resistor (GM3842A/43A) Figure 4. Error Amp Open-Loop Gain vs. Frequency Vth (V) VCC= 15V 1.0 0.8 0.6 0.4 0.2 TA= 125°C TA= 25°C ISC (mA) 100 90 80 70 60 VCC= 15V 0 2 4 6 VO (V) 50 0 25 50 75 Figure 5. Current Sense Input Threshold vs. Error Amp Output Voltage 100 T (°C) A Figure 6. Reference Short Circuit Current vs. Temperature Vsat (V) -1 -2 80µs Pulsed Load 120Hz Rate ICC (mA) ISense= 0V Sourse Saturation (Load to Ground) VFB= 0V RT= 10K TA= 25°C 20 C = 3.3nF T GM3843A/ 45A 15 10 Sink Saturation (Load to VCC) 5 0 200 400 600 IO (mA) 0 10 20 30 VCC(V) Figure 7. Output Saturation Voltage vs. Load Current TA= 25°C Figure 8. Supply Current vs. Supply Voltage VCC= 15V 3 2 1 0 0 GM3842A, GM3843A, GM3844A, GM3845A 7 GM3842A/ 44A OPERATING DESCRIPTION GM3842A, GM3843A, GM3844A and GM3845A are high performance with fixed frequency, current mode controllers. They are designed for off-ine and DC-to-DC converter applications offering great versatility with minimal external components. A representative block diagram is shown on page 4. Oscillator The oscillator frequency is determined by the values of the timing components RT and CT. Capacitor CT is charged from the 5.0 V reference through resistor RT to approximately 2.8 V and discharged to 1.2 V by an internal current sink. During the of CT, the oscillator generates an internal blanking pulse that holds the center input of the NOR gate high. This causes the output to be in a low state, thus producing a controlled amount of Figure 2 show RT versus oscillator frequency and Figure 2, Output deadtime versus frequency, both for given values of CT output deadtime. Note that different values of RT and CT will give the same oscillator frequency, but only one combination will yield a specific output deadtime at a given frequency. The oscillator thresholds are temperature compensated. These interned circuit vefinements minimizes refinements of oscillator frequency and maximum output duty cycle. In many noise sensitive applications, it may be desirable to frequency-lock the converter to an external system clock. This can be accmplished by applying a clock signal to the circuit shown in Figure 9. For best locking results, set the free-unning oscillator frequency to about 10% less than the clock frequency. A method for multi unit synchronization is shown in Figure 10. You can get very accurate output duty cycle clamping by tweaking the clock waveform. Error Amplifier GM384XA series has a fully compensated error amplifier with access to both the inverting input and output, and providing DC voltage gain of 90 dB (typical). The noninverting input is internally biased at 2.5 V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current is -2.0 µA, which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. The Error Amplifier Output (Pin 1) allows external loop compensation. The output voltage is offset by the two diode drops ( 1.4 V) and divided by three before it connects to the inverting input of the Current Sense Comparator. This assures that no drive pulses appear at the Output (Pin 6) when Pin 1 is at its lowest state (VOL). This happens when the power supply is operating and the load is removed, or at the beginning of a softstart interval (Figures 11, 12). The Error Amp minimum feedback resistance is limited by the amplifier's source current (0.5 mA) and the required output voltage (VOH) to reach the comparator's 1.0 V clamp level: Rf(min) 3.0(1.0V) + 1.4V = 8800W 0.5mA GM3842A, GM3843A, GM3844A, GM3845A Current Sense Comparator and PWM Latch GM384XA series operates as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the Error Amplifier Output/Compensation (Pin1). The error signal controls the peak inductor current cycle-by-cycle basis. The Current Sense Comparator PWM Latch configuration assures that only a single pulse appears at the Output during any given oscillator cycle. The inductor current is converted to a voltage by inserting the groundreferenced sense resistor RS in series with the source of output switch Q1. This voltage is monitored by the Current Sense Input (Pin 3) and compared to a level derived from the Error Amp Output. The peak inductor current under normal operating conditions is controlled by the voltage at pin 1 where: Ipk= V(PIN1) - 1.4V 3 RS When the power supply output is overloaded or if output voltage sensing is lost, the chip operation is not normal. In these situations, the Current Sense Comparator threshold will be internally clamped to 1.0 V and the maximum peak switch current is: 1.0V Ipk(mak)= R S 8 When designing a high power switching regulator, it becomes desirable to reduce the internal clamp voltage in order, to keep a reasonable level of power dissipation of RS. Adjusting the internal clamp voltage is very simple, as shown in Figure 11. The two external diodes compensate the internal diodes so you get a constant clamp voltage over temperature. Avoid too much reduction of the Ipk(max) clamp voltage, or you will get noise pickup and erratic results. A narrow spike on the leading edge of the current waveform often occurs and can cause the power supply instability when the output load is light. This spike is caused by power transformer interwinding capacitance and output rectifier recovery time. You can eliminate this problem by adding an RC filter on the Current Sense Input, with a time constant similar to the spike's duration; see Figure 16. Undervoltage Lockout Two UVLO comparators in GM384XA series assure that the chips are fully functional before the output stage is enabled. The positive power supply terminal (VCC) and the reference output (Vref) have separate comparators. Each has built-in hysteresis to prevent erratic output behavior as their thresholds are reached. The VCC comparator's upper and lower thresholds are 16 V/10 V for GM3842A and GM3844A, and 8.4V/7.6V for GM3843A and GM3845A. The Vref comparator's upper and lower thresholds are 3.6V/3.4 V. The large hysteresis and low startup current of the GM3842A and GM3844A makes them ideal for off-line converter applications where efficient bootstrap startup is required. GM3843A and GM3845A are intended for lower voltage DC-to-DC converter applications. A 36 V zener is connected as a shunt regulator from VCC to ground. Its purpose is to protect the IC from excessive voltage that can occur during system startup. The minimum operating voltage for GM3842A and GM3844A is 11V; for GM3843A and GM3845A it is 8.2V. GM384XA series has a single totem pole output stage that was designed for direct drive of power MOSFETs. It provides up to ±1.0 A peak drive current and has a typical rise/ fall time of 50 ns with a 1.0 nF load. Additional internal circuitry keeps the output in a sinking mode whenever a UVLO is active. This eliminates the need for an external pull-down resistor. Reference The 5.0 V bandgap reference is trimmed to ±1.0% tolerance at TJ = 25°C on the GM384XA series. Its primary purpose is to supply charging current to the oscillator timing capacitor. The reference has short circuit protection and it can provide more than 20mA for powering additional control system circuitry. Design Considerations Do not make your converter to use wire-wrap or plug-in prototype boards. High-frequency circuit layout techniques must be observed to prevent pulsewidth jitter. This is usually caused by excessive noise pick-up imposed on the Current Sense or Voltage Feedback inputs. You can improve noice immunity by lowering circuit impedances at these points. The PCB layout should have a ground plane with low-current signal and highcurrent switch and output grounds returning on separate paths to the input filter capacitor. Ceramic bypass capacitors (0.1 µF) connected directly to VCC, VC, and Vref may be required, depending upon circuit layout, to provide a low impedance path for filtering high frequency noise. All high-current loops should be as short as possible and use heavy copper runs to minimize radiated EMI. The Error Amp compensation circuitry and the converter output voltage divider should be placed as close as possible to the GM384XA, and as far as possible from the power switch and other noise- generating components. GM3842A, GM3843A, GM3844A, GM3845A 9 Output Current mode converters can exhibit subharmonic oscillations when operating at a duty cycle greater than 50% with continuous inductor current. This instability is independent of the regulators closed–loop characteristics and is caused by the simultaneous operating conditions of fixed frequency and peak current detecting. Figure 9.A shows the phenomenon graphically. At t0, switch conduction begins and causes causing the inductor current to rise at a slope of m1. This slope is a function of the input voltage divided by the inductance. At t1, the Current Sense Input reaches the threshold established by the control voltage. This causes the switch to turn off and the current to decay at a slope of m2 until the next oscillator cycle. The unstable condition can be shown if a pertubation is added to the control voltage, and resulting in a small DI (dashed line). With a fixed oscillator period, the current decay time is reduced and the minimum current at switch turn–on (t2) is increased by DI + DI m2/m1. The minimum current at next cycle (t3) decreases to (DI + DI m2/m1) (m2/m1). This pertubation is multiplied by m2.m1 on each succeeding cycle, alternately increasing and decreasing the inductor current at switch turn–on. Several oscillator cycles may be required before the inductor current reaches zero, which caused causing the process to commence again. If m2/m1 is greater than 1, the converter will be unstable. Figure 9.B shows that by adding an artificial ramp, that is synchronized with the PWM clock to the control voltage, the DI pertubation will decrease to zero on succeeding cycles. This compensation ramp (m3) must have a slope equal to or slightly greater than m2/2 for stability. With m2/2 slope compensation, the average inductor current follows the control voltage yielding true current mode operation. The compensating ramp can be DI A GM3842A, GM3843A, GM3844A, GM3845A Control Voltage m2 Inductor Current m1 DI + DI Oscillator Period t0 t1 t2 t3 m2 m1 (DI + DI m2 m2 )( ) m1 m1 Control Voltage B m3 DI m1 m2 Oscillator Period t4 t5 Figure 9. Continuous Current Waveforms t6 Inductor Current 10 Figure 10. External Clock Synchronization 8 Vref RT R 4 CT R Internal Bias Oscillartor External Sync Input 0.01 + 47 2 + Error Amplifier 2R 1 R * The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of CT to go more than 300 mV below ground. 5 Figure 11. External DUTY CYCLE CLAMP and multi-unit synchronization 8 R RA 8 4 3 RB 6 5 5.0k 2 C 5.0k 1 1 GND 5 5.0k 4 R Internal Bias Oscillator + + - R + Q + Error Amplifier 2R S 7 2 R To Additional GM384XA series f= 1.44 (RA + 2RB) C Dmax RB RA + 2RB GM3842A, GM3843A, GM3844A, GM3845A 11 Figure 12. Adjustable reduction of clamp level VCC VIN Vclamp= 1.67 R2 ( R1 + 1) +0.33X10-3 ( R1 + R2 ) R1 + R2 8 R 5.0 Vref Internal Bias + Oscillator VCC 7 IPK(max)= where: 0 Vclamp RS Vclamp 1.0V R2 + - + 7 R 4 + 6 Q1 + Vclamp + 2 Error Amplifier 1.0mA 2R + R 1.0V R1 5 RS S Q R 3 5 Comp/ Latch 1 GM3842A, GM3843A, GM3844A, GM3845A Figure 13. Soft-start circuit 8 R R 4 Internal Bias 5.0 Vref + Oscillator + - + S Q 2 + Error Amplifier 1.0mA 2R + R 1.0V 5 R 1 1.0M tsoft-start 3600C in µF C 12 Figure 14. Adjustable buffered reduction of clamp level with soft-start VCC VIN Vclamp= 1.67 R2 VCC 7 ( R1 + 1) Vclamp IPK(max)= RS where: 0 Vclamp 1.0V 8 R R 4 Internal Bias 5.0 Vref + - + - 7 VC tsoftstart= -ln [ 1] 3Vclamp C R1 + R2 R1 + R2 + Oscillator + 6 Q1 Vcalmp + 2 R2 1 Error Amplifier R 1.0V 5 1.0mA 2R + - S Q R Comp/ Latch 5 3 RS C R1 MPSA63 Figure 15. Current sensing power mosfet VCC VIN VPIN 5= RS IPK RDS(on) RDS(on) + RS 5.0 Vref VCC 7 If= SENSEFET= MTP10N10M RS= 200 Then : VPIN 5= 0.075 lPK + - + - + - 7 D SENSEFET S G M 5 K + 6 S + R For proper operation during over current conditions, a reduction of the Ipk(max) clamp level must be implemented. Refer to Figures 11 and 12. 1.0V 5 Q R Comp/ Latch Power Ground to Input Source Retum 3 1/4W Control Circuitry Ground RS GM3842A, GM3843A, GM3844A, GM3845A 13 Figure 16. current wavefrom spike suppression VCC VIN VCC 7 5.0 Vref + + 7 + - + Q1 8 TQ 5 Q S GM3842A, GM3843A, GM3844A, GM3845A + - R Comp/ Latch R 1.0V 3 R C 5 RS * The addition of the RC filter will eliminate instability caused by the leading edge spike on the current waveform. 14 Figure 17. MOSFET Parasitic Oscillations VCC 7 + + 7 6 5 S + R Q 3 Rs Rg Q1 VIN 5.0 VREF + + - Comp/ Latch Series gate resistor Rg will damp any high frequency parasitic oscillations caused by the MOSFET input capacitance and any series wiring inductance in the gate-source circuit. Figure 18. Isolated MOSFET Drive VO RI 2 CI RD RF 2.5V + EA 1 + 1.0mA 2R R 5 Error Amp compensation circuit for stabilizing any current-mode topology except for boost and flyback converters operating with continuous inductor current. GM3842A, GM3843A, GM3844A, GM3845A 15 Figure 19. Latched Shutdown 8 R Bias R 4 + + 1 EA 1.0mA 2R OSC 2 R MCR101 5 2N3905 2N3903 GM3842A, GM3843A, GM3844A, GM3845A The MCR101 SCR must be selected for a holding of less than 0.5 mA at TA (min). The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10 k. Figure Error Amplifier Compensation VO RP RI CI RF 2 2.5V + EA 1 + 1.0mA 2R R CP RD 5 Error Amp compensation circuit for stabilizing current-mode boost and flyback topologies operating with continuous inductor current. 16 SOP-8 PACKAGE OUTLINE DIMENSIONS 0° ~8° 0.0285 ± 0.0105 0.725 ± 0.275 P ad Layout 0.060 1.52 0.238 ± 0.008 6.04 ± 0.2 0.155 ± 0.004 3.94 ± 0.1 0.275 7.0 0.155 4.0 PIN INDENT 0.024 0.6 0.050 1.270 0.008 ± 0.002 0.203 ± 0.05 0.693 ± 0.504 4.91 ± 0.1 0.05 1.27 Inches ( mm ) 0.057 ± 0.004 1.45 ± 0.1 0.063 ± 0.006 1.60 ± 0.15 0.007 ± 0.003 0.175 ± 0.075 0.016 ± 0.004 0.406 ± 0.1 DIP-8 PACKAGE OUTLINE DIMENSIONS 0.252 ± 0.008 6.40 ± 0.2 0.3 ± 0.008 7.62 ± 0.2 0.362 ± 0.008 9.20 ± 0.2 0.012 ± 0.004 0.304 ± 0.1 0.3425 ± 0.0155 8.70 ± 0.4 0.134 ± 0.008 3.40 ± 0.2 0.158 ± 0.012 4.01 ± 0.3 0.02 MIN 0.51 MIN 0.13 ± 0.008 3.30 ± 0.2 0.018 ± 0.004 0.46 ± 0.10 0.1 ± 0.008 2.54 ± 0.2 0.06 ± 0.006 1.524 ± 0.15 Inches ( mm ) GM3842A, GM3843A, GM3844A, GM3845A 17 ORDERING NUMBER GM 3842 A S8 R Gamma Micro. Circuit Type Package S8: SOP-8 D8: DIP-8 Shipping R: Tape & Reel "A" Version GM3842A, GM3843A, GM3844A, GM3845A 18 19 GM3842A, GM3843A, GM3844A, GM3845A