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GL3523-OV3S1

GL3523-OV3S1

  • 厂商:

    GENESYS(创惟科技)

  • 封装:

    QFN88

  • 描述:

    GL3523-OV3S1

  • 数据手册
  • 价格&库存
GL3523-OV3S1 数据手册
Genesys Logic, Inc. GL3523 USB 3.1 Gen 1 Hub Controller Datasheet Revision 1.70 Mar. 02, 2017 GL3523 Datasheet Copyright Copyright © 2017 Genesys Logic, Inc. All rights reserved. No part of the materials shall be reproduced in any form or by any means without prior written consent of Genesys Logic, Inc. Ownership and Title Genesys Logic, Inc. owns and retains of its right, title and interest in and to all materials provided herein. Genesys Logic, Inc. reserves all rights, including, but not limited to, all patent rights, trademarks, copyrights and any other propriety rights. No license is granted hereunder. Disclaimer All Materials are provided “as is”. Genesys Logic, Inc. makes no warranties, express, implied or otherwise, regarding their accuracy, merchantability, fitness for any particular purpose, and non-infringement of intellectual property. In no event shall Genesys Logic, Inc. be liable for any damages, including, without limitation, any direct, indirect, consequential, or incidental damages. The materials may contain errors or omissions. Genesys Logic, Inc. may make changes to the materials or to the products described herein at anytime without notice. Genesys Logic, Inc. 12F., No. 205, Sec. 3, Beixin Rd., Xindian Dist. 231, New Taipei City, Taiwan Tel : (886-2) 8913-1888 Fax : (886-2) 6629-6168 http://www.genesyslogic.com © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 2 GL3523 Datasheet Revision History Revision Date Description 1.00 04/14/2015 Formal release 1.10 05/18/2015 Updated CH4.3.6 &4.3.7, p. 23 Updated CH6.5 On-Chip Power Regulator, p. 29, 30 1.20 06/03/2015 Add SMBus information 1.21 06/09/2015 Modify SMBUS information 1.22 07/29/2015 Update Power Consumption 1.23 09/09/2015 Update description of fast-charging 1.30 09/21/2015 Add GL3523-S and GL3523-Q information 1.40 11/11/2015 Update Section 4.4.6 Port Configuration and Chapter 8 Ordering Information 1.50 02/18/2016 Modify the description for CHIPEN pin 1.51 03/25/2016 Rename BGA as VFBGA 1.52 05/11/2016 Correct the pin description of OVCUR pins, p. 14 1.60 06/22/2016 Correct the pin description of V5, p. 15 1.61 06/28/2016 Update power consumption, p. 43 1.62 11/17/2016 Modify the pin description of OVCUR pins, p.14, 23, and 29 Add description for power consumption, p.43 1.63 03/02/2017 Correct the pin description Add V5_CC pin description, p. 25 1.70 03/02/2017 Update GL3523-S Pin-out diagram, P. 17~21 Remove GL3523-Q © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 3 GL3523 Datasheet Table of Contents CHAPTER 1 GENERAL DESCRIPTION ......................................................................... 8 CHAPTER 2 FEATURES .................................................................................................... 8 CHAPTER 3 PIN ASSIGNMENT..................................................................................... 11 3.1 GL3523 Pin-out Diagram............................................................................................ 11 3.2 GL3523 Pin Descriptions ............................................................................................ 14 3.3 GL3523-S Series Pin-out Diagram ............................................................................. 17 3.4 GL3523-S Pin Descriptions ......................................................................................... 22 CHAPTER 4 FUNCTION DESCRIPTION ..................................................................... 26 4.1 GL3523 Functional Block ........................................................................................... 26 4.2 GL3523-S Functional Block........................................................................................ 27 4.3 General Description..................................................................................................... 28 4.3.1 USB 2.0 USPORT Transceiver ........................................................................... 28 4.3.2 USB 3.1 Gen 1 USPORT Transceiver ................................................................ 28 4.3.3 PLL (Phase Lock Loop) ...................................................................................... 28 4.3.4 Regulator .............................................................................................................. 28 4.3.5 SPI Engine ............................................................................................................ 28 4.3.6 RAM/ROM/CPU.................................................................................................. 28 4.3.7 UTMI (USB 2.0 Transceiver Microcell Interface) ............................................ 28 4.3.8 SIE (Serial Interface Engine) .............................................................................. 28 4.3.9 Control/Status Register ....................................................................................... 28 4.3.10 Power Management Engine .............................................................................. 28 4.3.11 Router/Aggregator Engine................................................................................ 29 4.3.12 REPEATER ....................................................................................................... 29 4.3.13 TT ........................................................................................................................ 29 4.3.14 CDP Control Logic ............................................................................................ 30 4.3.15 USB 3.1 Gen 1/USB 2.0 DSPORT Transceiver ............................................... 30 4.4 Configuration and I/O Settings .................................................................................. 31 4.4.1 RESET Setting ..................................................................................................... 31 4.4.2 PGANG Setting .................................................................................................... 32 © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 4 GL3523 Datasheet 4.4.3 SELF/BUS Power Setting ................................................................................... 33 4.4.4 LED Connections ................................................................................................. 33 4.4.5 Power Switch Enable Polarity ............................................................................ 34 4.4.6 Port Configuration .............................................................................................. 34 4.4.7 Non-removable Port Setting ............................................................................... 34 4.4.8 SMBUS Mode (SMBUS Slave Address=0x25) .................................................. 34 CHAPTER 5 FAST CHARGING SUPPORT .................................................................. 35 5.1 Introduction to Battery Charging Specification Rev.1.2 ......................................... 35 5.2 Standard Downstream Port (SDP) ............................................................................. 35 5.3 Charging Downstream Port (CDP) ............................................................................ 35 5.4 Dedicated Charging Port (DCP) ................................................................................ 36 5.5 ACA-Dock .................................................................................................................... 36 5.6 Apple and Samsung Devices ....................................................................................... 36 5.7 Charging Downstream Port Configuration .............................................................. 36 CHAPTER 6 ELECTRICAL CHARACTERISTICS ..................................................... 37 6.1 Maximum Ratings ....................................................................................................... 37 6.2 Operating Ranges ........................................................................................................ 37 6.3 DC Characteristics ...................................................................................................... 38 6.3.1 DC Characteristics except USB Signals ............................................................. 38 6.3.2 USB 2.0 Interface DC Characteristics ............................................................... 38 6.3.3 USB 3.1 Gen 1 Interface DC Characteristics .................................................... 38 6.4 Power Consumption .................................................................................................... 39 6.5 On-Chip Power Regulator .......................................................................................... 40 6.5.1 5V to 3.3V Regulator ........................................................................................... 40 6.5.2 5V to 1.2V Regulator ........................................................................................... 41 6.6 External Clock ............................................................................................................. 41 CHAPTER 7 PACKAGE DIMENSION ........................................................................... 42 CHAPTER 8 ORDERING INFORMATION................................................................... 47 © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 5 GL3523 Datasheet List of Figures Figure 3.1 - GL3523 QFN 76 Pin-out Diagram ................................................................... 11 Figure 3.2 - GL3523 QFN 64 Pin-out Diagram ................................................................... 12 Figure 3.3 - GL3523 QFN 48 Pin-out Diagram ................................................................... 13 Figure 3.4 - GL3523-S VFBGA144 Ball Diagram (Bottom View) ..................................... 17 Figure 3.5 - GL3523-S QFN88 (2C3A) Pin-out Diagram ................................................... 18 Figure 3.6 - GL3523-S QFN88 (1C4A) Pin-out Diagram ................................................... 19 Figure 3.7 - GL3523-S QFN76 Pin-out Diagram ................................................................. 20 Figure 3.8 - GL3523-S QFN64 (1C2A) Pin-out Diagram ................................................... 21 Figure 4.1 – GL3523 Architecture Diagram ........................................................................ 26 Figure 4.2 – GL3523-S Architecture Diagram .................................................................... 27 Figure 4.3 - Operating in USB 1.1 Schemes ......................................................................... 29 Figure 4.4 - Operating in USB 2.0 Schemes ......................................................................... 30 Figure 4.5 - Power on Reset Diagram ................................................................................... 31 Figure 4.6 - Power on Sequence of GL3523 ......................................................................... 31 Figure 4.7 - Timing of PGANG Strapping ........................................................................... 32 Figure 4.8 - GANG Mode Setting ......................................................................................... 32 Figure 4.9 - SELF/BUS Power Setting ................................................................................. 33 Figure 4.10 - LED Connection .............................................................................................. 33 Figure 4.11 - SMBus Timing Diagram ................................................................................. 34 Figure 6.1 - Vin(V5) vs Vout(V33)* ...................................................................................... 40 Figure 6.2 - Vin (V5) vs. Vout (V1.2) .................................................................................... 41 Figure 7.1 - QFN76 Package.................................................................................................. 42 Figure 7.2 - QFN64 Package.................................................................................................. 43 Figure 7.3 - QFN48 Package.................................................................................................. 44 Figure 7.4 - VFBGA144 Package .......................................................................................... 45 Figure 7.5 - QFN88 Package.................................................................................................. 46 © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 6 GL3523 Datasheet List of Tables Table 4.1 - Configuration by Power Switch Type ............................................................... 34 Table 6.1 - Maximum Ratings ............................................................................................... 37 Table 6.2 - Operating Ranges ................................................................................................ 37 Table 6.3 - DC Characteristics except USB Signals ............................................................ 38 Table 8.1 - Ordering Information ......................................................................................... 47 © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 7 GL3523 Datasheet CHAPTER 1 GENERAL DESCRIPTION Genesys GL3523 is a 4-port, low-power, and configurable hub controller. It is compliant with the USB 3.1 specification. GL3523 integrates Genesys Logic self-developed USB 3.1 Gen 1 Super Speed transmitter/receiver physical layer (PHY) and USB 2.0 High-Speed PHY. It supports Super Speed, Hi-Speed, and Full-Speed USB connections and is fully backward compatible to all USB 2.0 and USB 1.1 hosts. GL3523 also implements multiple TT* (Note1) architecture providing dedicated TT* to each downstream (DS) port, which guarantees Full-Speed(FS) data passing bandwidth when multiple FS devices perform heavy loading operations. Furthermore, GL3523 has built-in 5V to 3.3V and 5V to 1.2V regulators, which saves customers’ BOM cost, and eases for PCB design. GL3523 features the native fast-charging and complies with USB-IF battery charging specification rev1.2, it could fast-charge Apple, Samsung Galaxy devices, and any device complaint with BC1.2/1.1. It also allows portable devices to draw up to 1.5A from GL3523 charging downstream ports (CDP 1) or dedicated charging port (DCP2). It can enable systems to fast charge handheld devices even during “Sleep” and “Power-off” modes. With different part numbers, GL3523 also has USB Type-C function integrated (GL3523-S). All available packages for GL3523 are listed as the following tables. Product Series GL3523 GL3523-S (USB-C Integrated) Package Type Number of DFPs Power Mgmt. LED Support QFN 76 4 Individual/ Gang Green/Amber QFN 64 4 Individual/ Gang N/A QFN 48 2 Individual/ Gang N/A VFBGA144 (5C) 4 Individual/ Gang Green/Amber QFN88 (2C3A) 4 Individual/ Gang Amber QFN88 (1C4A) 4 Individual/ Gang Green/Amber QFN76 (3C) 2 Individual/ Gang N/A QFN64 (1C2A) 2 Individual/ Gang Green/Amber GL3523 Total Packages *Note: TT (transaction translator) implements the control logic defined in Section 11.14 ~ 11.22 of USB specification revision 2.0. TT basically handles the unbalanced traffic speed between the USPORT (operating in HS) and DSPORTS (operating in FS/LS) of hub. CHAPTER 2  1 2 FEATURES Compliant with USB 3.1 Gen 1 Specification CDP, charging downstream port, the Battery Charging Rev.1.2-compliant USB port that does data communication and charges device up to 1.5A. DCP, dedicated charging port, the Battery Charging Rev.1.2-compliant USB port that only charges devices up to 1.5A, similar to wall chargers. © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 8 GL3523 Datasheet -         Upstream port supports SuperSpeed (SS), HighSpeed (HS) and FullSpeed (FS) traffic Downstream ports support SS, HS, FS, and LowSpeed (LS) traffic 1 control pipe and 1 interrupt pipe Backward compatible to USB specification Revision 2.0/1.1 Native USB Type-C support in GL3523-S series - Compliant with USB Type-C Cable and Connection Specification Revision 1.0 - Featuring USB Type-C functions - Detecting flip-able/reversible plugging - Discovering/configuring VBUS - Supporting USB Type-C Current modes , including USB Default, 1.5A@5V, 3A@5V - Configuring/Supporting VCONN Power Featuring fast-charging on all downstream ports and upstream port - Compliant with USB Battery Charging Revision v1.2, supporting CDP, DCP, and ACA-Dock - Downstream ports can be turned from a Standard Downstream Port (SDP) into Charging Downstream Port (CDP) or Dedicated Charging Port (DCP) - Downstream devices can be charged while upstream VBUS is not present, which can be applied on wall charger applications - Upstream port is capable of charging and data communicating simultaneously for portable devices supporting ACA-Dock or proprietary charging protocols - Supporting Apple 1A/2.1A/2.4A and Samsung Galaxy devices fast-charging On-chip 8-bit micro-processor - RISC-like architecture - USB optimized instruction set - 1 cycle instruction execution (maximum) - Performance: 12 MIPS @ 12.5MHz (maximum) - With 256-byte RAM, 20K-byte internal ROM, and 24K-byte SRAM Multiple Transaction Translator (TT) architecture - Providing dedicated TT control logics for each downstream port - Superior performance when multiple FS devices operate concurrently Integrated USB transceiver - Improving output drivers with slew-rate control for EMI reduction - Internal power-fail detection for ESD recovery Advanced power management and low power consumption - Supporting USB 3.1 U0/U1/U2/U3 power management states - Supporting USB Link Power Management (LPM) L0/L1/L2 - Supporting individual/gang mode over-current detection for all downstream ports - Supporting both low/high-enabled power switches - Patented Smart Power Management Configurable settings by firmware in SPI flash - Configurable charging port - Configurable 4/3/2 downstream ports, downstream port can be disabled/enabled by each specific port for USB3.1/USB2.0 - Configurable Upstream and Downstream Ports in GL3523-S - Supporting multiple upstream ports in GL3253-S OV3S1 and OV5S1 packages - Supporting full in-system programming firmware upgrade by SPI-flash and configuration by EEPROM - Supporting compound-device (non-removable setting on downstream ports) - Supporting customization VID/PID Flexible design - Supporting Poly-fuse/Power-switch - Automatic switching between self-powered and bus-powered modes - Supporting electrical tuning for each specific port © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 9 GL3523 Datasheet -    Supporting programmable breathing LED Supporting register setting by firmware Supporting vendor command and SMBUS Allow downstream ports to connect up to 8 devices, 4 x USB3.1 non-removable devices with 4 x USB2.0 non-removable devices or exposed ports Low BOM cost - Single external 25 MHz crystal / Oscillator clock input - Built-in upstream port 1.5KΩ pull-up and downstream port 15KΩ pull-down resistors - Built-in 5 to 3.3V and 5 to 1.2V regulator Different package types available for various applications Applications - Standalone USB hub/Docking station - Tablet/Ultrabook/NB - Motherboard - Monitor built-in hub, GPIOs can be programmed as I2C interface to easily update scalar firmware through USB interface - TV built-in hub - Compound device, such as hub-reader application - USB wall charger - Other consumer electronics - Customized applications  Dynamically disable/enable ports  GPIO signaling of ambient light sensor or rotation/position sensor © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 10 GL3523 Datasheet CHAPTER 3 PIN ASSIGNMENT 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 X1 X2 DVDD33 VBUS PGANG P_SPI_CZ P_SPI_DI P_SPI_CK P_SPI_DO RESETJ DVDD12 RTERM CHIPEN V33 V5 VDDP SW VSSP FB 3.1 GL3523 Pin-out Diagram GL3523 QFN - 76 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 OVCUR1J PWREN1J PWREN2J OVCUR2J OVCUR3J/SMC PWREN3J PWREN4J OVCUR4J/SMD PAMBER_P2 PGREEN_P2 DVDD12 AVDD33_3 DM_P2 DP_P2 RXP1_P2 RXN1_P2 VP12_P2 TXP1_P2 TXN1_P2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 PAMBER_P4 PGREEN_P3 PAMBER_P3 AVDD12 TXN1_P4 TXP1_P4 VP12_P4 RXN1_P4 RXP1_P4 DP_P4 DM_P4 AVDD33_2 DP_P3 DM_P3 TXN1_P3 TXP1_P3 VP12_P3 RXN1_P3 RXP1_P3 TXN1_P1 TXP1_P1 VP12_P1 RXN1_P1 RXP1_P1 DP_P1 DM_P1 AVDD33_1 DP_P0 DM_P0 TXN1_P0 TXP1_P0 VP12_P0 RXN1_P0 RXP1_P0 AVDD33 PGREEN_P1 PAMBER_P1 PGREEN_P4 Figure 3.1 - GL3523 QFN 76 Pin-out Diagram © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 11 X1 X2 DVDD33 VBUS PGANG P_SPI_CZ P_SPI_DI P_SPI_CK P_SPI_DO RESETJ DVDD12 RTERM V33 V5 VDDP SW 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 GL3523 Datasheet TXN1_P1 49 32 VSSP TXP1_P1 50 31 FB VP12_P1 51 30 OVCUR1J RXN1_P1 52 29 PWREN1J RXP1_P1 53 28 OVCUR2J DP_P1 54 27 OVCUR3J/SMC DM_P1 55 26 OVCUR4J/SMD AVDD33_1 56 25 DVDD12 DP_P0 57 24 AVDD33_3 DM_P0 58 23 DM_P2 TXN1_P0 59 22 DP_P2 TXP1_P0 60 21 20 RXP1_P2 19 VP12_P2 GL3523 RXN1_P2 VP12_P0 61 RXN1_P0 62 RXP1_P0 63 18 TXP1_P2 AVDD33 64 17 TXN1_P2 10 11 12 13 14 15 16 DP_P3 TXN1_P3 TXP1_P3 VP12_P3 RXN1_P3 RXP1_P3 9 AVDD33_2 DM_P3 8 DP_P4 DM_P4 6 RXP1_P4 7 5 VP12_P4 RXN1_P4 3 TXP1_P4 4 2 TXN1_P4 AVDD12 1 QFN - 64 Figure 3.2 - GL3523 QFN 64 Pin-out Diagram © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 12 36 35 34 33 32 31 30 29 28 27 26 25 VBUS PGANG P_SPI_CZ P_SPI_DI P_SPI_CK P_SPI_DO RESETJ DVDD12 RTERM V33 V5 VDDP GL3523 Datasheet GL3523 QFN - 48 1 2 3 4 5 6 7 8 9 10 11 12 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 SW VSSP FB PWREN2J OVCUR2J OVCUR3J PWREN3J AVDD33_3 DM_P2 DP_P2 RXP1_P2 RXN1_P2 AVDD12 AVDD33_2 DP_P3 DM_P3 TXN1_P3 TXP1_P3 VP12_P3 RXN1_P3 RXP1_P3 TXN1_P2 TXP1_P2 VP12_P2 DVDD33 X2 X1 AVDD33_1 DP_P0 DM_P0 TXN1_P0 TXP1_P0 VP12_P0 RXN1_P0 RXP1_P0 AVDD33 Figure 3.3 - GL3523 QFN 48 Pin-out Diagram © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 13 GL3523 Datasheet 3.2 GL3523 Pin Descriptions USB Interface Pin Name TXN1_P0 TXP1_P0 RXN1_P0 RXP1_P0 TXN1_P1 TXP1_P1 RXN1_P1 RXP1_P1 TXN1_P2 TXP1_P2 RXN1_P2 RXP1_P2 TXN1_P3 TXP1_P3 RXN1_P3 RXP1_P3 TXN1_P4 TXP1_P4 RXN1_P4 RXP1_P4 DM_P0 DP_P0 DM_P1 DP_P1 DM_P2 DP_P2 DM_P3 DP_P3 DM_P4 DP_P4 QFN 76 68 69 71 72 58 59 61 62 20 21 23 24 15 16 18 19 5 6 8 9 67 66 64 63 26 25 14 13 11 10 QFN 64 59 60 62 63 49 50 52 53 17 18 20 21 12 13 15 16 2 3 5 6 58 57 55 54 23 22 11 10 8 7 QFN 48 43 44 46 47 Type I O - I 10 11 13 14 5 6 8 9 USB3.1 Gen 1 Differential Data Transmitter TX-/TX+ of USPORT USB3.1 Gen 1 Differential Data Receiver RX-/RX+ of USPORT USB3.1 Gen 1 Differential Data Transmitter TX-/TX+ of DSPORT1 USB3.1 Gen 1 Differential Data Receiver RX-/RX+ of DSPORT1 USB3.1 Gen 1 Differential Data Transmitter TX-/TX+ of DSPORT2 USB3.1 Gen 1 Differential Data Receiver RX-/RX+ of DSPORT2 USB3.1 Gen 1 Differential Data Transmitter TX-/TX+ of DSPORT3 USB3.1 Gen 1 Differential Data Receiver RX-/RX+ of DSPORT3 USB3.1 Gen 1 Differential Data Transmitter TX-/TX+ of DSPORT4 USB3.1 Gen 1 Differential Data Receiver RX-/RX+ of DSPORT4 O - Description O I O I - O - I 42 41 B USB 2.0 DM/DP for USPORT - B USB 2.0 DM/DP for DSPORT1 B USB 2.0 DM/DP for DSPORT2 B USB 2.0 DM/DP for DSPORT3 B USB 2.0 DM/DP for DSPORT4 16 15 4 3 - Hub Interface QFN QFN 64 76 74,29, PGREEN1~4 2,76 75,30, PAMBER1~4 3,1 37,36, PWREN1~4J 29 33,32 38,35, 30,28, OVCUR1~4J 34,31 27,26 Pin Name QFN 48 Type - B Green LED indicator for DSPORT1~4 - B Amber LED indicator for DSPORT1~4 21 18 20 19 Description Active low. Power enable output for DSPORT1~4 PWREN1# is the only power-enable output for GANG mode. Active low. Over current indicator for DSPORT1~4 I (pd) The OVCUR pin of DFP1 will be the only over-current flag B © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 14 GL3523 Datasheet for GANG mode. *In reset state : OVCUR3J will be SMC, OVCUR4J will be SMD * SMBUS function is only available in QFN76 and QFN64 PGANG Default put in input mode after power-on reset. Individual/gang mode is strapped during this period. I 53 44 35 QFN 64 QFN 48 Type X1 QFN 76 57 48 39 I X2 56 47 38 O RESETJ 48 39 30 CHIPEN 45 - - Clock and Reset Interface Pin Name Description Crystal / OSC clock input Crystal clock output. Active low. External reset input, default pull high 10KΩ. I (pd) When RESET# = low, whole chip is reset to the initial state. 0: Disable whole chip and keep hub in lowest power state (standby mode) I (pu) 1: Normal state SPI Interface Pin Name QFN 76 QFN 64 QFN 48 Type P_SPI_CK 50 41 32 B For SPI data clock P_SPI_CZ 52 43 34 B For SPI data chip enable P_SPI_DO 49 40 31 B For SPI data Input P_SPI_DI 51 42 33 B For SPI data Output Description Power/Ground Interface Pin Name VP12_P0~P4 QFN QFN QFN Type Description 64 48 76 70,60,22, 61,51, 45,12,7 P Analog 1.2V power input for Analog circuit 17,7 19,14,4 AVDD12 4 1 1 P Analog 1.2V power input for Analog PLL circuit DVDD12 28,47 25,38 29 P 1.2V digital power input for digital circuits DVDD33 55 46 37 P 3.3V digital power input for digital circuits AVDD33 AVDD33_1 AVDD33_2 AVDD33_3 73 65 12 27 64 56 9 24 48 40 2 17 P Analog 3.3V power input VBUS 54 45 36 I VBUS detection pin for valid VBUS V33 44 36 27 P V5 43 35 26 P 5V-to-3.3V regulator Vout & 3.3 input 5V Power input. It should be connected to V33 if using external 3.3V regulator © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 15 GL3523 Datasheet Switching Regulator (5V to 1.2V) Pin Name QFN 76 QFN 64 QFN 48 Type Description FB 39 31 22 A Switcher Feedback Voltage. This pin is the inverting input of the error amplifier. VOUT senses the switcher output through an external resistor divider network. For the fixed voltage version, connect this pin to the output voltage. SW 41 33 24 A Internal Switches Output. Connect this pin to the output inductor. VDDP 42 34 25 P Dedicated 5V power input for embedded switching regulator VSSP 40 32 23 P Dedicated Ground for embedded switching regulator Miscellaneous Interface Name QFN 76 QFN 64 QFN 48 Type Description RTERM 46 37 28 A A 20Kohm resister must be connected between RTERM and Ground Note: Analog circuits are quite sensitive to power and ground noise, so please take care the power routing and the ground plane for PCB design. For detailed information, please refer to USB3.1 Hub Design Guide. Notation: Type O I B P A pu pd Output Input Bi-directional Power / Ground Analog Internal pull up Internal pull down © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 16 GL3523 Datasheet 3.3 GL3523-S Series Pin-out Diagram Figure 3.4 - GL3523-S VFBGA144 Ball Diagram (Bottom View) © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 17 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 X1 X2 DVDD33 VBUS PGANG P_SPI_CZ P_SPI_DI P_SPI_CK P_SPI_DO RESETJ DVDD12 V5_CC CC1_P1 CC2_P1 CC1_P2 CC2_P2 V5_CC RTERM CHIPEN V33 V5 VDDP GL3523 Datasheet GL3523-S QFN - 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 SW VSSP FB OVCUR1J PWREN1J PWREN2J OVCUR2J OVCUR3J PWREN3J/SMC PWREN4J OVCUR4J/SMD PAMBER_P2 DVDD12 AVDD33_3 DM_P2 DP_P2 TXN2_P2 TXP2_P2 VP12_P2 RXP2_P2 RXN2_P2 RXP1_P2 PAMBER_P4 PAMBER_P3 AVDD12 TXN1_P4 TXP1_P4 VP12_P4 RXN1_P4 RXP1_P4 DP_P4 DM_P4 AVDD33_2 DP_P3 DM_P3 TXN1_P3 TXP1_P3 VP12_P3 RXN1_P3 RXP1_P3 TXN1_P2 TXP1_P2 VP12_P2 RXN1_P2 TXN1_P1 TXP1_P1 VP12_P1 RXN1_P1 RXP1_P1 RXN2_P1 RXP2_P1 VP12_P1 TXP2_P1 TXN2_P1 DP_P1 DM_P1 AVDD33_1 DP_P0 DM_P0 TXN1_P0 TXP1_P0 VP12_P0 RXN1_P0 RXP1_P0 AVDD33 PAMBER_P1 Figure 3.5 - GL3523-S QFN88 (2C3A) Pin-out Diagram © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 18 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 X1 X2 DVDD33 VBUS PGANG P_SPI_CZ P_SPI_DI P_SPI_CK P_SPI_DO RESETJ DVDD12 CC1_P4 CC2_P4 V5_CC RTERM CHIPEN V33 V5 VDDP SW VSSP FB GL3523 Datasheet GL3523-S QFN - 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 PSELF OVCUR1J PWREN1J PWREN2J OVCUR2J OVCUR3J PWREN3J PWREN4J OVCUR4J PAMBER_P2 PGREEN_P2 DVDD12 AVDD33_3 DM_P2 DP_P2 RXP1_P2 RXN1_P2 VP12_P2 TXP1_P2 TXN1_P2 RXP1_P3 RXN1_P3 PAMBER_P4 PGREEN_P3 PAMBER_P3 AVDD12 TXN1_P4 TXP1_P4 VP12_P4 RXN1_P4 RXP1_P4 RXN2_P4 RXP2_P4 VP12_P4 TXP2_P4 TXN2_P4 DP_P4 DM_P4 AVDD33_2 DP_P3 DM_P3 TXN1_P3 TXP1_P3 VP12_P3 TXN1_P1 TXP1_P1 VP12_P1 RXN1_P1 RXP1_P1 DP_P1 DM_P1 AVDD33_1 DP_P0 DM_P0 TXN1_P0 TXP1_P0 VP12_P0 RXN1_P0 RXP1_P0 AVDD33 PGREEN_P1 PAMBER_P1 PGREEN_P4 NC NC NC Figure 3.6 - GL3523-S QFN88 (1C4A) Pin-out Diagram © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 19 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 PGANG P_SPI_CZ P_SPI_DI P_SPI_CK P_SPI_DO RESETJ DVDD12 CC1_P0 CC2_P0 V5_CC CC1_P2 CC2_P2 CC1_P3 CC2_P3 RTERM CHIPEN V33 V5 VDDP GL3523 Datasheet GL3523-S QFN - 76 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 SW VSSP NC FB PWREN2J OVCUR2J OVCUR3J PWREN3J DVDD12 AVDD33_3 DM_P2 DP_P2 TXN2_P2 TXP2_P2 VP12_P2 RXP2_P2 RXN2_P2 RXP1_P2 RXN1_P2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 AVDD12 AVDD33_2 DP_P3 DM_P3 TXN1_P3 TXP1_P3 VP12_P3 RXN1_P3 RXP1_P3 RXN2_P3 RXP2_P3 VP12_P3 TXP2_P3 TXN2_P3 NC NC TXN1_P2 TXP1_P2 VP12_P2 VBUS DVDD33 X2 X1 VP12 AVDD33_1 DP_P0 DM_P0 TXN1_P0 TXP1_P0 VP12_P0 RXN1_P0 RXP1_P0 RXN2_P0 RXP2_P0 VP12_P0 TXP2_P0 TXN2_P0 AVDD33 Figure 3.7 - GL3523-S QFN76 Pin-out Diagram © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 20 PGANG P_SPI_CZ P_SPI_DI P_SPI_CK P_SPI_DO RESETJ DVDD12 CC1_P4 CC2_P4 V5_CC RTERM CHIPEN V33 V5 VDDP SW 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 GL3523 Datasheet VBUS 49 32 VSSP DVDD33 50 31 FB X2 51 30 PWREN2J X1 52 29 OVCUR2J NC 53 28 PWREN4J VP12_P1 54 27 OVCUR4J AVDD33_1 55 26 PAMBER_P2 DP_P0 56 25 PGREEN_P2 DM_P0 57 24 DVDD12 TXN1_P0 58 23 AVDD33_3 TXP1_P0 59 22 DM_P2 VP12_P0 60 DP_P2 RXN1_P0 61 21 20 RXP1_P0 62 19 RXN1_P2 AVDD33 63 18 VP12_P2 PGREEN_P4 64 17 TXP1_P2 GL3523-S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PAMBER_P4 AVDD12 TXN1_P4 TXP1_P4 VP12_4 RXN1_P4 RXP1_P4 RXN2_P4 RXP2_P4 VP12_P4 TXP2_P4 TXN2_P4 DP_P4 DM_P4 AVDD33_2 TXN1_P2 QFN - 64 RXP1_P2 Figure 3.8 - GL3523-S QFN64 (1C2A) Pin-out Diagram © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 21 GL3523 Datasheet 3.4 GL3523-S Pin Descriptions USB Interface Name TXN1_P0 TXP1_P0 TXN2_P0 TXP2_P0 RXN1_P0 RXP1_P0 RXN2_P0 RXP2_P0 TXN1_P1 TXP1_P1 TXN2_P1 TXP2_P1 RXN1_P1 RXP1_P1 RXN2_P1 RXP2_P1 TXN1_P2 TXP1_P2 TXN2_P2 TXP2_P2 RXN1_P2 RXP1_P2 RXN2_P2 RXP2_P2 TXN1_P3 TXP1_P3 TXN2_P3 TXP2_P3 RXN1_P3 RXP1_P3 RXN2_P3 RXP2_P3 TXN1_P4 TXP1_P4 TXN2_P4 TXP2_P4 RXN1_P4 RXP1_P4 RXN2_P4 RXP2_P4 DM_P0 DP_P0 DM_P1 DP_P1 VFBGA QFN88 144 (2C3A) A6 82 B6 83 B2 A2 A5 85 B5 86 B3 A3 A11 67 B11 68 B7 76 A7 75 A10 70 B10 71 B8 72 A8 73 M3 19 L3 20 L7 28 M7 27 M4 22 L4 23 L6 24 M6 25 H1 14 H2 15 M2 M1 J1 17 J2 18 L2 L1 C1 4 C2 5 G2 G1 D1 7 D2 8 F2 F1 A4 81 B4 80 A9 78 B9 77 QFN88 QFN76 QFN64 Type Description (1C4A) 77 66 58 USB 3.1 Gen 1 Differential Data Transmitter O TX-/TX+ of USPORT 78 67 59 75 USB 3.1 Gen 1 Differential Data Transmitter O TX-/TX+ of USPORT for Type-C 74 80 69 61 USB 3.1 Gen 1 Differential Data Receiver I RX-/RX+ of USPORT 81 70 62 71 USB 3.1 Gen 1 Differential Data Receiver I RX-/RX+ of USPORT for Type-C 72 67 USB 3.1 Gen 1 Differential Data Transmitter O TX-/TX+ of DSPORT1 68 USB 3.1 Gen 1 Differential Data Transmitter O TX-/TX+ of DSPORT1 for Type-C 70 USB 3.1 Gen 1 Differential Data Receiver I RX-/RX+ of DSPORT1 71 USB 3.1 Gen 1 Differential Data Receiver I RX-/RX+ of DSPORT1 for Type-C 25 17 16 USB 3.1 Gen 1 Differential Data Transmitter O TX-/TX+ of DSPORT2 26 18 17 26 USB 3.1 Gen 1 Differential Data Transmitter O TX-/TX+ of DSPORT2 for Type-C 25 28 20 19 USB 3.1 Gen 1 Differential Data Receiver I RX-/RX+ of DSPORT2 29 21 20 22 USB 3.1 Gen 1 Differential Data Receiver I RX-/RX+ of DSPORT2 for Type-C 23 20 5 USB 3.1 Gen 1 Differential Data Transmitter O TX-/TX+ of DSPORT3 21 6 14 USB 3.1 Gen 1 Differential Data Transmitter O TX-/TX+ of DSPORT3 for Type-C 13 23 8 USB 3.1 Gen 1 Differential Data Receiver I RX-/RX+ of DSPORT3 24 9 10 USB 3.1 Gen 1 Differential Data Receiver I RX-/RX+ of DSPORT3 for Type-C 11 5 3 USB 3.1 Gen 1 Differential Data Transmitter O TX-/TX+ of DSPORT4 6 4 14 12 USB 3.1 Gen 1 Differential Data Transmitter O TX-/TX+ of DSPORT4 for Type-C 13 11 8 6 USB 3.1 Gen 1 Differential Data Receiver I RX-/RX+ of DSPORT4 9 7 10 8 USB 3.1 Gen 1 Differential Data Receiver I RX-/RX+ of DSPORT4 for Type-C 11 9 76 65 57 B USB 2.0 DM/DP for USPORT 75 64 56 73 B USB 2.0 DM/DP for DSPORT1 72 © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 22 GL3523 Datasheet DM_P2 DP_P2 DM_P3 DP_P3 DM_P4 DP_P4 M5 L5 K1 K2 E1 E2 30 29 13 12 10 9 31 30 19 18 16 15 28 27 4 3 - 22 21 B USB 2.0 DM/DP for DSPORT2 - B USB 2.0 DM/DP for DSPORT3 14 13 B USB 2.0 DM/DP for DSPORT4 Type-C Interface Name CC1_P0 CC2_P0 CC1_P1 CC2_P1 CC1_P2 CC2_P2 CC1_P3 CC2_P3 CC1_P4 CC2_P4 VFBGA QFN88 QFN88 QFN76 QFN64 Type Description 144 (2C3A) (1C4A) E11 50 I/O Configuration Channel for USPORT D12 49 F11 54 I/O Configuration Channel for DSPORT1 E12 53 F10 52 47 I/O Configuration Channel for DSPORT2 E10 51 46 G9 45 I/O Configuration Channel for DSPORT3 F9 44 H10 55 41 I/O Configuration Channel for DSPORT4 G10 54 40 Hub Interface VFBGA QFN88 QFN88 QFN76 QFN64 Type Description 144 (2C3A) (1C4A) PGREEN E3,L8, 83,34,2,8 25, 64 B Green LED indicator for DSPORT1~4 _P1~4 5 G4,F3 PAMBER D3,M8,G 88,33, 84,35,3,1 26, 1 B Amber LED indicator for DSPORT1~4 _P1~4 3,F4 2,1 Active low. Power enable output for 30 DSPORT1~4 PWREN1 L10,L9, 40,39, 42,41,38, 34,31 B ~4J K7,K6 37 36,35 28 PWREN1# is the only power-enable output for GANG mode. Active low. Over current indicator for DSPORT1~4 The OVCUR pin of DFP1 will be the only 29 over-current flag for GANG mode. OVCUR1 M10,M9, 41,38, 43,40,39, 33,32 I (pd) ~4J K8,J6 36 37,34 27  In reset state : OVCUR3J will be SMC, OVCUR4J will be SMD  SMBUS function is only available in VFBGA144 and QFN88 Default put in input mode after power-on reset. PGANG D11 62 62 57 48 I Individual/gang mode is strapped during this period. 0: Hub is bus-powered. PSELF J9 44 I 1: Hub is self-powered. Name © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 23 GL3523 Datasheet Clock and Reset Interface Name X1 VFBGA QFN88 QFN88 QFN76 QFN64 Type Description 144 (2C3A) (1C4A) A12 66 66 61 52 I Crystal / OSC clock input X2 B12 65 65 60 51 RESETJ C11 57 57 52 43 CHIPEN H12 48 51 42 37 O Crystal clock output. Active low. External reset input, default pull high 500KΩ. I When RESET# = low, whole chip is reset to the initial state. 0: Disable whole chip and keep hub in lowest I (pu) power state (standby mode) 1: Normal state SPI Interface Name VFBGA QFN88 QFN88 QFN76 QFN64 Type 144 (2C3A) (1C4A) Description P_SPI_CK G12 59 59 54 45 B For SPI data clock P_SPI_CZ F12 61 61 56 47 B For SPI data chip enable P_SPI_DO H11 58 58 53 44 B For SPI data Input P_SPI_DI G11 60 60 55 46 B For SPI data Output Power/Ground Interface Name VFBGA 144 QFN88 QFN88 QFN76 QFN64 Type (2C3A) (1C4A) C5,C4,D4,C 84,74,69, 79,69,7, 62,73,6 60, 9,C10K4,K5, VP12_P0~4 26,21, 27,22,1 8,24,19, 54,18 J3,K3 2 7,12 10,5 A1,B1 16,6 Description P Analog 1.2V power input for Analog circuit AVDD12 C3 3 4 1 2 P Analog 1.2V power input for Analog PLL circuit DVDD12 K9,D10 32,56 33,56 30,51 24,42 P 1.2V digital power input for digital circuits DVDD33 D9 64 64 59 50 P 3.3V digital power input for digital circuits AVDD33 AVDD33_1 AVDD33_2 AVDD33_3 D6, C8,D8, H4,J4, J5,J7 C6,C7,D5,D 7,E4~9, F5~8, G5~8, H3, H5~9, J8 87 79 11 31 82 32 76,63,2, 29 63 55 15 23 P Analog 3.3V power input - - - - P Digital/Analog ground VBUS C12 63 63 58 49 I VBUS detection pin for valid input V33 J11 47 50 41 36 P 5V-to-3.3V regulator Vout & 3.3 input V5 - 46 49 40 35 P 5V Power input. It should be connected to V33 if using external 3.3V regulator GND © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 24 GL3523 Datasheet V5_CC J12 50,55 53 48 39 P 5V Power input of CC. It has to be supplied with 5V to make CC functioning. Switching Regulator (5V to 1.2V) Name VFBGA 144 QFN88 (2C3A) QFN88 (1C4A) QFN 76 QFN64 Type FB K10 42 45 35 31 A SW L12, M12 44 47 38 33 A VDDP K11,K12 45 48 39 34 P VSSP L11, M11 43 46 37 32 P Description Feedback sense, output 1.2V Internal switches output. Connect this pin to the output inductor Dedicated 5V power input for embedded switching regulator Dedicated Ground for embedded switching regulator Miscellaneous Interface Name VFBGA QFN88 QFN88 QFN76 QFN64 Type 144 (2C3A) (1C4A) RTERM J10 49 NC - - 52 43 86,87,8 15,16, 8 36 Description 38 A A 20Kohm resister must be connected between RTERM and Ground 53 -- Not Connect Note: Analog circuits are quite sensitive to power and ground noise. PCB layout must take care the power routing and the ground plane. For detailed information, please refer to USB 3.1 Hub Design Guide. Notation: Type O I B P A pu pd Output Input Bi-directional Power / Ground Analog Internal pull up Internal pull down © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 25 GL3523 Datasheet CHAPTER 4 FUNCTION DESCRIPTION 4.1 GL3523 Functional Block 1.2V 25MHz 5V 3.3V SPI Flash Upstream Port PLL 5V→1.2V Regulator DM & DP SS RX USB 2.0 USPORT Transceiver SS TX 5V→3.3V Regulator SPI Engine USB 3.1 USPORT Transceiver RAM ROM Control / Status Register UTMI / SIE CPU Repeater TT TT TT Power Management Engine Router / Aggregator Engine Control / Status Register TT CDP Control Logic CDP Control Logic CDP Control Logic CDP Control Logic USB 2.0 DSPORT transceiver USB 2.0 DSPORT transceiver USB 2.0 DSPORT transceiver USB 2.0 DSPORT transceiver USB 3.1 DSPORT Transceiver Power Control Logic USB 3.1 DSPORT Transceiver USB 3.1 DSPORT Transceiver USB 3.1 DSPORTT Transceiver SS TX & RX SS TX & RX SS TX & RX SS TX & RX DM & DP DM & DP DM & DP Downstream Port 1 DM & DP Downstream Port 2 Downstream Port 3 Downstream Port 4 Figure 4.1 – GL3523 Architecture Diagram © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 26 GL3523 Datasheet 4.2 GL3523-S Functional Block 1.2V 25MHz 5V 3.3V SPI Flash Upstream Port DM & DP PLL 5V→1.2V Regulator SS RX CC Controller 5V→3.3V Regulator SPI Engine SS TX USB 2.0 USPORT Transceiver USB 3.1 USPORT Transceiver RAM ROM Control / Status Register UTMI / SIE Power Management Engine CPU Repeater TT TT TT Router / Aggregator Engine Control / Status Register TT CDP Control Logic CDP Control Logic CDP Control Logic CDP Control Logic USB 2.0 DSPORT transceiver USB 2.0 DSPORT transceiver USB 2.0 DSPORT transceiver USB 2.0 DSPORT transceiver USB 3.1 DSPORT Transceiver Power Control Logic USB 3.1 DSPORT Transceiver USB 3.1 DSPORT Transceiver USB 3.1 DSPORTT Transceiver SS TX & RX DM & DP SS TX & RX SS TX & RX SS TX & RX DM & DP DM & DP CC Controller Downstream Port 1 DM & DP CC Controller CC Controller Downstream Port 2 Downstream Port 3 CC Controller Downstream Port 4 Figure 4.2 – GL3523-S Architecture Diagram © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 27 GL3523 Datasheet 4.3 General Description 4.3.1 USB 2.0 USPORT Transceiver USB 2.0 USPORT (upstream port) transceiver is the analog circuit that supports both full-speed and high-speed electrical characteristics defined in Chapter 7 of USB specification revision 2.0. USPORT transceiver will operate in full-speed electrical signaling when GL3523 is plugged into a 1.1 host/hub. USPORT transceiver will operate in high-speed electrical signaling when GL3523 is plugged into a 2.0 host/hub. 4.3.2 USB 3.1 Gen 1 USPORT Transceiver USB3.1 Gen 1 USPORT (upstream port) transceiver is the analog circuit that has elastic buffer and supports receiver detection, data serialization and de-serialization. Besides, it has PIPE interface with SuperSpeed Link Layer 4.3.3 PLL (Phase Lock Loop) PLL generates the clock sources for the whole chip. The generated clocks are proven quite accurate that help in generating high speed signal without jitter. 4.3.4 Regulator GL3523 build in internal regulators convert 5V input to 3.3V/1.2V output. 4.3.5 SPI Engine SPI engine is to move code from external flash to the internal RAM. 4.3.6 RAM/ROM/CPU The micro-processor unit of GL3523 is an 8-bit RISC processor with 20K-byte ROM and 256-bytes RAM. It operates at 12MIPS of 12 MHz clock( maximum) to decode the USB command issued from host and then prepares the data to respond to the host. 4.3.7 UTMI (USB 2.0 Transceiver Microcell Interface) UTMI handles the low level USB protocol and signaling. It’s designed based on the Intel’s UTMI specification 1.01. The major functions of UTMI logic are to handle the data and clock recovery, NRZI encoding/decoding, Bit stuffing /de-stuffing, supporting USB 2.0 test modes, and serial/parallel conversion. 4.3.8 SIE (Serial Interface Engine) SIE handles the USB protocol defined in Chapter 8 of USB specification revision 2.0. It co-works with μ C to play the role of the hub kernel. The main functions of SIE include the state machine of USB protocol flow, CRC check, PID error check, and timeout check. Unlike USB 1.1, bit stuffing/de-stuffing is implemented in UTMI, not in SIE. 4.3.9 Control/Status Register Control/Status register is the interface register between hardware and firmware. This register contains the information necessary to control endpoint0 and endpoint1 pipelines. Through the firmware based architecture, GL3523 possesses higher flexibility to control the USB protocol easily and correctly. 4.3.10 Power Management Engine The power management of GL3523 is compliant with USB3.1 Gen 1 specification. When operating in SuperSpeed mode, GL3523 supports U0, U1, U2, and U3 power states. U0 is the functional state. U1 and U2 are lower power states compared to U0. U1 is a low power state with fast exit to U0; U2 is a low power state which saves more power than U1 with slower exit to U0. U3 is suspend state, which is the most power-saving state, with tens of milliseconds exit to U0. Unlike USB 2.0, SuperSpeed packet traffic is © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 28 GL3523 Datasheet unicast rather than broadcast. Packet only travels the direct path in-between host and the target device. SuperSpeed traffic will not reach an unrelated device. When enabled for U1/U2 entry, and there is no pending traffic within comparable exit latency, GL3523 will initiate U1/U2 entry to save the power. On the other hand, the link partner of GL3523 may also initiate U1/U2 entry. In this case, GL3523 will accept or reject low power state entry according to its internal condition. 4.3.11 Router/Aggregator Engine Router/Aggregator Engine implements the control logic defined in Chapter10 of USB 3.1 specification. Router/Aggregator Engine uses smart method for route packet to device or aggregate packet to host. 4.3.12 REPEATER Repeater logic implements the control logic defined in Section 11.4 and Section 11.7 of USB specification revision 2.0. REPEATER controls the traffic flow when upstream port and downstream port are signaling in the same speed. In addition, REPEATER will generate internal resume signal whenever a wakeup event is issued under the situation that hub is globally suspended. 4.3.13 TT TT (Transaction Translator) implements the control logic defined in Section 11.14 ~ 11.22 of USB specification revision 2.0. TT basically handles the unbalanced traffic speed between the USPORT (operating in HS) and DSPORTS (operating in FS/LS) of hub. GL3523 adopts multiple TT architecture to provide the most performance effective solution. Multiple TT provides control logics for each downstream port respectively. 4.3.13.1 Connected to 1.1 Host/Hub If an USB 2.0 hub is connected to the downstream port of an USB 1.1 host/hub, it will operate in USB 1.1 mode. For an USB 1.1 hub, both upstream direction traffic and downstream direction traffic are passing through REPEATER. That is, the REPEATER/TT routing logic will route the traffic channel to the REPEATER. USB 1.1 Host/Hub USPORToperating in FS signaling Traffic channel is routed to REPEATER TT REPEATER TT DSPORT operating in FS/LS signaling Figure 4.3 - Operating in USB 1.1 Schemes © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 29 GL3523 Datasheet 4.3.13.2 Connected to USB 2.0 Host/Hub If an USB 2.0 hub is connected to an USB 2.0 host/hub, it will operate in USB 2.0 mode. The upstream port signaling is in high speed with bandwidth of 480 Mbps under this environment. The traffic channel will then be routed to the REPEATER when the device connected to the downstream port is signaling also in high speed. On the other hand, the traffic channel will then be routed to TT when the device connected to the downstream port is signaling in full/low speed. USB 2.0 Host/Hub USPORToperating in HS signaling HS vs. HS: Traffic channel is routed to REPEATER REPEATER TT HS vs. FS/LS: Traffic channel is routed to TT TT DSPORT operating in FS/LS signaling DSPORT operating in HS signaling Figure 4.4 - Operating in USB 2.0 Schemes 4.3.14 CDP Control Logic CDP (charging downstream port) control logic implements the logic defined in USB Battery charging specification revision 1.2. The major function of it is to control DSPORT Transceiver to make handshake with a portable device which is compliant with USB Battery charging spec rev1.2 as well. After recognizing charging detection each other, portable device will draw up to 1.5A from VBUS to fast charge its battery. 4.3.15 USB 3.1 Gen 1/USB 2.0 DSPORT Transceiver DSPORT transceiver is the analog circuit that supports high-speed, full-speed, and low-speed electrical characteristics. In addition, each DSPORT transceiver accurately controls its own squelch level to detect the detachment and attachment of devices. © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 30 GL3523 Datasheet 4.4 Configuration and I/O Settings 4.4.1 RESET Setting GL3523’s power on reset can either be triggered by external reset or internal power good reset circuit. The external reset pin, RESETJ, is connected to upstream port Vbus (5V) to sense the USB plug / unplug or 5V voltage drop. The reset trigger voltage can be set by adjusting the value of resistor R1 and R2 (Suggested value refers to schematics) GL3523’s internal reset is designed to monitor silicon’s internal core power (1.2V) and initiate reset when unstable power event occurs. The power on sequence will start after the power good voltage has been met, and the reset will be released after approximately 40 μS after power good. GL3523’s reset circuit as depicted in the picture. Silicon PCB Ext. VBUS power-good detection circuit input (Pin"RESET#") VBUS (External 5V) R1 R2 Global Reset# EXT INT Int. 3.3V power-good detection circuit input (USB PHY reset) Pin “VBUS” Figure 4.5 - Power on Reset Diagram To fully control the reset process of GL3523, we suggest the reset time applied in the external reset circuit should longer than that of the internal reset circuit. Timing of POR is illustrated as below figure. Power good voltage, 2.5V~2.8V (3.3V) 0.861V (1.2V) VCC(3.3V) (1.2V) ≒ 40 μs Internal reset External reset Figure 4.6 - Power on Sequence of GL3523 © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 31 GL3523 Datasheet 4.4.2 PGANG Setting To save pin count, GL3523 uses the same pin to decide individual/gang mode as well as to output the suspend flag. The individual/gang mode is decided within 21us after power on reset. Then, about 50ms later, this pin is changed to output mode. GL3523 outputs the suspend flag once it is globally suspended. For individual mode, a pull low resister greater than 100KΩ should be placed. For gang mode, a greater than 100KΩ pull high resister should be placed. In figure 4.7, we also depict the suspend LED indicator schematics. It should be noticed that the polarity of LED must be followed, otherwise the suspend current will be over spec limitation (2.5mA). RESET# 50 ms GANG_CTL Output mode, indicating Input mode, strapping to decide individual or gang mode GL3523 is in normal mode or suspend mode Figure 4.7 - Timing of PGANG Strapping GAND Mode DVDD(3.3V) DVDD(3.3V) 100K ohm "0": Individual Mode "1": GANG Mode Suspend LED Indicator SUSPNDO GANG_CTL 100K ohm Inside GL3523 Suspend LED Indicator On PCB Individual Mode Figure 4.8 - GANG Mode Setting © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 32 GL3523 Datasheet 4.4.3 SELF/BUS Power Setting By setting PSELF, GL3523 can be configured as a bus-power or a self-power hub. 1: Self Power PSELF 0: Bus Power Inside GL3523 On PCB Figure 4.9 - SELF/BUS Power Setting 4.4.4 LED Connections GL3523 controls the LED lighting according to the flow defined in Section 11.5.3 of Universal Serial Bus Specification Revision2.0. Both manual mode and Automatic mode are supported in GL3523. When GL3523 is globally suspended, GL3523 will turn off the LED to save power. AMBER/GREEN LED DGND Inside GL3523 On PCB Figure 4.10 - LED Connection © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 33 GL3523 Datasheet 4.4.5 Power Switch Enable Polarity Both low/high-enabled power switches are supported. It is determined by jumper setting. The power switch polarity will be configured by the state of pin AMBER2, as the following table: Table 4.1 - Configuration by Power Switch Type AMBER2 Power Switch Enable Polarity 0 Low-active 1 High-active Note: When AMBER2=1, the external resistor of PWREN1~4 need pull down 4.4.6 Port Configuration Each specific downstream port can be disabled individually by firmware, SMBus or vendor command, which extends the flexibility for PCB design and fits more applications. In GL3523-S series of Hub, multiple upstream ports are also allowed for special applications. For further usage information, please contact Genesys FAE or sales team. 4.4.7 Non-removable Port Setting For compound applications or embedded systems, downstream ports that always connect inside the system can be set as non-removable by firmware configuration, EEPROM, and pin strapping. Please refer to Genesys USB3.1 Hub FW ISP Tool User Guide for the detailed setting information. 4.4.8 SMBUS Mode (SMBUS Slave Address=0x25) GL3523 enters SMBUS mode since Power-On occurs, and RESET# pin is asserted as well. After that, GL3523 will define OVCUR3J as SMC and OVCUR4J as SMD. GL3523 will exit the SMBUS mode since the RESET# pin is de-asserted. The more complicated settings such as PID, VID, power saving, port number, port non/removable, and downstream port electrical tuning can be configured by SMBUS. Figure 4.11 - SMBus Timing Diagram © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 34 GL3523 Datasheet CHAPTER 5 FAST CHARGING SUPPORT 5.1 Introduction to Battery Charging Specification Rev.1.2 The USB ports on personal computers are convenient places for portable devices to draw current for charging their batteries. This convenience has led to the creation of dedicated chargers that simply expose a USB standard-A receptacle. This allows portable devices to use the same USB cable to charge from either a PC or from a dedicated charger. If a portable device is attached to a USB host or hub, then the USB 2.0 specification requires that after connecting, a portable device must draw less than:  2.5 mA average if the bus is suspended  100 mA maximum if bus is not suspended and not configured  500 mA maximum if bus is not suspended and configured for 500 mA If a portable device is attached to a charging host or hub, it is allowed to draw a current up to 1.5A, regardless of suspend. In order for a portable device to determine how much current it is allowed to draw from an upstream USB port, the USB-IF Battery Charging specification defines the mechanisms that allow the portable device to distinguish between a USB standard host, hub or a USB charging host. Since portable devices can be attached to USB charging ports from various manufactures, it is important that all USB charging ports behave the same way. This specification also defines the requirements for a USB chargers and charging downstream ports. 5.2 Standard Downstream Port (SDP) GL3523 complies with Battery Charging Specification rev1.2, which defines three charging ports: SDP, CDP and DCP. The SDP is a standard USB port which can transfer data and provide maximum 500mA current. 5.3 Charging Downstream Port (CDP) GL3523 supports battery charging detection, turning its downstream port from a standard downstream port (SDP) into charging downstream port (CDP). GL3523 will make physical layer handshaking when a portable device that complies with BC rev1.2 attaches to its downstream port. After physical layer handshaking, a portable device is allowed to draw more current up to 1.5A. Once the charging downstream port of GL3523 is enabled, it will monitor the VDP_SRC on D+ line anytime. When a portable device, which is compliant with BC rev1.2, is attached to the downstream port, it will drive VDP_SRC on D+ line to initiate the handshake with charging downstream port. GL3523 will response on its Dline by VDM_SRC and keep in a certain period of time and voltage level. The portable device will accept this handshaking on its D- line in correct timing period and voltage level, and then turns off its VDP_SRC on D+ line. GL3523 will recognize that charging negotiation is finished by counting time between the portable device turning on and off its VDP_SRC. After that, the portable device can start to draw more current from VBUS to charge its battery more rapidly. It can draw current up to 1.5A. If there is no response from D- line, the portable device will recognize that it is attached to a standard downstream port, not a charging port. © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 35 GL3523 Datasheet 5.4 Dedicated Charging Port (DCP) GL3523 also supports dedicated charging port, which is a downstream port on a device that outputs power through a USB connector, but it is not capable of enumerating a downstream device. With the adequate system circuit design, GL3523 will turn its downstream port from a standard downstream port (SDP) into dedicated charging port (DCP), i.e short the D+ line to the D- line, to let the portable device draws current up to 1.5A. Please refer to the USB3.1 Hub Design Guide document for the detailed information. 5.5 ACA-Dock An ACA-Dock is a docking station that has one upstream port, and zero or more downstream ports. The upstream port can be attached to a portable device (PD), and is capable of sourcing ICDP to the PD, which means that the upstream port can charge and have data communication with the PD at the same time. Please refer to Battery Charging Spec v1.2 for more details. 5.6 Apple and Samsung Devices GL3523 Hub not only supports BC1.2, but also supports fast-charging for Apple 1A/2.4A and Samsung Galaxy devices. 5.7 Charging Downstream Port Configuration Fast-charging capability can be disabled/enabled by each specific downstream port. Please refer to the Genesys USB3.1 Hub FW ISP Tool User Guide document for the detailed setting information. © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 36 GL3523 Datasheet CHAPTER 6 ELECTRICAL CHARACTERISTICS 6.1 Maximum Ratings Table 6.1 - Maximum Ratings Symbol Parameter Min. Max. Unit V5 5V Power Supply -0.5 +6.0 V VDD 3.3V Power Supply -0.5 +3.6 V VDDcore 1.2VPower Supply -0.5 +1.32 V VIN 3.3V Input Voltage for digital I/O(EE_DO) pins* -0.5 +5 V Vincore 1.2V -0.5 +1.32 V VINUSB Input Voltage for USB signal (DP, DM) pins -0.5 +3.6 V TS Storage Temperature under bias -60 +100 o FOSC Frequency C 25 MHz  0.03% *Please refer to the reference design schematic. 6.2 Operating Ranges Table 6.2 - Operating Ranges Symbol Parameter Min. Typ. Max. Unit V5 5V Power Supply 4.75 5.0 5.25 V VDD 3.3V Power Supply 3.0 3.3 3.6 V VDDcore 1.2V Power Supply 1.15 1.2 1.32 V VIND Input Voltage for digital I/O pins -0.5 3.3 3.6 V VINUSB Input Voltage for USB signal (DP, DM) pins 0.5 3.3 3.6 V 70 o 125 o TA TJ Ambient Temperature Absolute maximum junction temperature © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential 0 0 - C C Page 37 GL3523 Datasheet 6.3 DC Characteristics 6.3.1 DC Characteristics except USB Signals Table 6.3 - DC Characteristics except USB Signals Symbol Parameter Min. Typ. Max. Unit VDD Power Supply Voltage 3 3.3 3.6 V VIL LOW level input voltage - - 1 V VIH HIGH level input voltage 1.4 - - V VTLH Schmitt trigger PAD*-LOW to HIGH threshold voltage 1.7 - - V VTHL Schmitt trigger PAD*- HIGH to LOW threshold voltage - - 0.7 V VOL LOW level output voltage when IOL=8mA - - 0.4 V VOH 2.4 - - V - - 30 A RDN HIGH level output voltage when IOH=8mA Leakage current for pads with internal pull up or pull down resistor Pad internal pull down resister 232 378 647 KΩ RUP Pad internal pull up resister 276 435 718 KΩ IOLK * Schmitt trigger pads are VBUS, RESET 6.3.2 USB 2.0 Interface DC Characteristics GL3523 conforms to DC characteristics for Universal Serial Bus specification rev. 2.0. Please refer to the specification for more information. 6.3.3 USB 3.1 Gen 1 Interface DC Characteristics GL3523 conforms to DC characteristics for Universal Serial Bus 3.1 specification. Please refer to the specification for more information. © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 38 GL3523 Datasheet 6.4 Power Consumption GL3523 integrates 5V-to-3.3V and 5V-to-1.2V regulators. If supplying 5V power, internal regulators convert 5V to 3.3V and 1.2 V, and power consumed in 5V domain in the following table already includes 1.2V and 3.V power consumption and conversion loss. In other words, if using 5V as input power, 1.2V and 3.3V power can be ignored; if using external 1.2V and 3.3V power as input sources, the total power consumption will be the sum of 1.2V and 3.3V. Using 5V power input Number of Active USB 3.1 Ports Using 1.2V and 3.3V power input 5V 1.2V Read/ Write Config. 3.3V Read/ Write Config. Unit Read/ Write Config. Reset (standby) 6 1.9 2 mW Suspend 12.5 5 3.3 mW 0 140 - 16 - 79 - mW 1 442 444 285 286 80 80 mW 2 563 564 389 391 80 80 mW 3 688 691 494 496 80 80 mW 4 821 825 599 600 80 80 mW Using 5V power input Number of Active USB 2.0 Ports Using 1.2V and 3.3V power input 5V 1.2V Read/ Write Config. 3.3V Read/ Write Config. Unit Read/ Write Config. Reset 6 1.9 2 mW Suspend 12.5 5 3.3 mW 0 140 - 16 - 79 - mW 1 171 212 16 16 98 125 mW 2 201 273 16 16 117 164 mW 3 231 310 16 16 138 188 mW 4 261 342 16 16 158 210 mW Note: Test result represents silicon level operating current without considering additional power consumption contributed by external over-current protection circuit. The power consumption could be different depending on configurations. © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 39 GL3523 Datasheet 6.5 On-Chip Power Regulator GL3523 requires 3.3V and 1.2V source power for normal operation of internal core logic and USB physical layer (PHY). There are two kinds of regulators integrated in GL3523; one is low-drop power regulator converts 5V power input from USB cable (Vbus) to 3.3V voltage for silicon power source; another one is DC-DC switching regulator converts 5V to 1.2 V. The 3.3V and 1.2V power output are guaranteed by internal voltage reference circuits to prevent unstable 5V power compromise USB data integrity. The regulators’ maximum currents loading are 250mA (5-3.3V) and 0.8A (5-1.2V), which provide enough tolerance for normal GL3523 operation (below 100mA). 6.5.1 5V to 3.3V Regulator 5V to 3.3V On-chip Power Regulator features are described as follows.     5V to 3.3V low-drop power regulator 250mA maximum output driving capability Provide stable 3.3V output when Vin = 4.5V~5.5V 125uA maximum quiescent current (typical 80uA). Vin (V5) vs Vout (V33)* 3.285 3.28 Vout (V) 3.275 3.27 3.265 3.26 3.255 3.25 3.245 4.5 4.7 4.9 5.1 5.3 5.5 Vin (V) *Note: Measured environment: Ambient temperature = 25℃, Current Loading = 250mA Figure 6.1 - Vin(V5) vs Vout(V33)* © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 40 GL3523 Datasheet 6.5.2 5V to 1.2V Regulator 5V to 1.2V DC-DC Switching Regulator features are described as follows.   5V to 1.2V DC-DC switching regulator 0.8A maximum output driving capability 5V to 1.2V DC-DC Transfer Efficiency 90.0% 80.0% efficiency(%) 70.0% 60.0% 50.0% 40.0% 30.0% 20.0% 10.0% 0.0% 0 200 400 600 800 Iout (mA) Figure 6.2 - Vin (V5) vs. Vout (V1.2) 6.6 External Clock XOUT: XIN: 25MHz crystal oscillator output. It should be left open if an external clock source is used. 25MHz crystal oscillator input. If an external 3.3V clock source is used, its frequency has to be 25MHz +/-300ppm with a peak-to-peak jitter less than 50ps.. © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 41 GL3523 Datasheet CHAPTER 7 PACKAGE DIMENSION GL3523 AAAAAAAAAA YWWXXXXXXXX Date Code Lot Code Figure 7.1 - QFN76 Package © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 42 GL3523 Datasheet GL3523 AAAAAAAAAA YWWXXXXXXXX Date Code Lot Code Figure 7.2 - QFN64 Package © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 43 GL3523 Datasheet GL3523 AAAAAAAA AA YWW XXXXXXXX Date Code Lot Code Figure 7.3 - QFN48 Package © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 44 GL3523 Datasheet GL3523 AAAAAAAAAA YWWXXXXXXXX Date Code Lot Code Figure 7.4 - VFBGA144 Package © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 45 GL3523 Datasheet GL3523 AAAAAAAAAA YWWXXXXXXXX Date Code Lot Code Figure 7.5 - QFN88 Package © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 46 GL3523 Datasheet CHAPTER 8 ORDERING INFORMATION Table 8.1 - Ordering Information Part Number Package Material Version Status GL3523-OTY10 QFN 76 Green Package 10 Available GL3523-OSY10 QFN 64 Green Package 10 Available GL3523-ONY10 QFN 48 Green Package 10 Available GL3523-VBYS1 VFBGA144 Green Package S1 Available GL3523-OV3S1 QFN88 (2C3A) Green Package S1 Available GL3523-OV5S1 QFN88 (1C4A) Green Package S1 Available GL3523-OTYS1 QFN76 Green Package S1 Available GL3523-OSYS1 QFN64 Green Package S1 Available © 2017 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 47
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