GL423

Genesys Logic, Inc. GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution Datasheet Revision 1.00 Aug. 16, 2006 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution Copyright: Copyright © 2006 Genesys Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic Inc.. Disclaimer: ALL MATERIALS ARE PROVIDED “AS IS” WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY, INCLUDING, WITHOUT LIMITATION, THE X-D PICTURE CARDTM LICENSE. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE. Trademarks: is a registered trademark of Genesys Logic, Inc. All trademarks are the properties of their respective owners. Office: Genesys Logic, Inc. 12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel: (886-2) 8913-1888 Fax: (886-2) 6629-6168 http ://www.genesyslogic.com ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 2 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution Revision History Revision 0.95 Date 09/02/2005 First formal release 1.Modify Block Diagram,Ch1 2.Add “56-Pin QFN Package” 3.Add “USB CONTROLLER STRUCTURE”,Ch3 10/18/2005 4.Add QFN-56 Package Diagram,Ch4.2 5.Modify “PAD/PIN Descruption”,Ch4.6 6.Add “D.C.Characteristics”, Ch5.3 08/16/2006 1. Remove 54-Pin LGA Package 2. Add 54-Pin VFBGA Package Description 0.96 1.00 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 3 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution TABLE OF CONTENTS CHAPTER 1 GENERAL DESCRIPTION................................................. 7 1.1 USB INTERFACE...................................................................................... 8 1.2 CARD INTERFACE .................................................................................. 8 1.3 FLASH ACCESS INTERFACE ..................................................................... 8 1.4 CONTROL LOGIC..................................................................................... 8 1.5 EMBEDDED CPU ..................................................................................... 8 CHAPTER 2 FEATURES ........................................................................... 9 2.1 USB 2.0 INTERFACE ................................................................................ 9 2.2 SD HOST INTERFACE .............................................................................. 9 2.3 MMC HOST INTERFACE ......................................................................... 9 2.4 FLASH MEMORY INTERFACE ................................................................ 10 2.5 MICRO CONTROLLER AND ANALOG SYSTEM........................................ 10 2.6 PRODUCT PACKAGES ............................................................................ 10 2.7 TECHNOLOGY ....................................................................................... 10 2.8 MANUFACTURE ..................................................................................... 10 CHAPTER 3 PIN ASSIGNMENT ............................................................ 11 3.1 FUNCTION DESCRIPTION ....................................................................... 11 3.1.1 USB specification compliance ...................................................... 11 3.1.2 Integrated USB building blocks................................................... 11 3.1.3 Embedded 8051 micro-controller ................................................ 11 3.1.4 3.3V power source ........................................................................ 11 3.1.5 Memory Stick TM interface......................................................... 11 3.1.6 Secure Digital (SD) and Multi Media Card (MMC)................... 11 3.1.7 High efficient hardware engine.................................................... 12 3.1.8 Inter-Media transfer capability ................................................... 12 3.2 BLOCK DIAGRAM................................................................................... 12 3.2.1 UTM .............................................................................................. 12 3.2.2 SIE................................................................................................. 12 3.2.3 EPFIFO......................................................................................... 13 3.2.4 MHE.............................................................................................. 13 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 4 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution CHAPTER 4 COMBO STRUCTURE ...................................................... 14 4.1 DIE DIAGRAM........................................................................................ 14 4.2 DIE TO QFN -56 PACKAGE DIAGRAM ................................................... 15 4.3 QFN -56 PACKAGE TOP VIEW .............................................................. 16 4.4 DIE TO VFBGA -54 PACKAGE DIAGRAM.............................................. 17 4.5 VFBGA -54 PACKAGE TOP VIEW......................................................... 18 4.6 PAD/PIN DESCRIPTON ......................................................................... 19 4.6.1 USB Interface ............................................................................... 19 4.6.2 Regulator Interface ...................................................................... 21 4.6.3 Card Interface .............................................................................. 22 4.6.4 Flash Interface .............................................................................. 24 4.6.5 System Interface ........................................................................... 25 4.6.6 Test Interface ................................................................................ 26 4.6.7 Use Flash Interface as USB Test Interface.................................. 27 4.6.8 Use Card Interface as USB Test Interface .................................. 28 CHAPTER 5 ELECTRICAL CHARACTERISTICS.............................. 29 5.1 ABSOLUTE MAXIMUM RATINGS ............................................................ 29 5.2 BUS OPERATING CONDITIONS ............................................................... 29 5.3 D.C. CHARACTERISTICS........................................................................ 29 CHAPTER 6 PACKAGE DIMENSION................................................... 31 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 5 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution LIST OF FIGURES FIGURE 1.1 - GL422/GL423 BLOCK DIAGRAM ................................................................7 FIGURE 3.1 - USB CONTROLLER DIAGRAM ....................................................................12 FIGURE 4.1 - GL422/GL423 DIE DIAGRAM ...................................................................14 FIGURE 4.2 - GL422/GL423 DIE TO QFN-56 PACKAGE DIAGRAM................................15 FIGURE 4.3 - GL422/GL423 QFN 56 PACKAGE TOP VIEW ...........................................16 FIGURE 4.4 - GL422/GL423 VFBGA54 PACKAGE DIAGRAM .......................................17 FIGURE 4.5 - GL422/GL423 VFBGA 54 PACKAGE TOP VIEW ......................................18 FIGURE 6.1 – GL422/GL423 56 PIN QFN PACKAGE......................................................31 FIGURE 6.2 – GL422/GL423 54 PIN VFBGA PACKAGE ................................................32 LIST OF TABLES TABLE 4.1- USB INTERFACE ..........................................................................................19 TABLE 4.2 – REGULATOR INTERFACE ............................................................................21 TABLE 4.3 – CARD INTERFAC .........................................................................................22 TABLE 4.4 – FLASH INTERFACE .....................................................................................24 TABLE 4.5 – SYSTEM INTERFACE ...................................................................................25 TABLE 4.6 – TEST INTERFACE ........................................................................................26 TABLE 4.7 –USE FLASH INTERFACE AS USB TEST INTERFACE ......................................27 TABLE 4.8 – USE CARD INTERFACE AS USB TEST INTERFACE.......................................28 TABLE 5.1 – ABSOLUTE MAXIMUM RATINGS .................................................................29 TABLE 5.2 – BUS OPERATING CONDITIONS ....................................................................29 TABLE 5.3 – D.C. CHARACTERISTICS.............................................................................29 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 6 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution CHAPTER 1 GENERAL DESCRIPTION Genesys Logic’s GL422/GL423 controller is an single-chip controllers support both USB2.0 and MMC4.0/SD1.1 specifications. While USB controller and SD/MMC card controller are integrated as a combo-function single chip, this chip provides an enhanced combo solution of USB2.0 and SD/MMC card. GL422/GL423 is designed based on USB2.0 and MMC4.0/SD1.1 specification. Its unique RAM based firmware strategy provides flexibility for fast compatibility and performance improvement, therefore, give customers strong support to win in today’s fast-changing market. GL422/GL423 manages interface protocol, data storage and retrieval, error detection and correction, defect handling and diagnostic, as well as power management. With a built-in flash management algorithm, GL422/GL423 is applicable for most types of flash in the market: SAMSUNG, MICRON, ST, TOSHIBA, HYNIX and RENESAS. GL422/GL423 is packaged QFN-56 and VFBGA-54. Both die and QFN/VFBGA package are available and completely meet SD and MMC memory card mechanical thickness requirement. The pin assignment that fits to card sockets provides easy PCB layout. GL422/GL423 die has a dual channel flash access interface, which remarkably speed up read/write performance. QFN-56 packaged GL422/GL423 supports SD1.1 only. VFBGA-54 packaged GL422/GL423 supports both SD1.1 and MMC4.0. Figure 1.1 is the block diagram of VFBGA422/GL423. USB Interface USB PHY USB Controller Flash Access IF Flash1 Interface Control Logic CARD Controller CARD Interface Flash2 Interface GL422/GL423 Figure 1.1 - GL422/GL423 Block Diagram ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 7 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 1.1 USB Interface The USB controller, complied with USB2.0 and USB1.1 specification, explains commands from USB host and transfers data as a USB application. 1.2 CARD Interface The card controller, complied with SD1.1/MMC4.0 specification, explains commands from SD/MMC host and transfers data between SD/MMC host and flash. 1.3 Flash Access Interface The flash access interface communicates with CPU. It also manages two channels of flash, based on flash commands. Moreover, it implements defect processing, ECC, and address mapping, etc. 1.4 Control Logic The control logic module switches the command and data between the USB host and SD/MMC host. By this module, the chip operates in different mode. 1.5 Embedded CPU Embedded CPU performs arithmetic and logical operations. In addition, it extracts instruction from ROM and SRAM, decodes and executes them. It also manages control and status signals between flash access interface and itself. ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 8 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution CHAPTER 2 FEATURES 2.1 USB 2.0 Interface • Complies with Universal Serial Bus Specification Version 2.0 • Complies with USB Mass Storage Class Specification Version 1.0 • Integrated USB 2.0 Transceiver Macro-cell (UTM), Serial Interface Engine (SIE), Build-in power-on reset (POR) and low-voltage detector (LVD) • Supports one USB device address and up to 5 endpoints, including one control, one interrupt and 2 bulk IN/OUT endpoint pairs • Embedded 8051 micro-controller operates at 60MHz clock • 64 / 512 bytes Data Payload for full / high speed Bulk Endpoint • Supports USB 2.0 TEST mode features 2.2 SD Host Interface • Complies with SD Specification Version 1.1 • Backward compatible with SD Specification, Version 1.0 • Supports SPI mode and CPRM functions • Supports clock rate up to 25 MHZ for SD1.0 • Supports clock rate up to 52MHz for SD1.1 • Buffers for multi-block flash memory programming • DMA operation between buffers and flash memory • Supports automatic CRC16 generation and verification on DATA 3-0 2.3 MMC Host Interface • Complies with MultiMediaCard System Specification, Version 4.0 • Backward compatible with MultiMediaCard System Specification, Version 3.3 • Supports SPI mode and CPRM functions • Supports clock rate up to 25 MHZ for MMC 3.3 • Supports clock rate up to 52MHz for MMC 4.0 • Buffers for multi-block flash memory programming • DMA operation between buffers and flash memory • Supports automatic CRC16 generation and verification on DATA 7-0 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 9 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 2.4 Flash Memory Interface • Direct interface to NAND/AND flash chips (SAMSUNG / TOSHIBA / HITACHI / RENESAS / MICRON / ST / HYNIX) • Direct interface to NOR/OR Flash chips (die only) • Supports dual-channel, 16 bits flash (die only) • Drives up to 4 flash memory chips, respectively (die only) • Supports 64 Mb / 128 Mb / 256 Mb / 512 Mb /1Gb / 2Gb / 4Gb / 8Gb flash chips • Embedded firmware support for flash file system (FTL) • Built-in flash management algorithm • Powerful ECC for error detection and correction up to 6 bytes per 512 bytes 2.5 Micro Controller and Analog System • RISC core with fast speed and less code size • Flexibility to update system code • Ability to add customers’ own feature 2.6 Product Packages • 56-pin QFN package • 54-pin VFBGA package 2.7 Technology • 0.18um process 2.8 Manufacture • Easy firmware development environment • Supports firmware upgrade tool via PC ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 10 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution CHAPTER 3 PIN ASSIGNMENT 3.1 Function description 3.1.1 USB specification compliance • Confirms to USB 480Mbps Specification, version 2.0. • Backward compatible with USB 12Mbps Specification, version 1.1. • Support one USB device address and up to 5 endpoints, including one control, one interrupt and 2 bulk IN / OUT endpoint pairs 3.1.2 Integrated USB building blocks • USB2.0 transceiver macro (UTM), Serial Interface Engine (SIE), Build-in power-on reset (POR) and low-voltage detector (LVD) 3.1.3 Embedded 8051 micro-controller • Operates at 60 MHz clock, 12 clocks per instruction cycle • Embedded 48K Byte mask ROM and internal 256 byte SRAM • Embedded 4K Byte external SRAM 3.1.4 3.3V power source 3.1.5 Memory Stick TM interface • Compliant with Memory Stick interface specification • Hardware support BS/SDIO/SCLK signals • Support INS signal • Support automatic CRC16 generation and verification 3.1.6 Secure Digital (SD) and Multi Media Card (MMC) • Compliant with Secure Digital / MMC interface specification • Support both SD / MMC mode access CLK/CMD/DAT0/DAT1/DAT2/DAT3 • Command transmit and response receive can be enabled separately • Automatic CRC7 generation for command and CRC7 verification for response on CMD • Support automatic CRC16 generation and verification on DAT3-0 • In addition to full packet transaction, optional single byte / bit operation on both CMD and DAT line / lines • Process data in block or byte ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 11 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 3.1.7 High efficient hardware engine • Automatic data read / write with card by hardware engine • Easier firmware development • Media interface signals output low automatically when suspend 3.1.8 Inter-Media transfer capability • Support copy data between flash cards or within same flash card 3.2 Block diagram MHE EPFIFO MHE control MCFIFO (32B) MS MIF EP0 FIFO (64B) SIE EP3 FIFO (64B) BULK FIFO (512B*2) MSP MIF SD MIF Register SIE/ FIFO/ MHE control 8051 core SRAM 256B LUT Mask ROM (48KB) LUT 4KB UTM Figure 3.1 - USB Controller diagram 3.2.1 UTM USB2.0 Transceiver Macro 3.2.2 SIE Serial Interface Engine ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 12 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 3.2.3 EPFIFO Endpoint FIFO: it includes Control FIFO (FIFO0), interrupt FIFO (FIFO3), Bulk In/Out FIFO (BULKFIFO) 3.2.3.1 Control FIFO FIFO of control endpoint 0. It is 64-byte FIFO, and it is used for endpoint 0 data transfer. 3.2.3.2 Interrupt FIFO 64-byte-depth FIFO of endpoint 3 for status interrupt. 3.2.3.3 Bulk In/Out FIFO It can be in the TX mode or RX mode: • It contains ping-pong FIFO (512 bytes each bank) for transmit/receive data continuously. • It can be directly accessed by micro controller • Support SIE won’t transmit data filled before micro controller check data integrity complete. • It can be used to copy data block from source to destination in the same card or from one card to other card. 3.2.4 MHE It contains 3 MIF (Media Interface), control and MCFIFO 3.2.4.1 MIFs • SD / MMC MIF • Memory Stick MIF • Memory Stick-PRO MIF 3.2.4.2 MCFIFO 32-byte FIFO shared by Memory Stick, Memory Stick-PRO, SD/MMC MIF. • Memory Stick and Memory Stick-PRO MIF can use MCFIFO as command FIFO. • SD/MMC MIF use MCFIFO for command and response. ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 13 XI DP XO DM VDD GND GND RREF AVDD AVDD AVDD AVDD AGND AGND AGND AGND REXT1 REXT2 V18OUT CVDD18 99 98 97 96 95 94 93 92 91 90 89 88 87 CHAPTER 4 4.1 Die Diagram 121 DP CUTCELL DGND1 DGND2 AGND3 AGND1 AGND2 DVDD1 AVDD1 AVDD2 AVDD2 AVDD3 AVDD1 AVDD2 GND REXT1 REXT2 RREF OUT1 OUT2 OUT2 VIN DM XI VIN VIN VBUS XO AVSS1 AVSS2 AVSS2 PAD_SCLK PAD_SDATA PAD_A14 CVDD18 D igital P o w er R ing( 1.8V /3.3V /G N D ) PAD_A15 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 1 P A D _ A 11 P A D _ A 10 P A D _A 9 P A D _A 8 USB P A D _T7 P A D _T6 P A D _ P rt _ B P A D _A 5 P A D _A 4 P A D _A 3 P A D _A 2 P A D _A 1 P A D _A 0 V C C 33 P A D _r st _B P A D _r st _o P A D _O S C _E CGND PG ND P A D _W P _ B C V D D 18 P A D _W E _ B P A D _A L E P A D _C L E P A D _C E 1 _B P A D _C E 0 _B P A D _R E _ B P A D _B U S Y _B P A D _D A 7 P A D _D A 6 P A D _A 2 3 P A D _A 6 P A D _A 7 P A D _A 1 3 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 P A D _ A 12 2 REGULATOR 3 4 5 T7 6 T6 7 8 U S B _A C T V C C 33 P A D _M C LK P A D _O S C O P A D _U D A TA 2 P A D _H D A TA 2 P A D _U D A TA 3 P A D _H D A TA 3 P A D _U D A TA 4 P A D _H D A TA 4 P A D _U C M D P A D _H C M D x P A D _H C M D y P A D _U D A TA 5 P A D _H D A TA 5 PG ND CGND P A D _U C LK P A D _H C LK V C C 33 P A D _U D A TA 0 P A D _H D A TA 0 9 P A D _U S B _A C TV V C C 33 10 M C LK 11 ©2000-2006 Genesys Logic Inc. - All rights reserved. V C C 33 R s t_ O S C _E GND W P_ C V D D 18 W E_ A LE C LE C E 1_ C E 0_ RE_ BUSY_ DA7 DA6 O SCO 12 H D ATA2 13 14 COMBO STRUCTURE H D ATA3 15 16 Digital Power Ring(1.8V/3.3V/GND) H D ATA4 17 18 Digital Power Ring(1.8V/3.3V/GND) UCMD 19 20 HCMD 21 H D ATA5 22 23 SD/MMC CONTROLLER GND 24 25 26 Figure 4.1 - GL422/GL423 Die Diagram D i g i ta l P o w e r R i n g ( 1 . 8 V / 3 . 3 V /G N D ) CGND PGND VCC33 PAD_T5 PAD_T2 PAD_T4 PAD_T0 PAD_T1 PAD_T3 PAD_DA2 PAD_DA3 PAD_DA1 PAD_DA0 PAD_DA4 PAD_DA5 CVDD18 PAD_A22 PAD_A16 PAD_A17 PAD_A18 PAD_A19 PAD_A20 PAD_A21 PAD_UDATA6 PAD_HDATA6 PAD_HDATA7 PAD_UDATA1 PAD_HDATA1 PAD_UDATA7 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 GND HDATA6 HDATA7 HDATA1 T4 T5 T0 T1 T2 T3 CVDD18 VCC33 DA0 DA1 DA2 DA3 DA4 DA5 H C LK 27 V C C 33 28 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution H D ATA0 29 30 Page 14 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 4.2 Die to QFN -56 Package Diagram 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PAD_DA6 60 PAD_A23 PAD_BUSY_B PAD_OSC_E PAD_CE1_B PAD_CE0_B PAD_WP_B PAD_WE_B PAD_RE_B PAD_rst_B PAD_rst_o Digital Power Ring(1.8V/3.3V/GND) 87 88 43 89 90 91 92 44 93 94 45 95 REXT2 REXT1 OUT2 OUT2 OUT1 VIN VIN VIN GND REGULATOR PAD_A22 PAD_A21 PAD_A20 PAD_A19 PAD_A18 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 15 16 26 25 24 23 22 21 20 19 18 17 46 47 48 49 50 51 52 96 97 98 99 100 101 102 103 104 105 106 AVDD2 Digital Power Rin g(1.8V/3.3V/GND) AVDD1 RREF AGND2 AGND1 DM DP AVDD3 AGND3 VBUS DGND2 DGND1 DVDD1 AVSS2 XI XO AVDD2 CUTCELL USB PAD_DA7 PAD_CLE PAD_ALE PAD_A13 CVDD18 PAD_A7 PAD_A6 PAD_A5 PAD_A4 PAD_A3 PAD_A2 PAD_A1 PAD_A0 VCC33 CGND PGND PAD_A17 PAD_A16 CGND PGND Dig it al Power Ring(1.8V/3.3V/GND) PAD_DA5 VCC33 PAD_DA4 PAD_DA3 PAD_DA2 PAD_DA1 PAD_DA0 PAD_T3 PAD_T2 PAD_T1 PAD_T0 PAD_HDATA1 PAD_UDATA1 PAD_HDATA7 PAD_UDATA7 PAD_HDATA6 PAD_UDATA6 PAD_T5 PAD_T4 SD/MMC CONTROLLER 53 107 108 109 54 55 110 111 112 56 113 114 115 116 AVDD2 AVSS2 AVSS1 AVDD1 117 118 119 120 121 CVDD18 PAD_SCLK PAD_SDATA PAD_A15 PAD_A14 Digital Power Ring(1.8V/3.3V/GND) CVDD18 PAD_A12 PAD_A11 PAD_A10 PAD_A9 PAD_A8 PAD_T7 PAD_T6 VCC33 PAD_UDATA2 PAD_HDATA2 PAD_UDATA3 PAD_HDATA3 PAD_UDATA4 PAD_HDATA4 PAD_UDATA5 PAD_HDATA5 VCC33 PAD_UDATA0 29 PAD_ USB_ACTV 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 10 11 12 13 Figure 4.2 - GL422/GL423 Die to QFN-56 Package Diagram ©2000-2006 Genesys Logic Inc. - All rights reserved. 14 1 2 3 4 5 4 6 7 8 9 30 1 2 3 4 5 6 7 8 9 PAD_HDATA0 PAD_Prt_B PAD_MCLK PAD_UCLK PAD_OSCO PAD_HCMDx PAD_HCMDy PAD_UCMD PAD_HCLK PGND CGND Page 15 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 4.3 QFN -56 Package Top View AVDD XO XI AGND AGND AVDD DP DM AGND RREF AVDD GND AVDD V18OUT AGND CVDD18 USB_ACT VCC33 MCLK HDATA2 HDATA3 UCMD HCMD GND UCLK HCLK VCC33 HDATA0 56 55 54 53 52 51 50 49 48 47 46 45 44 43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GL422/GL423 56-Pin Package (Top View) REXT1 REXT2 VCC33 rst_ OSC_E GND CVDD18 WE_ ALE CLE CE1_ CE0_ RE_ BUSY_ Figure 4.3 - GL422/GL423 QFN 56 Package Top View ©2000-2006 Genesys Logic Inc. - All rights reserved. CVDD18 HDATA1 T2 T3 DA0 DA1 DA2 DA3 DA4 VCC33 DA5 GND DA6 DA7 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Page 16 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 4.4 Die to VFBGA -54 Package Diagram A2 A3 E4 63 B6 D4 A4 A5 B4 C4 B5 C2 35 A1 56 62 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 61 PA D_DA6 B2 36 PA D_A23 60 66 F2 F3 PA D_BUSY _B PA D_OSC_ E PA D_CE1_ B PA D_CE0_ B PA D_WP_B PA D_WE_B PA D_RE_B PA D_rst_B PA D_rst_o Digital Power Ring(1.8V/3.3V/GND) A1 B1 B2 87 88 89 90 91 92 REXT2 REXT1 OUT2 OUT2 OUT1 VIN VIN VIN GND REGULATOR PAD_A22 PAD_A21 PAD_A20 PAD_A19 PAD_A18 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 H6 G6 F6 C6 G3 D5 E5 D6 F4 G4 F5 E6 E4 C1 93 94 E4 95 C2 C3 E3 D1 D2 D3 E3 96 97 98 99 100 101 102 103 104 105 106 107 AVDD2 Digital Po wer Ring (1.8V/3.3 V/GND) AVDD1 RREF AGND2 AGND1 DM DP AVDD3 AGND3 VBUS DGND2 DGND1 DVDD1 AVSS2 XI XO AVDD2 CUTCELL USB PA D_DA7 PA D_CLE PA D_ALE PA D_A13 C VDD18 PA D_A7 PA D_A6 PA D_A5 PA D_A4 PA D_A3 PA D_A2 PA D_A1 PA D_A0 VC C33 C GND PG ND PAD_A17 PAD_A16 CGND PGND Digit al Power Ring(1.8V/ 3.3V/GND ) PAD_DA5 VCC33 PAD_DA4 PAD_DA3 PAD_DA2 PAD_DA1 PAD_DA0 PAD_T3 PAD_T2 PAD_T1 PAD_T0 PAD_HDATA1 PAD_UDATA1 PAD_HDATA7 PAD_UDATA7 PAD_HDATA6 PAD_UDATA6 PAD_T5 PAD_T4 SD/MMC CONTROLLER E3 108 109 E1 E2 110 111 112 F1 113 E3 114 115 116 H1 117 118 119 120 121 G5 AVDD2 AVSS2 AVSS1 AVDD1 CVDD18 PAD_SCLK PAD_SDATA PAD_A15 PAD_A14 Digital Power Ring(1.8V/3.3V/GND) CVDD18 PAD_A12 PAD_A11 PAD_A10 PAD_A9 PAD_A8 PAD_T7 PAD_T6 VCC33 PAD_ UDATA2 PAD_ HDATA2 PAD_ UDATA3 PAD_ HDATA3 PAD_ UDATA4 PAD_ HDATA4 PAD_ UDATA5 PAD_ HDATA5 VCC33 PAD_ UDATA0 29 PAD_US B_ACTV 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 G1 G2 H2 H3 H4 H5 G3 E4 J1 J2 J3 J4 J5 Figure 4.4 - GL422/GL423 VFBGA54 Package Diagram ©2000-2006 Genesys Logic Inc. - All rights reserved. J6 30 1 2 3 4 5 6 7 8 9 PAD_ HDATA0 PA D_Prt_B PA D_MCLK PA D_UCLK PA D_OSCO PAD _HCMDx PAD _HCMDy PAD _UCMD PA D_HCLK PGND CGND Page 17 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 4.5 VFBGA -54 Package Top View 1 A B C D E F G H J REXT2 RST_B OSC_E WE_B CLE 6 DA7 REXT1 OUT2 WP_B CE1_B RE_B DA6 VIN AVDD1 RREF CE0_B BUSY_B DA5 DM DP AVDD CVDD18 DA4 DA2 X1 X2 AGND DGND AVSS VSS VSSD GND DA3 T2 VDDX VDD33 VDD33 ALE DA1 T3 HDATA1 VDD33 HDATA3 VCC33 DA0 HDATA7 HDATA6 CVDD18 HDATA2 HCMDY HDATA5 UCLK CVDD18 USB_AC TV MCLK DATA4 HCMDX HCLK HDATA0 Figure 4.5 - GL422/GL423 VFBGA 54 Package Top View ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 18 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 4.6 PAD/PIN Descripton 4.6.1 USB Interface Table 4.1- USB Interface QFN56 Pin# VFBG A54 Pin# Pin Name Pad# Pad Name Type Description Analog 3.3V power (Double Bonding) Analog 3.3V power 96 46 C2 AVDD 97 AVDD2 P AVDD1 P (Double Bonding) Reference resistor, normal 680ohm (1%) between RREF and GND 47 C3 RREF 98 RREF A 99 48 E3 AGND 100 49 50 51 52 NC 53 D1 D2 D3 E3 NC E3 DM DP AVDD AGND  AGND 101 102 103 104 105 106 AGND2 P Analog ground (Double Bonding) AGND1 DM DP AVDD3 AGND3 VBUS DGND2 P B B P P P P Analog ground (Double Bonding) USB DUSB D+ Analog 3.3V power Analog ground (No Bonding) Digital ground. (Tri-bonding) 53 E3 AGND  107 DGND1 P Digital ground. (Tri-bonding) NC NC 108 DVDD1 P Digital power (No Bonding) Analog ground 53 54 55 56 - E3 E1 E2 F1 - AGND XI XO AVDD - 109 110 111 112 - AVSS2 XI XO AVDD2 CUTCELL P I O P - (Tri-bonding) Crystal driver input Crystal driver output Analog 3.3V power (Double Bonding) (No Bonding) Page 19 ©2000-2006 Genesys Logic Inc. - All rights reserved. GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 56 F1 VDD 113 AVDD2 P Analog 3.3V power (Double Bonding) Analog ground 114 1 E3 AGND 115 AVSS2 P (Double Bonding) Analog ground (Double Bonding) AVSS1 P 116 2 H1 CVDD18 117 AVDD1 P 1.8V power supply (Double Bonding) CVDD18 P 1.8V power supply (Double Bonding) ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 20 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 4.6.2 Regulator Interface Table 4.2 – Regulator Interface QFN56 Pin# NC VFBG A54 Pin# NC Pin Name Pad# Pad Name Type Description 1.8V output (Max.40mA) (No Bonding)  91 OUT1 O 89 43 B2 V18OUT 90 OUT2 O 1.8V output (Max.100mA) (Double Bonding) OUT2 O Regulator 1.8V output (Double Bonding) 92 VIN P Analog 3.3V power (Tri-bonding ) 44 C1 AVDD 93 VIN P Analog 3.3V power (Tri-bonding ) 94 45 42 41 E4 B1 A1 GND REXT1 REXT2 95 88 87 VIN GND REXT1 REXT2 P P A A Analog 3.3V power (Tri-bonding ) Analog ground External Resistor pad External Resistor pad ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 21 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 4.6.3 Card Interface Table 4.3 – Card Interface QFN56 Pin# 11 VFBGA 54 Pin# H5 Pin Name Pad# Pad Name Type Description Controller clock signal from USB reader to card (rising edge) UCLK 26 PAD_UCLK B 12 J5 HCLK 27 PAD_HCLK B Controller clock signal from HOST Only to card (rising edge) SD/MMC mode: HCMD from/to 19 PAD_UCMD B USB reader SPI mode: Data-in signal from USB reader(Double Bonding) 8 J4 UCMD SD/MMC mode: HCMD from/to HOST 20 PAD_HCMDx B SPI mode: Data-in signal from HOST (Double Bonding) SD/MMC mode: HCMD from/to 9 H3 HCMD 21 PAD_HCMDy B HOST SPI mode: Data-in signal from HOST SD/MMC mode: HDATA0 from/to USB reader 29 PAD_UDATA0 B SPI mode: Data-out signal to USB reader 14 J6 HDATA0 (Double Bonding) SD/MMC mode: HDATA0 from/to 30 PAD_HDATA0 B HOST. SPI mode: Data-out signal to HOST (Double Bonding) SD/MMC mode: HDATA1 from/to 16 F6 HDATA1 38 PAD_UDATA1 B USB reader. SPI mode: not connected (Double Bonding) ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 22 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution SD/MMC mode: HDATA1 from/to 39 PAD_HDATA1 B HOST. SPI mode: not connected (Double Bonding) SD/MMC mode: HDATA2 from/to USB reader. 13 PAD_UDATA2 B SPI mode: not connected (Double Bonding) 6 H2 HDATA2 SD/MMC mode: HDATA2 from/to 14 PAD_HDATA2 B HOST. SPI mode: not connected (Double Bonding) SD/MMC mode: HDATA3 from/to 15 PAD_UDATA3 B USB reader. SPI mode: CS signal 7 G2 HDATA3 (Double Bonding) SD/MMC mode: HDATA3 from/to 16 PAD_HDATA3 B HOST. SPI mode: CS signal (Double Bonding) MMC mode: HDATA4 from/to USB 17 NC J3 18 PAD_HDATA4 B PAD_UDATA4 B reader. (Double Bonding) MMC mode: HDATA4 from/to HOST. (Double Bonding) MMC mode: HDATA5 from/to USB 22 NC H4 MMC mode: HDATA5 from/to 23 PAD_HDATA5 B HOST. (Double Bonding) MMC mode: HDATA6 from/to USB NC G6 34 PAD_UDATA6 B reader. (Double Bonding) PAD_UDATA5 B reader. (Double Bonding) ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 23 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution MMC mode: HDATA6 from/to 35 PAD_HDATA6 B HOST. (Double Bonding) MMC mode: HDATA7 from/to USB 36 NC G5 MMC mode: HDATA7 from/to 37 PAD_HDATA7 B HOST. (Double Bonding) PAD_UDATA7 B reader. (Double Bonding) 4.6.4 Flash Interface The flash interface is used to access AND/NAND flash, defined as Table 4.4. It is also shared with USB test interface, refers to Table 4.7. Table 4.4 – Flash Interface QFN56 Pin# VFBGA 54 Pin# C4 Pin Name Pad# Pad Name Type Description ‘0’ for FLASH chip 0 to select active (low-active). 31 CE0_ 65 PAD_CE0_B B 32 33 34 30 35 29 NC 19 20 21 22 B4 A5 F3 B5 A4 C5 B3 G4 F4 D6 E5 CE1_ CLE ALE RE_ WE_ BUSY_ WP_ DA0 DA1 DA2 DA3 66 67 68 64 69 63 71 44 45 46 47 PAD_CE1_B PAD_CLE PAD_ALE PAD_RE_B PAD_WE_B PAD_BUSY_B PAD_WP_B PAD_DA0 PAD_DA1 PAD_DA2 PAD_DA3 B B B B B B B B B B B ‘0’ for FLASH chip 1 to select active (low-active). FLASH command latch enable FLASH address latch enable FLASH read enable (low active) FLASH write enable (low active) FLASH ready when high, busy when low. FLASH write protect (low active) FLASH bus bit0 FLASH bus bit1 FLASH bus bit2 FLASH bus bit3 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 24 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 23 25 27 28 D5 C6 B6 A6 DA4 DA5 DA6 DA7 48 50 61 62 PAD_DA4 PAD_DA5 PAD_DA6 PAD_DA7 B B B B FLASH bus bit4 FLASH bus bit5 FLASH bus bit6 FLASH bus bit7 4.6.5 System Interface Table 4.5 – System Interface QFN56 Pin# VFBGA 54 Pin# Pin Name Pad# Pad Name Type Description Power-on reset input, low active (Double Bonding) 76 39 A2 rst_ 75 PAD_rst_B I PAD_rst_o PAD_USB_A CTV O Power-on reset output (Double Bonding) 3 J1 USB_ACT     MCLK OSC_E VCC33 VCC33 VCC33 VCC33 CVDD18 CVDD18 9 B USB active NC NC 8 PAD_Prt_B B Protect (No Bonding) NC NC 118 PAD_SCLK B Test port CLK. (No Bonding) NC NC 5 38 40 24 13 4 36 15 NC NC J2 A3 F2 G3 G3 G1 D4 H6 119 12 11 74 77 49 28 10 70 31 PAD_SDATA PAD_OSCO PAD_MCLK PAD_OSC_E VCC33 VCC33 VCC33 VCC33 CVDD18 CVDD18 B O I I P P P P P P Test port Data. (No Bonding) Clock output for test Main clock input. (No Bonding) Oscillator enable Digital 3.3V power supply Digital 3.3V power supply Digital 3.3V power supply Digital 3.3V power supply Digital 1.8V power supply Digital 1.8V power supply ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 25 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 73 37 E4 GND 72 CGND P Digital Ground (Double Bonding) PGND P Digital Ground (Double Bonding) 52 CGND PGND P Digital Ground (Double Bonding) 26 E4 GND 51 P Digital Ground (Double Bonding) 25 10 E4 GND 24 CGND PGND P Digital Ground (Double Bonding) P Digital Ground (Double Bonding) 4.6.6 Test Interface Table 4.6 – Test Interface QFN56 Pin# NC NC 17 18 NC NC NC VFBGA 54 Pin# NC NC E6 F5 NC NC NC Pin Name   T2 T3    Pad# 40 41 42 43 32 33 7 Pad Name PAD_T0 PAD_T1 PAD_T2 PAD_T3 PAD_T4 PAD_T5 PAD_T6 Type B B B B B B B Description Dual channel flash2 bus bit0 to bit7. (on-chip pulled-up). When power-on or hardware reset, T[3:0] is: 4’b0000: USB CPU Test (CPUTST = 1) 4’b0001: USB UTM Scan Mode (UTMSCANM = 1 ) 4’b0010: USB Scan Mode (SCANMOD = 1) 4’b0011: USB UTM Test (UTMTEST = 1) others: SD Controller Test Mode (T[7:4],T[1:0] no bonding) NC NC  6 PAD_T7 B ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 26 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 4.6.7 Use Flash Interface as USB Test Interface This interface is shared with Flash Interface. This is only for testing. In test mode, the flash interface will be used for USB test patterns: Table 4.7 –Use Flash Interface as USB Test Interface Pin Name CE0_ CE1_ CLE ALE RE_ WE_ BUSY_ WP_ DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 Pad# 65 66 67 68 64 69 63 71 44 45 46 47 48 50 61 62 Pad Name PAD_CE0_B PAD_CE1_B PAD_CLE PAD_ALE PAD_RE_B PAD_WE_B PAD_BUSY_B PAD_WP_B PAD_DA0 PAD_DA1 PAD_DA2 PAD_DA3 PAD_DA4 PAD_DA5 PAD_DA6 PAD_DA7 Type B B B B B B B B B B B B B B B B SCAN MOD DO4 DO7 UTM TEST TERM SUSP OP1 OP0 UTM SCANM DO4 DO7 CPU TEST DO6 DO1 SCANTE ST RXERR RXV TXVH DO6 DO1 SCANTEST VMI VPI RXACT TXV DO2 PLLDIS DataO_Sel DO0 TXRDY DO0 DO2 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 27 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution 4.6.8 Use Card Interface as USB Test Interface This interface is shared with card interface. This is only for testing. In test mode, the card interface will be also used for USB test patterns: Table 4.8 – Use Card Interface as USB Test Interface Pin Name UCLK UCMD HDATA0 HDATA1 HDATA2 HDATA3 HDATA4 HDATA5 HDATA6 HDATA7 Pad# 26 19 29 38 13 15 17 22 34 36 Pad Name PAD_UCLK PAD_UCMD PAD_UDATA0 PAD_UDATA1 PAD_UDATA2 PAD_UDATA3 PAD_UDATA4 PAD_UDATA5 PAD_UDATA6 PAD_UDATA7 Type B B B B B B B B B B SCAN MOD SCAN_EN DO5 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 UTM TEST SPEED D0 D1 D2 D3 D4 D5 D6 D7 UTM SCANM DO5 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 CPU TEST P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 28 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution CHAPTER 5 ELECTRICAL CHARACTERISTICS 5.1 Absolute Maximum Ratings Table 5.1 – Absolute Maximum Ratings Parameter Supply Voltage Supply Voltage Differentials (Vss1, Vss2) Storage Temperature Junction Temperature Symbol VDD Min 2.0 -0.3 -40 Max. 3.6 0.3 85 95 Unit V V o o Remark CMD0, 15,55, ACMD41 C C 5.2 Bus Operating Conditions Table 5.2 – Bus Operating Conditions Parameter Peak Voltage on all Lines Ground Voltage Operation Temperature Operation Moisture and Corrosion Symbol VDD Min 2.6 0 -25 Max. 3.6 Unit V V Remark 85 95% o C Rel. humidity 5.3 D.C. Characteristics Table 5.3 – D.C. Characteristics Parameter Supply voltage Input Leakage Current (HCLK, HCMD and HDATA2-0 to Ground) Input Leakage Current (HCLK, HCMD and HDATA2-0 to VDD) II 0< VIN < VCC 0.2 0.3 µA II 0< VIN < VCC 0.2 0.3 µA Symbol VCC Condition Min 2.0 Type 3.3 Max 3.6 Unit V ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 29 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution Input Leakage Current at HDATA3 to Ground Output High Voltage at HCMD Output High Voltage at HDATA Output Low Voltage at HCMD Output Low Voltage at HDATA Read/Write Current II VOH VOH VOL VOL ICC 0< VIN < VCC Clock = 20MHZ Clock = 20MHZ Clock = 20MHZ Clock = 20MHZ - - 0.43 3588 3586 - µA mV mV mV mV mA 39 39 - ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 30 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution CHAPTER 6 PACKAGE DIMENSION Figure 6.1 – GL422/GL423 56 Pin QFN Package ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 31 GL422/GL423 USB 2.0 +SD/MMC-controller Combo Solution Figure 6.2 – GL422/GL423 54 Pin VFBGA Package ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 32