GL424-WMGXX

Genesys Logic, Inc. GL424 SD/MMC Flash Card Controller Datasheet Revision 1.00 Apr. 18, 2007 GL424 SD/MMC Flash Card Controller Copyright: Copyright © 2007 Genesys Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic, Inc. Disclaimer: ALL MATERIALS ARE PROVIDED “AS IS” WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY, INCLUDING, WITHOUT LIMITATION, THE X-D PICTURE CARDTM LICENSE. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE. Trademarks: Is a registered trademark of Genesys Logic, Inc. All trademarks are the properties of their respective owners. Office: Genesys Logic, Inc. 12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel: (886-2) 8913-1888 Fax: (886-2) 6629-6168 http ://www.genesyslogic.com ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 2 GL424 SD/MMC Flash Card Controller Revision History Revision 0.90 1.00 Date 04/06/2006 04/18/2007 First formal release Add Die Pad, 46 PIN LGA, 51PIN LGA 1. Pin Assignment, p.11 2. Package Dimension, p.30 Description ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 3 GL424 SD/MMC Flash Card Controller TABLE OF CONTENTS CHAPTER 1 GENERAL DESCRIPTION................................................... 7 1.1 CARD INTERFACE ..................................................................................... 8 1.2 FLASH ACCESS INTERFACE ....................................................................... 8 1.3 EMBEDDED CPU ........................................................................................ 8 CHAPTER 2 FEATURES .............................................................................. 9 2.1 SD HOST INTERFACE ................................................................................. 9 2.2 MMC HOST INTERFACE ............................................................................ 9 2.3 FLASH MEMORY INTERFACE ..................................................................... 9 2.4 MICRO CONTROLLER AND ANALOG SYSTEM ......................................... 10 2.5 8KV-ESD PROTECTION ........................................................................... 10 2.6 DUAL CHANNEL FLASH TO REACH TOP READ/WRITE SPEED .............. 10 2.7 DUAL VOLTAGE APPLICATION ................................................................. 10 2.8 PRODUCT PACKAGES ............................................................................... 10 2.9 TECHNOLOGY........................................................................................... 10 2.10 MANUFACTURE ...................................................................................... 10 CHAPTER 3 PIN ASSIGNMENT .............................................................. 11 3.1 PINOUT ..................................................................................................... 11 3.2 PIN DESCRIPTIONS ................................................................................... 16 3.2.1 Regulator Interface......................................................................... 16 3.2.2 Card Interface ................................................................................. 18 3.2.3 Flash Interface................................................................................. 21 3.2.4 System Interface.............................................................................. 24 3.2.5 Test Interface................................................................................... 27 CHAPTER 4 ELECTRICAL CHARACTERISTICS............................... 28 4.1 ABSOLUTE MAXIMUM RATINGS .............................................................. 28 4.2 BUS OPERATING CONDITIONS ................................................................. 28 4.3 D.C. CHARACTERISTICS .......................................................................... 28 CHAPTER 5 PACKAGE DIMENSION..................................................... 30 CHAPTER 6 ORDERING INFORMATION ............................................ 34 ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 4 GL424 SD/MMC Flash Card Controller LIST OF FIGURES FIGURE 1. 1 - GL424 BLOCK DIAGRAM .............................................................................. 8 FIGURE 3.1 - 46 PIN LQFN PINOUT .................................................................................. 11 FIGURE 3.2 - 54 PIN VFBGA PINOUT ............................................................................... 12 FIGURE 3.3 – DIE PAD PINOUT .......................................................................................... 13 FIGURE 3.4 – 46 PIN LGA PINOUT .................................................................................... 14 FIGURE 3.5 – 51 PIN LGA PINOUT .................................................................................... 15 FIGURE 5.1- 46 PIN LQFN PACKAGE DIMENSION ........................................................... 30 FIGURE 5.2- 54 PIN VFBGA PACKAGE DIMENSION......................................................... 31 FIGURE 5.3- 46 PIN LGA PACKAGE DIMENSION ............................................................. 32 FIGURE 5.4- 51 PIN LGA PACKAGE DIMENSION ............................................................. 33 ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 5 GL424 SD/MMC Flash Card Controller LIST OF TABLES TABLE 3.1 - 46 PIN LQFN REGULATOR INTERFACE ....................................................... 16 TABLE 3.2 - 54 PIN VFBGA REGULATOR INTERFACE .................................................... 16 TABLE 3.3 – DIE PAD REGULATOR INTERFACE ................................................................ 16 TABLE 3.4 – 46 PIN LGA REGULATOR INTERFACE ......................................................... 17 TABLE 3.5 – 51 PIN LGA REGULATOR INTERFACE ......................................................... 17 TABLE 3.3 - 46 PIN LQFN CARD INTERFACE .................................................................. 18 TABLE 3.4 - 54 PIN VFBGA CARD INTERFACE ............................................................... 18 TABLE 3.5 – DIE PAD CARD INTERFACE ........................................................................... 19 TABLE 3.6 - 46 PIN LGA CARD INTERFACE ..................................................................... 20 TABLE 3.7 - 51 PIN LGA CARD INTERFACE ..................................................................... 20 TABLE 3.8 - 46 PIN LQFN FLASH INTERFACE ................................................................. 21 TABLE 3.9 - 54 PIN VFBGA FLASH INTERFACE .............................................................. 21 TABLE 3.10 – DIE PAD FLASH INTERFACE ........................................................................ 22 TABLE 3.11 – 46 PIN LGA FLASH INTERFACE ................................................................. 23 TABLE 3.12 – 51 PIN LGA FLASH INTERFACE ................................................................. 23 TABLE 3.13 - 46 PIN LQFN SYSTEM INTERFACE ............................................................ 24 TABLE 3.14 - 54 PIN VFBGA SYSTEM INTERFACE.......................................................... 24 TABLE 3.15 - DIE PAD SYSTEM INTERFACE ...................................................................... 25 TABLE 3.16 - 46 PIN LGA SYSTEM INTERFACE ............................................................... 26 TABLE 3.17 - 51 PIN LGA SYSTEM INTERFACE ............................................................... 26 TABLE 3.18 - 54 PIN VFBGA TEST INTERFACE .............................................................. 27 TABLE 3.19 - DIE PAD TEST INTERFACE ........................................................................... 27 TABLE 4.1 - ABSOLUTE MAXIMUM RATINGS .................................................................... 28 TABLE 4.2 - BUS OPERATING CONDITIONS ....................................................................... 28 TABLE 4.3 - D.C. CHARACTERISTICS ................................................................................ 28 TABLE 6.1- ORDERING INFORMATION .............................................................................. 34 ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 6 GL424 SD/MMC Flash Card Controller CHAPTER 1 GENERAL DESCRIPTION GL424 is a single-chip controller for SD and MMC memory cards. It is designed based on SD1.0/SD1.1/SD2.0 and MMC3.3/MMC4.0 specification. Its unique RAM based firmware strategy provides flexibility for fast compatibility and performance improvement, therefore, give customers strong support to win in today’s fast-changing market. With its simple interface, customers can easily apply it to SD and MMC memory cards manufacturing at the same time. GL424 manages interface protocol, data storage and retrieval, error detection and correction, defect handling and diagnostic, as well as power management. With a built-in flash management algorithm, GL424 is applicable for most types of flash in the market: SAMSUNG, MICRON, ST, TOSHIBA, HYNIX and RENESAS. GL424 is packaged LQFN-46 and VFBGA-54. Both die and LQFN/VFBGA package are available and completely meet SD and MMC memory card mechanical thickness requirement. card sockets provides easy PCB layout. The pin assignment that fits to GL424 is unique in its three advanced features: (1) Dual-channel solution as well as normal single channel solution with top access speed; (2) Dual voltage for both 1.8V and 3.3V interface; (3) 8KV-ESD protecting the whole card. VFBGA54 packaged GL424 has a dual channel flash access interface, which remarkably speed up read/write performance. It supports 16-bit flash also. GL424 provides 8KV ESD (human body mode) and 15KV ESD (mechanical mode) protection. Especially, GL424 can also provide such high voltage ESD protection to FLASH on the whole SD/MMC card. Therefore, greatly improved SD/MMC card’s reliability and high quality in unpredictable application environment. ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 7 GL424 SD/MMC Flash Card Controller Flash1 Interface HOST Interface Host Interface CARD Controller Flash Access IF Flash2 Interface GL424 Figure 1. 1 - GL424 Block Diagram 1.1 CARD Interface The card controller, complied with SD/MMC specification, explains commands from SD/MMC host and transfers data between SD/MMC host and flash. 1.2 Flash Access Interface The flash access interface communicates with CPU. It also manages two channels of flash, based on flash commands. Moreover, it implements defect processing, ECC, and address mapping, etc. 1.3 Embedded CPU Embedded CPU performs arithmetic and logical operations. In addition, it extracts instruction from ROM and SRAM, decodes and executes them. It also manages control and status signals between flash access interface and itself. ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 8 GL424 SD/MMC Flash Card Controller CHAPTER 2 FEATURES 2.1 SD Host Interface 2.2 MMC Host Interface 2.3 Flash Memory Interface ©2000-2007 Genesys Logic Inc. - All rights reserved. ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ Complies with SD Specification, Version 2.0 Complies with SD Specification, Version 1.1 Complies with SD Specification, Version 1.0 Supports SPI mode and CPRM functions Supports clock rate up to 25 MHz for SD1.0 Supports clock rate up to 52 MHz for SD1.1 and SD2.0 Buffers for multi-block flash memory programming DMA operation between buffers and flash memory Supports automatic CRC16 generation and verification on DATA3-0 Supports SD card exceed 4Gbytes capacity Complies with MultiMediaCard System Specification, Version 4.0 Complies with MultiMediaCard System Specification, Version 3.3 Supports SPI mode and CPRM functions Supports clock rate up to 20 MHz for MMC3.3 Supports clock rate up to 52 MHz for MMC4.0 Buffers for multi-block flash memory programming DMA operation between buffers and flash memory Supports automatic CRC16 generation and verification on DATA7-0 Direct interface to NAND/AND flash chips (SAMSUNG / TOSHIBA / HITACHI / RENESAS / MICRON / ST / HYNIX) Supports dual-channel, 16 bits flash (VFBGA54 package and die) Drives up to 4 flash memory chips, respectively (VFBGA54 package and die) Supports 64M / 128M / 256M / 512M / 1G / 2G / 4G / 8G bits flash chips Embedded firmware support for flash file system (FTL) Built-in flash management algorithm Powerful ECC for error detection and correction up to 6 bytes per 512bytes Page 9 GL424 SD/MMC Flash Card Controller 2.4 Micro Controller and Analog System 2.5 8KV-ESD protection ‧ 8KV human body ESD protection (contact discharge mode) for the whole card (not only controller chip itself) 2.6 Dual Channel FLASH to reach top Read/Write Speed 2.7 Dual voltage application 2.8 Product Packages 2.9 Technology 2.10 Manufacture ©2000-2007 Genesys Logic Inc. - All rights reserved. ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ RISC core with fast speed and less code size Flexibility to update system code Ability to add customers’ own feature ‧ 15KV mechanical mode ESD protection (air discharge mode) for the whole card (not only controller chip itself) GL424 provides dual channel flash access solution. This can reach the read/write speed almost doubled compared with single channel solution. GL424 provides the solution for dual voltage application. This means MMC4.0 card with GL424 can work with either 1.8V or 3.3V host interface. 46-pin LQFN package 54-pin VFBGA package 46-pin LGA package 51-pin LGA package 0.18um process Easy firmware development environment Supports firmware upgrade tool via PC Page 10 GL424 SD/MMC Flash Card Controller CHAPTER 3 PIN ASSIGNMENT 3.1 Pinout Figure 3.1 - 46 Pin LQFN Pinout ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 11 GL424 SD/MMC Flash Card Controller Figure 3.2 - 54 Pin VFBGA Pinout ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 12 ©2000-2007 Genesys Logic Inc. - All rights reserved. PAD1 PAD1 5 PAD1 6 PAD1 7 PAD1 8 PAD2 9 PAD2 0 PAD2 1 PAD2 2 PAD2 3 PAD2 4 PAD2 5 PAD2 6 PAD2 7 PAD2 8 PAD3 9 PAD3 0 PAD3 1 PAD3 2 PAD3 3 PAD3 4 PAD3 5 PAD3 6 PAD3 7 PAD3 8 PAD4 9 PAD4 0 PAD4 1 PAD4 2 PAD4 3 4 PAD_OSCO PAD_T0 PAD_T1 PAD_T2 PAD_T3 PAD_T4 PAD_T5 PAD_T6 VDDIN PAD_T7 PAD_CE0_B PAD_CE1_B PAD_ALE PAD_CLE PAD_WP_B PAD_RE_B PAD_WE_B PAD_BUSY_B PAD_DA7 PAD_DA6 PAD_DA5 V18IN VDDIN PAD_DA4 GNDIN PAD_DA3 PAD_DA2 PAD_DA1 PAD_DA0 PAD_Prt_B PAD4 PAD4 5 PAD4 6 PAD4 7 PAD4 8 PAD5 9 PAD5 0 PAD5 1 PAD5 2 PAD5 3 PAD5 4 PAD5 5 PAD5 6 PAD5 7 PAD5 8 PAD6 9 PAD6 0 1 PAD_DETECT PAD_DETECT PAD_HDATA2 PAD_HDATA2 PAD_HDATA3 PAD_HDATA3 PAD_HCMD PAD_HCMD VCC PAD_HCLK PAD_HCLK GND GND PAD_HDATA0 PAD_HDATA0 PAD_HDATA1 PAD_HDATA1 Figure 3.3 – Die Pad Pinout GL424 SD/MMC Flash Card Controller Page 13 GL424 SD/MMC Flash Card Controller GL424 46 PIN LGA Figure 3.4 – 46 Pin LGA Pinout ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 14 GL424 SD/MMC Flash Card Controller GL424 51 PIN LGA Figure 3.5 – 51 Pin LGA Pinout ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 15 GL424 SD/MMC Flash Card Controller 3.2 Pin Descriptions 3.2.1 Regulator Interface Table 3.1 - 46 PIN LQFN Regulator Interface Pin No. 1 2 3 4 5 6 Pin Name R1 R2 V18OUT VIN GND GNDOUT Type A A O P P P External Resistor pad External Resistor pad 1.8V output (Max.100mA) 3.3V power Ground Ground output Description Table 3.2 - 54 PIN VFBGA Regulator Interface Pin No. A6 A5 B5 C4 A4 B4 G5 Pin Name R1 R2 V18OUT V18Fsh VIN GND GNDX Type A A O O P P P External Resistor pad External Resistor pad Description 1.8V output (Max.100mA) 1.8V output (Max.30mA) 3.3V power Ground Ground Table 3.3 – Die Pad Regulator Interface Pad No. PAD1 PAD2 PAD3 Pad Name R1 R2 V18-out2 Type A A O External Resistor pad External Resistor pad Description 1.8V output (Max.100mA) (Double Bonding) Regulator 1.8V output (Double Bonding) 1.8V output (Max.40mA) PAD4 PAD5 V18-out2 V18-out1 O O ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 16 GL424 SD/MMC Flash Card Controller PAD6 VIN P 3.3V power (Tri-bonding ) 3.3V power (Tri-bonding ) 3.3V power (Tri-bonding ) Ground (Double Bonding) Ground (Double Bonding) Ground output when enhanced 8KV-ESD protected PAD7 VIN P PAD8 VIN P PAD9 GND P PAD10 PAD11 GND GNDOUT P P Table 3.4 – 46 PIN LGA Regulator Interface Pin No. 16 17 18 19 20 21 Pin Name R1 R2 V18OUT VIN GND GNDOUT Type A A O P P P External Resistor pad External Resistor pad Description 1.8V output (Max.100mA) 3.3V power Ground Ground Table 3.5 – 51 PIN LGA Regulator Interface Pin No. 17 18 19 48 20 21 22 Pin Name R1 R2 V18 V18Fsh VIN GND GNDX Type A A O O P P P External Resistor pad External Resistor pad Description 1.8V output (Max.100mA) 1.8V output (Max.30mA) 3.3V power Ground Ground ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 17 GL424 SD/MMC Flash Card Controller Note : A: Analog I: Input O: Output P: Power supply B: Bi-direction 3.2.2 Card Interface Table 3.3 - 46 PIN LQFN Card Interface Pin No. 20 18 Pin Name HCLK HCMD Type I B HCLK from HOST Description SD/MMC mode: HCMD from/to HOST SPI mode: Data-in signal from HOST SD/MMC mode: HDATA0 from/to HOST. SPI mode: Data-out signal to HOST SD/MMC mode: HDATA1 from/to HOST. SPI mode: not connected SD/MMC mode: HDATA2 from/to HOST. SPI mode: not connected SD/MMC mode: HDATA3 from/to HOST. SPI mode: CS signal MMC mode: HDATA4 from/to HOST. MMC mode: HDATA5 from/to HOST. MMC mode: HDATA6 from/to HOST. MMC mode: HDATA7 from/to HOST. 22 HDATA0 B 23 HDATA1 B 16 HDATA2 B 17 25 26 27 28 HDATA3 HDATA4 HDATA5 HDATA6 HDATA7 B B B B B Table 3.4 - 54 PIN VFBGA Card Interface Pin No. H1 F2 Pin Name HCLK HCMD Type I B HCLK from HOST Description SD/MMC mode: HCMD from/to HOST SPI mode: Data-in signal from HOST SD/MMC mode: HDATA0 from/to HOST. SPI mode: Data-out signal to HOST Page 18 J2 HDATA0 B ©2000-2007 Genesys Logic Inc. - All rights reserved. GL424 SD/MMC Flash Card Controller J1 HDATA1 B SD/MMC mode: HDATA1 from/to HOST. SPI mode: not connected SD/MMC mode: HDATA2 from/to HOST. SPI mode: not connected SD/MMC mode: HDATA3 from/to HOST. SPI mode: CS signal MMC mode: HDATA4 from/to HOST. MMC mode: HDATA5 from/to HOST. MMC mode: HDATA6 from/to HOST. MMC mode: HDATA7 from/to HOST. E1 HDATA2 B F1 J3 H2 H4 H3 HDATA3 HDATA4 HDATA5 HDATA6 HDATA7 B B B B B Table 3.5 – Die Pad Card Interface Pad No. PAD54 PAD55 Pad Name PAD_HCLK PAD_HCLK Type B B HCLK from HOST Backup PAD (No Bonding) Description PAD51 PAD_HCMD B SD/MMC mode: HCMD from/to HOST SPI mode: Data-in signal from HOST Backup PAD (No Bonding) SD/MMC mode: HDATA0 from/to HOST. SPI mode: Data-out signal to HOST Backup PAD (No Bonding) SD/MMC mode: HDATA1 from/to HOST. SPI mode: not connected Backup PAD (No Bonding) SD/MMC mode: HDATA2 from/to HOST. SPI mode: not connected Backup PAD (No Bonding) PAD52 PAD_HCMD B PAD59 PAD_HDATA0 B PAD58 PAD_HDATA0 B PAD61 PAD_HDATA1 B PAD60 PAD_HDATA1 B PAD47 PAD_HDATA2 B PAD48 PAD_HDATA2 B ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 19 GL424 SD/MMC Flash Card Controller Table 3.6 - 46 PIN LGA Card Interface Pin No. 37 35 Pin Name HCLK HCMD Type I B HCLK from HOST Description SD/MMC mode: HCMD from/to HOST SPI mode: Data-in signal from HOST SD/MMC mode: HDATA0 from/to HOST. SPI mode: Data-out signal to HOST SD/MMC mode: HDATA1 from/to HOST. SPI mode: not connected SD/MMC mode: HDATA2 from/to HOST. SPI mode: not connected SD/MMC mode: HDATA3 from/to HOST. SPI mode: CS signal MMC mode: HDATA4 from/to HOST. MMC mode: HDATA5 from/to HOST. MMC mode: HDATA6 from/to HOST. MMC mode: HDATA7 from/to HOST. 39 HDATA0 B 40 HDATA1 B 33 HDATA2 B 34 42 43 44 45 HDATA3 HDATA4 HDATA5 HDATA6 HDATA7 B B B B B Table 3.7 - 51 PIN LGA Card Interface Pin No. 38 36 Pin Name HCLK HCMD Type I B HCLK from HOST Description SD/MMC mode: HCMD from/to HOST SPI mode: Data-in signal from HOST SD/MMC mode: HDATA0 from/to HOST. SPI mode: Data-out signal to HOST SD/MMC mode: HDATA1 from/to HOST. SPI mode: not connected SD/MMC mode: HDATA2 from/to HOST. SPI mode: not connected SD/MMC mode: HDATA3 from/to HOST. SPI mode: CS signal MMC mode: HDATA4 from/to HOST. MMC mode: HDATA5 from/to HOST. Page 20 40 HDATA0 B 41 HDATA1 B 34 HDATA2 B 35 42 43 HDATA3 HDATA4 HDATA5 B B B ©2000-2007 Genesys Logic Inc. - All rights reserved. GL424 SD/MMC Flash Card Controller 44 45 HDATA6 HDATA7 B B MMC mode: HDATA6 from/to HOST. MMC mode: HDATA7 from/to HOST. 3.2.3 Flash Interface Table 3.8 - 46 PIN LQFN Flash Interface Pin No. 11 12 14 13 46 45 44 15 33 34 35 36 38 41 42 43 Pin Name CE0_ CE1_ CLE ALE RE_ WE_ BUSY_ WP_ DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 Type B B B B B B B B B B B B B B B B Description ‘0’ for FLASH chip 0 to select active (low-active). ‘0’ for FLASH chip 1 to select active (low-active). FLASH command latch enable FLASH address latch enable FLASH read enable (low active) FLASH write enable (low active) FLASH ready when high, busy when low. FLASH write protect (low active) FLASH bus bit0 FLASH bus bit1 FLASH bus bit2 FLASH bus bit3 FLASH bus bit4 FLASH bus bit5 FLASH bus bit6 FLASH bus bit7 Table 3.9 - 54 PIN VFBGA Flash Interface Pin No. B6 C5 C6 D5 D6 E6 Pin Name CE0_ CE1_ ALE CLE RE_ WE_ Type B B B B B B Description ‘0’ for FLASH chip 0 to select active (low-active). ‘0’ for FLASH chip 1 to select active (low-active). FLASH address latch enable FLASH command latch enable FLASH read enable (low active) FLASH write enable (low active) Page 21 ©2000-2007 Genesys Logic Inc. - All rights reserved. GL424 SD/MMC Flash Card Controller E5 D4 J5 J6 H5 H6 G6 F5 F6 E4 BUSY_ WP_ DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 B B B B B B B B B B FLASH ready when high, busy when low. FLASH write protect (low active) FLASH bus bit0 FLASH bus bit1 FLASH bus bit2 FLASH bus bit3 FLASH bus bit4 FLASH bus bit5 FLASH bus bit6 FLASH bus bit7 Table 3.10 – Die Pad Flash Interface Pad No. PAD25 PAD26 PAD28 PAD27 PAD30 PAD31 PAD32 PAD29 PAD43 PAD42 PAD41 PAD40 PAD38 PAD35 PAD34 PAD33 Pad Name PAD_CE0_B PAD_CE1_B PAD_CLE PAD_ALE PAD_RE_B PAD_WE_B PAD_BUSY_B PAD_WP_B PAD_DA0 PAD_DA1 PAD_DA2 PAD_DA3 PAD_DA4 PAD_DA5 PAD_DA6 PAD_DA7 Type B B B B B B B B B B B B B B B B Description ‘0’ for FLASH chip 0 to select active (low-active). ‘0’ for FLASH chip 1 to select active (low-active). FLASH command latch enable FLASH address latch enable FLASH read enable (low active) FLASH write enable (low active) FLASH ready when high, busy when low. FLASH write protect (low active) FLASH bus bit0 FLASH bus bit1 FLASH bus bit2 FLASH bus bit3 FLASH bus bit4 FLASH bus bit5 FLASH bus bit6 FLASH bus bit7 ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 22 GL424 SD/MMC Flash Card Controller Table 3.11 – 46 PIN LGA Flash Interface Pin No. 26 27 28 29 31 32 15 30 4 5 6 7 9 12 13 14 Pin Name CE0_ CE1_ ALE CLE RE_ WE_ BUSY_ WP_ DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 Type B B B B B B B B B B B B B B B B Description ‘0’ for FLASH chip 0 to select active (low-active). ‘0’ for FLASH chip 1 to select active (low-active). FLASH address latch enable FLASH command latch enable FLASH read enable (low active) FLASH write enable (low active) FLASH ready when high, busy when low. FLASH write protect (low active) FLASH bus bit0 FLASH bus bit1 FLASH bus bit2 FLASH bus bit3 FLASH bus bit4 FLASH bus bit5 FLASH bus bit6 FLASH bus bit7 Table 3.12 – 51 PIN LGA Flash Interface Pin No. 11 12 14 13 10 15 9 16 1 2 3 Pin Name CE0_ CE1_ ALE CLE RE_ WE_ BUSY_ WP_ DA0 DA1 DA2 Type B B B B B B B B B B B Description ‘0’ for FLASH chip 0 to select active (low-active). ‘0’ for FLASH chip 1 to select active (low-active). FLASH address latch enable FLASH command latch enable FLASH read enable (low active) FLASH write enable (low active) FLASH ready when high, busy when low. FLASH write protect (low active) FLASH bus bit0 FLASH bus bit1 FLASH bus bit2 ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 23 GL424 SD/MMC Flash Card Controller 4 5 6 7 8 DA3 DA4 DA5 DA6 DA7 B B B B B FLASH bus bit3 FLASH bus bit4 FLASH bus bit5 FLASH bus bit6 FLASH bus bit7 3.2.4 System Interface Table 3.13 - 46 PIN LQFN System Interface Pin No. 7 8 9 31 10 39 40 37 19 29 21 32 24 30 Pin Name MCLK Rst_ OSCO OSC_E VDDIN VDDIN V18IN GNDIN VCC VCC GND GND CVDD18 VDDOUT Type I I O I P P P P P P P P P P Main clock input. Power-on reset, low active Main clock output Oscillator enable Power supply for IO Power supply for IO Digital 1.8V power supply Digital GND 3.3V power supply 3.3V power supply Ground Ground 1.8V power supply 3.3V power output Description Table 3.14 - 54 PIN VFBGA System Interface Pin No. B3 A3 C3 E2 D2 Pin Name MCLK Rst_ OSCO OSC_E VDDIN Type I I O I P Main clock input. Description Power-on reset, low active Main clock output Oscillator enable Power supply for flash interface IO Page 24 ©2000-2007 Genesys Logic Inc. - All rights reserved. GL424 SD/MMC Flash Card Controller F4 F3 G3 G4 G2 J4 E3 G1 V18IN VCC VCC GND CVDD18 VDDOUT Prt_ DETECT P P P P P P B O Digital 1.8V power supply 3.3V power supply 3.3V power supply Ground 1.8V power supply 3.3V power output Protect Power detect Table 3.15 - Die Pad System Interface Pad No. PAD13 PAD14 PAD44 PAD15 PAD12 PAD45 PAD46 PAD74 PAD73 PAD23 PAD37 PAD36 PAD39 PAD53 PAD56 PAD57 PAD62 PAD71 PAD72 PAD75 Pad Name PAD_rst_B PAD_rst_o PAD_Prt_B PAD_OSCO PAD_MCLK PAD_DETECT PAD_DETECT PAD_OSC_E PAD_OSC_E VDDIN VDDIN V18IN GNDIN VCC GND GND CVDD18 VCC V33OUT GND Type I O B O I B B I I P P P P P P P P P P P Description Power-on reset input, low active Power-on reset output Protect Clock output for test Main clock input. Card detect Backup PAD (No Bonding) Oscillator enable Backup PAD (No Bonding) Power supply for flash interface IO Power supply for flash interface IO Digital 1.8V power supply Ground input 3.3V power supply Ground Ground 1.8V power supply 3.3V power supply 3.3V power output when enhanced 8KV-ESD protected Ground ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 25 GL424 SD/MMC Flash Card Controller Table 3.16 - 46 PIN LGA System Interface Pin No. 22 23 24 2 10 25 1 36 46 3 38 8 11 41 Pin Name MCLK Rst_ OSCO OSC_E VDDIN VDDIN VDDOUT VCC VCC GND GND GNDIN V18IN CVDD18 Type I I O I P P P P P P P P P P Main clock input. Description Power-on reset, low active Main clock output Oscillator enable Power supply for flash interface IO Power supply for flash interface IO 3.3V power output 3.3V power supply 3.3V power supply Ground Ground Ground 1.8V power supply 1.8V power supply Table 3.17 - 51 PIN LGA System Interface Pin No. 51 23 49 47 32 37 39 46 33 50 Pin Name MCLK Rst_ OSCO OSC_E VDDIN VCC GND VDDOUT Prt_ DETECT Type I I O I P P P P B O Main clock input. Description Power-on reset, low active Main clock output Oscillator enable Power supply for flash interface IO 3.3V power supply Ground 3.3V power output Protect Power detect ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 26 GL424 SD/MMC Flash Card Controller 3.2.5 Test Interface Table 3.18 - 54 PIN VFBGA Test Interface Pin No. A1 A2 B2 B1 C2 C1 D3 D1 Pin Name T0 T1 T2 T3 T4 T5 T6 T7 Type B B B B B B B B Description Flash2 bus bit0 to bit7 when dual channel mode; Flash bus bit8 to bit15 when 16-bit flash mode; Test mode input when testing mode. (On-chip pulled-up). Table 3.19 - Die Pad Test Interface Pad No. PAD16 PAD17 PAD18 PAD19 PAD20 PAD21 PAD22 PAD24 Pad Name PAD_T0 PAD_T1 PAD_T2 PAD_T3 PAD_T4 PAD_T5 PAD_T6 PAD_T7 Type B B B B B B B B Description Flash2 bus bit0 to bit7 when dual channel mode; Flash bus bit8 to bit15 when 16-bit flash mode; Test mode input when testing mode. (On-chip pulled-up). ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 27 GL424 SD/MMC Flash Card Controller CHAPTER 4 ELECTRICAL CHARACTERISTICS 4.1 Absolute Maximum Ratings Table 4.1 - Absolute Maximum Ratings Parameter Supply Voltage Supply Voltage Differentials (Vss1, Vss2) Storage Temperature Junction Temperature Symbol VDD Min 2.0 -0.3 -40 Max. 3.6 0.3 85 95 Unit V V o o Remark CMD0, 15,55, ACMD41 C C 4.2 Bus Operating Conditions Table 4.2 - Bus Operating Conditions Parameter Peak Voltage on all Lines Ground Voltage Operation Temperature Operation Moisture and Corrosion Symbol VDD Min 2.6 0 -25 Max. 3.6 Unit V V Remark 85 95% o C Rel. humidity 4.3 D.C. Characteristics Table 4.3 - D.C. Characteristics Parameter Supply voltage Input Leakage Current (HCLK, HCMD and HDATA2-0 to Ground) Input Leakage Current (HCLK, HCMD and HDATA2-0 to VDD) Input Leakage Current at HDATA3 to Ground II 0< VIN < VCC 0.2 0.3 µA II 0< VIN < VCC 0.2 0.3 µA Symbol VCC Condition Min 2.0 Typ. 3.3 Max 3.6 Unit V II 0< VIN < VCC - - 0.43 µA ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 28 GL424 SD/MMC Flash Card Controller Output High Voltage at HCMD Output High Voltage at HDATA Output Low Voltage at HCMD Output Low Voltage at HDATA Read/Write Current VOH VOH VOL VOL ICC Clock = 20MHz Clock = 20MHz Clock = 20MHz Clock = 20MHz 39 39 - - 3588 3586 - mV mV mV mV mA ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 29 GL424 SD/MMC Flash Card Controller CHAPTER 5 PACKAGE DIMENSION Figure 5.1- 46 Pin LQFN Package Dimension ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 30 GL424 SD/MMC Flash Card Controller Figure 5.2- 54 Pin VFBGA Package Dimension ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 31 GL424 SD/MMC Flash Card Controller Figure 5.3- 46 PIN LGA Package Dimension ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 32 GL424 SD/MMC Flash Card Controller Figure 5.4- 51 PIN LGA Package Dimension ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 33 GL424 SD/MMC Flash Card Controller CHAPTER 6 ORDERING INFORMATION Table 6.1- Ordering Information Part Number GL424-PMGXX GL424-PMGXX GL424-WMGXX GL424-WOGXX Package 46-Pin LQFN 54-Pin VFBGA 46-Pin LGA 51-Pin LGA Normal/Green Green Package Green Package Green Package Green Package Version XX XX XX XX Status Available Available Available Available ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 34