GL811E

Genesys Logic, Inc. GL811E USB 2.0 to ATA / ATAPI Bridge Controller Datasheet Revision 1.25 May. 03, 2006 GL811E USB 2.0 to ATA/ATAPI Bridge Controller Copyright: Copyright © 2006 Genesys Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic Inc.. Disclaimer: ALL MATERIALS ARE PROVIDED “AS IS” WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE. Trademarks: is a registered trademark of Genesys Logic, Inc. All trademarks are the properties of their respective owners. Office: Genesys Logic, Inc. 12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel: (886-2) 8913-1888 Fax: (886-2) 6629-6168 http ://www.genesyslogic.com ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 2 GL811E USB 2.0 to ATA/ATAPI Bridge Controller Revision History Revision 1.00 1.01 1.10 1.11 1.20 1.21 1.22 1.23 1.24 1.25 Date 06/13/2003 06/24/2003 11/26/2003 11/27/2003 05/05/2004 09/23/2004 12/29/2004 02/02/2005 10/14/2005 05/03/2006 First formal release. Changed product name from GL811 to GL811E. 1. Added some features in Chapter 2. 2. Added 64 pin LQFP data in pinouts, pin description and package dimension. Description 3. Added Chapter 8 “Ordering Infromation”. Changed pin# 38,39,21 name from IOADR0~2 to DA0~2. 1. Removed PIO mode description. 2. Changed package dimension 1. Added USB2.0 certified Test ID in Chapter 2 Features 2. Updated IC Marking in package dimension diagram Added TQFP package information in Features, Package Dimension and Ordering Information. Changed IC marking in package dimension Add IDE Bus voltage tolerance information, table3.1, p.11~12 Delete 48 Pin TQFP and 64 Pin TQFP Pinout/Package ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 3 GL811E USB 2.0 to ATA/ATAPI Bridge Controller TABLE OF CONTENTS CHAPTER 1 CHAPTER 2 CHAPTER 3 GENERAL DESCRIPTION................................................. 7 FEATURES ........................................................................... 8 PIN ASSIGNMENT .............................................................. 9 3.1 PINOUTS .................................................................................................. 9 3.2 PIN DESCRIPTIONS ................................................................................ 11 CHAPTER 4 CHAPTER 5 CHAPTER 6 BLOCK DIAGRAM............................................................ 13 FUNCTION DESCRIPTION ............................................. 14 ELECTRICAL CHARACTERISTICS.............................. 15 6.1 ABSOLUTE MAXIMUM RATINGS ............................................................ 15 6.2 TEMPERATURE CONDITIONS ................................................................. 15 6.3 DC CHARACTERISTICS.......................................................................... 15 6.3.1 I/O 8 Type digital pins (For pad type I/O 8 @ VCC=3.6V) ......... 15 6.3.2 I/O 16 Type digital pins (For pad type I/O 16 @ VCC=3.6V)...... 16 6.3.3 D+/ D- (For pad type u20mia @ VCC=3.6V)................................ 16 6.3.4 Switching Characteristics ............................................................ 16 6.4 AC CHARACTERISTICS- ATA/ ATAPI ................................................. 17 6.4.1 Register Transfers ........................................................................ 18 6.4.2 Multiword DMA data transfer .................................................... 19 6.4.3 Ultra DMA data transfer ............................................................. 23 6.5 AC CHARACTERISTICS - USB 2.0.......................................................... 30 CHAPTER 7 CHAPTER 8 PACKAGE DIMENSION................................................... 31 ORDERING INFORMATION........................................... 33 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 4 GL811E USB 2.0 to ATA/ATAPI Bridge Controller LIST OF FIGURES FIGURE 3.1 - 48 PIN LQFP PINOUT DIAGRAM .................................................................9 FIGURE 3.2 - 64 PIN LQFP PINOUT DIAGRAM ...............................................................10 FIGURE 4.1 - BLOCK DIAGRAM ......................................................................................13 FIGURE 6.1 - INITIATING A MULTIWORD DMA DATA BURST ........................................20 FIGURE 6.2 - SUSTAINING A MULTIWORD DMA DATA BURST .......................................21 FIGURE 6.3 - DEVICE TERMINATING A MULTIWORD DMA DATA BURST ......................21 FIGURE 6.4 - HOST TERMINATING A MULTIWORD DMA DATA BURST ..........................22 FIGURE 6.5 - INITIATING AN ULTRA DMA DATA-IN BURST ...........................................24 FIGURE 6.6 - SUSTAINED ULTRA DMA DATA-IN BURST ................................................24 FIGURE 6.7 - HOST PAUSING AN ULTRA DMA DATA-IN BURST .....................................25 FIGURE 6.8 - DEVICE TERMINATING AN ULTRA DMA DATA-IN BURST.........................25 FIGURE 6.9 - HOST TERMINATING AN ULTRA DMA DATA-IN BURST ............................26 FIGURE 6.10 - INITIATING AN ULTRA DMA DATA-OUT BURST .....................................27 FIGURE 6.11 - SUSTAINED ULTRA DMA DATA-OUT BURST...........................................27 FIGURE 6.12 - DEVICE PAUSING AN ULTRA DMA DATA-OUT BURST ............................28 FIGURE 6.13 - HOST TERMINATING AN ULTRA DMA DATA-OUT BURST.........................29 FIGURE 6.14 - DEVICE TERMINATING AN ULTRA DMA DATA-OUT BURST ...................30 FIGURE 7.1 - GL811E 48 PIN LQFP PACKAGE ..............................................................31 FIGURE 7.3 - GL811E 64 PIN LQFP PACKAGE ..............................................................32 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 5 GL811E USB 2.0 to ATA/ATAPI Bridge Controller LIST OF TABLES TABLE 3.1 - PIN DESCRIPTIONS ......................................................................................11 TABLE 6.1 - MAXIMUM RATINGS ...................................................................................15 TABLE 6.2 - TEMPERATURE CONDITIONS.......................................................................15 TABLE 6.3 - I/O 8 TYPE DIGITAL PINS (FOR PAD TYPE I/O 8 @ VCC=3.6V) ....................15 TABLE 6.4 - I/O 16 TYPE DIGITAL PINS (FOR PAD TYPE I/O 16 @ VCC=3.6V) ................16 TABLE 6.5 - D+/ D- (FOR PAD TYPE U20MIA @ VCC=3.6V) ............................................16 TABLE 6.6 - SWITCHING CHARACTERISTICS ..................................................................16 TABLE 6.7 - ULTRA DMA DATA BURST TIMING REQUIREMENTS ....................................23 TABLE 8.1 - ORDERING INFORMATION...........................................................................33 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 6 GL811E USB 2.0 to ATA/ATAPI Bridge Controller CHAPTER 1 GENERAL DESCRIPTION The GL811E is a highly-compatible, low cost USB 2.0 to ATA / ATAPI bridge controller, which integrates Genesys Logic own design high speed UTMI (USB 2.0 Transceiver Macrocell Interface) transceiver. As a one-chip solution which complies with Universal Serial Bus specification rev. 2.0 and ATA / ATAPI-6 specification rev 1.0, the GL811E can support various kinds of ATA / ATAPI device. There are totally 4 endpoints in the GL811E controller, Control (0), Bulk In (1), Bulk Out (2), and Interrupt (3). By complies with the USB Storage Class specification ver.1.0 (Bulk only protocol), the GL811E can support not only plug and play but also Windows XP/ 2000/ ME default driver. The GL811E uses 12MHz crystal and slew-rate controlled pads to reduce the EMI issue. With 48-pin LQFP (9mmX9mm) package, the GL811E is the best cost/ performance solution to fit different situations in the USB 2.0 high speed storage class applications such as Hard Disk, CD-ROM, CD-R / RW and DVD-ROM. ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 7 GL811E USB 2.0 to ATA/ATAPI Bridge Controller CHAPTER 2 • • • • • • • • • • • • • • • • • • • • • FEATURES Complies with Universal Serial Bus specification rev. 2.0. Complies with ATA/ATAPI-6 specification rev 1.0. Complies with USB Storage Class specification ver.1.0. (Bulk only protocol) Operating system supported: Win XP / 2000 / Me / 98 / 98SE; Mac OS 9.X / X. Integrated USB 2.0 Transceiver Macrocell Interface (UTMI) transceiver and Serial Interface Engine (SIE). USB 2.0 certified (TestID=40380268) Supports 4 endpoints: Control (0) / Bulk Read (1) / Bulk Write (2) / Interrupt (3). 64 / 512 bytes Data Payload for full / high speed Bulk Endpoint. Supports 16-bit Multiword DMA mode and Ultra DMA mode interface (Ultra 33 / 66). Embedded 7.5 MIPS RISC CPU. ROM size: 4k words; RAM size: 128 bytes. Supports Power Down mode and USB suspend indicator. Supports USB 2.0 TEST mode features. Supports 2 GPIO (GPIO5 & 6) for programmable AP (only for 64 pin package). Supports device power control for power on/off when running suspend mode (only for 64 pin package). Supports 32 bit and 48 bit LBA hard disk. Provides LED indicator for Full Speed and High Speed (only for 64 pin package). 12 MHz external clock to provide better EMI. 3.3V power input; 5V tolerance pad for IDE interface. Supports Wakeup ability. Available in 48-pin LQFP and 64-pin LQFP package. ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 8 GL811E USB 2.0 to ATA/ATAPI Bridge Controller CHAPTER 3 3.1 Pinouts PIN ASSIGNMENT DMACK_ AGND1 DIOW_ IOR DY INTRQ DIOR_ TEST CS0_ DA1 DA0 X1 26 11 IODD[15] 36 35 34 33 32 31 30 29 28 27 10 G P IO 7 DVC C1 DGND1 IODD[8] IODD[9] IODD[10] IODD[11] IODD[12] IODD[13] Figure 3.1 - 48 Pin LQFP Pinout Diagram ©2000-2006 Genesys Logic Inc. - All rights reserved. IODD[14] CBLID_ 12 1 2 3 4 5 6 7 8 9 25 X2 Page 9 GL811E USB 2.0 to ATA/ATAPI Bridge Controller NC DMARQ IODD0 IODD1 IODD2 IODD3 DGND1 DVCC1 IODD4 IODD5 IODD6 IODD7 GPIO1 PWR_CT L 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 X2 AVCC1 RREF AGND0 DMH DMF DPH DPF AVCC0 RPU RESET# DA2 CS1_ NC NC NC GL811E LQFP - 64 25 24 23 22 21 20 19 18 17 F_LED H_LED Figure 3.2 - 64 Pin LQFP Pinout Diagram ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 10 GL811E USB 2.0 to ATA/ATAPI Bridge Controller 3.2 Pin Descriptions Table 3.1 - Pin Descriptions Pin Name GPIO7 GPIO5~6 IODD[8:11] DVCC1~2 DGND1~2 IODD[12:15] CBLID_ CS1_ DA2/SK RESET# RPU AVCC0~1 DPF DPH DMF DMH AGND0~1 RREF X2 X1 TEST CS0_ DA0~1 DA2 INTRQ DMACK_ IORDY 48Pin# 64 Pin# I/O Type 1 2~5 6,43 7,42 8~11 12 13 14 15 16 17,24 18 19 20 21 22,27 23 25 26 28 29 30,31 32 33 34 1 3,4 5~8 56,9 55,10 11~14 15 20 22 23 24,31 25 26 27 28 29,34 30 32 33 37 38,39 21 44 45 46 B (tri) O B (tri) P P B (tri) I (tri) O (tri) O (tri) I (pu) A P B B B B P A B I I (pd) O (tri) O (tri) O (tri) I (tri) O (tri) I (pu) GPIO7 (**) AP programmable IDE data bus 8~11 (*****) Digital VCC Digital ground IDE data bus 12~15 (*****) Cable select input (*****) Chip select 1 (*****) IDE address 2 / Serial data clock for EEPROM (*****) Description Reset pin (***) 3.3v output Analog VCC Full speed DP High speed DP Full speed DM High speed DM Analog ground Reference resister connect (****) Crystal output Crystal input, 12Mhz TEST mode input Chip select 0 (*****) IDE address 0~1 (*****) IDE address 2 (*****) IDE interrupt input (*****) IDE acknowledge (*****) IDE ready (*****) ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 11 GL811E USB 2.0 to ATA/ATAPI Bridge Controller O (tri) O (tri) I (pd) B (tri) B (tri) B (tri) O O O DIOR_ DIOW_ DMARQ IODD[0:3] IODD[4:7] GPIO1 PWR_CTL F_LED H_LED 35 36 37 38~41 44~47 48 - 47 48 50 51~54 57~60 61 62 63 64 IDE read signal (*****) IDE write signal (*****) IDE request (*****) IDE data bus 0~3 (*****) IDE data bus 4~7 (*****) GPIO1 Power control Full speed LED High speed LED 2,16~19, NC No connection 35,49, (*) The different of I/O 8 type from I/O 16 type is the typical drive current. The typical drive current of I/O 8 type is 8 mA, and for I/O pad 16 is 16 mA. (**) When operating in default mode: GPIO7 is the ATA/ ATAPI reset input , 5V tolerance. (***) When Reset pin is pulled low, the IDE bus will be in tri-state. (****) RREF must be connected with a 510 ohm resister to ground. (*****) 5V tolerance Notation: Type O I B B/I B/O P A SO pu pd odpu tri Output Input Bi-directional Bi-directional, default input Bi-directional, default output Power / Ground Analog Automatic output low when suspend Internal pull up Internal pull down Open drain with internal pull up Tri-state ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 12 GL811E USB 2.0 to ATA/ATAPI Bridge Controller CHAPTER 4 BLOCK DIAGRAM DMACK_ DIOR_ DIOW_ CS1_, CS0_ DA2 DA1 DA0 IODD15-0 INTRQ CBLID_ DMARQ IORDY CLK15 GPIO1 CPU Control Register RPU GPIO7 8 CONTROL FIFO CLK30 DPF RXSTS DPH TXFIFO0 8/16-Bit IDE 4 TXFIFO1 SIE TXCTL UTMI USB2.0 DMF DMH Engine 16 RXFIFO0 LOGIC TXCVR 12-96MHz RXFIFO1 DATA RREF X10 Clkgen 12MHz X40 Figure 4.1 - Block Diagram ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 13 GL811E USB 2.0 to ATA/ATAPI Bridge Controller CHAPTER 5 FUNCTION DESCRIPTION 1. USB 2.0 TXCVR The USB 2.0 Transceiver is the analog circuitry to handle the USB HS/FS signaling. 2. UTMI (USB 2.0 Transceiver Macrocell Interface) Logic The UTMI Logic is compliant to Intel’s UTMI specification 1.01. This block handles the low level USB protocol and signaling. The major jobs of UTMI Logic is data and clock recovery, NRZI encoding/decoding, Bit Stuffing/De-stuffing, USB2.0 test modes supporting and serial / parallel conversion. 3. SIE (Serial Interface Engine) The SIE contains the USB packet ID and address recognition logic, and other sequencing and state machine logic to handle USB packets and transactions. 4. PLL 10XPLL provides the 120MHz clock output for UTMI Logic block. UTMI operates in 120MHz for USB HS data processing. 40XPLL block will provide 480MHz for USB HS data transmission. 5. CLKGEN CLKGEN is the clock generator block for the logic blocks. It generates 15MHz clock for micro controller, 48MHz for MDMA mode, 96MHz for UDMA mode, and 30MHz clock for UTMI, SIE, and FIFO. 6. CPU The CPU is the control center of GL811E. It’s an 8-bit micro controller operating in 15MHz, 7.5 MIPS. After receiving a USB command, it decodes the host command, then it re-assigns tasks to the IDE engine, GPIO, FIFO, and response proper data/status to USB host. 7. IDE Engine The IDE engine is extended from standard ATA / ATAPI protocol. It supports multiword DMA mode, and ultra DMA mode data transfers. 8. FIFOs Control FIFO is used as Control Read / Write FIFO. TXFIFO0 / TXFIFO1 are two sets of 512-byte ping-pong FIFO for Bulk Read endpoint. It buffers data from IDE engine, and re-direct to USB SIE logic. RXFIFO0 / RXFIFO1 are two sets of 512-byte ping-pong FIFO for Bulk Write endpoint. It buffers data from USB SIE logic, and re-direct to IDE engine. 9. Control Registers Control Register configures GL811E to proper operation. For example, CPU can set register to generate wakeup event, enter suspend, transmits proper USB packet to host. 10. ATA/ATAPI The GL811E complies with ATA/ATAPI-6 specification rev. 1.0. Please refer to the specifications for more information. 11. USB 2.0 The GL811E complies with Universal Serial Bus specification rev. 2.0, and it integrates Genesys Logic own design UTMI transceiver that fully complies with the USB 2.0 Transceiver Macercell Interface (UTMI) specification rev. 1.01. Please refer to the specifications for more information. ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 14 GL811E USB 2.0 to ATA/ATAPI Bridge Controller CHAPTER 6 ELECTRICAL CHARACTERISTICS 6.1 Absolute Maximum Ratings Table 6.1 - Maximum Ratings Symbol VCC VI VI/O VAI/O VESD TA DC supply voltage DC input voltage DC input voltage range for I/O DC input voltage for USB D+/D- pins Static discharge voltage Ambient Temperature Parameter Min. +3.0 -0.3 -0.3 -0.3 4000 0 100 Max. +3.6 VCC + 0.3 VCC + 0.3 VCC + 0.3 Unit V V V V V o C 6.2 Temperature Conditions Table 6.2 - Temperature Conditions Item Storage Temperature Operating Temperature Value -50oC ~ 150 oC 0 oC ~ 70 oC 6.3 DC Characteristics 6.3.1 I/O 8 Type digital pins (For pad type I/O 8 @ VCC=3.6V) Table 6.3 - I/O 8 Type digital pins (For pad type I/O 8 @ VCC=3.6V) Parameter Current sink @ VOL = 0.4V Current output @ VOH = 2.4V (TTL high) Falling slew rate at 30 pF loading capacitance Rising slew rate at 30 pF loading capacitance Input high threshold voltage Input low threshold voltage Hysteresis voltage Leakage current for pads with internal pull up or pull down resistor Pad internal pull down resister Pad internal pull up resister Supply current 1.36 0 46 51K 85K 105K 168K 152K 251K 109 Min. 7.79 16.36 0.26 0.30 Typ. 10.83 19.87 0.50 0.57 Max. 14.09 23.39 0.80 0.91 1.64 Unit mA mA V/ns V/ns V V V µA Ohms Ohms mA ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 15 GL811E USB 2.0 to ATA/ATAPI Bridge Controller 6.3.2 I/O 16 Type digital pins (For pad type I/O 16 @ VCC=3.6V) Table 6.4 - I/O 16 Type digital pins (For pad type I/O 16 @ VCC=3.6V) Parameter Current sink @ VOL = 0.4V Current output @ VOH = 2.4V (TTL high) Falling slew rate at 30 pF loading capacitance Rising slew rate at 30 pF loading capacitance Input high threshold voltage Input low threshold voltage Pad internal pull down resister 0.89 51K 105K 152K Min. 16.20 24.13 0.51 0.46 Typ. 21.90 29.46 0.93 0.83 Max. 27.68 34.80 1.35 1.27 2.15 Unit mA mA V/ns V/ns V V Ohms 6.3.3 D+/ D- (For pad type u20mia @ VCC=3.6V) Table 6.5 - D+/ D- (For pad type u20mia @ VCC=3.6V) Parameter D+/D- static output LOW (RL of 1.5K to VCC ) D+/D- static output HIGH (RL of 15K to GND ) Differential input sensitivity Single-ended receiver threshold Transceiver capacitance Hi-Z state data line leakage Driver output resistance -10 28 Min. 0 2.8 0.2 0.8 2.0 20 +10 43 Typ. Max. 0.3 3.6 Unit V V V V pF µA Ohms 6.3.4 Switching Characteristics Table 6.6 - Switching Characteristics Parameter X1 crystal frequency X1 cycle time D+/D- rise time with 50pF loading D+/D- fall time with 50pF loading 4 4 Min. 11.97 Typ. 12 83.3 20 20 Max. 12.03 Unit MHz ns ns ns ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 16 GL811E USB 2.0 to ATA/ATAPI Bridge Controller 6.4 AC Characteristics- ATA/ ATAPI The GL811E complies with ATA / ATAPI-6 specification rev 1.0, which supports following data transfer modes: 1. DMA (Direct Memory Access) data transfer: DMA data transfer means of data transfer between device and host memory without host processor intervention. - Multiword DMA: Multiword DMA is a data transfer protocol used with the READ DMA, WRITE DMA, READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When a Multiword DMA transfer is enabled as indicated by IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data, this data transfer protocol shall be used for the data transfers associated with these commends. (Please refer to the ATA / ATAPI-6 specification rev 1.0 for more information.) - Ultra DMA: Ultra DMA Is a data transfer protocol used with the READ DMA, WRITE DMA, READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When this protocol is enabled, the Ultra DMA protocol shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only. (Please refer to the ATA / ATAPI-6 specification rev 1.0 for more information.) Following listed the symbols and their respective definitions that are used in the timing diagram: Signal transition (asserted or negated) Data transition (asserted or negated) Data valid Undefined but not necessarily released Asserted, negated or released Released The “other” condition if a signal is shown with no change - All signals are shown with the asserted condition facing to the top of the page. The negated condition is shown towards the bottom of the page relative to the asserted condition. The interface uses a mixture of negative and positive signals for control and data. The terms asserted and negated are used for consistency and are independent of electrical characteristics. In all timing diagrams, the lower line indicates negated, and the upper line indicates asserted. The following illustrates the representation of a signal named Test going from negated to asserted and back to negated, based on the polarity of the signal. ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 17 GL811E USB 2.0 to ATA/ATAPI Bridge Controller 6.4.1 Register Transfers Notes: 1. Device address consists of signals CS0_, CS1_ and DA(2:0). 2. Data consists of IODD(7:0). 3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is to be extended is made by the host after tA from the assertion of DIOR_ or DIOW_. The assertion and negation of IORDY are described as following: 3.1 Device never negates IORDY, devices keeps IORDY released: no wait is generated. 3.2 Device negates IORDY before tA, but causes IORDY to be asserted before tA. IORDY is released prior to negation and may be asserted for no more than 5 ns before release: no wait generated. 3.3 Device negates IORDY before tA, IORDY is released prior to negation and may be asserted for no more than 5 ns before release: wait generated. The cycle completes after IORDY is released. For cycles where a wait is generated and DIOR_ is asserted, the device shall read data on IODD(0:7) for tRD before asserting IORDY. 4. DMACK_ shall remain negated during a register transfer. ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 18 GL811E USB 2.0 to ATA/ATAPI Bridge Controller Register transfer timing parameters t0 t1 t2 t2i t3 t4 t5 t6 t6Z t9 tRD tA tB tC Cycle time Address valid to DIOR_/ DIOW_ setup DIOR_/ DIOW_ pulse width 8-bit DIOR_/ DIOW_ recovery time DIOW_ data setup DIOW_ data hold DIOR_ data setup DIOR_ data hold DIOR_ data tristate DIOR_/ DIOW_ to address valid hold Read Data Valid to IORDY active (if IORDY initially low after tA) IORDY Setup time IORDY Pulse Width IORDY assertion to release (max) Timing (ns) 2000 1000 300 900 80 40 900 - 6.4.2 Multiword DMA data transfer Register transfer timing parameters t0 tD tE tF tG tH tI tJ tKR tKW tLR tLW tM tN tZ Cycle time DIOR_/ DIOW_ asserted pulse width DIOR_ data access DIOR_ data hold DIOR_/ DIOW_ data setup DIOW_ data hold DMACK to DIOR_/ DIOW_ setup DIOR_/ DIOW_ to DMACK hold DIOR_ negated pulse width DIOW_ negated pulse width DIOR_ to DMARQ delay DIOW_ to DMARQ delay CS(1:0) (max) valid to DIOR_/ DIOW_ CS(1:0) hold DMACK_ to read data released Timing (ns) 120 80 40 18 18 20 36 36 36 18 - ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 19 GL811E USB 2.0 to ATA/ATAPI Bridge Controller Note: The host shall not assert DMACK_ or negate both CS0_ and CS1_ until the assertion of DMARQ is detected. The maximum time from the assertion of DMARQ to the assertion of DMACK_ or the negation of both CS0_ and CS1_ is not defined. Figure 6.1 - Initiating a Multiword DMA Data Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 20 GL811E USB 2.0 to ATA/ATAPI Bridge Controller Figure 6.2 - Sustaining a Multiword DMA Data Burst Note: To terminate the data burst, the Device shall negate DMARQ within the tL of the assertion of the current DIOR_ or DIOW_ pulse. The last data word for the burst shall then be transferred by the negation of the current DIOR_ or DIOW_ pulse. If all data for the command has not been transferred, the device shall reassert DMARQ again at any later time to resume the DMA operation. Figure 6.3 - Device Terminating a Multiword DMA Data Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 21 GL811E USB 2.0 to ATA/ATAPI Bridge Controller Note: 1. To terminate the transmission of a data burst, the Host shall negate DMACK_ within the specified time after a DIOR_ or DIOW_ pulse. No further DIOR_ or DIOW_ pulses shall be asserted for this burst. 2. If the device is able to continue the transfer of data, the device may leave DMARQ asserted and wait for the host to reassert DMACK_ or may negate DMARQ at any time after detecting that DMACK_ has been negated. Figure 6.4 - Host terminating a Multiword DMA Data Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 22 GL811E USB 2.0 to ATA/ATAPI Bridge Controller 6.4.3 Ultra DMA data transfer Table 6.7 - Ultra DMA data burst timing requirements Name Mode 0 (in ns) min max Mode 1 (in ns) min max Mode 2 (in ns) min max Mode 3 (in ns) min max Mode 4 (in ns) Min max Comment Typical sustained average two cycle time Cycle time allowing for asymmetry and clock variations Two cycle time allowing for clock variations Data setup time at recipient Data hold time at recipient Data valid setup time at sender Data valid hold time at sender First STORBE time Limited interlock time Interlock time with minimum Unlimited interlock time t2CYCTYP 240 112 230 15 5 70 6 0 0 20 0 10 20 0 20 70 50 75 160 20 0 20 50 230 150 160 73 154 10 5 48 6 0 0 20 0 10 20 0 20 70 30 70 125 20 0 20 50 200 150 120 54 115 7 5 30 6 0 0 20 0 10 20 0 20 70 20 60 100 20 0 20 50 170 150 90 39 86 7 5 20 6 0 0 20 0 10 20 0 20 55 NA 60 100 20 0 20 50 130 100 60 25 57 5 5 6 6 0 0 20 0 10 20 0 20 55 NA 60 100 20 0 20 50 120 100 tCYC t2CYC tDS tDH tDVS tDVH tFS tLI tMLI tUI tAZ tZAH tZAD tENV tSR tRFS tRP tIORDYZ tZIORDY tACK tSS Maximum time allowed for output drivers to release Minimum delay time required for output Drivers to assert or negate Envelope time STROBE to DMARDY_ time Ready to final STROBE time Minimum time to assert STOP or negate DMARQ Maximum time before releasing IORDY Minimum time before driving STROBE Setup and hold times for DMACK_ Time from STROBE edge to negation of DMARQ or assertion of STOP ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 23 GL811E USB 2.0 to ATA/ATAPI Bridge Controller Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are not in efficient until DMARQ and DMACK are asserted. Figure 6.5 - Initiating an Ultra DMA Data-In Burst Notes: IODD(15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device. Figure 6.6 - Sustained Ultra DMA Data-In Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 24 GL811E USB 2.0 to ATA/ATAPI Bridge Controller Notes: 1. The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY_ is negated. 2. If the tSR timing is not satisfied, the host may receive zero, one, or two more data words from the device. Figure 6.7 - Host Pausing an Ultra DMA Data-In Burst Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 6.8 - Device Terminating an Ultra DMA Data-In Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 25 GL811E USB 2.0 to ATA/ATAPI Bridge Controller Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 6.9 - Host Terminating an Ultra DMA Data-In Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 26 GL811E USB 2.0 to ATA/ATAPI Bridge Controller Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. Figure 6.10 - Initiating an Ultra DMA Data-Out Burst Notes: IODD(15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the devicet until some time after they are driven by the host. Figure 6.11 - Sustained Ultra DMA Data-Out Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 27 GL811E USB 2.0 to ATA/ATAPI Bridge Controller Notes: 1. The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY_ is negated. 2. If the tSR timing is not satisfied, the device may receive zero, one, or two more data words from the host. Figure 6.12 - Device Pausing an Ultra DMA Data-Out Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 28 GL811E USB 2.0 to ATA/ATAPI Bridge Controller Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 6.13 - Host terminating an Ultra DMA data-out burst ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 29 GL811E USB 2.0 to ATA/ATAPI Bridge Controller Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 6.14 - Device Terminating an Ultra DMA Data-Out Burst 6.5 AC Characteristics - USB 2.0 The GL811E conforms to all timing diagrams and specifications for Universal Serial Bus specification rev. 2.0. Please refer to this specification for more information. ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 30 GL811E USB 2.0 to ATA/ATAPI Bridge Controller CHAPTER 7 PACKAGE DIMENSION D D1 D2 D A A2 A1 36 37 25 24 Internal No. A N : Normal package G : Green package GL811E B AAAAAAAGAA YWWXXXXXXXX Date Code Lot Code 48 1 e b 4X Version No. 13 12 4X aaa C A B D c bbb H A B D 01 0 ddd M C A B s D s C ccc C SEATING PLANE 02 R1 H R2 GAGE PLANE 0.25mm S L 03 - NOTES : 1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 2. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08mm. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD IS 0.07mm. CONTROL DIMENSIONS ARE IN MILLIMETERS. MILLIMETER INCH SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. A 1.60 0.063 A1 0.05 0.15 0.002 0.006 1.35 A2 1.40 1.45 0.053 0.055 0.057 D 9.00 BASIC 0.354 BASIC E 9.00 BASIC 0.354 BASIC D1 7.00 BASIC 0.276 BASIC E1 7.00 BASIC 0.276 BASIC D2 5.50 BASIC 0.217 BASIC E2 5.50 BASIC 0.217 BASIC R1 0.08 0.003 R2 0.08 0.20 0.003 0.008 0° 3.5° 7° 0° 3.5° 7° 0 -1 0° 0° 0 -2 0 11° 12° 13° 11° 12° 13° -3 0 11° 12° 13° 11° 12° 13° c 0.09 0.20 0.004 0.008 L 0.45 0.60 0.75 0.018 0.024 0.030 L1 1.00 REF 0.039 REF S 0.20 0.008 b 0.17 0.20 0.27 0.007 0.008 0.011 e 0.50 BASIC 0.020 BASIC TOLERANCES OF FORM AND POSITION aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.08 0.003 Figure 7.1 - GL811E 48 Pin LQFP Package ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 31 GL811E USB 2.0 to ATA/ATAPI Bridge Controller D D1 D2 D A A2 A1 48 49 33 32 A InternalNo . N : Normal package G : Green package GL811E B AAAAAAAGAA YWWXXXXXXXX Date Code Lot Code 64 1 e 4X b Version No. 17 16 4X aaa C A B D c bbb H A B D 01 0 ddd M C A B s D s C ccc C SEATING PLANE 02 R1 H R2 0.25mm GAGE PLANE S L 03 - NOTES : 1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 2. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08mm. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD IS 0.07mm. CONTROL DIMENSIONS ARE IN MILLIMETERS. MILLIMETER INCH SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. A 1.60 0.063 A1 0.05 0.15 0.002 0.006 1.35 A2 1.40 1.45 0.053 0.055 0.057 D 12.00 BASIC 0.472 BASIC E 12.00 BASIC 0.472 BASIC D1 10.00 BASIC 0.393 BASIC E1 10.00 BASIC 0.393 BASIC D2 7.50 BASIC 0.295 BASIC E2 7.50 BASIC 0.295 BASIC R1 0.08 0.003 R2 0.08 0.20 0.003 0.008 0 3.5 7 0 3.5 7 0 0 0 01 02 11 12 13 11 12 13 03 11 12 13 11 12 13 c 0.09 0.20 0.004 0.008 L 0.45 0.60 0.75 0.018 0.024 0.030 L1 1.00 REF 0.039 REF S 0.20 0.008 b 0.17 0.20 0.27 0.007 0.008 0.011 e 0.50 BASIC 0.020 BASIC TOLERANCES OF FORM AND POSITION aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.08 0.003 Figure 7.3 - GL811E 64 Pin LQFP Package ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 32 GL811E USB 2.0 to ATA/ATAPI Bridge Controller CHAPTER 8 ORDERING INFORMATION Table 8.1 - Ordering Information Part Number GL811E -MSNXX GL811E -MNNXX GL811E -MSGXX GL811E -MNGXX Package 64-pin LQFP 48-pin LQFP 64-pin LQFP 48-pin LQFP Normal/Green Normal Package Normal Package Green Package Green Package Version XX XX XX XX Status Available Available Available Available ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 33