GL824C

Genesys Logic, Inc. GL824/GL824C USB 2.0 On-The-Go Controller Datasheet Revision 1.06 Nov. 07, 2006 GL824/GL824C USB 2.0 On-The-Go Controller Copyright: Copyright © 2006 Genesys Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic Inc. Disclaimer: ALL MATERIALS ARE PROVIDED “AS IS” WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE. Trademarks: is a registeredd trademark of Genesys Logic, Inc. All trademarks are the properties of their respective owners. Office: Genesys Logic, Inc. 12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel: (886-2) 8913-1888 Fax: (886-2) 6629-6168 http://www.genesyslogic.com ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 2 GL824/GL824C USB 2.0 On-The-Go Controller Revision History Revision 1.00 1.01 1.02 1.03 1.04 1.05 1.06 Date 10/24/2005 02/24/2006 04/19/2006 06/02/2006 07/10/2006 08/15/2006 11/07/2006 First Formal Release 1.Modify External Memory Flash Interface to ATA/ATAPI Interface 2.Change DRVVBUS pin’s description. 3.Change SDRAM Interface to SDRAM/HOST Interface Change flash ROM to reprogrammable flash memory in page10. Modified the timing diagram of host interface Modified the timing diagram and parameter of host interface Modified the timing diagram of host interface Modified the timing diagram of host interface Description ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 3 GL824/GL824C USB 2.0 On-The-Go Controller TABLE OF CONTENTS CHAPTER 1 CHAPTER 2 CHAPTER 3 GENERAL DESCRIPTION................................................. 9 FEATURES ......................................................................... 10 PIN ASSIGNMENT ............................................................ 12 3.1 PINOUT .................................................................................................. 12 3.2 PIN LIST ................................................................................................ 14 3.3 PIN DESCRIPTIONS ................................................................................ 16 CHAPTER 4 CHAPTER 5 BLOCK DIAGRAM............................................................ 24 FUNCTION DESCRIPTION ............................................. 25 5.1 OTG (ON-THE-GO) .............................................................................. 25 5.2 SIE (SERIAL INTERFACE ENGINE) ........................................................ 25 5.3 EPFIFO (ENDPOINT FIFO).................................................................. 25 5.4 SSI (SYNCHRONOUS SERIAL INTERFACE) ............................................. 25 5.4.1 One Byte Receive/Transmit Mode ............................................... 25 5.4.2 Continues Receive/Transmit Data Mode .................................... 26 5.5 UART (UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER) ........ 27 5.6 HOST INTERFACE .................................................................................. 27 CHAPTER 6 ELECTRICAL CHARACTERISTICS.............................. 31 6.1 ABSOLUTE MAXIMUM RATINGS ............................................................ 31 6.2 OPERATING CONDITIONS ...................................................................... 31 6.3 DC CHARACTERISTICS.......................................................................... 31 6.4 PMOS CHARACTERISTICS .................................................................... 32 6.5 AC CHARACTERISTICS.......................................................................... 34 6.5.1 External Flash............................................................................... 34 6.5.2 SmartMedia .................................................................................. 35 6.5.3 xD-Picture ..................................................................................... 36 6.5.4 Memory Stick ............................................................................... 37 6.5.5 Memory Stick PRO ...................................................................... 37 6.5.6 Secure Digital / MultiMedia Card ............................................... 37 6.5.7 CompactFlash Card ..................................................................... 38 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 4 GL824/GL824C USB 2.0 On-The-Go Controller 6.5.8 Reset Timing ................................................................................. 39 6.5.9 ATA/ ATAPI................................................................................. 39 6.5.10 Register Transfers ...................................................................... 41 6.5.11 Multiword DMA data transfer .................................................. 42 6.5.12 Ultra DMA data transfer ........................................................... 46 CHAPTER 7 CHAPTER 8 PACKAGE DIMENSION................................................... 54 ORDERING INFORMATION........................................... 56 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 5 GL824/GL824C USB 2.0 On-The-Go Controller LIST OF FIGURES FIGURE 3.1 - 208 PIN LQFP PINOUT DIAGRAM .............................................................12 FIGURE 3.2 – 128 PIN LQFP PINOUT DIAGRAM.............................................................13 FIGURE 4.1 - GL824 BLOCK DIAGRAM ..........................................................................24 FIGURE 5.1 - ONE BYTE RECEIVE/TRANSMIT TIMING DIAGRAM (CLOCK OPPOSITE)...26 FIGURE 5.2 - ONE BYTE RECEIVE/TRANSMIT TIMING DIAGRAM (CLOCK NORMAL).......26 FIGURE 5.3 - CONTINUES RECEIVE/TRANSMIT DATA TIMING DIAGRAM (CLOCK OPPOSITE) ......................................................................................................................26 FIGURE 5.4 - CONTINUES RECEIVE/TRANSMIT DATA TIMING DIAGRAM (CLOCK NORMAL)........................................................................................................................26 FIGURE 5.5 - DATA FRAME.............................................................................................27 FIGURE 5.6 - COMMAND WRITE TIMING DIAGRAM .......................................................28 FIGURE 5.7 - STATUS READ TIMING DIAGRAM ..............................................................28 FIGURE 5.8 - DATA WRITE TIMING DIAGRAM ...............................................................29 FIGURE 5.9 - DATA READ TIMING DIAGRAM .................................................................29 FIGURE 6.1 – EMBEDDED PMOS SWITCH ARCHITECTURE............................................32 FIGURE 6.2 – I-V CURVE OF PMOS SWTICH .................................................................33 FIGURE 6.3 – TRANSIENT ANALYSIS OF PMOS SWITCH ................................................34 FIGURE 6.4 – TIMING DIAGRAM OF EXTERNAL FLASH ..................................................34 FIGURE 6.5 - TIMING DIAGRAM OF SMARTMEDIA .........................................................35 FIGURE 6.6 - TIMING DIAGRAM OF XD-PICTURE ...........................................................36 FIGURE 6.7 - TIMING DIAGRAM OF MEMORYSTICK ......................................................37 FIGURE 6.8 - TIMING DIAGRAM OF MEMORYSTICK PRO..............................................37 FIGURE 6.9 - TIMING DIAGRAM OF SD / MMC ..............................................................37 FIGURE 6.10 - TIMING DIAGRAM OF COMPACTFLASH ...................................................38 FIGURE 6.11 - TIMING DIAGRAM OF RESET ...................................................................39 FIGURE 6.12 – REGISTER TRANSFERS TIMING ...............................................................41 FIGURE 6.13 - INITIATING A MULTIWORD DMA DATA BURST ......................................43 FIGURE 6.14 - SUSTAINING A MULTIWORD DMA DATA BURST .....................................44 FIGURE 6.15 - DEVICE TERMINATING A MULTIWORD DMA DATA BURST ....................44 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 6 GL824/GL824C USB 2.0 On-The-Go Controller FIGURE 6.16 - HOST TERMINATING A MULTIWORD DMA DATA BURST ........................45 FIGURE 6.17 - INITIATING AN ULTRA DMA DATA-IN BURST .........................................47 FIGURE 6.18 - SUSTAINED ULTRA DMA DATA-IN BURST ..............................................47 FIGURE 6.19 - HOST PAUSING AN ULTRA DMA DATA-IN BURST ...................................48 FIGURE 6.20 - DEVICE TERMINATING AN ULTRA DMA DATA-IN BURST.......................48 FIGURE 6.21 - HOST TERMINATING AN ULTRA DMA DATA-IN BURST ..........................49 FIGURE 6.22 - INITIATING AN ULTRA DMA DATA-OUT BURST .....................................50 FIGURE 6.23 - SUSTAINED ULTRA DMA DATA-OUT BURST...........................................50 FIGURE 6.24 - DEVICE PAUSING AN ULTRA DMA DATA-OUT BURST ............................51 FIGURE 6.25 - HOST TERMINATING AN ULTRA DMA DATA-OUT BURST.........................52 FIGURE 6.26 - DEVICE TERMINATING AN ULTRA DMA DATA-OUT BURST ...................53 FIGURE 7.1 - GL824 208 PIN LQFP PACKAGE ..............................................................54 FIGURE 7.2 - GL824C 128 PIN LQFP PACKAGE............................................................55 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 7 GL824/GL824C USB 2.0 On-The-Go Controller LIST OF TABLES TABLE 3.1 -GL824 208 PIN LQFP PIN LIST ..................................................................14 TABLE 3.2 – GL824C 128-PIN LQFP PIN LIST ..............................................................15 TABLE 3.3 – GL824 208 PIN DESCRIPTIONS...................................................................16 TABLE 3.4 – GL824C 128 PIN DESCRIPTIONS ................................................................20 TABLE 5.1 - AC CHARACTERISTICS ...............................................................................27 TABLE 5.2 - HOST INTERFACE AC CHARACTERISTICS ..................................................29 TABLE 6.1 - ABSOLUTE MAXIMUM RATINGS .................................................................31 TABLE 6.2 - OPERATING CONDITIONS ............................................................................31 TABLE 6.3 - DC CHARACTERISTICS ...............................................................................31 TABLE 6.4 – PMOS CHARACTERISTICS .........................................................................32 TABLE 6.5 - ULTRA DMA DATA BURST TIMING REQUIREMENTS ....................................46 TABLE 8.1 - ORDERING INFORMATION...........................................................................56 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 8 GL824/GL824C USB 2.0 On-The-Go Controller CHAPTER 1 GENERAL DESCRIPTION The GL824/824C USB On-The-Go (OTG) Dual-Role-Device controller which include Milti-I/F and ATA/ATAPI interface is a highly integral microprocessor, which optimized and specially designed for embedded system, portable device, multi-function peripheral and consumer products with External uP interface, SSI, I2C and Flash cards interface.Using the GL824, developers can create OTG-compliant dual-role products capable of point-to-point communication. Its focus on power efficiency makes the GL824 ideal for set top box, DVD player, PDA, PMP, Digital TV and home entertainment with USB OTG and Flash card reader. The GL824/GL824C had USB 2.0 Multi-I/F and SD/MMC/MS/MSPro Interface Flash Card Reader Controller. It supports USB 2.0 high-speed transmission to: CompactFlash TM (CF) Type I/II, Micro Drive, Secure DigitalTM (SD), Mini SDTM, MultiMediaCardTM (MMC), RS MultiMediaCardTM (RS MMC), HS-MMC, MMC-Mobile, Memory StickTM (MS), Memory Stick DuoTM (MS Duo), High Speed Memory StickTM (HS MS), Memory Stick ProTM (MS Pro), Memory Stick ProTM Duo (MS Pro Duo) Memory Stick ROM, SmartMediaTM (SM) 5V/3.3V, and xD-Picture Card TM (xD) on one chip (GL824C are SD/MMC/MS/MSPro I/F only). The GL824/GL824C also embeds a powerful 8-bit MCU engine to handle the operations among the USB host, peripheral, OTG and ATA/ATAPI controllers. Provide flexibility Card-to-HDD, HDD-to-Card, USB-to-HDD, HDD-to-USB, USB-to-Card and Card-to-USB multi-path copy back bridge. ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 9 GL824/GL824C USB 2.0 On-The-Go Controller CHAPTER 2 • - FEATURES USB OTG Controller Compliant with USB specification Rev. 2.0 at high-speed and full-speed data transfer rate Compliant with On-The-Go (OTG) supplement Rev. 1.0 Complies with USB Storage Class specification rev. 1.0 Support Suspend, Resume, HNP and SRP External source to drive Vbus signal Supports 1 device address and up to 4 endpoints: Control (0)/ Bulk Read (1)/ Bulk Write (2)/Interrupt (3). • Integrated USB building blocks USB2.0 transceiver macro (UTM), Serial Interface Engine (SIE), Build-in power-on reset (POR) and low-voltage detector (LVD) • Embedded 8051 micro-controller Operate @ 60 MHz clock, 1 clocks per instruction cycle Embedded 64K*2 Byte reprogrammable flash memory and internal 256 byte SRAM Embedded 8K Byte external SRAM • • • • Support power saving mode Support firmware upgrade via USB and external serial flash memory On-Chip power MOSFETs for supplying flash media card power except Compact Flash. (GL824 only) Interface Support external SDRAM interface (option) Support 16bit host interface (Support external uP Read/Write Status/Command and Read/Write FIFO) (option) Supports ATA/ATAPI interface Support serial MP3 decoder interface Support serial LCD Panel interface Support memory cards interface Support SSI interface for master and slave mode up to 15MHz Support I2C interface - Support UART interface • ATA/ATAPI interface Complies with ATA/ATAPI-6 specification rev 1.0 Support 16-bit Multiword DMA mode and Ultra DMA mode interface (Ultra 33/66) • CompactFlashTM interface ( GL824 only ) Support CFA specification v2.1 / v3.0 Support True IDE mode Support 8 / 16 bit data mode and different timing Page 10 ©2000-2006 Genesys Logic Inc. - All rights reserved. GL824/GL824C USB 2.0 On-The-Go Controller • xD-Picture Interface (GL824 only) xD-Picture specification v1.2B xD-Picture Type M card support • SmartMediaTM interface ( GL824 only ) 8 bit data width and different speed Support different page size, and automatic append redundant area data (8 / 16 bytes) • MemoryStickTM / MemoryStick Pro interface Compliant with MemoryStick interface specification Support INS signal Support automatic CRC16 generation and verification • Secure DigitalTM and MultiMediaCardTM Compliant with Secure Digital / MMC interface specification Supports both SD / MMC mode access CLK/CMD/DAT0/DAT1/DAT2/DAT3/DAT4/DAT5/DAT6/DAT7 - Supports SD specification v1.0 / v1.1 - Supports MMC specification v4.0 / v4.1 x1 / x4 / x8 data transmission Automatic CRC7 generation for command and CRC7 verification for response on CMD Support automatic CRC16 generation and verification on DAT0:7 In addition to full packet transaction, optional single byte / bit operation on both CMD and DAT line / lines - Process data in block or byte • High efficient hardware engine Automatic data read / write with card by hardware engine Easier firmware development • • On board 24Mhz Crystal driver circuit Available in 208-pin LQFP 24x24 mm package, support all card interface with external Flash/Serial Interface for MP3 Decoder/2Pins Serial Interface LCD panel/ATA(ATAPI)/SDRAM(Host Interface) ( GL824 ) • Available in 128-pin LQFP 14x14 mm package, Support SD/MMC/MS/MSPro card interface/Serial Interface for MP3 Dcecoder (Only support Serial Data/Control interface in the same pins)/ATA(ATAPI)/SDRAM(Host Interface) ( GL824C ) ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 11 3.1 Pinout CHAPTER 3 PIN ASSIGNMENT ©2000-2006 Genesys Logic Inc. - All rights reserved. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 DQM XD_CDZ CA S_CS_ SM_CLE CK O SM_WPDZ RA S_/RE_ SM_CDZ CK E CF SM_D3 SA12 CF SM_D11 SA11 CF SM_D4 BA 0/WSTS CF SM_D12 SA9 BA 1/RSTS SA8 SA10 SA0/A0 SA7 SA6 SA1 SA5 SA2 SA4 SA3 PVCC PGND CG ND CV CC CF SM_D5 CF SM_D13 ARES ET_ CF SM_D6 DD7 CF SM_14 DD8 CF SM_D7 DD6 CF SM_D15 DD9 CF _CS0Z DD5 CF _CS1Z DD1 0 CF _IORZ DD4 CF _IOWZ DD1 1 INTRQ Figure 3.1 - 208 Pin LQFP Pinout Diagram GPIO5 GPIO6 GPIO7 BSYNC DREQ DCLK SD ATA SSICLK SSIDI SS IDO CV CC CGND PGND PV CC S D_CDZ SD_WP Z SD_D1 SD_D0 S D_CLK SD_CMD SD_D3 SD_D2 GP IO1/SD_D4 GP IO2/SD_D5 GP IO3/SD_D6 GP IO4/SD_D7 MS_BS MS_D1 MS_D0 MS_D2 MS_INS MS_D3 MS _CLK DRV VBUS VDD ID VSS AVS S1A VBUS RREF AGND3 AVDD3 DVDD1 DGND1 GNDS AGND1 AGND1 DP DM AVDD1 RVO RVDD GL824/GL824C USB 2.0 On-The-Go Controller Page 12 ©2000-2006 Genesys Logic Inc. - All rights reserved. DCLK SDATA SSIDI CVCC CGND PVCC SD_D1 SD_D0 SD_CLK SD_CMD SD_D3 SD_D2 MS_BS MS_D1 MS_D0 MS_D2 MS_INS MS_D3 M S_CLK DRVVBU VDD ID VSS VBUS RREF AGND3 AVDD3 DGND1 GNDS DP DM AVDD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 DQM CAS_/CS_ CKO RAS_/RE_ CKE SA12 SA11 BA0/WSTS SA9 BA1/RSTS SA8 SA10 SA0/A0 SA7 SA6 SA1 SA5 SA2 SA4 SA3 PVCC CGND CVCC ARESET_ DD7 DD8 DD6 DD9 DD5 DD10 DD4 DD11 Figure 3.2 – 128 Pin LQFP Pinout Diagram GL824/GL824C USB 2.0 On-The-Go Controller Page 13 GL824/GL824C USB 2.0 On-The-Go Controller 3.2 Pin List Table 3.1 -GL824 208 Pin LQFP Pin List Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type 1 GPIO5(ISP) B 53 RVSS P 105 INTRQ I 157 NC 2 GPIO6 B 54 PGND P 106 DD11 B 158 SM_ALE O 3 4 5 6 7 8 9 GPIO7 BSYNC DREQ DCLK SDATA SSICLK SSIDI B B B O B B B B P P P P B B B B O B B B B B B B O B B B B B O O P I 55 X2 56 X1 57 PVCC 58 PIO1 59 PIO2 60 PIO3 61 PIO4 62 TEST 63 EXTRST_ 64 CF_CDZ 65 CS0_ 66 CFSM_D10 67 DA0 68 CFSM_D9 69 DA2 70 CFSM_D2 71 DA1 72 PMOSI1 73 PMOSO1 74 PMOSI2 75 PMOSO2 76 PVCC 77 PGND 78 CGND 79 CVCC 80 AINTRQ 81 DMACK_ 82 AIORDY 83 DIOR_ 84 DIOW_ 85 DMARQ 86 CS1_ 87 CFSM_D8 88 DD15 O I P B B B B I I B O B O B O B O I O I O P P P P I O I O O I O B B 107 C_IOWZ 108 DD4 109 CF_IORZ 110 DD10 111 CF_CS1Z 112 DD5 113 CF_CS0Z 114 DD9 115 CFSM_D15 116 DD6 117 CFSM_D7 118 DD8 119 CFSM_D14 120 DD7 121 CFSM_D6 122 ARESET_ 123 CFSM_D13 124 CFSM_D5 125 CVCC 126 CGND 127 PGND 128 PVCC 129 SA3 130 SA4 131 SA2 132 SA5 133 SA1 134 SA6 135 SA7 136 SA0/A0 137 SA10 138 SA8 139 BA1/RSTS 140 SA9 O B O B O B O B B B B B B B B B B B P P P P O O O O O O O O O O O 159 WE_/WE_ 160 SM_REZ 161 DQ8 162 SM_WEZ 163 DQ7 164 SM_RBZ 165 DQ9 166 SM_WPZ 167 DQ6 168 SM_D0 169 DQ10 170 SM_D1 171 DQ5 172 SM_D7 173 DQ11 174 SM_D2 175 DQ4 176 SM_D6 177 DQ12 178 SM_D3 179 DQ3 180 SM_D5 181 DQ13 182 SM_D4 183 DQ2 184 DQ14 185 DQ1 186 DQ15 187 DQ0 189 CGND 190 PGND 191 PVCC 192 PMOSI3 O/I O B O B B B B B B B B B B B B B B B B B B B B B B B B B P P P P I 10 SSIDO 11 CVCC 12 CGND 13 PGND 14 PVCC 15 SD_CDZ 16 SD_WPZ 17 SD_D1 18 SD_D0 19 SD_CLK 20 SD_CMD 21 SD_D3 22 SD_D2 GPIO1/ 23 MMC_D4 GPIO2/ 24 MMC_D5 GPIO3/ 25 MMC_D6 GPIO4/ 26 MMC_D7 27 MS_BS 28 MS_D1 29 MS_D0 30 MS_D2 31 MS_INS 32 MS_D3 33 MS_CLK 34 DRVVBUS 35 VDD 36 ID O/I 188 CVCC ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 14 GL824/GL824C USB 2.0 On-The-Go Controller 37 VSS 38 AVSSA 39 VBUS 40 RREF 41 AGND 42 AVDD 43 DVDD 44 DGND 45 GNDS 46 AGND1 47 AGND1 48 DP 49 DM 50 AVDD 51 RVO 52 RVDD P P I B P P P P P P P A A P O I 89 CFSM_D1 90 DD0 91 CFSM_D0 92 DD14 93 CF_A0 94 DD1 95 CF_A1 96 DD13 97 CF_A2 98 DD2 99 IORDY 100 DD12 101 CF_RST 102 DD3 103 NC 104 NC B B B B O B O B O B I B B B 141 CFSM_D12 142 BA0/WSTS 143 CFSM_D4 144 SA11 145 CFSM_D11 146 SA12 147 CFSM_D3 148 CKE 149 SM_CDZ 150 RAS_/RE_ 151 SM_WPDZ 152 CKO 153 SM_CLE 154 CAS_/CS_ 155 XD_CDZ 156 DQM B O B O B O B O B B O O B O 193 PMOSO3 194 PMOSI4 195 PMOSO4 196 RXD 197 TXD 198 PIO5 199 PIO6 200 PIO7 O I O B O B B B B O B B P I I P 201 PIO8 O/I 202 I2CK 203 I2CD 204 GPIO8 205 VSSA 207 VBAT 208 VDDA O/I 206 VSEL Table 3.2 – GL824C 128-Pin LQFP Pin List Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type 1 DCLK O 33 RVO O 65 DD11 B 97 WE O/I 2 3 4 5 6 7 8 9 SDATA SSIDI CVCC CGND PVCC SD_D1 SD_D0 SD_CLK B B P P P B B O B B B O B B B B B O O P 34 RVDD 35 RVSS 36 X2 37 X1 38 PVCC 39 PIO1 40 PIO2 41 TEST 42 EXTRST_ 43 CS0 44 DA0 45 DA2 46 DA1 47 PVCC 48 PGND 49 CVCC 50 AINTRQ 51 DMACK_ 52 AIORDY 53 DIOR_ I P O I P B B I I O O O O P P P I O I O 66 DD4 67 DD10 68 DD5 69 DD9 70 DD6 71 DD8 72 DD7 73 ARESET_ 74 CVCC 75 CGND 76 PVCC 77 SA3 78 SA4 79 SA2 80 SA5 81 SA1 82 SA6 83 SA7 84 SA0/A0 85 SA10 B B B B B B B O P P P O O O O O O O O 98 DQ8 99 DQ7 100 DQ9 101 DQ6 102 DQ10 103 DQ5 104 DQ11 105 DQ4 106 DQ12 107 DQ3 108 DQ13 109 DQ2 110 DQ14 111 DQ1 112 DQ15 113 DQ0 114 CVCC 115 CGND 117 RXD B B B B B B B B B B B B B B B B P P P B Page 15 10 SD_CMD 11 SD_D3 12 SD_D2 13 MS_BS 14 MS_D1 15 MS_D0 16 MS_D2 17 MS_INS 18 MS_D3 19 MS_CLK 20 DRVVBUS 21 VDD O/I 116 PVCC ©2000-2006 Genesys Logic Inc. - All rights reserved. GL824/GL824C USB 2.0 On-The-Go Controller 22 ID 23 VSS 24 VBUS 25 RREF 26 AGND3 27 AVDD3 28 DGND1 29 AGND1 30 DP 31 DM 32 AVDD1 I P I B P P P P B B P 54 DIOW_ 55 DMARQ 56 CS1 57 DD15 58 DD0 59 DD14 60 DD1 61 DD13 62 DD2 63 DD12 64 DD3 O I O B B B B B B B B 86 SA8 87 BA1/RSTS 88 SA9 89 BA0/WSTS 90 SA11 91 SA12 92 CKE 93 RAS_/RE_ 94 CKO 95 CAS_/CS_ 96 DQM O O O O O O O O O 118 TXD 119 PIO5 120 I2CK 121 I2CD 122 GPIO8 123 VSSA 124 VSEL 126 VDDA 128 DREQ O B O B B P I I P B B O/I 125 VBAT O/I 127 BSYNC 3.3 Pin Descriptions Table 3.3 – GL824 208 Pin Descriptions USB Interface Pin Name GPIO5(ISP) GPIO6 GPIO7 BYYNC DREQ DCLK SDATA SSICLK SSIDI SSIDO DRVVBUS ID VBUS RREF DP DM PIO1~8 Test Pin# 1 2 3 4 5 6 7 8 9 10 34 36 39 40 48 49 58~61, 198~201 62 Type B (pu) B (pu) B (pu) B (pd) B (pd) O (pd) B (pd) B (pd) B (pd) B (pd) O I I B B B B (pd) I (pd) Description General Purpose I/O 5 (In System Programming) General Purpose I/O 6 General Purpose I/O 7 Byte synchronization signal (for MP3 decoder I/F) Data request input (for MP3 decoder I/F) Serial output data bus clock (for MP3 decoder I/F) Serial output data (for MP3 decoder I/F) Synchronous Serial Clock Output Synchronous Serial data input Synchronous Serial data output Drive VBUS on control output pin ID VBUS Reference resistor USB D+ USB DProgrammable I/O #1~#8 Test pin ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 16 GL824/GL824C USB 2.0 On-The-Go Controller I (pd) B (pu) O (pu) O (pu) B (pu) I I EXTRST_ RXD TXD I2CK I2CD VSEL VBAT 63 196 197 202 203 206 207 External reset UART receives data input UART transmits data output I2C bus clock I2C data Key voltage detection input Battery voltage detection input ATA/ATAPI Interface Pin Name CS0_ CS1_ DA0~2 AINTRQ DMACK_ AIORDY DIOR_ DIOW_ DMARQ Pin# 65 86 67,71,69 80 81 82 83 84 85 90,94,98,102, Type O O O I (pd) O I (pu) O O I (pd) B (pd) O PESETZ (PCVS2Z) PESETZ (PCVS1Z) Address 0~2 Description IREQZ DMACK IORDY (WAITZ) I/O read strobe I/O write strobe DMARQ DD0~15 108,112,116, 120,118,114, 110,106,100, Data 0~15 ARESET_ 96,92,88 122 ARESET SDRAM/Host Interface Pin Name SA1~12 Pin# 133,131,129, 130,132,134, 135,138,140, 137,144,146 136 142 139 148 150 Type O O/I (pd) SDRAM_A1~A12 Description SA0/A0 BA0/WSTS SDRAM_A0 / share pin with A0 pin of HOST interface SDRAM_BA0 / share pin with write status pin of HOST interface SDRAM_BA1 / share pin with read status pin of HOST interface SDRAM_CKE SDRAM_RAS / share pin with read enable pin of HOST interface Page 17 BA1/RSTS CKE RAS_/RE_ O O O/I (pu) ©2000-2006 Genesys Logic Inc. - All rights reserved. GL824/GL824C USB 2.0 On-The-Go Controller CKO CAS_/CS_ DQM WE_/WE_ 152 154 156 159 187,185,183, 179,175,171, 167,163,161, 165,169,173, 177,181,184, O O/I (pu) O O/I (pu) B (pd) Clock SDRAM_CAS / Share pin with chip select pin of HOST interface SDRAM_UDQM Write enable / Share pin with write enable pin of HOST interface SDRAM_D0~D15 / Share pin with Data0~15 bus of HOST interface DQ0~15 186 CompactFlash / MicroDrive Interface Pin Name CF_CDZ Pin# 64 91,89,70,147, Type B (pu) B (pd) O I (pu) B (pd) I (pd) O O O O Description Card detection 143,124,121, CFSM_D0~15 CF_A0~2 IORDY CF_RST INTRQ CF_IOWZ 117,87,68, 66,145,141, 123,119,115 93,95,97 99 101 105 107 109 111 113 Data bus 0~15 Address 0~2 I/O read stobe Reset INTRQ I/O write strobe I/O read strobe CS1Z CS0Z CF_IORZ CF_CS1Z CF_CS0Z SmartMeia / xD-Picture Card / NAND Flash Memory Interface Pin Name SM_CDZ SM_WPDZ SM_CLE XD_CDZ SM_ALE SM_REZ SM_WEZ SM_RBZ Pin# 149 151 153 155 158 160 162 164 Type B (pu) B (pu) O B (pu) O O O B (pu) Description Card detection Write Protect Detect Command latch enable Card detection Address latch enable Read enable Write enable Read/Busy Page 18 ©2000-2006 Genesys Logic Inc. - All rights reserved. GL824/GL824C USB 2.0 On-The-Go Controller B (pu) B (pd) SM_WPZ SM_D0~7 166 168,170,174, 178,182,180, Write Protect Detect Address 0~7 176,172 SecureDigital / MultiMediaCard Interface Pin Name SD_CDZ SD_WPZ SD_D0~3 MMC_D4~7 SD_CLK SD_CMD Pin# 15 16 18,17,22,21, 23~26 19 20 Type B (pu) B (pu) B (pu) O B (pu) Description Card detection# Write Protect Detection Data 0~7 SD/MMC clock SD/MMC command and response Memory Stick Pro / Memory Stick Interface Pin Name MS_BS MS_D0~3 MS_INS MS_CLK Pin# 27 29,28,30,32 31 33 Type O B (pd) B (pu) O Bus state Data 0~3 Card detection Description Clock Miscellaneous Interface Pin Name GPIO1~8 NC Pin# 23~26,1~3, 204 103,104,157 Type B (pu) Description General Purpose I/O #1~#8 No connection Power / Ground Pin Name CVCC CGND PGND PVCC VDD Pin# 11,79,125, 188 12,78,126, 189 13,77,127, 190 14,76,128, 191 35 37 38 41 Type P P P P P P P P Core power 2.5V Core Ground Pad ground Pad power 3.3V Description Digital circuit power 2.5V Digital circuit ground AVSSA Analog ground #3 Page 19 VSS AVSSA AGND ©2000-2006 Genesys Logic Inc. - All rights reserved. GL824/GL824C USB 2.0 On-The-Go Controller AVDD DVDD DGND GNDS AGND AGND AVDD RVO RVDD RVSS PGND X2 X1 PVCC PMOSI1~4 PMOSO1~4 VSSA VDDA 42 43 44 45 46 47 50 51 52 53 54 55 56 57 72,74,192, 194 73,75,,193, 195 205 208 P P P P P P P P P P P P P P I O P P Analog power#3 Digital power #1 Digital ground #1 Ground Analog ground #1 Analog ground #1 Analog power 2.5V regulator output 2.5V regulator power 2.5V regulator ground 24MHz crystal ground 24MHz crystal output 24MHz crystal input 24MHz crystal power 3.3V PMOS #1~#4 input 3.3V PMOS #1~#4 output 3.3V ADC ground ADC 3.3V power Table 3.4 – GL824C 128 Pin Descriptions USB Interface Pin Name BYYNC DREQ DCLK SDATA SSIDI DRVVBUS ID VBUS RREF DP DM PIO1 Test Pin# 127 128 1 2 3 20 22 24 25 30 31 39 41 Type B (pd) B (pd) O (pd) B (pd) B (pd) O I I B B B B (pd) I (pd) Description Byte synchronization signal (for MP3 decoder I/F) Data request input (for MP3 decoder I/F) Serial output data bus clock (for MP3 decoder I/F) Serial output data (for MP3 decoder I/F) Synchronous Serial data input Drive VBUS on control output pin ID VBUS Reference resistor USB D+ USB DProgrammable I/O #1 Test pin ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 20 GL824/GL824C USB 2.0 On-The-Go Controller I (pd) B (pu) O (pu) O (pu) B (pu) I I EXTRST_ RXD TXD I2CK I2CD VSEL VBAT 42 117 118 120 121 124 125 External reset UART receives data input UART transmits data output I2C bus clock I2C data Key voltage detection input Battery voltage detection input ATA/ATAPI Interface Pin Name CS0_ CS1_ DA0~2 AINTRQ DMACK_ AIORDY DIOR_ DIOW_ DMARQ Pin# 43 56 44,46,45 50 51 52 53 54 55 58,60,62,64, Type O O O I (pd) O I (pu) O O I (pd) B (pd) O PESETZ (PCVS2Z) PESETZ (PCVS1Z) Address 0~2 Description IREQZ DMACK IORDY (WAITZ) I/O read strobe I/O write strobe DMARQ DD0~15 66,68,70, 72,71,69, 67,65,63, Data 0~15 ARESET_ 61,59,57 73 ARESET SDRAM Interface Pin Name SA1~12 Pin# 81,79,77, 78,80,82, 83,86,88, 85,90,91 84 89 87 92 93 Type O O/I (pd) SDRAM_A1~A12 Description SA0/A0 BA0/WSTS SDRAM_A0 / share pin with A0 pin of HOST interface SDRAM_BA0 / share pin with write status pin of HOST interface SDRAM_BA1 / share pin with read status pin of HOST interface SDRAM_CKE SDRAM_RAS / share pin with read enable pin of HOST interface Page 21 BA1/RSTS CKE RAS_/RE_ O O O/I (pu) ©2000-2006 Genesys Logic Inc. - All rights reserved. GL824/GL824C USB 2.0 On-The-Go Controller CKO CAS_/CS_ DQM WE_/WE_ 94 95 96 97 113,111,109, 107,105,103, 101,99,98, 100,102,104, 106,108,110, O O/I (pu) O O/I (pu) B (pd) Clock SDRAM_CAS / Share pin with chip select pin of HOST interface SDRAM_UDQM Write enable / Share pin with write enable pin of HOST interface SDRAM_D0~D15 / Share pin with Data0~15 bus of HOST interface DQ0~15 112 SecureDigital / MultiMediaCard Interface Pin Name SD_CDZ SD_WPZ SD_D0~3 SD_CLK SD_CMD Pin# 119 40 8,7,12,11, 9 10 Type B (pu) B (pu) B (pu) O B (pu) Description Card detection# Write Protect Detection Data 0~3 SD/MMC clock SD/MMC command and response Memory Stick Pro / Memory Stick Interface Pin Name MS_BS MS_D0~3 MS_INS MS_CLK Pin# 13 15,14,13,18 17 19 Type O B (pd) B (pu) O Bus state Data 0~3 Card detection Description Clock Miscellaneous Interface Pin Name GPIO8 Pin# 122 Type B (pu) Description General Purpose I/O #8 Power / Ground Pin Name CVCC CGND PVCC VDD Pin# 4,49,74, 114 5,48,75, 115 6,47,76, 116 21 Type P P P P Core power 2.5V Core Ground Pad power 3.3V Description Digital circuit power 2.5V Page 22 ©2000-2006 Genesys Logic Inc. - All rights reserved. GL824/GL824C USB 2.0 On-The-Go Controller VSS AGND AVDD DGND GNDS AVDD RVO RVDD RVSS X2 X1 PVCC VSSA VDDA 23 26 27 28 29 32 33 34 35 36 37 38 123 126 P P P P P P P P P P P P P P Digital circuit ground Analog ground #3 Analog power#3 Digital ground #1 Ground Analog power 2.5V regulator output 2.5V regulator power 2.5V regulator ground 24MHz crystal output 24MHz crystal input 24MHz crystal power 3.3V ADC ground ADC 3.3V power Notation: Type O I B B/I B/O P A pu pd odpu Output Input Bi-directional Bi-directional, default input Bi-directional, default output Power / Ground Analog Internal pull up Internal pull down Open drain with internal pull up ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 23 GL824/GL824C USB 2.0 On-The-Go Controller CHAPTER 4 BLOCK DIAGRAM DP DM OTG Physical/Logic Controller SIE ATAPI Interface ATAPI Interface SDRAM Interface MCU 8051 PLL /RST Reset Voltage Regulator EPFIFO HOST Interface 16- bit bus Share Pin Interface 60 MHz Internal Reset Internal Power RAM Flash ROM UART Interface Flash Cards Interface I2C Interface SSI Interface VCC Flash Cards Interface Figure 4.1 - GL824 Block Diagram Figure 4.2 - GL824 System Block Diagram ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 24 GL824/GL824C USB 2.0 On-The-Go Controller CHAPTER 5 FUNCTION DESCRIPTION 5.1 OTG (On-The-Go) A dual-role OTG device that has the following features and characteristics: •Liminted Hos capability •High/Full-speed operation as peripheral •High/Full-speed support as host •Targeted Peripheral List •Session Request Protocol •Host Negotiation Protocol •One Mini-AB receptacle •Minimum 8mA output on VBUS 5.2 SIE (Serial Interface Engine) The Serial Interface Engine, which contains the USB PID and address recognition logic, and other sequencing and state machine logic to habdle USB packets and transactions. 5.3 EPFIFO (Endpoint FIFO) Endpoint FIFO includes Control FIFO (FIFO0), Interrupt FIFO (FIFO3) and Bulk In/Out FIFO (BULKFIFO). •Control FIFO •Interrupt FIFO •Bulk In/Out FIFO It can be in the TX mode or RX mode: FIFO of control endpoint 0. It is 64-bytes FIFO, and it is used for endpoint 0 data transfer. 64-bytes depth FIFO of endpoint 3 for status interrupt. a. It contains ping-pong FIFO (512 bytes each bank) for transmit/receive data continuously. b. It can be directly accessed by Uc. c. Support automatic hardware SmartMedia ECC error correction. 5.4 SSI (Synchronous Serial Interface) The Synchronous Serial Interface provides serial data in and out for communication with serial fingerprint sensor The SSI uses following pins: SSICLK, SSIDO and SSIDI. SSICLK: SSIDO: SSIDI: Synchronous Serial Interface Clock Synchronous Serial Interface Data Output Synchronous Serial Interface Data Input 5.4.1 One Byte Receive/Transmit Mode GL824 provides a programmable synchronous serial interface. The SSI not only supports both clock normal and clock opposite phases but also supports MSB or LSB data formats. One Byte Receive/Transmit timing diagram see Figure 5.1 ~ Figure 5.2. User can read/write register/command from/to fingerprint sensor in this mode. ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 25 GL824/GL824C USB 2.0 On-The-Go Controller Figure 5.1 - One Byte Receive/Transmit Timing Diagram (Clock Opposite) tWL tWH SSICLK SSIDO SSIDI D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 tSU tH tV Figure 5.2 - One Byte Receive/Transmit timing diagram (clock normal) 5.4.2 Continues Receive/Transmit Data Mode For fingerprint sensor application, GL824 gets image row/column data by continues receive mode. Figure 5.3 shows the data receive timing diagram. The SSICLK clock rate can be configured by DIV register. Figure 5.3 - Continues Receive/Transmit Data timing diagram (clock opposite) Figure 5.4 - Continues Receive/Transmit Data timing diagram (clock normal) ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 26 GL824/GL824C USB 2.0 On-The-Go Controller Table 5.1 - AC Characteristics Symbol tWL tWH tSU tH tV Clock Low Time Clock High Time Data Setup Time Data Hold Time Data Valid Time Parameter Min. 35 35 1/2 * tWL 3/4 * tWL 1/4 * tWL Max. Unit ns ns ns ns ns 5.5 UART (Universal Asynchronous Receiver/Transmitter) GL824 has three 16-bit timers/counters that are same as the timer of the standard 8052 family up to 921.6Kbps. The serial port has three asynchronous modes of operation. For fingerprint sensor application, the data frame consists of 10 bits: one start bit, eight data bits and one stop bit. Serial data is transmitted on the TxD pin and received on the RxD pin. The data frame shows in Figure 5.5. D0 D1 D2 D3 D4 D5 D6 D7 D8 Data Byte Start Bit Ninth Data Bit (Modes 2 and 3 only) Figure 5.5 - Data Frame Stop Bit 5.6 Host Interface l Pin Description /CS: Chip Select and active low. A0: Command/Status and Data select. When A0 is high, GL824 is operation at Command Write and Status Read mode. When A0 is low, GL824 is operation at continues data receive/transfer mode. /RE: Read Enable; Active low. GL824 read frequency must lower than 30 MHz. /WE: Write Enable; Active low. Write frequency must lower than 30 MHz. Data[0:15]: 16 bit Data bus WSTS: Command/Data Write Status. When WSTS is high, it indicated that GL824 is ready for HOST write command/data. RSTS: Command/Data Read Status. When RSTS is high, it indicated that GL824 is ready for HOST read data/status. ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 27 GL824/GL824C USB 2.0 On-The-Go Controller l Command Write Command, address and data are all written through Data[0:15] port by bring /WE to low, while A0 is high and WSTS also pull high, it indicated that GL824 is ready for HOST write command. When /CS is low, command is latched on the rising edge of /WE. When WSTS goes low it indicates that Command is latched into command register by GL824. Figure 5.6 - Command Write Timing Diagram l Status Read Register status, address and data can be read through Data[0:15] port by bring RE to low, while A0 is high and RSTS also return high, it indicated that GL824 is ready for HOST read status. When /CS is low. Register status latched on the rising edge of /RE. After status read operation is finished, RSTS is low. tSC tCR t CRH / CS A0 /WE /RE Data[0: 15] tD tRL Status t rH RSTS Figure 5.7 - Status Read Timing Diagram l Data Write External HOST pull A0 low, while WSTS active high, it indicated that Data Buffer Memory is ready to be written by external microprocessor through Data[0:15] port. HOST continues write 256 words data by bring /CS is low. Data is latched on the rising edge of /WE. The GL824 Data Buffer Memory Address Pointer is increased automatically. After data continues write operation is finished and latched into Data Buffer Memory, WSTS will drive low. When GL824 Data Buffer Memory is ready for HOST write data, WSTS return to high. ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 28 GL824/GL824C USB 2.0 On-The-Go Controller Figure 5.8 - Data Write Timing Diagram l Data Read External HOST pull A0 low, while RSTS active high, it indicated that Data Buffer Memory is ready to be read by external microprocessor through Data[0:15] port. HOST continues read 256 words data by bring /CS is low. Data is latched on the rising edge of /RE. The GL824 Data Buffer Memory Address Pointer is increased automatically. After data continues read operation is finished, RSTS is low. When GL824 Data Buffer Memory is ready for HOST read data, RSTS return to high. Figure 5.9 - Data Read Timing Diagram Table 5.2 - Host Interface AC Characteristics Symbol tCW tCWH tSC tWL tSU tH tRL tCYC tEH tEL tCR tCRH trH Parameter Chip Select Low to Write Enable Low delay time Chip Select High for Write Enable High delay time A0 High to Write Enable Low delay time Write Enable Low time Data Setup Time for /WE signal Data Hold Time for /WE signal Read Enable Low time Write Enable clock cycle time Write Pulse High width Write pulse Low width Chip Select Low to Read Enable Low delay time Chip Select High for Read Enable High delay time Command/Data read hold time for enable signal Min. 5 5 5 20 20 5 20 40 20 20 5 5 Max. 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Page 29 ©2000-2006 Genesys Logic Inc. - All rights reserved. GL824/GL824C USB 2.0 On-The-Go Controller tD Data ready for command/Data read 5 ns ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 30 GL824/GL824C USB 2.0 On-The-Go Controller CHAPTER 6 ELECTRICAL CHARACTERISTICS 6.1 Absolute Maximum Ratings Table 6.1 - Absolute Maximum Ratings Parameter Storage Temperature Ambient Temperature Supply Voltage to Ground Potential DC Input Voltage to Any Pin Value -65°C to +150 °C -40°C to +80 °C -0.5V to +4.0V -0.5V to +5.8V 6.2 Operating Conditions Table 6.2 - Operating Conditions Parameter Ta (Ambient Temperature Under Bias) Supply Voltage Ground Voltage FOSC (Oscillator or Crystal Frequency) Value 0°C to 70°C +3.0V to +3.6V 0V 24 MHz ± 0.25% 6.3 DC Characteristics Table 6.3 - DC Characteristics Symbol VCC VIH VIL II VOH VOL IOH IOL CIN ISUSP ICC Parameter Supply Voltage Input High Voltage Input Low Voltage Input Leakage current Output High Voltage Output Low Voltage Output Current High Output Current Low Input Pin Capacitance Suspend current Supply current 1.5K external pull-up included Connect to USB with 8051 operating VDD=3.3V VOH=2.6V VDD=3.3V VOL=0.8V 0 < VIN < VCC Condition Min. 3.0 2.6 0 -5 3.0 Typ. 8 8 5 Max. 3.6 5 0.7 5 0.2 500 100 Unit V V V µA V V mA mA pF µA mA ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 31 GL824/GL824C USB 2.0 On-The-Go Controller 6.4 PMOS Characteristics Table 6.4 – PMOS Characteristics (Core Power=2.5V, IO Power=3.3V) Simulation Results Driving Strength Turn-On Slew Rate (V/uS) On-Resistance (ohm) TT (25oC) 124.4 0.256 1.61 SS (80oC) 102.5 0.175 1.95 FF (0oC) 140.5 0.2560.321 1.611.42 Note: 1. Driving strength is defined as the PMOS sinking current when Vio=3.3V, Vd=3.1V. 2. Turn-on slew rate is defined as the falling speed of PMOS’s gate voltage from 3.2V to 0.2V. 3. On-resistance is calculated by 0.2V divided by driving strength. Figure 6.1 – Embedded PMOS Switch Architecture ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 32 GL824/GL824C USB 2.0 On-The-Go Controller Figure 6.2 – I-V Curve of PMOS Swtich ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 33 GL824/GL824C USB 2.0 On-The-Go Controller Figure 6.3 – Transient Analysis of PMOS Switch 6.5 AC Characteristics 6.5.1 External Flash NVMA[0..15] NVMOE# NVMWE# NVMD[0..7] dddddxdddddddddddddddxddddd \\\\\;\\\\\\\\\\\\\\@’\\\\\ Twc lllllrhhhhhhhhhhhhhhhflllll \\\\\;\\\@;\\\\\@’\\\;\\@’\ Tow Tww Tra hhhhhhhhhhfllllllrhhhhhhhhh dddddxddddxddddddddddxdddxd Figure 6.4 – Timing Diagram of External Flash Description Write data cycle time Write pulse width OE# to WE# time Read Access time Min Typ 102.5 41.6 38.6 Max 90 ns Unit Parameter TWC TWW TOW TRA ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 34 GL824/GL824C USB 2.0 On-The-Go Controller 6.5.2 SmartMedia Read RE# D[0..7] Write CLE \\\\\;\\\\\\\\\\\\\@;\\\\\@’ Tcr Trw hhhhhfllllllrhhhhhhhfllllllr Tds Tdh \\\\\\\\;\\@;\@’\\\\\\\\\\\\ zzzzzzzznddddddozzzzzzzznddd ALE WE# D[0..7] lrhhhhflllllllllllllllllllll \;\\\@’\\\\\\\\\\\\\;\\\\@’\ Tcw lllllllllrhhhhhhhfllllllllll T Tww \\\\\\\\\\\\\\\\\\\\;\@’\\\\ hhhhhhhhhhhhhhhhhhhhfllrhhfl Tdp Tcd Tdw Tai Tdw Tdd Tad \;@;@’\\\;@’;@;@’\\\\;@;@’\\ zzzndozzzzndozndozzzzndddozn Figure 6.5 - Timing Diagram of SmartMedia Parameter Tcw Description CLE active width Mode Normal Slow Min - Typ 165 198 100 166 66 100 33.3 67 100 33.3 33.3 33.3 33.3 133.3 166.6 100 40 20 Max - Unit Twc Write data cycle time Normal Slow Normal Slow Normal Slow Normal Slow - Tww Tcd Tdw Tad Tai Tdp Tdd Tcr Trw Tds Tdh Write pulse width CLE-to-command delay Data width ALE-to-address delay Address data interval time Data pre-output delay Data delay time Read data cycle time Read pulse width Data setup time Data hold time ns ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 35 GL824/GL824C USB 2.0 On-The-Go Controller 6.5.3 xD-Picture Read RE# D[0..7] Write CLE \\\\\;\\\\\\\\\\\\\@;\\\\\@’ Tcr Trw hhhhhfllllllrhhhhhhhfllllllr Tds Tdh \\\\\\\\;\\@;\@’\\\\\\\\\\\\ zzzzzzzznddddddozzzzzzzznddd ALE WE# D[0..7] lrhhhhflllllllllllllllllllll \;\\\@’\\\\\\\\\\\\\;\\\\@’\ Tcw lllllllllrhhhhhhhfllllllllll T Tww \\\\\\\\\\\\\\\\\\\\;\@’\\\\ hhhhhhhhhhhhhhhhhhhhfllrhhfl Tdp Tcd Tdw Tai Tdw Tdd Tad \;@;@’\\\;@’;@;@’\\\\;@;@’\\ zzzndozzzzndozndozzzzndddozn Figure 6.6 - Timing Diagram of xD-Picture Parameter Tcw Description CLE active width Mode Normal Slow Min Typ 165 198 100 166 66 100 33.3 Max Unit Twc Write data cycle time Normal Slow Normal Slow Tww Tcd Tdw Tad Tai Tdp Tdd Tcr Trw Tds Tdh Write pulse width CLE-to-command delay Data width ALE-to-address delay Address data interval time Data pre-output delay Data delay time Read data cycle time Read pulse width Data setup time Data hold time Normal Slow 67 100 33.3 33.3 33.3 33.3 ns Normal Slow 133.3 166.6 100 40 20 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 36 GL824/GL824C USB 2.0 On-The-Go Controller 6.5.4 Memory Stick BS SCLK SDIO llrhhhhhhhhhhhhhhhfllllllllll lllrfrfrfrfrfrfrfrfrfrfrfrfrf ddddxdddddddddddddddxdddddddd Figure 6.7 - Timing Diagram of MemoryStick Parameter Description Mode 0 Typ 1.5M 6M 15M 20M Unit Remark Fck SCLK frequency 1 2 3 Hz 6.5.5 Memory Stick PRO BS SCLK DATA llrhhhhhhhhhhhhhhhfllllllllll lllrfrfrfrfrfrfrfrfrfrfrfrfrf dddxdxdxdxdxdxdxdxdxdxdxdxdxd Figure 6.8 - Timing Diagram of MemoryStick PRO Parameter Fck Description SCLK frequency Mode 0 1 Typ 30M 40M Unit Hz Remark 6.5.6 Secure Digital / MultiMedia Card CMD CLK DAT dddxdxdxdddddddddddddddddxdddd rfrfrfrfrfrfrfrfrfrfrfrfrfrfrf dddddddddddddxdddddddddddxdddd Figure 6.9 - Timing Diagram of SD / MMC Parameter Description Mode 0 1 Typ 375K 6M 15M 24M 48M Unit Remark Fck CLK frequency 2 3 4 Hz ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 37 GL824/GL824C USB 2.0 On-The-Go Controller 6.5.7 CompactFlash Card \\\;\\\\\\\\\\@;\\\\@’\\\\ IOR-/IOWhhhflllllrhhhhhflllllrhhhh Td Thw \\\;@’\\\;@’\\\\\\\\\\\\\\ WRITE DD[15:0] zzzzzndddddozzzzzndddddozz Tsu Thr \\\\\\\;@;@’\\\\\\\\\\\\\\ READ DD[15:0] zzzzzzzndddozzzzzzzndddozz Figure 6.10 - Timing Diagram of CompactFlash Parameter Description Mode 0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3 Min 600 383 240 180 120 100 80 165 125 100 80 70 65 55 0 0 0 0 0 0 0 30 20 15 10 10 5 5 50 35 20 20 Typ Max Unit ns Tcyc Read/Write Cycle Time Tw Read/Write Active Width Td Delay Time for Write Data Thw Data Hold Time following IOW- Tsu Data Setup Time before IOR- ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 38 GL824/GL824C USB 2.0 On-The-Go Controller 4 5 6 0 1 2 3 4 5 6 20 15 10 5 5 5 5 5 5 5 - Thr Data Hold Time following IOR- 6.5.8 Reset Timing Trst Extrstz Figure 6.11 - Timing Diagram of Reset Parameter Trst Description This active low signal is used by the system to reset the chip; the active low pulse should be at least 1us wide. Minimum 1 Unit us Remark 6.5.9 ATA/ ATAPI The GL824 complies with ATA / ATAPI-6 specification rev 1.0, which supports following data transfer modes: 1. DMA (Direct Memory Access) data transfer: DMA data transfer means of data transfer between device and host memory without host processor intervention. - Multiword DMA: Multiword DMA is a data transfer protocol used with the READ DMA, WRITE DMA, READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When a Multiword DMA transfer is enabled as indicated by IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data, this data transfer protocol shall be used for the data transfers associated with these commends. (Please refer to the ATA / ATAPI-6 specification rev 1.0 for more information.) - Ultra DMA: Ultra DMA Is a data transfer protocol used with the READ DMA, WRITE DMA, READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When this protocol is enabled, the Ultra DMA protocol shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only. (Please refer to the ATA / ATAPI-6 specification rev 1.0 for more information.) Following listed the symbols and their respective definitions that are used in the timing diagram: ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 39 GL824/GL824C USB 2.0 On-The-Go Controller - Signal transition (asserted or negated) Data transition (asserted or negated) Data valid Undefined but not necessarily released Asserted, negated or released Released The “other” condition if a signal is shown with no change - All signals are shown with the asserted condition facing to the top of the page. The negated condition is shown towards the bottom of the page relative to the asserted condition. The interface uses a mixture of negative and positive signals for control and data. The terms asserted and negated are used for consistency and are independent of electrical characteristics. In all timing diagrams, the lower line indicates negated, and the upper line indicates asserted. The following illustrates the representation of a signal named Test going from negated to asserted and back to negated, based on the polarity of the signal. ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 40 GL824/GL824C USB 2.0 On-The-Go Controller 6.5.10 Register Transfers Figure 6.12 – Register Transfers Timing Notes: 1. Device address consists of signals CS0_, CS1_ and DA(2:0). 2. Data consists of IODD(7:0). 3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is to be extended is made by the host after tA from the assertion of DIOR_ or DIOW_. The assertion and negation of IORDY are described as following: 3.1 Device never negates IORDY, devices keeps IORDY released: no wait is generated. 3.2 Device negates IORDY before tA, but causes IORDY to be asserted before tA. IORDY is released prior to negation and may be asserted for no more than 5 ns before release: no wait generated. 3.3 Device negates IORDY before tA, IORDY is released prior to negation and may be asserted for no more than 5 ns before release: wait generated. The cycle completes after IORDY is released. For cycles where a wait is generated and DIOR_ is asserted, the device shall read data on IODD(0:7) for tRD before asserting IORDY. 4. DMACK_ shall remain negated during a register transfer. ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 41 GL824/GL824C USB 2.0 On-The-Go Controller Register transfer timing parameters t0 t1 t2 t2i t3 t4 t5 t6 t6Z t9 tRD tA tB tC Cycle time Address valid to DIOR_/ DIOW_ setup DIOR_/ DIOW_ pulse width 8-bit DIOR_/ DIOW_ recovery time DIOW_ data setup DIOW_ data hold DIOR_ data setup DIOR_ data hold DIOR_ data tristate DIOR_/ DIOW_ to address valid hold Read Data Valid to IORDY active (if IORDY initially low after tA) IORDY Setup time IORDY Pulse Width IORDY assertion to release (max) Timing (ns) 2000 1000 300 900 80 40 900 - 6.5.11 Multiword DMA data transfer Register transfer timing parameters t0 tD tE tF tG tH tI tJ tKR tKW tLR tLW tM tN tZ Cycle time DIOR_/ DIOW_ asserted pulse width DIOR_ data access DIOR_ data hold DIOR_/ DIOW_ data setup DIOW_ data hold DMACK to DIOR_/ DIOW_ setup DIOR_/ DIOW_ to DMACK hold DIOR_ negated pulse width DIOW_ negated pulse width DIOR_ to DMARQ delay DIOW_ to DMARQ delay CS(1:0) (max) valid to DIOR_/ DIOW_ CS(1:0) hold DMACK_ to read data released Timing (ns) 120 80 40 18 18 20 36 36 36 18 - ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 42 GL824/GL824C USB 2.0 On-The-Go Controller Note: The host shall not assert DMACK_ or negate both CS0_ and CS1_ until the assertion of DMARQ is detected. The maximum time from the assertion of DMARQ to the assertion of DMACK_ or the negation of both CS0_ and CS1_ is not defined. Figure 6.13 - Initiating a Multiword DMA Data Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 43 GL824/GL824C USB 2.0 On-The-Go Controller Figure 6.14 - Sustaining a Multiword DMA Data Burst Note: To terminate the data burst, the Device shall negate DMARQ within the tL of the assertion of the current DIOR_ or DIOW_ pulse. The last data word for the burst shall then be transferred by the negation of the current DIOR_ or DIOW_ pulse. If all data for the command has not been transferred, the device shall reassert DMARQ again at any later time to resume the DMA operation. Figure 6.15 - Device Terminating a Multiword DMA Data Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 44 GL824/GL824C USB 2.0 On-The-Go Controller Note: 1. To terminate the transmission of a data burst, the Host shall negate DMACK_ within the specified time after a DIOR_ or DIOW_ pulse. No further DIOR_ or DIOW_ pulses shall be asserted for this burst. 2. If the device is able to continue the transfer of data, the device may leave DMARQ asserted and wait for the host to reassert DMACK_ or may negate DMARQ at any time after detecting that DMACK_ has been negated. Figure 6.16 - Host terminating a Multiword DMA Data Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 45 GL824/GL824C USB 2.0 On-The-Go Controller 6.5.12 Ultra DMA data transfer Table 6.5 - Ultra DMA data burst timing requirements Name Mode 0 (in ns) min max Mode 1 (in ns) min max Mode 2 (in ns) min max Mode 3 (in ns) min max Mode 4 (in ns) Min max Comment Typical sustained average two cycle time Cycle time allowing for asymmetry and clock variations Two cycle time allowing for clock variations Data setup time at recipient Data hold time at recipient Data valid setup time at sender Data valid hold time at sender First STORBE time Limited interlock time Interlock time with minimum Unlimited interlock time t2CYCTYP 240 112 230 15 5 70 6 0 0 20 0 10 20 0 20 70 50 75 160 20 0 20 50 230 150 160 73 154 10 5 48 6 0 0 20 0 10 20 0 20 70 30 70 125 20 0 20 50 200 150 120 54 115 7 5 30 6 0 0 20 0 10 20 0 20 70 20 60 100 20 0 20 50 170 150 90 39 86 7 5 20 6 0 0 20 0 10 20 0 20 55 NA 60 100 20 0 20 50 130 100 60 25 57 5 5 6 6 0 0 20 0 10 20 0 20 55 NA 60 100 20 0 20 50 120 100 tCYC t2CYC tDS tDH tDVS tDVH tFS tLI tMLI tUI tAZ tZAH tZAD tENV tSR tRFS tRP tIORDYZ tZIORDY tACK tSS Maximum time allowed for output drivers to release Minimum delay time required for output Drivers to assert or negate Envelope time STROBE to DMARDY_ time Ready to final STROBE time Minimum time to assert STOP or negate DMARQ Maximum time before releasing IORDY Minimum time before driving STROBE Setup and hold times for DMACK_ Time from STROBE edge to negation of DMARQ or assertion of STOP ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 46 GL824/GL824C USB 2.0 On-The-Go Controller Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are not in efficient until DMARQ and DMACK are asserted. Figure 6.17 - Initiating an Ultra DMA Data-In Burst Notes: IODD(15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device. Figure 6.18 - Sustained Ultra DMA Data-In Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 47 GL824/GL824C USB 2.0 On-The-Go Controller Notes: 1. The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY_ is negated. 2. If the tSR timing is not satisfied, the host may receive zero, one, or two more data words from the device. Figure 6.19 - Host Pausing an Ultra DMA Data-In Burst Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 6.20 - Device Terminating an Ultra DMA Data-In Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 48 GL824/GL824C USB 2.0 On-The-Go Controller Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 6.21 - Host Terminating an Ultra DMA Data-In Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 49 GL824/GL824C USB 2.0 On-The-Go Controller Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. Figure 6.22 - Initiating an Ultra DMA Data-Out Burst Notes: IODD(15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the devicet until some time after they are driven by the host. Figure 6.23 - Sustained Ultra DMA Data-Out Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 50 GL824/GL824C USB 2.0 On-The-Go Controller Notes: 1. The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY_ is negated. 2. If the tSR timing is not satisfied, the device may receive zero, one, or two more data words from the host. Figure 6.24 - Device Pausing an Ultra DMA Data-Out Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 51 GL824/GL824C USB 2.0 On-The-Go Controller Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 6.25 - Host terminating an Ultra DMA data-out burst ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 52 GL824/GL824C USB 2.0 On-The-Go Controller Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 6.26 - Device Terminating an Ultra DMA Data-Out Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 53 GL824/GL824C USB 2.0 On-The-Go Controller CHAPTER 7 PACKAGE DIMENSION SYMBOL A A1 A2 b c D D1 E E1 e L L1 Y Internal No. Green Package Code No. Date Code Lot Code DIMENSION MM (MIL) MIN. NOM. MAX. --1.60(63) 0.05(2) -0.15(6) 1.35(53) 1.40(55) 1.45(57) 0.17(7) 0.22(9) 0.27(11) 0.09(4) -0.20(8) 30.00 (1181) BSC 28.00 (1102) BSC 30.00 (1181) BSC 28.00 (1120) BSC 0.50 (20) BSC 0.45(18) 0.60(24) 0.75(30) 1.00 (39) REF --0.08(3) 0o 3.5o 7o GAGE PLANE Figure 7.1 - GL824 208 Pin LQFP Package ©2000-2006 Genesys Logic Inc. - All rights reserved. A1 A2 A Page 54 GL824/GL824C USB 2.0 On-The-Go Controller 65 97 64 SYMBOL A A1 A2 b c D D1 E E1 e L L1 Y Internal No. Green Package Code No. Date Code Lot Code DIMENSION MM (MIL) MIN. NOM. MAX. 1.60(63) 0.05(2) 0.15(6) 1.35(53) 1.40(55) 1.45(57) 0.13(5) 0.18(7) 0.23(9) 0.09(4) 0.20(8) 16.00 (630) BSC 14.00 (551) BSC 16.00 (630) BSC 14.00 (551) BSC 0.40 (16) BSC 0.45(18) 0.60(24) 0.75(30) 1.00 (39) REF 0.10(4) 0o 3.5o 7o 33 128 1 e b 32 NOTE: 1.REFER TO JEDEC MS-026/BEE REV.B 2.ALL DIMENSIIONS IN MILLIMETERS. Q D1 E1 YS D S E b BASE METAL X GAGE PLANE X L L1 SEATING PLANE SECTION X-X PLATING Detall Q Figure 7.2 - GL824C 128 Pin LQFP Package ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 55 GL824/GL824C USB 2.0 On-The-Go Controller CHAPTER 8 ORDERING INFORMATION Table 8.1 - Ordering Information Part Number GL824-MZGXX GL824C-MXGXX Package 208-pin LQFP 128-pin LQFP Green Green Package Green Package Version XX XX Status Available Available ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 56