GL830-MXGXX

Genesys Logic, Inc. GL830 USB 2.0 to SATA Bridge Controller Datasheet Revision 1.02 Aug. 21, 2007 GL830 USB2.0 to SATA Bridge Controller Copyright: Copyright © 2007 Genesys Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic, Inc. Disclaimer: ALL MATERIALS ARE PROVIDED "AS IS" WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE. Trademarks: is a registrated trademark of Genesys Logic, Inc. All trademarks are the properties of their respective owners. Office: Genesys Logic, Inc. 12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel: (886-2) 8913-1888 Fax: (886-2) 6629-6168 http://www.genesyslogic.com ©2007 Genesys Logic Inc. - All rights reserved. Page 2 GL830 USB2.0 to SATA Bridge Controller Revision History Revision 1.00 1.01 1.02 Date 06/14/2007 7/17/2007 08/21/2007 First Formal Release Add 48 and 128pin description Modify LQFP48/64/128 description Description ©2007 Genesys Logic Inc. - All rights reserved. Page 3 GL830 USB2.0 to SATA Bridge Controller TABLE OF CONTENTS CHAPTER 1 GENERAL DESCRIPTION................................................... 8 CHAPTER 2 FEATURES .............................................................................. 9 CHAPTER 3 PIN ASSIGNMENT .............................................................. 10 3.1 PINOUTS.................................................................................................... 10 3.2 PIN LIST.................................................................................................... 13 3.3 PIN DESCRIPTIONS ................................................................................... 15 CHAPTER 4 BLOCK DIAGRAM.............................................................. 22 CHAPTER 5 FUNCTION DESCRIPTION ............................................... 23 5.1 UTM......................................................................................................... 23 5.2 SIE............................................................................................................ 23 5.3 EP0/EP3 FIFO AND BULK BUFFER ........................................................ 23 5.4 OPERATION REGISTER............................................................................. 23 5.5 SPI INTERFACE ........................................................................................ 23 5.6 PHY LAYER ............................................................................................. 23 5.7 LINK LAYER ............................................................................................. 23 5.8 TRANSPORT LAYER .................................................................................. 23 5.9 APPLICATION LAYER ............................................................................... 23 CHAPTER 6 ELECTRICAL CHARACTERISTICS............................... 24 6.1 ABSOLUTE MAXIMUM RATINGS .............................................................. 24 6.2 TEMPERATURE CONDITIONS ................................................................... 24 6.3 DC CHARACTERISTICS ............................................................................ 24 6.3.1 I/O Type digital pins ....................................................................... 24 6.3.2 USB Interface DC Characteristics ................................................ 25 6.3.3 SATA Interface DC Characteristics ............................................. 25 6.3.4 Reference Clock Input Requirement ............................................ 25 6.3.5 Reference Resistor Requirement ................................................... 25 6.4 AC CHARACTERISTICS ............................................................................ 25 6.4.1 USB Interface AC Characteristics ................................................ 25 6.4.2 SATA Interface AC Characteristics ............................................. 25 ©2007 Genesys Logic Inc. - All rights reserved. Page 4 GL830 USB2.0 to SATA Bridge Controller CHAPTER 7 PACKAGE DIMENSION..................................................... 26 CHAPTER 8 ORDERING INFORMATION ............................................ 29 ©2007 Genesys Logic Inc. - All rights reserved. Page 5 GL830 USB2.0 to SATA Bridge Controller LIST OF FIGURES FIGURE 3.1 - 48 PIN LQFP PINOUT DIAGRAM.................................................................. 10 FIGURE 3.2 - 64 PIN LQFP PINOUT DIAGRAM.................................................................. 11 FIGURE 3.3 - 128 PIN LQFP PINOUT DIAGRAM ............................................................... 12 FIGURE 4.1 - BLOCK DIAGRAM ......................................................................................... 22 FIGURE 7.1 – GL830 48 PIN LQFP PACKAGE .................................................................. 26 FIGURE 7.2 - GL830 64 PIN LQFP PACKAGE ................................................................... 27 FIGURE 7.3 - GL830 128 PIN LQFP PACKAGE ................................................................. 28 ©2007 Genesys Logic Inc. - All rights reserved. Page 6 GL830 USB2.0 to SATA Bridge Controller LIST OF TABLES TABLE 3.1 – 48 PIN LIST .................................................................................................... 13 TABLE 3.2 – 64 PIN LIST .................................................................................................... 13 TABLE 3.3 – 128 PIN LIST .................................................................................................. 14 TABLE 3.4 – 48 PIN DESCRIPTIONS.................................................................................... 15 TABLE 3.5 – 64 PIN DESCRIPTIONS.................................................................................... 16 TABLE 3.6 – 128 PIN DESCRIPTIONS.................................................................................. 18 TABLE 6.1 - MAXIMUM RATINGS ...................................................................................... 24 TABLE 6.2 - TEMPERATURE CONDITIONS ......................................................................... 24 TABLE 6.3 - I/O TYPE DIGITAL PINS .................................................................................. 24 TABLE 6.6 - REFERENCE CLOCK INPUT REQUIREMENT .................................................. 25 TABLE 6.7 - REFERENCE RESISTOR REQUIREMENT ......................................................... 25 TABLE 8.1 - ORDERING INFORMATION ............................................................................. 29 ©2007 Genesys Logic Inc. - All rights reserved. Page 7 GL830 USB2.0 to SATA Bridge Controller CHAPTER 1 GENERAL DESCRIPTION The GL830 is a highly-compatible, low cost USB 2.0 to SATA bridge controller, which integrates Genesys Logic own design high speed UTMI (USB 2.0 Transceiver Macrocell Interface) transceiver/receiver and Serial ATA PHY. As a one-chip solution which complies with Universal Serial Bus specification rev. 2.0 and Serial ATA specification rev. 2.6. There are totally 4 endpoints in the GL830 controller, Control (0), Bulk In (1), Bulk Out (2), and Interrupt (3). By complies with the USB Storage Class specification ver.1.0 (Bulk only protocol), the GL830 can support not only plug and play but also Windows Vista/ XP/ 2000/ ME default driver. The GL830 uses 25MHz crystal and slew-rate controlled pads to reduce the EMI issue. With 64-pin LQFP (7mmX7mm) package, the GL830 is the best cost/ performance solution to fit different situations in the USB 2.0 high speed storage class applications such as SATA HDD and ODD. ©2007 Genesys Logic Inc. - All rights reserved. Page 8 GL830 USB2.0 to SATA Bridge Controller CHAPTER 2 FEATURES · Complies with Universal Serial Bus specification rev. 2.0. · Complies with USB Storage Class specification ver.1.0. (Bulk only protocol) · Operating system supported: Win Vista/ Win XP / 2000 / Me / 98 / 98SE; Mac OS 9.X / X. · Integrated USB 2.0 Transceiver Macrocell Interface (UTMI) transceiver and Serial Interface Engine (SIE). · Support 4 endpoints: Control (0) / Bulk Read (1) / Bulk Write (2) / Interrupt (3). · 64 / 512 bytes Data Payload for full / high speed Bulk Endpoint. · Complies with Serial ATA specification rev. 2.6. · Support SATA hot-plug · Support Spread Spectrum Clocking to reduce EMI · Support Partial/Slumber power management · Provide adjustable TX signal amplitude and pre-emphasis level · Provide specified OOB signal detection and transmission · Embedded Turbo 8051. · ROM size: 12k words; RAM size: 1280 bytes. (Bulk Buffer: 512 words, MC RAM: 256 bytes) · Supports Power Down mode and USB suspend indicator. · Supports USB 2.0 TEST mode features. · Supports 4 PIO and 4GPIO for programmable AP. · Supports device power control for power on/off when running suspend mode. · Provides LED indicator for Full Speed and High Speed . · using 25 MHz external clock to provide better EMI. · 3.3V power input; 5V tolerance pad. · Supports Wakeup ability. · Embedded Regulator (3.3V to 1.8V). · Embedded Regulator (5V to 3.3V). · Provides SPI interface for Finger Print (only for 64 pin package). · Available in 48/64/128-pin LQFP. ©2007 Genesys Logic Inc. - All rights reserved. Page 9 GL830 USB2.0 to SATA Bridge Controller CHAPTER 3 PIN ASSIGNMENT 3.1 Pinouts AGND AVDD CVDD CVDD GND VDD GND VDD 36 35 34 33 32 31 30 29 28 27 26 RTERM PLLVDD PLLVSS TXVSS TXVDD 37 38 39 40 41 42 43 44 45 46 47 48 25 DM DP X1 X2 24 23 22 21 20 19 18 17 16 15 AGND RREF AVDD NC GPIO1 NC PIO2 GPIO2 NC V5 VDD GND TXP TXN RXN RXP RXVDD RXVSS CVDD LQFP - 48 14 13 10 11 PIO1 HRST_ PIO3 GPIO0 GPIO3 CVDD TEST PIO0 Figure 3.1 - 48 Pin LQFP Pinout Diagram ©2007 Genesys Logic Inc. - All rights reserved. CVDD GND VDD GND 12 1 2 3 4 5 6 7 8 9 Page 10 GL830 USB2.0 to SATA Bridge Controller 48 PLLVDD PLLVSS RXPEXT RXNEXT TXNEXT 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC GPIO1 NC NC PIO2 NC GPIO2 NC V5 VDD GND CVDD NC NC NC 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TXPEXT TXVSS TXVDD TXP TXN RXN RXP RXVDD RXVSS CVDD GND GL830 LQFP - 64 24 23 22 21 20 19 18 17 Figure 3.2 - 64 Pin LQFP Pinout Diagram ©2007 Genesys Logic Inc. - All rights reserved. Page 11 GL830 USB2.0 to SATA Bridge Controller NC NC NC NC NC NC NC PLLVDD PLLVDD PLLVSS RXPEXT RXNEXT TXNEXT TXPEXT TXVSS TXVDD TXP TXN RXN RXP RXVDD RXVSS CVDD GND NC ROM_A8 ROM_A7 ROM_A9 ROM_A6 ROM_A10 ARESET_ SPDSEL 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 GL830 LQFP - 128 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 GPIO4 PHYRDY DMACK_ GPIO1 IORDY T_ROM DIOR_ PIO2 DIOW_ GPIO2 DMARQ ROM_D5 V5 VDD VDD MODE1 GND CVDD DD15 ROM_D2 DD0 ROM_D6 DD14 ROM_D1 DD1 ROM_D7 DD13 ROM_D0 DD2 ROM_A0 PIO1 PIO0 Figure 3.3 - 128 Pin LQFP Pinout Diagram ©2007 Genesys Logic Inc. - All rights reserved. Page 12 GL830 USB2.0 to SATA Bridge Controller 3.2 Pin List Table 3.1 – 48 Pin List Pin# 1 2 3 4 5 6 7 8 9 10 11 12 Pin Name GND GPIO0 GPIO3 PIO3 HRST_ CVDD VDD GND TEST PIO0 PIO1 CVDD Type Pin# P B B B I P P P I B B P 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name GND VDD V5 NC GPIO2 PIO2 NC GPIO1 NC AVDD RREF AGND Type Pin# P P P B B B P A P 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name DM DP AVDD AGND CVDD VDD GND VDD X2 X1 CVDD GND Type Pin# B B P P P P P P B I P P 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name RTERM PLLVDD PLLVSS TXVSS TXVDD TXP TXN RXN RXP RXVDD RXVSS CVDD Type A P P P P O O I I P P P Table 3.2 – 64 Pin List Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 Pin Name GPIO0 GPIO3 PIO3 NC HRST_ NC NC CVDD VDD MODE GND TEST NC Type Pin# B B B I P P I P I 17 18 19 20 21 22 23 24 25 26 27 28 29 Pin Name NC NC NC CVDD GND VDD V5 NC GPIO2 NC PIO2 NC NC Type Pin# P P P P B B 33 34 35 36 37 38 39 40 41 42 43 44 45 Pin Name AVDD RREF AGND DM DP AVDD3 AGND3 CVDD VDD GND VDD X2 X1 Type Pin# P A P B B P P P P P P B I 49 50 51 52 53 54 55 56 57 58 59 60 61 Pin Name PLLVDD PLLVSS RXPEXT RXNEXT TXNEXT TXPEXT TXVSS TXVDD TXP TXN RXN RXP RXVDD Type P P I I O O P P O O I I P ©2007 Genesys Logic Inc. - All rights reserved. Page 13 GL830 USB2.0 to SATA Bridge Controller 14 15 16 NC PIO0 PIO1 B B 30 31 32 GPIO1 NC NC B - 46 47 48 CVDD GND RTERM P P A 62 63 64 RXVSS CVDD GND P P P Table 3.3 – 128 Pin List Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin Name GPIO0 GPIO3 PIO4 PIO3 ROM_A5 DD7 ROM_A11 DD8 HRST_ DD6 ROM_A4 DD9 ROM_A12 DD5 ROM_A3 CVDD CVDD VDD MOD0 GND DD10 ROM_A13 TEST TXD RXD Type Pin# B B B B O B O B I B O B O B O P P P I P B O I O B 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 Pin Name PIO0 PIO1 ROM_A0 DD2 ROM_D0 DD13 ROM_D7 DD1 ROM_D1 DD14 ROM_D6 DD0 ROM_D2 DD15 CVDD GND MODE1 VDD VDD V5 ROM_D5 DMARQ GPIO2 DIOW_ PIO2 Type Pin# B B O B B B B B B B B B B B P P I P P I B B B B B 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Pin Name AINTRQ AVDD AVDD RREF AGND AGND DM DP AVDD AGND GND GND CVDD DA1 DA0 NC DA2 ROM_D3 CS0_ ROM_D4 CS1_ GND VDD VDD GND Type Pin# B P P A P P B B P P P P P B B B B B B B P P P P 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 Pin Name NC NC NC NC NC NC NC PLLVDD PLLVDD PLLVSS RXPEXT RXNEXT TXNEXT TXPEXT TXVSS TXVDD TXP TXN RXN RXP RXVDD RXVSS CVDD GND NC Type P P P I I O O P P O O I I P P P P - ©2007 Genesys Logic Inc. - All rights reserved. Page 14 GL830 USB2.0 to SATA Bridge Controller 26 27 28 29 30 31 32 DD4 ROM_A2 DD11 ROM_A14 DD3 ROM_A1 DD12 B O B O B O B 58 59 60 61 62 63 64 DIOR_ T_ROM IORDY GPIO1 DMACK_ PHYRDY GPIO4 B I B B B O B 90 91 92 93 94 95 96 GND VDD X2 X1 VDD GND RTERM P P B I P P A 122 123 124 125 126 127 128 ROM_A8 ROM_A7 ROM_A9 ROM_A6 ROM_A10 ARESET_ SPDSEL O O O O O B I 3.3 Pin Descriptions Table 3.4 – 48 Pin Descriptions USB Interface Pin Name RREF DM DP AVDD AGND Pin# 23 25 26 22,27 24,28 Type A B B P P Reference resistor HS DHS D+ USB Analog 3.3V power USB Analog Ground Description SATA Interface Pin Name RTERM PLLVDD PLLVSS TXVSS TXVDD TXP TXN RXN RXP RXVDD RXVSS Pin# 37 38 39 40 41 42 43 44 45 46 47 Type A P P P P O O I I P P Reference resistor 1.8V Power Supplies for internal PLL Ground for internal PLL Ground for transceiver part 1.8V Power Supplies for transceiver part SATA Differential Transmit TX+ SATA Differential Transmit TXSATA Differential Receive RXSATA Differential Receive RX+ 1.8V Power Supplies for receiver part Ground for receiver part Description Digital Power and Ground Pin Name Pin# Type Description ©2007 Genesys Logic Inc. - All rights reserved. Page 15 GL830 USB2.0 to SATA Bridge Controller CVDD 6,12,29, 35,48 7,14 30, 32 1,8,13, 31,36 15 P 1.8V Digital Power VDD P 3.3V Digital Power GND V5 P p Digital Ground 5V Power Input Miscellaneous Interface Pin Name TEST X2 X1 HRST_ GPIO0~3 PIO0~3 NC Pin# 9 33 34 5 2,20,17,3 10,11,18, 4 16,19,21 Type I (pd) Test Mode Input B I Crystal Output Crystal Input Description I (pu) Reset Pin B (pu) B (pd) General Purpose I/O #0~#3 Programmable I/O #0~#3 No connection Table 3.5 – 64 Pin Descriptions USB Interface Pin Name RREF DM DP AVDD AGND Pin# 34 36 37 33,38 35,39 Type A B B P P Reference resistor HS DHS D+ USB Analog 3.3V power USB Analog Ground Description SATA Interface Pin Name RTERM PLLVDD PLLVSS RXPEXT RXNEXT Pin# 48 49 50 51 52 Type A P P I I Reference resistor 1.8V Power Supplies for internal PLL Ground for internal PLL eSATA Differential Receive RX+ eSATA Differential Receive RXDescription ©2007 Genesys Logic Inc. - All rights reserved. Page 16 GL830 USB2.0 to SATA Bridge Controller TXNEXT TXPEXT TXVSS TXVDD TXP TXN RXN RXP RXVDD RXVSS 53 54 55 56 57 58 59 60 61 62 O O P P O O I I P P eSATA Differential Transmit TXeSATA Differential Transmit TX+ Ground for transceiver part 1.8V Power Supplies for transceiver part SATA Differential Transmit TX+ SATA Differential Transmit TXSATA Differential Receive RXSATA Differential Receive RX+ 1.8V Power Supplies for receiver part Ground for receiver part Digital Power and Ground Pin Name CVDD Pin# 8,20,40, 46,63 9,22,41, 43 11,21,42, 47,64 23 Type P 1.8V Digital Power Description VDD P 3.3V Digital Power GND V5 P p Digital Ground 5V Power Input Miscellaneous Interface Pin Name TEST X2 X1 HRST_ MODE GPIO0~3 PIO0~3 Pin# 12 44 45 5 10 1,30,25,2 15,16,27, 3 4,6,7,13, 14,17,18, 19,24,26, 28,29,31, 32 Type I (pd) Test Mode Input B I Crystal Output Crystal Input Description I (pu) Reset Pin I (pd) Mode Select (0=> USB to SATA; 1=> eSATA to SATA) B (pu) B (pd) General Purpose I/O #0~#3 Programmable I/O #0~#3 NC - No connection ©2007 Genesys Logic Inc. - All rights reserved. Page 17 GL830 USB2.0 to SATA Bridge Controller Table 3.6 – 128 Pin Descriptions USB Interface Pin Name RREF DM DP AVDD AGND Pin# 68 71 72 66,67,73 69,70,74 Type A B B P P Reference resistor HS DHS D+ USB Analog 3.3V power USB Analog Ground Description SATA Interface Pin Name RTERM PLLVDD PLLVSS RXPEXT RXNEXT TXNEXT TXPEXT TXVSS TXVDD TXP TXN RXN RXP RXVDD RXVSS Pin# 96 104,105 106 107 108 109 110 111 112 113 114 115 116 117 118 Type A P P I I O O P P O O I I P P Reference resistor 1.8V Power Supplies for internal PLL Ground for internal PLL eSATA Differential Receive RX+ eSATA Differential Receive RXeSATA Differential Transmit TXeSATA Differential Transmit TX+ Ground for transceiver part 1.8V Power Supplies for transceiver part SATA Differential Transmit TX+ SATA Differential Transmit TXSATA Differential Receive RXSATA Differential Receive RX+ 1.8V Power Supplies for receiver part Ground for receiver part Description Digital Power and Ground Pin Name CVDD VDD Pin# 16,17,47, 77,119 18,50,51 87,88,91, 94 20,48,75, 76,86,89, 90,95, 120 Type P P 1.8V Digital Power 3.3V Digital Power Description GND P Digital Ground ©2007 Genesys Logic Inc. - All rights reserved. Page 18 GL830 USB2.0 to SATA Bridge Controller V5 52 p 5V Power Input ATA/ ATAPI Interface (Host mode) Pin Name Pin# 44,40,36, 30,26,14, 10,6,8,12, 21,28,32, 38,42,46 127 85, 83 79,78,81 65 62 60 58 56 54 Type Description DD0~15 B IDE Data Bus ARESET_ CS1_, CS0_ DA0~2 INTRQ DMACK_ IORDY DIOR_ DIOW_ DMARQ I (pu) I (pu) I (pd) O I (pu) O I (pu) I (pu) O Device Reset Chip Select #1,#0 IDE Address #2,#1,#0 IDE interrupt input IDE Acknowledge IDE Ready IDE read signal IDE write signal IDE request ATA/ ATAPI Interface (Device mode) Pin Name Pin# 44,40,36, 30,26,14, 10,6,8,12, 21,28,32, 38,42,46 127 85, 83 79,78,81 65 62 60 58 56 54 Type Description DD0~15 B IDE Data Bus ARESET_ CS1_, CS0_ DA0~2 INTRQ DMACK_ IORDY DIOR_ DIOW_ DMARQ O O O I (pd) O I (pu) O O I (pd) Device Reset Chip Select #1,#0 IDE Address #2,#1,#0 IDE interrupt input IDE Acknowledge IDE Ready IDE read signal IDE write signal IDE request ©2007 Genesys Logic Inc. - All rights reserved. Page 19 GL830 USB2.0 to SATA Bridge Controller Miscellaneous Interface Pin Name TEST X2 X1 HRST_ Pin# 23 92 93 9 Type I (pd) Test Mode Input B I Crystal Output Crystal Input Description I (pu) Reset Pin Mode Select 00=> USB to SATA; 10=> eSATA to SATA; I 01=> USB to PATA; 11=> SATA to PATA (pd) When MODE0,1=11, PIO1=0 is device mode. When MODE0,1=11, PIO1=1 is host mode. B General Purpose I/O #0~#4 (pu) B Programmable I/O #0~#4 (pd) O 8051 UART TXD (pu) B 8051 UART RXD (pu) I 0 => force in 1.5G; 1 => negotiate interface speed with attached (pd) device (1.5G or 3G) O SATA PHY ready MODE0,1 19,49 GPIO0~4 PIO0~4 TXD RXD SPDSEL PHYRDY T_ROM 1,61,55,2, 64 33,34,57, 4,3 24 25 128 63 59 35,31,27, 15,11,5, 125,123, 122,124, 126,7,13, 22,29 37,41,45, 82,84,53, 43,39 80,97,98, 99,100, 101,102, 103 I (pd) 0 => Internal ROM; 1 => External ROM ROM_A0~14 O ROM Address #0~#14 ROM_D0~7 B (pd) ROM Data #0~#7 NC - No connection Notation: Type O I B B/I B/O P A Output Input Bi-directional Bi-directional, default input Bi-directional, default output Power / Ground Analog Page 20 ©2007 Genesys Logic Inc. - All rights reserved. GL830 USB2.0 to SATA Bridge Controller SO pu pd odpu Automatic output low when suspend Internal pull up Internal pull down Open drain with internal pull up ©2007 Genesys Logic Inc. - All rights reserved. Page 21 GL830 USB2.0 to SATA Bridge Controller CHAPTER 4 BLOCK DIAGRAM GPIO PATA Application Layer SPI Transport Layer Bulk Buffer EP0/3 FIFO Controller Operation Register Link Layer SIE 8051 Core PHY Layer UTM ROM RAM eSATA SATA USB Figure 4.1 - Block Diagram ©2007 Genesys Logic Inc. - All rights reserved. Page 22 GL830 USB2.0 to SATA Bridge Controller CHAPTER 5 FUNCTION DESCRIPTION 5.1 UTM The USB 2.0 Transceiver Macrocell, it’s the analog circuitry that handles the low level USB protocol and signaling, and shifts the clock domain of the data from the USB 2.0 rate to one that is compatible with the general logic. 5.2 SIE The Serial Interface Engine, which contains the USB PID and address recognition logic, and other sequencing and state machine logic to handle USB packets and transactions. 5.3 EP0/EP3 FIFO and Bulk Buffer Endpoint 0/3 FIFO: The Control and Interrupt FIFO. It is composed of TX03FIFO and RX03FIFO, with 64-byte FIFO each, and it is used for endpoint 0/3 data transfer. Bulk Buffer: It is constructed in interleaved architecture and composed by two data buffers which is used to store data transferred between USB host and IDE device. 5.4 Operation Register It is a register space to store status information and to control the functions of GL830 by 8051. 5.5 SPI Interface The Serial Peripheral Interface is a serial, synchronous communication protocol. It is compatible with Motorola’s SPI specifications. 5.6 PHY Layer It has elastic buffer and supports receiver detection, data serialization and de-serialization. 5.7 Link Layer The Link layer transmits and receives frames, transmits primitives based on control signals from the Transport layer, and receives primitives from the Phy layer which are converted to control signals to the Transport layer. 5.8 Transport Layer The Transport layer constructs Frame Information Structures for transmission and decomposes received Frame Information Structure 5.9 Application Layer The Application Layer translates the ATA operation onto internal protocols. ©2007 Genesys Logic Inc. - All rights reserved. Page 23 GL830 USB2.0 to SATA Bridge Controller CHAPTER 6 ELECTRICAL CHARACTERISTICS 6.1 Absolute Maximum Ratings Table 6.1 - Maximum Ratings Symbol VIO Vcore VAUSB VASATA VESD TA Parameter Digital I/O pad power supply voltage Digital power supply voltage Analog power supply voltage for USB PHY Analog power supply voltage for SATA PHY Static discharge voltage Ambient Temperature Min. 3.0 1.62 3.0 1.62 4000 0 100 Typ. 3.3 1.8 3.3 1.8 Max. 3.6 1.98 3.6 1.98 Unit V V V V V o C 6.2 Temperature Conditions Table 6.2 - Temperature Conditions Item Storage Temperature Operating Temperature Value -50oC ~ 150 oC 0 oC ~ 70 oC 6.3 DC Characteristics 6.3.1 I/O Type digital pins Table 6.3 - I/O Type digital pins Parameter Current sink @ VOL = 0.4V Current output @ VOH = 2.4V (TTL high) Falling slew rate at 30 pF loading capacitance Rising slew rate at 30 pF loading capacitance Schmitt trigger low to high threshold point Schmitt trigger low to high threshold point Pad internal pull up resister Pad internal pull down resister Min. 10.58 14.74 0.56 0.58 1.4 1.4 37.87K 29.85K Typ. 14.21 27.46 0.91 0.91 1.5 1.5 64.7K 59.45K Max. 16.87 43.0 1.28 1.72 1.6 1.6 108.11K 134.26K Unit mA mA V/ns V/ns V V Ohms Ohms ©2007 Genesys Logic Inc. - All rights reserved. Page 24 GL830 USB2.0 to SATA Bridge Controller 6.3.2 USB Interface DC Characteristics The GL830 conforms to DC characteristics for Universal Serial Bus specification rev. 2.0. Please refer to this specification for more information. 6.3.3 SATA Interface DC Characteristics The GL830 conforms to DC characteristics for Serial ATA specification rev. 2.6. Please refer to this specification for more information. 6.3.4 Reference Clock Input Requirement Table 6.6 - Reference Clock Input Requirement Parameter X1 crystal frequency X1 cycle time Min. Typ. 25 40 Max. Unit MHz ns 6.3.5 Reference Resistor Requirement Table 6.7 - Reference Resistor Requirement Parameter USB Reference Resistor SATA Reference Resistor Min. Typ. 680 5.1K Max. Unit Ohms Ohms 6.4 AC Characteristics 6.4.1 USB Interface AC Characteristics The GL830 conforms to all timing diagrams and specifications for Universal Serial Bus specification rev. 2.0. Please refer to this specification for more information. 6.4.2 SATA Interface AC Characteristics The GL830 conforms to all timing diagrams and specifications for Serial ATA specification rev. 2.6. Please refer to this specification for more information. ©2007 Genesys Logic Inc. - All rights reserved. Page 25 GL830 USB2.0 to SATA Bridge Controller CHAPTER 7 PACKAGE DIMENSION Figure 7.1 – GL830 48 Pin LQFP Package ©2007 Genesys Logic Inc. - All rights reserved. Page 26 GL830 USB2.0 to SATA Bridge Controller Figure 7.2 - GL830 64 Pin LQFP Package ©2007 Genesys Logic Inc. - All rights reserved. Page 27 GL830 USB2.0 to SATA Bridge Controller D D1 D2 D A A2 0.05 S A1 96 97 65 64 Internal No. A E1 E2 E GL830 AAAAAAAGAA YWWXXXXXXXX Date Code Lot Code Green Package B Code No. 128 1 32 4X e b 33 bbb H A B D c ddd M C A B s D s L1 4X aaa C A B D 01 0 C ccc C SEATING PLANE 02 R1 H R2 0.25mm GAGE PLANE S L 03 - NOTES : 1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 2. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08mm. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. CONTROL DIMENSIONS ARE IN MILLIMETERS. MILLIMETER INCH SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. 0.063 1.60 A 0.006 0.05 0.15 0.002 A1 1.35 1.40 1.45 0.053 0.055 0.057 A2 16.00 BASIC 0.630 BASIC D 16.00 BASIC 0.630 BASIC E 14.00 BASIC 0.551 BASIC D1 14.00 BASIC 0.551 BASIC E1 12.40 BASIC D2 0.488 BASIC 12.40 BASIC E2 0.488 BASIC 0.08 0.003 R1 R2 0.08 0.20 0.003 0.008 0 0 3.5 7 0 3.5 7 01 0 0 02 11 12 13 11 12 13 03 11 12 13 11 12 13 0.09 0.20 0.004 0.008 c 0.45 0.60 0.75 0.018 0.024 0.030 L L1 1.00 REF 0.039 REF 0.20 0.008 S 0.13 0.16 0.23 0.005 0.006 0.009 b 0.40 BASIC 0.016 BASIC e TOLERANCES OF FORM AND POSITION aaa 0.20 0.008 0.20 0.008 bbb 0.08 0.003 ccc 0.003 ddd 0.07 Figure 7.3 - GL830 128 Pin LQFP Package ©2007 Genesys Logic Inc. - All rights reserved. Page 28 GL830 USB2.0 to SATA Bridge Controller CHAPTER 8 ORDERING INFORMATION Table 8.1 - Ordering Information Part Number GL830-MNGXX GL830-MSGXX GL830-MXGXX Package 48-pin LQFP 64-pin LQFP 128-pin LQFP Green Green Package Green Package Green Package Version XX XX XX Status Available Available Available ©2007 Genesys Logic Inc. - All rights reserved. Page 29