GL852-MNNXX

Genesys Logic, Inc. GL852 USB 2.0 MTT HUB Controller Datasheet Revision 1.14 Jul. 19, 2007 GL852 USB 2.0 MTT HUB Controller Copyright: Copyright © 2007 Genesys Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic, Inc. Disclaimer: ALL MATERIALS ARE PROVIDED “AS IS” WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE. Trademarks: is a registered trademark of Genesys Logic, Inc. All trademarks are the properties of their respective owners. Office: Genesys Logic, Inc. 12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel: (886-2) 8913-1888 Fax: (886-2) 6629-6168 http://www.genesyslogic.com ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 2 GL852 USB 2.0 MTT HUB Controller Revision History Revision 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.10 1.11 1.12 1.13 1.14 Date 07/07/2005 09/07/2005 09/15/2005 12/28/2005 01/19/2006 03/29/2006 06/15/2006 07/18/2006 09/05/2006 11/03/2006 12/08/2006 03/12/2007 05/03/2007 05/16/2007 07/19/2007 First Formal release Modify Pin Description, table3.3, p.12 Modify HUB Interface ,table3.3 Pin Description, p.12 Modify Pin List and Pin Descriptions of EE_CS, EE_DI, EE_SK, p.11~12 Add AC Characteristics, Ch6.5, p.26 Add Input Voltage for digital I/O(Ovcur1-4,Pself,Reset) pins, p.23 Changed GL852-N to GL852 1.GL852 48 Pin Pinout, Pin List, Pin Description, p.10~13 Add GL852 QFN 48PIN Modify GL852 48 Pin QFN Package, p.30 Modify Clock and Reset Interface of GL852 48 pin to 64 pin, p.14 Description Modify 93C46 Configuration, Table 5.1, p.22 Modify General Description, Ch1, p.7 Modify RESET# Setting, Ch5.2.1, p.18 Add “TJ” , Table 6.2, p.24 Add Modify PGANG/SUSPND Setting, Ch5.2.2, p.19 ©2000-2007 Genesys Logic Inc. - All rights reserved. ” θ“ JA , Table 6.2, p.24 Page 3 GL852 USB 2.0 MTT HUB Controller TABLE OF CONTENTS CHAPTER 1 GENERAL DESCRIPTION................................................... 7 CHAPTER 2 FEATURES .............................................................................. 8 CHAPTER 3 PIN ASSIGNMENT ................................................................ 9 3.1 PINOUTS...................................................................................................... 9 3.2 PIN LIST.................................................................................................... 12 3.3 PIN DESCRIPTIONS ................................................................................... 13 CHAPTER 4 BLOCK DIAGRAM.............................................................. 15 CHAPTER 5 FUNCTION DESCRIPTION ............................................... 16 5.1 GENERAL .................................................................................................. 16 5.2 CONFIGURATION AND I/O SETTINGS ....................................................... 18 CHAPTER 6 ELECTRICAL CHARACTERISTICS............................... 24 6.1 MAXIMUM RATINGS................................................................................. 24 6.2 OPERATING RANGES ................................................................................ 24 6.3 DC CHARACTERISTICS ............................................................................ 24 6.4 POWER CONSUMPTION ............................................................................ 26 6.5 AC CHARACTERISTICS ............................................................................ 27 CHAPTER 7 PACKAGE DIMENSION..................................................... 28 CHAPTER 8 ORDERING INFORMATION ............................................ 31 ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 4 GL852 USB 2.0 MTT HUB Controller LIST OF FIGURES FIGURE 3.1－GL852 64 PIN LQFP PINOUT DIAGRAM ...................................................... 9 FIGURE 3.2－GL852 48 PIN LQFP PINOUT DIAGRAM .................................................... 10 FIGURE 3.2－GL852 48 PIN QFN PINOUT DIAGRAM ...................................................... 11 FIGURE 4.1 - GL852 BLOCK DIAGRAM (MULTIPLE TT) .................................................. 15 FIGURE 5.1 - OPERATING IN USB 1.1 SCHEME.................................................................. 17 FIGURE 5.2 - OPERATING IN USB 2.0 SCHEME.................................................................. 18 FIGURE 5.3 - RESET# (EXTERNAL RESET) SETTING AND APPLICATION......................... 19 FIGURE 5.4 - POWER ON SEQUENCE OF GL852................................................................. 19 FIGURE 5.5 - TIMING OF PGANG/SUSPND STRAPPING ................................................. 20 FIGURE 5.6 - GANG MODE SETTING ................................................................................ 20 FIGURE 5.7 - SELF/BUS POWER SETTING ....................................................................... 21 FIGURE 5.8 - LED CONNECTION ....................................................................................... 21 FIGURE 5.9 - SCHEMATICS BETWEEN GL852 AND 93C46................................................ 23 FIGURE 7.1 - GL852 64 PIN LQFP PACKAGE ................................................................... 28 FIGURE 7.2 – GL852 48 PIN LQFP PACKAGE .................................................................. 29 FIGURE 7.2 – GL852 48 PIN QFN PACKAGE .................................................................... 30 ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 5 GL852 USB 2.0 MTT HUB Controller LIST OF TABLES TABLE 3.1－GL852 64 PIN LIST ....................................................................................... 12 TABLE 3.2－GL852 48 PIN LIST ....................................................................................... 12 TABLE 3.3 - PIN DESCRIPTIONS ......................................................................................... 13 TABLE 5.1 - 93C46 CONFIGURATION ................................................................................ 22 TABLE 6.1 - MAXIMUM RATINGS ...................................................................................... 24 TABLE 6.2 - OPERATING RANGES ...................................................................................... 24 TABLE 6.3 - DC CHARACTERISTICS EXCEPT USB SIGNALS ............................................ 24 TABLE 6.4 - DC CHARACTERISTICS OF USB SIGNALS UNDER FS/LS MODE.................. 25 TABLE 6.5 - DC CHARACTERISTICS OF USB SIGNALS UNDER HS MODE ....................... 25 TABLE 6.6 - DC SUPPLY CURRENT .................................................................................... 26 TABLE 6.7 - AC CHARACTERISTICS OF EEPROM INTERFACE ....................................... 27 TABLE 8.1 - ORDERING INFORMATION ............................................................................. 31 ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 6 GL852 USB 2.0 MTT HUB Controller CHAPTER 1 GENERAL DESCRIPTION GL852 is Genesys Logic’s brand new Hub solutions which fully comply with Universal Serial Bus Specification Revision 2.0. This series includes GL852. GL852 embeds an 8-bit RISC processor to manipulate the control/status registers and respond to the requests from USB host. Firmware of GL852 will control its general purpose I/O (GPIO) to access the external EEPROM and then respond to the host the customized PID and VID configured in the external EEPROM. Default settings in the internal mask ROM is responded to the host without having external EEROM. GL852 is designed for customers with much flexibility. The more complicated settings such as PID, VID, and number of downstream ports settings are easily achieved by programming the external EEPROM (Ref. to Chapter 5). Each downstream port of GL852 supports two-color (green/amber) status LEDs to indicate normal/abnormal status. To fully meet the performance requirement, GL852 series is a multiple TT hub solution to provide every down stream port with a TT. With the dedicated TT in each down stream port, GL852 can provide the best performance even connect with several Full/Low-Speed devices and running heavy bandwidth-consuming operations concurrently. *TT (transaction translator) is the main traffic control engine in an USB 2.0 hub to handle the unbalanced traffic speed between the upstream port and the downstream ports. Product Name GL852 GL852 GL852 Package type 64LQFP 48LQFP 48QFN Power mode Individual/Gang Individual/Gang Individual/Gang LED support Green/Amber Green/Amber Green/Amber ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 7 GL852 USB 2.0 MTT HUB Controller CHAPTER 2 FEATURES • Compliant to USB specification Revision 2.0 − 4 downstream ports − Upstream port supports both high-speed (HS) and full-speed (FS) traffic − Downstream ports support HS, FS, and low-speed (LS) traffic − 1 control pipe (endpoint 0, 64-byte data payload) and 1 interrupt pipe (endpoint 1, 1-byte data payload) − Backward compatible to USB specification Revision 1.1 On-chip 8-bit micro-processor − RISC-like architecture − USB optimized instruction set − Dual cycle instruction execution − Performance: 6 MIPS @ 12MHz − With 64-byte RAM and 2K internal ROM − Support customized PID, VID by reading external EEPROM − Support downstream port configuration by reading external EEPROM Multiple Transaction translator (MTT) − MTT provides respective TT control logics for each downstream port. This is a performance better choice for USB 2.0 hub. Each downstream port supports two-color status indicator, with automatic and manual modes compliant to USB specification Revision 2.0 Support both individual and gang modes of power management and over-current detection for downstream ports Support gang mode of power management and over-current detection for downstream ports Conform to bus power requirements Automatic switching between self-powered and bus-powered modes Integrate USB 2.0 transceiver PLL embedded with external 12 MHz crystal Operate on 3.3 Volts Embed serial resister for USB signals and integrate pull-up resister for upstream USB signal Improve output drivers with slew-rate control for EMI reduction Internal power-fail detection for ESD recovery 64-pin LQFP package , 48-pin LQFP package , 48-pin QFN package Applications: − Stand-alone USB hub − Monitor hub − PC motherboard USB hub, Docking of notebook − Any compound device to support USB HUB function • • • • • • • • • • • • • • • ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 8 GL852 USB 2.0 MTT HUB Controller CHAPTER 3 PIN ASSIGNMENT 3.1 Pinouts GREEN2/EE_DO PWREN3# PWREN4# OVCUR3# OVCUR4# AMBER3 AMBER4 GREEN3 GREEN4 34 RESET# DVDD DGND DVDD DGND TEST 48 AMBER2/EE_DI PSELF DGND DVDD PGANG/SUSPND 47 46 45 44 43 42 41 40 39 38 37 36 35 33 32 31 30 29 28 27 26 25 DP4 DM4 NC AGND AVDD NC DP3 DM3 NC AGND AVDD X2 X1 AGND AVDD RREF 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 OVCUR2# PWREN2# OVCUR1# PWREN1# DGND DVDD GREEN1/EE_SK AMBER1/EE_CS DGND DVDD AVDD GL852 LQFP - 64 NC 24 23 22 21 20 19 18 17 NC AGND AVDD ANGD NC NC NC NC NC DP0 DP1 NC DM0 DM1 Figure 3.1 GL852 64 Pin LQFP Pinout Diagram ©2000-2007 Genesys Logic Inc. - All rights reserved. DM2 DP2 － － － － Page 9 GL852 USB 2.0 MTT HUB Controller AMBER2/EE_DI PWREN3# PWREN4# OVCUR3# OVCUR4# AMBER3 GREEN2 GREEN3 RESET# 26 DVDD 36 35 34 33 32 31 30 29 28 27 PSELF DVDD PGANG OVCUR2# PWREN2# OVCUR1# PWREN1# DVDD GREEN1/EE_SK AMBER1/EE_CS DGND DVDD 37 38 39 40 41 42 43 44 45 46 47 48 25 DVDD TEST 24 23 22 21 20 19 AMBER4 GREEN4 DP4 DM4 AGND AVDD DP3 DM3 AVDD X2 X1 AGND GL852 LQFP - 48 18 17 16 15 14 13 10 11 RREF DP0 DP1 DM0 DM1 AVDD AGND AVDD AGND DM2 DP2 Figure 3.2 GL852 48 Pin LQFP Pinout Diagram ©2000-2007 Genesys Logic Inc. - All rights reserved. AVDD 12 1 2 3 4 5 6 7 8 9 － － － － Page 10 GL852 USB 2.0 MTT HUB Controller AMBER2/EE_DI PWREN3# PWREN4# OVCUR3# OVCUR4# AMBER3 GREEN2 GREEN3 RESET# 26 DVDD 36 35 34 33 32 31 30 29 28 27 PSELF DVDD PGANG OVCUR2# PWREN2# OVCUR1# PWREN1# DVDD GREEN1/EE_SK AMBER1/EE_CS DGND DVDD 37 38 39 40 41 42 43 44 45 46 47 48 25 DVDD TEST 24 23 22 21 20 19 AMBER4 GREEN4 DP4 DM4 AGND AVDD DP3 DM3 AVDD X2 X1 AGND GL852 QFN - 48 18 17 16 15 14 13 10 11 RREF DP0 DP1 DM0 DM1 AVDD AGND AVDD AGND DM2 DP2 Figure 3.2 GL852 48 Pin QFN Pinout Diagram ©2000-2007 Genesys Logic Inc. - All rights reserved. AVDD 12 1 2 3 4 5 6 7 8 9 － － － － Page 11 GL852 USB 2.0 MTT HUB Controller 3.2 Pin List Table 3.1 Pin# 1 2 3 4 5 6 7 8 9 Pin Name AGND NC DM0 DP0 NC NC NC DM1 DP1 Type Pin# P B B B B P P B B - Pin Name 17 RREF 18 AVDD 19 AGND 2 0 X1 21 X2 22 AVDD 23 AGND 2 4 NC 25 DM3 26 DP3 2 7 NC 28 AVDD 29 AGND 3 0 NC 31 DM4 32 DP4 1 0 NC 11 AVDD 12 AGND 1 3 NC 14 DM2 15 DP2 1 6 NC Table 3.2 Pin# 1 2 3 4 5 6 7 8 9 Pin Name AVDD AGND DM0 DP0 DM1 DP1 AVDD AGND DM2 Type Pin# P P B B B B P P B B Pin Name 13 AGND 1 4 X1 1 5 X2 16 AVDD 17 DM3 18 DP3 19 AVDD 20 AGND 21 DM4 22 DP4 10 DP2 ©2000-2007 Genesys Logic Inc. - All rights reserved. － － － － － － － － GL852 64 Pin List Type Pin# B P P I O P P B B P P B B Pin Name Type Pin# O O P P I I I O I O O O P P B 49 Pin Name AMBER2/ EE_DI Type O I P P B I O I O P P O O P P P 3 3 NC 34 GREEN4 35 AMBER4 36 DGND 37 DVDD 38 RESET# 39 TEST 40 OVCUR4# 41 PWREN4# 42 OVCUR3# 43 PWREN3# 44 GREEN3 45 AMBER3 46 DGND 47 DVDD 48 GREEN2/ EE_DO 50 PSELF 51 DGND 52 DVDD PGANG/ 53 SUSPND 54 OVCUR2# 55 PWREN2# 56 OVCUR1# 57 PWREN1# 58 DGND 59 DVDD GREEN1/ 60 EE_SK AMBER1/ 61 EE_CS 62 DGND 63 AVDD 64 AVDD GL852 48 Pin List Type Pin# P I O P B B P P B B Pin Name Type Pin# P I I I O I O O O P Pin Name Type I P B I O I O P O O 25 DVDD 26 RESET# 27 TEST 28 OVCUR4# 29 PWREN4# 30 OVCUR3# 31 PWREN3# 32 GREEN3 33 AMBER3 34 DVDD 37 PSELF 38 DVDD 39 PGANG 40 OVCUR2# 41 PWREN2# 42 OVCUR1# 43 PWREN1# 44 DVDD 45 46 GREEN1/ EE_SK AMBER1/ EE_CS Page 12 GL852 USB 2.0 MTT HUB Controller GREEN2/ EE_DO AMBER2/ EE_DI 11 RREF 12 AVDD B P 23 GREEN4 24 AMBER4 O O 35 36 O O 47 DGND 48 DVDD P P 3.3 Pin Descriptions Table 3.3 - Pin Descriptions USB Interface Pin Name DM0,DP0 DM1,DP1 DM2,DP2 DM3,DP3 DM4,DP4 RREF GL852 64 Pin# 3,4 8,9 14,15 25,26 31,32 17 GL852 48Pin# 3,4 5,6 9,10 17,18 21,22 11 B B B B B B USB signals for USPORT USB signals for DSPORT1 USB signals for DSPORT2 USB signals for DSPORT3 USB signals for DSPORT4 A 680 resister must be connected between RREF and analog ground (AGND). I/O Type Description Note: USB signals must be carefully handled in PCB routing. For detailed information, please refer to GL852 Design Guideline. HUB Interface Pin Name GL852 64 Pin# OVCUR1#~4 GL852 48Pin# I/O Type I (pu) Description 56,54, 42,40 57,55, 43,41 60,48, 44,34 61,49, 45,35 50 PWREN1#~4 GREEN1~4 AMBER1~4 PSELF PGANG/ SUSPND 53 Active low. Over current indicator for DSPORT1~4 OVCUR1# is the only over current flag for GANG mode. Active low. Power enable output for DSPORT1~4 PWREN1# is the only power-enable output for GANG 43,41,31,29 O mode. 1,3,4: O Green LED indicator for DSPORT1~4 45,35,32,23 2: B *GREEN[1~2] are also used to access the external EEPROM For detailed information, please refer to Chapter 5. (pd) O Amber LED indicator for DSPORT1~4 46,36,33,24 (pd) *Amber [1~2] are also used to access the external EEPROM 0: GL852 is bus-powered. 37 I 1: GL852 is self-powered. This pin is default put in input mode after power-on reset. Individual/gang mode is strapped during this period. After the strapping period, this pin will be set to output mode, and then output high for normal mode. 39 B When GL852 is suspended, this pin will output low. *For detailed explanation, please see Chapter 5 Gang input:1, output: 0@normal, 1@suspend Individual input:0, output: 1@normal, 0@suspend 42,40,30,28 ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 13 GL852 USB 2.0 MTT HUB Controller Clock and Reset Interface Pin Name X1 X2 RESET# GL852 64Pin# 20 21 38 GL852 48Pin# 14 15 26 I O I 12MHz crystal clock input. 12MHz crystal clock output. Active low. External reset input, default pull high 10K . When RESET# = low, whole chip is reset to the initial state. I/O Type Description System Interface Pin Name TEST GL852 64 Pin# 39 GL852 48Pin# 27 I (pd) 0: Normal operation. 1: Chip will be put in test mode. I/O Type Description Power / Ground Pin Name AVDD AGND DVDD DGND GL852 64 Pin# GL852 48Pin# P P P P 3.3V analog power input for analog circuits. Analog ground input for analog circuits. 3.3V digital power input for digital circuits I/O Type Description 11,18,22, 1,7,12,16,19 28,64 1,12,19, 23,29 37,47, 52,59 36,46, 51,58,62 2,5~7,10, 13,16,24, 27,30,33 2,8,13,20, 25,34,38,44, 48 47 Digital ground input for digital circuits. NC - - No connection Note: Analog circuits are quite sensitive to power and ground noise. PCB layout must take care the power routing and the ground plane. For detailed information, please refer to GL852 Design Guideline. Notation: Type O I B B/I B/O P A SO pu pd odpu Output Input Bi-directional Bi-directional, default input Bi-directional, default output Power / Ground Analog Automatic output low when suspend Internal pull up Internal pull down Open drain with internal pull up ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 14 GL852 USB 2.0 MTT HUB Controller CHAPTER 4 BLOCK DIAGRAM 12MHz D+ D- USPORT FRTIMER Transceiver PLL x40, x10 RAM ROM GPIO CPU USPORT UTMI Logic SIE Control/Status Register TT REPEATER (Transaction Translator) TT (Transaction Translator) TT (Transaction Translator) TT (Transaction Translator) REPEATER / TT Routing Logic DSPORT1 Logic DSPORT2 Logic DSPORT3 Logic DSPORT4 Logic DSPORT Transceiver DSPORT Transceiver DSPORT Transceiver DSPORT Transceiver D+ D- LED/ OVCUR/ PWRENB D+ D- LED/ OVCUR/ PWRENB D+ D- LED/ OVCUR/ PWRENB D+ D- LED/ OVCUR/ PWRENB Figure 4.1 - GL852 Block Diagram (multiple TT) ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 15 GL852 USB 2.0 MTT HUB Controller CHAPTER 5 FUNCTION DESCRIPTION 5.1 General 5.1.1 USPORT Transceiver USPORT (upstream port) transceiver is the analog circuit that supports both full-speed and high-speed electrical characteristics defined in chapter 7 of USB specification Revision 2.0. USPORT transceiver will operate in full-speed electrical signaling when GL852 is plugged into a 1.1 host/hub. USPORT transceiver will operate in high-speed electrical signaling when GL852 is plugged into a 2.0 host/hub. 5.1.2 PLL (Phase Lock Loop) GL852 contains a 40x PLL. PLL generates the clock sources for the whole chip. The generated clocks are proven quite accurate that help in generating high speed signal without jitter. 5.1.3 FRTIMER This module implements hub (micro)frame timer. The (micro)frame timer is derived from the hub’s local clock and is synchronized to the host (micro)frame period by the host generated Start of (micro)frame (SOF). FRTIMER keeps tracking the host’s SOF such that GL852 is always safely synchronized to the host. The functionality of FRTIMER is described in section 11.2 of USB Specification Revision 2.0. 5.1.4 µC µC is the micro-processor unit of GL852. It is an 8-bit RISC processor with 2K ROM and 64 bytes RAM. It operates at 6MIPS of 12Mhz clock to decode the USB command issued from host and then prepares the data to respond to the host. In addition, µC can handle GPIO (general purpose I/O) settings and reading content of EEPROM to support high flexibility for customers of different configurations of hub. These configurations include self/bus power mode setting, individual/gang mode setting, downstream port number setting, device removable/non-removable setting, and PID/VID setting. 5.1.5 UTMI (USB 2.0 Transceiver Macrocell Interface) UTMI handles the low level USB protocol and signaling. It’s designed based on the Intel’s UTMI specification 1.01. The major functions of UTMI logic are to handle the data and clock recovery, NRZI encoding/decoding, Bit stuffing /de-stuffing, supporting USB 2.0 test modes, and serial/parallel conversion. 5.1.6 USPORT logic USPORT implements the upstream port logic defined in section 11.6 of USB specification Revision 2.0. It mainly manipulates traffics in the upstream direction. The main functions include the state machines of Receiver and Transmitter, interfaces between UTMI and SIE, and traffic control to/from the REPEATER and TT. 5.1.7 SIE (Serial Interface Engine) SIE handles the USB protocol defined in chapter 8 of USB specification Revision 2.0. It co-works with C to play the role of the hub kernel. The main functions of SIE include the state machine of USB protocol flow, CRC check, PID error check, and timeout check. Unlike USB 1.1, bit stuffing/de-stuffing is implemented in UTMI, not in SIE. 5.1.8 Control/Status register Control/Status register is the interface register between hardware and firmware. This register contains the information necessary to control endpoint0 and endpoint1 pipelines. Through the firmware based architecture, GL852 possesses higher flexibility to control the USB protocol easily and correctly. 5.1.9 REPEATER Repeater logic implements the control logic defined in section 11.4 and section 11.7 of USB specification Revision 2.0. REPEATER controls the traffic flow when upstream port and downstream port are signaling in the same speed. In addition, REPEATER will generate internal resume signal whenever a wakeup event is issued under the situation that hub is globally suspended. ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 16 μ GL852 USB 2.0 MTT HUB Controller 5.1.10. TT (Transaction Translator) TT implements the control logic defined in section 11.14 ~ 11.22 of USB specification Revision 2.0. TT basically handles the unbalanced traffic speed between the USPORT (operating in HS) and DSPORTS (operating in FS/LS) of hub. GL852 adopts multiple TT architecture to provide the most performance effective solution. Multiple TT provides control logics for each downstream port respectively. 5.1.11 REPEATER/TT routing logic REPEATER and TT are the major traffic control machines in the USB 2.0 hub. Under situation that USPORT and DSPORT are signaling in the same speed, REPEATER/TT routing logic switches the traffic channel to the REPEATER. Under situation that USPORT is in the high speed signaling and DSPORT is in the full/low speed signaling, REPEATER/TT routing logic switches the traffic channel to the TT. 5.1.11.1 Connected to 1.1 Host/Hub If an USB 2.0 hub is connected to the downstream port of an USB 1.1 host/hub, it will operate in USB 1.1 mode. For an USB 1.1 hub, both upstream direction traffic and downstream direction traffic are passing through REPEATER. That is, the REPEATER/TT routing logic will route the traffic channel to the REPEATER. USB1.1 HOST/HUB USPORToperating in FS signaling Traffic channel is routed to REPEATER REPEATER TT TT DSPORT operating in FS/LS signaling Figure 5.1 - Operating in USB 1.1 scheme 5.1.11.2 Connected to USB 2.0 Host/Hub If an USB 2.0 hub is connected to an USB 2.0 host/hub, it will operate in USB 2.0 mode. The upstream port signaling is in high speed with bandwidth of 480 Mbps under this environment. The traffic channel will then be routed to the REPEATER when the device connected to the downstream port is signaling also in high speed. On the other hand, the traffic channel will then be routed to TT when the device connected to the downstream port is signaling in full/low speed. ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 17 GL852 USB 2.0 MTT HUB Controller USB2.0 HOST/HUB USPORToperating in HS signaling HS vs. HS: Traffic channel is routed to REPEATER REPEATER TT TT HS vs. FS/LS: Traffic channel is routed to TT DSPORT operating in HS signaling DSPORT operating in FS/LS signaling Figure 5.2 - Operating in USB 2.0 scheme 5.12 DSPORT logic DSPORT (downstream port) logic implements the control logic defined in section 11.5 of USB specification Revision 2.0. It mainly manipulates the state machine, the connection/disconnection detection, over current detection and power enable control, and the status LED control of the downstream port. Besides, it also output the control signals to the DSPORT transceiver. 5.13 DSPORT Transceiver DSPORT transceiver is the analog circuit that supports high-speed, full-speed, and low-speed electrical characteristics defined in chapter 7 of USB specification Revision 2.0. In addition, each DSPORT transceiver accurately controls its own squelch level to detect the detachment and attachment of devices. 5.2 Configuration and I/O Settings 5.2.1 RESET# Setting GL852 integrates in the pull-up 1.5K resister of the upstream port. When RESET# is enabled, the internal 1.5K pull-up resister will be disconnected to the 3.3V power. To meet the requirement (p.141) of the USB 2.0 specification, pull-up resister should be disconnected while lacking of USB cable power (Vbus). Therefore, we suggest designing the RESET# circuit as following figure to meet the requirement mentioned above. ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 18 GL852 USB 2.0 MTT HUB Controller Figure 5.3 - RESET# (External Reset) setting and application GL852 internally contains a power on reset circuit. The power on sequence is depicted in the next picture. To fully control the reset process of GL852, we suggest the reset time applied in the external reset circuit should longer than that of the internal reset circuit. VCC(3.3V) Power good voltage, 2.5~2.8V Internal reset External reset Figure 5.4 - Power on sequence of GL852 5.2.2 PGANG/SUSPND Setting To save pin count, GL852 uses the same pin to decide individual/gang mode as well as to output the suspend flag. The individual/gang mode is decided within 20us after power on reset. Then, about 50ms later, this pin is changed to output mode. GL852 outputs the suspend flag once it is globally suspended. For individual mode, a pull low resister greater than 100K should be placed. For gang mode, a pull high resister which greater than 100K should be placed. In figure 5.6, we also depict the suspend LED indicator schematics. It should be noticed that the polarity of LED must be followed, otherwise the suspend current will be over spec limitation (2.5mA). ©2000-2007 Genesys Logic Inc. - All rights reserved. μ≒ 2.7 s Page 19 GL852 USB 2.0 MTT HUB Controller RESET# 50 ms GANG_CTL Input mode, strapping to decide individual or gang mode Output mode, indicating GL852 is in normal mode or suspend mode Figure 5.5 - Timing of PGANG/SUSPND strapping GAND Mode DVDD(3.3V) DVDD(3.3V) "0": Individual Mode "1": GANG Mode 100K ohm Suspend LED Indicator SUSPNDO GANG_CTL 100K ohm Inside GL852 On PCB Individual Mode 5.2.3 SELF/BUS Power Setting GL852 can operate under bus power and conform to the power consumption limitation completely (suspend current < 2.5 mA, normal operation current < 100 mA). By setting PSELF, GL852 can be configured as a bus-power or a self-power hub. ©2000-2007 Genesys Logic Inc. - All rights reserved. GNAGP Suspend LED Indicator Figure 5.6 - GANG Mode Setting Page 20 GL852 USB 2.0 MTT HUB Controller 1: Power Self PSELF 0: Power Bus Inside GL852 On PCB Figure 5.7 - SELF/BUS Power Setting 5.2.4 LED Connections GL852 controls the LED lighting according to the flow defined in section 11.5.3 of Universal Serial Bus Specification Revision2.0. Both manual mode and Automatic mode are supported in GL852. When GL852 is globally suspended, GL852 will turn off the LED to save power. AMBER/GREEN LED DGND Inside GL852 On PCB Figure 5.8 - LED Connection 5.2.5 EEPROM Setting GL852 replies to host commands by the default settings in the internal ROM. GL852 also offers the ability to reply to the host according to the settings in the external EEPROM(93C46). The following table shows the configuration of 93C46. ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 21 GL852 USB 2.0 MTT HUB Controller Table 5.1 - 93C46 Configuration Unit: Byte 00 00h 10h 20h 30h 40h 50h 60h 70h SERIAL NUMBER LENGTH PRODUCT LENGTH 01 02 03 04 05 06 07 08 MaxPower 09 0A 0B 0C 0D 0E 0F FF FF FF FF FF FF FF VID_L VENDOR LENGTH VID_H PID_L PID_H CHKSUM FF PORT DEVICE REMOVABLE NUMBER start Vendor string (ASC II code) end start Product String(ASC II code) end start end Serial Number String(ASC II code) Note: 1. VID_H/VID_L: high/low byte of VID value 2. PID_H/PID_L: high/low byte of PID value 3. CHKSUM: CHKSUM must equal to VID_H + VID_L + PID_H + PID_L + 1,otherwise firmware will ignore the EEPROM settings. 4. PORT_NO: port number, value must be 1~4. 5. MaxPower : Describe the maximum power consumption, range=0Ma~500Ma . Value -> 00H~FAH (unit = 2Ma) 6. DEVICE REMOVALBE: PORT4 PORT3 PORT2 PORT1 REMOVABLE REMOVABLE REMOVABLE REMOVABLE 0: Device attached to this port is removable. 1: Device attached to this port is non-removable. - 7. VENDOR LENGTH: offset 10h contains the length of the vendor string. Values of vendor string is contained from 11h~3Fh. 8. PRODUCT LENGTH: offset 40h contains the length of product string. Values of product string is contained from 41h~6Fh. 9. SERIAL NUMBER LENGTH: offset 70h contains the value of serial number string. Values of serial number string is contained after offset 71h. ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 22 GL852 USB 2.0 MTT HUB Controller The schematics between GL852 and 93C46 is depicted in the following figures: DVDD EE_CS EE_SK EE_DI EE_DO CS SK DI DO VCC NC NC GND 93C46 Figure 5.9 - Schematics Between GL852 and 93C46 GL852 firstly verifies the check sum after power on reset. If the check sum is correct, GL852 will take the configuration of 93C46 as part of the descriptor contents. To prevent the content of 93C46 from being over-written, amber LED will be disabled when 93C46 exists. ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 23 GL852 USB 2.0 MTT HUB Controller CHAPTER 6 ELECTRICAL CHARACTERISTICS 6.1 Maximum Ratings Table 6.1 - Maximum Ratings Symbol VCC VIN VIN VINUSB TS FOSC Power Supply Input Voltage for digital I/O(EE_DO) pins Input Voltage for digital I/O(Ovcur1-4,Pself,Reset) pins Input Voltage for USB signal (DP, DM) pins Storage Temperature under bias Frequency Parameter Min. -0.5 -0.5 -0.5 -0.5 -60 Max. +3.6 +3.6 +5.25 +3.6 +100 12 MHz ± 0.05% Unit V V V V o C 6.2 Operating Ranges Table 6.2 - Operating Ranges Symbol VCC VIND VINUSB TA TJ Power Supply Input Voltage for digital I/O pins Input Voltage for USB signal (DP, DM) pins Ambient Temperature Absolute maximum junction temperature Thermal Characteristics 48 LQFP Parameter Min. 3.0 -0.5 0.5 0 0 - Typ. 3.3 3.3 3.3 52.2 Max. 3.6 3.6 3.6 70 125 - Unit V V V o o o C C 6.3 DC Characteristics Table 6.3 - DC Characteristics Except USB Signals Symbol PD VDD VIL VIH VTLH VTHL VOL VOH IOLK RDN Power Dissipation Power Supply Voltage LOW level input voltage HIGH level input voltage LOW to HIGH threshold voltage HIGH to LOW threshold voltage LOW level output voltage when IOL=8mA HIGH level output voltage when IOH=8mA Leakage current for pads with internal pull up or pull down resistor Pad internal pull down resister ©2000-2007 Genesys Logic Inc. - All rights reserved. θ JA C/W Parameter Min. 70 3 2.0 1.36 1.36 2.4 81K Typ. 3.3 1.48 1.48 103K Max. 190 3.6 0.9 1.62 1.62 0.4 30 181K Unit mA V V V V V V V µA Page 24 GL852 USB 2.0 MTT HUB Controller RUP Pad internal pull up resister 81K 103K 181K Table 6.4 - DC Characteristics of USB Signals Under FS/LS Mode Symbol VOL VOH VDI VCM VSE CIN ILO ZDRV Parameter DPF/DMF static output LOW(RL of 1.5K to 3.6V ) DPF/DMF static output HIGH (RL of 15K to GND ) Differential input sensitivity Differential common mode range Single-ended receiver threshold Transceiver capacitance Hi-Z state data line leakage Driver output resistance Min. 0 2.8 0.2 0.8 0.2 -10 28 Typ. - Max. 0.3 3.6 2.5 20 +10 43 Unit V V V V V pF µA Table 6.5 - DC Characteristics of USB Signals Under HS Mode Symbol VOL CIN ILO ZDRV Parameter DPH/DMH static output LOW(RL of 1.5K to 3.6V ) Transceiver capacitance Hi-Z state data line leakage Driver output resistance for USB 2.0 HS Min. 4 -5 48 Typ. 4.5 0 45 Max. 0.1 5 +5 42 Unit V pF µA ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 25 GL852 USB 2.0 MTT HUB Controller 6.4 Power Consumption Table 6.6 - DC Supply Current Symbol Active ports ISUSP Condition Host Suspend F 4 *2 Typ. Device 510/800*1 F H F F H F F H F F H F 83 187 107 82 170 106 81 147 105 79 124 104 78 102 Unit µA mA mA mA mA mA mA mA mA mA mA mA mA mA mA H H F 3 H H F ICC 2 H H F 1 H H No Active *1: 48/64-pin package types *2: F: Full-Speed, H: High-Speed F H ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 26 GL852 USB 2.0 MTT HUB Controller 6.5 AC Characteristics Symbol tCSS tCSH tSKH tSKL tDIS tDIH tPD1 tPD0 Parameter CS Setup Time CS Hold Time SK High Time SK Low Time DI Setup Time DI Hold Time Output Delay to “1” Output Delay to “0” Min 3.0 3.0 1.0 2.2 1.8 2.4 Typ Max Units us 1.8 1.8 Table 6.7 - AC Characteristics of EEPROM Interface ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 27 GL852 USB 2.0 MTT HUB Controller CHAPTER 7 PACKAGE DIMENSION D D1 D2 D A A2 A1 48 49 33 32 A E2 E1 E InternalNo . N : Normal package G : Green package GL852 B AAAAAAAGAA YWWXXXXXXXX Date Code Lot Code 17 1 e 4X b Version No. 64 bbb H A B D L1 16 4X aaa C A B D 0.05 S c 01 0 ddd M C A B s D s C ccc C SEATING PLANE 02 R1 H R2 0.25mm GAGE PLANE S L 03 - NOTES : 1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. DIMENSION b DOES NOT INCLUDE DAMBAR 2. PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08mm. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD IS 0.07mm. CONTROL DIMENSIONS ARE IN MILLIMETERS. MILLIMETER INCH SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. 1.60 0.063 A 0.006 0.05 0.15 0.002 A1 1.35 1.40 1.45 0.053 0.055 0.057 A2 12.00 BASIC 0.472 BASIC D 12.00 BASIC 0.472 BASIC E D1 10.00 BASIC 0.393 BASIC E1 10.00 BASIC 0.393 BASIC 7.50 BASIC 0.295 BASIC D2 7.50 BASIC 0.295 BASIC E2 R1 0.08 0.003 R2 0.08 0.20 0.003 0.008 0 0 3.5 7 0 3.5 7 0 0 01 02 11 12 13 11 12 13 03 11 12 13 11 12 13 0.20 0.004 0.008 0.09 c 0.45 0.60 0.75 0.018 0.024 0.030 L 1.00 REF 0.039 REF L1 0.20 0.008 S 0.27 0.007 0.008 0.011 0.17 0.20 b 0.50 BASIC 0.020 BASIC e TOLERANCES OF FORM AND POSITION aaa 0.20 0.008 0.008 0.20 bbb 0.08 0.003 ccc 0.08 0.003 ddd Figure 7.1 - GL852 64 Pin LQFP Package ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 28 GL852 USB 2.0 MTT HUB Controller D D1 D2 D A A2 0.05 S A1 36 37 25 24 Internal No. A E1 E2 E N : Normal package G : Green package GL852 B AAAAAAAGAA YWWXXXXXXXX Date Code Lot Code 48 1 e b 4X Version No. 13 bbb H A B D L1 12 4X aaa C A B D c 01 0 ddd M C A B s D s C ccc C SEATING PLANE 02 R1 H R2 0.25mm GAGE PLANE S L 03 - NOTES : 1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 2. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08mm. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD IS 0.07mm. CONTROL DIMENSIONS ARE IN MILLIMETERS. MILLIMETER INCH SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. 1.60 0.063 A 0.006 0.05 0.15 0.002 A1 1.35 A2 1.40 1.45 0.053 0.055 0.057 9.00 BASIC 0.354 BASIC D E 9.00 BASIC 0.354 BASIC 0.276 BASIC D1 7.00 BASIC E1 7.00 BASIC 0.276 BASIC 5.50 BASIC D2 0.217 BASIC 5.50 BASIC 0.217 BASIC E2 R1 0.08 0.003 R2 0.08 0.20 0.003 0.008 0 0° 3.5° 7° 0° 3.5° 7° 0° 01 0° 02 11° 12° 13° 11° 12° 13° 03 11° 12° 13° 11° 12° 13° 0.09 0.20 0.004 0.008 c 0.45 0.60 0.75 0.018 0.024 0.030 L L1 1.00 REF 0.039 REF 0.20 0.008 S 0.17 0.20 0.27 0.007 0.008 0.011 b 0.50 BASIC 0.020 BASIC e TOLERANCES OF FORM AND POSITION aaa 0.20 0.008 0.008 bbb 0.20 0.08 0.003 ccc 0.08 0.003 ddd Figure 7.2 – GL852 48 Pin LQFP Package ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 29 GL852 USB 2.0 MTT HUB Controller Figure 7.2 – GL852 48 Pin QFN Package ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 30 GL852 USB 2.0 MTT HUB Controller CHAPTER 8 ORDERING INFORMATION Table 8.1 - Ordering Information Part Number GL852-MSNXX GL852-MNNXX GL852-MSGXX GL852-MNGXX GL852-ONGXX Package 64-pin LQFP 48-pin LQFP 64-pin LQFP 48-pin LQFP 48-pin QFN Normal/Green Normal Package Normal Package Green Package Green Package Green Package Version XX XX XX XX XX Status Available Available Available Available Available ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 31