GL852G-HHG12

035/4 Genesys Logic, Inc. GL852G USB 2.0 MTT Hub Controller Datasheet Revision 1.32 Mar. 31, 2015 GL852G Datasheet Copyright Copyright © 2015 Genesys Logic, Inc. All rights reserved. No part of the materials shall be reproduced in any form or by any means without prior written consent of Genesys Logic, Inc. Ownership and Title Genesys Logic, Inc. owns and retains of its right, title and interest in and to all materials provided herein. Genesys Logic, Inc. reserves all rights, including, but not limited to, all patent rights, trademarks, copyrights and any other propriety rights. No license is granted hereunder. Disclaimer All Materials are provided “as is”. Genesys Logic, Inc. makes no warranties, express, implied or otherwise, regarding their accuracy, merchantability, fitness for any particular purpose, and non-infringement of intellectual property. In no event shall Genesys Logic, Inc. be liable for any damages, including, without limitation, any direct, indirect, consequential, or incidental damages. The materials may contain errors or omissions. Genesys Logic, Inc. may make changes to the materials or to the products described herein at anytime without notice. Genesys Logic, Inc. 12F., No. 205, Sec. 3, Beixin Rd., Xindian Dist. 231, New Taipei City, Taiwan Tel : (886-2) 8913-1888 Fax : (886-2) 6629-6168 http ://www.genesyslogic.com © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 2 GL852G Datasheet Revision History Revision Date Description 1.00 1.01 05/26/2009 06/18/2009 1.02 09/01/2009 1.03 1.04 1.05 10/23/2009 11/04/2009 05/17/2010 1.06 06/04/2010 1.07 12/27/2010 1.08 03/22/2011 1.09 1.10 1.20 1.21 1.22 1.23 1.24 1.25 1.26 1.27 1.28 1.29 1.30 1.31 1.32 04/21/2011 05/11/2011 07/15/2011 07/15/2011 08/26/2011 11/21/2011 12/22/2011 01/03/2012 05/16/2012 08/31/2012 12/28/2012 05/17/2013 05/30/2013 03/03/2014 03/31/2015 First formal release Add On-chip power regulator spec, Ch6.6, p.28 Update 3.3 pin description,p.14 Update table-6.2 operating ranges, p.24 Update table-6.3 power dissipation, p.25 Update Ch8 order information, p.32 Modify table 5.3 – port number configuration, p.23 Update Table 6.6 – DC Supply Current, p.26 Update Table 6.6 – DC Supply Current for GL852G-1x version, p.26 Update Table 5.3 – port number configuration for GL852G-1x version, p.24 Add SSOP28 package information, p.8, 9, 12~15, 26 Modify Ch2 features, p.9 Modify 5.2.5 EEPROM Setting, p.24 Modify 6.6 On-Chip Power Regulator, p.31 Modify SSOP28 pinout, p.12~15 Update table-6.3 DC characteristics except USB signals, p.27 Add LQFN 46 package information, p8, 9, 13, 15~17, 26, 27, 37, 38 Modify SSOP28 package dimension information, p.36 Update Table 3.3 pin description, RREF I/O type, p.16 Update Table 3.1, 3.2, 3.3, 3.4, 3.5 RREF I/O type, p.14~16 Update Table-6.3 DC characteristics except USB signals (RDN, RUP), p.29 Update Table 3.5 Pin Description, p.17 Updated Table 6.2 Operating Ranges, p.28 Updated Table 3.5 Pin Descriptions, p.17 Modified CH8 Ordering Information, p.38 Updated Table 6.6 - GL852G Power Consumption, p. 30 Modified Typo, p. 38 Updated CH1 General Description, p. 8 Updated CH5.2.8 Non-removable Port Configuration, p. 28 Updated Reset Timing Information, p. 24, 25 Removed LQFN46 Package Information. © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 3 GL852G Datasheet Table of Contents CHAPTER 1 GENERAL DESCRIPTION ........................................................................ 8 CHAPTER 2 FEATURES.................................................................................................... 9 CHAPTER 3 PIN ASSIGNMENT .................................................................................... 10 3.1 Pinouts ......................................................................................................................... 10 3.2 Pin List ......................................................................................................................... 13 3.3 Pin Descriptions .......................................................................................................... 14 CHAPTER 4 BLOCK DIAGRAM ................................................................................... 17 CHAPTER 5 FUNCTION DESCRIPTION ..................................................................... 18 5.1 General Description.................................................................................................... 18 5.1.1 USPORT Transceiver ......................................................................................... 18 5.1.2 PLL (Phase Lock Loop) ..................................................................................... 18 5.1.3 FRTIMER ........................................................................................................... 18 5.1.4 μC ......................................................................................................................... 18 5.1.5 UTMI (USB 2.0 Transceiver Microcell Interface) ........................................... 18 5.1.6 USPORT Logic ................................................................................................... 18 5.1.7 SIE (Serial Interface Engine) ............................................................................. 18 5.1.8 Control/Status Register ...................................................................................... 18 5.1.9 REPEATER ........................................................................................................ 19 5.1.10 TT (Transaction Translator) ........................................................................... 19 5.1.11 REPEATER/TT Routing Logic ....................................................................... 19 5.1.12 DSPORT Logic ................................................................................................. 20 5.1.13 DSPORT Transceiver ....................................................................................... 20 5.2 Configuration and I/O Settings ................................................................................. 21 5.2.1 RESET Setting .................................................................................................... 21 5.2.2 PGANG Setting ................................................................................................... 22 5.2.3 SELF/BUS Power Setting .................................................................................. 23 5.2.4 LED Connections ................................................................................................ 23 5.2.5 EEPROM Setting ................................................................................................ 24 5.2.6 Power Switch Enable Polarity (Only Available for LQFP48 Package) ......... 24 5.2.7 Port Number Configuration (Only Available for LQFP48 Package) ............ 24 5.2.8 Non-removable Port Configuration (Only Available for LQFP48 Package)....... 25 5.2.9 Reference Clock Configuration (Only Available for LQFP48 Package) ....... 25 © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 4 GL852G Datasheet CHAPTER 6 ELECTRICAL CHARACTERISTICS..................................................... 26 6.1 Maximum Ratings ...................................................................................................... 26 6.2 Operating Ranges ....................................................................................................... 26 6.3 DC Characteristics ..................................................................................................... 26 6.4 Power Consumption ................................................................................................... 27 6.5 AC Characteristics ..................................................................................................... 28 6.5.1 93C46 EEPROM IF ............................................................................................ 28 6.5.2 24C02 EEPROM Interface ................................................................................ 29 6.6 On-Chip Power Regulator ......................................................................................... 30 CHAPTER 7 PACKAGE DIMENSION .......................................................................... 31 CHAPTER 8 ORDERING INFORMATION .................................................................. 34 © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 5 GL852G Datasheet List of Figures Figure 3.1 - GL852G 48 Pin LQFP Pinout Diagram .......................................................... 10 Figure 3.2 - GL852G 28 Pin QFN Pinout Diagram ............................................................. 11 Figure 3.3 - GL852G SSOP 28 Pin Pinout Diagram ........................................................... 12 Figure 4.1 - GL852G Block Diagram (Multiple TT) ........................................................... 17 Figure 5.1 - Operating in USB 1.1 Schemes ......................................................................... 19 Figure 5.2 - Operating in USB 2.0 Schemes ......................................................................... 20 Figure 5.3 - Power on Reset Diagram ................................................................................... 21 Figure 5.4 - Power on Sequence of GL852G ........................................................................ 21 Figure 5.5 - Timing of PGANG Strapping ........................................................................... 22 Figure 5.6 - GANG Mode Setting ......................................................................................... 22 Figure 5.7 - SELF/BUS Power Setting ................................................................................. 23 Figure 5.8 - LED Connection ................................................................................................ 23 Figure 5.9 - Schematics between GL852G and 93C46 ........................................................ 24 Figure 6.1 - Vin(V5) vs Vout(V33)* ...................................................................................... 30 Figure 7.1 - GL852G 48 Pin LQFP Package ........................................................................ 31 Figure 7.2 - GL852G 28 Pin QFN Package .......................................................................... 32 Figure 7.3 - GL852G 28 Pin SSOP Package ........................................................................ 33 © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 6 GL852G Datasheet List of Tables Table 3.1 - GL852G LQFP 48 Pin List ................................................................................. 13 Table 3.2 - GL852G QFN 28 Pin List ................................................................................... 13 Table 3.3 - GL852G SSOP 28 Pin List ................................................................................. 13 Table 3.5 - Pin Descriptions ................................................................................................... 14 Table 5.1 - Reset Timing ........................................................................................................ 22 Table 5.2 - Configuration by Power Switch Type ............................................................... 24 Table 5.3 - Port Number Configuration ............................................................................... 24 Table 5.4 - Ref. Clock Configuration.................................................................................... 25 Table 6.1 - Maximum Ratings ............................................................................................... 26 Table 6.2 - Operating Ranges ................................................................................................ 26 Table 6.3 - DC Characteristics except USB Signals ............................................................ 26 Table 6.4 - DC Characteristics of USB Signals under FS/LS Mode .................................. 27 Table 6.5 - DC Characteristics of USB Signals under HS Mode ....................................... 27 Table 6.6 - GL852G power consumption ............................................................................. 27 Table 6.7 - AC Characteristics of EEPROM Interface (93C46) ........................................ 28 Table 6.8 - AC Characteristics of EEPROM Interface (24C02) ........................................ 29 Table 8.1 - Ordering Information ......................................................................................... 34 © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 7 GL852G Datasheet CHAPTER 1 GENERAL DESCRIPTION GL852G is Genesys Logic’s premium 4-port hub solution which fully complies with Universal Serial Bus Specification Revision 2.0. GL852G implements multiple TT* (Note1) architecture that provide dedicated TT* to each downstream (DS) ports, which guarantee Full-Speed(FS) data passing bandwidth when multiple FS device perform heavy loading operations. The controller inherits Genesys Logic’s cutting edge technology on cost and power efficient serial interface design. GL852G has proven compatibility, lower power consumption figure and better cost structure above all USB2.0 hub solutions worldwide. GL852G implements multiple hub configuration features onto internal mask ROM, which traditionally requires one external EEPROM. The microprocessor detects general purpose I/O (GPIO) status during the initial stage to configure hub settings such as (1) number of DSport, (2) declare of compound device (3) gang/individual mode selection…etc. External EEPROM can be removed if no vendor specified PID/VID or product string is required for the application. GL852G supports three package types, summarized as below table. LQFP48 package provides full hub features such as (1) two-color (green/amber) status LEDs for each DS ports, (2) Individual/Gang mode power management scheme that indicates DS port over-current events. (3) Number of DS ports setting configured by GPIO setting (4) non-removable declaration configured by GPIO setting (5) Support both 93C46 and 24C02 EEPROM (6) power switch polarity selections…etc. QFN28/SSOP28 package support only partial hub features but provide smaller footprint that targets space limited PCB layout environments such as embedded system or UMPC/MID applications. Package Type # of DS Ports Port # Config. Non-removable Declaration Power Mgmt. LED Support EEPROM LQFP 48 4 EEPROM/ GPIO EEPROM/ GPIO Individual/Gang Green/Amber 93C46/ 24C02 QFN 28 4 EEPROM EEPROM Individual/Gang N/A 24C02 SSOP 28 4 EEPROM EEPROM Gang N/A 24C02 GL852G Package – Feature Summary *Note 1: TT (transaction translator) is the main traffic control engine in an USB 2.0 hub to handle the unbalanced traffic speed between the upstream port and the downstream ports. © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 8 GL852G Datasheet CHAPTER 2 FEATURES                   Compliant to USB specification Revision 2.0  4 downstream ports  Upstream port supports both high-speed (HS) and full-speed (FS) traffic  Downstream ports support HS, FS, and low-speed (LS) traffic  1 control pipe (endpoint 0, 64-byte data payload) and 1 interrupt pipe (endpoint 1, 1-byte data payload)  Backward compatible to USB specification Revision 1.1 On-chip 8-bit micro-processor  RISC-like architecture  USB optimized instruction set  Dual cycle instruction execution  Performance: 6 MIPS @ 12MHz  With 64-byte RAM and 9K internal ROM  Support customized PID, VID by reading external EEPROM  Support downstream port configuration by reading external EEPROM Multiple Transaction translator (MTT)  MTT provides respective TT control logics for each downstream port. Each downstream port supports two-color status indicator, with automatic and manual modes compliant to USB specification Revision 2.0 Built-in upstream port 1.5KΩ pull-up and downstream port 15KΩ pull-down resistors Support both individual and gang modes of power management and over-current detection for downstream ports Conform to bus power requirements of USB 2.0 specification Automatic switching between self-powered and bus-powered modes Integrate USB 2.0 transceiver Embedded PLL support external 12 MHz crystal / Oscillator clock input Optional 27/48 MHz Oscillator clock input (Only available in LQFP48 package) Support compound-device (non-removable in downstream ports) by I/O pin configuration (Only available in LQFP48 package) Number of Downstream port can be configured by GPIO without external EEPROM (Only available in LQFP48 package) Built-in 5V to 3.3V regulator Improve output drivers with slew-rate control for EMI reduction Internal power-fail detection for ESD recovery Available package types: 48 pin LQFP, 28 pin QFN and 28 pin SSOP Applications:  Stand-alone USB hub / USB docking  UMPC/MID, motherboard on-board applications  Consumer electronics built-in hub application  Monitor built-in hub  Embedded systems  Compound device to support USB hub function such as keyboard hub applications © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 9 GL852G Datasheet CHAPTER 3 PIN ASSIGNMENT AMBER2/EE_DI GREEN2/EE_DO DVDD AMBER3 GREEN3 PWREN3# OVCUR3# PWREN4# OVCUR4# TEST / SCL RESET# SEL48# 36 35 34 33 32 31 30 29 28 27 26 25 3.1 Pinouts PWREN1# / SDA 43 DP3 SEL27# 44 GL852G 18 17 DM3 GREEN1/EE_SK 45 16 AVDD AMBER1/EE_CS 46 LQFP-48 15 X2 V5 47 14 X1 V33 48 13 GND 12 AVDD AVDD 19 11 42 RREF OVCUR1# 10 GND DP2 20 9 41 DM2 PWREN2# 8 DM4 GND 21 7 40 AVDD OVCUR2# 6 DP4 DP1 22 5 39 DM1 PGANG 4 GREEN4 DP0 23 3 38 DM0 DVDD 2 AMBER4 GND 24 1 37 AVDD PSELF Figure 3.1 - GL852G 48 Pin LQFP Pinout Diagram © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 10 DVDD OVCUR3# OVCUR4# TEST/SCL RESET# DP4 DM4 21 20 19 18 17 16 15 GL852G Datasheet PSELF 22 14 AVDD PGANG 23 13 DP3 OVCUR2# 24 12 DM3 OVCUR1# 25 11 X2 SDA 26 10 X1 V5 27 9 AVDD V33 28 8 RREF GL852G 1 2 3 4 5 6 7 DM0 DP0 DM1 DP1 AVDD DM2 DP2 QFN-28 Figure 3.2 - GL852G 28 Pin QFN Pinout Diagram © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 11 GL852G Datasheet AVDD 1 28 DP1 DM2 2 27 DM1 DP2 3 26 DP0 RREF 4 25 DM0 AVDD 5 24 V33 X1 6 23 V5 X2 7 22 PWREN1# DM3 8 DP3 9 GL852G AVDD 10 DM4 11 21 OVCUR1# 20 PWREN2# 19 OVCUR2# SSOP - 28 18 PGANG DP4 12 17 PSELF RESET# 13 16 DVDD TEST/SCL 14 15 GND Figure 3.3 - GL852G SSOP 28 Pin Pinout Diagram © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 12 GL852G Datasheet 3.2 Pin List Table 3.1 - GL852G LQFP 48 Pin List Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type 1 AVDD P 13 GND P 25 SEL48# I 37 PSELF I 2 GND P 14 X1 I 26 RESET# I 38 DVDD P 3 DM0 B 15 X2 O 27 TEST / SCL B 39 PGANG B 4 DP0 B 16 AVDD P 28 OVCUR4# I 40 OVCUR2# I 5 DM1 B 17 DM3 B 29 PWREN4# O 41 PWREN2# O 6 DP1 B 18 DP3 B 30 OVCUR3# I 42 OVCUR1# I 7 AVDD P 19 AVDD P 31 PWREN3# O 43 PWREN1#/ SDA B 8 GND P 20 GND P 32 GREEN3 O 44 SEL27# I 9 DM2 B 21 DM4 B 33 AMBER3 O 45 GREEN1/EE_SK O 10 DP2 B 22 DP4 B 34 DVDD P 46 AMBER1/EE_CS O 11 RREF A 23 GREEN4 O 35 O 47 V5 I/P 12 AVDD P 24 AMBER4 O 36 O 48 V33 O/P GREEN2/ EE_DO AMBER2/ EE_DI Table 3.2 - GL852G QFN 28 Pin List Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name 1 DM0 B 8 RREF A 15 DM4 B 22 PSELF I_5V 2 DP0 B 9 AVDD P 16 DP4 B 23 PGANG B 3 DM1 B 10 X1 I 17 RESET# 4 DP1 B 11 X2 I 18 TEST/SCL 5 AVDD P 12 DM3 B 19 OVCUR4# I_5V 26 SDA O 6 DM2 B 13 DP3 B 20 OVCUR3# I_5V 27 V5 I/P 7 DP2 B 14 AVDD P 21 V33 O/P I_5V 24 I/B DVDD P 25 28 Type OVCUR2# I_5V OVCUR1# I_5V Table 3.3 - GL852G SSOP 28 Pin List Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Pin Name Type 1 AVDD P 8 DM3 B 15 GND P 22 PWREN1# O 2 DM2 B 9 DP3 B 16 DVDD P 23 V5 P 3 DP2 B 10 AVDD P 17 PSELF I_5V 24 V33 P 4 RREF A 11 DM4 B 18 PGANG 25 DM0 B 5 AVDD P 12 DP4 B 19 OVCUR2# I_5V 26 DP0 B 6 X1 I 13 RESET# I 20 PWREN2#* 27 DM1 B 7 X2 O 14 TEST/SCL I/B 21 OVCUR1#* I_5V 28 DP1 B © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Type Pin# B O Page 13 GL852G Datasheet 3.3 Pin Descriptions Table 3.5 - Pin Descriptions USB Interface GL852G I/O Type Pin Name LQFP 48 Pin QFN 28 Pin SSOP 28 Pin Description DM0,DP0 3,4 1,2 25,26 B USB signals for USPORT DM1,DP1 5,6 3,4 27,28 B USB signals for DSPORT1 DM2,DP2 9,10 6,7 2,3 B USB signals for DSPORT2 DM3,DP3 17,18 12,13 8,9 B USB signals for DSPORT3 DM4,DP4 21,22 15,16 11,12 B USB signals for DSPORT4 RREF 11 8 4 A A 680Ω resister must be connected between RREF and analog ground (AGND). Note: USB signals must be carefully handled in PCB routing. Please refer to USB 2.0 Hub Design Guide for detailed information. Hub Interface GL852G Pin Name I/O Type LQFP 48 Pin QFN 28 Pin SSOP 28 Pin OVCUR1#~4 42,40, 30,28 25,24, 20,19 21,19 I (pu) PWREN1#~4 43,41, 31,29 - 22,20 O GREEN1~4 45,35, 32,23 - - AMBER1~4 46,36, 33,24 - - 37 22 PSELF PGANG 39 Description Active low. Over current indicator for DSPORT1~4 OVCUR1# is the only over current flag for GANG mode. Active low. Power enable output for DSPORT1~4 PWREN1# is the only power-enable output for GANG mode. Green LED indicator for DSPORT1~4 1,3,4: O *GREEN[1~2] are also used to access the external 2: B EEPROM (pd) For detailed information, please refer to Chapter 5. Amber LED indicator for DSPORT1~4 O *Amber [1~2] are also used to access the external (pd) EEPROM 23 17 18 I B 0: GL852G is bus-powered. 1: GL852G is self-powered. This pin is default put in input mode after power-on reset. Individual/gang mode is strapped during this period. After the strapping period, this pin will be set to output mode, and then output high for normal mode. When GL852G is suspended, this pin will output low. *For detailed explanation, please see Chapter 5 Gang input:1, output: 0@normal, 1@suspend Individual input:0, output: 1@normal, 0@suspend © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 14 GL852G Datasheet Clock and Reset Interface GL852G I/O Type Pin Name LQFP 48 Pin QFN 28 Pin SSOP 28 Pin X1 14 10 6 I Crystal / OSC clock input X2 15 11 7 O Crystal clock output. I Active low. External reset input, default pull high 10KΩ. When RESET# = low, whole chip is reset to the initial state. I SEL48#/SEL27#: 0 1: 48MHz OSC-in 1 0: 27MHz OSC-in 1 1: 12MHz X’tal/OSC-in RESET# SEL48#/ SEL27# 26 25,44 17 -- 13 -- Description System Interface GL852G Pin Name LQFP 48 Pin QFN 28 Pin SSOP 28 Pin TEST/SCL 27 18 14 SDA -- 26 -- I/O Type Description I TEST: 0: Normal operation. (pd) 1: Chip will be put in test mode. B I2C: clock output pin B I2C data pin Power / Ground GL852G Pin Name I/O Type Description LQFP 48 Pin 1,7,12, 16,19 QFN 28 Pin SSOP 28 Pin 5,9,14 1,5,10 P 3.3V analog power input for analog circuits. DVDD 34,38 21 16 P 3.3V digital power input for digital circuits GND 2,8, 13,20 - 15 V5 47 27 23 V33 48 28 24 AVDD Ground Exposed pad is connected to GND (QFN28) 5V Power input. It need be NC if using external P/I regulator 5V-to-3.3V regulator Vout (LQFP48) 5V-to-3.3V regulator Vout & 3.3 input P / O (QFN28/SSOP28) It can be NC or connect to 3.3V power if using external regulator (LQFP48 only) P Note: Analog circuits are quite sensitive to power and ground noise. PCB layout must take care the power routing and the ground plane. Please refer to USB 2.0 Hub Design Guide for detailed information. © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 15 GL852G Datasheet Notation: Type O I B B/I B/O P A SO pu pd odpu Output Input Bi-directional Bi-directional, default input Bi-directional, default output Power / Ground Analog Automatic output low when suspend Internal pull up Internal pull down Open drain with internal pull up © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 16 GL852G Datasheet CHAPTER 4 BLOCK DIAGRAM D+ 12/27/48 MHz D- USPORT RA M PLL FRTIMER Transceiver x40, x10 ROM GPIO CPU USPORT Control/Status UTMI SIE Logic REPEATER Register TT TT TT TT (Transaction Translator) (Transaction Translator) (Transaction Translator) (Transaction Translator) REPEATER / TT Routing Logic DSPORT1 Logic DSPORT2 Logic DSPORT3 Logic DSPORT4 Logic DSPORT DSPORT DSPORT DSPORT Transceiver Transceiver Transceiver Transceiver D+ D- LED/ OVCUR/ PWRENB D+ D- LED/ OVCUR/ PWRENB D+ D- LED/ OVCUR/ PWRENB D+ D- LED/ OVCUR/ PWRENB Figure 4.1 - GL852G Block Diagram (Multiple TT) © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 17 GL852G Datasheet CHAPTER 5 FUNCTION DESCRIPTION 5.1 General Description 5.1.1 USPORT Transceiver USPORT (upstream port) transceiver is the analog circuit that supports both full-speed and high-speed electrical characteristics defined in chapter 7 of USB specification Revision 2.0. USPORT transceiver will operate in full-speed electrical signaling when GL852G is plugged into a 1.1 host/hub. USPORT transceiver will operate in high-speed electrical signaling when GL852G is plugged into a 2.0 host/hub. 5.1.2 PLL (Phase Lock Loop) GL852G contains a 40x PLL. PLL generates the clock sources for the whole chip. The generated clocks are proven quite accurate that help in generating high speed signal without jitter. 5.1.3 FRTIMER This module implements hub (micro)frame timer. The (micro)frame timer is derived from the hub’s local clock and is synchronized to the host (micro)frame period by the host generated Start of (micro)frame (SOF). FRTIMER keeps tracking the host’s SOF such that GL852G is always safely synchronized to the host. The functionality of FRTIMER is described in section 11.2 of USB Specification Revision 2.0. 5.1.4 μC μC is the micro-processor unit of GL852G. It is an 8-bit RISC processor with 9K ROM and 64 bytes RAM. It operates at 6MIPS of 12 MHz clock to decode the USB command issued from host and then prepares the data to respond to the host. In addition, μC can handle GPIO (general purpose I/O) settings and reading content of EEPROM to support high flexibility for customers of different configurations of hub. These configurations include self/bus power mode setting, individual/gang mode setting, downstream port number setting, device removable/non-removable setting, and PID/VID setting. 5.1.5 UTMI (USB 2.0 Transceiver Microcell Interface) UTMI handles the low level USB protocol and signaling. It’s designed based on the Intel’s UTMI specification 1.01. The major functions of UTMI logic are to handle the data and clock recovery, NRZI encoding/decoding, Bit stuffing /de-stuffing, supporting USB 2.0 test modes, and serial/parallel conversion. 5.1.6 USPORT Logic USPORT implements the upstream port logic defined in section 11.6 of USB specification Revision 2.0. It mainly manipulates traffics in the upstream direction. The main functions include the state machines of Receiver and Transmitter, interfaces between UTMI and SIE, and traffic control to/from the REPEATER and TT. 5.1.7 SIE (Serial Interface Engine) SIE handles the USB protocol defined in chapter 8 of USB specification Revision 2.0. It co-works with μ C to play the role of the hub kernel. The main functions of SIE include the state machine of USB protocol flow, CRC check, PID error check, and timeout check. Unlike USB 1.1, bit stuffing/de-stuffing is implemented in UTMI, not in SIE. 5.1.8 Control/Status Register Control/Status register is the interface register between hardware and firmware. This register contains the information necessary to control endpoint0 and endpoint1 pipelines. Through the firmware based architecture, GL852G possesses higher flexibility to control the USB protocol easily and correctly. © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 18 GL852G Datasheet 5.1.9 REPEATER Repeater logic implements the control logic defined in section 11.4 and section 11.7 of USB specification Revision 2.0. REPEATER controls the traffic flow when upstream port and downstream port are signaling in the same speed. In addition, REPEATER will generate internal resume signal whenever a wakeup event is issued under the situation that hub is globally suspended. 5.1.10 TT (Transaction Translator) TT implements the control logic defined in section 11.14 ~ 11.22 of USB specification Revision 2.0. TT basically handles the unbalanced traffic speed between the USPORT (operating in HS) and DSPORTS (operating in FS/LS) of hub. GL852G adopts multiple TT architecture to provide the most performance effective solution. Multiple TT provides control logics for each downstream port respectively. 5.1.11 REPEATER/TT Routing Logic REPEATER and TT are the major traffic control machines in the USB 2.0 hub. Under situation that USPORT and DSPORT are signaling in the same speed, REPEATER/TT routing logic switches the traffic channel to the REPEATER. Under situation that USPORT is in the high speed signaling and DSPORT is in the full/low speed signaling, REPEATER/TT routing logic switches the traffic channel to the TT. 5.1.11.1 Connected to 1.1 Host/Hub If an USB 2.0 hub is connected to the downstream port of an USB 1.1 host/hub, it will operate in USB 1.1 mode. For an USB 1.1 hub, both upstream direction traffic and downstream direction traffic are passing through REPEATER. That is, the REPEATER/TT routing logic will route the traffic channel to the REPEATER. USB 1.1 HOST/HUB USPORToperating in FS signaling Traffic channel is routed to REPEATER REPEATER TT TT DSPORT operating in FS/LS signaling Figure 5.1 - Operating in USB 1.1 Schemes © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 19 GL852G Datasheet 5.1.11.2 Connected to USB 2.0 Host/Hub If an USB 2.0 hub is connected to an USB 2.0 host/hub, it will operate in USB 2.0 mode. The upstream port signaling is in high speed with bandwidth of 480 Mbps under this environment. The traffic channel will then be routed to the REPEATER when the device connected to the downstream port is signaling also in high speed. On the other hand, the traffic channel will then be routed to TT when the device connected to the downstream port is signaling in full/low speed. USB 2.0 HOST/HUB USPORToperating in HS signaling HS vs. HS: Traffic channel is routed to REPEATER REPEATER TT TT DSPORT operating in HS signaling HS vs. FS/LS: Traffic channel is routed to TT DSPORT operating in FS/LS signaling Figure 5.2 - Operating in USB 2.0 Schemes 5.1.12 DSPORT Logic DSPORT (downstream port) logic implements the control logic defined in section 11.5 of USB specification Revision 2.0. It mainly manipulates the state machine, the connection/disconnection detection, over current detection and power enable control, and the status LED control of the downstream port. Besides, it also output the control signals to the DSPORT transceiver. 5.1.13 DSPORT Transceiver DSPORT transceiver is the analog circuit that supports high-speed, full-speed, and low-speed electrical characteristics defined in chapter 7 of USB specification Revision 2.0. In addition, each DSPORT transceiver accurately controls its own squelch level to detect the detachment and attachment of devices. © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 20 GL852G Datasheet 5.2 Configuration and I/O Settings 5.2.1 RESET Setting GL852G’s power on reset can either be triggered by external reset or internal power good reset circuit. The external reset pin, RESETJ, is connected to upstream port Vbus (5V) to sense the USB plug / unplug or 5V voltage drop. The reset trigger voltage can be set by adjusting the value of resistor R1 and R2 (Suggested value refers to schematics) GL852G’s internal reset is designed to monitor silicon’s internal core power (3.3V) and initiate reset when unstable power event occurs. The power on sequence will start after the power good voltage has been met, and the reset will be released after approximately 2.7 μS after power good. GL852G’s reset circuit as depicted in the picture Silicon PCB Ext. VBUS power-good detection circuit input (Pin"RESET#") VBUS (External 5V) R1 R2 Global Reset# EXT INT Int. 3.3V power-good detection circuit input (USB PHY reset) Figure 5.3 - Power on Reset Diagram To fully control the reset process of GL852G, we suggest the reset time applied in the external reset circuit should longer than that of the internal reset circuit. Timing of POR is illustrated as below figure. Power good voltage, 2.5 ~ 2.8V VDD Internal reset TPG External reset Clock … … USB command T1 T2 Figure 5.4 - Power on Sequence of GL852G © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 21 GL852G Datasheet Table 5.1 - Reset Timing Symbol Parameter Min. Max. Unit TPG VDD power up to internal reset (power good) assert (12MHz) - 2.7 μs T1 VDD power up to external reset (RESETJ) assert 3 - μs T2 RESET assert to respond USB command ready 70 - ms 5.2.2 PGANG Setting To save pin count, GL852G uses the same pin to decide individual/gang mode as well as to output the suspend flag. The individual/gang mode is decided within 20us after power on reset. Then, about 50ms later, this pin is changed to output mode. GL852G outputs the suspend flag once it is globally suspended. For individual mode, a pull low resister greater than 100KΩ should be placed. For gang mode, a pull high resister which greater than 100KΩ should be placed. In figure 5.6, we also depict the suspend LED indicator schematics. It should be noticed that the polarity of LED must be followed, otherwise the suspend current will be over spec limitation (2.5mA). RESET# 50 ms GANG_CTL Input mode, strapping to decide individual or gang mode Output mode, indicating GL852G is in normal mode or suspend mode Figure 5.5 - Timing of PGANG Strapping GAND Mode DVDD(3.3V) "0": Individual Mode "1": GANG Mode DVDD(3.3V) 100K ohm Suspend LED Indicator SUSPNDO GANG_CTL 100K ohm Suspend LED Indicator Inside GL852G On PCB Individual Mode Figure 5.6 - GANG Mode Setting © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 22 GL852G Datasheet 5.2.3 SELF/BUS Power Setting GL852G can operate under bus power and conform to the power consumption limitation completely (suspend current < 2.5 mA, normal operation current < 100 mA). By setting PSELF, GL852G can be configured as a bus-power or a self-power hub. 1: Power Self PSELF 0: Power Bus Inside GL852G On PCB Figure 5.7 - SELF/BUS Power Setting 5.2.4 LED Connections GL852G controls the LED lighting according to the flow defined in section 11.5.3 of Universal Serial Bus Specification Revision2.0. Both manual mode and Automatic mode are supported in GL852G. When GL852G is globally suspended, GL852G will turn off the LED to save power. AMBER/GREEN LED DGND Inside GL852G On PCB Figure 5.8 - LED Connection © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 23 GL852G Datasheet 5.2.5 EEPROM Setting GL852G replies to host commands by the default settings in the internal ROM. GL852G also offers the ability to reply to the host according to the settings in the external EEPROM (LQFP48 supports both 93C46 and 24C02; QFN28 only supports 24C02). And to prevent the content of EEPROM from being over-written, amber LED will be disabled when EEPROM exists. Please refer to the USB 2.0 Hub AP Note_EEPROM Info for detailed information. The schematics between GL852G and 93C46 are depicted in the following figures: DVDD EE_CS CS VCC EE_SK SK NC EE_DI DI NC EE_DO DO GND 93C46 Figure 5.9 - Schematics between GL852G and 93C46 GL852G firstly verifies the check sum after power on reset. If the check sum is correct, GL852G will take the configuration of 93C46 as part of the descriptor contents. To prevent the content of 93C46 from being over-written, amber LED will be disabled when 93C46 exists. 5.2.6 Power Switch Enable Polarity (Only Available for LQFP48 Package) Both low/high-enabled power switches are supported. It is determined by jumper setting, based on the state of pin AMBER2, as the following table: Table 5.2 - Configuration by Power Switch Type AMBER2 Power Switch Enable Polarity 0 Low-active 1 High-active 5.2.7 Port Number Configuration (Only Available for LQFP48 Package) Number of downstream port can be configured as 2/3/4 ports by pin strapping in addition to EEPROM, based on the state of pin AMBER 3, AMBER 4, as the following table: Table 5.3 - Port Number Configuration AMBER 3 AMBER 4 # of DP Declaration 1 1 1 (Port1) 1 0 2 (Port1/2) 0 1 3 (Port1/2/3) 0 0 4 (Port1/2/3/4) © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 24 GL852G Datasheet 5.2.8 Non-removable Port Configuration (Only Available for LQFP48 Package) For compound application or embedded system, downstream ports that always connected inside the system can be set as non-removable based on the state of corresponding status LED, pin GREEN 1~4. If the pin is pulled high in the initial stage, the corresponding port will be set as non-removable. 5.2.9 Reference Clock Configuration (Only Available for LQFP48 Package) GL852G can support optional 27/48MHz clock source, which is selectable through GPIO configurations. For some on-board design that 27/48MHz clock source is available, such as motherboard or Monitor built-in applications, system integrator can leverage this feature to further reduce BOM cost by removing external crystal. Table 5.4 - Ref. Clock Configuration SEL48 SEL27 Clock Source 0 1 48MHz OSC-in 1 0 27MHz OSC-in 1 1 12MHz X’tal/OSC-in © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 25 GL852G Datasheet CHAPTER 6 ELECTRICAL CHARACTERISTICS 6.1 Maximum Ratings Table 6.1 - Maximum Ratings Symbol Parameter Min. Max. Unit V5 5V Power Supply -0.5 +6.0 V VDD 3.3V Power Supply -0.5 +3.6 V VIN 3.3V Input Voltage for digital I/O(EE_DO) pins -0.5 +3.6 V VINOD Open-Drain Input (Ovcur1-4,Pself,Reset) -0.5 +5.5 V VINUSB Input Voltage for USB signal (DP, DM) pins -0.5 +3.6 V +100 o TS Storage Temperature under bias FOSC Frequency -60 C 12 MHz  500ppm 6.2 Operating Ranges Table 6.2 - Operating Ranges Symbol Parameter Min. Typ. Max. Unit V5 5V Power Supply 4.5 5.0 5.5 V VDD 3.3V Power Supply 3.0 3.3 3.6 V VIND Input Voltage for digital I/O pins -0.5 3.3 3.6 V VINUSB Input Voltage for USB signal (DP, DM) pins 0.5 3.3 3.6 V 70 o 125 o TA TJ Ambient Temperature Absolute maximum junction temperature Thermal Characteristics LQFP 48 θ JA Thermal Characteristics QFN 28 Thermal Characteristics SSOP 28 0 - 0 - 78.7 33.3 61.6 C C - o - o - o C/W C/W C/W 6.3 DC Characteristics Table 6.3 - DC Characteristics except USB Signals Symbol Parameter Min. Typ. Max. Unit PD Power Dissipation - - 431.5 mW VIL LOW level input voltage - - 0.8 V VIH HIGH level input voltage 2.0 - - V VTLH LOW to HIGH threshold voltage 1.4 1.5 1.6 V VTHL HIGH to LOW threshold voltage 0.87 0.94 0.99 V VOL LOW level output voltage when IOL=8mA - - 0.4 V VOH 2.4 - - V - - 30 A RDN HIGH level output voltage when IOH=8mA Leakage current for pads with internal pull up or pull down resistor Pad internal pull down resister 29K 59K 135K Ω RUP Pad internal pull up resister 80K 108K 140K Ω IOLK © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 26 GL852G Datasheet Table 6.4 - DC Characteristics of USB Signals under FS/LS Mode Symbol Parameter Min. Typ. Max. Unit VOL DPF/DMF static output LOW(RL of 1.5K to 3.6V ) 0 - 0.3 V VOH DPF/DMF static output HIGH (RL of 15K to GND ) 2.8 - 3.6 V VDI Differential input sensitivity 0.2 - - V VCM Differential common mode range 0.8 - 2.5 V VSE Single-ended receiver threshold 0.2 - - V CIN Transceiver capacitance - - 20 pF ILO Hi-Z state data line leakage -10 - +10 A ZDRV Driver output resistance 28 - 44 Ω Table 6.5 - DC Characteristics of USB Signals under HS Mode Symbol Parameter Min. Typ. Max. Unit VOL DPH/DMH static output LOW(RL of 1.5K to 3.6V ) - - 0.1 V CIN Transceiver capacitance 4 4.5 5 pF ILO Hi-Z state data line leakage -5 0 +5 A ZDRV Driver output resistance for USB 2.0 HS 48 45 42 Ω 6.4 Power Consumption Table 6.6 - GL852G power consumption Condition Symbol Active ports ISUSP ICC Host Current Unit 473 uA Device Suspend 4 H*1 H 76 mA 3 H H 66 mA 2 H H 58 mA 1 H H 50 mA No Active H N/A 41.7 mA *:H: High-Speed Note: Test result represents silicon level operating current, without considering additional power consumption contributed by external over-current protection circuit such as power switch or polyfuse. © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 27 GL852G Datasheet 6.5 AC Characteristics GL852G LQFP 48 pin package can support both 93C46 & 24C02 type EEPROM for customized VID/PID. GL852G QFN28/SSOP28 pin package can only support 24C02 type EEPROM. AC characteristics of these two types of EEPROM summarized as below figures and tables. 6.5.1 93C46 EEPROM IF tCSH CE tCSS tSKH tSKL SK tDIS tDIH DI tPD0 tPD1 DO Table 6.7 - AC Characteristics of EEPROM Interface (93C46) Symbol Parameter Min. Typ. Max. tCSS CS Setup Time 3.0 tCSH CS Hold Time 3.0 tSKH SK High Time 1.0 tSKL SK Low Time 2.2 tDIS DI Setup Time 1.8 tDIH DI Hold Time 2.4 tPD1 Output Delay to “1” 1.8 tPD0 Output Delay to “0” 1.8 Units us © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 28 GL852G Datasheet 6.5.2 24C02 EEPROM Interface Table 6.8 - AC Characteristics of EEPROM Interface (24C02) © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 29 GL852G Datasheet 6.6 On-Chip Power Regulator GL852G requires 3.3V source power for normal operation of internal core logic and USB physical layer (PHY). The integrated low-drop power regulator converts 5V power input from USB cable (Vbus) to 3.3V voltage for silicon power source. The 3.3V power output is guaranteed by an internal voltage reference circuit to prevent unstable 5V power compromise USB data integrity. The regulator’s maximum current loading is 200mA, which provides enough tolerance for normal GL852G operation (below 100mA). On-chip Power Regulator Features: 5V to 3.3V low-drop power regulator 200mA maximum output driving capability Provide stable 3.3V output when Vin = 3.4V~5.5V Max. suspend current:190uA; typical suspend current 164uA 3.5 V33     3 2.5 2 1.5 1 0 5… 5… 5… 5… 5… 5… 4… 4… 4… 4… 4… 4… 4… 4… 4… 4… 3… 3… 3… 3… 3… 3… 3… 3… 3… 3… 0.5 Figure 6.1 - Vin(V5) vs Vout(V33)* *Note: Measured environment: Ambient temperature = 25℃ / Current Loading = 200mA © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 30 V5 GL852G Datasheet CHAPTER 7 PACKAGE DIMENSION Internal No. GL852G Versio n No. AAAAAAAAAA YWWXXXXXXXX Date Code Lot Code Figure 7.1 - GL852G 48 Pin LQFP Package © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 31 GL852G Datasheet Internal No. GL852G Version No. AAAAAAA YWWXXXX Date Code Lot Code Figure 7.2 - GL852G 28 Pin QFN Package © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 32 GL852G Datasheet GL852G AAAAAAAAAA Version No. YWWXXXXXXXX Internal No. Date Code Lot Code Figure 7.3 - GL852G 28 Pin SSOP Package © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 33 GL852G Datasheet CHAPTER 8 ORDERING INFORMATION Table 8.1 - Ordering Information Part Number Package Green/Wire Material Version Status GL852G-MNYXX LQFP 48 Green Package XX Available GL852G-OHYXX QFN 28 Green Package XX Available GL852G-HHYXX SSOP 28 Green Package XX Available Note: The marking of "OHY" will not be shown on the IC due to QFN28 package size limitation. © 2015 Genesys Logic, Inc. - All rights reserved. GLI Confidential Page 34