GL9711

Genesys Logic, Inc. GL9711 PCI ExpressTM PIPE x1 PHY Datasheet Revision 1.10 Jul. 04, 2006 GL9711 PCI ExpressTM PIPE x1 PHY Copyright: Copyright © 2006 Genesys Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic Inc.. Disclaimer: ALL MATERIALS ARE PROVIDED "AS IS" WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE. Trademarks: is a registered trademark of Genesys Logic, Inc. All trademarks are the properties of their respective owners. Office: Genesys Logic, Inc. 12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel: (886-2) 8913-1888 Fax: (886-2) 6629-6168 http://www.genesyslogic.com ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 2 GL9711 PCI ExpressTM PIPE x1 PHY Revision History Revision 0.95 Date 7/11/2005 Preliminary release 1. Modify Table3.1–Ball Out, p.11 2. Modify “PIPE Interface” and “Other Signals”, Table3.4–Pin Descriptions, p.15~p.17 3. Modify Ch4.2 Registers Descriptions, p.19 4. Modify Ch6.10 Operation Mode and Multi-Functional Pins, p.28 5. Modify Table6.1-Pin Functions, p.28~p.30 6. Modify Table8.1~8.5, p.36~p.37 1. Add “Bottom View”, Figures.3.1, p.10 2. Update Table3.4, p.15~p.18 3. Update Table3.5, p.18 4. Modify the default value of REG0 and REG1, Table4.1, p.19 5. Modify Ch4.2 Registers Descriptions for REG0 and REG1, p.20 6. Add Ch 4.3, p.22~p.25 7. Update Table 7.5 for power consumption, p.35 8. Change TXDx to RXDx, Figure 8.4, p.39 9. The minimum and maximum value of TCYCLE, Table8.2 and Table 8.5, p.40 1. Update Table 7.8 for temperature ranges (p.37) 2. Update Table 8.1~8.4 for output delay of RX bus (p.39~p.40) 1. Modify the description of OSC25MI and OSC25MO signals, Table 3.4, p.15 2. Swap the Pin Out of OSC25MI and OSC25MO in Table 3.1~Table 3.4. 3. Update Table 7.1 for deleting IDD1-X4, IDD2-X4, IDD3-X4, IDD1-X2, IDD2-X2, and IDD3-X2 six items, p.34 4. Update Table 7.8 for deleting the ISUPPLY-1.8 item and adding θJA, ΨJT and θJC three items, p.37 Divide Table 7.8 into Table 7.8(Temperature Range) and Table 7.9(Thermal Characteristics), p.37 1. Update Table 3.5 for the parameter of buffer I/O, p.18 2. Remove Table 7.2, p.34 3. Update Fig. 8.1, 8.2 and Table 8.1~8.5 for PIPE input and output timing characteristic, p.38~p.40 Description 0.96 7/27/2005 0.97 09/20/2005 Modify Package Dimension,Ch9 , p.40 0.98 11/15/2005 1.00 12/15/2005 1.01 04/13/2006 1.02 04/26/2006 1.10 07/04/2006 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 3 GL9711 PCI ExpressTM PIPE x1 PHY TABLE OF CONTENTS CHAPTER 1 CHAPTER 2 CHAPTER 3 GENERAL DESCRIPTION................................................. 8 FEATURES ........................................................................... 9 PIN ASSIGNMENT ............................................................ 10 3.1 PINOUT .................................................................................................. 10 3.2 BALL OUT ............................................................................................. 10 3.3 PIN LIST ................................................................................................ 11 3.4 PIN DESCRIPTIONS ................................................................................ 15 CHAPTER 4 REGISTERS........................................................................ 19 4.1 REGISTERS BASE ADDRESS ................................................................... 19 4.2 REGISTERS DESCRIPTIONS .................................................................... 20 4.3 SMBUS PROTOCAL ............................................................................... 22 CHAPTER 5 BLOCK DIAGRAM............................................................ 26 5.1 SIMPLIFIED DIAGRAM ........................................................................... 26 5.2 TRANSMITTER DATA PATH PER LANE .................................................. 27 5.3 RECEIVER DATA PATH PER LANE......................................................... 28 CHAPTER 6 FUNCTION DESCRIPTION ............................................. 29 6.1 CLOCK AND RESET................................................................................ 29 6.2 RECEIVER DETECTION .......................................................................... 29 6.3 BEACON TRANSMITTING AND DETECTION ............................................ 29 6.4 RECEIVER STATUS REPORT .................................................................. 29 6.5 LOOPBACK ............................................................................................ 30 6.6 POLARITY INVERSION ........................................................................... 30 6.7 SETTING NEGATIVE DISPARITY ............................................................ 30 6.8 BEHAVIOR SUMMARY............................................................................ 31 6.9 POWER SAVING SUPPORT...................................................................... 31 6.10 OPERATION MODE AND MULTI-FUNCTIONAL PINS ............................ 32 CHAPTER 7 ELECTRICAL CHARACTERISTICS.............................. 34 7.1 DC VOLTAGE SPECIFICATIONS ............................................................. 34 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 4 GL9711 PCI ExpressTM PIPE x1 PHY 7.2 TRANSMIT AND RECEIVE LATENCY TIME ............................................. 34 7.3 TRANSITION TIME OF POWER STATE .................................................... 34 7.4 POWER CONSUMPTION.......................................................................... 35 7.5 DIFFERENTIAL TRANSMITTER AND RECEIVER SERIAL OUTPUT ........... 35 7.6 RECOMMENDED OPERATING CONDITIONS ........................................... 37 CHAPTER 8 PIPE TIMING CHARACTERISTICS .............................. 38 8.1 INPUT SETUP, HOLD TIME AND OUTPUT TIMING .................................. 38 8.2 REFERENCE TIMING INFORMATION ...................................................... 40 CHAPTER 9 CHAPTER 10 PACKAGE DIMENSION................................................... 41 ORDERING INFORMATION......................................... 42 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 5 GL9711 PCI ExpressTM PIPE x1 PHY LIST OF FIGURES FIGURE 3.1 - 233 PIN LFBGA PINOUT DIAGRAM ..........................................................10 FIGURE 4.1 – SMBUS TOPOLOGY OF GL9711................................................................22 FIGURE 4.2 – DATA VALIDITY ........................................................................................23 FIGURE 4.3 – START AND STOP CONDITION ...............................................................23 FIGURE 4.4 – ACK AND NACK SIGNALING OF SMBUS .................................................24 FIGURE 4.5 – SMBUS PACKET PROTOCOL DIAGRAM ELEMENT KEY ............................24 FIGURE 4.6 – WRITE BYTE PROTOCOL ..........................................................................25 FIGURE 4.7 – READ BYTE PROTOCOL ............................................................................25 FIGURE 4.8 – THE MINIMUM WAIT TIME FROM POWER ON TO PROGRAMMING REGISTERS .....................................................................................................................25 FIGURE 5.1 - SIMPLIFIED DIAGRAM ...............................................................................26 FIGURE 5.2 - TRANSMITTER DATA PATH PER LANE .......................................................27 FIGURE 5.3 - RECEIVER DATA PATH PER LANE .............................................................28 FIGURE 8.1 – DEFINITION OF INPUT SETUP AND HOLD TIME ..........................................38 FIGURE 8.2 – DEFINITION OF OUTPUT TIMING ..............................................................39 FIGURE 9.1 - GL9711 233 PIN LFBGA PACKAGE ..........................................................41 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 6 GL9711 PCI ExpressTM PIPE x1 PHY LIST OF TABLES TABLE 3.1 - BALL OUT ...................................................................................................10 TABLE 3.2 - NUMERIC PIN LIST......................................................................................11 TABLE 3.3 - ALPHABETIC PIN LIST ................................................................................13 TABLE 3.4 - PIN DESCRIPTIONS ......................................................................................15 TABLE 3.5 - PARAMETER OF BUFFER I/O.......................................................................18 TABLE 4.1 - BASE ADDRESS FOR REGISTERS ..................................................................19 TABLE 6.1 - PIN FUNCTIONS ...........................................................................................32 TABLE 7.1 - DC VOLTAGE SPECIFICATIONS...................................................................34 TABLE 7.2 - TRANSMIT AND RECEIVE LATENCY TIME...................................................34 TABLE 7.3 – TRANSITION TIME OF POWER STATE .........................................................34 TABLE 7.4 - POWER CONSUMPTION OF EACH POWER STATE IN DIFFERENT OPERATION MODE .............................................................................................................................35 TABLE 7.5 – TRANSMITTER SERIAL OUTPUT .................................................................35 TABLE 7.6 – RECEIVER SERIAL OUTPUT ........................................................................36 TABLE 7.7 – TEMPERATURE RANGE...............................................................................36 TABLE 7.8 – THERMAL CHARACTERISTICS ....................................................................36 TABLE 8.1 – INPUT SETUP, HOLD TIME AND OUTPUT TIMING FOR 8-BIT SDR MODE ...39 TABLE 8.2 – INPUT SETUP, HOLD TIME AND OUTPUT TIMING FOR 8-BIT DDR MODE...40 TABLE 8.3 – INPUT SETUP, HOLD TIME AND OUTPUT TIMING FOR 16-BIT MODE..........40 TABLE 8.4 – INPUT SETUP, HOLD TIME AND OUTPUT TIMING FOR 10-BIT SDR MODE .40 TABLE 8.5 – INPUT SETUP, HOLD TIME AND OUTPUT TIMING FOR 10-BIT DDR MODE.40 TABLE 8.6 – REFERENCE TIMING INFORMATION ...........................................................40 TABLE 10.1 - ORDERING INFORMATION .........................................................................42 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 7 GL9711 PCI ExpressTM PIPE x1 PHY CHAPTER 1 GENERAL DESCRIPTION The GL9711 is a 1-lane PCI Express PHY Layer Controller, which is compliant with PCI Express Base Specification rev. 1.0a and Intel’s PHY Interface for the PCI Express Architecture rev. 1.0. It integrates one SerDes and the Physical Coding Sublayer (PCS) which performs 8b/10b encoding and decoding, elastic buffer and receiver detection, data serialization and deserialization. The SerDes in the GL9711 supports an effective serial interface speed (2.5 Gb/s) of data bandwidth, intended for use in ultrahigh-speed bi-directional data transmission system. The GL9711 can also be externally configured for various parallel bus width which is flexible and suitable for implementation. It also supports four operational states for power management to minimize power consumption. For production and self-test purposes, the GL9711 provides BIST and an internal loopback capability. The primary application of this chip is to provide very high-speed I/O data channels for point-to-point baseband data transmission over an on-chip termination resister of 50 Ohm +/- 10%. This device can also be used to replace parallel data transmission architectures by providing a reduction in the number of traces, connector pins, and transmit/receive pins. Parallel data loaded into the transmitter is delivered to the receiver over a serial channel. It is then reconstructed into its original parallel format. The maximum data transfer rate in each direction is 256M bytes per second. It also offers various power saving modes to significantly reduce power consumption as well as scalability for a higher data rate in the future. ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 8 GL9711 PCI ExpressTM PIPE x1 PHY CHAPTER 2 l l l l l l l l l l l l l l l l l FEATURES Complies with PCI Express Base Specification rev. 1.0a Complies with Intel’s PHY Interface for PCI Express Architecture rev. 1.0 Integrates 2.5 gigabit per second (Gpbs) Serializer/Deserializer Supports 8-bit or 10-bit parallel interface @250MHz Supports 16-bit parallel interface @125MHz Supports DDR configuration for 8-bit or 10-bit mode Beacon transmission and reception Receiver detection Transmission and detection of electrical idle Clock tolerance for 600 ppm in frequencies between bit rates at the two end of a Link On-chip 8-bit/10-bit encoding/decoding and comma alignment On-chip PLL provides clock synthesis 1.8-V power supply for core 2.5-V power supply for IO Above 2.0 kV ESD protection 0.18 µm process Available in LFBGA-233 package ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 9 GL9711 PCI ExpressTM PIPE x1 PHY CHAPTER 3 3.1 Pinout PIN ASSIGNMENT 17 16 15 14 13 12 11 10 9 A B C D E F G H J K L M N P R T U 8 7 6 5 4 3 2 1 Bottom View Figure 3.1 - 233 Pin LFBGA Pinout Diagram 3.2 Ball Out Table 3.1 - Ball Out 1 A REFCLKP B REFCLKN C OSC25MO D OSC25MI E F G H J K L NC VSS NC NC NC VDD25 VSS 2 NC NC NC VDD25 NC NC VDD25 NC VSS NC VSS NC VSS NC 3 VDDTX VSSTX NC NC NC NC NC NC NC NC NC VDD18 NC NC 4 NC NC VDD18 VSS NC NC NC NC NC VDD12 VDD18 NC NC NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 5 VDDRX VSSRX NC VSS 6 NC NC NC NC 7 VDDTX 8 9 VDDRX NC VSSTX NC VSSRX VSSTX VDDPLL NC VDD18 RTERM VSSPLL VSS M NC N P VDD25 NC NC NC NC VSS Page 10 ©2000-2006 Genesys Logic Inc. - All rights reserved. GL9711 PCI ExpressTM PIPE x1 PHY R T U NC NC VSS 1 10 A B C D E F G H J K L M N P R VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS TXN NC VDD25 NC 2 11 VDDTX NC NC VSS 3 12 RXN RXP VDD18 NC NC NC NC 4 13 VDDRX NC VDD25 PHYSTS 5 14 NC NC TXD9 TXD11 TXD13 NC NC RXD13 VDD12 TXD2 TXCMP RXSTS1 RXD3 RXD5 NC PCLK VSS 14 NC VDD18 NC 6 15 VDDTX VSS NC NC 7 16 NC NC TXD14 VDD25 TXD10 RXD8 RXD10 RXD15 RXD14 TXDK0 TXD1 TXD3 TXD7 VSS RXD0 RXD2 RXD6 16 NC NC NC 8 17 VDDRX OPMODE0 NC VDD25 9 TXP VSSTX NC NC VSSRX NC TXD8 VSSTX VSSGR TXD12 TXDK1 NC RXD9 RXD11 VSS VDD25 TXD6 TXD4 RXDK0 RXD1 RXD4 VSS NC 15 VSSRX TXD15 NC RXDK1 VDD25 RXD12 VDD18 VDD18 NC TXD0 VSS TXD5 RXSTS0 VDD25 RXSTS2 VDD18 NC PD1 SCC RXVLD TXDET/ LPBK NC TXIDLE RXIDLE RST_N 12 RXD7 VDD25 NC RXPLR 13 PD0 T TESTD U OPMODE1 TESTC 10 11 VDD25 17 3.3 Pin List Table 3.2 - Numeric Pin List Pin# A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 Pin Name REFCLKP NC VDDTX NC VDDRX NC VDDTX NC VDDRX TXN VDDTX RXN Pin# C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 Pin Name OSC25MO NC NC VDD18 NC NC VSSTX VDDPLL NC VDD18 NC VDD18 Pin# E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 Pin Name NC NC NC NC Pin# G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 VSS VSS VSS VSS VSS Pin Name NC VDD25 NC NC Pin# J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 Page 11 VSS VSS VSS VSS VSS Pin Name NC VSS NC NC ©2000-2006 Genesys Logic Inc. - All rights reserved. GL9711 PCI ExpressTM PIPE x1 PHY A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 VDDRX NC VDDTX NC VDDRX REFCLKN NC VSSTX NC VSSRX NC VSSTX NC VSSRX TXP VSSTX RXP VSSRX NC VSSTX NC VSSRX C13 C14 C15 C16 C17 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 NC TXD9 VSSGR TXD14 TXD15 OSC25MI VDD25 NC VSS VSS NC VDD18 RTERM VSSPLL NC NC NC TXD8 TXD11 TXD12 VDD25 NC E13 E14 E15 E16 E17 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 NC NC RXD8 VDD25 TXD13 TXDK1 TXD10 RXDK1 VSS NC NC NC G13 G14 G15 G16 G17 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 RXD13 RXD11 RXD15 VDD18 VSS VSS VSS VSS VSS NC RXD9 RXD10 RXD12 NC NC NC NC J13 J14 J15 J16 J17 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 TXD2 VDD25 TXDK0 NC VSS VSS VSS VSS VSS VDD12 VSS RXD14 VDD18 VDD25 NC NC VDD12 Pin# L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 Pin Name VSS VSS NC VDD18 Pin# N1 N2 N3 N4 N5 N6 Pin Name NC VSS NC NC Pin# R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R12 R13 Pin Name NC NC NC NC NC NC VSS NC OPMODE0 SCC TXIDLE VDD25 NC Pin# Pin Name U1 U2 U3 U4 U5 U6 U7 U8 U9 VSS NC VSS NC PHYSTS NC NC NC VDD25 TESTC RST_N RXPLR VSS VSS VSS VSS VSS VSS N7 N8 N9 N10 N11 N12 N13 U10 OPMODE1 U12 U13 U14 R11 TXDET/LPBK U11 TXCMP N14 RXD3 R14 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 12 GL9711 PCI ExpressTM PIPE x1 PHY L15 L16 L17 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 RXSTS1 TXD4 TXD3 VSS TXD6 TXD1 TXD0 VSS NC VDD18 NC N15 N16 N17 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 RXDK0 TXD7 TXD5 VDD25 NC NC NC NC NC NC NC VSS PD1 RXVLD NC RXD7 RXD5 RXD1 VSS RXSTS0 R15 R16 R17 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 RXD4 RXD0 VDD25 NC VDD25 NC NC VDD25 VDD18 NC NC NC TESTD PD0 RXIDLE NC PCLK VSS RXD2 RXSTS2 Blank U15 U16 U17 NC RXD6 VDD25 Table 3.3 - Alphabetic Pin List Pin Name NC NC NC NC NC NC NC NC NC NC NC OPMODE0 OPMODE1 OSC25MO OSC25MI Pin# C3 C5 C6 C9 C11 C13 D6 D10 D11 D12 K17 R9 U10 C1 D1 Pin Name NC NC NC NC NC NC NC NC RXDK1 RXDK0 NC NC NC RXIDLE NC Pin# G4 E2 F3 D3 E3 E4 F4 C2 E17 N15 T1 E1 T13 T12 T8 Pin Name NC TXCMP NC NC TXD8 TXD9 TXD10 TXD11 TXD12 TXD13 TXD14 TXD15 TXD0 TXD1 TXD2 Pin# F15 L14 R3 G1 D13 C14 E16 D14 D15 E14 C16 C17 L17 L16 K14 Pin Name NC NC NC TXP NC NC VDD12 VDD12 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 Pin# A6 A2 B14 B10 B6 B2 J14 K4 C4 C10 C12 D7 H17 J17 L4 Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin# H7 H8 H9 H10 H11 J2 J7 J8 J9 J10 J11 J15 K7 K8 K9 Page 13 ©2000-2006 Genesys Logic Inc. - All rights reserved. GL9711 PCI ExpressTM PIPE x1 PHY PCLK PD0 PD1 PHYSTS REFCLKN REFCLKP RST_N RTERM RXD8 RXD9 RXD10 RXD11 RXD12 RXD13 RXD14 RXD15 RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 NC NC NC NC NC NC NC NC T14 T11 P10 U5 B1 A1 U12 D8 F16 G15 G16 H15 G17 H14 J16 H16 R16 P15 T16 N14 R15 P14 U16 P13 N4 P2 P3 R1 M4 N1 N3 M2 NC NC RXN NC NC NC RXP NC NC NC RXPLR NC NC NC NC NC RXSTS0 RXSTS1 RXSTS2 NC NC NC NC NC NC NC RXVLD NC NC SCC TESTC TESTD P8 A16 A12 A8 A4 B16 B12 B8 B4 U15 U13 T9 R8 F14 G14 D17 P17 M14 T17 P5 R2 P4 H4 F2 G3 P12 P11 U7 U6 R10 U11 T10 TXD3 TXD4 TXD5 TXD6 TXD7 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC TXDET/LPBK M16 M15 N17 L15 N16 U4 R6 T4 P6 U2 R5 T3 R4 K2 K3 J1 J4 H1 J3 H2 H3 R11 E15 K16 P7 L3 R14 R12 U8 T7 A14 A10 VDD18 VDD18 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDDPLL VDDRX VDDRX VDDRX VDDRX VDDTX VDDTX VDDTX VDDTX VSS VSS VSS VSS VSS VSS VSS VSS M3 T6 D2 D16 F17 G2 K1 K15 P1 R13 R17 T2 T5 U9 U17 C8 A17 A13 A9 A5 A15 A11 A7 A3 D4 D5 F1 G7 G8 G9 G10 G11 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSGR VSSPLL VSSRX VSSRX VSSRX VSSRX VSSTX VSSTX VSSTX VSSTX VSSTX K10 K11 L1 L2 L7 L8 L9 L10 L11 M1 M17 N2 P9 P16 R7 T15 U1 U3 U14 C15 D9 B17 B13 B9 B5 B15 B11 B7 C7 B3 TXDK1 TXDK0 NC NC NC TXIDLE NC NC NC TXN ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 14 GL9711 PCI ExpressTM PIPE x1 PHY 3.4 Pin Descriptions Table 3.4 - Pin Descriptions PIPE Interface Pin Name RST_N I/O Standard LVCMOS2 Pin# U12 Type I Description Global reset Parallel interface clock All data movement across the parallel interface is synchronous to this clock. 1. For 8-bit mode: PCLK operates at 250 MHz and is applied to synchronize all TXD, RXD data bus and all commands. 2. For 16-bit mode: PCLK operates at 125 MHz and is applied to synchronize all TXD, RXD data bus and all commands. 3. For 10-bit mode(TBC): PCLK operates at 250 MHz and is applied to synchronize the TXD data bus and all commands. 1. For 8-bit and 16-bit modes: Encodes receiver status and error codes for the received data stream and receiver detection 000 Received data OK 001 1 SKP added 010 1 SKP removed 011 Receiver detected 100 8B/10B decode error 101 Elastic Buffer overflow 110 Elastic Buffer underflow 111 Receiver disparity error 2. For 10-bit modes: RXSTS[2]: RBC, synchronize the RXD data bus RXSTS[1]: RXPRSNT, report the result of receiver detection RXSTS[0]: RXD9, bit 9 of RXD data bus Indicates receiver detection of an electrical idle This is an asynchronous signal. Used to communicate completion of several PHY functions including power state transitions and receiver detection Indicates symbol lock and valid data on RXDx and RXDKx 1. For 8-bit and 16-bit modes: Sets the running disparity to negative 2. For 10-bit mode: TXD9, bit 9 of TXD data bus Forces Tx output to electrical idle PCLK SSTL2_I T14 O RXSTS[2:0] SSTL2_I T17, M14, P17 O RXIDLE LVCMOS2 T12 O PHYSTS RXVLD SSTL2_I LVCMOS2 U5 P11 O O TXCMP TXIDLE SSTL2_I LVCMOS2 L14 R12 I I ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 15 GL9711 PCI ExpressTM PIPE x1 PHY 1. For 8-bit and 16-bit modes: K-code indication for the received symbols In 8-bit mode, RXDK = RXDK0 In 16-bit mode, RXDK = {RXDK1, RXDK0} 2. For 10-bit mode: RXDK[0]: RXD8, bit 8 of RXD data bus RXD[7:0]: Parallel data output bus for all 8-bit, 16-bit and 10-bit modes RXD[15:0]: Parallel data output bus for 16-bit mode only 1. For 8-bit and 16-bit modes: K-code indication for the transmitted symbols In 8-bit mode, TXDK = TXDK0 In 16-bit mode, TXDK = {TXDK1, TXDK0} 2. For 10-bit mode: TXDK[0]: TXD8, bit 8 of TXD data bus TXD[7:0]: Parallel data input bus for all 8-bit, 16-bit and 10-bit modes TXD[15:0]: Parallel data input bus for 16-bit mode only Receiver detection/Loopback Sets the power states 00 P0, normal operation 01 P0s, low recovery time latency, power saving state 10 P1, longer recovery time(64us max) latency, lower power state RXDK[1:0] SSTL2_I E17, N15 O RXD[15:0] SSTL2_I H16, J16, H14, G17, H15, G16, G15, F16, P13, U16, P14, R15, N14, T16, P15, R16 O TXDK[1:0] SSTL2_I E15, K16 I TXD[15:0] TXDET/LPBK C17, C16, E14, D15, D14, E16, C14, D13, SSTL2_I N16, L15, N17, M15, M16, K14, L16, L17 LVCMOS2 R11 I I PD[1:0] LVCMOS2 P10, T11 I RXPLR LVCMOS2 U13 I 11 P2, lowest power state Inverts the polarity on the RXP/RXN Power and Ground Signals Pin Name VDD25 VDD18 Pin# D2, D16, F17, G2, K1, K15, P1, R13, R17, T2, T5, U9, U17 C4, C10, C12, D7, H17, J17, L4, Type P P P Description 2.5V Power Supplies for general I/O 1.8V Power Supplies for core and bias voltage 1.25V Reference Voltage for high speed I/O M3, T6 VDD12 J14, K4 D4, D5, F1, G7, G8, G9, G10, G11, H7, H8, H9, H10, H11, J2, J7, J8, J9, J10, J11, J15, K7, K8, K9, K10, VSS K11, L1, L2, L7, L8, L9, L10, L11, M1, M17, N2, P9, P16, R7, T15, U1, U3, U14 VDDPLL C8 VSSPLL VDDRX VSSRX VDDTX VSSTX D9 A17, A13, A9, A5 B17, B13, B9, B5 A15, A11, A7, A3 B15, B11, B7, C7, B3 P Digital ground P P P P 1.8V Power Supplies for internal PLL Ground for internal PLL 1.8V Power Supplies for receiver part 1.8V Power Supplies for transceiver part Page 16 ©2000-2006 Genesys Logic Inc. - All rights reserved. GL9711 PCI ExpressTM PIPE x1 PHY VSSGR C15 P Ground for the guard ring of the SerDes block Serial Signals Pin Name RXN RXP RTERM TXN TXP Pin# A12 B12 Type I I I O O Description Received serial input, complement Received serial input, true Connects an external 5.1KΩ resistor to ground for calibrating the on-chip termination resistors Transmitted serial output, complement Transmitted serial output, true D8 A10 B10 Other Signals Pin Name REFCLKP REFCLKN OSC25MO I/O Standard Analogue Analogue Crystal Crystal/ Oscillator Pin# A1 B1 C1 Type I I O Description Reference clock signal Reference clock signal OSC25MI D1 U11 T10 I I Connect to 25MHz crystal when using crystal as the reference clock source Connect to 25MHz crystal/oscillator when using crystal/oscillator as the reference clock source Test clock/SMBus clock TESTC/SMC LVCMOS2 TESTD/SMD LVCMOS2 SCC LVCMOS2 R10 OPMODE[1:0] LVCMOS2 U10, R9 I/O Test data/SMBus data Configures clock input source When SCC=1, the chip clock sources from a pair of differential signals, REFCLKP and I REFCLKN, with a nominal frequency of 100 MHz. When SCC=0, the chip clock sources from a crystal at 25MHz. Operational Mode of the GL9711 00 8-bit mode 01 16-bit mode I 10 10-bit mode 11 Internal use only NC - A2, A4, A6, A8, A14, A16, B2, B4, B6, B8, B14, B16, C2, C3, C5, C6, C9, C11, C13, D3, D6, D10, D11, D12, D17, E1, E2, E3, E4, F2, F3, F4, F14, F15, G1, G3, G4, G14, H1, H2, H3, H4, J1, J3, J4, K2, K3, K17, L3, - No connection ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 17 GL9711 PCI ExpressTM PIPE x1 PHY M2, M4, N1, N3, N4, P2, P3, P4, P5, P6, P7, P8, P12, R1, R2, R3, R4, R5, R6, R8, R14, T1, T3, T4, T7, T8, T9, T13, U2, U4, U6, U7, U8, U15 Note: ”NC” pins should be left open on circuit board. Table 3.5 - Parameter of Buffer I/O VIH VIL VOH VOL (Input High Voltage, (Input Low Voltage, (Output High Voltage, (Output Low Voltage, V) V) V) V) Min Norm Max Min Norm Max Min Norm Max Min Norm Max Buffer type LVCMOS2 SSTL2 1.7 1.57 - - - - 0.7 0.93 2.4 1.76 - - - - 0.4 0.74 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 18 GL9711 PCI ExpressTM PIPE x1 PHY CHAPTER 4 REGISTERS There are some registers built-in the GL9711 for test purpose. These registers can be accessed through a serial bus interface using pin TESTC and TESTD. Registers at Offset 05h ~ 0Bh are for internal test only. Please be careful to leave them as default values. 4.1 Registers Base Address Table 4.1 - Base Address for Registers Mnemonic REVID XCVROPT LPBKTEST BCNPAT2 BCNPAT3 BT SLCDT Notation: R/W R/O W/O R/W1C R/W/C Offset 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh Description Revision ID and Auto-calibration Result Register Transceiver Option Register BIST and Beacon/Test Data Pattern Register, Part 1 Beacon/Test Data Pattern Register, Part 2 Beacon/Test Data Pattern Register, Part 3 For internal test only For internal test only For internal test only For internal test only For internal test only For internal test only For internal test only Buffer Test Register Serial Loopback and Comma Detect Test Register Default 8’bxxxx1xxx 8’hE9 8’h00 8’h03 8’hFF 8’h00 8’h00 Read / Write Read Only Write Only Read / Write “1” to Clear Read / Write and hardware automatic Clear ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 19 GL9711 PCI ExpressTM PIPE x1 PHY 4.2 Registers Descriptions Offset 00h – REVID …………………………………………….………… Default value = 8’bxxxx1xxx REV3 R 7-4 REV[3:0] 3 BY1 2-0 RCAL[0:2] REV2 R REV1 R REV0 R BY1 R RCAL0 R RCAL1 R RCAL2 R Chip revision code x1 package Calibration result of on-chip termination resistors Offset 01h – XCVROPT ……………………………………………..…………. Default value = 8’hE9 SW1 R/W 7-6 SW[1:0] SW0 DEM1 R/W DEM0 R/W BW0 R/W BW1 R/W RDEF R/W FEVAL R/W R/W 5-4 DEM[1:0] 3-2 BW[0:1] 1 RDEF 0 FEVAL Swing control of transmitter output Output Swing (Differential, peak-to-peak) 00 0.6V 01 0.8V 10 1.0V 11 1.2V De-emphasis control of transmitter output Amount of De-emphasis 00 No de-emphasis 01 -1.6dB 10 -3.5dB 11 -6.0dB Bandwidth control of clock recovery circuit Relative Bandwidth 00 1 01 2 10 4 11 Reserved Disable calibration of on-chip termination resistors and leave the resistors to their default value Force calibration of on-chip termination resistors When RDEF=0, writing a one to this bit will make the resistors re-calibrated. This bit is auto-cleared and always read as zero. ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 20 GL9711 PCI ExpressTM PIPE x1 PHY Offset 02h – LPBKTEST …………………………………………..…………. Default value = 8’h00 BIST0 R/W 7-5 BIST[0:2] BIST1 BIST2 R/W --- BCN19 R/W BCN18 R/W BCN17 R/W BCN16 R/W R/W 4 RESERVED 3-0 BCN[19:16] Select of built-in test pattern Bit Pattern 00x BIST disabled 100 0000000000 0000000000 010 1111111111 1111111111 110 0101010101 0101010101 101 0011111010 1010101010 1100000101 0101010101 011 0011111010 10100*01010 1100000101 01011*10101 111 PRBS pattern It should be noted that the expected pattern while BIST[0:2]=011 is the same as BIST[0:2]=101. But when coming out of the transmitter, the two bits with “*” in BIST[0:2]=011 are different from BIST[0:2]=101. As a result, even when there is no bit error, there will be bit errors intentionally introduced to verify the BIST circuit is functional. Data pattern for beacon and TXTEST Offset 03h – BCNPAT2 ………………………………………………….……. Default value = 8’h03 BCN15 R/W 7-0 BCN[15:8] BCN14 R/W BCN13 R/W BCN12 R/W BCN11 R/W BCN10 R/W BCN9 R/W BCN8 R/W Data pattern for beacon and TXTEST Offset 04h – BCNPAT3 ………………………………………………….……. Default value = 8’hFF BCN7 R/W 7-0 BCN[7:0] BCN6 R/W BCN5 R/W BCN4 R/W BCN3 R/W BCN2 R/W BCN1 R/W BCN0 R/W Data pattern for beacon and TXTEST Offset 0Ch – BT ……………...…………………………………………...……. Default value = 8’h00 ----DDR R/W REN TXTEST R/W PLPBK R/W SKPDEL R/W SKPADD R/W R/W 7-6 RESERVED 5 DDR 4 REN 3 TXTEST 2 PLPBK Enable DDR at PIPE interface and make PCLK = 125MHz @ 8/10-bit mode Enable terminator for REFCLKP/N Enable transmitter test with data pattern BCN[19:0], which are programmed in REG02h, 03h and 04h Enable parallel loopback of PCS Page 21 ©2000-2006 Genesys Logic Inc. - All rights reserved. GL9711 PCI ExpressTM PIPE x1 PHY 1 SKPDEL 0 SKPADD Enable SKP deleting test of SKP ordered sets Enable SKP adding test of SKP ordered sets Offset 0Dh – SLCDT ………...…………………………………………...……. Default value = 8’h00 --7 6 5-3 2 1-0 SLPBK --- --- --- FENCD R/W --- --- R/W RESERVED SLPBK RESERVED FENCD RESERVED Enable serial loopback Force comma detect - 4.3 SMBus Protocal GL9711 registers are programmed by System Management Bus (SMBus). Fig. 4.1 shows the SMBus topology. The VDD power is 2.5V +/- 10% and the pull up resistor is 1KΩ. Both SMBCLK and SMBDAT lines are bi-directional, connected to 2.5V supply voltage through a pull-up resistor. The operating frequency is 10~100KHz and the SMBus address of GL9711 is 7’h2C. Figure 4.1 – SMBus Topology of GL9711 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 22 GL9711 PCI ExpressTM PIPE x1 PHY SMBus uses fixed voltage levels to define the logic “ZERO” and logic “ONE” on the bus respectively. The data on SMBDAT must be stable during the “HIGH” period of the clock. Data can change state only when SMBCLK is low. Fig. 4.2 illustrates the relationships. Figure 4.2 – Data Validity Two unique bus situations define a message START and STOP condition. 1. A HIGH to Low transition of the SMBDAT line while SMBCLK is HIGH indicates a message START condition. 2. A LOW to HIGH transition of the SMBDAT line while SMBCLK is HIGH defines a message STOP condition. Figure 4.3 – START and STOP Condition ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 23 GL9711 PCI ExpressTM PIPE x1 PHY Every byte consists of 8 bits. Each byte transferred on the bus must be followed by an acknowledge bit. Bytes are transferred with the most significant bit (MSB) first. Fig. 4.4 illustrates the positioning of acknowledge (ACK) and not acknowledge (NACK) pulses relative to other data. Figure 4.4 – ACK and NACK Signaling of SMBus Below is a key to the protocol diagrams. S Sr Rd Wr x ` A P Start Condition Repeated Start Condition Read (bit value of 1) Write (bit value of 0) Shown under a field indicates that that field is required to have the value of ‘x’ Acknowledge (this bit position may be ‘0’ for an ACK or ‘1’ for a NACK) Stop Condition Master-to-GL9711 GL9711-to-Master Figure 4.5 – SMBus Packet Protocol Diagram Element Key ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 24 GL9711 PCI ExpressTM PIPE x1 PHY The first byte of a Write Byte access is the command code. The next one byte is the data to be written. In this example the master asserts GL9711’s address followed by the write bit. GL9711 acknowledges and the master delivers the command code. GL9711 again acknowledges before the master sends the data byte. GL9711 acknowledges the data byte, and the entire transaction is finished with a STOP condition. Figure 4.6 – Write Byte Protocol Reading data is slightly more complicated than writing data. First the host must write a command to GL9711. Then it must follow that command with a repeated START condition to denote a read from GL9711’s address. GL9711 then returns one byte of data. Note that there is no STOP condition before the repeated START condition, and that a NACK signified the end of the read transfer. Figure 4.7 – Read Byte Protocol GL9711 requires a minimum time (16us) to reach the steady state after power on. So the master must start programming at least 16us later after power on. Figure 4.8 – The Minimum Wait Time from Power on to Programming Registers ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 25 GL9711 PCI ExpressTM PIPE x1 PHY CHAPTER 5 BLOCK DIAGRAM 5.1 Simplified Diagram Figure 5.1 - Simplified Diagram ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 26 GL9711 PCI ExpressTM PIPE x1 PHY 5.2 Transmitter Data Path Per Lane Data x16 or x8 PCLK Optional 16, 8-bit x8 TXCMP 8b 10b Encoding TXDK0,TXDK1 250 MHz Loopback path from receiver x10 From PLL Parallel to Serial Conversion 2.5 GHz TXIDLE Transmitter Differential Driver TXDET/LPBK TXP TXN Figure 5.2 - Transmitter Data Path per Lane ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 27 GL9711 PCI ExpressTM PIPE x1 PHY 5.3 Receiver Data Path Per Lane RXP RXN Differential Recieiver 2.5 GHz RXIDLE Clock Recovery Circuit Data Recovery Circuit (DRC) RXPLR Serial to Paralle K28.5 Detection RXVLD x10 Recovered Symbol Clock Elastic Buffer Buffer Overflow/Underflow SKP Added/Removed Decode Error Receiver Status RXSTS x10 Disparity Error 250 MHz 8b 10b Decoder RXDK x8 Loopback path to transmitter Optional 8, 16-bit PCL Data x16 or x8 Figure 5.3 - Receiver Data Path per Lane ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 28 GL9711 PCI ExpressTM PIPE x1 PHY CHAPTER 6 FUNCTION DESCRIPTION 6.1 Clock and Reset The clock source of the GL9711 comes externally from either the 100 MHz differential clock pair or the 25MHz crystal, which is selectable by pin SCC. The GL9711 uses the clock source with its PLL to generate the 2.5 GHz bit rate for transmitting and receiving. The GL9711 also drives a clock output for the synchronization of MAC interface. Since the MAC interface can be configured to 8-bit, 16-bit and 10-bit mode, the clock, PCLK, runs at 250 MHz for 8-bit mode and 125 MHz for 16-bit mode. The MAC should use the rising edge of the clock to send and receive parallel data. To initialize the GL9711, the MAC should assert the reset of the GL9711 to low. While the reset is asserted, the MAC should also make TXDET/LPBK deasserted, TXIDLE asserted, TXCMP deasserted, RXPLR deasserted and PD[1:0] = P1. When the GL9711 senses its reset asserted, it will drive its PHYSTS high immediately. After the reset deasserted, the GL9711 requires typically 16.7us for internal PLL stable and then transitions its PHYSTS to low. When MAC deasserts the reset, it should monitor the state of PHYSTS to make sure the GL9711 is ready for normal operation. 6.2 Receiver Detection The receiver detection can only be performed while the GL9711 is in P1 state. To instruct the GL9711 to enter a receiver detection sequence, the MAC asserts TXDET/LPBK and hold it asserted until the GL9711 asserts PHYSTS for response. While finishing the receiver detection, the GL9711 will assert PHYSTS and present a appropriate value to RXSTS[2:0] to signal a detection completion. When the MAC detects PHYSTS asserted, it knows the detection result from RXSTS[2:0] and can deassert TXDET/LPBK. 6.3 Beacon Transmitting and Detection Beacon transmitting is required for the GL9711 in P2 state to wake up the receiver in the other side of the link. When the GL9711 is in P2 state, the MAC can deassert TXIDLE to instruct the GL9711 to repeatedly transmit a beacon. For the beacon receiving side, if the GL9711 receives a beacon, it will transition RXIDLE to low to indicate an exit from electrical idle. When the GL9711 is in P2 state and MAC senses the RXIDLE transitioned from high to low, it knows a beacon has been detected. 6.4 Receiver Status Report l Add and Remove a SKP The GL9711 implements an elastic buffer to compensate the clock rate difference between the recovery clock and its transmit clock. While receiving a SKP ordered-set, compliant to PCI Express Base specification REV. 1.0a, the GL9711 can insert or remove one SKP symbol in the SKP ordered-set to avoid the buffer overrun or underrun. Whenever adding or removing a SKP symbol, the GL9711 will signal PHYSTS and corresponding RXSTS[2:0] to MAC. SKP Ordered-Set Received Add a SKP Remove a SKP l Receiver Detected Detected Result Receiver not present Receiver present RXSTS code 000b 011b RXSTS Code 001b 010b ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 29 GL9711 PCI ExpressTM PIPE x1 PHY l 8B/10B Decode Error When the GL9711 decodes the received 10-bit symbol and detects an error code which does not correspond to any valid data, it will replace the code with an EDB symbol, assert PHYSTS and encode RXSTS[2:0] with the values of decode error status, 3’b100. Elastic Buffer Overrun and Underrun When the overrun or underrun of the elastic buffer occurs, the GL9711 will assert PHYSTS and encode RXSTS[2:0] with the values of decode error status. Elastic Buffer Overrun Underrun RXSTS Code 101b 110b l In the case of elastic buffer overrun, the GL9711 drops the symbol. For the elastic buffer underrun, the GL9711 inserts the EDB symbol. The PHYSTS and RXSTS[2:0] are presented on the MAC interface during the clock cycle where GL9711 drops or inserts the symbol. l Disparity Errors To report a disparity error detected, the GL9711 asserts PHYSTS and encodes RXSTS[2:0] with the values of decode error status, 3’b111. 6.5 Loopback The GL9711 supports a Loopback mode to re-transmit its received data. When the MAC sets the GL9711 in P0 state and asserts TXDET/LPBK, the GL9711 enters a Loopback. In Loopback, the GL9711 transmits data from it received data instead of MAC interface. Meanwhile, it presents the received data on the MAC interface as normal operation. When set into Loopback mode and acting as a Loopback slave according to the PCI Express Base Specification Rev. 1.0a, the GL9711 received data from the Loopback master. If the master intends to end the Loopback, it sends an electrical idle ordered-set to the GL9711. When the MAC detects the electrical idle ordered-set, it de-asserts TXDET/LPBK and asserts TXIDLE to instruct the GL9711 to stop Loopback. The MAC should take care the GL9711 has retransmit at least three bytes of the electrical idle before it makes the GL9711’s transmitter into electrical idle. 6.6 Polarity Inversion The GL9711 supports lane polarity inversion. While pin RXPLR asserted, the GL9711 inverts its received data on the MAC interface. 6.7 Setting Negative Disparity To set the running disparity to negative, the MAC asserts TXCMP for one PCLK cycle that matches with the data that is to be transmitted where running disparity is negative. ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 30 GL9711 PCI ExpressTM PIPE x1 PHY 6.8 Behavior Summary PD[1:0] TXDET/LPBK 0 P0 0 1 1 P0S X X X P1 0 1 P2 X X TXIDLEx 0 1 0 1 0 1 0 1 1 0 1 Behavior GL9711 is transmitting data from MAC interface normally. GL9711 is not transmitting and is in electrical idle. GL9711 enters Loopback mode. Illegal Illegal GL9711 is not transmitting and is in electrical idle. Illegal GL9711 is idle. GL9711 performs a receiver detection. GL9711 transmits a beacon. GL9711 is idle. 6.9 Power Saving Support The GL9711 supports four power states including P0, P0s, P1 and P2 and can be controlled to perform Active State Power Management on a PCI Express link. P0 is the normal operational state where data and control packets can be transmitted and received. When directed from P0 to a lower power state, the GL9711 can immediately take appropriate power saving actions. The power saving scheme of the GL9711 for various power down states is listed in the table below. PD[1:0] P0 P0s P1 Transmitter On High-impedance Electrical Idle High-impedance Electrical Idle High-impedance Electrical Idle (Capable of transmitting Receiver On On Off but exit from Electrical Idle is detectable Off but exit from Electrical Idle is detectable PLL On On On PCLK Output On On On P2 Off Off a Beacon) ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 31 GL9711 PCI ExpressTM PIPE x1 PHY 6.10 Operation Mode and Multi-Functional Pins There are four modes for GL9711 operation which is selected by pin OPMODE[1:0]. Mode 1 2 3 4 [1] 0 0 1 1 [0] 0 1 0 1 8 bit mode 16 bit mode 10 bit mode Internal use only Description Mode 1: The GL9711 is configured into 8-bit parallel bus. The parallel bus is synchronous with PCLK at 250 MHz. Mode 2: The GL9711 acts as a 1-lane PHY with a 16-bit parallel interface at 125 MHz. Mode 3: The GL9711 is configured as a SerDes with 10-bit parallel bus. Mode 4: For internal use only Table 6.1 - Pin Functions Pin Number T14 C17 C16 E14 D15 D14 E16 C14 D13 N16 L15 N17 M15 M16 K14 L16 L17 E15 K16 R12 L14 U13 H16 J16 H14 G17 H15 Mode 1 PCLK(O) Mode 2 PCLK(O) TXD15(I) TXD14(I) TXD13(I) TXD12(I) TXD11(I) TXD10(I) TXD9(I) TXD8(I) TXD7(I) TXD6(I) TXD5(I) TXD4(I) TXD3(I) TXD2(I) TXD1(I) TXD0(I) TXDK1(I) TXDK0(I) TXIDLE(I) TXCMP(I) RXPLR(I) RXD15(O) RXD14(O) RXD13(O) RXD12(O) RXD11(O) Mode 3 TBC(O) TXD7(I) TXD6(I) TXD5(I) TXD4(I) TXD3(I) TXD2(I) TXD1(I) TXD0(I) TXDK(I) TXIDLE(I) TXCMP(I) RXPLR(I) TXD7(I) TXD6(I) TXD5(I) TXD4(I) TXD3(I) TXD2(I) TXD1(I) TXD0(I) TXD8(I) TXIDLE(I) TXD9(I) RXPLR(I) ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 32 GL9711 PCI ExpressTM PIPE x1 PHY G16 G15 F16 P13 U16 P14 R15 N14 T16 P15 R16 E17 N15 P11 T17 M14 P17 U5 T12 RXD10(O) RXD9(O) RXD8(O) RXD7(O) RXD6(O) RXD5(O) RXD4(O) RXD3(O) RXD2(O) RXD1(O) RXD0(O) RXDK1(O) RXDK0(O) RXVLD(O) RXSTS2(O) RXSTS1(O) RXSTS0(O) PHYSTS(O) RXIDLE(O) RXD7(O) RXD6(O) RXD5(O) RXD4(O) RXD3(O) RXD2(O) RXD1(O) RXD0(O) RXDK(O) RXVLD(O) RXSTS2(O) RXSTS1(O) RXSTS0(O) PHYSTS(O) RXIDLE(O) RXD7(O) RXD6(O) RXD5(O) RXD4(O) RXD3(O) RXD2(O) RXD1(O) RXD0(O) RXD8(O) RXVLD(O) RBC(O) RXPRSNT(O) RXD9(O) PHYSTS(O) RXIDLE(O) ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 33 GL9711 PCI ExpressTM PIPE x1 PHY CHAPTER 7 ELECTRICAL CHARACTERISTICS 7.1 DC Voltage Specifications Table 7.1 - DC Voltage Specifications Symbol VDD25 VDD18 VDD12 VDDTX VDDRX Parameter PHY Interface Voltage Core Voltage Reference Voltage for PHY Inerface Voltage for Transmitters Voltage for Receivers Min 2.375 1.71 1.1875 1.71 1.71 1.71 Typ 2.5 1.8 1.25 1.8 1.8 1.8 Max 2.625 1.89 1.3125 1.89 1.89 1.89 Unit V V V V V V VDDPLL Voltage for PLL 7.2 Transmit and Receive Latency Time Table 7.2 - Transmit and Receive Latency Time Symbol TTX-LAT Parameter Transmit Latency, time for data moving from MAC interface (PCLK rising edge) to TX serial lines (the first bit of 10-bit symbol) Receive Latency, time for data moving from RX serial lines (the first bit of 10-bit symbol) to MAC interface (PCLK rising edge) Min 25 Typ Max 30 Unit ns TRX-LAT 48 - 54 ns 7.3 Transition Time of Power State Table 7.3 – Transition Time of Power State Symbol TP0S-P0 Parameter Time for PHY to return to P0, after having been in P0s. Time is measured when PD[1:0] are set to P0 until the PHY asserts PHYSTS Time for PHY to return to P0, after having been in P1. Time is measured when PD[1:0] are set to P0 until the PHY asserts PHYSTS Time for PHY to return to P1, after having been in P2. Time is measured when PD[1:0] are set to P1 until the PHY asserts PHYSTS Time for PHY to return to P0s, after having been in P0. Time is measured when PD[1:0] are set to P0s until the PHY asserts PHYSTS Time for PHY to return to P1, after having been in P0. Time is measured when PD[1:0] are set to P1 until the PHY asserts PHYSTS Time for PHY to return to P2, after having been in P0. Time is measured when PD[1:0] are set to P2 until the PHY asserts PHYSTS Min 52 Typ Max 74 Unit ns TP1-P0 52 - 74 ns µs ns TP2-P1 TP0-P0S 16 - 17 52 - 74 TP0-P1 52 - 74 ns µs TP0-P2 16 - 17 ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 34 GL9711 PCI ExpressTM PIPE x1 PHY 7.4 Power Consumption l Power Consumption Table 7.4 - Power Consumption of Each Power State in Different Operation Mode Current at 2.5V (mA) Current at Analogue 1.8V (mA) 59 90 Current at Digital 1.8V (mA) 57 All on PLL on 12 71 49 TX idle RX on PLL on 12 64 38 TX idle RX idle PLL off 6 36 6 TX idle RX idle P2 16-bit @3.13MHz PCLK 90.6 P1 16-bit @125MHz PCLK 213.6 P0s P0 16-bit @125MHz PCLK 16-bit @125MHz PCLK 246 Operation Power Condition State Power Operation Mode Consumption (mW) 412.1 7.5 Differential Transmitter and Receiver Serial Output l Transmitter Serial Output Table 7.5 – Transmitter Serial Output Symbol UI VTX-DIFFp-p VTX-DE-RATIO TTX-EYE TTX-EYE-MEDIAN-to-MAX-JITTER TTX-RISE, TTX-FALL VTX-CM-ACp VTX-CM-DC-ACTIVE-IDLE-DELTA VTX-CM-DC-LINE-DELTA VTX-IDLE-DIFFp Unit interval Differential peak to peak output voltage De-emphasized differential output voltage (Ratio) Minimum TX eye width Maximum time between the jitter median and maximum deviation from the median D+/D- TX output rise/fall time RMS AC peak common mode output voltage Absolute delta of DC common mode voltage during L0 and electrical idle Absolute delta of DC common mode voltage between D+ and DElectrical idle differential peak output Parameter Min 399.88 0.8 -3.0 0.7 0.125 0 0 0 Typ 400 -3.5 Max 400.12 1.2 -4.0 0.15 20 100 25 20 Unit ps UI dB UI UI UI mA mA mA mA Page 35 ©2000-2006 Genesys Logic Inc. - All rights reserved. GL9711 PCI ExpressTM PIPE x1 PHY voltage VTX-RCV-DETECT VTX-DC-CM ITX-SHORT TTX-IDLE-MIN TTX-IDLE-SET-TO-IDLE The amount of voltage change allowed during receiver detection The TX DC common mode voltage TX short circuit current limit Minimum time spent in electrical idle Maximum time to transition to a valid electrical idle after sending an electrical idle ordered set Maximum time to transition to valid TX specifications after leaving an electrical idle condition Differential return loss Common mode return loss DC differential TX impedance AC coupling capacitor Crosslink random timeout 0 50 600 3.6 90 20 mA V mA UI UI TTX-IDLE-TO-DIFF-DATA RLTX-DIFF RLTX-CM ZTX-DIFF-DC CTX Tcrosslink 12 6 80 75 0 100 - 20 120 200 1 UI dB dB Ω nF ms l Receiver Serial Output Table 7.6 – Receiver Serial Output Symbol UI VRX-DIFFp-p TRX-EYE TRX-EYE-MEDIAN-to-MAX-JITTER VRX-CM-ACp RLRX-DIFF RLRX-CM ZRX-DIFF-DC ZRX-DC ZRX-HIGH-IMP-DC VRX-IDLE-DET-DIFFp-p TRX-IDLE-DET-DIFF-ENTERTIME Unit interval Differential input peak to peak voltage Minimum receiver eye width Maximum time between the jitter median and maximum deviation from the median AC peak common mode input voltage Differential return loss Common mode return loss DC differential input impedance DC input impedance Powered down DC input impedance Electrical idle detect threshold Unexpected electrical idle enter detect threshold integration time Parameter Min 399.88 0.175 0.4 15 6 80 40 200k 65 Typ 400 100 50 Max 400.12 1.2 0.3 150 120 60 175 10 Unit ps V UI UI mV dB dB Ω Ω Ω mV ms ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 36 GL9711 PCI ExpressTM PIPE x1 PHY 7.6 Recommended Operating Conditions Table 7.7 – Temperature Range Symbol Parameter Min 0 0 -40 Typ Max 125 75 150 Unit ℃ ℃ ℃ TJUNCTOIN Junction operating temperature range TA TSTG Operating ambient temperature range Storage temperature range Table 7.8 – Thermal Characteristics Symbol Parameter Min Typ 33.2 28.7 27.5 0.39 Max Unit ℃/W ℃/W ℃/W ℃/W θJA (0 m/s) Thermal resistance from junction to ambient PS: “(x m/s)” means the air flow velocity θJA (1 m/s) (JEDEC JESD51-6 moving air, maximum reflow θJA (2 m/s) temperature for SMT is 255℃~260℃) ΨJT Thermal characterization parameter from junction-to-top center (JEDEC JESD51-2 still air, maximum reflow temperature for SMT is 255℃~260℃) Thermal resistance from junction to case (JEDEC JESD51-2 still air, maximum reflow temperature for SMT is 255℃~260℃) θJC - 12.3 - ℃/W ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 37 GL9711 PCI ExpressTM PIPE x1 PHY CHAPTER 8 PIPE TIMING CHARACTERISTICS 8.1 Input Setup, Hold Time and Output Timing Figure 8.1 – Definition of Input Setup and Hold Time ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 38 GL9711 PCI ExpressTM PIPE x1 PHY Figure 8.2 – Definition of Output Timing Table 8.1 – Input Setup, Hold Time and Output Timing for 8-bit SDR Mode Symbol TCYCLE Duty-H TIS TIH TCO TOH PCLK cycle time Duty cycle for PCLK high Input setup time Input hold time Clock to output delay Output hold time Parameter Min 3.99 35 1 1 Typ 4 2.7 2.1 Max 4.01 50 1 3.2 Unit ns % ns ns ns ns Table 8.2 – Input Setup, Hold Time and Output Timing for 8-bit DDR Mode Symbol TCYCLE TIS TIH TCO TOH PCLK cycle time Input setup time Input hold time Clock to output delay Output hold time Parameter Min 7.98 0.5 0.8 Typ 8 1.5 1 Max 8.02 1.4 1.6 Unit ns ns ns ns ns ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 39 GL9711 PCI ExpressTM PIPE x1 PHY Table 8.3 – Input Setup, Hold Time and Output Timing for 16-bit Mode Symbol TCYCLE Duty-H TIS TIH TCO TOH PCLK cycle time Duty cycle for PCLK high Input setup time Input hold time Clock to output delay Output hold time Parameter Min 7.98 48 0.5 4.3 Typ 8 5.3 4.7 Max 8.02 50 1.4 5.6 Unit ns % ns ns ns ns Table 8.4 – Input Setup, Hold Time and Output Timing for 10-bit SDR Mode Symbol TCYCLE Duty-H TIS TIH TCO TOH PCLK cycle time Duty cycle for PCLK high Input setup time Input hold time Clock to output delay Output hold time Parameter Min 3.99 35 1 3.4 Typ 4 4 3.7 Max 4.01 50 1 4.2 Unit ns % ns ns ns ns Table 8.5 – Input Setup, Hold Time and Output Timing for 10-bit DDR Mode Symbol TCYCLE TIS TIH TCO TOH PCLK cycle time Input setup time Input hold time Clock to output delay Output hold time Parameter Min 7.98 0.5 3.5 Typ 8 4.1 3.7 Max 8.02 1.4 4.3 Unit ns ns ns ns ns 8.2 Reference Timing Information Table 8.6 – Reference Timing Information Symbol TRECDET TPHYSTS-RESET TRESET Parameter Time for receiver detection Timing from de-asserting RST_N to the falling edge of PHYSTS Reset Assertion Time to GL9711 Min 10 Typ 10 16.7 Max Unit us us us ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 40 GL9711 PCI ExpressTM PIPE x1 PHY CHAPTER 9 PACKAGE DIMENSION Figure 9.1 - GL9711 233 Pin LFBGA Package ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 41 GL9711 PCI ExpressTM PIPE x1 PHY CHAPTER 10 ORDERING INFORMATION Table 10.1 - Ordering Information Part Number GL9711-TgGXX Package Green Version XX Status Engineering Sample 233-pin LFBGA Green Package ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 42