ACS8509 SETS
Synchronous Equipment Timing Source for
SONET or SDH Network Elements
ADVANCED COMMUNICATIONS
Description
FINAL
Features
The ACS8509 is a highly integrated, single-chip solution
for the Synchronous Equipment Timing Source (SETS)
function in a SONET or SDH Network Element. The device
generates SONET or SDH Equipment Clocks (SEC) and
Frame Synchronization clocks. The ACS8509 is fully
compliant with the required international specifications
and standards.
The device supports Free-run, Locked and Holdover
modes. It also supports all three types of reference clock
source: recovered line clock, PDH network, and node
synchronization. The ACS8509 generates independent
SEC and BITS/SSU clocks, an 8 kHz Frame
Synchronization clock and a 2 kHz Multi-Frame
Synchronization clock.
Two ACS8509 devices can be used together in a Master/
Slave configuration mode allowing system protection
against a single ACS8509 failure.
A microprocessor port is incorporated, providing access to
the configuration and status registers for device setup
and monitoring.
The ACS8509 includes a choice of edge alignment for
8 kHz input, as well as a low jitter n x E1/DS1 output
mode. The User can choose between OCXO or TCXO to
define the Stratum and/or Holdover performance
required.
Block Diagram
DATASHEET
Suitable for Stratum 3E*, 3, 4E, 4 and SONET
Minimum Clock (SMC) or SONET/SDH Equipment
Clock (SEC) applications
Meets AT&T, ITU-T, ETSI and Telcordia specifications
Accepts four individual input reference clocks
Generates six output clocks
Supports Free-run, Locked and Holdover modes of
operation
Robust input clock source quality monitoring on all
inputs
Automatic “hit-less” source switchover on loss of input
Phase build-out for output clock phase continuity
during input switchover and mode transitions
Microprocessor interface - Intel, Motorola, Serial,
Multiplexed, EPROM
Programmable wander and jitter tracking attenuation
0.1 Hz to 20 Hz
Support for Master/Slave device configuration
alignment and hot/standby redundancy
IEEE 1149.1 JTAG Boundary Scan
Single +3.3 V operation, +5 V I/O compatible
Operating temperature (ambient) -40°C to +85°C
Available in 100 pin LQFP package.
Lead (Pb)-free version available (ACS8509T), RoHS
and WEEE compliant.
Note...* Meets holdover requirements, lowest bandwidth 0.1 Hz.
Figure 1 Block Diagram of the ACS8509 SETS
Programmable Outputs:
01 (PECL (default)/LVDS) =
T4 DPLL/Freq. Synthesis
TOUT4
Selector
4 x TTL
Programmable;
2 kHz
4 kHz
N x 8 kHz
1.544/2.048 MHz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
Divider
PFD
Digital
Loop
Filter
Programmable: 19.44 MHz (default),
51.84 MHz (OC-1), 77.76 MHz and
155.52 MHz (OC-3)
DTO
02 (TTL/CMOS) = 6.48 MHz (default)
19.44 MHz and 25.92 MHz,
and E1/DS1 multiples:
1 x, 2 x, 4 x, 8 x (1.544/2.048 MHz)
Input
Port
Monitors
and
Selection
Control
6x
Output
Ports
03 (TTL/CMOS) = 19.44 MHz (fixed)
04 (TTL/CMOS) =
1.544 MHz/2.048 MHz (E1/DS1)
T0 DPLL/Freq. Synthesis
4 x SEC
TOUT0
Selecor
Divider
PFD
Digital
Loop
Filter
T0 APLL
(output)
DTO
Frequency
Dividers
FrSync (TTL/CMOS) =
8 kHz Frame Sync,
Fixed 50:50 MSR
MFrSync (TTL/CMOS) =
2 kHz Multiframe Sync,
Fixed 50:50 MSR
TCK
TDI
TMS
TRST
TDO
IEEE
1149.1
JTAG
Chip
Clock
Generator
Priority Register Set
Table
Microprocessor
Port
OCXO or
TCXO
F85509 001BLOCKDIA 01
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Table of Contents
ADVANCED COMMUNICATIONS
Table of Contents
FINAL
Section
ACS8509 SETS
DATASHEET
Page
Description ................................................................................................................................................................................................. 1
Block Diagram............................................................................................................................................................................................ 1
Features ..................................................................................................................................................................................................... 1
Table of Contents ...................................................................................................................................................................................... 2
Pin Diagram ............................................................................................................................................................................................... 4
Pin Description........................................................................................................................................................................................... 5
Functional Description .............................................................................................................................................................................. 8
Local Oscillator Clock.........................................................................................................................................................................8
Crystal Frequency Calibration.................................................................................................................................................. 8
Input Interfaces..................................................................................................................................................................................9
Over-Voltage Protection .....................................................................................................................................................................9
Input Reference Clock Ports .............................................................................................................................................................9
DivN Examples....................................................................................................................................................................... 10
Input Wander and Jitter Tolerance ................................................................................................................................................ 10
Frame Sync and Multi-Frame Sync Clocks (Part of TOUT0) ................................................................................................. 12
Output Clock Ports .......................................................................................................................................................................... 12
Low-speed Output Clock (TOUT4) .......................................................................................................................................... 12
High-speed Output Clock (Part of TOUT0) ............................................................................................................................. 12
Low Jitter Multiple E1/DS1 Outputs .................................................................................................................................... 13
Output Wander and Jitter ............................................................................................................................................................... 13
Phase Variation ............................................................................................................................................................................... 14
Phase Build-Out .............................................................................................................................................................................. 17
Microprocessor Interface ............................................................................................................................................................... 17
Motorola Mode ...................................................................................................................................................................... 17
Intel Mode.............................................................................................................................................................................. 17
Multiplexed Mode.................................................................................................................................................................. 17
Serial Mode............................................................................................................................................................................ 17
EPROM Mode......................................................................................................................................................................... 17
Register Set ..................................................................................................................................................................................... 18
Configuration Registers ........................................................................................................................................................ 18
Status Registers .................................................................................................................................................................... 18
Register Access............................................................................................................................................................................... 18
Interrupt Enable and Clear ............................................................................................................................................................. 18
Register Map ................................................................................................................................................................................... 18
Register Map Description............................................................................................................................................................... 23
Selection of Input Reference Clock Source................................................................................................................................... 36
Forced Control Selection....................................................................................................................................................... 36
Automatic Control Selection ................................................................................................................................................. 36
Ultra Fast Switching .............................................................................................................................................................. 37
Clock Quality Monitoring................................................................................................................................................................. 37
Activity Monitoring........................................................................................................................................................................... 38
Frequency Monitoring..................................................................................................................................................................... 39
Modes of Operation ........................................................................................................................................................................ 39
Free-run mode ....................................................................................................................................................................... 39
Pre-Locked mode .................................................................................................................................................................. 39
Locked mode ......................................................................................................................................................................... 39
Lost_Phase mode.................................................................................................................................................................. 40
Holdover mode ...................................................................................................................................................................... 40
Pre-Locked(2) mode.............................................................................................................................................................. 41
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ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Section
Page
Protection Facility............................................................................................................................................................................ 41
Alignment of Priority Tables in Master and Slave ACS8509 .............................................................................................. 42
Alignment of the Selection of Reference Sources for TOUT4 Generation in the Master and Slave ACS8509 ................ 42
Alignment of the Phases of the 8 kHz and 2 kHz Clocks in both Master and Slave ACS8509 ....................................... 42
JTAG ................................................................................................................................................................................................. 43
PORB................................................................................................................................................................................................ 43
Electrical Specification ........................................................................................................................................................................... 45
Operating Conditions ...................................................................................................................................................................... 45
DC Characteristics .......................................................................................................................................................................... 45
Notes for Tables 24 to 30..................................................................................................................................................... 51
Input/Output Timing ....................................................................................................................................................................... 52
Motorola Mode ...................................................................................................................................................................... 53
Intel Mode.............................................................................................................................................................................. 55
Multiplexed Mode.................................................................................................................................................................. 57
Serial Mode............................................................................................................................................................................ 59
EPROM Mode......................................................................................................................................................................... 61
Package Information .............................................................................................................................................................................. 62
Thermal Conditions......................................................................................................................................................................... 63
Application Information .......................................................................................................................................................................... 64
References .............................................................................................................................................................................................. 65
Abbreviations .......................................................................................................................................................................................... 65
Trademark Acknowledgements ............................................................................................................................................................. 66
Revision Status/History ......................................................................................................................................................................... 67
Ordering Information .............................................................................................................................................................................. 68
Disclaimers...................................................................................................................................................................................... 68
Contacts........................................................................................................................................................................................... 68
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ACS8509 SETS
ADVANCED COMMUNICATIONS
Pin Diagram
FINAL
DATASHEET
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
SONSDHB
MSTSLVB
IC
IC
IC
O4
IC
IC
DGND
VDD
O3
IC
O2
DGND
VDD
VDD
DGND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Figure 2 ACS8509 Pin Diagram Synchronous Equipment Timing Source for SONET or SDH Network Elements
AGND
TRST
IC
NC
AGND
VA1+
TMS
INTREQ
TCK
REFCLK
DGND
VD+
VD+
DGND
DGND
VD+
NC
IC
VA2+
AGND
TDO
IC
TDI
DGND
DGND
ACS8509
SONET/SDH SETS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RDY
PORB
ALE
RDB
WRB
CSB
A0
A1
A2
A3
A4
A5
A6
DGND
VDD
UPSEL0
UPSEL1
UPSEL2
IC
SEC4
IC
SEC3
IC
IC
SEC2
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
IC
IC
DGND
FrSync
MFrSync
GND_DIFF
VDD_DIFF
IC
IC
O1POS
O1NEG
GND_DIFF
VDD_DIFF
IC
IC
IC
IC
VDD5
SYNC2K
IC
IC
SEC1
DGND
VDD
1
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
16
17
18
19
20
21
22
23
24
25
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ACS8509 SETS
ADVANCED COMMUNICATIONS
Pin Description
FINAL
DATASHEET
Table 1 Power Pins
Pin Number
Symbol
I/O
Type
Description
12, 13, 16
VD+
P
-
Supply Voltage: Digital supply to gates in analog section, +3.3 Volts ±10%.
33, 39
VDD_DIFF
P
-
Supply Voltage: Digital supply for differential ports, +3.3 Volts ±10%.
44
VDD5
P
-
Digital Supply for +5 Volts Tolerance to Input Pins. Connect to +5 Volts
(±10%) for clamping to +5 Volts. Connect to VDD for clamping to +3.3
Volts. Leave floating for no clamping, input pins tolerant up to +5.5 Volts.
50, 61, 85,
86 91
VDD
P
-
Supply Voltage: Digital supply to logic, +3.3 Volts ±10%.
6
VA1+
P
-
Supply Voltage: Analog supply to clock multiplying PLL, +3.3 Volts ±10%.
19
VA2+
P
-
Supply Voltage: Analog supply to output PLLs, +3.3 Volts ±10%.
11, 14, 15,
24, 25, 29,
49, 62, 84,
87,92
DGND
P
-
Supply Ground: Digital ground for logic
32,
38
GND_DIFF
P
-
Supply Ground: Digital ground for differential ports.
1, 5,
20
AGND
P
-
Supply Ground: Analog grounds.
Note...I = Input, O = Output, P = Power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor.
Table 2 Not Connected or Internally Connected Pins
Pin Number
4, 17, 26
Symbol
NC
3, 18, 22, 27, IC
28, 34, 35,
40, 41, 42,
43, 46, 47,
52, 53, 55,
57, 89, 93,
94, 96, 97, 98
I/O
Type
Description
NC
-
Not connected: Leave to Float
IC
-
Internally Connected: Leave to Float.
I/O
Type
Table 3 Other Pins
Pin Number
Symbol
Description
2
TRST
I
TTLD
JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary Scan mode.
TRST = 0 for Boundary Scan stand-by mode, still allowing correct device
operation. If not used connect to GND or leave floating.
7
TMS
I
TTLU
JTAG Test Mode Select: Boundary Scan enable. Sampled on rising edge of
TCK. If not used connect to VDD or leave floating.
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ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Table 3 Other Pins (cont...)
Pin Number
Symbol
I/O
Type
Description
8
INTREQ
O
TTL/CMOS
9
TCK
I
TTLD
JTAG Clock: Boundary Scan clock input. If not used connect to GND or leave
floating. This pin may require a capacitor placed between the pin and the
nearest GND, to reduce noise pickup. A value of 10 pF should be adequate,
but the value is dependent on PCB layout.
10
REFCLK
I
TTL
Reference Clock: 12.800 MHz (refer to “Local Oscillator Clock” on page 8).
21
TDO
O
TTL/CMOS
JTAG Output: Serial test data output. Updated on falling edge of TCK. If not
used leave floating.
23
TDI
I
TTLU
30
FrSync
O
TTL/CMOS
Output Reference: 8 kHz Frame Sync output (square wave).
31
MFrSync
O
TTL/CMOS
Output Reference: 2 kHz Multi-Frame Sync output (square wave).
36,
37
O1POS, O1NEG
O
PECL/LVDS
Output Reference O1: Programmable, default 19.44 MHz. Also 51.84 MHz,
77.76 MHz, 155.52 MHz. MHz, default type PECL.
45
SYNC2K
I
TTLD
Synchronize 2 kHz: Connect to 2 kHz Multi-Frame Sync output of partner
ACS8509 in redundancy system.
48
SEC1
I
TTLD
Input Reference SEC1: Programmable, default 19.44 MHz
(Default Priority 7).
51
SEC2
I
TTLD
Input Reference SEC2 : Programmable, default 19.44 MHz
(Default Priority 8).
54
SEC3
I
TTLD
Input Reference SEC3: Programmable, default (Master mode)
1.544/2.048 MHz, default (Slave mode) 6.48 MHz.
(Default Priority 11).
56
SEC4
I
TTLD
Input Reference SEC4 (Priority 13): Programmable, default
1.544/2.048 MHz (Default Priority 13).
58 - 60
UPSEL(2:0)
I
TTLD
Microprocessor Select: Configures the interface for a particular
microprocessor type at reset.
63 - 69
A(6:0)
I
TTLD
Microprocessor Interface Address: Address bus for the microprocessor
interface registers. A(0) is SDI in Serial mode - output in EPROM mode only.
70
CSB
I
TTLU
Chip Select (Active Low): This pin is asserted Low by the microprocessor to
enable the microprocessor interface - output in EPROM mode only.
71
WRB
I
TTLU
Write (Active Low): This pin is asserted Low by the microprocessor to
initiate a write cycle. In Motorola mode, WRB = 1 for Read.
72
RDB
I
TTLU
Read (Active Low): This pin is asserted Low by the microprocessor to
initiate a read cycle.
73
ALE
I
TTLD
Address Latch Enable: This pin becomes the address latch enable from the
microprocessor. When this pin transitions from High to Low, the address
bus inputs are latched into the internal registers. ALE = SCLK in Serial
mode.
74
PORB
I
TTLU
Power-On Reset: Master reset. If PORB is forced Low, all internal states are
reset back to default values.
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Interrupt Request: Active High software Interrupt output.
JTAG Input: Serial test data Input. Sampled on rising edge of TCK. If not
used connect to VDD or leave floating.
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ACS8509 SETS
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Table 3 Other Pins (cont...)
Pin Number
Symbol
I/O
Type
Description
Ready/Data Acknowledge: This pin is asserted High to indicate the device
has completed a read or write operation.
75
RDY
O
TTL/CMOS
76 - 83
AD(7:0)
IO
TTLD
88
O2
O
TTL/CMOS
Output Reference 2: Default 6.48 MHz. Also Dig1 (1.544 MHz/2.048 MHz
and 2, 4, 8 x), 19.44 MHz, 25.92 MHz
90
O3
O
TTL/CMOS
Output Reference 3: 19.44 MHz - fixed.
95
O4
O
TTL/CMOS
Output Reference 4: 1.544/2.048 MHz, (T4 BITS).
99
MSTSLVB
I
TTLU
Master/Slave Select: Sets the initial power-up state (or state after a PORB)
of the Master/Slave selection register, Reg. 34, Bit 1. The register state
can be changed after power up by software.
100
SONSDHB
I
TTLD
SONET or SDH Frequency Select: Sets the initial power-up state (or state
after a PORB) of the SONET/SDH frequency selection registers, Reg. 34, Bit
2 and Reg. 38, Bit 5 and Bit 6. When set Low, SDH rates are selected
(2.048 MHz etc.) and when set High, SONET rates are selected (1.544 MHz
etc.) The register states can be changed after power-up by software.
Revision 2.00/January 2006 © Semtech Corp.
Address/Data: Multiplexed data/address bus depending on the
microprocessor mode selection. AD(0) is SDO in Serial mode.
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ACS8509 SETS
ADVANCED COMMUNICATIONS
Functional Description
FINAL
The ACS8509 is a highly integrated, single-chip solution
for the SETS function in a SONET/SDH Network Element,
for the generation of SEC and frame synchronization
pulses.
In Free-run mode, the ACS8509 generates a stable, low
noise clock signal from an internal oscillator.
In Locked mode, the ACS8509 selects the most
appropriate input reference source and generates a
stable, low-noise clock signal locked to the selected
reference.
Parameter
In all modes, the frequency accuracy, jitter and drift
performance of the clock meet the requirements of ITU
G.812[10], G.813[11], G.823[13], and Telcordia GR-1244CORE[19].
The ACS8509 supports all three types of reference clock
source: recovered line clock (TIN1), PDH network
synchronization timing (TIN2) and node synchronization
(TIN3). The ACS8509 generates independent TOUT0 and
TOUT4 clocks, an 8 kHz Frame Synchronization clock and
a 2 kHz Multi-Frame Synchronization clock.
The ACS8509 has a high tolerance to input jitter and
wander. The jitter/wander transfer is programmable (0.1
Hz up to 20 Hz cut-off points).
The ACS8509 supports protection. Two ACS8509 devices
can be configured to provide protection against a single
ACS8509 failure.
The protection maintains alignment of the two ACS8509
devices (Master and Slave) and ensures that both
ACS8509 devices maintain the same priority table,
choose the same reference input and generate the TOUT0
clock, the 8 kHz Frame Synchronization clock and the 2
kHz Multi-Frame Synchronization clock with the same
phase.
The ACS8509 includes a microprocessor port, providing
access to the configuration and status registers for device
setup and monitoring.
The Master system clock on the ACS8509 should be
provided by an external clock oscillator of frequency
Revision 2.00/January 2006 © Semtech Corp.
12.80 MHz. The clock specification is important for
meeting the ITU/ETSI and Telcordia performance
requirements for Holdover mode. ITU and ETSI
specifications permit a combined drift characteristic, at
constant temperature, of all non-temperature related
parameters, of up to 10 ppb per day. The same
specifications allow a drift of 1 ppm over a temperature
range of 0 to +70°C.
Table 4 ITU and ETSI Specification
In Holdover mode, the ACS8509 generates a stable, lownoise clock signal from the internal oscillator, adjusted to
match the last known good frequency of the last selected
reference source.
Local Oscillator Clock
DATASHEET
Value
Tolerance
±4.6 ppm over 20 year lifetime
Drift
(Frequency Drift
over supply
voltage range of
+2.7 V to +3.3 V)
±0.05 ppm/15 seconds @ constant temp.
±0.01 ppm/day @ constant temp.
±1 ppm over temp. range 0 to +70°C
Telcordia specifications are somewhat tighter, requiring a
non-temperature-related drift of less than 40 ppb per day
and a drift of 280 ppb over the temperature range 0 to
+50°C.
Table 5 Telcordia GR-1244 CORE Specification
Parameter
Value
Tolerance
±4.6 ppm over 20 year lifetime
Drift
(Frequency Drift
over supply
voltage range of
+2.7 V to +3.3 V)
±0.05 ppm/15 seconds @ constant temp.
±0.04 ppm/15 seconds @ constant temp.
±0.28 ppm/over temp. range 0 to +50°C
Please contact Semtech for information on crystal
oscillator suppliers.
Crystal Frequency Calibration
The absolute crystal frequency accuracy is less important
than the stability since any frequency offset can be
compensated by adjustment of register values in the IC.
This allows for calibration and compensation of any
crystal frequency variation away from its nominal value.
± 50 ppm adjustment would be sufficient to cope with
most crystals, in fact the range is an order of magnitude
larger due to the use of two 8-bit register locations. The
setting of the conf_nominal_frequency register allows for
this adjustment. An increase in the register value
increases the output frequencies by 0.02 ppm for each
LSB step. The default value (in decimal) is 39321.
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ACS8509 SETS
ADVANCED COMMUNICATIONS
FINAL
The minimum being 0 and the maximum 65535, gives a
-700 ppm to +500 ppm adjustment range of the output
frequencies.
For example, if the crystal was oscillating at 12.8 MHz
+ 5 ppm, then the calibration value in the register to give
a -5 ppm adjustment in output frequencies to
compensate for the crystal inaccuracy, would be:
39321 - (5 / 0.02) = 39071 (decimal)
frequency being 77.76 MHz. The actual spot frequencies
supported are:
• 2 kHz,
• 4 kHz,
• 8 kHz (and N x 8 kHz),
• 1.544 MHz (SONET)/2.048 MHz (SDH),
• 6.48 MHz,
Input Interfaces
• 19.44 MHz,
The ACS8509 supports up to four input reference clock
sources from input types TIN1, TIN2 and TIN3 using TTL/
CMOS I/O technologies. These interface technologies
support +3.3 V and +5 V operation.
• 25.92 MHz,
• 38.88 MHz,
• 51.84 MHz,
• 77.76 MHz.
Over-Voltage Protection
The ACS8509 may require Over-Voltage Protection on
input reference clock ports according to ITU
Recommendation K.41. Semtech protection devices are
recommended for this purpose (see separate Semtech
data book).
Input Reference Clock Ports
Table 6 gives details of the input reference ports, showing
the input technologies and the range of frequencies
supported on each port; the default spot frequencies and
default priorities assigned to each port on power-up or by
reset are also shown. Note that SDH and SONET networks
use different default frequencies; the network type is pinselectable using the SONSDHB pin). Specific frequencies
and priorities are set by configuration.
Although each input port is shown as belonging to one of
the types, TIN1, TIN2 or TIN3, they are fully interchangeable
as long as the selected speed is within the maximum
operating speed of the input port technology.
SDH and SONET networks use different default
frequencies; the network type is selectable using the
config_mode register 34 Hex, bit 2.
For SONET, config_mode register 34 Hex, bit 2 = 1, for
SDH config_mode register 34 Hex, bit 2 = 0. On power-up
or by reset, the default will be set by the state of the
SONSDHB pin (pin 100). Specific frequencies and
priorities are set by configuration.
TTL ports (compatible also with CMOS signals) support
clock speeds up to 100 MHz, with the highest spot
Revision 2.00/January 2006 © Semtech Corp.
DATASHEET
The frequency selection is programmed via the
cnfg_ref_source_frequency register. The internal DPLL
will normally lock to the selected input at the frequency of
the input, e.g. 19.44 MHz will lock the DPLL phase
comparisons at 19.44 MHz. It is, however, possible to
utilize an internal pre-divider to the DPLL to divide the
input frequency before it is used for phase comparisons in
the DPLL. This pre-divider can be used in one of 2 ways:
1. Any of the supported spot frequencies can be divided
to 8 kHz by setting the lock8K bit (bit 6) in the
appropriate cnfg_ref_source_frequency register
location. For good jitter tolerance for all frequencies
and for operation at 19.44 MHz and above, use
lock8K. It is possible to choose which edge of the
8 kHz input to lock to, by setting the appropriate bit of
the cnfg_control1 register.
2. Any multiple of 8 kHz between 1544 kHz to 100 MHz
can be supported by using the DivN feature (bit 7 of
the cnfg_ref_source_frequency register). Any
reference input can be set to use DivN independently
of the frequencies and configurations of the other
inputs.
Any reference input with the DivN bit set in the
cnfg_ref_source_frequency register will employ the
internal pre-divider prior to the DPLL locking.
The cnfg_freq_divn register contains the divider ratio N
where the reference input will get divided by (N+1) where
0 100s
Reference sources are flagged as valid when
active, in-band and have no phase alarm set.
(4) valid standby ref
&
[main ref invalid or
(higher-priority ref valid
& in revertive mode) or
out of lock > 100s]
All sources are continuously checked for
activity and frequency
Pre-locked
wait for up to 100s
(state 110)
Only the main source is checked for phase.
A phase lock alarm is only raised on a
reference when that reference has lost phase
whilst being used as the main reference. The
micro-processor can reset the phase lock
alarm.
(5) selected ref
phase locked
A source is considered to have phase locked
when it has been continuously in phase lock
for between 1 and 2 seconds.
Locked
keep ref
(state 100)
(6) no valid standby ref
&
main ref invalid
(10) selected source
phase locked
(8) phase
regained
(9) valid standby ref
within 100s
&
[main ref invalid or
(higher priority ref valid
& in revertive mode)]
Pre-locked2
wait for up to 100s
(state 101)
(12) valid standby ref
&
(main ref invalid
or out of lock >100s)
(15) valid standby ref
&
[main ref invalid or
(higher-priority ref valid
& in revertive mode) or
out of lock >100s]
Revision 2.00/January 2006 © Semtech Corp.
(7) phase lost
on main ref
(11) no valid standby ref
&
Lost-phase
(main ref invalid
wait for up to 100s
or out of lock >100s)
(state 111)
Holdover
select ref
(state 010)
(13) no valid standby ref
&
(main ref invalid
or out of lock >100s)
(14) all refs evaluated
&
at least one ref valid
Page 44
F8530D_018AutoModeContStateDia_02
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Electrical Specification
FINAL
DATASHEET
Maximum Ratings
Important Note: The “Absolute Maximum Ratings”are stress ratings only, and functional operation of the device at
conditions other than those indicated in the “Operating Conditions” sections of this specification are not implied.
Exposure to the absolute maximum ratings for an extended period may reduce the reliability or useful lifetime of the
product.
Table 16 Absolute Maximum Ratings
Parameter
Symbol
Minimum
Maximum
Units
Power Supply (dc voltage)
VDD, VD+, VA1+, VA2+, VDD_DIFF
VDD
-0.5
3.6
V
Input Voltage (non-supply pins)
VIN
-
5.5
V
VOUT
-
5.5
V
TA
-40
+85
o
TSTOR
-50
+150
o
Output Voltage (non-supply pins)
Ambient Operating Temperature Range
Storage Temperature
C
C
Operating Conditions
Table 17 Operating Conditions
Parameter
Symbol
Minimum
Typical
Maximum
Units
Power Supply (dc voltage)
VDD, VD+, VA1+, VA2+, VDD_DIFF
VDD
3.0
3.3
3.6
V
Power Supply (dc voltage) VDD5
VDD5
3.0
3.3/5.0
5.5
V
Ambient Temperature Range
TA
-40
-
+85
o
Supply Current
(Typical - one 19 MHz output)
IDD
-
130
222
mA
Total Power Dissipation
PTOT
-
430
800
mW
C
DC Characteristics
Table 18 DC Characteristics: TTL Input Port
Across all operating conditions, unless otherwise stated
Parameter
Symbol
Minimum
Typical
Maximum
Units
VIN High
VIH
2.0
-
-
V
VIN Low
VIL
-
-
0.8
V
Input Current
IIN
-
-
10
µA
Revision 2.00/January 2006 © Semtech Corp.
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Table 19 DC Characteristics: TTL Input Port with Internal Pull-up
Across all operating conditions, unless otherwise stated
Parameter
Symbol
Minimum
Typical
Maximum
Units
VIN High
VIH
2
-
-
V
VIN Low
VIL
-
-
0.8
V
Pull-up Resistor
PU
30
-
80
kΩ
Input Current
IIN
-
-
120
µΑ
Table 20 DC Characteristics: TTL Input Port with Internal Pull-down
Across all operating conditions, unless otherwise stated
Parameter
Symbol
Minimum
Typical
Maximum
Units
VIN High
VIH
2.0
-
-
V
VIN Low
VIL
-
-
0.8
V
Pull-down Resistor
PD
30
-
80
kΩ
Input Current
IIN
-
-
120
µA
Symbol
Minimum
Typical
Maximum
Units
VOUT Low (lOL = 4 mA)
VOL
0
-
0.4
V
VOUT High (lOH = 4 mA)
VOH
2.4
-
-
V
ID
-
-
4
mA
Symbol
Minimum
Typical
Maximum
Units
PECL Output Low Voltage (Note (ii))
VOLPECL
VDD-2.10
-
VDD-1.62
V
PECL Output High Voltage (Note (ii))
VOHPECL
VDD-1.25
-
VDD-0.88
V
PECL Output Differential Voltage (Note (i))
VODPECL
580
-
900
mV
Table 21 DC Characteristics: TTL Output Port
Across all operating conditions, unless otherwise stated
Parameter
Drive Current
Table 22 DC Characteristics: PECL Output Port
Across all operating conditions, unless otherwise stated
Parameter
Notes: (i) Assuming a differential input voltage of at least 100 mV.
(ii) With 50 Ω load on each pin to VDD -2 V, i.e. 82 Ω to GND and 130 Ω to VDD.
Revision 2.00/January 2006 © Semtech Corp.
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Figure 11 Recommended Line Termination for PECL Output Port
VDD
ZO = 50Ω
O1POS
ZO = 50Ω
O1NEG
130 Ω
82 Ω
Frequencies:
19.44 MHz
51.84 MHz
77.76 MHz
155.52 MHz
130 Ω
82 Ω
ZO = Transmission line Impedance
VDD = +3.3 V
F8509D_024PECL_02
GND
Table 23 DC Characteristics: LVDS Output Port
Across all operating conditions, unless otherwise stated
Parameter
Symbol
Minimum
Typical
Maximum
Units
LVDS Output High Voltage
(Note (i))
VOHLVDS
-
-
1.585
V
LVDS Output Low Voltage
(Note (i))
VOLLVDS
0.885
-
-
V
LVDS Differential Output Voltage
VODLVDS
250
-
450
mV
LVDS Change in Magnitude of Differential
Output Voltage for complementary States
(Note (i))
VDOSLVDS
-
-
25
mV
LVDS Output Offset Voltage
Temperature = 25oC (Note (i))
VOSLVDS
1.125
-
1.275
V
Note:
(i) With 100 Ω load between the differential outputs.
Figure 12 Recommended Line Termination for LVDS Output Port
01POS
01NEG
ZO = 50Ω
ZO = 50Ω
100 Ω
ZO = Transmission line Impedance
Revision 2.00/January 2006 © Semtech Corp.
Page 47
Frequencies:
19.44 MHz
51.84 MHZ
77.76 MHz
155.52 MHz
F8509D_025LVDS_01
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Jitter Performance
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DATASHEET
Table 24 DC Characteristics: Output Jitter Generation (Test Definition G.813)
Across all operating conditions unless otherwise stated
Output jitter generation measured over 60 seconds interval, UIp-p max measured using Vectron 6664 12.8 MHz
TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.
Test Definition
Filter used
UI Spec
UI Measurement on ACS8509
G813[11] for 155 MHz option 1
500 Hz to 1.3 MHz UIp-p = 0.5
0.058 (Note (ii))
G813[11]
65 kHz to 1.3 MHz UIp-p = 0.1
0.048 (Note (iii)
0.048 (Note (ii))
for 155 MHz option 1
0.053 (Note (iv))
0.053 (Note (v))
0.058 (Note (vi))
0.053 (Note (vii))
G813
[11]
for 155 MHz option 2
12 kHz to 1.3 MHz UIp-p = 0.1
0.053 (Note (ii))
0.058 (Note (iii))
0.057 (Note (viii))
0.055 (Note (ix))
0.057 (Note (x))
0.057 (Note (xi))
0.057 (Note (xii))
0.053 (Note (xiii))
G813[11] and G812[10] for 2.048 MHz option 1 20 Hz to 100 kHz
UIp-p = 0.05
0.046 (Note (xiv))
Table 25 DC Characteristics: Output Jitter Generation (Test Definition G812)
Across all operating conditions unless otherwise stated
Output jitter generation measured over 60 seconds interval, UIp-p max measured using Vectron 6664 12.8 MHz
TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.
Test Definition
Filter used
UI Spec
UI Measurement on ACS8509
G812[10] for 1.544 MHz
10 Hz to 40 kHz
G812[10]
500 Hz to 1.3 MHz UIp-p = 0.5
0.058 (Note (xv))
65 Hz to 1.3 MHz
0.048 (Note (xv))
for 155.52 MHz electrical
G812[10] for 2.048 MHz
Revision 2.00/January 2006 © Semtech Corp.
UIp-p = 0.05
UIp-p = 0.075
Page 48
0.036 (Note (xiv))
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Table 26 DC Characteristics: Output Jitter Generation (Test Definition ETS-300-462-3)
Across all operating conditions unless otherwise stated
Output jitter generation measured over 60 seconds interval, UIp-p max measured using Vectron 6664 12.8 MHz
TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.
Test Definition
Filter used
UI Spec
UI Measurement on ACS8509
ETS-300-462-3[3] for 2.048 MHz SEC
20 Hz to 100 kHz
UIp-p = 0.5
0.046 (Note (xiv))
ETS-300-462-3[3] for 2.048 MHz SEC (Filter
spec 49 Hz to 100 kHz)
20 Hz to 100 kHz
UIp-p = 0.2
0.046 (Note (xiv))
ETS-300-462-3[3] for 2.048 MHz SSU
20 Hz to 100 kHz
UIp-p = 0.05
0.046 (Note (xiv))
ETS-300-462-3[3] for 155.52 MHz
500 Hz to 1.3 MHz UIp-p = 0.5
0.058 (Note (xv))
ETS-300-462-3[3] for 155.52 MHz
65 kHz to 1.3 MHz UIp-p = 0.1
0.048 (Note (xv))
Table 27 DC Characteristics: Output Jitter Generation (Test Definition GR-253-CORE)
Across all operating conditions unless otherwise stated
Output jitter generation measured over 60 seconds interval, UIp-p max measured using Vectron 6664 12.8 MHz
TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.
Test Definition
Filter used
UI Spec
UI Measurement on ACS8509
GR-253-CORE[17] net i/f, 51.84 MHz
100 Hz to 0.4 MHz UIp-p = 1.5
0.022 (Note (xv))
GR-253-CORE[17] net i/f, 51.84 MHz (Filter
spec 20 kHz to 400 Hz)
18 kHz to 0.4 MHz UIp-p = 0.15
0.019 (Note (xv))
GR-253-CORE[17] net i/f, 155.52 MHz
500 Hz to 1.3 MHz UIp-p = 1.5
0.058 (Note (xv))
GR-253-CORE[17] net i/f, 155.52 MHz
65 kHz to 1.3 MHz UIp-p = 0.15
0.048 (Note (xv))
GR-253-CORE[17] cat II elect i/f, 155.52 MHz
12 kHz to 400 kHz UIp-p = 0.1
0.057 (Note (xv))
UIrms= 0.1
0.006 (Note (xv))
12 kHz to 1.3 MHz UIp-p = 0.1
0.017 (Note (xv))
GR-253-CORE[17] cat II elect i/f, 51.84 MHz
GR-253-CORE[17] DS1 i/f, 1.544 MHz
Revision 2.00/January 2006 © Semtech Corp.
10_Hz to 40 kHz
UIrms= 0.01
0.003 (Note (xv))
UIp-p = 0.1
0.036 (Note (xiv))
UIrms= 0.01
0.0055 (Note (xiv))
Page 49
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Table 28 DC Characteristics: Output Jitter Generation (Test Definition AT&T 62411)
Across all operating conditions unless otherwise stated
Output jitter generation measured over 60 seconds interval, UIp-p max measured using Vectron 6664 12.8 MHz
TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.
Test Definition
Filter used
UI Spec
UI Measurement on ACS8509
AT&T 62411[2] for 1.544 MHz
(Filter spec 10 Hz to 8 kHz)
10 Hz to 40 kHz
UIrms = 0.02
0.0055 (Note (xiv))
AT&T 62411[2] for 1.544 MHz
10 Hz to 40 kHz
UIrms = 0.025
0.0055 (Note (xiv))
10 Hz to 40 kHz
UIrms = 0.025
0.0055 (Note (xiv))
Broadband
UIrms = 0.05
0.0055 (Note (xiv))
AT&T 62411
[2]
for 1.544 MHz
AT&T 62411[2] for 1.544 MHz
Table 29 DC Characteristics: Output Jitter Generation (Test Definition G.742)
Across all operating conditions unless otherwise stated
Output jitter generation measured over 60 seconds interval, UIp-p max measured using Vectron 6664 12.8 MHz
TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.
Test Definition
Filter used
UI Spec
UI Measurement on ACS8509
G-742[8] for 2.048 MHz
DC to 100 kHz
UIp-p = 0.25
0.047 (Note (xiv))
G-742[8] for 2.048 MHz
(Filter spec 18 kHz to 100 kHz)
20 Hz to 100 kHz
UIp-p = 0.05
0.046 (Note (xiv))
G-742[8] for 2.048 MHz
20 Hz to 100 kHz
UIp-p = 0.05
0.046 (Note (xiv))
Table 30 DC Characteristics: Output Jitter Generation (Test Definition GR-499-CORE)
Across all operating conditions unless otherwise stated
Output jitter generation measured over 60 seconds interval, UIp-p max measured using Vectron 6664 12.8 MHz
TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.
Test Definition
Filter used
UI Spec
UI Measurement on ACS8509
GR-499-CORE[18] & G824[14] for 1.544 MHz
10 Hz to 40 kHz
UIp-p = 5.0
0.036 (Note (xiv))
GR-499-CORE[18] & G824[14] for 1.544 MHz
(Filter spec 8 kHz to 40 kHz)
10 Hz to 40 kHz
UIp-p = 0.1
0.036 (Note (xiv))
GR-499-CORE[18] for 1.544 MHz
>10 Hz
UIp-p = 0.05
0.036 (Note (xiv))
Revision 2.00/January 2006 © Semtech Corp.
Page 50
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Notes for Tables 24 to 30
Notes: (i) Filter used is that defined by test definition unless otherwise stated
(ii) 5 Hz bandwidth, 19.44 MHz direct lock.
(iii) 5 Hz bandwidth, 8 kHz lock.
(iv) 20 Hz bandwidth, 19.44 MHz direct lock.
(v) 20 Hz bandwidth, 8 kHz lock.
(vi) 10 Hz bandwidth, 19.44 MHz direct lock.
(vii) 10 Hz bandwidth, 8 kHz lock.
(viii) 2.5 Hz bandwidth, 19.44 MHz direct lock.
(ix) 2.5 Hz bandwidth, 8 kHz lock.
(x) 1.2 Hz bandwidth, 19.44 MHz direct lock.
(xi) 1.2 Hz bandwidth, 8 kHz lock.
(xii) 0.6 Hz bandwidth, 19.44 MHz direct lock.
(xiii) 0.6 Hz bandwidth, 8 kHz lock.
(xiv) 5 Hz bandwidth, 8 kHz lock, 2.048 MHz input.
(xv) 5 Hz bandwidth, 8 kHz lock, 19.44 MHz input.
Figure 13 JTAG Timing
tCYC
TCK
tSUR
tHT
TMS
TDI
tDOD
TDO
F8110D_022JTAGTiming_01
Table 31 JTAG Timing (for use with Figure 13)
Parameter
Symbol
Minimum
Typical
Maximum
Units
Cycle Time
tCYC
50
-
-
ns
TMS/TDI to TCK rising edge time
tSUR
3
-
-
ns
TCK rising to TMS/TDI hold time
tHT
23
-
-
ns
tDOD
-
-
5
ns
TCK falling to TDO valid
Revision 2.00/January 2006 © Semtech Corp.
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Input/Output Timing
FINAL
DATASHEET
Figure 14 Input/Output Timing with Phase Build-out Off
Revision 2.00/January 2006 © Semtech Corp.
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Motorola Mode
In MOTOROLA mode, the device is configured to interface with a microprocessor using a 680x0 type bus as parallel
data + address. Figure 15 and Figure 16 show the timing diagrams of read and write accesses for this mode.
Figure 15 Read Access Timing in MOTOROLA Mode
tpw1
CSB
tsu2
WRB
th2
X
X
th1
tsu1
A
X
address
X
td1
AD
Z
data
td2
RDY
(DTACK)
td3
tpw2
th3
Z
td4
Z
Z
F8110D_007ReadAccMotor_01
Table 32 Read Access Timing in MOTOROLA Mode (for use with Figure 15)
Symbol
Note:
Parameter
MIN
TYP
MAX
tsu1
Setup A valid to CSBfalling edge
0 ns
-
-
tsu2
Setup WRB valid to CSBfalling edge
0 ns
-
-
td1
Delay CSBfalling edge to AD valid
-
-
177 ns
td2
Delay CSBfalling edge to DTACKrising edge
-
-
13 ns
td3
Delay CSBrising edge to AD high-Z
-
-
0 ns
td4
Delay CSBrising edge to RDY high-Z
-
-
7 ns
-
-
310 ns
-
472 ns
ns(i)
tpw1
CSB Low time
tpw2
RDY High time
th1
Hold A valid after CSBrising edge
0 ns
-
-
th2
Hold WRB valid after CSBrising edge
0 ns
-
-
th3
Hold CSB Low after RDYfalling edge
0 ns
-
-
tp
Time between consecutive accesses (CSBrising edge to CSBfalling edge)
320 ns
-
-
485
(i) Timing with RDY. If RDY not used, tpw1 becomes 178 ns.
Revision 2.00/January 2006 © Semtech Corp.
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Figure 16 Write Access Timing in MOTOROLA Mode
tpw1
CSB
tsu2
WRB
th2
X
X
th1
tsu1
A
X
address
X
tsu3
AD
data
X
td2
RDY
(DTACK)
th4
tpw2
th3
X
td4
Z
Z
F8110D_008WriteAccMotor_01
Table 33 Write Access Timing in MOTOROLA Mode (for use with Figure 16)
Symbol
Note:
Parameter
MIN
TYP
MAX
tsu1
Setup A valid to CSBfalling edge
0 ns
-
-
tsu2
Setup WRB valid to CSBfalling edge
0 ns
-
-
tsu3
Setup AD valid before CSBrising edge
3 ns
-
-
td2
Delay CSBfalling edge to RDYrising edge
-
-
13 ns
td4
Delay CSBrising edge to RDY High-Z
-
-
7 ns
tpw1
CSB Low time
485 ns(i)
-
-
tpw2
RDY High time
310 ns
-
472 ns
th1
Hold A valid after CSBrising edge
3 ns
-
-
th2
Hold WRB Low after CSBrising edge
0 ns
-
-
th3
Hold CSB Low after RDYfalling edge
0 ns
-
-
th4
Hold AD valid after CSBrising edge
4 ns
-
-
tp
Time between consecutive accesses (CSBrising edge to CSBfalling edge)
320 ns
-
-
(i) Timing with RDY. If RDY not used, tpw1 becomes 178 ns.
Revision 2.00/January 2006 © Semtech Corp.
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Intel Mode
In Intel mode, the device is configured to interface with a microprocessor using a 80x86 type bus as parallel data +
address. Figure 17 and Figure 18 show the timing diagrams of read and write accesses for this mode.
Figure 17 Read Access Timing in INTEL Mode
CSB
WRB
tpw1
tsu2
th2
RDB
th1
tsu1
A
address
td1
td4
Z
data
AD
td3
td2
tpw2
th3
td5
Z
RDY
F8110D_009ReadAccIntel_01
Table 34 Read Access Timing in INTEL Mode (for use with Figure 17)
Symbol
Note:
Parameter
MIN
TYP
MAX
tsu1
Setup A valid to CSBfalling edge
0 ns
-
-
tsu2
Setup CSBfalling edge to RDBfalling edge
0 ns
-
-
td1
Delay RDBfalling edge to AD valid
-
-
177 ns
td2
Delay CSBfalling edge to RDY active
-
-
13 ns
td3
Delay RDBfalling edge to RDYfalling edge
-
-
14 ns
td4
Delay RDBrising edge to AD high-Z
-
-
10 ns
td5
Delay CSBrising edge to RDY high-Z
-
-
9 ns
-
-
310 ns
-
472 ns
(i)
tpw1
RDB Low time
486 ns
tpw2
RDY Low time
th1
Hold A valid after RDBrising edge
0 ns
-
-
th2
Hold CSB Low after RDBrising edge
0 ns
-
-
th3
Hold RDB Low after RDYrising edge
0 ns
-
-
tp
Time between consecutive accesses (RDBrising edge to RDBfalling edge,
or RDBrising edge to WRBfalling edge)
320 ns
-
-
(i) Timing with RDY. If RDY not used, tpw1 becomes 180 ns.
Revision 2.00/January 2006 © Semtech Corp.
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Figure 18 Write Access Timing in INTEL Mode
CSB
tpw1
tsu2
th2
WRB
RDB
tsu1
th1
address
A
tsu3
th4
data
AD
td3
td2
RDY
tpw2
th3
td5
Z
Z
F8110D_010WriteAccIntel_01
Table 35 Write Access Timing in INTEL Mode (for use with Figure 18)
Symbol
Parameter
MIN
TYP
MAX
tsu1
Setup A valid to CSBfalling edge
0 ns
-
-
tsu2
Setup CSBfalling edge to WRBfalling edge
0 ns
-
-
tsu3
Setup AD valid before WRBrising edge
3 ns
-
-
td2
Delay CSBfalling edge to RDY active
-
-
13 ns
td3
Delay WRBfalling edge to RDYfalling edge
-
-
14 ns
td5
Delay CSBrising edge to RDY high-Z
-
-
9 ns
tpw1
WRB Low time
486 ns(i)
-
-
tpw2
RDY Low time
310 ns
-
472 ns
-
-
ns(ii)
th1
Hold A valid after WRBrising edge
th2
Hold CSB Low after WRBrising edge
0 ns
-
-
th3
Hold WRB Low after RDYrising edge
0 ns
-
-
th4
Hold AD valid after WRBrising edge
4 ns
-
-
tp
Time between consecutive accesses (WRBrising edge to WRBfalling edge,
or WRBrising edge to RDBfalling edge)
320 ns
-
-
170
Notes: (i) Timing with RDY. If RDY not used, tpw1 becomes 180 ns.
(ii) Timing if th2 is greater than 170 ns, otherwise 5 ns after CSB rising edge.
Revision 2.00/January 2006 © Semtech Corp.
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Multiplexed Mode
In MULTIPLEXED mode, the device is configured to interface with a microprocessor using a multiplexed address/data
bus. Figures 19 and 20 show the timing diagrams of read and write accesses.
Figure 19 Read Access Timing in MULTIPLEXED Mode
tpw3
tp1
ALE
tsu1
th1
CSB
tsu2
WRB
tpw1
th2
RDB
td1
address
AD
X
td2
RDY
td4
data
td3
tpw2
X
th3
td5
Z
Z
F8110D_011ReadAccMultiplex_01
Table 36 Read Access Timing in MULTIPLEXED Mode (for use with Figure 19)
Symbol
Note:
Parameter
MIN
TYP
MAX
tsu1
Setup AD address valid to ALEfalling edge
2 ns
-
-
tsu2
Setup CSBfalling edge to RDBfalling edge
0 ns
-
-
td1
Delay RDBfalling edge to AD data valid
-
-
177 ns
td2
Delay CSBfalling edge to RDY active
-
-
13 ns
td3
Delay RDBfalling edge to RDYfalling edge
-
-
15 ns
td4
Delay RDBrising edge to AD data high-Z
-
-
9 ns
td5
Delay CSBrising edge to RDY high-Z
-
-
10 ns
-
-
ns(i)
tpw1
RDB Low time
tpw2
RDY Low time
310 ns
-
472 ns
tpw3
ALE High time
2 ns
-
-
th1
Hold AD address valid after ALEfalling edge
3 ns
-
-
th2
Hold CSB Low after RDBrising edge
0 ns
-
-
th3
Hold RDB Low after RDYrising edge
0 ns
-
-
tp1
Time between ALEfalling edge and RDBfalling edge
0 ns
-
-
tp2
Time between consecutive accesses (RDBrising edge to ALErising edge)
320 ns
-
-
487
(i) Timing with RDY. If RDY not used, tpw1 becomes 180 ns.
Revision 2.00/January 2006 © Semtech Corp.
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Figure 20 Write Access Timing in MULTIPLEXED Mode
tpw3
tp1
ALE
tsu1
th1
CSB
tsu2
th2
tpw1
WRB
RDB
tsu3
address
AD
X
td2
RDY
th4
data
td3
tpw2
X
th3
td5
Z
Z
F8110D_012WriteAccMultiplex_01
Table 37 Write Access Timing in MULTIPLEXED Mode (For use with Figure 20)
Symbol
Note:
Parameter
MIN
TYP
MAX
tsu1
Set up AD address valid to ALEfalling edge
2 ns
-
-
tsu2
Set up CSBfalling edge to WRBfalling edge
0 ns
-
-
tsu3
Set up AD data valid to WRBrising edge
3 ns
-
-
td2
Delay CSBfalling edge to RDY active
-
-
13 ns
td3
Delay WRBfalling edge to RDYfalling edge
-
-
15 ns
td5
Delay CSBrising edge to RDY high-Z
-
-
9 ns
tpw1
WRB Low time
487 ns(i)
-
-
tpw2
RDY Low time
310 ns
-
472 ns
tpw3
ALE High time
2 ns
-
-
th1
Hold AD address valid after ALEfalling edge
3 ns
-
-
th2
Hold CSB Low after WRBrising edge
0 ns
-
-
th3
Hold WRB Low after RDYrising edge
0 ns
-
-
th4
AD data hold valid after WRBrising edge
4 ns
-
-
tp1
Time between ALEfalling edge and WRBfalling edge
0 ns
-
-
tp2
Time between consecutive accesses (WRBrising edge to ALErising edge)
320 ns
-
-
(i) Timing with RDY. If RDY not used, tpw1 becomes 180 ns.
Revision 2.00/January 2006 © Semtech Corp.
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ACS8509 SETS
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Serial Mode
In Serial mode, the device is configured to interface with a serial microprocessor bus. The combined minimum High
and Low times for SCLK define the maximum clock rate.
For Write access this is 2.77 MHz (360 ns). For Read access the maximum SCLK rate is slightly slower and is affected
by the setting of CLKE, being either 2.0 MHz (500 ns) or 1 MHz (1 us).
This mismatch in rates is caused by the sampling technique used to detect the end of the address field in Read mode.
It takes up to 3 cycles of an internal 6.40 MHz clock to start the Read process following receipt of the final address bit.
This is 468 ns. The Read data is then decoded and clocked out onto SDO directly using SCLK. With CLKE=1, the falling
edge of SCLK is used to clock out the SDO. With CLKE=0, the rising edge of SCLK is used to clock out the SDO.
A minimum period of 500 ns (468 capture plus 32 decode) is required between the final address bit and clocking it
out onto SDO. This means that to guarantee the correct operation of the Serial interface, with CLKE=0, SCLK has a
maximum clock rate of 2 MHz. With CLKE=1, SCLK has a maximum clock rate of 1 MHz.
SCLK is not required to run between accesses (i.e., when CSB = 1). The following Figures show the timing diagrams for
Write and Read access for this mode.
Figure 21 Read Access Timing in SERIAL Mode
CLKE = 0; SDO data is clocked out on the rising edge of SCLK
CSB
tsu2
tpw2
th2
ALE=SCLK
th1
tsu1
_
A(0) = SDI
R/W
tpw1
A0 A1 A2 A3 A4 A5 A6
td1
AD(0)=SDO
Output not driven, pulled low by internal resistor
td2
D0 D1 D2 D3 D4 D5 D6 D7
CLKE = 1; SDO data is clocked out on the falling edge of SCLK
CSB
th2
ALE=SCLK
_
A(0)=SDI
R/W
A0 A1 A2 A3 A4 A5 A6
td1
AD(0)=SDO
Output not driven, pulled low by internal resistor
td2
D0 D1 D2 D3 D4 D5 D6 D7
F8530D_013ReadAccSerial_01
Revision 2.00/January 2006 © Semtech Corp.
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ACS8509 SETS
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FINAL
DATASHEET
Table 38 Read Access Timing in SERIAL Mode (For use with Figure 21)
Symbol
Parameter
MIN
TYP
MAX
0 ns
-
-
160 ns
-
-
tsu1
Setup SDI valid to SCLKrising edge
tsu2
Setup CSBfalling edge to SCLKrising edge
td1
Delay SCLKrising edge (SCLKfalling edge for CLKE = 1) to SDO valid
-
-
17 ns
td2
Delay CSBrising edge to SDO high-Z
-
-
10 ns
tpw1
SCLK Low time
CLKE = 0
CLKE = 1
-
-
250 ns
500 ns
tpw2
SCLK High time
CLKE = 0
CLKE = 1
-
-
250 ns
500 ns
th1
Hold SDI valid after SCLKrising edge
170 ns
-
-
th2
Hold CSB Low after SCLKrising edge, for CLKE = 0
Hold CSB Low after SCLKfalling edge, for CLKE = 1
5 ns
-
-
tp
Time between consecutive accesses (CSBrising edge to CSBfalling edge)
160 ns
-
-
Figure 22 Write Access Timing in SERIAL Mode
CSB
tsu2
tpw2
th2
ALE=SCLK
th1
tsu1
_
A(0)=SDI
AD(0)=SDO
R/W
tpw1
A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7
Output not driven, pulled low by internal resistor
F8110D 014W it A S i l 02
Table 39 Write Access Timing in SERIAL Mode (For use with Figure 22)
Symbol
Parameter
MIN
TYP
MAX
0 ns
-
-
tsu1
Setup SDI valid to SCLKrising edge
tsu2
Setup CSBfalling edge to SCLKrising edge
160 ns
-
-
tpw1
SCLK Low time
180 ns
-
-
tpw2
SCLK High time
180 ns
-
-
th1
Hold SDI valid after SCLKrising edge
170 ns
-
-
th2
Hold CSB Low after SCLKrising edge
5 ns
-
-
tp
Time between consecutive accesses (CSBrising edge to CSBfalling edge)
160 ns
-
-
Revision 2.00/January 2006 © Semtech Corp.
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ACS8509 SETS
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FINAL
DATASHEET
EPROM Mode
This mode is suitable for use with an EPROM, in which configuration data is stored (one-way communication - status
information will not be accessible). A state machine internal to the ACS8509 device will perform numerous EPROM
read operations to read the data out of the EPROM. In EPROM Mode, the ACS8509 takes control of the bus as Master
and reads the device set-up from an AMD AM27C64 type EPROM at lowest speed (250ns) after device set-up (system
reset). The EPROM access state machine in the up interface sequences the accesses. Figure 23 shows the access
timing of the device in EPROM mode.
Further information can be found in the AMD AM27C64 datasheet.
Figure 23 Access Timing in EPROM mode
CSB (=OEB)
address
A
tacc
AD
Z
Z
data
F8110D_015ReadAccEEPROM_01
Table 40 Access Timing in EPROM mode (For use with Figure 23)
Symbol
tacc
Parameter
Delay CSBfalling edge or A change to AD valid
Revision 2.00/January 2006 © Semtech Corp.
Page 61
MIN
TYP
MAX
-
-
920 ns
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ACS8509 SETS
ADVANCED COMMUNICATIONS
Package Information
FINAL
DATASHEET
Figure 24 LQFP Package
D
2
D1 1
3
AN2
AN3
1
Section A-A
R1
S
E
1
2
R2
B
AN1
E1
A
A
B
3
AN4
L
4
L1
5
1 2 3
b
Section B-B
7
e
A
A2
c
c1
7
7
Seating plane
A1 6
b1 7
b
8
Notes
1
The top package body may be smaller than the bottom package body by as much as 0.15 mm.
2
To be determined at seating plane.
3
Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side.
D1 and E1 are maximum plastic body size dimensions including mold mismatch.
4
Details of pin 1 identifier are optional but will be located within the zone indicated.
5
Exact shape of corners can vary.
6
A1 is defined as the distance from the seating plane to the lowest point of the package body.
7
These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
8
Shows plating.
Table 41 100 Pin LQFP Package Dimension Data (for use with Figure 24)
100 LQFP
Package
Dimensions
in mm
D/E
D1/
E1
Min.
-
-
Nom.
Max.
e
AN1 AN2 AN3 AN4
-
11o
11o
0o
0o
16.00 14.00 1.50 0.10 1.40 0.50 12o
12o
-
3.5o
-
13o
13o
-
7o
-
-
-
A
A1
A2
1.40 0.05 1.35
1.60 0.15 1.45
Revision 2.00/January 2006 © Semtech Corp.
-
Page 62
R1
R2
L
0.08 0.08 0.45
-
L1
-
0.60 1.00
(ref)
0.20 0.75
-
S
b
b1
c
c1
0.20 0.17 0.17 0.09 0.09
-
0.22 0.20
-
-
-
0.27 0.23 0.20 0.16
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ACS8509 SETS
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Thermal Conditions
FINAL
DATASHEET
The device is rated for full temperature range when this package is used with a 4 layer or more PCB. Copper coverage
must exceed 50%. All pins must be soldered to the PCB. Maximum operating temperature must be reduced when the
device is used with a PCB with less than these requirements.
Figure 25 Typical 100 Pin LQFP Footprint
Width = 0.3 mm
Pitch = 0.5 mm
18.3 mm
17.0 mm (1)
14.6 mm
1.85 mm
F8509D_004QFNFootprint100_01
Notes: (i) (1) Solderable to this limit.
(ii) Square package - dimensions apply in both X and Y directions.
(iii) Typical example. The user is responsible for ensuring compatibility with PCB manufacturing process, etc.
Revision 2.00/January 2006 © Semtech Corp.
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ACS8509 SETS
ADVANCED COMMUNICATIONS
Application Information
FINAL
DATASHEET
Figure 26 Simplified Application Schematic
VDD
IC2
VDD5v
P1
VDD2
EZ1086CT-3.3
3
5v
VDD3
2
VIN
VOUT
1
0v
VDDA
GND
(+)
(+)
term_connect
100uF
C2
Power supply and ground
connections to 'star'
connect back to these
decoupling capacitors at
the regulator and only
connect together at this
point
C7
100nF
C4
100nF
10uF_TANT
C3
AGND
DGND3
ZD1
BZV90C-5.6v
Optional EPROM interface
selection
Optional Processor/EPROM
interface type selection
DGND2
DGND
Decoupling capacitor, C21 should be placed close to the xtal
pins that are being decoupled
RDY RDB CSB
ALE WRB
Int
CC parts are easily cut links that can also take SM
capacitors or Ohm resistor links.
All tcxo options to be placed as close as possible to IC1,
with short output track.
O2
VDD
O3
C29
C9
VDD
100nF
100nF
O4
DGND
DGND
VDDA
AGND
R1
X1
C10
100nF
10R
2 vdd
output
1
VDD3
gnd2
5
C11
100nF
C21
4
optn
VDDA
R6
DGND3
10R
C12
100nF
3 gnd1
Vectron
AGND
AGND
TRST
IC
NC
AGND
VA1+
TMS
INTREQ
TCK
REFCLK
DGND
VD+
VD+
DGND
DGND
VD+
NC
IC
VA2+
AGND
TDO
IC
TDI
DGND
DGND
RDY
PORB
ALE
RDB
WRB
CSB
A0
A1
A2
A3
A4
A5
A6
DGND
VDD
UPSEL0
UPSEL1
UPSEL2
IC
SEC4
IC
SEC3
IC
IC
SEC2
IC1
ACS8509
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
C8
1nF
DGND
VDD
100nF
C13
DGND
Optional
UPSEL0 Processor
UPSEL1 interface type
UPSEL2 selection
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NC
IC
IC
DGND
FrSync
MFrSync
GND_DIFF
VDD_DIFF
IC
IC
O1POS
O1NEG
GND_DIFF
VDD_DIFF
IC
IC
IC
IC
VDD5
SYNC2K
IC
IC
SEC1
DGND
VDD
txco
12.8MHz
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
DGND
VDD
VDD
DGND
O2
IC
O3
VDD
DGND
IC
IC
O4
IC
IC
IC
MSTSLVB
SONSDHB
VDD
100nF
All decoupling capacitors, C29,
C9, C13, C14, C15, C6, C5,
C12, C11, C10,C32 should be
placed close to the IC1 pins that
are being decoupled
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DGND
VDD
DGND2
C14
100nF
DGND
VDD2
C15
C32
100nF
100nF
DGND2
FrSync
MFrSync
VDD2
O1
DGND2
SYNC2K
SEC2
SEC1
SEC3
SEC4
DGND
F8509D_031EvalBdSchem_01
Revision 2.00/January 2006 © Semtech Corp.
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ACS8509 SETS
ADVANCED COMMUNICATIONS
Abbreviations
APLL
BITS
DFS
DPLL
DS1
DTO
E1
I/O
LOF
LOS
LQFP
LVDS
MTIE
NE
OCXO
PBO
PDH
PECL
PFD
PLL
POR
ppb
ppm
p-p
R/W
rms
RO
RoHS
SDH
SEC
SETS
SONET
SSF
SSU
STM
TDEV
TCXO
UI
WEEE
FINAL
References
Analogue Phase Locked Loop
Building Integrated Timing Supply
Digital Frequency Synthesis
Digital Phase Locked Loop
1544 kb/s interface rate
Discrete Time Oscillator
2048 kb/s interface rate
Input - Output
Loss of Frame Alignment
Loss Of Signal
Low profile Quad Flat Pack
Low Voltage Differential Signal
Maximum Time Interval Error
Network Element
Oven Controlled Crystal Oscillator
Phase Build-out
Plesiochronous Digital Hierarchy
Positive Emitter Coupled Logic
Phase and Frequency Detector
Phase Locked Loop
Power-On Reset
parts per billion
parts per million
peak-to-peak
Read/Write
root-mean-square
Read Only
Restrictive Use of Certain Hazardous
Substances (directive)
Synchronous Digital Hierarchy
SDH/SONET Equipment Clock
Synchronous Equipment Timing source
Synchronous Optical Network
Synchronization Signal Failure
Synchronization Supply Unit
Synchronous Transport Module
Time Deviation
Temperature Compensated Crystal
Oscillator
Unit Interval
Waste Electrical and Electronic
Equipment (directive)
Revision 2.00/January 2006 © Semtech Corp.
DATASHEET
[1] ANSI T1.101-1999 (1999)
Synchronization Interface Standard
[2] AT & T 62411 (12/1990)
ACCUNET® T1.5 Service description and Interface
Specification
[3] ETSI ETS 300 462-3, (01/1997)
Transmission and Multiplexing (TM); Generic
requirements for synchronization networks; Part 3: The
control of jitter and wander within synchronization
networks
[4] ETSI ETS 300 462-5 (09/1996)
Transmission and Multiplexing (TM); Generic
requirements for synchronization networks; Part 5: Timing
characteristics of slave clocks suitable for operation in
Synchronous Digital Hierarchy (SDH) equipment
[5] IEEE 1149.1 (1990)
Standard Test Access Port and Boundary-Scan
Architecture
[6] ITU-T G.703 (10/1998)
Physical/electrical characteristics of hierarchical digital
interfaces
[7] ITU-T G.736 (03/1993)
Characteristics of a synchronous digital multiplex
equipment operating at 2048 kbit/s
[8] ITU-T G.742 (1988)
Second order digital multiplex equipment operating at
8448 kbit/s, and using positive justification
[9] ITU-T G.783 (10/2000)
Characteristics of synchronous digital hierarchy (SDH)
equipment functional blocks
[10] ITU-T G.812 (06/1998)
Timing requirements of slave clocks suitable for use as
node clocks in synchronization networks
[11] ITU-T G.813 (08/1996)
Timing characteristics of SDH equipment slave clocks
(SEC)
[12] ITU-T G.822 (11/1988)
Controlled slip rate objectives on an international digital
connection
[13] ITU-T G.823 (03/2000)
The control of jitter and wander within digital networks
which are based on the 2048 kbit/s hierarchy
Page 65
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ACS8509 SETS
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Trademark Acknowledgements
[14] ITU-T G.824 (03/2000)
The control of jitter and wander within digital networks
which are based on the 1544 kbit/s hierarchy
Semtech and the Semtech S logo are registered
trademarks of Semtech Corporation.
[15] ITU-T G.825 (03/2000)
The control of jitter and wander within digital networks
which are based on the Synchronous Digital Hierarchy
(SDH)
ACCUNET® is a registered trademark of AT & T.
[16] ITU-T K.41 (05/1998)
Resistibility of internal interfaces of telecommunication
centres to surge overvoltages
AMD is a registered trademark of Advanced Micro
Devices, Inc.
Vectron is a registered trademark of
Vectron International.
[17] Telcordia GR-253-CORE, Issue 3 (09/ 2000)
Synchronous Optical Network (SONET) Transport
Systems: Common Generic Criteria
ICT Flexacom is a registered trademark of ICT Electronics.
[18] Telcordia GR-499-CORE, Issue 2 (12/1998)
Transport Systems Generic Requirements (TSGR)
Common requirements
Motorola is a registered trademark of Motorola, Inc.
Intel is a registered trademark of the Intel Corporation.
Telcordia is a registered trademark of Telcordia
Technologies.
[19] Telcordia GR-1244-CORE, Issue 2 (12/2000)
Clocks for the Synchronized Network: Common Generic
Criteria
Revision 2.00/January 2006 © Semtech Corp.
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ACS8509 SETS
ADVANCED COMMUNICATIONS
Revision Status/History
FINAL
The Revision Status of the datasheet, as shown in the
center of the datasheet header bar, may be DRAFT,
PRELIMINARY, or FINAL, and refers to the status of the
Device (not the datasheet) within the design cycle. DRAFT
status is used when the design is being realized but is not
yet physically available, and the datasheet content
reflects the intention of the design. The datasheet is
raised to PRELIMINARY status when initial prototype
devices are physically available, and the datasheet
content more accurately represents the realization of the
design. The datasheet is only raised to FINAL status after
DATASHEET
the device has been fully characterized, and the
datasheet content updated with measured, rather than
simulated parameter values.
This is a FINAL release (Revision 2.00) of the ACS8509
datasheet. Changes made for this document revision are
given in Table 42, together with a brief summary of
previous revisions. For specific changes between earlier
revisions, refer (where available) to those earlier
revisions. Always use the current version of the datasheet.
Table 42 Revision History
Revision
Reference
Description of Changes
1.00 September 2004 All pages
New draft.
2.00 January 2006
Updated to FINAL and updated to reflect availability of lead(Pb)-free
packaged part.
All pages
Revision 2.00/January 2006 © Semtech Corp.
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ACS8509 SETS
ADVANCED COMMUNICATIONS
Ordering Information
FINAL
DATASHEET
Table 43 Parts List
Part Number
Description
ACS8509
SETS Synchronous Equipment Timing Source for SONET or SDH Network Elements.
ACS8509T
Lead (Pb) -free packaged version of ACS8509; RoHS and WEEE compliant.
Disclaimers
Life support- This product is not designed or intended for use in life support equipment, devices or systems, or other critical
applications. This product is not authorized or warranted by Semtech for such use.
Right to change- Semtech Corporation reserves the right to make changes, without notice, to this product. Customers are advised
to obtain the latest version of the relevant information before placing orders.
Compliance to relevant standards- Operation of this device is subject to the User’s implementation and design practices. It is the
responsibility of the User to ensure equipment using this device is compliant to any relevant standards.
Contacts
For Additional Information, contact the following:
Semtech Corporation Advanced Communications Products
E-mail:
sales@semtech.com
acsupport@semtech.com
Internet:
http://www.semtech.com
USA:
200 Flynn Road, Camarillo, CA 93012-8790
Tel: +1 805 498 2111,
Fax: +1 805 498 3804
FAR EAST: 11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, R.O.C.
Tel: +886 2 2748 3380
Fax: +886 2 2748 3390
EUROPE:
Semtech Ltd., Units 2 and 3, Park Court, Premier Way,
Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN
Tel: +44 (0)1794 527 600
Fax: +44 (0)1794 527 601
ISO9001
CERTIFIED
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