ACS8510REV2.1T

ACS8510 Rev2.1 SETS Synchronous Equipment Timing Source for SONET or SDH Network Elements FINAL ADVANCED COMMUNICATIONS Description Features The ACS8510 is a highly integrated, single-chip solution for the Synchronous Equipment Timing Source (SETS) function in a SONET or SDH Network Element. The device generates SONET or SDH Equipment Clocks (SEC) and frame synchronization clocks. The ACS8510 is fully compliant with the required specifications and standards. The device supports Free-run, Locked and Holdover modes. It also supports all three types of reference clock source: recovered line clock, PDH network, and node synchronization. The ACS8510 generates independent SEC and BITS clocks, an 8 kHz Frame Synchronization clock and a 2 kHz Multi-Frame Synchronization clock. Two ACS8510 devices can be used together in a Master/Slave configuration mode allowing system protection against a single ACS8510 failure. A microprocessor port is incorporated, providing access to the configuration and status registers for device setup and monitoring. The ACS8510 supports IEEE 1149.1 JTAG boundary scan. Rev2.1 adds choice of edge alignment for 8kHz input, as well as a low jitter n x E1/DS1 output mode. Other minor changes are made, with all described in Appendix A. •Suitable for Stratum 3E*, 3, 4E and 4 SONET or SDH Equipment Clock (SEC) applications •Meets AT&T, ITU-T, ETSI and Telcordia specifications •Accepts 14 individual input reference clocks •Generates 11 output clocks •Supports Free-run, Locked and Holdover modes of operation •Robust input clock source quality monitoring on all inputs •Automatic ‘hit-less’ source switchover on loss of input •Phase build out for output clock phase continuity during input switchover and mode transitions •Microprocessor interface - Intel, Motorola, Serial, Multiplexed, EPROM •Programmable wander and jitter tracking attenuation 0.1 Hz to 20 Hz •Support for Master/Slave device configuration alignment and hot/standby redundancy •IEEE 1149.1 JTAG Boundary Scan •Single +3.3 V operation, +5 V I/O compatible •Operating temperature (ambient) -40°C to +85°C •Available in 100 pin LQFP package * Meets Holdover requirements, lowest bandwidth 0.1 Hz. Block Diagram Figure 1. Simple Block Diagram 2 x AMI 10 x TTL 2 x PECL/LVDS Programmable; 64/8kHz 2kHz 4kHz N x 8kHz 1.544/2.048MHz 6.48MHz 19.44MHz 25.92MHz 38.88MHz 51.84MHz 77.76MHz 155.52MHz Input Ports TOUT4 selector Divider Digital Loop Filter PFD DTO DPLL/Freq. Synthesis 14xSEC 9xSEC Monitors TOUT0 selector PFD Divider IEEE 1149.1 JTAG Digital Loop Filter DTO DPLL/Freq. Synthesis MFrSync TCK TDI TMS TRST TDO Output Ports Chip Clock Generator Priority Table Register Set APLL Frequency Dividers FrSync MFrSync 1 x AMI 6 x TTL 2 x PECL/LVDS Programmable: 64/8kHz 1.544/2.048MHz 3.088/4.096MHz 6.176/8.182MHz 12.352/16.384MHz 6.48MHz 19.44MHz 25.92MHz 38.88MHz 51.84MHz 77.76MHz 155.52MHz 311.04MHz 2kHz MFrSync 8kHz FrSync Microprocessor Port TCXO (*OCXO) Revision 2.00/September 2003 Semtech Corp. www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS TTable able of Cont ents Contents List of Sections Description ................................................................................................................................................................................................ 1 Block Diagram ........................................................................................................................................................................................... 1 Features ..................................................................................................................................................................................................... 1 Table of Contents ...................................................................................................................................................................................... 2 Pin Diagram ............................................................................................................................................................................................... 5 Pin Descriptions ........................................................................................................................................................................................ 6 Functional Description ............................................................................................................................................................................. 9 Local Oscillator Clock ................................................................................................................................................................................... 10 ITU and ETSI Specification ............................................................................................................................................................. 10 Telcordia GR-1244 CORE Specification ....................................................................................................................................... 10 Crystal Frequency Calibration ...................................................................................................................................................... 10 Input Interfaces ............................................................................................................................................................................................. 10 Over-Voltage Protection .............................................................................................................................................................................. 10 Input Reference Clock Ports ....................................................................................................................................................................... 11 Input Wander and Jitter Tolerance .............................................................................................................................................................. 9 Output Clock Ports ........................................................................................................................................................................................ 12 Low Speed Output Clock (DPLL2) ................................................................................................................................................. 12 High Speed Output Clock (DPLL1) ............................................................................................................................................... 12 Frame Sync and Multi-Frame Sync Clocks (Part of DPLL1) ................................................................................................... 13 Low Jitter Multiple E1/DS1 Outputs ........................................................................................................................................... 13 Output Wander and Jitter ............................................................................................................................................................................ 13 Phase Variation ............................................................................................................................................................................................. 18 Phase Build Out ............................................................................................................................................................................................. 21 Microprocessor Interface ............................................................................................................................................................................. 21 Motorola Mode ................................................................................................................................................................................ 21 Intel Mode ........................................................................................................................................................................................ 21 Multiplexed Mode ........................................................................................................................................................................... 21 Serial Mode ...................................................................................................................................................................................... 21 EPROM Mode ................................................................................................................................................................................... 21 Register Set ..................................................................................................................................................................................... 22 Configuration Registers ................................................................................................................................................................. 22 Status Registers .............................................................................................................................................................................. 22 Register Access ............................................................................................................................................................................... 22 Interrupt Enable and Clear ......................................................................................................................................................................... 22 Register Map .................................................................................................................................................................................................. 23 Register Map Description ........................................................................................................................................................................... 27 Selection of Input Reference Clock Source ............................................................................................................................................. 36 Forced Control Selection ............................................................................................................................................................... 37 Automatic Control Selection ........................................................................................................................................................ 37 Ultra Fast Switching ....................................................................................................................................................................... 37 External Protection Switching ..................................................................................................................................................... 38 Clock Quality Monitoring ............................................................................................................................................................................. 38 Activity Monitoring ....................................................................................................................................................................................... 39 Frequency Monitoring .................................................................................................................................................................................. 39 Modes of Operation ...................................................................................................................................................................................... 41 Free-run mode ................................................................................................................................................................................. 41 Pre-Locked mode ............................................................................................................................................................................ 41 Locked mode .................................................................................................................................................................................... 41 Lost_Phase mode ........................................................................................................................................................................... 41 Holdover mode ................................................................................................................................................................................ 42 Pre-Locked(2) mode ........................................................................................................................................................................ 42 Protection Facility ........................................................................................................................................................................................ 43 Alignment of Priority Tables in Master and Slave ACS8510 ................................................................................................. 44 Alignment of the Selection of Reference Sources for TOUT4 Generation in the Master and Slave ACS8510 ........... 45 Alignment of the Phases of the 8kHz and 2kHz Clocks in both Master and Slave ACS8510 ....................................... 45 JTAG .................................................................................................................................................................................................................. 45 PORB ................................................................................................................................................................................................................ 45 Electrical Specification .......................................................................................................................................................................... 48 Revision 2.00/September 2003 Semtech Corp. 2 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS DC Characteristics: AMI Input/Output Port ........................................................................................................................................... 54 Microprocessor Interface Timing .......................................................................................................................................................... 63 Motorola Mode .............................................................................................................................................................................................. 63 Intel Mode ....................................................................................................................................................................................................... 65 Multiplexed Mode ......................................................................................................................................................................................... 67 Serial Mode .................................................................................................................................................................................................... 69 EPROM Mode ................................................................................................................................................................................................. 71 Package Information .............................................................................................................................................................................. 72 Thermal Conditions ....................................................................................................................................................................................... 73 Application Information .......................................................................................................................................................................... 74 Revision History ...................................................................................................................................................................................... 75 Ordering Information .............................................................................................................................................................................. 76 Disclaimers ..................................................................................................................................................................................................... 76 List of Figures Figure 1. Simple Block Diagram ............................................................................................................................................................. 1 Figure 2. ACS8510 Pin Diagram ............................................................................................................................................................ 5 Figure 3. Minimum Input Jitter Tolerance (OC-3/STM-1) ................................................................................................................... 15 Figure 4. Minimum Input Jitter Tolerance (DS1/E1) .......................................................................................................................... 16 Figure 5. Wander and Jitter Measured Transfer Characteristics ....................................................................................................... 18 Figure 6. Maximum Time Interval Error of TOUT0 output port ........................................................................................................... 20 Figure 7. Time Deviation of TOUT0 output port ................................................................................................................................... 20 Figure 8. Phase error accumulation of TOUT0 output port in Holdover mode .................................................................................. 20 Figure 9. Inactivity and Irregularity Monitoring ................................................................................................................................... 38 Figure 10. Master-Slave Schematic ..................................................................................................................................................... 46 Figure 11. Automatic Mode Control State Diagram ........................................................................................................................... 47 Figure 12. Recommended Line Termination for PECL Input/Output Ports ...................................................................................... 51 Figure 13. Recommended Line Termination for LVDS Input/Output Ports ...................................................................................... 53 Figure 14. Signal Structure of 64 kHz/8kHz Central Clock Interface ............................................................................................ 55 Figure 15. AMI Input and Output Signal Levels .................................................................................................................................. 55 Figure 16. Recommended Line Termination for AMI Output/Output Ports ..................................................................................... 56 Figure 17. JTAG Timing ............................................................................................................................................................................ 61 Figure 18. Input/Output Timing ............................................................................................................................................................ 62 Figure 19. Read Access Timing in MOTOROLA Mode ........................................................................................................................ 63 Figure 20. Write Access Timing in MOTOROLA Mode ....................................................................................................................... 64 Figure 21. Read Access Timing in INTEL Mode ................................................................................................................................... 65 Figure 22. Write Access Timing in INTEL Mode .................................................................................................................................. 66 Figure 23. Read Access Timing in MULTIPLEXED Mode .................................................................................................................... 67 Figure 24. Write Access Timing in MULTIPLEXED Mode ................................................................................................................... 68 Figure 25. Read Access Timing in SERIAL Mode ................................................................................................................................ 69 Figure 26. Write Access Timing in SERIAL Mode ............................................................................................................................... 70 Figure 27. Access Timing in EPROM Mode ......................................................................................................................................... 71 Figure 28. LQFP Package ...................................................................................................................................................................... 72 Figure 29. Typical 100 Pin LQFP Footprint ......................................................................................................................................... 73 Figure 30. Simplified Application Schematic ...................................................................................................................................... 74 Revision 2.00/September 2003 Semtech Corp. 3 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS List of TTables ables Table 1. Power Pins .................................................................................................................................................................................... 6 Table 2. No Connections ............................................................................................................................................................................ 6 Table 3. Other Pins ..................................................................................................................................................................................... 7 Table 4. Input Reference Source Selection and Priority Table .......................................................................................................... 12 Table 5. Input ReferenceSource Jitter Tolerance ................................................................................................................................. 14 Table 6. Amplitude and Frequency Values for Jitter Tolerance ............................................................................................................ 15 Table 7. Amplitude and Frequency Values for Jitter Tolerance ............................................................................................................ 16 Table 8. Output Reference Source Selection Table ............................................................................................................................. 17 Table 9. Multiple E1/DS1 Output in Relation to Normal Outputs ..................................................................................................... 17 Table 10. Microprocessor Interface Mode Selection ......................................................................................................................... 21 Table 11. Register Map .......................................................................................................................................................................... 23 Table 12. Register Map Description ..................................................................................................................................................... 27 Table 13. Master-Slave Relationship .................................................................................................................................................... 46 Table 14. Absolute Maximum Ratings .................................................................................................................................................. 48 Table 15. Operating Conditions ............................................................................................................................................................. 48 Table 16. DC Characteristics: TTL Input Port ....................................................................................................................................... 48 Table 17. DC Characteristics: TTL Input Port with Internal Pull-up .................................................................................................... 49 Table 18. DC Characteristics: TTL Input Port with Internal Pull-down ............................................................................................... 49 Table 18. DC Characteristics: TTL Output Port .................................................................................................................................... 49 Table 20. DC Characteristics: PECL Input/Output Port ...................................................................................................................... 50 Table 21. DC Characteristics: LVDS Input/Output Port ...................................................................................................................... 52 Table 22. DC Characteristics: AMI Input/Output Port ........................................................................................................................ 54 Table 23. DC Characteristics: Ouput Jitter Generation (Test Definition G.813) ............................................................................. 57 Table 24. DC Characteristics: Ouput Jitter Generation (Test Definition G.812) ............................................................................. 57 Table 25. DC Characteristics: Ouput Jitter Generation (Test Definition ETS-300-462-3) .............................................................. 58 Table 26. DC Characteristics: Ouput Jitter Generation (Test Definition GR-253-CORE) ............................................................... 58 Table 27. DC Characteristics: Ouput Jitter Generation (Test Definition AT&T 62411) ................................................................... 59 Table 28. DC Characteristics: Ouput Jitter Generation (Test Definition G.742) .............................................................................. 59 Table 29. DC Characteristics: Ouput Jitter Generation (Test Definition TR-NWT-000499) ........................................................... 59 Table 30. DC Characteristics: Ouput Jitter Generation (Test Definition GR-1244-CORE) ............................................................. 60 Table 31. JTAG Timing (for use with Figure 17) ................................................................................................................................... 61 Table 32. Read Access Timing in MOTOROLA Mode (for use with Figure 19) ................................................................................. 63 Table 33. Write Access Timing in MOTOROLA Mode (for use with Figure 20) ................................................................................ 64 Table 34. Read Access Timing in INTEL Mode (for use with Figure 21) ............................................................................................ 65 Table 35. Write Access Timing in INTEL Mode (for use with Figure 22) ........................................................................................... 66 Table 36. Read Access Timing in MULTIPLEXED Mode (for use with Figure 23) ............................................................................. 67 Table 37. Write Access Timing in MULTIPLEXED Mode (for use with Figure 24) ............................................................................. 68 Table 38. Read Access Timing in SERIAL Mode (for use with Figure 25) ......................................................................................... 70 Table 39. Write Access Timing in SERIAL Mode (for use with Figure 26) ........................................................................................ 70 Table 40. Access Timing in EPROM Mode (for use with Figure 27) .................................................................................................. 71 Table 41. 100 Pin LQFP Package Dimension Data (for use with Figure 28) ................................................................................... 73 Revision 2.00/September 2003 Semtech Corp. 4 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Pin Diagram Figure 2. ACS8510 Pin Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 AGND TRST IC NC AGND VA1+ TMS INTREQ TCK REFCLK DGND VD+ VD+ DGND DGND VD+ NC SRCSW VA2+ AGND TDO IC TDI I1 I2 VAMI+ TO8NEG TO8POS GND_AMI FrSync MFrSync GND_DIFF VDD_DIFF TO6POS TO6NEG TO7POS TO7NEG GND_DIFF VDD_DIFF I5POS I5NEG I6POS I6NEG VDD5 SYNC2K I3 I4 I7 DGND VDD 1 ACS8510 SDH/SONET SETS Rev 2.1 NC - Not Connected; leave to Float. IC - Internally Connected; leave to Float. Revision 2.00/September 2003 Semtech Corp. 5 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SONSDHB MSTSLVB IC IC IC TO9 TO5 TO4 DGND VDD TO3 TO2 TO1 DGND VDD VDD DGND AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 RDY PORB ALE RDB WRB CSB A0 A1 A2 A3 A4 A5 A6 DGND VDD UPSEL0 UPSEL1 UPSEL2 I14 I13 I12 I11 I10 I9 I8 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Pin Descriptions Table 1. Power Pins PIN SYMB OL IO IO T YPE N A M E /DE S CR I P T I O N 12, 13, 16 VD+ P - S u p p l y v o l t a g e : Digital supply to gates in analog section, +3.3 Volts. +/- 10% 26 VAMI+ P - S u p p l y v o l t a g e : Digital supply to AMI output, +3.3 Volts. +/- 10% 33, 39 VDD_DIFF P - S u p p l y v o l t a g e : Digital supply for differential por ts, +3.3 Volts. +/- 10% 44 VDD5 P - V D D 5 : Digital supply for +5 Volts tolerance to input pins. Connect to +5 Volts (+/- 10%) for clamping to +5 Volts. Connect to VDD for clamping to +3.3 Volts. Leave floating for no clamping, input pins tolerant up to +5.5 Volts. 50, 61, 85, 86, 91 VDD P - S u p p l y v o l t a g e : Digital supply to logic, +3.3 Volts. +/- 10% 6 VA1+ P - S u p p l y v o l t a g e : Analog supply to clock multipying PLL, +3.3 Volts. +/- 10% 19 VA2+ P - S u p p l y v o l t a g e : Analog supply to output PLL, +3.3 Volts. +/- 10% 11, 14, 15, 49, 62, 84, 87, 92 DGN D P - S u p p l y G r o u n d : Digital ground for logic 29 GN D_AMI P - S u p p l y G r o u n d : Digital ground for AMI output 32, 38 GN D_DIFF P - S u p p l y G r o u n d : Digital ground for differential por ts 1, 5, 20 AGN D P - S u p p l y G r o u n d : Analog ground Table 2. No Connections PIN SYMB OL IO IO T YPE N A M E /DE S CR I P T I O N 4, 17 NC - - N o t C o n n e c t e d : Leave to Float 3, 22, 96, 97,98 IC - - I n t e r n a l l y C o n n e c t e d : Leave to Float Note: I = input, O = output, P = power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor Revision 2.00/September 2003 Semtech Corp. 6 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 3. Other Pins PIN SYMB OL IO IO T YPE N A M E /DE S CR I P T I O N 2 TRST I T T LD J TA G C o n t r o l R e s e t I n p u t : TRST = 1 to enable JTAG Boundary Scan mode. TRST = 0 for normal device op eration (JTAG logic transp arent). If not used connect to GN D or leave floating. 7 T MS I T T LU J TA G Te s t M o d e S e l e c t : Boundary Scan enable. Samp led on rising edge of TCK. If not used connect to VDD or leave floating. 8 IN T R E Q O TTL CMOS I n t e r r u p t R e q u e s t : Active high software Interrup t outp ut 9 TCK I T T LD J TA G C l o c k : Boundary Scan clock inp ut. If not used connect to GN D or leave floating. This p in may require a cap acitor p laced between the p in and the nearest GN D, to reduce noise p ickup . A value of 10 p F should be adequate, but the value is dep endent on PCB layout. 10 REFCLK I TTL R e f e r e n c e C l o c k : 12.8 MHz (refer to section headed Local Oscillator Clock) 18 SRCSW I T T LD S o u r c e S w i t c h i n g : Force Fast Source Switching 21 TDO O TTL CMOS 23 TDI I T T LU J TA G I n p u t : Serial test data Inp ut. Samp led on rising edge of TCK. If not used connect to VDD or leave floating. 24 I1 I A MI I n p u t r e f e r e n c e 1 : comp osite clock 64 kHz + 8 kHz 25 I2 I A MI I n p u t r e f e r e n c e 2 : comp osite clock 64 kHz + 8 kHz 27 TO8N EG O A MI O u t p u t r e f e r e n c e 8 : comp osite clock, 64 kHz + 8 kHz negative p ulse 28 TO8POS O A MI O u t p u t r e f e r e n c e 8 : comp osite clock, 64 kHz + 8 kHz p ositive p ulse 30 FrSync O TTL CMOS O u t p u t r e f e r e n c e 10 : 8 kHz Frame Sync clock outp ut (square wave) 31 MFrSync O TTL CMOS O u t p u t r e f e r e n c e 1 1 : 2 kHz Multi-Frame Sync clock outp ut (square wave) 34 35 TO6POS TO6N EG O LVDS PECL O u t p u t r e f e r e n c e 6 : default 38.88 MHz. Also Dig1 (1.544 MHz/2.048 MHz and 2, 4, 8 x), 19.44 MHz, 155.52 MHz, 311.04 MHz. Default typ e LVDS. 36 37 TO7POS TO7N EG O PECL LVDS O u t p u t r e f e r e n c e 7 : default 19.44 MHz. Also 51.84 MHz, 77.76 MHz, 155.52 MHz. Default typ e PECL. 40 41 I5POS I5N EG I LVDS PECL I n p u t r e f e r e n c e 5 : default 19.44 MHz, default typ e LVDS 42 43 I6POS I6N EG I PECL LVDS I n p u t r e f e r e n c e 6 : default 19.44 MHz, default typ e PECL Revision 2.00/September 2003 Semtech Corp. J TA G O u t p u t : Serial test data outp ut. Up dated on falling edge of TCK. If not used leave floating. 7 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 3. Other Pins (continued) PIN SYMB OL IO IO T YPE N A M E /DE S CR I P T I O N 45 SYN C2K I T T LD S y n c h r o n i s e 2 k H z : Connect to 2 kHz Multi-Frame Sync outp ut of p ar tner ACS8510 in redundancy system 46 I3 I T T LD I n p u t r e f e r e n c e 3 : p rogrammable, default 8 kHz 47 I4 I T T LD I n p u t r e f e r e n c e 4 : p rogrammable, default 8 kHz 48 I7 I T T LD I n p u t r e f e r e n c e 7 : p rogrammable, default 19.44 MHz 51 I8 I T T LD I n p u t r e f e r e n c e 8 : p rogrammable, default 19.44 MHz 52 I9 I T T LD I n p u t r e f e r e n c e 9 : p rogrammable, default 19.44 MHz 53 I10 I T T LD I n p u t r e f e r e n c e 10 : p rogrammable, default 19.44 MHz. 54 I11 I T T LD I n p u t r e f e r e n c e 1 1 : p rogrammable, default (master mode)1.544/2.048 MHz, default (slave mode) 6.48 MHz 55 I12 I T T LD I n p u t r e f e r e n c e 1 2 : p rogrammable, default 1.544/2.048 MHz. 56 I13 I T T LD I n p u t r e f e r e n c e 1 3 : p rogrammable, default 1.544/2.048 MHz. 57 I14 I T T LD I n p u t r e f e r e n c e 14 : p rogrammable, default 1.544/2.048 MHz. 58 - 60 UPSEL(2:0) I T T LD M i c r o p r o c e s s o r s e l e c t : Configures the inter face for a p ar ticular microp rocessor typ e. 63 - 69 A(6:0) I T T LD M i c r o p r o c e s s o r I n t e r f a c e A d d r e s s : Address bus for the microp rocessor inter face registers. A(0) is SDI in Serial mode. 70 CSB I T T LU C h i p S e l e c t ( A c t i v e L o w ) : This p in is asser ted Low by the microp rocessor to enable the microp rocessor inter face. 71 WRB I T T LU W r i t e ( A c t i v e L o w ) : This p in is asser ted Low by the microp rocessor to initiate a write cycle. In Motorola mode, WRB = 1 for Read. 72 RDB I T T LU R e a d ( A c t i v e L o w ) : This p in is asser ted Low by the microp rocessor to initiate a read cycle. 73 A LE I T T LD A d d r e s s L a t c h E n a b l e : This p in becomes the address latch enable from the microp rocessor. When this p in transitions from Low to High, the address bus inp uts are latched into the internal registers. ALE = SCLK in Serial mode. 74 PORB I T T LU P o w e r O n R e s e t : Master reset. If PORB is forced Low, all internal states are reset back to default values. 75 RDY O TTL CMOS R e a d y / D a t a a c k n o w l e d g e : This p in is asser ted High to indicate the device has comp leted a read or write op eration. 76 - 83 AD(7:0) IO T T LD A d d r e s s / D a t a : Multip lexed data/address bus dep ending on the microp rocessor mode selection. AD(0) is SDO in Serial mode. Revision 2.00/September 2003 Semtech Corp. 8 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 3. Other Pins (continued) PIN SYMB OL IO IO T YPE 88 TO1 O TTL CMOS O u t p u t r e f e r e n c e 1 : default 6.48 MHz. Also Dig1 (1.544 MHz/2.048 MHz and 2, 4, 8 x), 19.44 MHz, 25.92 MHz 89 TO2 O TTL CMOS O u t p u t r e f e r e n c e 2 : default 38.88 MHz. Also Dig2 (1.544 MHz/2.048 MHz and 2, 4, 8 x), 25.92 MHz, 51.84 MHz 90 TO3 O TTL CMOS O u t p u t r e f e r e n c e 3 : 19.44 MHz - fixed. 93 TO4 O TTL CMOS O u t p u t r e f e r e n c e 4 : 38.88 MHz - fixed. 94 TO5 O TTL CMOS O u t p u t r e f e r e n c e 5 : 77.76 MHz - fixed. 95 TO9 O TTL CMOS O u t p u t r e f e r e n c e 9 : 1.544/2.048 MHz. (T4 BITS) 99 100 MSTSLVB SON SDHB I I N A M E /DE S CR I P T I O N T T LU M A S T E R S L AV E B : Master slave select: sets the initial p ower up state (or state after a PORB) of the Master/Slave selection register, addr 34, bit 1. The register state can be changed after p ower up by software. T T LD S O N E T S D H B : SON ET or SDH frequency select: sets the initial p ower up state (or state after a PORB) of the SON ET/SDH frequency selection registers, addr 34h, bit 2 and addr 38, bits 5 and 6. The register states can be changed after p ower up by software. FFunctional unctional Description The ACS8510 is a highly integrated, single-chip solution for the SETS function in a SONET/SDH Network Element, for the generation of SEC and frame synchronization pulses. In Free-run mode, the ACS8510 generates a stable, lownoise clock signal from an internal oscillator. In Locked mode, the ACS8510 selects the most appropriate input reference source and generates a stable, low-noise clock signal locked to the selected reference. In Holdover mode, the ACS8510 generates a stable, low-noise clock signal from the internal oscillator, adjusted to match the last known good frequency of the last selected reference source. In all modes, the frequency accuracy, jitter and drift performance of the clock meet the requirements of ITU G.812, G.813, G.823, and GR-1244-CORE. Revision 2.00/September 2003 Semtech Corp. 9 The ACS8510 supports all three types of reference clock source: recovered line clock (TIN1), PDH network synchronization timing (TIN2) and node synchronization (TIN3). The ACS8510 generates independent TOUT0 and TOUT4 clocks, an 8 kHz Frame Synchronization clock and a 2 kHz Multi-Frame Synchronization clock. The ACS8510 has a high tolerance to input jitter and wander. The jitter/wander transfer is programmable (0.1 Hz up to 20 Hz cut-off points). The ACS8510 supports protection. Two ACS8510 devices can be configured to provide protection against a single ACS8510 failure. The protection maintains alignment of the two ACS8510 devices (Master and Slave) and ensures that both ACS8510 devices maintain the same priority table, choose the same www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS reference input and generate the TOUT0 clock, the 8 kHz Frame Synchronization clock and the 2 kHz Multi-Frame Synchronization clock with the same phase. The ACS8510 includes a microprocessor port, providing access to the configuration and status registers for device setup and monitoring. Local Oscillator Clock The Master system clock on the ACS8510 should be provided by an external clock oscillator of frequency 12.80 MHz. The clock specification is important for meeting the ITU/ETSI and Telcordia performance requirements for Holdover mode. ITU and ETSI specifications permit a combined drift characteristic, at constant temperature, of all non-temperaturerelated parameters, of up to 10 ppb per day. The same specifications allow a drift of 1 ppm over a temperature range of 0 to +70 °C. Telcordia specifications are somewhat tighter, requiring a non-temperature-related drift of less than 40 ppb per day and a drift of 280 ppb over the temperature range 0 to +50 °C. ITU and ETSI Specification Crystal Frequency Calibration The absolute crystal frequency accuracy is less important than the stability since any frequency offset can be compensated by adjustment of register values in the IC. This allows for calibration and compensation of any crystal frequency variation away from its nominal value. +/- 50 ppm adjustment would be sufficient to cope with most crystals, in fact the range is an order of magnitude larger due to the use of two 8 bit register locations. The setting of the conf_nominal_frequency register allows for this adjustment. An increase in the register value increases the output frequencies by 0.02 ppm for each LSB step. The default value (in decimal) is 39321. The minimum being 0 and the maximum 65535, gives a -700 ppm to +500 ppm adjustment range of the output frequencies. For example, if the crystal was oscillating at 12.8 MHz + 5 ppm, then the calibration value in the register to give a -5 ppm adjustment in output frequencies to compensate for the crystal inaccuracy, would be : 39321 - (5 / 0.02) = 39071 (decimal) Tolerance: +/- 4.6 ppm over 20 year life time. Drift*: +/- 0.05 ppm/15 seconds @ constant temp. Input Interfaces +/- 0.01 ppm/day @ constant temp. The ACS8510 supports up to fourteen input reference clock sources from input types TIN1, TIN2 and TIN3 using TTL, CMOS, PECL, LVDS and AMI buffer I/O technologies. These interface technologies support +3.3 V and +5 V operation. +/- 1 ppm over temp. range 0 to +70 °C *Frequency drift over supply range of +2.7V to +3.3V. Telcordia GR-1244 CORE Specification Tolerance: +/- 4.6 ppm over 20 year life time. Drift*: +/- 0.05 ppm/15 seconds @ constant temp. Over-Voltage Protection +/- 0.04 ppm/day @ constant temp. +/- 0.28 ppm over temp. range 0 to +50 °C *Frequency drift over supply range of +2.7V to +3.3V. Please contact Semtech for information on crystal oscillator suppliers. Revision 2.00/September 2003 Semtech Corp. 10 The ACS8510 may require Over-Voltage Protection on input reference clock ports according to ITU Recommendation K.41. Semtech protection devices are recommended for this purpose (see separate Semtech data book). www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Input Reference Clock Ports Table 4 gives details of the input reference ports, showing the input technologies and the range of frequencies supported on each port; the default spot frequencies and default priorities assigned to each port on power-up or by reset are also shown. Note that SDH and SONET networks use different default frequencies; the network type is pin-selectable (using the SONSDHB pin). Specific frequencies and priorities are set by configuration. Although each input port is shown as belonging to one of the types, TIN1, TIN2 or TIN3, they are fully interchangeable as long as the selected speed is within the maximum operating speed of the input port technology. SDH and SONET networks use different default frequencies; the network type is selectable using the config_mode register 34 Hex, bit 2. For SONET, config_mode register 34 Hex, bit 2 = 1, for SDH config_mode register 34 Hex, bit 2 = 0. On power-up or by reset, the default will be set by the state of the SONSDHB pin (pin 100). Specific frequencies and priorities are set by configuration. TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being 77.76 MHz. The actual spot frequencies supported are: • 2 kHz • 4 kHz • 8 kHz (and N x 8 kHz) • 1.544 MHz (SONET)/2.048 MHz (SDH) • 6.48 MHz, • 19.44 MHz, • 25.92 MHz, • 38.88 MHz, • 51.84 MHz, • 77.76 MHz. Revision 2.00/September 2003 Semtech Corp. 11 The frequency selection is programmed via the cnfg_ref_source_frequency register. The internal DPLL will normally lock to the selected input at the frequency of the input, eg. 19.44 MHz will lock the DPLL phase comparisons at 19.44 MHz. It is, however, possible to utilise an internal pre-divider to the DPLL to divide the input frequency before it is used for phase comparisons in the DPLL. This pre-divider can be used in one of 2 ways: 1. Any of the supported spot frequencies can be divided to 8 kHz by setting the ‘lock8K’ bit (bit 6) in the appropriate cnfg_ref_source_frequency register location. For good jitter tolerance for all frequencies and for operation at 19.44 MHz and above, use lock8K. It is possible to choose which edge of the 8kHz input to lock to, by setting the appropriate bit of the cnfg_control1 register. 2. Any multiple of 8 kHz between 1544 kHz to 100 MHz can be supported by using the ‘DivN’ feature (bit 7 of the cnfg_ref_source_frequency register). Any reference input can be set to use DivN independently of the frequencies and configurations of the other inputs. Any reference input with the DivN bit set in the cnfg_ref_source_frequency register will employ the internal pre-divider prior to the DPLL locking. The cnfg_freq_divn register contains the divider ratio N where the reference input will get divided by (N+1) where 0100s) Reference sources are flagged as 'valid' when active, 'in-band' and have no phase alarm set. (4) valid standby ref & [ main ref invalid or (higher-priority ref valid & in revertive mode) or out of lock >100s] pre-locked w ait for up to 100s (state 110) (5) selected ref phase locked All sources are continuously checked for activity and frequency. Only the main source is checked for phase. A phase lock alarm is only raised on a reference when that reference has lost phase whilst being used as the main reference. The micro-processor can reset the phase lock alarm. A source is considered to have phase locked when it has been continuously in phase lock for between 1 and 2 seconds locked keep ref (state 100) (10) selected source phase locked (9) valid standby ref & [ main ref invalid or (higher-priority ref valid & in revertive mode) ] pre-locked2 w ait for up to 100s (state 101) (12) valid standby ref & (main ref invalid or out of lock >100s) (15) valid standby ref & [ main ref invalid or (higher-priority ref valid & in revertive mode) or out of lock >100s] Revision 2.00/September 2003 Semtech Corp. (8) phase regained within 100s (6) no valid standby ref & main ref invalid (7) phase lost on main ref Lost phase w ait for up to 100s (state 111) (11) no valid standby ref & (main ref invalid or out of lock >100s) holdover select ref (state 010) (13) no valid standby ref & (main ref invalid or out of lock >100s) (14) all refs evaluated & at least one ref valid 47 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Electrical Specification Important Note Note: The ‘Absolute Maximum Ratings’ are stress ratings only, and functional operation of the device at conditions other than those indicated in the ‘Operating Conditions’ sections of this specification are not implied. Exposure to the absolute maximum ratings for an extended period may reduce the reliability or useful lifetime of the product. Table 14. Absolute Maximum Ratings PA RA METER SYMB OL M IN IN M AX AX U N ITS Sup p ly Voltage VDD, VD+, VA1+,VA2+ VDD -0.5 3.6 V Inp ut Voltage (non-sup p ly p ins) Vin - 5.5 V Outp ut Voltage (non-sup p ly p ins) Vout - 5.5 V TA -40 +85 °C Tstor -50 +150 °C Ambient Op erating Temp erature Range Storage Temp erature Table 15. Operating Conditions PA RA METER SYMB OL MIN T YP MA X U N ITS Power Sup p ly (dc voltage) VDD, VD+,VA1+, VA2+, VAMI+, VDD_DIFF VDD 3.0 3.3 3.6 V Power Sup p ly (dc voltage) VDD5 VDD5 3.0 3.3/5.0 5.5 V Ambient temp erature Range TA -40 - +85 °C Sup p ly current IDD - 110 200 mA PTOT - 360 720 mW (Typ ical - one 19 MHz outp ut) Total p ower dissip ation Table 16. DC Characteristics: TTL Input Port Across all operating conditions, unless otherwise stated PA R A M E T E R SYMB OL MIN T YP MA X U N ITS Vin High V ih 2.0 - - V Vin Low V il - - 0.8 V Inp ut current Ii n - - 10 µA Revision 2.00/September 2003 Semtech Corp. 48 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 17. DC Characteristics: TTL Input Port with Internal Pull-up Across all operating conditions, unless otherwise stated PA R A M E T E R SYMB OL MIN T YP MA X U N ITS Vin High V ih 2.0 - - V Vin Low V il - - 0.8 V Pull-up resistor PU 30 - 80 kΩ Inp ut current Ii n - - 120 µA Table 18. DC Characteristics: TTL Input Port with Internal Pull-down Across all operating conditions, unless otherwise stated PA R A M E T E R SYMB OL MIN T YP MA X U N ITS Vin High V ih 2.0 - - V Vin Low V il - - 0.8 V Pull-down resistor PD 30 - 80 kΩ Inp ut current Ii n - - 120 µA Table 19. DC Characteristics: TTL Output Port Across all operating conditions, unless otherwise stated PA R A M E T E R SYMB OL MIN T YP MA X U N ITS Vout Low Iol = 4mA Vol 0 - 0.4 V Vout High Ioh = 4mA Voh 2.4 - Drive current ID - - Revision 2.00/September 2003 Semtech Corp. 49 V 4 mA www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 20. DC Characteristics: PECL Input/Output Port Across all operating conditions, unless otherwise stated PA R A M E T E R SYMB OL MIN T YP MA X U N ITS VILPECL VDD-2.5 - VDD-0.5 V Differential inp uts (N ote 1) VIHPECL VDD-2.4 - VDD-0.4 V Inp ut Differential voltage VIDPECL 0.1 - 1.4 V VILPECL_S VDD-2.4 - VDD-1.5 V VIHPECL_S VDD-1.3 - VDD-0.5 V IIHPECL -10 - +10 µA IILPECL -10 - +10 µA VOLPECL VDD-2.10 - VDD-1.62 V VOHPECL VDD-1.25 - VDD-0.88 V VODPECL 580 - 900 mV PECL Inp ut Low voltage Differential inp uts (N ote 1) PECL Inp ut High voltage PECL Inp ut Low voltage Single ended inp ut (N ote 2) PECL Inp ut High voltage Single ended inp ut (N ote 2) Inp ut High current Inp ut differential voltage VID = 1.4v Inp ut Low current Inp ut differential voltage VID = 1.4v PECL Outp ut Low voltage (N ote 3) PECL Outp ut High voltage (N ote 3) PECL Outp ut Differential voltage (N ote 1) Notes to Table 20 Unused differential input ports should be left floating and set in LVDS mode, or the positive and negative inputs tied to VDD and GND respectively. Note 1. Assuming a differential input voltage of at least 100 mV. Note 2. Unused differential input terminated to VDD-1.4 V. Note 3. With 50 load on each pin to VDD-2 V. i.e. 82 to GND and 130 to VDD. Revision 2.00/September 2003 Semtech Corp. 50 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 12. Recommended Line Termination for PECL Input/Output Ports V DD 8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz ZO=50Ω V DD 130R ZO=50Ω I5POS ZO=50Ω 130R 82R 130R T06POS ZO=50Ω I5NEG 130R 82R T06NEG 82R 82R GND GND V DD 8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz ZO=50Ω V DD 130R ZO=50Ω I6POS ZO=50Ω 130R T07POS 130R 82R 19.44, 38.88, 155.52, 311.04 MHz & DIG1 ZO=50Ω I6NEG 130R 82R 19.44, 51.84, 77.76, 155.52 MHz T07NEG 82R 82R GND GND VDD = +3.3 V Revision 2.00/September 2003 Semtech Corp. 51 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 21. DC Characteristics: LVDS Input/Output Port Across all operating conditions, unless otherwise stated PA R A M E T E R SYMB OL MIN T YP MA X U N ITS VVRLVDS 0 - 2.40 V VDITH -100 - +100 mV VIDLVDS 0.1 - 1.4 V R TERM 95 100 105 Ω VOHLVDS - - 1.585 V VOLLVDS 0.885 - - V (N ote 1) VODLVDS 250 - 450 mV LVDS Change in magnitude of differential outp ut voltage for comp limentary states VDOSLVDS - - 25 mV VOSLVDS 1.125 - 1.275 V LVDS Inp ut voltage range Differential inp ut voltage = 100 mV LVDS Differential inp ut threshold LVDS Inp ut Differential voltage LVDS Inp ut termination resistance Must be p laced externally across the LVDS+/- inp ut p ins of ACS8510. Resistor should be 100Ω with 5% tolerance LVDS Outp ut high voltage (N ote 1) LVDS Outp ut low voltage (N ote 1) LVDS Differential outp ut voltage (N ote 1) LVDS outp ut offset voltage Temp erature = 25°C (N ote 1) Note to Table 21 Note 1. With 100 load between the differential outputs. Revision 2.00/September 2003 Semtech Corp. 52 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 13. Recommended Line Termination for LVDS Input/Output Ports 8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz 8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz ZO=50Ω ZO=50Ω I5POS ZO=50Ω T06POS 100R ZO=50Ω I5NEG T06NEG I6POS T07POS ZO=50Ω ZO=50Ω 100R 19.44, 38.88, 155.52, 311.04 MHz & DIG1 ZO=50Ω 100R ZO=50Ω I6NEG Revision 2.00/September 2003 Semtech Corp. 100R 19.44, 51.84, 77.76, 155.52 MHz T07NEG 53 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS DC Characteristics: AMI Input/Output Port Across all operating conditions, unless otherwise stated The Alternate Mark Inversion (AMI) signal is DC balanced and consists of positive and negative pulses with a peak to peak voltage of 2.0 +/- 0.2 V. The electrical specifications are taken from option a) of Table 2/G.703 - Digital 64 kbit/s centralized clock interface, from ITU G.703. Table 22. DC Characteristics: AMI Input/Output Port PA R A M E T E R SYMB OL MIN T YP MA X U N ITS Inp ut Pulse width t PW 1.56 7.8 14.04 us Inp ut Pulse rise/fall time tR/F - - 5 us AMI Inp ut voltage high V IH A M I 2.5 - VDD + 0.3 V AMI Inp ut voltage middle V V IM A M I 1.5 1.65 1.8 V AMI Inp ut voltage low V V IL A M I 0 - 1.4 V AMI Outp ut current drive IAMIOUT - - 20 mA VOH AMI VDD - 0.16 - - V Outp ut current = 20mA VOLAMI - - 0.16 V N ominal test load imp edence RTEST - 110 - Ω "Mark" amp litude after transformer V MA R K 0.9 1.0 1.1 V "Sp ace" amp litude after transformer VSPACE -0.1 0 0.1 V AMI Outp ut high voltage Outp ut current = 20mA AMI Outp ut low voltage The electrical characteristics of 64 kbits/s interface are as follows; Nominal bit rate: 64 kbit/s. The tolerance is determined by the network clock stability. There should be a symmetrical pair carrying the composite timing signal (64 kHz and 8 kHz). The use of transformers is recommended. Over-voltage protection requirement; refer to Recommendation K.41. Code conversion rules; The data signals are coded in AMI code with 100% duty cycle. The composite clock timing signals convey the 64 kHz bit-timing information using AMI coding with a 50% to 70% duty ratio and the 8 kHz octet phase information by introducing violations in the code rule. The structure of the signals and voltage levels are shown in Figures 14 and 15. Revision 2.00/September 2003 Semtech Corp. 54 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 14. Signal Structure of 64 kHz/8kHz Central Clock Interface after suitable input/output transformer (also see Figure 6/G.703) 15.6us 7.8us + 1.0V IH 1V 2V p -p 0V IM 1V -1.0V IL Figure 15. AMI Input and Output Signal Levels 15.6us Signal structure of 64 kHz/ 8 kHz central clock interface after suitable transformer. 7.8us +V D D 15.6us 7.8us 0V + 1.0V IH I_1 1V 2V p -p TO8POS C1 0V IM C2 15.6us 1V I_2 -1.0V IL TO8NEG 7.8us +V D D C1 0V Revision 2.00/September 2003 Semtech Corp. 55 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 16. Recommended Line Termination for AMI Output/Output Ports AMI input signal Turns ratio 1:1 C1 C2 AMI input signal AMI output signal to external devices TO8POS TO8NEG R load C3 GND C1 Notes The AMI inputs and should be connected to the external AMI clock source by 470 nF coupling capacitor C1. The AMI differential output TO8POS/TO8NEG should be coupled to a line transformer with a turns ration of 3:1. Components C2 = 470 pF and C3 = 2 nF. If a transformer with a turns ratio of 1:1 is used, a 3:1 ratio potential divider Rload must be used to achieve the required 1 V pp voltage level for the positive and negative pulses. Revision 2.00/September 2003 Semtech Corp. 56 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 23. DC Characteristics: Output Jitter Generation (Test Definition G.813) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Te s t d e f i n i t i o n F i l t er u sed U I sp ec U I m e a s u r e m e n t o n A C S 8 510 R ev 2 G.813 for 155.52 MHz op tion 1 500 Hz to 1.3 MHz UIpp = 0.5 0.058 (N ote 2) G.813 for 155.52 MHz op tion 1 65 kHz to 1.3 MHz UIpp = 0.1 0.048 (N ote 3) 0.048 (N ote 2) 0.053 (N ote 4) 0.053 (N ote 5) 0.058 (N ote 6) 0.053 (N ote 7) G.813 for 155.52 MHz op tion 2 12 kHz to 1.3 MHz UIpp = 0.1 0.053 (N ote 2) 0.058 (N ote 3) 0.057 (N ote 8) 0.055 (N ote 9) 0.057 (N ote 10) 0.057 (N ote 11) 0.057 (N ote 12) 0.053 (N ote 13) G.813 & G.812 for 2.048 MHz op tion 1 20 Hz to 100 kHz UIpp = 0.05 0.046 (N ote 14) Table 24. DC Characteristics: Output Jitter Generation (Test Definition G.812) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Te s t d e f i n i t i o n F i l t er u sed U I sp ec U I m e a s u r e m e n t o n A C S 8 510 R ev 2 G.812 for 1.544 MHz 10 Hz to 40 kHz UIpp = 0.05 0.036 (N ote 14) G.812 for 155.52 MHz electrical 500 Hz to 1.3 MHz UIpp = 0.5 0.058 (N ote 15) G.812 for 2.048 MHz electrical 65 kHz to 1.3 MHz U Ip p = 0.075 0.048 (N ote 15) Revision 2.00/September 2003 Semtech Corp. 57 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 25. DC Characteristics: Output Jitter Generation (Test Definition ETS-300-462-3) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Te s t d e f i n i t i o n F i l t er u sed U I sp ec U I m e a s u r e m e n t o n A C S 8 510 R ev 2 ETS-300-462-3 for 2.048 MHz SEC 20 Hz to 100 kHz UIpp = 0.5 0.046 (N ote 14) ETS-300-462-3 for 2.048 MHz SEC (Filter sp ec 49 Hz to 100 kHz) 20 Hz to 100 kHz UIpp = 0.2 0.046 (N ote 14) ETS-300-462-3 for 2.048 MHz SSU 20 Hz to 100 kHz UIpp = 0.05 0.046 (N ote 14) ETS-300-462-3 for 155.52 MHz 500 Hz to 1.3 MHz UIpp = 0.5 0.058 (N ote 15) ETS-300-462-3 for 155.52 MHz 65 kHz to 1.3 MHz UIpp = 0.1 0.048 (N ote 15) Table 26. DC Characteristics: Output Jitter Generation (Test Definition GR-253-CORE) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Te s t d e f i n i t i o n F i l t er u sed U I sp ec U I m e a s u r e m e n t o n A C S 8 510 R ev 2 GR-253-CORE net i/f, 51.84 MHz 100 Hz to 400 kHz UIpp = 1.5 0.022 (N ote 15) GR-253-CORE net i/f, 51.84 MHz (Filter sp ec 20 kHz to 400 kHz) 18 kHz to 400 kHz UIpp = 0.15 0.019 (N ote 15) GR-253-CORE net i/f, 155.52 MHz 500 Hz to 1.3 MHz UIpp = 1.5 0.058 (N ote 15) GR-253-CORE net i/f, 155.52 MHz 65 kHz to 1.3 MHz UIpp = 0.15 0.048 (N ote 15) GR-253-CORE cat II elect i/f, 155.52 MHz UIpp = 0.1 0.057 (N ote 15) 12 kHz to 400 kHz UIrms = 0.01 0.006 (N ote 15) GR-253-CORE cat II elect i/f, 51.84 MHz UIpp = 0.1 0.017 (N ote 15) 12 kHz to 1.3 MHz UIrms = 0.01 0.003 (N ote 15) GR-253-CORE DS1 i/f, 1.544 MHz UIpp = 0.1 0.036 (N ote 14) 10 Hz to 40 kHz UIrms = 0.01 0.0055 (N ote 14) Revision 2.00/September 2003 Semtech Corp. 58 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 27. DC Characteristics: Output Jitter Generation (Test Definition AT&T 62411) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Te s t d e f i n i t i o n F i l t er u sed U I sp ec U I m e a s u r e m e n t o n A C S 8 510 R ev 2 AT&T 62411 for 1.544 MHz (Filter sp ec 10 Hz to 8 kHz) 10 Hz to 40 kHz UIrms = 0.02 0.0055 (N ote 14) AT&T 62411 for 1.544 MHz 10 Hz to 40 kHz UIrms = 0.025 0.0055 (N ote 14) AT&T 62411 for 1.544 MHz 10 Hz to 40 kHz UIrms = 0.025 0.0055 (N ote 14) AT&T 62411 for 1.544 MHz Broadband UIrms = 0.05 0.0055 (N ote 14) Table 28. DC Characteristics: Output Jitter Generation (Test Definition G.742) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Te s t d e f i n i t i o n F i l t er u sed U I sp ec U I m e a s u r e m e n t o n A C S 8 510 R ev 2 G.742 for 2.048 MHz DC to 100 kHz UIpp = 0.25 0.047 (N ote 14) G.742 for 2.048 MHz (Filter spec 18 kHz to 100 kHz) 20 Hz to 100 kHz UIpp = 0.05 0.046 (N ote 14) G.742 for 2.048 MHz 20 Hz to 100 kHz UIpp = 0.05 0.046 (N ote 14) Table 29. DC Characteristics: Output Jitter Generation (Test Definition TR-NWT-000499) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Te s t d e f i n i t i o n F i l t er u sed U I sp ec U I m e a s u r e m e n t o n A C S 8 510 R ev 2 TR-N WT-000499 & G824 for 1.544 MHz 10 Hz to 40 kHz UIpp = 5.0 0.036 (N ote 14) TR-N WT-000499 & G824 for 1.544 MHz (Filter spec 8 kHz to 40 kHz) 10 Hz to 40 kHz UIpp = 0.1 0.036 (N ote 14) Revision 2.00/September 2003 Semtech Corp. 59 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 30. DC Characteristics: Output Jitter Generation (Test Definition GR-1244-CORE) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Te s t d e f i n i t i o n F i l t er u sed U I sp ec U I m e a s u r e m e n t o n A C S 8 510 R ev 2 GR-1244-CORE for 1.544 MHz >10 Hz UIpp = 0.05 0.036 (N ote 14) Notes for Tables 23 - 30 Note 1. Filter used is that defined by test definition unless otherwise stated Note 2. 5 Hz bandwidth, 19.44 MHz direct lock Note 3. 5 Hz bandwidth, 8 kHz lock Note 4. 20 Hz bandwidth, 19.44 MHz direct lock Note 5. 20 Hz bandwidth, 8 kHz lock Note 6. 10 Hz bandwidth, 19.44 MHz direct lock Note 7. 10 Hz bandwidth, 8 kHz lock Note 8. 2.5 Hz bandwidth, 19.44 MHz direct lock Note 9. 2.5 Hz bandwidth, 8 kHz lock Note 10. 1.2 Hz bandwidth, 19.44 MHz direct lock Note 11. 1.2 Hz bandwidth, 8 kHz lock Note 12. 0.6 Hz bandwidth, 19.44 MHz direct lock Note 13. 0.6 Hz bandwidth, 8 kHz lock Note 14. 5 Hz bandwidth, 8 kHz lock, 2.048 MHz input Note 15. 5 Hz bandwidth, 8 kHz lock, 19.44 MHz input Revision 2.00/September 2003 Semtech Corp. 60 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 17. JTAG Timing t CYC TCK t SU R t HT TM S TDI t DO D TDO Table 31. JTAG Timing (for use with Figure 17) PA R A M E T E R SYMB OL MIN T YP MA X U N ITS Cycle time tCYC 50 - - ns TMS/TDI to TCK rising edge time tSUR 3 - - ns TCK rising to TMS/TDI hold time tHT 23 - - ns TCK falling to TDO valid tDOD - - 5 ns Revision 2.00/September 2003 Semtech Corp. 61 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 18. Input/Output Timing Typical Delay Input/Output 8 kHz input Output ± 1.5 ns Typical Phase Alignment 8 kHz output 8 kHz 6.48 MHz input 2 kHz < ±1 ns +6.5 to +8.5 ns 6.48 MHz output 19.44 MHz input +5.5 to +7.5 ns T1 +3.5 to +5.5 ns (Multiples have the same offset) E1 +3.5 to +5.5 ns (Multiples have the same offset) 19.44 MHz output 25.92 MHz input 6.48 MHz +3.0 to +5.0 ns 19.44 MHz +2.5 to +4.5 ns 25.92 MHz +3.0 to +5.0 ns 38.88 MHz +3.0 to +4.5 ns 51.84 MHz +6.0 to +8.0 ns (Additional delay for this output) 77.76 MHz +2.0 to +4.0 ns +6.5 to +8.5 ns 25.92 MHz output 38.88 MHz input +4.0 to +6.0 ns 38.88 MHz output 51.84 MHz input +6.0 to +8.0 ns 51.84 MHz output 77.76 MHz input +5.5 to +7.5 ns 155.52 MHz < ± 1 ns 311.04 MHz < ± 0.5 ns 77.76 MHz output Revision 2.00/September 2003 Semtech Corp. 62 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Microprocessor Interface Timing Motorola Mode In MOTOROLA mode, the device is configured to interface with a microprocessor using a 680x0 type bus. The following figures show the timing diagrams of write and read accesses for this mode. Figure 19. Read Access Timing in MOTOROLA Mode t pw1 CSB t su2 WRB t h2 X X t h1 t su1 A X address X t d3 t d1 AD Z t d2 RDY (DTACK) Z data t pw2 t h3 t d4 Z Z Table 32. Read Access Timing in MOTOROLA Mode (for use with Figure 19) S y m b ol tsu1 tsu2 P ar am et er Setup A valid to CSBfalling edge Setup WRB valid to CSBfalling edge MIN T YP MA X 0 ns - - 0 ns - - td 1 Delay CSBfalling edge to AD valid - - 177 ns td 2 Delay CSBfalling edge to DTACKrising edge - - 13 ns td 3 Delay CSBrising edge to AD high-Z - - 0 ns td 4 Delay CSBrising edge to RDY high-Z - - 7 ns tp w 1 CSB low time 485 ns(1) - - tp w 2 RDY high time 310 ns - 472 ns th 1 Hold A valid after CSBrising edge 0 ns - - th 2 Hold WRB high after CSBrising edge 0 ns - - th 3 Hold CSB low after RDYfalling edge 0 ns - - tp Time between consecutive accesses (CSBrising edge to CSBfalling edge) 320 ns - - Note 1: Timing with RDY. If RDY not used, tpw1 becomes 178 ns. Revision 2.00/September 2003 Semtech Corp. 63 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 20. Write Access Timing in MOTOROLA Mode t pw1 CSB t su2 WRB t h2 X X t h1 t su1 A X address X t h4 t su3 AD X data t d2 RDY (DTACK) t pw2 X t h3 t d4 Z Z Table 33. Write Access Timing in MOTOROLA Mode (for use with Figure 20) S y m b ol tsu1 P ar am et er Setup A valid to CSBfalling edge MIN T YP MA X 0 ns - - tsu2 Setup WRB valid to CSBfalling edge 0 ns - - tsu3 Setup AD valid before CSBrising edge 3 ns - - td 2 Delay CSBfalling edge to RDYrising edge - - 13 ns td 4 Delay CSBrising edge to RDY high-Z - - 7 ns tp w 1 CSB low time 485 ns(1) - - tp w 2 RDY high time 310 ns - 472 ns th 1 Hold A valid after CSBrising edge 3 ns - - th 2 Hold WRB low after CSBrising edge 0 ns - - th 3 Hold CSB low after RDYfalling edge 0 ns - - th 4 Hold AD valid after CSBrising edge 4 ns tp Time between consecutive accesses (CSBrising edge to CSBfalling edge) - - 320 ns Note 1: Timing with RDY. If RDY not used, tpw1 becomes 178 ns. Revision 2.00/September 2003 Semtech Corp. 64 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Intel Mode In INTEL mode, the device is configured to interface with a microprocessor using a 80x86 type bus. The following figures show the timing diagrams of write and read accesses for this mode. Figure 21. Read Access Timing in INTEL Mode CSB WRB t su2 t pw 1 t h2 RDB t su1 t h1 A a dd re ss t d1 AD Z d ata t d2 RDY t d4 Z t d3 t pw 2 t h3 t d5 Z Z Table 34. Read Access Timing in INTEL Mode (for use with Figure 21) S y m b ol tsu1 tsu2 P ar am et er Setup A valid to CSBfalling edge Setup CSBfalling edge to RDBfalling edge MIN T YP MA X 0 ns - - 0 ns - - td 1 Delay RDBfalling edge to AD valid - - 177 ns td 2 Delay CSBfalling edge to RDY active - - 13 ns td 3 Delay RDBfalling edge to RDYfalling edge - - 14 ns td 4 Delay RDBrising edge to AD high-Z - - 10 ns td 5 Delay CSBrising edge to RDY high-Z tp w 1 RDB low time 486 ns(1) - - tp w 2 RDY low time 310 ns - 472 ns th 1 Hold A valid after RDBrising edge 0 ns - - th 2 Hold CSB low after RDBrising edge 0 ns - - th 3 Hold RDB low after RDYrising edge 0 ns - - tp Time between consecutive accesses (RDBrising edge to RDBfalling edge , or RDBrising edge to WRBfalling edge) 320 ns - - 9 ns Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns. Revision 2.00/September 2003 Semtech Corp. 65 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 22. Write Access Timing in INTEL Mode CSB t su2 t pw1 t h2 WRB RDB t su1 t h1 A address t su3 AD data t d2 RDY t h4 t d3 t pw2 t h3 t d5 Z Z Table 35. Write Access Timing in INTEL Mode (for use with Figure 22) S y m b ol tsu1 tsu2 P ar am et er Setup A valid to CSBfalling edge Setup CSBfalling edge to WRBfalling edge MIN T YP MA X 0 ns - - 0 ns - - tsu3 Setup AD valid to WRBrising edge 3 ns - - td 2 Delay CSBfalling edge to RDY active - - 13 ns td 3 Delay WRBfalling edge to RDYfalling edge - - 14 ns td 5 Delay CSBrising edge to RDY high-Z tp w 1 WRB low time 486 ns(1) - - tp w 2 RDY low time 310 ns - 472 ns th 1 Hold A valid after WRBrising edge 170 ns(2) - - th 2 Hold CSB low after WRBrising edge 0 ns - - th 3 Hold WRB low after RDYrising edge 0 ns - - th 4 Hold AD valid after WRBrising edge 4 ns tp Time between consecutive accesses (WRBrising edge to WRBfalling edge , or WRBrising edge to RDBfalling edge) - - 9 ns 320 ns Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns. Note 2: Timing if th2 is greater than 170 ns, otherwise 5 ns after CSB rising edge. Revision 2.00/September 2003 Semtech Corp. 66 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Multiplexed Mode In MULTIPLEXED mode, the device is configured to interface with a microprocessor using a multiplexed address/ data bus. The following figures show the timing diagrams of write and read accesses for this mode. Figure 23. Read Access Timing in MULTIPLEXED Mode t t pw 3 p1 ALE t su1 t h1 CSB t su2 W RB t t pw 1 h2 RDB t AD X a d d re s s t RDY t d1 d4 X d a ta t d2 d3 t pw 2 t t h3 d5 Z Z Table 36. Read Access Timing in MULTIPLEXED Mode (for use with Figure 23) S y m b ol tsu1 P ar am et er Setup A D address valid to A LEfalling edge MIN T YP MA X 2 ns - - tsu2 Setup CSBfalling edge to RDBfalling edge 0 ns - - td 1 Delay RDBfalling edge to A D data valid - - 177 ns td 2 Delay CSBfalling edge to RDY active - - 13 ns td 3 Delay RDBfalling edge to RDYfalling edge - - 15 ns td 4 Delay RDBrising edge to A D data high-Z - - 9 ns td 5 Delay CSBrising edge to RDY high-Z - - 10 ns tp w 1 RDB low time - - tp w 2 RDY low time 310 ns - 472 ns tp w 3 A LE high time 2 ns th 1 Hold A D address valid after A LEfalling edge 3 ns - - th 2 Hold CSB low after RDBrising edge 0 ns - - th 3 Hold RDB low after RDYrising edge 0 ns - - tp 1 Time b etween A LEfalling edge and RDBfalling edge 0 ns - - tp 2 Time b etween consecutive accesses (RDBrising edge to A LErising edge) 320 ns - - 487 ns (1) Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns. Revision 2.00/September 2003 Semtech Corp. 67 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 24. Write Access Timing in MULTIPLEXED Mode t t pw 3 p1 ALE t t su1 h1 CSB t t su2 t pw 1 h2 W RB RDB t AD a d d re s s RDY h4 d a ta X t t su3 t d2 d3 t X pw 2 t h3 t d5 Z Z Table 37. Write Access Timing in MULTIPLEXED Mode (for use with Figure 24) S y m b ol tsu1 P ar am et er Setup AD address valid to ALEfalling edge MIN T YP MA X 2 ns - - tsu2 Setup CSBfalling edge to WRBfalling edge 0 ns - - tsu3 Setup AD data valid to WRBrising edge 3 ns - - td 2 Delay CSBfalling edge to RDY active - - 13 ns td 3 Delay WRBfalling edge to RDYfalling edge - - 15 ns td 5 Delay CSBrising edge to RDY high-Z tp w 1 WRB low time 487 ns(1) - - tp w 2 RDY low time 310 ns - 472 ns tp w 3 ALE high time 2 ns - - th 1 Hold AD address valid after ALEfalling edge 3 ns - - th 2 Hold CSB low after WRBrising edge 0 ns - - th 3 Hold WRB low after RDYrising edge 0 ns - - th 4 AD data hold valid after WRBrising edge 4 ns tp 1 Time between ALEfalling edge and WRBfalling edge 0 ns - - tp 2 Time between consecutive accesses (WRBrising edge to ALErising edge) 320 ns - - 9 ns Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns. Revision 2.00/September 2003 Semtech Corp. 68 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Serial Mode In Serial mode, the device is configured to interface with a serial microprocessor bus.The combined minimum High and Low times for SCLK define the maximum clock rate. For Write access this is 2.77 MHz (360 ns). For Read access the maximum SCLK rate is slightly slower and is affected by the setting of CLKE, being either 2.0 MHz (500 ns) or 1 MHz (1 us). This mismatch in rates is caused by the sampling technique used to detect the end of the address field in Read mode. It takes up to 3 cycles of an internal 6.40 MHz clock to start the Read process following receipt of the final address bit. This is 468 ns. The Read data is then decoded and clocked out onto SDO directly using SCLK. With CLKE=1, the falling edge of SCLK is used to clock out the SDO. With CLKE=0, the rising edge of SCLK is used to clock out the SDO. A minimum period of 500 ns (468 capture plus 32 decode) is required between the final address bit and clocking it out onto SDO. This means that to guarantee the correct operation of the Serial interface, with CLKE=0, SCLK has a maximum clock rate of 2 MHz. With CLKE=1, SCLK has a maximum clock rate of 1 MHz. SCLK is not required to run between accesses (i.e., when CSB = 1). The following Figures show the timing diagrams for Write and Read access for this mode. Figure 25. Read Access Timing in Serial Mode CLKE = 0; SDO data is clocked out on the rising edge of SCLK CSB tsu2 tpw2 th2 SCLK th1 tsu1 _ SDI R/W tpw1 A0 A1 A2 A3 A4 A5 A6 td1 SDO Output not driven, pulled low by internal resistor td2 D0 D1 D2 D3 D4 D5 D6 D7 CLKE = 1; SDO data is clocked out on the falling edge of SCLK CSB th2 SCLK _ SDI R/W A0 A1 A2 A3 A4 A5 A6 td1 SDO Output not driven, pulled low by internal resistor td2 D0 D1 D2 D3 D4 D5 D6 D7 F8525D_013ReadAccSerial_01 Revision 2.00/September 2003 Semtech Corp. 69 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 38. Read Access Timing in SERIAL Mode (for use with Figure 25) S y m b ol P ar am et er Setup SDI valid to SCLKrising edge tsu1 Setup CSBfalling edge to SCLKrising edge tsu2 MIN T YP MA X 0 ns - - 160 ns - - td 1 Delay SCLKrising edge (SCLKfalling edge for CLKE = 1) to SDO valid - - 17 ns td 2 Delay CSBrising edge to SDO high-Z - - 10 ns tp w 1 SCLK low time CLKE = 0 CLKE = 1 250ns 500ns - - tp w 2 SCLK high time CLKE = 0 CLKE = 1 250ns 500ns - - th 1 Hold SDI valid after SCLKrising edge 170 ns - - th 2 Hold CSB low after SCLKrising edge, for CLKE = 0 Hold CSB low after SCLKfalling edge, for CLKE = 1 5 ns - - tp Time b etween consecutive accesses (CSBrising edge to CSBfalling edge) 160 ns - - Figure 26. Write Access Timing in SERIAL Mode CSB tsu2 tpw2 th2 ALE=SCLK th1 tsu1 _ A(0)=SDI AD(0)=SDO R/W tpw1 A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 Output not driven, pulled low by internal resistor F8110D_014WriteAccSerial_02 Table 39. Write Access Timing in SERIAL Mode (for use with Figure 26) S y m b ol P ar am et er MIN T YP MA X 0 ns - - tsu1 Setup SDI valid to SCLKrising edge tsu2 Setup CSBfalling edge to SCLKrising edge 160 ns - - tp w 1 SCLK low time 180 ns - - tp w 2 SCLK high time 180 ns - - th 1 Hold SDI valid after SCLKrising edge 170 ns - - th 2 Hold CSB low after SCLKrising edge 5 ns - - tp Time between consecutive accesses (CSBrising edge to CSBfalling edge) 160 ns - - Revision 2.00/September 2003 Semtech Corp. 70 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS EPROM Mode In EPROM mode, the ACS8510 takes control of the bus as Master, and reads the device set-up from an AMD AM27C64 type EPROM at lowest speed (250ns), after device start-up (system reset). The EPROM access state machine in the up interface sequences the accesses. Further details can be found in the AMD AM27C64 data sheet. Figure 27. Access Timing in EPROM Mode CSB (=OEB) A address t acc AD Z Z data Table 40. Access Timing in EPROM Mode (for use with Figure 27) S y m b ol tacc P ar am et er Delay CSBfalling edge or A change to AD valid Revision 2.00/September 2003 Semtech Corp. 71 MIN T YP MA X - - 920 ns www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Package Information Figure 28. LQFP Package D 2 D1 1 3 AN2 AN3 1 Section A-A R1 S E 2 R2 B AN1 E1 1 A A B 3 AN4 L 4 L1 5 1 2 3 b A Section B-B 7 e A2 7 c c1 7 Seating plane A1 6 b1 7 b 8 Notes 1 The top package body may be smaller than the bottom package body by as much as 0.15 mm. 2 To be determined at seating plane. 3 Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 4 Details of pin 1 identifier are optional but will be located within the zone indicated. 5 Exact shape of corners can vary. 6 A1 is defined as the distance from the seating plane to the lowest point of the package body. 7 These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 8 Shows plating. Revision 2.00/September 2003 Semtech Corp. 72 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 41. 100 Pin LQFP Package Dimension Data (for use with Figure 28) 10 0 L Q F P P ack ag e Di m en si on s i n mm D/E D1/E 1 Mi n N om Max 16.00 14.00 A A1 A1 A2 A2 1.40 0.05 1.35 1.50 0.10 1.40 1.60 0.15 1.45 e 0.50 AN1 AN2 AN3 AN4 R1 R1 R2 R2 L 11° 11° 0° 0° 0.08 0.08 0.45 12° 12° - 3.5° - - 0.60 13° 13° - 7° - 0.20 0.75 L1 L1 1.00 (ref) S b b1 b1 c c1 c1 0.20 0.17 0.17 0.09 0.09 - 0.22 0.20 - - - 0.27 0.23 0.20 0.16 Thermal Conditions The device is rated for full temperature range when this package is used with a 4 layer or more PCB. Copper coverage must exceed 50%. All pins must be soldered to the PCB. Maximum operating temperature must be reduced when the device is used with a PCB with less than these requirements. Figure 29. Typical 100 Pin LQFP Footprint 18.3 mm 17.0 mm (1) 14.6 mm 1.85 mm Pitch 0.5 mm Width 0.3 mm Notes (1) Solderable to this limit. Square package - dimensions apply in both X and Y directions. Typical example. The user is reponsible for ensuring compatibility with PCB manufacturing process, etc. Revision 2.00/September 2003 Semtech Corp. 73 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Application Information Figure 30. Simplified Application Schematic Revision 2.00/September 2003 Semtech Corp. 74 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Revision History Table 42. Changes from Revision 1.06 to 2.00 September 2003 Item 1 Section Non-Revertive Mode Page 36-37 Description Updated description of Non-Revertive Mode Operation Revision 2.00/September 2003 Semtech Corp. 75 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Ordering Information PA R T N U M B E R DE S CR I P T I O N ACS8510 Rev2.1 SON ET/SDH Synchronisation, 100 p in LQFP Disclaimers Life support - This product is not designed or intended for use in life suport equipment, devices or systems, or other critical applications. This product is not authorized or warranted by Semtech Corporation for such use. Right to change - Semtech Corporation reserves the right to make changes, without notice, to this product. Customers are advised to obtain the latest version of the relevant information before placing orders. Compliance to relevant standards - Operation of this device is subject to the user’s implementation, and design practices. The user is responsible to ensure equipment using this device is compliant to any relevant standards. For additional information, contact the following: Semtech Corporation Advanced Communications Products E-Mail: sales@semtech.com acsupport@semtech.com Internet: http://www.semtech.com USA: Mailing Address: P.O. Box 6097, Camarillo, CA 93011-6097 Street Address: 200 Flynn Road, Camarillo, CA 93012-8790 Tel: +1 805 498 2111, Fax: +1 805 498 3804 FAR EAST: 11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, Taiwan, R.O.C. Tel: +886 2 2748 3380, Fax: +886 2 2748 3390 EUROPE: Units 2 & 3 Park Court, Premier Way, Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN, UK Tel: +44 1794 527 600, Fax: +44 1794 527 601 ISO9001 CERTIFIED Revision 2.00/September 2003 Semtech Corp. 76 www.semtech.com