ACS8522 SETS LITE
Synchronous Equipment Timing Source for
Stratum 3/4E/4 and SMC Systems
ADVANCED COMMUNICATIONS
Description
FINAL
Features
DATASHEET
The ACS8522 is a highly integrated, single-chip solution
for the Synchronous Equipment Timing Source (SETS)
function in a SONET or SDH Network Element. The device
generates SONET or SDH Equipment Clocks (SEC) and
Frame Synchronization clocks. The ACS8522 is fully
compliant with the required international specifications
and standards.
Suitable for Stratum 3, 4E, 4 and SONET Minimum
Clock (SMC) or SONET/SDH Equipment Clock (SEC)
applications (to Telcordia 1244-CORE[19] Stratum 3
and GR-253[17], and ITU-T G.813[11] Options Ι and ΙΙ
specifications)
The device supports Free-run, Locked and Holdover
modes, with mode selection controlled either
automatically by an internal state machine or forced by
register configuration.
Simultaneously generates four output clocks, plus two
Sync pulse outputs
The ACS8522 accepts up to four independent input SEC
reference clock sources from Recovered Line Clock, PDH
network, and Node Synchronization. The ACS8522
generates independent SEC and BITS clocks, an 8 kHz
Frame Synchronization clock and a 2 kHz Multi-Frame
Synchronization clock, both with programmable pulse
width and polarity.
The ACS8522 includes a Serial Port, which can be SPI
compatible, providing access to the configuration and
status registers for device setup.
Accepts four individual input reference clocks, all with
robust input clock source quality monitoring
Absolute Holdover accuracy better than 3 x 10-10
(manual), 7.5 x 10-14 (instantaneous); Holdover
stability defined by choice of external XO
Programmable PLL bandwidth, for wander and jitter
tracking/attenuation, 0.1 Hz to 70 Hz in 10 steps
Automatic hit-less source switchover on loss of input
Serial SPI compatible interface
Output phase adjustment in 6 ps steps up to ±200 ns
IEEE 1149.1[5] JTAG Boundary Scan
The ACS8522 supports IEEE 1149.1[5] JTAG boundary
scan.
Available in LQFP 64-pin package
The User can choose between OCXO or TCXO to define the
Stratum and/or Holdover performance required.
Block Diagram
Single 3.3 V operation. 5 V tolerant
Lead (Pb)-free version available (ACS8522T), RoHS
and WEEE compliant.
Figure 1 Block Diagram of the ACS8522 SETS LITE
T4 DPLL/Freq. Synthesis
Inputs: 4 x TTL
Programmable;
2 kHz
4 kHz
N x 8 kHz
1.544/2.048 MHz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
TCK
TDI
TMS
TRST
TDO
T4 DPLL
Selector
Optional
Divider, 1/n
n = 1 to 214
PFD
Digital
Loop
Filter
DTO
T4 Output
APLL
Frequency
Dividers
Output
Ports
O1
to
O4
Input
Port
Monitors
and
Selection
Control
T0 Output
APLL
T0 DPLL/Freq. Synthesis
4 x SEC
T0 DPLL
Selector
IEEE
1149.1
JTAG
Chip
Clock
Generator
Optional
Divider, 1/n
n = 1 to 214
PFD
Priority Register Set
Table
Digital
Loop
Filter
Serial
Port
OCXO or
TCXO
Frequency
Dividers
FrSync
&
MFrSync
Output O1: PECL/LVDS
Outputs O2 - 04: TTL
Programmable;
E1/DS1 (2.048/
1.544 MHz)
and frequency
multiples:
1.5 x, 2 x, 3 x
4 x, 6 x, 12 x
16 x and 24 x
E3/DS3
2 kHz
8 kHz
and OC-N* rates
8 kHz
(FrSync)
2 kHz
(MFrSync)
DTO
T0 Feedback
APLL
OC-N* rates =
OC-1 51.84 MHz
OC-3 155.52 MHz
and derivatives:
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
311.04 MHz
F8522P_001BLOCKDIA_04
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Table of Contents
ADVANCED COMMUNICATIONS
Table of Contents
FINAL
Section
ACS8522 SETS LITE
DATASHEET
Page
Description ................................................................................................................................................................................................. 1
Block Diagram............................................................................................................................................................................................ 1
Features ..................................................................................................................................................................................................... 1
Table of Contents ...................................................................................................................................................................................... 2
Pin Diagram ............................................................................................................................................................................................... 4
Pin Description........................................................................................................................................................................................... 5
Introduction................................................................................................................................................................................................ 7
General Description................................................................................................................................................................................... 7
Overview .............................................................................................................................................................................................7
Input Reference Clock Ports .............................................................................................................................................................9
Locking Frequency Modes ....................................................................................................................................................... 9
Clock Quality Monitoring................................................................................................................................................................. 10
Activity Monitoring ................................................................................................................................................................. 11
Frequency Monitoring ........................................................................................................................................................... 12
Selection of Input Reference Clock Source................................................................................................................................... 12
Forced Control Selection....................................................................................................................................................... 13
Automatic Control Selection ................................................................................................................................................. 13
Ultra Fast Switching .............................................................................................................................................................. 13
Fast External Switching Mode-SRCSW pin .......................................................................................................................... 13
Output Clock Phase Continuity on Source Switchover ....................................................................................................... 14
Modes of Operation ........................................................................................................................................................................ 14
Free-run Mode ....................................................................................................................................................................... 14
Pre-locked Mode ................................................................................................................................................................... 14
Locked Mode ......................................................................................................................................................................... 14
Lost-phase Mode................................................................................................................................................................... 14
Holdover Mode ...................................................................................................................................................................... 15
Pre-locked2 Mode ................................................................................................................................................................. 17
DPLL Architecture and Configuration ............................................................................................................................................ 17
TO DPLL Main Features ........................................................................................................................................................ 18
T4 DPLL Main Features ........................................................................................................................................................ 18
TO DPLL Automatic Bandwidth Controls.............................................................................................................................. 18
Phase Detectors .................................................................................................................................................................... 18
Phase Lock/Loss Detection.................................................................................................................................................. 19
Damping Factor Programmability......................................................................................................................................... 19
Local Oscillator Clock ............................................................................................................................................................ 20
Output Wander ...................................................................................................................................................................... 20
Jitter and Wander Transfer ................................................................................................................................................... 23
Phase Build-out ..................................................................................................................................................................... 23
Input-to-Output Phase Adjustment....................................................................................................................................... 24
Input Wander and Jitter Tolerance....................................................................................................................................... 24
Using the DPLLs for Accurate Frequency and Phase Reporting ........................................................................................ 26
MFrSync and FrSync Alignment-SYNC2K............................................................................................................................. 27
Output Clock Ports .......................................................................................................................................................................... 27
PECL/LVDS Output Port Selection ....................................................................................................................................... 27
Output Frequency Selection and Configuration .................................................................................................................. 28
Power-On Reset............................................................................................................................................................................... 38
Serial Interface................................................................................................................................................................................ 38
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ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Section
Page
Register Map........................................................................................................................................................................................... 41
Register Organization ..................................................................................................................................................................... 41
Register Access ..................................................................................................................................................................... 41
Interrupt Enable and Clear ................................................................................................................................................... 41
Defaults.................................................................................................................................................................................. 41
Register Descriptions ............................................................................................................................................................................. 45
Electrical Specifications ....................................................................................................................................................................... 105
JTAG ............................................................................................................................................................................................... 105
Over-voltage Protection ................................................................................................................................................................ 105
ESD Protection .............................................................................................................................................................................. 105
Latchup Protection........................................................................................................................................................................ 105
Maximum Ratings ......................................................................................................................................................................... 106
Operating Conditions .................................................................................................................................................................... 106
DC Characteristics ........................................................................................................................................................................ 106
Jitter Performance ........................................................................................................................................................................ 109
Input/Output Timing ..................................................................................................................................................................... 111
Package Information ............................................................................................................................................................................ 112
Thermal Conditions....................................................................................................................................................................... 113
Application Information ........................................................................................................................................................................ 114
References ............................................................................................................................................................................................ 115
Abbreviations ........................................................................................................................................................................................ 115
Trademark Acknowledgements ........................................................................................................................................................... 116
Revision Status/History ....................................................................................................................................................................... 117
Ordering Information ............................................................................................................................................................................ 118
Disclaimers.................................................................................................................................................................................... 118
Contacts......................................................................................................................................................................................... 118
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ACS8522 SETS LITE
ADVANCED COMMUNICATIONS
Pin Diagram
FINAL
DATASHEET
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
SONSDHB
IC11
IC10
IC9
IC8
O4
AGND4
VA3+
O3
O2
VDD7
DGND6
SDO
TDI
TDO
TCK
Figure 2 ACS8522 Pin Diagram Synchronous Equipment Timing Source for Stratum 3/4E/4 and SMC Systems
AGND1
IC1
AGND2
VA1+
INTREQ
REFCLK
DGND1
VD1+
VD2+
DGND2
DGND3
VD3+
SRCSW
VA2+
AGND3
IC2
ACS8522
SETS LITE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PORB
SCLK
VDD6
VDD5
CSB
SDI
CLKE
TMS
DGND5
VDD4
VDD3
TRST
VDD2
IC7
SEC4
SEC3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
FrSync
MFrSync
O1POS
O1NEG
GND_DIFF
VDD_DIFF
IC3
IC4
IC5
IC6
VDD5V
SYNC2K
SEC1
SEC2
DGND4
VDD1
1
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
16
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ACS8522 SETS LITE
ADVANCED COMMUNICATIONS
Pin Description
FINAL
DATASHEET
Table 1 Power Pins
Pin Number
Symbol
I/O
Type
Description
8, 9,
12
VD1+, VD2+,
VD3+
P
-
Supply Voltage: Digital supply to gates in analog section, +3.3 Volts
±10%.
22
VDD_DIFF
P
-
Supply Voltage: Digital supply for differential output pins 19 and 20,
+3.3 Volts ±10%.
27
VDD5V
P
-
VDD5V: Digital supply for +5 Volts tolerance to input pins. Connect to
+5 Volts (±10%) for clamping to +5 Volts. Connect to VDD for clamping
to +3.3 Volts. Leave floating for no clamping. Input pins tolerant up to
+5.5 Volts.
32, 36,
38, 39,
45, 46,
54
VDD1, VDD2,
VDD3, VDD4,
VDD5, VDD6,
VDD7
P
-
Supply Voltage: Digital supply to logic, +3.3 Volts ±10%.
4
VA1+
P
-
Supply Voltage: Analog supply to clock multiplying PLL,
+3.3 Volts ±10%.
14, 57
VA2+, VA3+
P
-
Supply Voltage: Analog supply to output PLLs APLL2 and APLL1,
+3.3 Volts ±10%.
15, 58
AGND3, AGND4
-
Supply Ground: Analog ground for output PLLs APLL2 and APLL1.
7, 10,
11
DGND1, DGND2,
DGND3
P
-
Supply Ground: Digital ground for components in PLLs.
31, 40,
53
DGND4, DGND5,
DGND6
P
-
Supply Ground: Digital ground for logic.
21
GND_DIFF
P
-
Supply Ground: Digital ground for differential output pins 19 and 20.
1, 3
AGND1, AGND2
P
-
Supply Ground: Analog grounds.
Note...I = Input, O = Output, P = Power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor.
Table 2 Internally Connected Pins
Pin Number
Symbol
I/O
Type
2, 16, 23, 24,
25, 26, 35,
60, 61, 62,
63
IC1, IC2, IC3, IC4,
IC5, IC6, IC7,
IC8, IC9, IC10,
IC11
-
-
I/O
Type
Description
Internally Connected: Leave to Float.
Table 3 Other Pins
Pin Number
Symbol
5
INTREQ
O
TTL/CMOS
6
REFCLK
I
TTL
Revision 5/November 2006 © Semtech Corp.
Description
Interrupt Request: Active High/Low software Interrupt output.
Reference Clock: 12.800 MHz (refer to section headed Local Oscillator
Clock).
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ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Table 3 Other Pins (cont...)
Pin Number
Symbol
I/O
Type
Description
13
SRCSW
I
TTLD
17
FrSync
O
TTL/CMOS
Output Reference: 8 kHz Frame Sync output.
18
MFrSync
O
TTL/CMOS
Output Reference: 2 kHz Multi-Frame Sync output.
19, 20
O1POS, O1NEG
O
LVDS/PECL
Output Reference: Programmable, default 38.88 MHz, LVDS.
28
SYNC2K
I
TTLD
Multi-Frame Sync 2kHz input.
29
SEC1
I
TTLD
Input Reference: Programmable, default 8 kHz.
30
SEC2
I
TTLD
Input Reference: Programmable, default 8 kHz.
33
SEC3
I
TTLD
Input Reference: Programmable, default 19.44 kHz.
34
SEC4
I
TTLD
Input Reference: Programmable, default 19.44 kHz.
37
TRST
I
TTLD
JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary Scan
mode. TRST = 0 for Boundary Scan stand-by mode, still allowing correct
device operation. If not used connect to GND or leave floating.
41
TMS
I
TTLD
JTAG Test Mode Select: Boundary Scan enable. Sampled on rising edge
of TCK. If not used connect to VDD or leave floating.
42
CLKE
I
TTLD
SCLK Edge Select: SCLK active edge select, CLKE = 1, selects falling
edge of SCLK to be active.
43
SDI
I
TTLD
Microprocessor Interface Address: Serial Data Input.
44
CSB
I
TTLU
Chip Select (Active Low): This pin is asserted Low by the microprocessor
to enable the microprocessor interface.
47
SCLK
I
TTLD
Serial Data Clock. When this pin goes High data is latched from SDI pin.
48
PORB
I
TTLU
Power-On Reset: Master reset. If PORB is forced Low, all internal states
are reset back to default values.
49
TCK
I
TTLD
JTAG Clock: Boundary Scan clock input.
50
TDO
O
TTL/CMOS
51
TDI
I
TTLD
JTAG Input: Serial test data Input. Sampled on rising edge of TCK.
52
SDO
O
TTLD
Interface Address: SPI compatible Serial Data Output.
55
O2
O
TTL/CMOS
Output Reference 2: Programmable, default 38.88 MHz.
56
O3
O
TTL/CMOS
Output Reference 3: Programmable, default 19.44 MHz.
59
O4
O
TTL/CMOS
Output Reference 4: Programmable, default 1.544/2.048 MHz (BITS).
64
SONSDHB
I
TTLD
SONET or SDH Frequency Select: Sets the initial power-up state (or state
after a PORB) of the SONET/SDH frequency selection registers, Reg. 34
Bit 2, and Reg. 38 Bits 5 and 6. When set Low, SDH rates are selected
(2.048 MHz etc.), and when set High, SONET rates are selected (1.544
MHz etc.). The register states can be changed after power-up by
software.
Revision 5/November 2006 © Semtech Corp.
Source Switching: Force Fast Source Switching on SEC1 and SEC2.
JTAG Output: Serial test data output. Updated on falling edge of TCK.
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ADVANCED COMMUNICATIONS
Introduction
FINAL
The ACS8522 is a highly integrated, single-chip solution
for the SETS function in a SONET/SDH Network Element,
for the generation of SEC and Frame/MultiFrame sync
pulses. Digital Phase Locked Loop (DPLL) and direct
digital synthesis methods are used in the device so that
the overall PLL characteristics are very stable and
consistent compared to traditional analog PLLs.
In Free-run mode, the ACS8522 generates a stable, lownoise clock signal at a frequency to the same accuracy as
the external oscillator, or it can be made more accurate
via software calibration to within 0.02 ppm. In Locked
mode, the ACS8522 selects the most appropriate input
reference source and generates a stable, low-noise clock
signal locked to the selected reference. In Holdover mode,
the ACS8522 generates a stable, low-noise clock signal,
adjusted to match the last known good frequency of the
last selected reference source. A high level of phase and
frequency accuracy is made possible by an internal
resolution of up to 54 bits and internal Holdover accuracy
of 0.0012 ppb (1.2 x 10-12). In all modes, the frequency
accuracy, jitter and drift performance of the clock meet
the requirements of ITU G.736[7], G.742[8], G783[9],
G.812[10], G.813[11], G.823[13],G.824[14] and Telcordia
GR-253-CORE[17] and GR-1244-CORE[19].
The ACS8522 supports all three types of reference clock
source: recovered line clock, PDH network
synchronization timing and node synchronization. The
ACS8522 generates independent T0 and T4 clocks, an
8 kHz Frame Synchronization clock and a 2 kHz
Multi-Frame Synchronization clock.
One key architectural advantage that the ACS8522 has
over traditional solutions is in the use of DPLL technology
for precise and repeatable performance over temperature
or voltage variations and between parts. The overall PLL
bandwidth, loop damping, pull-in range and frequency
accuracy are all determined by digital parameters that
provide a consistent level of performance. An Analog PLL
(APLL) takes the signal from the DPLL output and provides
a lower jitter output. The APLL bandwidth is set four orders
of magnitude higher than the DPLL bandwidth. This
ensures that the overall system performance still
maintains the advantage of consistent behavior provided
by the digital approach.
The DPLLs are clocked by the external Oscillator module
(TCXO or OCXO) so that the Free-run or Holdover
frequency stability is only determined by the stability of
the external oscillator module. This second key advantage
Revision 5/November 2006 © Semtech Corp.
DATASHEET
confines all temperature critical components to one well
defined and pre-calibrated module, whose performance
can be chosen to match the application; for example an
TCXO for Stratum 3 applications.
All performance parameters of the DPLLs are
programmable without the need to understand detailed
PLL equations. Bandwidth, damping factor and lock range
can all be set directly, for example. The PLL bandwidth
can be set over a wide range, 0.1 Hz to 70 Hz in 18 steps,
to cover all SONET/SDH clock synchronization
applications.
The ACS8522 includes a serial port, providing access to
the configuration and status registers for device setup
and monitoring.
General Description
Overview
The following description refers to the Block Diagram
(Figure 1 on page 1).
The ACS8522 SETS device has four SEC clock inputs
(SEC1 to SEC4), and generates four output clocks on
outputs O1 to O4. The device offers a total of 55 possible
output frequencies. There are two independent paths
through the device: T0 path comprising T0 DPLL and T0
Output and Feedback APLLs, and T4 path comprising T4
DPLL and T4 Output APLL.
The T0 path is a high quality, highly configurable path
designed to provide features necessary for node timing
synchronization within a SONET/SDH network. The T4
path is a simpler and less configurable path designed to
give a totally independent path for internal equipment
synchronization. The device supports use of either or both
paths, either locked together or independent.
The four SEC inputs ports are TTL/CMOS, 3 V and 5 V
compatible (with clamping if required by connecting the
VDD5V pin). Refer to the electrical characteristics section
for more information on the electrical compatibility and
details. Input frequencies supported range from 2 kHz to
100 MHz.
Common E1, DS1, OC3 and sub-divisions are supported
as spot frequencies that the DPLLs will directly lock to.
Any input frequency, up to 100 MHz, that is a multiple of
8 kHz can also be locked to via an inbuilt programmable
divider.
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FINAL
An input reference monitor is assigned to each of the four
inputs. The monitors operate continuously such that at all
times the status of all of the inputs to the device are
known. Each input can be monitored for both frequency
and activity, activity alone, or the monitors can be
disabled.
The frequency monitors have a “hard” (rejection) alarm
limit and a “soft” (flag only) alarm limit for monitoring
frequency, whilst the reference is still within its allowed
frequency band. Each input reference can be
programmed with a priority number allowing references to
be chosen according to the highest priority valid input. The
two paths (T0 and T4) have independent priorities to allow
completely independent operation of the two paths. Both
paths operate either automatic or external source
selection.
For automatic input reference selection, the T0 path has
a more complex state machine than the T4 path.
The T0 and T4 PLL paths support the following common
features:
z
z
z
z
z
z
z
z
Automatic source selection according to input
priorities and quality level
Different quality levels (activity alarm thresholds) for
each input
Variable bandwidth, lock range and damping factor
Direct PLL locking to common SONET/SDH input
frequencies or any integer multiple of 8 kHz up to
100 MHz
Automatic mode switching between Free-run, Locked
and Holdover states
Fast detection on input failure and entry into Holdover
mode (holds at the last good frequency value)
Frequency translation between input and output rates
via direct digital synthesis
High accuracy digital architecture for stable PLL
dynamics combined with an APLL for low jitter final
output clocks.
There are a number of features supported by the T0 path
that are not supported by the T4 path, although these can
also all be externally controlled by software.
The additional T0 features supported are:
z
z
z
Non-revertive mode
Phase Build-out on source switch (hit-less source
switching)
I/O phase offset control
Revision 5/November 2006 © Semtech Corp.
DATASHEET
z
Greater programmable bandwidth from 0.1 Hz to
70 Hz in 10 steps (T4 path programmable bandwidth
in 3 steps, 18, 35 and 70 Hz)
z
Noise rejection on low frequency input
z
Manual Holdover frequency control
z
Controllable automatic Holdover frequency filtering
z
Frame Sync pulse alignment.
Either the software or an internal state machine controls
the operation of the DPLL in the T0 path. The state
machine for the T4 path is very simple and cannot be
manually/externally controlled, however the overall
operation can be controlled by manual reference source
selection. One additional feature of the T4 path is the
ability to measure a phase difference between two inputs.
The T0 path DPLL always produces an output at
77.76 MHz to feed the APLL, regardless of the frequency
selected at the output pins. The T4 path can be operated
at a number of frequencies. This is to enable the
generation of extra output frequencies, which cannot be
easily related to 77.76 MHz. When the T4 path is selected
to lock to the T0 path, the T4 DPLL locks to the 8 kHz from
the T0 DPLL. This is because all of the frequencies of
operation of the T4 path can be divided to 8 kHz and this
will ensure synchronization of all the frequencies within
the two paths.
Both of the DPLLs’ outputs are connected to multiplying
and filtering APLLs. The outputs of these APLLs are
divided making a number of frequencies simultaneously
available for selection at the output clock ports. The
various combinations of DPLL, APLL and divider
configurations allow for generation of a comprehensive
set of frequencies as listed in Table 12).
To synchronize the lower output frequencies when the T0
PLL is locked to a high frequency reference input, an
additional input is provided. The SYNC2K pin (pin 28) is
used to reset the dividers that generate the 2 kHz and
8 kHz outputs such that the output 2/8 kHz clocks are
lined up with the input 2 kHz. This synchronization
method could allow for example, a master and a slave
device to be in precise alignment.
The ACS8522 also supports Sync pulse references of
4 kHz or 8 kHz although in these cases frequencies lower
than the Sync pulse reference may not necessarily be in
phase.
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ADVANCED COMMUNICATIONS
Input Reference Clock Ports
FINAL
Locking Frequency Modes
Table 4 gives details of the input reference ports, showing
the input technologies and the range of frequencies
supported on each port; the default spot frequencies and
default priorities assigned to each port on power-up or by
reset are also shown. Note that SDH and SONET networks
use different default frequencies; the network type is pinselectable (using either the SONSDHB pin or via
software). Specific frequencies and priorities are set by
configuration.
The input ports are fully interchangeable.
SDH and SONET networks use different default
frequencies; the network type is selectable using
cnfg_input_mode Reg. 34, Bit 2 ip_sonsdhb.
z
z
DATASHEET
There are three locking frequency modes that can be
configured: Direct Lock, Lock 8k and DivN.
Direct Lock Mode
In Direct Lock Mode, the internal DPLL can lock to the
selected input at the spot frequency of the input, for
example 19.44 MHz performs the DPLL phase
comparisons at 19.44 MHz.
In Lock8K and DivN modes an internal divider is used
prior to the DPLL to divide the input frequency before it is
used for phase comparisons in the DPLL.
Lock8K Mode
For SONET, ip_sonsdhb = 1
For SDH, ip_sonsdhb = 0
On power-up or by reset, the default will be set by the state
of the SONSDHB pin (pin 64). Specific frequencies and
priorities are set by configuration.
The frequency selection is programmed via the
cnfg_ref_source_frequency register (Reg. 22, 23, 27 and
28).
Lock8K mode automatically sets the divider parameters
to divide the input frequency down to 8 kHz. Lock8K can
only be used on the supported spot frequencies (see
Table 4 Note(i)). Lock8k mode is enabled by setting the
Lock8k bit (Bit 6) in the appropriate
cnfg_ref_source_frequency register location. Using lower
frequencies for phase comparisons in the DPLL results in
a greater tolerance to input jitter. It is possible to choose
which edge of the input reference clock to lock to, by
setting 8K edge polarity (Bit 2 of Reg. 03, test_register1).
Table 4 Input Reference Source Selection and Priority Table
Input Port
Channel
Number (Bin)
Input Port
Technology
Frequencies Supported
Default
Priority
SEC1
0011
TTL/CMOS
Up to 100 MHz (see Note (i))
Default (SONET): 8 kHz Default (SDH): 8 kHz
2
SEC2
0100
TTL/CMOS
Up to 100 MHz (see Note (i))
Default (SONET): 8 kHz Default (SDH): 8 kHz
3
SEC3
1000
TTL/CMOS
Up to 100 MHz (see Note (i))
Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz
4
SEC4
1001
TTL/CMOS
Up to 100 MHz (see Note (i))
Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz
5
Note:
(i) TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being
77.76 MHz. The actual spot frequencies are: 2 kHz, 4 kHz, 8 kHz (and N x 8 kHz), 1.544 MHz (SONET)/2.048 MHz (SDH), 6.48 MHz,
19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz. SONET or SDH input rate is selected via Reg. 34 Bit 2, ip_sonsdhb).
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DivN Mode
FINAL
Clock Quality Monitoring
In DivN mode, the divider parameters are set manually by
configuration (Bit 7 of the cnfg_ref_source_frequency
register), but must be set so that the frequency after
division is 8 kHz. The DivN function is defined as:
DivN = “Divide by N+ 1”, i.e. it is the dividing factor used
for the division of the input frequency, and has a value of
(N+1) where N is an integer from 1 to 12499 inclusive.
Therefore, in DivN mode the input frequency can be
divided by any integer value between 2 to 12500.
Consequently, any input frequency which is a multiple of
8 kHz, between 8 kHz to 100 MHz, can be supported by
using DivN mode.
Note...Any reference input can be set to use DivN
independently of the frequencies and configurations of the
other inputs. However only one value of N is allowed, so all
inputs with DivN selected must be running at the same
frequency.
DivN Examples
(a) To lock to 2.000 MHz:
(i)
Set the cnfg_ref_source_frequency register to
10XX0000 (binary) to enable DivN, and set the
frequency to 8 kHz - the frequency required after
division. (XX = “Leaky Bucket” ID for this input).
(ii) To achieve 8 kHz, the 2 MHz input must be
divided by 250. So, if DivN = 250 = (N + 1)
then N must be set to 249. This is done by writing
F9 hex (249 decimal) to the DivN register pair
Reg. 46/47.
(b) To lock to 10.000 MHz:
(i)
The cnfg_ref_source_frequency register is set to
10XX0000 (binary) to set the DivN and the
frequency to 8 kHz, the post-division frequency.
(XX = “Leaky Bucket” ID for this input).
(ii) To achieve 8 kHz, the 10 MHz input must be
divided by 1,250. So, if DivN, = 250 = (N+1)
then N must be set to 1,249. This is done by
writing 4E1 hex (1,249 decimal) to the DivN
register pair Reg. 46/47
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Clock quality is monitored and used to modify the priority
tables. The following parameters are monitored:
1. Activity (toggling).
2. Frequency (this monitoring is only performed when
there is no irregular operation of the clock or loss of
clock condition).
Any reference source that suffers a loss-of-activity or
clock-out-of-band condition will be declared as
unavailable.
Clock quality monitoring is a continuous process which is
used to identify clock problems. There is a difference in
dynamics between the selected clock and the other
reference clocks. Anomalies occurring on non-selected
reference sources affect only that source's suitability for
selection, whereas anomalies occurring on the selected
clock could have a detrimental impact on the accuracy of
the output clock.
Anomalies detected by the activity detector are integrated
in a Leaky Bucket Accumulator. Occasional anomalies do
not cause the Accumulator to cross the alarm setting
threshold, so the selected reference source is retained.
Persistent anomalies cause the alarm setting threshold to
be crossed and result in the selected reference source
being rejected.
Anomalies on the currently locked-to input reference
clock, whether affecting signal purity or signal frequency,
could induce jitter or frequency offsets in the output clock,
leading to anomalous behavior. Anomalies on the
selected clock, therefore, have to be detected as they
occur and the phase locked loop must be temporarily
isolated until the clock is once again pure. The clock
monitoring process cannot be used for this because the
high degree of accuracy required dictates that the
process be slow. To achieve the immediacy required by
the phase locked loop requires an alternative
mechanism.
The phase locked loop itself contains a fast activity
detector such that within approximately two missing input
clock cycles, a no-activity flag is raised and the DPLL is
frozen in Holdover mode. This flag can also be read as the
main_ref_failed bit (from Reg. 06, Bit 6) and can be set to
indicate a phase lost state by enabling Reg. 73, Bit 6. With
the DPLL in Holdover mode it is isolated from further
disturbances. If the input becomes available again before
the activity or frequency monitor rejection alarms have
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been raised, then the DPLL will continue to lock to the
input, with little disturbance. In this scenario, with the
DPLL in the “locked” state, the DPLL uses “nearest edge
locking” mode (±180° capture) avoiding cycle slips or
glitches caused by trying to lock to an edge 360° away, as
would happen with traditional PLLs.
Activity Monitoring
The ACS8522 has a combined inactivity and irregularity
monitor. The ACS8522 uses a Leaky Bucket Accumulator,
which is a digital circuit which mimics the operation of an
analog integrator, in which input pulses increase the
output amplitude but die away over time. Such integrators
are used when alarms have to be triggered either by fairly
regular defect events, which occur sufficiently close
together, or by defect events which occur in bursts. Events
which are sufficiently spread out should not trigger the
alarm. By adjusting the alarm setting threshold, the point
at which the alarm is triggered can be controlled. The
point at which the alarm is cleared depends upon the
decay rate and the alarm clearing threshold.
On the alarm setting side, if several events occur close
together, each event adds to the amplitude and the alarm
will be triggered quickly; if events occur further apart, but
still sufficiently close together to overcome the decay, the
alarm will be triggered eventually. If events occur at a rate
which is not sufficient to overcome the decay, the alarm
will not be triggered. On the alarm clearing side, if no
defect events occur for a sufficient time, the amplitude
will decay gradually and the alarm will be cleared when
the amplitude falls below the alarm clearing threshold.
The ability to decay the amplitude over time allows the
importance of defect events to be reduced as time passes
by. This means that, in the case of isolated events, the
alarm will not be set, whereas, once the alarm becomes
set, it will be held on until normal operation has persisted
for a suitable time (but if the operation is still erratic, the
alarm will remain set). See Figure 3.
There is one Leaky Bucket Accumulator per input channel.
Each Leaky Bucket can select from four Configurations
(Leaky Bucket Configuration 0 to 3). Each Leaky Bucket
Configuration is programmable for size, alarm set and
reset thresholds, and decay rate.
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DATASHEET
Each source is monitored over a 128 ms period. If, within
a 128 ms period, an irregularity occurs that is not deemed
to be due to allowable jitter/wander, then the
Accumulator is incremented.
The Accumulator will continue to increment up to the
point that it reaches the programmed Bucket size. The “fill
rate” of the Leaky Bucket is, therefore, 8 units/second.
The “leak rate” of the Leaky Bucket is programmable to
be in multiples of the fill rate (x 1, x 0.5, x 0.25 and
x 0.125) to give a programmable leak rate from
8 units/sec down to 1 unit/sec. A conflict between trying
to “leak” at the same time as a “fill” is avoided by
preventing a leak when a fill event occurs.
Disqualification of a non-selected reference source is
based on inactivity, or on an out-of-band result from the
frequency monitors. The currently selected reference
source can be disqualified for phase, frequency, inactivity
or if the source is outside the DPLL lock range. If the
currently selected reference source is disqualified, the
next highest priority, qualified reference source is
selected.
Interrupts for Activity Monitors
The loss of the currently selected reference source will
eventually cause the input to be considered invalid,
triggering an interrupt, if not masked. The time taken to
raise this interrupt is dependent on the Leaky Bucket
Configuration of the activity monitors. The fastest Leaky
Bucket setting will still take up to 128 ms to trigger the
interrupt. The interrupt caused by the brief loss of the
currently selected reference source is provided to
facilitate very fast source failure detection if desired. It is
triggered after missing just a couple of cycles of the
reference source. Some applications require the facility to
switch downstream devices based on the status of the
reference sources. In order to provide extra flexibility, it is
possible to flag the main_ref_failed interrupt (Reg. 06 Bit
6) on the pin TDO. This is simply a copy of the status bit in
the interrupt register and is independent of the mask
register settings. The bit is reset by writing to the interrupt
status register in the normal way. This feature can be
enabled and disabled by writing to Reg. 48 Bit 6.
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Figure 3 Inactivity and Irregularity Monitoring
Inactivities/Irregularities
Reference
Source
bucket_size
Leaky
Bucket
Response
upper_threshold
lower_threshold
Programmable Fall Slopes
(all programmable)
Alarm
Leaky Bucket Timing
The time taken (in seconds) to raise an inactivity alarm on
a reference source that has previously been fully active
(Leaky Bucket empty) will be:
(cnfg_upper_threshold_n) / 8
where n is the number of the Leaky Bucket Configuration.
If an input is intermittently inactive then this time can be
longer. The default setting of cnfg_upper_threshold is 6,
therefore the default time is 0.75 s.
The time taken (in seconds) to cancel the activity alarm on
a previously completely inactive reference source is
calculated, for a particular Leaky Bucket, as:
The sts_reference_sources out-of-band alarm for a
particular reference source is raised when the reference
source is outside the acceptable frequency range. With
the default register settings a soft alarm is raised if the
drift is outside ±11.43 ppm and a hard alarm is raised if
the drift is outside ±15.24 ppm. Both of these limits are
programmable from 3.8 ppm up to 61 ppm.
The ACS8522 DPLL has a programmable lock and
capture range frequency limit up to ±80 ppm (default is
±9.2 ppm).
Selection of Input Reference Clock Source
Under normal operation, the input reference sources are
selected automatically by an order of priority. But, for
special circumstances, such as chip or board testing, the
selection may be forced by configuration.
[2 (a) x (b - c)]/ 8
where:
a = cnfg_decay_rate_n
b = cnfg_bucket_size_n
c = cnfg_lower_threshold_n
Frequency Monitoring
Automatic operation selects a reference source based on
its pre-defined priority and its current availability. A table
is maintained which lists all reference sources in the order
of priority. This is initially defined by the default
configuration and can be changed via the Serial interface
by the Network Manager. In this way, when all the defined
sources are active and valid, the source with the highest
programmed priority is selected but, if this source fails,
the next-highest source is selected, and so on.
The ACS8522 performs input frequency monitoring to
identify reference sources which have drifted outside the
acceptable frequency range measured with respect either
to the output clock or to the XO clock.
Restoration of repaired reference sources is handled
carefully to avoid inadvertent disturbance of the output
clock. For this, the ACS8522 has two modes of operation;
Revertive and Non-revertive.
(where n = the number of the relevant Leaky Bucket
Configuration in each case).
The default setting is shown in the following:
[21 x (8 - 4)] /8 = 1.0 secs
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In Revertive mode, if a re-validated (or newly validated)
source has a higher priority than the reference source
which is currently selected, a switch over will take place.
Many applications prefer to minimize the clock switching
events and choose Non-revertive mode.
In Non-revertive mode, when a re-validated (or newly
validated) source has a higher priority then the selected
source will be maintained. The re-validation of the
reference source will be flagged in the sts_sources_valid
register (Reg. 0E and 0F) and, if not masked, will generate
an interrupt. Selection of the re-validated source can take
place under software control or if the currently selected
source fails.
To enable software control, the software should briefly
enable Revertive mode to effect a switch-over to the
higher priority source. When there is a reference available
with higher priority than the selected reference, there will
be NO change of reference source as long as the
Non-revertive mode remains on, and the currently
selected source is valid. A failure of the selected
reference will always trigger a switch-over regardless of
whether Revertive or Non-revertive mode has been
chosen.
Forced Control Selection
A configuration register, force_select_reference_source
Reg. 33, controls both the choice of automatic or forced
selection and the selection itself (when forced selection is
required). For Automatic choice of source selection, the
four LSB bit value is set to all zeros or all ones (default).
To force a particular input the bit value must be set as
follows: 0011 forces SEC1, 0100 forces SEC2, 1000
forces SEC3 and 1001 forces SEC4. Forced selection is
not the normal mode of operation, and the
force_select_reference_source variable is defaulted to
the all-one value on reset, thereby adopting the automatic
selection of the reference source.
Automatic Control Selection
When an automatic selection is required, the
force_select_reference_source register LSB four bits
must be set to all zeros or all ones. The configuration
registers, cnfg_ref_selection_priority (Reg. 19, 1B and
1C), hold 4-bit values which represents the desired
priority of that particular port. Unused ports should be
given the value 0000 in the relevant register to indicate
they are not to be included in the priority table. On
power-up, or following a reset, the whole of the
configuration file will be defaulted to the values defined
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DATASHEET
by Table 4. The selection priority values are all relative to
each other, with lower-valued numbers taking higher
priorities. Each reference source should be given a unique
number; the valid values are 1 to 15 (dec). A value of zero
disables the reference source. However if two or more
inputs are given the same priority number those inputs
will be selected on a first in, first out basis. If the first of
two same priority number sources goes invalid the second
will be switched in. If the first then becomes valid again, it
becomes the second source on the first in, first out basis,
and there will not be a switch. If a third source with the
same priority number as the other two becomes valid, it
joins the priority list on the same first in, first out basis.
There is no implied priority based on the channel
numbers. Revertive/Non-revertive mode has no effect on
sources with the same priority value.
Ultra Fast Switching
A reference source is normally disqualified after the Leaky
Bucket monitor thresholds have been crossed. An option
for a faster disqualification has been implemented,
whereby if Reg. 48 Bit 5 (ultra_fast_switch) is set, then a
loss of activity of just a few reference clock cycles will set
the main_ref_failed alarm and cause a reference switch.
This can be configured (see Reg. 06, Bit 6) to cause an
interrupt to occur instead of, or as well as, causing the
reference switch.
The sts_interrupts register Reg. 06 Bit 6 (main_ref_failed)
is used to flag inactivity on the reference that the device
is locked to much faster than the activity monitors can
support. If Reg. 48 Bit 6 of the cnfg_monitors register
(los_flag_on_TDO) is set, then the state of this bit is driven
onto the TDO pin of the device.
Note...The flagging of the loss of the main reference failure on
TDO is simply allowing the status of the sts_interrupts bit
main_ref_failed (Reg. 06, Bit 6) to be reflected in the state of
the TDO output pin. The pin will, therefore, remain High until
the interrupt is cleared. This functionality is not enabled by
default so the usual JTAG functions can be used. When the
TDO output from the ACS8522 is connected to the TDI pin of
the next device in the JTAG scan chain, the implementation
should be such that a logic change caused by the action of the
interrupt on the TDI input should not effect the operation when
JTAG is not active.
Fast External Switching Mode-SRCSW pin
Fast External Switching mode allows fast switching
between inputs SEC1 and SEC2 only. The mode must first
be enabled before switching can take place, and then
switching is controlled via the SRCSW pin.
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There are two ways to enable Fast External Switching
mode:
z
Mode enable by register write - by writing to Reg. 48
Bit 4, or
z
Mode enable by hardware “initialization” - by holding
SRCSW High throughout reset and for at least a
further 251 ms after PORB has gone High (250 ms
allowance for the internal reset to be removed plus
1 ms allowance for APLLs to start-up and become
stable). A simple external circuit to set SCRSW high for
the required period is shown in “Simplified Application
Schematic” on page 114. If SCRSW pin is held Low at
any time during the 251 ms initialization period, this
may result in Fast External Switching mode not being
enabled correctly.
Once Fast External Switching mode is enabled, then the
value of the SRCSW pin directly selects either SEC1
(SRCSW High) or SEC2 (SRCSW Low). If this mode is
enabled by hardware initialization, then it configures the
default frequency tolerance of SEC1 and SEC2 to
± 80 ppm (Reg. 41 and Reg. 42). Either of these registers
can be subsequently reconfigured by external software, if
required.
When Fast External Switching mode is enabled, the
device operates as a simple switch. All clock monitoring is
disabled and the DPLL will simply be forced to try to lock
on to the indicated reference source. Consequently the
device will always indicate “locked” state in the
sts_operating register (Reg. 09, Bits 2:0).
Output Clock Phase Continuity on Source
Switchover
If either PBO is selected on (default), or, if DPLL frequency
limit is set to less than ±30 ppm or (±9.2 ppm default), the
device will always comply with GR-1244-CORE[19]
specification for Stratum 3 (maximum rate of phase
change of 81 ns/1.326 ms), for all input frequencies.
Modes of Operation
The ACS8522 has three primary modes of operation
(Free-run, Locked and Holdover) supported by three
secondary, temporary modes (Pre-locked, Lost-phase and
Pre-locked2). These are shown in the State Transition
Diagram, Figure 4.
The ACS8522 can operate in Forced or Automatic control.
On reset, the ACS8522 reverts to Automatic Control,
where transitions between states are controlled
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DATASHEET
completely automatically. Forced Control can be invoked
by configuration, allowing transitions to be performed
under external control. This is not the normal mode of
operation, but is provided for special occasions such as
testing, or where a high degree of hands-on control is
required.
Free-run Mode
The Free-run mode is typically used following a power-onreset or a device reset before network synchronization
has been achieved. In the Free-run mode, the timing and
synchronization signals generated from the ACS8522 are
based on the 12.800 MHz clock frequency provided from
the external oscillator and are not synchronized to an
input reference source. By default, the frequency of the
output clock is a fixed multiple of the frequency of the
external oscillator, and the accuracy of the output clock is
equal to the accuracy of the oscillator. However the
external oscillator frequency can be calibrated to improve
its accuracy by a software calibration routine using
register cnfg_nominal_frequency (Reg. 3C and 3D). For
example a 500 ppm offset crystal could be made to look
like one accurate to within ±0.02 ppm.
The transition from Free-run to Pre-locked occurs when
the ACS8522 selects a reference source.
Pre-locked Mode
The ACS8522 will enter the Locked state in a maximum of
100 seconds, as defined by GR-1244-CORE[19]
specification, if the selected reference source is of good
quality. If the device cannot achieve lock within 100
seconds, it reverts to Free-run mode and another
reference source is selected.
Locked Mode
The Locked mode is entered from Pre-locked, Pre-locked2
or Phase-lost mode when an input reference source has
been selected and the DPLL has locked. The DPLL is
considered to be locked when the phase loss/lock
detectors (See“Phase Lock/Loss Detection” on page 19)
indicate that the DPLL has remained in phase lock
continuously for at least one second. When the ACS8530
is in Locked mode, the output frequency and phase tracks
that of the selected input reference source.
Lost-phase Mode
Lost-phase mode is used whenever the phase loss/lock
detectors (See“Phase Lock/Loss Detection” on page 19)
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indicate that the DPLL has lost phase lock. The DPLL will
still be trying to lock to the input clock reference, if it
exists. If the Leaky Bucket Accumulator calculates that
the anomaly is serious, the device disqualifies the
reference source. If the device spends more than 100
seconds in Lost-phase mode, the reference is disqualified
and a phase alarm is raised on it. If the reference is
disqualified, one of the following transitions takes place:
1. Go to Pre-locked2;
- If a known good stand-by source is available.
z
Fast - (Reg. 40 Bit 6, cnfg_holdover_modes,
fast_averaging: set High), giving a -3 dB filter
response point corresponding to a period of
approximately eight minutes, or
z
Slow - (Reg. 40 Bit 6, cnfg_holdover_modes,
fast_averaging: set Low) giving a -3 dB filter response
point corresponding to a period of approximately 110
minutes.
Instantaneous
2. Go to Holdover;
- If no stand-by sources are available.
Holdover Mode
Holdover mode is the operating condition the device
enters when its currently selected input source becomes
invalid, and no other valid replacement source is
available. In this mode, the device resorts to using stored
frequency data, acquired when the input reference source
was still valid, to control its output frequency.
In Holdover mode, the ACS8522 provides the timing and
synchronization signals to maintain the Network Element
but is not phase locked to any input reference source. Its
output frequency is determined by an averaged version of
the DPLL frequency when last in the Locked Mode.
Holdover can be configured to operate in either:
z
Automatic mode
(Reg. 34 Bit 4, cnfg_input_mode: man_holdover set
Low), or
z
Manual mode
(Reg. 34 Bit 4, cnfg_input_mode: man_holdover set
High).
Automatic Mode
In Automatic mode, the device can be configured to
operate using either:
z
Averaged - (Reg. 40 Bit 7, cnfg_holdover_modes,
auto_averaging: set High), or
z
Instantaneous - (Reg. 40 Bit 7, cnfg_holdover_modes,
auto_averaging: set Low).
Averaged
In the Averaged mode, the frequency (as reported by
sts_current_DPLL_frequency, see Reg. 0C, Reg. 0D and
Reg. 07) is filtered internally using an Infinite Impulse
Response filter, which can be set to either:
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DATASHEET
In Instantaneous mode, the DPLL freezes at the frequency
it was operating at the time of entering Holdover mode. It
does this by using only its internal DPLL integral path
value (as reported in Reg. 0C, 0D, and 07) to determine
output frequency. The DPLL proportional path is not used
so that any recent phase disturbances have a minimal
effect on the Holdover frequency. The integral value used
can be viewed as a filtered version of the locked output
frequency over a short period of time. The period being in
inverse proportion to the DPLL bandwidth setting.
Manual Mode
(Reg. 34 Bit 4, cnfg_input_mode, man_holdover set
High.) The Holdover frequency is determined by the value
in register cnfg_holdover_frequency (Reg. 3E, Reg. 3F,
and part of Reg. 40). This is a 19-bit signed number, with
a LSB resolution of 0.0003068 ppm, which gives an
adjustment range of ±80 ppm. This value can be derived
from a reading of the register
sts_current_DPLL_frequency (Reg. 0D, 0C and 07), which
gives, in the same format, an indication of the current
output frequency deviation, which would be read when
the device is locked. If required, this value could be read
by external software and averaged over time. The
averaged value could then be fed to the
cnfg_holdover_frequency register, ready for setting the
averaged frequency value when the device enters
Holdover mode. The sts_current_DPLL_frequency value
is internally derived from the Digital Phase Locked Loop
(DPLL) integral path, which represents a short-term
average measure of the current frequency, depending on
the locked loop bandwidth (Reg. 67) selected.
It is also possible to combine the internal averaging filters
with some additional software filtering. For example the
internal fast filter could be used as an anti-aliasing filter
and the software could further filter this before
determining the actual Holdover frequency. To support
this feature, a facility to read out the internally averaged
frequency has been provided.
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Figure 4 Automatic Mode Control State Diagram
(1) Reset
Free-run
select ref
(state 001)
(2) all refs evaluated
&
at least one ref valid
(3) no valid standby ref
&
(main ref invalid
or out of lock > 100s
Reference sources are flagged as valid when
active, in-band and have no phase alarm set.
(4) valid standby ref
&
[main ref invalid or
(higher-priority ref valid
& in revertive mode) or
out of lock > 100s]
All sources are continuously checked for
activity and frequency
Pre-locked
wait for up to 100s
(state 110)
Only the main source is checked for phase.
A phase lock alarm is only raised on a
reference when that reference has lost phase
whilst being used as the main reference. The
micro-processor can reset the phase lock
alarm.
(5) selected ref
phase locked
A source is considered to have phase locked
when it has been continuously in phase lock
for between 1 and 2 seconds.
Locked
keep ref
(state 100)
(6) no valid standby ref
&
main ref invalid
(10) selected source
phase locked
(8) phase
regained
(9) valid standby ref
within 100s
&
[main ref invalid or
(higher priority ref valid
& in revertive mode)]
Pre-locked2
wait for up to 100s
(state 101)
(12) valid standby ref
&
(main ref invalid
or out of lock >100s)
(15) valid standby ref
&
[main ref invalid or
(higher-priority ref valid
& in revertive mode) or
out of lock >100s]
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(7) phase lost
on main ref
Lost-phase
wait for up to 100s
(state 111)
(11) no valid standby ref
&
(main ref invalid
or out of lock >100s)
Holdover
select ref
(state 010)
(13) no valid standby ref
&
(main ref invalid
or out of lock >100s)
(14) all refs evaluated
&
at least one ref valid
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By setting Reg. 40, Bit 5, cnfg_holdover_modes,
read_average, the value read back from the
cnfg_holdover_frequency register will be the filtered
value. The filtered value is available regardless of what
actual Holdover mode is selected. Clearly this results in
the register not reading back the data that was written to
it.
Example: Software averaging to eliminate temperature drift.
Select Manual Holdover mode by setting Reg. 34 Bit 4,
cnfg_input_mode, man_holdover High.
Select Fast Holdover Averaging mode by setting Reg. 40
Bit 6, cnfg_holdover_modes, auto_averaging High and
Reg. 40 Bit 7 High.
Select to be able to read back filtered output by setting
Reg. 40 Bit 5, cnfg_holdover_modes, read_average High.
Software periodically reads averaged value from the
cnfg_holdover_frequency register and the temperature
(not supplied from ACS8522). Software processed
frequency and temperature and places data in software
look-up table or other algorithm. Software writes back
appropriate averaged value into the
cnfg_holdover_frequency register.
Once Holdover mode is entered, software periodically
updates the cnfg_holdover_frequency register using the
temperature information (not supplied from ACS8522).
Mini-holdover Mode
Holdover mode so far described refers to a state to which
the internal state machine switches as a result of activity
or frequency alarms, and this state is reported in Reg. 09.
To avoid the DPLL’s frequency being pulled off as a result
of a failed input, then the DPLL has a fast mechanism to
freeze its current frequency within one or two cycles of the
input clock source stopping. Under these circumstances
the DPLL enters Mini-holdover mode; the Mini-holdover
frequency used being determined by Reg. 40, Bits [4:3],
cnfg_holdover_modes, mini_holdover_mode.
Mini-holdover mode only lasts until one of the following
happens:
z
A new source has been selected, or
z
The state machine enters Holdover mode, or
z
The original fault on the input recovers.
External Factors Affecting Holdover Mode
If the external TCXO/OCXO frequency is varying due to
temperature fluctuations in the room, then the
Revision 5/November 2006 © Semtech Corp.
DATASHEET
instantaneous value can be different from the average
value, and then it may be possible to exceed the
0.05 ppm limit (depending on how extreme the
temperature fluctuations are). It is advantageous to
shield the TCXO/OCXO to slow down frequency changes
due to drift and external temperature fluctuations.
The frequency accuracy of Holdover mode has to meet the
ITU-T, ETSI and Telcordia performance requirements. The
performance of the external oscillator clock is critical in
this mode, although only the frequency stability is
important - the stability of the output clock in Holdover is
directly related to the stability of the external oscillator.
Pre-locked2 Mode
This state is very similar to the Pre-Locked state. It is
entered from the Holdover state when a reference source
has been selected and applied to the phase locked loop.
It is also entered if the device is operating in Revertive
mode and a higher-priority reference source is restored.
Upon applying a reference source to the phase locked
loop, the ACS8522 will enter the Locked state in a
maximum of 100 seconds, as defined by GR-1244CORE[19] specification, if the selected reference source is
of good quality.
If the device cannot achieve lock within 100 seconds, it
reverts to Holdover mode and another reference source is
selected.
DPLL Architecture and Configuration
A Digital PLL gives a stable and consistent level of
performance that can be easily programmed for different
dynamic behavior or operating range. It is not affected by
operating conditions or silicon process variations. Digital
synthesis is used to generate all required SONET/SDH
output frequencies. The digital logic operates at
204.8 MHz that is multiplied up from the external
12.800 MHz oscillator module. Hence the best resolution
of the output signals from the DPLL is one 204.8 MHz
cycle or 4.9 ns.
Additional resolution and lower final output jitter is
provided by a de-jittering Analog PLL that reduces the
4.9 ns pk-pk jitter from the digital down to 500 ps pk-pk
and 60 ps RMS as typical final outputs measured
broadband (from 10 Hz to 1 GHz).
This arrangement combines the advantages of the
flexibility and repeatability of a DPLL with the low jitter of
an APLL. The DPLLs in the ACS8522 are uniquely very
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programmable for all PLL parameters of bandwidth (from
0.1 Hz up to 70 Hz), damping factor (from 1.2 to 20),
frequency acceptance and output range (from 0 to
80 ppm, typically 9.2 ppm), input frequency (12 common
SONET/SDH spot frequencies) and input-to-output phase
offset (in 6 ps steps up to 200 ns). There is no
requirement to understand the loop filter equations or
detailed gain parameters since all high level factors such
as overall bandwidth can be set directly via registers in
the microprocessor interface. No external critical
components are required for either the internal DPLLs or
APLLs, providing another key advantage over traditional
discrete designs.
The T4 DPLL is similar in structure to the T0 DPLL, but
since the T4 is only providing a clock synthesis and input
to output frequency translation function, with no defined
requirement for jitter attenuation or input phase jump
absorption, then its bandwidth is limited to the high end
and the T4 does not incorporate many of the Phase Buildout and adjustment facilities of the T0 DPLL.
TO DPLL Main Features
z
Two programmable DPLL bandwidth controls (Locked
and Acquisition bandwidth), each with 10 steps from
0.1 Hz to 70 Hz
z
Programmable damping factor: For optional faster
locking and peaking control. Factors = 1.2, 2.5, 5, 10
or 20
z
Multiple phase lock detectors
z
Input to output phase offset adjustment
(Master/Slave), ±200 ns, 6 ps resolution step size
z
PBO phase offset on source switching - disturbance
down to ±5 ns
z
Multi-cycle phase detection and locking,
programmable up to ±8192 UI - improves jitter
tolerance in direct lock mode
T4 DPLL Main Features
z
Single programmable DPLL bandwidth control: 18 Hz,
35 Hz or 70 Hz
z
Programmable damping factor: For optional faster
locking and peaking control. Factors = 1.2, 2.5, 5, 10
or 20
z
Multiple phase lock detectors
z
Multi-cycle phase detection and locking,
programmable up to ±8192 UI - improves jitter
tolerance in direct lock mode
z
DS3/E3 support (44.736 MHz / 34.368 MHz) at same
time as OC-N rates from T0 DPLL
z
Low jitter E1/DS1 options at same time as OC-N rates
from T0 DPLL
z
Frequencies of n x E1/DS1 including 16 and 12 x E1,
and 16 and 24 x DS1 supported
z
Low jitter MFrSync (2 kHz) and FrSync (8 kHz) outputs
z
Can use the T4 DPLL as an Independent FrSync DPLL
z
Can use the phase detector in T4 DPLL to measure
the input phase difference between two inputs.
The structure of the T0 and T4 PLLs are shown later in
Figure 10 in the section on output clock ports. That
section also details how the DPLLs and particular output
frequencies are configured. The following sections detail
some component parts of the DPLL.
TO DPLL Automatic Bandwidth Controls
In Automatic Bandwidth Selection mode (Reg. 3B), the T0
DPLL bandwidth setting is selected automatically from
the Acquisition Bandwidth or Locked Bandwidth
configurations programmed in cnfg_T0_DPLL_acq_bw
Reg. 69 and cnfg_T0_DPLL_locked_bw Reg. 67
respectively. If this mode is not selected, the DPLL
acquires and locks using only the bandwidth set by
Reg. 67.
Phase Detectors
z
Holdover frequency averaging with a choice of:
Average times: 8 minutes or 110 minutes. Value can
also be read out.
z
Multiple E1 and DS1 outputs supported
z
Low jitter MFrSync (2 kHz) and FrSync (8 kHz) outputs.
Revision 5/November 2006 © Semtech Corp.
DATASHEET
A Phase and Frequency detector is used to compare input
and feedback clocks. This operates at input frequencies
up to 77.76 MHz. The whole DPLL can operate at spot
frequencies from 2 kHz up to 77.76 MHz. A common
arrangement however is to use Lock8k mode (see Bit 6 of
Reg. 22, 23, 27 and 28) where all input frequencies are
divided down to 8 kHz internally. Marginally better MTIE
figures may be possible in direct lock mode due to more
regular phase updates.
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A patented multi-phase detector is used in order to give
an infinitesimally small input phase resolution combined
with large jitter tolerance. The following phase detectors
are used:
z
Phase and frequency detector (±360° or ±180°
range)
z
An early/late phase detector for fine resolution
z
A multi-cycle phase detector for large input jitter
tolerance (up to 8191 UI), which captures and
remembers phase differences of many cycles
between input and feedback clocks.
the loop has to pull in to is still tracked and remembered
by the multi-cycle phase detector in either case.
Phase Lock/Loss Detection
Phase lock/loss detection is handled in several ways.
Phase loss can be triggered from:
The phase detectors can be configured to be immune to
occasional missing input clock pulses by using nearest
edge detection (±180° capture) or the normal
± 360° phase capture range which gives frequency
locking. The device will automatically switch to nearest
edge locking when the multi-UI phase detector is not
enabled and the other phase detectors have detected
that phase lock has been achieved.
It is possible to disable the selection of nearest edge
locking via Reg. 03 Bit 6 set to 1. In this setting, frequency
locking will always be enabled.
The balance between the first two types of phase detector
employed can be adjusted via registers 6A to6D. The
default settings should be sufficient for all modes.
Adjustment of these settings affects only small signal
overshoot and bandwidth.
The multi-cycle phase detector is enabled via Reg. 74,
Bit 6 set to 1 and the range is set in exponentially
increasing steps from ±1 UI, 3 UI, 7 UI, 15 UI … up to
8191 UI via Reg. 74, Bits [3:0].
When this detector is enabled it keeps a track of the
correct phase position over many cycles of phase
difference to give excellent jitter tolerance. This provides
an alternative to switching to Lock8k mode as a method
of achieving high jitter tolerance.
An additional control (Reg. 74 Bit 5) enables the multiphase detector value to be used in the final phase value
as part of the DPLL loop. When enabled by setting High,
the multi cycle phase value will be used in the loop and
gives faster pull in (but more overshoot). The
characteristics of the loop will be similar to Lock8k mode
where again large input phase differences contribute to
the loop dynamics. Setting the bit Low only uses a max
figure of 360 degrees in the loop and will give slower pullin but gives less overshoot. The final phase position that
Revision 5/November 2006 © Semtech Corp.
DATASHEET
z
The fine phase lock detector, which measures the
phase between input and feedback clock
z
The coarse phase lock detector, which monitors whole
cycle slips
z
Detection that the DPLL is at min. or max. frequency
z
Detection of no activity on the input.
Each of these sources of phase loss indication is
individually enabled via register bits (see Reg. 73, 74 and
4D). Phase lock or lost is used to determine whether to
switch to nearest edge locking and whether to use
acquisition or Locked bandwidth settings for the DPLL.
Acquisition bandwidth is used for faster pull-in from an
unlocked state.
The coarse phase lock detector detects phase differences
of n cycles between input and feedback clocks, where n is
set by Reg. 74, Bits 3:0; the same register that is used for
the coarse phase detector range, since these functions go
hand in hand. This detector may be used in the case
where it is required that a phase loss indication is not
given for reasonable amounts of input jitter and so the
fine phase loss detector is disabled and the coarse
detector is used instead.
Damping Factor Programmability
The DPLL damping factor is set by default to provide a
maximum wander gain peak of around 0.1 dB. Many of
the specifications (e.g. GR-1244-CORE[19], G.812[10] and
G.813[11]) specify a wander transfer gain of less than
0.2 dB. GR-253[17] specifies jitter (not wander) transfer of
less than 0.1 dB. To accommodate the required levels of
transfer gain, the ACS8522 provides a choice of damping
factors, with more choice given as the bandwidth setting
increases into the frequency regions classified as jitter.
Table 5 shows which damping factors are available for
selection at the different bandwidth settings, and what
the corresponding jitter transfer approximate gain peak
will be.
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Table 5 Available Damping Factors for different DPLL
Bandwidths, and associated Jitter Peak Values
Bandwidth
Reg. 6B [2:0]
DATASHEET
Table 7 Telcordia GR-1244 CORE Specification
Parameter
Damping
Gain Peak/ dB
Factor selected
Value
Tolerance
±4.6 ppm over 20 year lifetime
Drift
(Frequency Drift
over supply
voltage range of
+2.7 V to +3.3 V)
±0.05 ppm/15 seconds @ constant temp.
0.1 Hz to 4 Hz
1, 2, 3, 4, 5
5
0.1
8 Hz
1
2.5
0.2
2, 3, 4, 5
5
0.1
1
1.2
0.4
2
2.5
0.2
3, 4, 5
5
0.1
and a drift of 280 ppb over the temperature range 0 to
+50°C. Please contact Semtech for information on crystal
oscillator suppliers
1
1.2
0.4
Crystal Frequency Calibration
2
2.5
0.2
3
5
0.1
4, 5
10
0.06
1
1.2
0.4
2
2.5
0.2
3
5
0.1
4
10
0.06
5
20
0.03
The absolute crystal frequency accuracy is less important
than the stability since any frequency offset can be
compensated by adjustment of register values in the IC.
This allows for calibration and compensation of any
crystal frequency variation away from its nominal value.
± 50 ppm adjustment would be sufficient to cope with
most crystals, in fact the range is an order of magnitude
larger due to the use of two 8-bit register locations. The
setting of the cnfg_nominal_frequency register allows for
this adjustment. An increase in the register value
increases the output frequencies by 0.0196229 ppm for
each LSB step.
18 Hz
35 Hz
70 Hz
Local Oscillator Clock
The Master system clock on the ACS8522 should be
provided by an external clock oscillator of frequency
12.800 MHz. The clock specification is important for
meeting the ITU/ETSI and Telcordia performance
requirements for Holdover mode. ITU and ETSI
specifications permit a combined drift characteristic, at
constant temperature, of all non-temperature-related
parameters, of up to 10 ppb per day. The same
specifications allow a drift of 1 ppm over a temperature
range of 0 to +70°C.
Value
Tolerance
±4.6 ppm over 20 year lifetime
Drift
(Frequency Drift
over supply
voltage range of
+2.7 V to +3.3 V)
±0.05 ppm/15 seconds @ constant temp.
Note...The default register value (in decimal) = 39321
(9999 hex) = 0 ppm offset. The minimum to maximum offset
range of the register is 0 to 65535 dec, giving an adjustment
range of -771 ppm to +514 ppm of the output frequencies, in
0.0196229 ppm steps.
Example: If the crystal was oscillating at 12.800 MHz + 5 ppm,
then the calibration value in the register to give a - 5 ppm
adjustment in output frequencies to compensate for the
crystal inaccuracy, would be:
39321 - (5 / 0.0196229) = 39066 (dec) = 989A (hex).
Output Wander
z
z
±0.01 ppm/day @ constant temp.
z
±1 ppm over temp. range 0 to +70°C
z
Telcordia specifications are somewhat tighter, requiring a
non-temperature-related drift of less than 40 ppb per day
Revision 5/November 2006 © Semtech Corp.
±0.28 ppm/over temp. range 0 to +50°C
Wander and jitter present on the output clocks are
dependent on:
Table 6 ITU and ETSI Specification
Parameter
±0.04 ppm/15 seconds @ constant temp.
The magnitudes of wander and jitter on the selected
input reference clock (in Locked mode)
The internal wander and jitter transfer characteristic
(in Locked mode)
The jitter on the local oscillator clock
The wander on the local oscillator clock (in Holdover
mode).
Wander and jitter are treated in different ways to reflect
their differing impacts on network design. Jitter is always
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strongly attenuated, whilst wander attenuation can be
varied to suit the application and operating state. Wander
and jitter attenuation is performed using a digital phase
locked loop (DPLL) with a programmable bandwidth. This
gives a transfer characteristic of a low pass filter, with a
programmable pole. It is sometimes necessary to change
the filter dynamics to suit particular circumstances - one
example being when locking to a new source, the filter can
be opened up to reduce locking time and can then be
tightened again to remove wander. A change between
different bandwidths for locking and for acquisition is
handled automatically within the ACS8522.
There may be a phase shift across the ACS8522 between
the selected input reference source and the output clock
over time, mainly caused by frequency wander in the
external oscillator module. Higher stability XOs will give
better performance for MTIE. The oscillator becomes
more critical at DPLL bandwidth near to or below 0.1 Hz
since the rate of change of the DPLL may be slow
compared to the rate of change of the oscillator
frequency. Shielding of the OCXO or TCXO can further slow
down the rate of change of temperature and hence
frequency, thus improving output wander performance.
The phase shift may vary over time but will be constrained
to lie within specified limits. The phase shift is
characterized using two parameters, MTIE (Maximum
Time Interval Error) and TDEV (Time Deviation) which,
although being specified in all relevant specifications,
differ in acceptable limits in each one.
Typical measurements for the ACS8522 are shown in
Figure 5, for Locked mode operation. Figure 6 shows a
typical measurement of Phase Error accumulation in
Holdover mode operation.
relevant specification (See “References” on page 115),
for example:
1. ETSI ETS-300 462-5[4], Section 9.1, requires that the
short-term phase error during switchover (i.e. Locked
to Holdover to Locked) be limited to an accumulation
rate no greater than 0.05 ppm during a 15 second
interval.
2. ETSI ETS-300 462-5[4], Section 9.2, requires that the
long-term phase error in the Holdover mode should
not exceed:
{(a1 + a2)S + 0.5bS2 + c}
where
a1 = 50 ns/s (allowance for initial frequency offset)
a2 = 2000 ns/s (allowance for temperature variation)
b = 1.16x10-4 ns/s2 (allowance for ageing)
c = 120 ns (allowance for entry into Holdover mode).
S = Elapsed time (s) after loss of external ref. input
3. ANSI Tin1.101-1999[1], Section 8.2.2, requires that
the phase variation be limited so that no more than
255 slips (of 125 µs each) occur during the first day of
Holdover. This requires a frequency accuracy better
than:
((24x60x60)+(255x125µs))/(24x60x60) = 0.37 ppm
Temperature variation is not restricted, except to
within the normal bounds of 0 to 50°C.
4. Telcordia GR-1244-CORE[19], Section 5.2, shows that
an initial frequency offset of 50 ppb is permitted on
entering Holdover, whilst a drift over temperature of
280 ppb is allowed; an allowance of 40 ppb is
permitted for all other effects.
5. ITU G.822[12], Section 2.6, requires that the slip rate
during category (b) operation (interpreted as being
applicable to Holdover mode operation) be limited to
less than 30 slips (of 125 µs each) per hour.
The required performance for phase variation during
Holdover is specified in several ways and depends on the
Revision 5/November 2006 © Semtech Corp.
DATASHEET
Page 21
((60 x 60) + (30 x 125 µs))/(60 x 60)) = 1.042 ppm
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Figure 5 Maximum Time Interval Error and Time Deviation of T0 PLL Output Port
MTIE for G.813 option 1,
Constant temperature wander limit
TDEV for G.813 option 1,
Constant temperature wander limit
F8530D_027MtieTdevCombF6_01
Figure 6 Phase Error Accumulation of T0 PLL Output Port in Holdover Mode
10000000
Phase Error (ns)
1000000
Permitted Phase Error Limit
100000
10000
1000
100
Revision 5/November 2006 © Semtech Corp.
Typical measurement, 25°C constant temperature
1000
10000
Page 22
100000
Observation interval (s)
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Jitter and Wander Transfer
The ACS8522 has a programmable jitter and wander
transfer characteristic. This is set by the DPLL bandwidth.
The -3 dB jitter transfer attenuation point can be set in the
range from 0.1 Hz to 70 Hz in 10 steps. The wander and
jitter transfer characteristic is shown in Figure 7. Wander
on the local oscillator clock will not have a significant
effect on the output clock whilst in Locked mode, provided
that the DPLL bandwidth is set high enough so that the
DPLL can compensate quickly enough for any frequency
changes in the crystal.
In Free-run or Holdover mode wander on the crystal is
more significant. Variation in crystal temperature or
supply voltage both cause drifts in operating frequency,
as does ageing. These effects must be limited by careful
selection of a suitable component for the local oscillator,
as specified in the section See Local Oscillator Clock.
Phase Build-out
Phase Build-out (PBO) is the function to minimize phase
transients on the output SEC clock during input reference
switching. If the currently selected input reference clock
source is lost (due to a short interruption, out of frequency
detection, or complete loss of reference) the second, next
highest priority reference source will be selected, and a
PBO event triggered.
[11]
DATASHEET
states that the maximum allowable shortITU-T G.813
term phase transient response, resulting from a switch
from one clock source to another, with Holdover mode
entered in between, should be a maximum of 1 µs over a
15 second interval. The maximum phase transient or
jump should be less than 120 ns at a rate of change of
less than 7.5 ppm and the Holdover performance should
be better than 0.05 ppm. The ACS8522 performance is
well within this requirement. The typical phase
disturbance on clock reference source switching will be
less than 5 ns on the ACS8522.
When a PBO event is triggered, the device enters a
temporary Holdover state. When in this temporary state,
the phase of the input reference is measured, relative to
the output. The device then automatically accounts for
any measured phase difference and adds the appropriate
phase offset into the DPLL to compensate. Following a
PBO event, whatever the phase difference on change of
input, the output phase transient is minimized to be no
greater than 5 ns.
On the ACS8522, PBO can be enabled, disabled or frozen
using the serial interface. By default, it is enabled. When
PBO is enabled, PBO can also be frozen (at the current
offset setting). The device will then ignore any further PBO
events occurring on any subsequent reference switch,
and maintain the current phase offset. If PBO is disabled
Figure 7 Sample of Wander and Jitter Measured Transfer Characteristics
Revision 5/November 2006 © Semtech Corp.
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while the device is in the Locked mode, there may be a
phase shift on the output SEC clocks as the DPLL locks
back to 0 degrees phase error. The rate of phase shift will
depend on the programmed bandwidth. Enabling PBO
whilst in the Locked stated will also trigger a PBO event.
PBO Phase Offset
In order to minimize the systematic (average) phase error
for PBO, a PBO Phase Offset can be programmed in
0.101 ns steps in the cnfg_PBO_phase_offset register,
Reg.72. The range of the programmable PBO phase offset
is restricted to ±1.4 ns. This can be used to eliminate an
accumulation of phase shifts in one direction.
Input-to-Output Phase Adjustment
When PBO is off (including Auto-PBO on phase transients),
such that the system always tries to align the outputs to
the inputs at the 0° position, there is a mechanism
provided in the ACS8522 for precise fine tuning of the
output phase position with respect to the input. This can
be used to compensate for circuit and board wiring
delays. The output phase can be adjusted in 6 ps steps up
to 200 ns in a positive or negative direction. The phase
adjustment actually changes the phase position of the
feedback clock so that the DPLL adjusts the output clock
phases to compensate. The rate of change of phase is
therefore related to the DPLL bandwidth. For the DPLL to
track large instant changes in phase, either Lock8k mode
should be on, or the coarse phase detector should be
enabled. Register cnfg_phase_offset at Reg. 70 and 71
controls the output phase, which is only used when PBO is
off (Reg. 48, Bit 2 = 0 and Reg. 76, Bit 4 = 0).
Revision 5/November 2006 © Semtech Corp.
DATASHEET
Input Wander and Jitter Tolerance
The ACS8522 is compliant to the requirements of all
relevant standards, principally ITU Recommendation
G.825[15], ANSI DS1.101-1999[1], Telcordia GR1244[19],
GR253[17], G812[10], G813[11] and ETS 300 462-5
(1996)[4].
All reference clock inputs have a tight frequency tolerance
but a generous jitter tolerance. Pull-in, hold-in and pull-out
ranges are specified in Table 8. Minimum jitter tolerance
masks are specified in Figures 8 and 9, and Tables 8 and
10, respectively. The ACS8522 will tolerate wander and
jitter components greater than those shown in Figure 8
and Figure 9, up to a limit determined by a combination of
the apparent long-term frequency offset caused by
wander and the eye-closure caused by jitter (the input
source will be rejected if the offset pushes the frequency
outside the hold-in range for long enough to be detected,
whilst the signal will also be rejected if the eye closes
sufficiently to affect the signal purity). Either the Lock8k
mode, or one of the extended phase capture ranges
should be engaged for high jitter tolerance according to
these masks.
All reference clock ports are monitored for quality,
including frequency offset and general activity. Single
short-term interruptions in selected reference clocks may
not cause re- arrangements, whilst longer interruptions,
or multiple, short-term interruptions, will cause rearrangements, as will frequency offsets which are
sufficiently large or sufficiently long to cause loss-of-lock
in the phase-locked loop. The failed reference source will
be removed from the priority table and declared as
unserviceable, until its perceived quality has been
restored to an acceptable level.
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DATASHEET
Table 8 Input Reference Source Jitter Tolerance
Jitter Tolerance
Frequency
Monitor
Acceptance
Range
Frequency Acceptance Range
(Pull-in)
Frequency Acceptance Range
(Hold-in)
Frequency Acceptance Range
(Pull-out)
G.703[6]
G.783[9]
±4.6 ppm (see Note (i))
±9.2 ppm (see Note (ii))
±16.6 ppm
G.823[13]
±4.6 ppm (see Note (i))
±9.2 ppm (see Note (ii))
±4.6 ppm (see Note (i))
±9.2 ppm (see Note (ii))
GR-1244-CORE[19]
Notes: (i) The frequency acceptance and generation range will be ±4.6 ppm around the required frequency when the external crystal
frequency accuracy is within a tolerance of ±4.6 ppm.
(ii) The fundamental acceptance range and generation range is ±9.2 ppm with an exact external crystal frequency of 12.800 MHz. This
is the default DPLL range, the range is also programmable from 0 to 80 ppm in 0.08 ppm steps.
Figure 8 Minimum Input Jitter Tolerance (OC-3/STM-1)
A0
A1
A2
A3
A4
Jitter and Wander Frequency (log scale)
f0
f1
f2
f3
f4
f5
f6
f7
f8
f9
F8530_003MINIPJITTOLOC3STM1_02
Note...For inputs supporting G.783[9] compliant sources.)
Table 9 Amplitude and Frequency Values for Jitter Tolerance (OC-3/STM-1)
STM
level
Peak to peak amplitude (unit
Interval)
A0
STM-1
2800
A1
A2
A3
A4
311 39 1.5 0.15
Revision 5/November 2006 © Semtech Corp.
Frequency (Hz)
F0
F1
F2
F3
F4
12 u 178 u 1.6 m 15.6 m 0.125
Page 25
F5
19.3
F6
F7
F8
F9
500 6.5 k 65 k 1.3
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Figure 9 Minimum Input Jitter Tolerance (DS1/E1)
Peak-to-peak Jitter and Wander Amplitude
(log scale)
A1
A2
Jitter and Wander Frequency (log scale)
f1
f2
f3
F8530D_004MINIPJITTOLDS1E1_02
f4
Table 10 Amplitude and Frequency Values for Jitter Tolerance (DS1/E1)
Type
Spec.
Amplitude (UI pk-pk)
A1
Frequency (Hz)
A2
F1
F2
F3
F4
DS1
GR-1244-CORE[19]
5
0.1
10
500
8k
40 k
E1
ITU G.823[13]
1.5
0.2
20
2.4 k
18 k
100
Using the DPLLs for Accurate Frequency and Phase
Reporting
The frequency monitors in the ACS8522 perform
frequency monitoring with a programmable acceptable
limit of up to ±60.96 ppm. The resolution of the
measurement is 3.8 ppm and the measured frequency
can be read back from Reg. 4C, with channel selection at
Reg. 4B. For more accurate measurement of both
frequency and phase, the T0 and T4 DPLLs and their
phase detectors, can be used to monitor both input
frequency and phase. The T0 DPLL is always monitoring
the currently locked to source, but if the T4 path is not
used then the T4 DPLL can be used as a roving phase and
frequency meter. Via software control it could be switched
to monitor each input in turn and both the phase and
frequency can be reported with a very fine resolution.
The registers sts_current_DPLL_frequency (Reg. 0C,
Reg. 0D and Reg. 07) report the frequency of either the
T0 or T4 DPLL with respect to the external crystal XO
frequency (after calibration via Reg. 3C, 3D if used). The
selection of T4 or T0 DPLL reporting is made via Reg. 4B,
Bit 4. The value is a 19-bit signed number with one LSB
representing 0.0003068 ppm (range of ±80 ppm). This
value is actually the integral path value in the DPLL, and
as such corresponds to an averaged measurement of the
Revision 5/November 2006 © Semtech Corp.
input frequency, with an averaging time inversely
proportional to the DPLL bandwidth setting. Reading this
regularly can show how the currently locked source is
varying in value e.g. due to frequency wander on its input.
The input phase, as seen at the DPLL phase detector, can
be read back from register sts_current_phase, Reg. 77
and 78. T0 or T4 DPLL phase detector reporting is again
controlled by Reg. 4B, Bit 4. One LSB corresponds to
approximately 0.7 degrees phase difference. For the T0
DPLL this will be reporting the phase difference between
the input and the internal feedback clock. The phase
result is internally averaged or filtered with a -3 dB
attenuation point at approximately 100 Hz. For low DPLL
bandwidths, 0.1 Hz for example, this measured phase
information from the T0 DPLL gives input phase wander in
the frequency band from for example 0.1 Hz to 100 Hz.
This could be used to give a crude input MTIE
measurement up to an observation period of
approximately 1000 seconds using external software.
In addition, the T4 DPLL phase detector can be used to
make a phase measurement between two inputs.
Reg. 65, Bit 7 is used to switch one input to the T4 phase
detector over to the current T0 input. The other phase
detector input remains connected to the selected T4 input
source, the selected source can be forced via Reg. 35,
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DATASHEET
Bits 3:0, or changed via the T4 priority (Reg. 19 to 1C,
when Reg. 4B, Bit 4 = 1).
MFrSync and 8 kHz FrSync outputs keep their precise
alignment with the other output clocks.
Consequently the phase detector from the T4 DPLL could
be used to measure the phase difference between the
currently selected source and the stand-by source, or it
could be used to measure the phase wander of all standby sources with respect to the current source by selecting
each input in sequence. An MTIE and TDEV calculation
could be made for each input via external processing.
When indep_FrSync/MFrSync Reg. 7B Bit 7 is Low the
FrSyncs and the other higher rate clocks are not
independent and their alignment on the falling 8kHz edge
is maintained. This means that when Bit Sync_OC-N_rates
is High, the OC-N rate dividers and clocks are also
synchronized by the SYNC2K input. On a change of phase
position of the SYNC2K, this could result in a shift in
phase of the 6.48 MHz output clock when a 19.44 MHz
precision is used for the SYNC2K input. To avoid
disturbing any of the output clocks and only align the
MFrSync and FrSync outputs, at the chosen level of
precision, then independent Frame Sync mode can be
used (Reg. 7B, bit 7 = 1). Edge alignment of the FrSync
output with other clocks outputs may then change
depending on the SYNC2K sampling precision used. For
example with a 19.44 MHz reference input clock and
Reg. 7B, bits 6 & 7 both High (independent mode and
Sync OC-N rates), then the FrSync output will still align
with the 19.44 MHz output but not with the 6.48 MHz
output clock.
MFrSync and FrSync Alignment-SYNC2K
The SYNC2K input will normally be a 2 kHz frequency and
only its falling edge is used. It can however be at a
frequencies of 4 kHz or 8 kHz without any change to the
register setups. Only alignment of the 8 kHz will be
achieved in this case.
Safe sampling of the SYNC2K input is achieved by using
the currently selected clock reference source to do the
input sampling. This is based on the principle that FrSync
alignment is being used on a Slave device that is locked
to the clock reference of a Master device that is also
providing the 2 kHz SYNC2K input. Phase Build-out mode
should be off (Reg. 48, Bit 2 = 0). The 2 kHz MFrSync
output from the Master device has its falling edge aligned
with the falling edge of the other output clocks, hence the
SYNC2K input is normally sampled on the rising edge of
the current input reference clock, in order to provide the
most margin. Some modification of the expected timing of
the SYNC2K with respect to the reference clock can be
achieved via Reg. 7B, Bits [1:0]. This allows for the
SYNC2K input to arrive either half a reference clock cycle
early or up to one and a half cycle late, hence allowing a
safe sampling margin to be maintained.
A different sampling resolution is used depending on the
input reference frequency and the setting of Reg. 7B,
cnfg_sync_phase, Bit 6 indep_FrSync/MFrSync. With this
bit Low, the SYNC2K input sampling has a 6.48 MHz
resolution, this being the preferred reference frequency to
lock to from the Master, in conjunction with the SYNC2K
2 kHz, since it gives the most timing margin on the
sampling and aligns all of the higher rate OC-3 derived
clocks. When Bit 6 is High the SYNC2K can have a
sampling resolution of either 19.44 MHz (when the
current locked to reference is 19.44 MHz) or 38.88 MHz
(all other frequencies). This would allow for instance a
19.44 MHz and 2 kHz pair to be used for Slave
synchronization or for Line card synchronization. Reg. 7B
Bit 7, indep_FrSync/MFrSync controls whether the 2 kHz
Revision 5/November 2006 © Semtech Corp.
The FrSync and MFrSync outputs always come from the
T0 DPLL path. 2kHz and 8kHz outputs can also be
produced at the O1 to O4 outputs. These can come from
either the T0 DPLL or from the T4 DPLL, controlled by
Reg. 7A, bit 7.
If required, this allows the T4 DPLL to be used as a
separate PLL for the FrSync and MFrSync path with a
2 kHz input and 2 kHz and 8 kHz Frame Sync outputs.
Output Clock Ports
The device supports a set of main output clocks, O1 to O4
and a pair of secondary Sync outputs, FrSync and
MFrSync. The four main output clocks are independent of
each other and are individually selectable. The two
secondary output clocks, FrSync and MFrSync, are
derived from the T0 path only. The frequencies of the
main output clocks are selectable from a range of predefined spot frequencies, as defined in Table 11. Output
technologies are TTL/CMOS for all outputs except O1
which can be PECL or LVDS.
PECL/LVDS Output Port Selection
The choice of PECL or LVDS compatibility for Output O1 is
programmed via the cnfg_differential_outputs register,
Reg. 3A.
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FINAL
Output Frequency Selection and Configuration
The output frequency of outputs O1 to O4 is controlled by
a number of interdependent parameters. These
parameters control the selections within the various
blocks shown in Figure 10.
The ACS8522 contains two main DPLL/APLL paths, T0
and T4. Whilst they are largely independent, there are a
number of ways in which these two structures can
interact. Figure 10 is an expansion of the top level Block
Diagram (Figure 1) showing the PLL paths in more detail.
T0 DPLL and APLLs
The T0 DPLL always produces 77.76 MHz regardless of
either the reference frequency (frequency at the input pin
of the device) or the locking frequency (frequency at the
input of the DPLL Phase and Frequency Detector (PFD)).
The input reference is either passed directly to the PFD or
via a pre-divider (not shown) to produce the reference
input. The feedback 77.76 MHz is either divided or
synthesized to generate the locking frequency.
Digital Frequency Synthesis (DFS) is a technique for
generating an output frequency using a higher frequency
system clock (204.8 MHz in the case of the 77.76 MHz
synthesis). However, the edges of the output clock are not
ideally placed in time, since all edges of the output clock
will be aligned to the active edge of the system clock. This
will mean that the generated clock will inherently have
jitter on it equivalent to one period of the system clock.
The T0 77M forward DFS block uses DFS clocked by the
204.8 MHz system clock to synthesize the 77.76 MHz
and, therefore, has an inherent 4.9 ns of pk-pk jitter.
There is an option to use an APLL, the T0 feedback APLL,
to filter out this jitter before the 77.76 MHz is used to
generate the feedback locking frequency in the T0
feedback DFS block. This analog feedback option allows
a lower jitter (
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