GS1559 HD-LINX™ II Multi-Rate Deserializer with Loop-Through Cable Driver
Key Features
Description
•
SMPTE 292M and SMPTE 259M-C compliant
descrambling and NRZI →NRZ decoding (with bypass)
•
DVB-ASI 8b/10b decoding
•
Auto-configuration for HD-SDI and SD-SDI
•
Serial loop-through Cable Driver output selectable as
reclocked or non-reclocked
•
Dual serial digital input buffers with 2 x 1 mux
•
Integrated serial digital signal termination
•
Integrated Reclocker
•
Automatic or Manual rate selection/indication
(HD/SD)
•
Descrambler Bypass option
•
User selectable additional processing features
including:
The GS1559 is a reclocking Deserializer with a serial
loop-through Cable Driver. When used in conjunction with
the GS1574 Automatic Cable Equalizer and the
GO1555/GO1525* Voltage Controlled Oscillator, a receive
solution can be realized for HD-SDI, SD-SDI and DVB-ASI
applications.
In addition to reclocking and deserializing the input data
stream, the GS1559 performs NRZI-to-NRZ decoding,
descrambling as per SMPTE 292M/259M-C, and word
alignment when operating in SMPTE mode. When
operating in DVB-ASI mode, the device will word align the
data to K28.5 sync characters and 8b/10b decode the
received stream.
Two serial digital input buffers are provided with a 2x1
Multiplexer to allow the device to select from one of two
serial digital input signals.
The Integrated Reclocker features a very wide Input Jitter
Tolerance of ±0.3 UI (total 0.6 UI), a rapid asynchronous
lock time, and full compliance with DVB-ASI data streams.
An integrated Cable Driver is provided for serial input
loop-through applications and can be selected to output
either buffered or reclocked data. This Cable Driver also
features an output mute on loss of signal, high-impedance
mode, adjustable signal swing, and automatic dual
slew-rate selection depending on HD/SD operational
requirements.
The GS1559 also includes a range of data processing
functions such as error detection and correction, automatic
standards detection, and EDH support. The device can also
detect and extract SMPTE 352M payload identifier packets
and independently identify the received video standard.
This information is read from internal registers via the Host
Interface port.
Line-based CRC errors, line number errors, TRS errors, EDH
CRC errors and ancillary data checksum errors can all be
detected. A single ‘DATA_ERROR’ pin is provided which is
a logical 'OR'ing of all detectable errors. Individual error
status is stored in internal ‘ERROR_STATUS’ registers.
Finally, the device can correct detected errors and insert
new TRS ID words, line-based CRC words, ancillary data
checksum words, EDH CRC words, and line numbers.
Illegal code re-mapping is also available. All processing
functions may be individually enabled or disabled via Host
Interface control.
•
•
•
•
CRC, TRS, ANC data checksum, line number and EDH
CRC error detection and correction
Programmable ANC data detection
Illegal code remapping
Internal Flywheel for noise immune H, V, F extraction
•
FIFO load Pulse
•
20-bit/10-bit CMOS parallel output data bus
•
148.5MHz / 74.25MHz / 27MHz / 13.5MHz parallel
digital output
•
Automatic standards detection and indication
•
1.8V core Power Supply and 3.3V Charge Pump Power
Supply
•
3.3V digital I/O supply
•
JTAG test interface
•
Available in a Pb-free package
•
Small footprint (11mm x 11mm)
Applications
•
SMPTE 292M Serial Digital Interfaces
•
SMPTE 259M-C Serial Digital Interfaces
•
DVB-ASI Serial Digital Interfaces
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
www.gennum.com
1 of 71
*For new designs use the GO1555.
Functional Block Diagram
20bit/10bit
IOPROC_EN/DIS
FW_EN/DIS
F
V
H
DVB_ASI
SMPTE_BYPASS
SD/HD
MASTER/SLAVE
LOCKED
PCLK
RC_BYP
CP_CAP
VCO
VCO
LB_CONT
LF
VCO_VCC
VCO_GND
IP_SEL
CD1
carrier_detect
CD2
rclk_ctrl
pll_lock
LOCK detect
smpte_sync_det
asi_sync_det
TERM 1
DDI_1
DDI_1
Reclocker
SMPTE Descramble, Word
alignment and
flywheel
S->P
TERM 2
DDI_2
Word alignment
and
8b/10b decode
DDI_2
(o/p mute)
pll_lock
rclk_bypass
DATA_ERROR
CRC check
Line number
check
TRS check
CSUM check
ANC data
detection
CRC correct
Line number
correct
TRS correct
CSUM correct
EDH check &
correct
Illegal code remap
DOUT[19:0]
I/O
Buffer
& mux
FIFO_LD
CANC
YANC
SDO_EN/DIS
SDO
SDO
Reset
HOST Interface / JTAG
test
RSET
JTAG/HOST
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
RESET_TRST
GS1559 Functional Block Diagram
Revision History
Version
ECR
PCN
Date
Changes and / or Modifications
8
147971
50711
July 2008
Changed register RASTER_STRUCTURE2 from 12 bits to 13 bits in Table 4-8: Host
Interface Description for Raster Structure Registers. Changed SMPTE 352 Lines from 13
to 10 in Table 4-9: Supported Video Standards. Removed references to DVB_ASI in
Master mode. Updated document to new format.
7
145031
–
May
2007
Updated description of H2 from PDBUFF_GND to EQ_GND in Table 1-1: Pin
Descriptions. Changed GND_EQ to EQ_GND in 5.2 Typical Application Circuit (Part B).
6
143592
42774
January
2007
Added RoHS compliance statement to 7.3 Packaging Data. Recommended GO1555
VCO for new designs.
5
140420
39452
May
2006
Corrected minor typing errors in Functional Block Diagram. Modified video format
numbers for system 1125 on Table 4-4: Switch Line Position for Digital Systems.
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
2 of 71
Contents
Key Features ........................................................................................................................................................1
Applications.........................................................................................................................................................1
Description...........................................................................................................................................................1
Functional Block Diagram ..............................................................................................................................2
Revision History .................................................................................................................................................2
1. Pin Out..............................................................................................................................................................5
1.1 Pin Assignment..................................................................................................................................5
1.2 Pin Descriptions ................................................................................................................................6
2. Electrical Characteristics ........................................................................................................................ 16
2.1 Absolute Maximum Ratings....................................................................................................... 16
2.2 DC Electrical Characteristics ..................................................................................................... 16
2.3 AC Electrical Characteristics ..................................................................................................... 18
3. Input/Output Circuits .............................................................................................................................. 20
3.1 Host Interface Map........................................................................................................................ 22
3.1.1 Host Interface Map (R/W Configurable Registers) ................................................ 23
3.1.2 Host Interface Map (Read Only Registers) ............................................................... 24
4. Detailed Description................................................................................................................................. 25
4.1 Functional Overview.................................................................................................................... 25
4.2 Serial Digital Input ........................................................................................................................ 25
4.2.1 Input Signal Selection ..................................................................................................... 25
4.2.2 Carrier Detect Input......................................................................................................... 26
4.2.3 Single Input Configuration............................................................................................ 26
4.3 Serial Digital Reclocker ............................................................................................................... 26
4.3.1 External VCO ..................................................................................................................... 26
4.3.2 Loop Bandwidth................................................................................................................ 27
4.4 Serial Digital Loop-Through Output........................................................................................ 27
4.4.1 Output Swing ..................................................................................................................... 27
4.4.2 Reclocker Bypass Control .............................................................................................. 28
4.4.3 Serial Digital Output Mute............................................................................................. 28
4.5 Serial-To-Parallel Conversion ................................................................................................... 29
4.6 Modes Of Operation ..................................................................................................................... 29
4.6.1 Lock Detect ......................................................................................................................... 29
4.6.2 Master Mode....................................................................................................................... 30
4.6.3 Slave Mode.......................................................................................................................... 31
4.7 SMPTE Functionality .................................................................................................................... 31
4.7.1 SMPTE Descrambling and Word Alignment ........................................................... 32
4.7.2 Internal Flywheel ............................................................................................................. 32
4.7.3 Switch Line Lock Handling............................................................................................ 33
4.7.4 HVF Timing Signal Generation .................................................................................... 36
4.8 DVB-ASI Functionality ................................................................................................................ 38
4.8.1 DVB-ASI 8b/10b Decoding and Word Alignment................................................. 38
4.8.2 Status Signal Outputs ...................................................................................................... 38
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
3 of 71
4.9 Data Through Mode ...................................................................................................................... 39
4.10 Additional Processing Functions ........................................................................................... 39
4.10.1 FIFO Load Pulse .............................................................................................................. 39
4.10.2 Ancillary Data Detection and Indication ............................................................... 40
4.10.3 SMPTE 352M Payload Identifier ............................................................................... 43
4.10.4 Automatic Video Standard and Data Format Detection................................... 44
4.10.5 Error Detection and Indication.................................................................................. 47
4.10.6 Error Correction and Insertion .................................................................................. 53
4.10.7 EDH Flag Detection ....................................................................................................... 55
4.11 Parallel Data Outputs................................................................................................................. 57
4.11.1 Parallel Data Bus Buffers ............................................................................................. 57
4.11.2 Parallel Output in SMPTE Mode................................................................................ 58
4.11.3 Parallel Output in DVB-ASI Mode............................................................................ 58
4.11.4 Parallel Output in Data-Through Mode.................................................................. 59
4.11.5 Parallel Output Clock (PCLK) ..................................................................................... 59
4.12 GSPI Host Interface..................................................................................................................... 60
4.12.1 Command Word Description ..................................................................................... 61
4.12.2 Data Read and Write Timing ...................................................................................... 61
4.12.3 Configuration and Status Registers.......................................................................... 62
4.13 JTAG................................................................................................................................................. 63
4.14 Device Power Up......................................................................................................................... 64
4.15 Device Reset.................................................................................................................................. 64
5. Application Reference Design .............................................................................................................. 65
5.1 Typical Application Circuit (Part A)......................................................................................... 65
5.2 Typical Application Circuit (Part B) ......................................................................................... 66
6. References & Relevant Standards ........................................................................................................ 67
7. Package & Ordering Information ......................................................................................................... 68
7.1 Package Dimensions..................................................................................................................... 68
7.2 Solder Reflow Profiles.................................................................................................................. 69
7.3 Packaging Data............................................................................................................................... 70
7.4 Ordering Information................................................................................................................... 70
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
4 of 71
1. Pin Out
1.1 Pin Assignment
1
2
3
4
5
6
7
A
LF
VCO_
VCC
VCO_
GND
VCO
VCO
NC
PCLK
IO_VDD DOUT18 DOUT19
B
CP_CAP
CP_VDD
CP_GND
LB_
CONT
NC
NC
FW_EN
/DIS
IO_GND
DOUT16 DOUT17
C
BUFF
_VDD
PD_VDD
PD/BUFF
_GND
NC
NC
YANC
DOUT14 DOUT15
D
DDI1
NC
NC
IP_SEL
CANC
DOUT12 DOUT13
E
DDI1
TERM1
NC
SD/HD
F
CD1
NC
NC
G
DDI2
NC
H
DDI2
J
K
MASTER/
RC_BYP
SLAVE
DVB_ASI LOCKED
NC
8
9
10
CORE
_GND
CORE
_VDD
NC
IO_VDD DOUT10 DOUT11
CORE
_GND
CORE
_VDD
NC
IO_GND
10bit
DOUT8
DOUT9
NC
IOPROC
_EN/DIS
SMPTE_
BYPASS
RESET
_TRST
NC
FIFO_LD
DOUT6
DOUT7
TERM2
NC
CS_
TMS
SCLK
_TCK
SDOUT
_TDO
DATA_
ERROR
H
DOUT4
DOUT5
CD2
NC
NC
NC
SDO_EN
/DIS
SDIN
_TDI
V
IO_GND
DOUT2
DOUT3
RSET
CD_VDD
SDO
SD0
CD_GND
JTAG/
HOST
F
IO_VDD
DOUT0
DOUT1
20bit/
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
5 of 71
1.2 Pin Descriptions
Table 1-1: Pin Descriptions
Pin
Number
Name
Timing
Type
Description
A1
LF
Analog
Output
Control voltage to external Voltage Controlled Oscillator. Nominally
+1.25V DC.
A2
VCO_VCC
–
Output
Power
Power Supply for the external Voltage Controlled Oscillator. Connect to
pin 7 of the GO1555/GO1525*. This pin is an output.
Should be isolated from all other power supplies.
*For new designs use the GO1555.
A3
VCO_GND
–
Output
Power
Ground reference for the external Voltage Controlled Oscillator.
Connect to pins 2, 4, 6, and 8 of the GO1555/GO1525*. This pin is an
output.
Should be isolated from all other grounds.
*For new designs use the GO1555.
A4, A5
VCO, VCO
Analog
Input
Differential inputs for the external VCO reference signal. For single
ended devices such as the GO1555/GO1525*, VCO should be AC
coupled to VCO_GND.
VCO is nominally 1.485GHz.
*For new designs use the GO1555.
A6, B5,
B6, C4,
C5, D2,
D3, D7,
E3, E7, F2,
F3, F7, G2,
G3, G7,
H3, J2, J3,
J4,
NC
–
–
A7
PCLK
–
Output
A8, E8, K8
IO_VDD
–
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
Power
No Connect.
PARALLEL DATA BUS CLOCK
Signal levels are LVCMOS/LVTTL compatible.
HD 20-bit mode
PCLK = 74.25MHz or 74.25/1.001MHz
HD 10-bit mode
PCLK = 148.5MHz or 148.5/1.001MHz
SD 20-bit mode
PCLK = 13.5MHz
SD 10-bit mode
PCLK = 27MHz
Power Supply connection for digital I/O buffers. Connect to +3.3V DC
digital.
6 of 71
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
A10, A9,
B10, B9,
C10, C9,
D10, D9,
E10, E9
DOUT[19:10]
Synchronous
with PCLK
Output
Description
PARALLEL DATA BUS
Signal levels are LVCMOS/LVTTL compatible.
DOUT19 is the MSB and DOUT10 is the LSB.
HD 20-bit mode
SD/HD = LOW
20bit/10bit = HIGH
Luma data output in SMPTE mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data output in Data-Through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
HD 10-bit mode
SD/HD = LOW
20bit/10bit = LOW
Multiplexed Luma and Chroma data
output in SMPTE mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data output in Data-Through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
SD 20-bit mode
SD/HD = HIGH
20bit/10bit = HIGH
Luma data output in SMPTE mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data output in Data-Through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
DVB-ASI data in DVB-ASI mode
SMPTE_BYPASS = LOW
DVB_ASI = HIGH
SD 10-bit mode
SD/HD = HIGH
20bit/10bit = LOW
Multiplexed Luma and Chroma data
output in SMPTE mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data input in data through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
DVB-ASI data in DVB-ASI mode
SMPTE_BYPASS = LOW
DVB_ASI = HIGH
B1
CP_CAP
Analog
Input
PLL lock time constant capacitor connection. Normally connected to
VCO_GND through 2.2nF.
B2
CP_VDD
–
Power
Power supply connection for the Charge Pump. Connect to +3.3V DC
analog.
B3
CP_GND
–
Power
Ground connection for the Charge Pump. Connect to analog GND.
B4
LB_CONT
Analog
Input
Control voltage to set the loop bandwidth of the integrated Reclocker.
Normally connected to VCO_GND through 40kΩ.
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
7 of 71
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
B7
FW_EN/DIS
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable the noise immune Flywheel of the device.
When set HIGH, the internal Flywheel is enabled. This Flywheel is used
in the extraction and generation of TRS timing signals, in automatic
video standards detection, and in manual switch line lock handling.
When set LOW, the internal Flywheel is disabled and TRS correction
and insertion is unavailable.
B8, F8, J8
IO_GND
–
Power
Ground connection for digital I/O buffers. Connect to digital GND.
C1
BUFF_VDD
–
Power
Power Supply connection for the Serial Digital Input buffers. Connect
to +1.8V DC analog.
C2
PD_VDD
–
Power
Power Supply connection for the Phase Detector. Connect to +1.8V DC
analog.
C3
PDBUFF_GND
–
Power
Ground connection for the Phase Detector and Serial Digital Input
buffers. Connect to analog GND.
C6
MASTER/SLAVE
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to determine the input / output selection for the DVB_ASI, SD/HD,
RC_BYP and SMPTE_BYPASS pins.
When set HIGH, the GS1559 is set to operate in Master mode where
SD/HD, RC_BYP and SMPTE_BYPASS become status signal output pins
set by the device. In this mode, the GS1559 will automatically detect,
reclock, deserialize and process SD SMPTE and HD SMPTE input data.
When set LOW, the GS1559 is set to operate in Slave mode where
DVB_ASI, SD/HD, RC_BYP and SMPTE_BYPASS become control signal
input pins. In this mode, the application layer must set these external
device pins for the correct reception of either SMPTE or DVB-ASI data.
Slave mode also supports the reclocking and deserializing of data not
conforming to SMPTE or DVB-ASI streams.
C7
RC_BYP
Non
Synchronous
Input
/Output
CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be an input set by the application layer in Slave mode, and
will be an output set by the device in Master mode.
Master mode (MASTER/SLAVE = HIGH)
The RC_BYP signal will be HIGH only when the device has successfully
locked to a SMPTE compliant input data stream. In this case, the serial
digital loop-through output will be a reclocked version of the input.
The RC_BYP signal will be LOW whenever the input does not conform
to a SMPTE compliant data stream. In this case, the serial digital
loop-through output will be a buffered version of the input.
Slave mode (MASTER/SLAVE = LOW)
When set HIGH, the serial digital output will be a reclocked version of
the input signal regardless of whether the device is in SMPTE, DVB-ASI
or Data-Through mode.
When set LOW, the serial digital output will be a buffered version of
the input signal in all modes.
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
8 of 71
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
C8
YANC
Synchronous
with PCLK
Output
Description
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the presence of ancillary data in the video stream.
HD Mode (SD/HD = LOW)
The YANC signal will be HIGH when the device has detected VANC or
HANC data in the luma video stream and LOW otherwise.
SD Mode (SD/HD = LOW)
For 20-bit demultiplexed data (20bit/10bit = HIGH), the YANC signal
will be HIGH when VANC or HANC data is detected in the Luma video
stream and LOW otherwise.
For 10-bit multiplexed data (20bit/10bit = LOW), the YANC signal will
be HIGH when VANC or HANC data is detected anywhere in the data
stream and LOW otherwise.
D1, E1
DDI1, DDI1
Analog
Input
Differential input pair for serial digital input 1.
D4
IP_SEL
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select DDI1 / DDI1 or DDI2 / DDI2 as the Serial Digital Input
signal, and CD1 or CD2 as the Carrier Detect input signal.
When set HIGH, DDI1 / DDI1 is selected as the Serial Digital Input and
CD1 is selected as the Carrier Detect input signal.
When set LOW, DDI2 / DDI2 Serial Digital Input and CD2 Carrier Detect
input signal is selected.
D5
DVB_ASI
Non
Synchronous
Input /
Output
CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be an input set by the application layer in Slave mode.
This pin and its function are not supported in Master mode.
Slave mode (MASTER/SLAVE = LOW)
When set HIGH in conjunction with SD/HD = HIGH and SMPTE_BYPASS
= LOW, the device will be configured to operate in DVB-ASI mode.
When set LOW, the device will not support the decoding or word
alignment of received DVB-ASI data.
D6
LOCKED
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
The LOCKED signal will be HIGH whenever the device has correctly
received and locked to SMPTE compliant data in SMPTE mode or
DVB-ASI compliant data in DVB-ASI mode.
It will be LOW otherwise.
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
9 of 71
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
D8
CANC
Synchronous
with PCLK
Output
Description
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the presence of ancillary data in the video stream.
HD Mode (SD/HD = LOW)
The CANC signal will be HIGH when the device has detected VANC or
HANC data in the chroma video stream and LOW otherwise.
SD Mode (SD/HD = LOW)
For 20-bit demultiplexed data (20bit/10bit = HIGH), the CANC signal
will be HIGH when VANC or HANC data is detected in the Chroma
video stream and LOW otherwise.
For 10-bit multiplexed data (20bit/10bit = LOW), the CANC signal will
be HIGH when VANC or HANC data is detected anywhere in the data
stream and LOW otherwise.
E2
TERM1
Analog
Input
E4
SD/HD
Non
Synchronous
Input /
Output
Termination for Serial Digital Input 1. AC couple to EQ_GND.
CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be an input set by the application layer in Slave mode, and
will be an output set by the device in Master mode.
Master mode (MASTER/SLAVE = HIGH)
The SD/HD signal will be LOW whenever the received serial digital
signal is 1.485Gb/s or 1.485/1.001Gb/s.
The SD/HD signal will be HIGH whenever the received serial digital
signal is 270Mb/s.
Slave mode (MASTER/SLAVE = LOW)
When set LOW, the device will be configured for the reception of
1.485Gb/s or 1.485/1.001Gb/s signals only and will not lock to any other
serial digital signal.
When set HIGH, the device will be configured for the reception of
270Mb/s signals only and will not lock to any other serial digital signal.
NOTE: When in Slave mode, reset the device after the SD/HD input has
been initially configured, and after each subsequent SD/HD data rate
change.
NOTE: This pin has an internal pull-up resistor of 100K.
E5, F5
CORE_GND
–
Power
Ground connection for the digital core logic. Connect to digital GND.
E6, F6
CORE_VDD
–
Power
Power Supply connection for the digital core logic. Connect to +1.8V
DC digital.
F1
CD1
Non
Synchronous
Input
STATUS SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the presence of a serial digital input signal. Normally
generated by a Gennum automatic cable Equalizer.
When LOW, the serial digital input signal received at the DDI1 and
DDI1 pins is considered valid.
When HIGH, the associated serial digital input signal is considered to
be invalid. In this case, the LOCKED signal is set LOW and all parallel
outputs are muted.
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
10 of 71
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
F4
20bit/10bit
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select the output data bus width in SMPTE or Data-Through
modes. This signal is ignored in DVB-ASI mode.
When set HIGH, the parallel output will be 20-bit demultiplexed data.
When set LOW, the parallel outputs will be 10-bit multiplexed data.
F10, F9,
G10, G9,
H10, H9,
J10, J9,
K10, K9
DOUT[9:0]
Synchronous
with PCLK
Output
PARALLEL DATA BUS
Signal levels are LVCMOS/LVTTL compatible.
DOUT9 is the MSB and DOUT0 is the LSB.
HD 20-bit mode
SD/HD = LOW
20bit/10bit = HIGH
Chroma data output in SMPTE mode
SMPTE_BYPASS =HIGH
DVB_ASI = LOW
Data output in Data-Through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
HD 10-bit mode
SD/HD = LOW
20bit/10bit = LOW
Forced LOW in all modes.
SD 20-bit mode
SD/HD = HIGH
20bit/10bit = HIGH
Chroma data output in SMPTE mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data output in Data-Through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
Forced LOW in DVB-ASI mode
SMPTE_BYPASS = LOW
DVB_ASI = HIGH
SD 10-bit mode
SD/HD = HIGH
20bit/10bit = LOW
G1, H1
DDI2, DDI2
Analog
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
Input
Forced LOW in all modes.
Differential input pair for serial digital input 2.
11 of 71
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
G4
IOPROC_EN/DIS
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable I/O processing features.
When set HIGH, the following I/O processing features of the device are
enabled:
• EDH CRC Error Correction (SD-only)
• ANC Data Checksum Correction
• Line-based CRC Error Correction (HD-only)
• Line Number Error Correction (HD-only)
• TRS Error Correction
• Illegal Code Remapping
To enable a subset of these features, keep IOPROC_EN/DIS HIGH and
disable the individual feature(s) in the IOPROC_DISABLE register
accessible via the Host Interface.
When set LOW, the I/O processing features of the device are disabled,
regardless of whether the features are enabled in the IOPROC_DISABLE
register.
G5
SMPTE_BYPASS
Non
Synchronous
Input /
Output
CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be an input set by the application layer in Slave mode, and
will be an output set by the device in Master mode.
Master mode (MASTER/SLAVE = HIGH)
The SMPTE_BYPASS signal will be HIGH only when the device has
locked to a SMPTE compliant data stream. It will be LOW otherwise.
Slave mode (MASTER/SLAVE = LOW)
When set HIGH in conjunction with DVB_ASI = LOW, the device will be
configured to operate in SMPTE mode. All I/O processing features may
be enabled in this mode.
When set LOW, the device will not support the descrambling, decoding
or word alignment of received SMPTE data. No I/O processing features
will be available.
G6
RESET_TRST
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to reset the internal operating conditions to default settings and
to reset the JTAG test sequence.
Host mode (JTAG/HOST = LOW)
When asserted LOW, all functional blocks will be set to default
conditions and all input and output signals become high-impedance,
including the Serial Digital Outputs SDO and SDO.
Must be set HIGH for normal device operation.
NOTE: When in Slave mode, reset the device after the SD/HD input has
been initially configured, and after each subsequent SD/HD data rate
change.
JTAG test mode (JTAG/HOST = HIGH)
When asserted LOW, all functional blocks will be set to default and the
JTAG test sequence will be held in reset.
When set HIGH, normal operation of the JTAG test sequence resumes.
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
12 of 71
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
G8
FIFO_LD
Synchronous
with PCLK
Output
Description
CONTROL SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used as a control signal for external FIFO(s).
Normally HIGH but will go LOW for one PCLK period at SAV.
H2
TERM2
Analog
Input
Termination for serial digital input 2. AC couple to EQ_GND.
H4
CS_TMS
Synchronous
with
SCLK_TCK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Chip Select/Test Mode Select
Host mode (JTAG/HOST = LOW)
CS_TMS operates as the Host Interface Chip Select, CS, and is active
LOW.
JTAG Test mode (JTAG/HOST = HIGH)
CS_TMS operates as the JTAG Test Mode Select, TMS, and is active
HIGH.
NOTE: If the Host Interface is not being used, tie this pin HIGH.
H5
SCLK_TCK
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Clock/Test Clock.
Host mode (JTAG/HOST = LOW)
SCLK_TCK operates as the Host Interface Burst Clock, SCLK. Command
and data read/write words are clocked into the device synchronously
with this clock.
JTAG Test Mode (JTAG/HOST = HIGH)
SCLK_TCK operates as the JTAG test clock, TCK.
NOTE: If the Host Interface is not being used, tie this pin HIGH.
H6
SDOUT_TDO
Synchronous
with
SCLK_TCK
Output
CONTROL SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Output/Test Data Output
Host mode (JTAG/HOST = LOW)
SDOUT_TDO operates as the Host Interface Serial Digital Output,
SDOUT, used to read status and configuration information from the
internal registers of the device.
JTAG Test Mode (JTAG/HOST = HIGH)
SDOUT_TDO operates as the JTAG test data output, TDO.
H7
DATA_ERROR
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
The DATA_ERROR signal will be LOW when an error within the
received data stream has been detected by the device. This pin is a
logical 'OR'ing of all detectable errors listed in the internal
ERROR_STATUS register.
Once an error is detected, DATA_ERROR will remain LOW until the
start of the next video frame/field, or until the ERROR_STATUS register
is read via the Host Interface.
The DATA_ERROR signal will be HIGH when the received data stream
has been detected without error.
NOTE: It is possible to program which error conditions are monitored
by the device by setting appropriate bits of the ERROR_MASK register
HIGH. All error conditions are detected by default.
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
13 of 71
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
H8
H
Synchronous
with PCLK
Output
Description
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video line containing active video
data. H signal timing is configurable via the H_CONFIG bit of the
IOPROC_DISABLE register accessible via the Host Interface.
Active Line Blanking (H_CONFIG = 0h)
The H signal will be HIGH for the entire Horizontal blanking period,
including the EAV and SAV TRS words, and LOW otherwise. This is the
default setting.
TRS Based Blanking (H_CONFIG = 1h)
The H signal will be HIGH for the entire Horizontal blanking period as
indicated by the H bit in the received TRS ID words, and LOW
otherwise.
J1
CD2
Non
Synchronous
Input
STATUS SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the presence of a serial digital input signal. Normally
generated by a Gennum automatic Cable Equalizer.
When LOW, the serial digital input signal received at the DDI2 and
DDI2 pins is considered valid.
When HIGH, the associated serial digital input signal is considered to
be invalid. In this case, the LOCKED signal is set LOW and all parallel
outputs are muted.
J5
SDO_EN/DIS
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable the serial digital output loop-through stage.
When set LOW, the Serial Digital Output signals SDO and SDO are
disabled and become high-impedance.
When set HIGH, the Serial Digital Output signals SDO and SDO are
enabled.
J6
SDIN_TDI
Synchronous
with
SCLK_TCK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data In/Test Data Input
Host mode (JTAG/HOST = LOW)
SDIN_TDI operates as the Host Interface Serial Digital Input, SDIN, used
to write address and configuration information to the internal
registers of the device.
JTAG Test Mode (JTAG/HOST = HIGH)
SDIN_TDI operates as the JTAG test data input, TDI.
NOTE: If the Host Interface is not being used, tie this pin HIGH.
J7
V
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video field/frame that is used for
Vertical blanking.
The V signal will be HIGH for the entire Vertical blanking period as
indicated by the V bit in the received TRS signals.
The V signal will be LOW for all lines outside of the Vertical blanking
interval.
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
14 of 71
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
K1
RSET
Analog
Input
Used to set the serial digital loop-through output signal amplitude.
Connect to CD_VDD through 281Ω +/- 1% for 800mVp-p single-ended
output swing.
K2
CD_VDD
–
Power
Power Supply connection for the serial digital Cable Driver. Connect to
+1.8V DC analog.
K3, K4
SDO, SDO
Analog
Output
Serial digital loop-through output signal operating at 1.485Gb/s,
1.485/1.001Gb/s, or 270Mb/s.
The slew rate of these outputs is automatically controlled to meet
SMPTE 292M and 259M requirements according to the setting of the
SD/HD pin.
K5
CD_GND
–
Power
Ground connection for the serial digital Cable Driver. Connect to
analog GND.
K6
JTAG/HOST
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select JTAG Test mode or Host Interface mode.
When set HIGH, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are
configured for JTAG boundary scan testing.
When set LOW, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are
configured as GSPI pins for normal Host Interface operation.
K7
F
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the ODD/EVEN field of the video signal.
The F signal will be HIGH for the entire period of field 2 as indicated by
the F bit in the received TRS signals.
The F signal will be LOW for all lines in field 1 and for all lines in
progressive scan systems.
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
15 of 71
2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Parameter
Value/Units
Supply Voltage Core
-0.3V to +2.1V
Supply Voltage I/O
-0.3V to +4.6V
Input Voltage Range (any input)
-2.0V to + 5.25V
Ambient Operating Temperature
-20°C < TA < 85°C
Storage Temperature
-40°C < TSTG < 125°C
ESD Protection On All Pins (see Note 1)
1kV
NOTES:
1. HBM, per JESDA-114B.
2.2 DC Electrical Characteristics
Table 2-1: DC Electrical Characteristics
TA = 0°C to 70°C, unless otherwise specified.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Test
Level
Notes
Operation Temperature
Range
TA
–
0
–
70
°C
3
1
Digital Core Supply Voltage
CORE_VDD
–
1.71
1.8
1.89
V
3
1
Digital I/O Supply Voltage
IO_VDD
–
3.13
3.3
3.47
V
3
1
Charge Pump Supply Voltage
CP_VDD
–
3.13
3.3
3.47
V
3
1
Phase Detector Supply
Voltage
PD_VDD
–
1.71
1.8
1.89
V
3
1
Input Buffer Supply Voltage
BUFF_VDD
–
1.71
1.8
1.89
V
3
1
Cable Driver Supply Voltage
CD_VDD
–
1.71
1.8
1.89
V
3
1
External VCO Supply Voltage
Output
VCO_VCC
–
2.25
–
2.75
V
1
–
+1.8V Supply Current
I1V8
SDO Enabled
–
–
245
mA
3
4
+3.3V Supply Current
I3V3
–
–
–
55
mA
3
5
System
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
16 of 71
Table 2-1: DC Electrical Characteristics (Continued)
TA = 0°C to 70°C, unless otherwise specified.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Test
Level
Notes
Total Device Power
PD
SDO Enabled
–
–
550
mW
3
–
PD
SDO
Disabled
–
–
450
mW
3
–
Input Logic LOW
VIL
–
–
–
0.8
V
4
–
Input Logic HIGH
VIH
–
2.1
–
–
V
4
–
Output Logic LOW
VOL
+8mA
–
0.2
0.4
V
4
–
Output Logic HIGH
VOH
-8mA
IO_VDD
- 0.4
–
–
V
4
–
Input Bias Voltage
VB
–
–
1.45
–
V
1
2
RSET Voltage
VRSET
RSET=281Ω
0.54
0.6
0.66
V
1
3
VCMOUT
75Ω load,
RSET=281Ω,
SD and HD
0.8
1.0
1.2
V
1
–
Digital I/O
Input
Output
Output Common Mode
Voltage
TEST LEVELS
NOTES
1. Production test at room temperature and nominal supply
voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply
voltage with guardbands for supply and temperature ranges
using correlated test.
3. Production test at room temperature and nominal supply
voltage.
4. QA sample test.
5. Calculated result based on Level 1, 2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of
similar product.
9. Indirect test.
1.
2.
3.
4.
5.
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
All DC and AC electrical parameters within specification.
Input common mode is set by internal biasing resistors.
Set by the value of the RSET resistor.
Sum of all 1.8V supplies.
Sum of all 3.3V supplies.
17 of 71
2.3 AC Electrical Characteristics
Table 2-2: AC Electrical Characteristics
TA = 0°C to 70°C, unless otherwise shown
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Test
Level
Notes
IJT
Nominal loop
bandwidth
0.6
–
–
UI
1
1
No data to HD
–
–
468
us
6,7
2
HD to SD
–
–
260
us
6,7
2
System
Serial Digital Input
Jitter Tolerance
Master Mode
Asynchronous Lock
Time
Slave Mode
Asynchronous Lock
Time
Device Latency
Reset Pulse Width
treset
No data to SD
–
–
340
us
6,7
2
SD to HD
–
–
256
us
6,7
2
No data to DVB-ASI
–
–
65
us
6,7
2
No data to HD
–
–
240
us
6,7
2
No data to SD
–
–
197
us
6,7
2
No data to DVB-ASI
–
–
68
us
6,7
2
10-bit SD
–
21
–
PCLK
8
–
20-bit HD
–
19
–
PCLK
8
–
DVB-ASI
–
11
–
PCLK
8
–
–
1
–
–
ms
8
4
–
–
1.485
–
Gb/s
1
–
–
–
1.485/1.001
–
Gb/s
9
–
–
–
270
–
Mb/s
1
–
200
600
1000
mVp-p
1
–
Serial Digital Differential Input
Serial Input Data
Rate
DRDDI
ΔVDDI
Differential with
internal 100Ω input
termination
Serial Output Data
Rate
DRSDO
–
–
1.485
–
Gb/s
1
–
–
–
1.485/1.001
–
Gb/s
9
–
Serial Output Swing
ΔVSDO
RSET = 281Ω
Load = 75Ω
Serial Output Rise
Time
20% ~ 80%
trSDO
Serial Output Fall
Time
20% ~ 80%
tfSDO
Serial Digital Input
Signal Swing
Serial Digital Output
–
–
270
–
Mb/s
1
–
650
800
950
mVp-p
1
–
HD signal
–
–
260
ps
1
–
SD signal
400
550
1500
ps
1
–
HD signal
–
–
260
ps
1
–
SD signal
400
550
1500
ps
1
–
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
18 of 71
Table 2-2: AC Electrical Characteristics (Continued)
TA = 0°C to 70°C, unless otherwise shown
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Test
Level
Notes
Serial Output
Intrinsic Jitter
tIJ
Pseudorandom and
pathological HD
signal
–
90
125
ps
5
3
Pseudorandom and
pathological SD
signal
–
270
350
ps
5
3
Parallel Output
Parallel Clock
Frequency
fPCLK
–
13.5
–
148.5
MHz
4
–
Parallel Clock Duty
Cycle
DCPCLK
–
40
50
60
%
4
–
Output Data Hold
Time
tOH
20-bit HD, 15pF
1.0
–
–
ns
4
–
10-bit SD, 15pF
19.5
–
–
ns
8
–
Output Data Delay
Time
tOD
20-bit HD, 15pF
–
–
4.5
ns
4
–
10-bit SD, 15pF
–
–
22.8
ns
8
–
Output Data Rise/Fall
Time
tr/tf
–
–
–
1.5
ns
3
–
GSPI Input Clock
Frequency
fSCLK
–
–
–
6.6
MHz
8
–
GSPI Input Clock
Duty Cycle
DCSCLK
–
40
–
60
%
8
–
GSPI Input Data
Setup Time
–
–
0
–
–
ns
8
–
GSPI Input Data Hold
Time
–
–
1.43
–
–
ns
8
–
GSPI Output Data
Hold Time
–
–
2.1
–
–
ns
8
–
GSPI Output Data
Delay Time
–
–
–
–
7.27
ns
8
–
GSPI
TEST LEVELS
NOTES
1. Production test at room temperature and nominal supply voltage with
guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with
guardbands for supply and temperature ranges using correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1, 2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar
product.
9. Indirect test.
1.
2.
3.
4.
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
6MHz sinewave modulation.
HD = 1080i, SD = 525i
Serial Digital Output Reclocked (RC_BYP = HIGH).
See Device Reset on page 64, Figure 4-16.
19 of 71
3. Input/Output Circuits
All resistors in ohms, all capacitors in farads, unless otherwise shown.
DDI
VDD
50
45K
TERM
150K
50
DDI
Figure 3-1: Serial Digital Input
VCO
VDD
25
1.5K
5K
25
VCO
Figure 3-2: VCO Input
LB_CONT
865mV
7.2K
Figure 3-3: PLL Loop Bandwidth Control
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
20 of 71
SDO
SDO
Figure 3-4: Serial Digital Output
LF
CP_CAP
300
Figure 3-5: VCO Control Output & PLL Lock Time Capacitor
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
21 of 71
019h
018h
017h
016h
015h
014h
013h
012h
011h
010h
00Fh
00Eh
00Dh
00Ch
00Bh
00Ah
009h
008h
007h
006h
005h
004h
003h
002h
001h
000h
FF_LINE_END_F1
FF_LINE_START_F1
FF_LINE_END_F0
FF_LINE_START_F0
AP_LINE_END_F1
AP_LINE_START_F1
AP_LINE_END_F0
AP_LINE_START_F0
RASTER_STRUCTURE4
RASTER_STRUCTURE3
RASTER_STRUCTURE2
RASTER_STRUCTURE1
VIDEO_FORMAT_OUT_B
VIDEO_FORMAT_OUT_A
EDH_FLAG
ERROR_STATUS
IOPROC_DISABLE
Not Used
Not Used
Not Used
b15
b15
b15
b15
b15
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
VFO4-b7
VFO2-b7
15
Not Used
Not Used
Not Used
ANC-UES
b14
b14
b14
b14
b14
VDS-b4
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
VFO4-b6
VFO2-b6
14
Not Used
Not Used
Not Used
ANC-IDA
b13
b13
b13
b13
b13
VDS-b3
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
VFO4-b5
VFO2-b5
13
Not Used
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
ANC_TYPE5
ANC_TYPE4
ANC_TYPE3
ANC_TYPE2
ANC_TYPE1
VIDEO_STANDARD
ADDRESS
01Ah
REGISTER NAME
ERROR_MASK
3.1 Host Interface Map
Not Used
Not Used
ANC-IDH
b12
b12
b12
b12
b12
VDS-b2
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
VFO4-b4
VFO2-b4
12
Not Used
Not Used
Not Used
ANC-EDA
b11
b11
b11
b11
b11
VDS-b1
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
b11
b11
VFO4-b3
VFO2-b3
11
Not Used
VD_STD_
ERR
Not Used
ANC-EDH
b10
b10
b10
b10
b10
VDS-b0
10
VD_STD_
ERR_
MASK
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
b10
b10
b10
b10
VFO4-b2
VFO2-b2
FF_CRC_
ERR
Not Used
FF-UES
b9
b9
b9
b9
b9
INT_PROG
9
FF_CRC_
ERR_
MASK
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
VFO4-b1
VFO2-b1
AP_CRC_
ERR
H_CONFIG
b8
b8
b8
b8
b8
STD_
LOCK
FF-IDA
8
AP_CRC_
ERR_
MASK
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
VFO4-b0
VFO2-b0
LOCK_
ERR
Not Used
FF-IDH
b7
b7
b7
b7
b7
CDF-b3
7
LOCK_
ERR_
MASK
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
VFO3-b7
VFO1-b7
Not Used
CCS_ERR
FF-EDA
b6
b6
b6
b6
b6
CDF-b2
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
VFO3-b6
VFO1-b6
6
CCS_ERR_MA
SK
ILLEGAL_RE
MAP
YCS_ERR
FF-EDH
b5
b5
b5
b5
b5
CDF-b1
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
VFO3-b5
VFO1-b5
5
YCS_ERR_MA
SK
CCRC_
ERR
EDH_CRC_IN
S
AP-UES
b4
b4
b4
b4
b4
CDF-b0
4
CCRC_
ERR_
MASK
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
VFO3-b4
VFO1-b4
YCRC_
ERR
ANC_
CSUM_INS
AP-IDA
b3
b3
b3
b3
b3
YDF-b3
3
YCRC_
ERR_
MASK
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
VFO3-b3
VFO1-b3
CRC_INS
LNUM_ERR
AP-IDH
b2
b2
b2
b2
b2
YDF-b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
VFO3-b2
VFO1-b2
2
LNUM_ERR_
MASK
TRS_INS
EAV_ERR
AP-EDH
b0
b0
b0
b0
b0
YDF-b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
VFO3-b0
VFO1-b0
0
EAV_ERR_M
ASK
22 of 71
LNUM_ INS
SAV_ERR
AP-EDA
b1
b1
b1
b1
b1
YDF-b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
VFO3-b1
VFO1-b1
1
SAV_ERR_M
ASK
019h
018h
017h
016h
015h
014h
013h
012h
011h
010h
00Fh
00Eh
00Dh
00Ch
00Bh
00Ah
009h
008h
007h
006h
005h
004h
003h
002h
001h
000h
FF_LINE_END_F1
FF_LINE_START_F1
FF_LINE_END_F0
FF_LINE_START_F0
AP_LINE_END_F1
AP_LINE_START_F1
AP_LINE_END_F0
AP_LINE_START_F0
b15
b15
b15
b15
b15
15
b14
b14
b14
b14
b14
14
b13
b13
b13
b13
b13
13
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
IOPROC_DISABLE
ANC_TYPE5
ANC_TYPE4
ANC_TYPE3
ANC_TYPE2
ANC_TYPE1
ADDRESS
01Ah
REGISTER NAME
ERROR_MASK
b12
b12
b12
b12
b12
12
b11
b11
b11
b11
b11
11
b10
b10
b10
b10
b10
b9
b9
b9
b9
b9
9
FF_CRC_
ERR_
MASK
b9
b9
b9
b9
b9
b9
b9
b9
10
VD_STD_
ERR_
MASK
3.1.1 Host Interface Map (R/W Configurable Registers)
8
H_CONFIG
b8
b8
b8
b8
b8
AP_CRC_
ERR_
MASK
b8
b8
b8
b8
b8
b8
b8
b8
7
b7
b7
b7
b7
b7
LOCK_
ERR_
MASK
b7
b7
b7
b7
b7
b7
b7
b7
6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
CCS_ERR_MA
SK
5
ILLEGAL_RE
MAP
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
YCS_ERR_MA
SK
4
EDH_CRC_IN
S
b4
b4
b4
b4
b4
CCRC_
ERR_
MASK
b4
b4
b4
b4
b4
b4
b4
b4
3
ANC_
CSUM_INS
b3
b3
b3
b3
b3
YCRC_
ERR_
MASK
b3
b3
b3
b3
b3
b3
b3
b3
2
CRC_INS
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
LNUM_ERR_
MASK
1
0
TRS_INS
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
EAV_ERR_M
ASK
23 of 71
LNUM_ INS
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
SAV_ERR_M
ASK
000h
003h
002h
001h
ADDRESS
01Ah
019h
018h
017h
016h
015h
014h
013h
012h
011h
010h
00Fh
00Eh
00Dh
00Ch
00Bh
00Ah
009h
008h
007h
006h
005h
004h
VFO4-b7
VFO2-b7
15
ANC-UES
VDS-b4
VFO4-b6
VFO2-b6
14
ANC-IDA
VDS-b3
VFO4-b5
VFO2-b5
13
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
ERROR_STATUS
EDH_FLAG
VIDEO_STANDARD
RASTER_STRUCTURE4
RASTER_STRUCTURE3
RASTER_STRUCTURE2
RASTER_STRUCTURE1
VIDEO_FORMAT_OUT_B
VIDEO_FORMAT_OUT_A
REGISTER NAME
ANC-IDH
VDS-b2
VFO4-b4
VFO2-b4
12
ANC-EDA
VDS-b1
b11
b11
VFO4-b3
VFO2-b3
11
VD_STD_
ERR
ANC-EDH
VDS-b0
b10
b10
b10
b10
VFO4-b2
VFO2-b2
10
3.1.2 Host Interface Map (Read Only Registers)
FF_CRC_
ERR
FF-UES
INT_PROG
b9
b9
b9
b9
VFO4-b1
VFO2-b1
9
AP_CRC_
ERR
STD_
LOCK
FF-IDA
b8
b8
b8
b8
VFO4-b0
VFO2-b0
8
LOCK_
ERR
FF-IDH
CDF-b3
b7
b7
b7
b7
VFO3-b7
VFO1-b7
7
CCS_ERR
FF-EDA
CDF-b2
b6
b6
b6
b6
VFO3-b6
VFO1-b6
6
YCS_ERR
FF-EDH
CDF-b1
b5
b5
b5
b5
VFO3-b5
VFO1-b5
5
CCRC_
ERR
AP-UES
CDF-b0
b4
b4
b4
b4
VFO3-b4
VFO1-b4
4
YCRC_
ERR
AP-IDA
YDF-b3
b3
b3
b3
b3
VFO3-b3
VFO1-b3
3
LNUM_ERR
AP-IDH
YDF-b2
b2
b2
b2
b2
VFO3-b2
VFO1-b2
2
EAV_ERR
AP-EDH
YDF-b0
b0
b0
b0
b0
VFO3-b0
VFO1-b0
0
24 of 71
SAV_ERR
AP-EDA
YDF-b1
b1
b1
b1
b1
VFO3-b1
VFO1-b1
1
4. Detailed Description
4.1 Functional Overview
The GS1559 is a multi-rate reclocking Deserializer with an integrated serial digital
loop-through output. When used in conjunction with the multi-rate GS1574 Adaptive
Cable Equalizer and the external GO1555/GO1525* Voltage Controlled Oscillator, a
receive solution at 1.485Gb/s, 1.485/1.001Gb/s or 270Mb/s is realized.
The device has two basic modes of operation which determine precisely how SMPTE or
DVB-ASI compliant input data streams are reclocked and processed.
In Master mode, (MASTER/SLAVE = HIGH), the GS1559 will automatically detect,
reclock, deserialize and process SD SMPTE 259M-C or HD SMPTE 292M input data.
In Slave mode, (MASTER/SLAVE = LOW), the application layer must set external device
pins for the correct reception of either SMPTE or DVB-ASI data. Slave mode also
supports the reclocking and deserializing of data not conforming to SMPTE or DVB-ASI
streams.
The provided serial loop-through outputs may be selected as either buffered or
reclocked versions of the input signal, and feature a high-impedance mode, output mute
on loss of signal and adjustable signal swing.
In the digital signal processing core, several data processing functions are implemented,
including error detection and correction, and automatic video standards detection.
These features are all enabled by default, but may be individually disabled via internal
registers accessible through the GSPI Host Interface.
Finally, the GS1559 contains a JTAG interface for boundary scan test implementations.
*For new designs use the GO1555.
4.2 Serial Digital Input
The GS1559 contains two current mode differential serial digital input buffers, allowing
the device to be connected to two SMPTE 259M-C or 292M compliant input signals.
Both input buffers have internal 50Ω termination resistors which are connected to
ground via the TERM1 and TERM2 pins. The input common mode level is set by internal
biasing resistors such that the serial digital input signals must be AC coupled into the
device. Gennum recommends using a capacitor value of 4.7μF to accommodate
pathological signals.
The input buffers use a separate power supply of +1.8V DC supplied via the BUFF_VDD
and PDBUFF_GND pins.
4.2.1 Input Signal Selection
A 2x1 input Multiplexer is provided to allow the application layer to select between the
two serial digital input streams using a single external pin. When IP_SEL is set HIGH,
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
25 of 71
serial digital input 1 (DDI1 / DDI1) is selected as the input to the GS1559's reclocker
stage. When IP_SEL is set LOW, serial digital input 2 (DDI2 / DDI2) is selected.
4.2.2 Carrier Detect Input
For each of the differential inputs, an associated Carrier Detect input signal is included,
(CD1 and CD2). These signals are generated by Gennum's family of automatic cable
Equalizers.
When LOW, CDx indicates that a valid serial digital data stream is being delivered to the
GS1559 by the Equalizer. When HIGH, the serial digital input to the device should be
considered invalid. If no Equalizer precedes the device, the application layer should set
CD1 and CD2 accordingly.
A 2x1 input Multiplexer is also provided for these signals. The internal
CARRIER_DETECT signal is determined by the setting of the IP_SEL pin and is used by
the lock detect block of the GS1559 to determine the lock status of the device, (see Lock
Detect on page 29).
4.2.3 Single Input Configuration
If the application requires a single differential input, the DDI pin for the second set of
inputs and the associated carrier detect should be tied HIGH. The DDI pin may be left
unconnected, and the termination pin should be AC terminated to ground.
4.3 Serial Digital Reclocker
The output of the 2x1 serial digital input Multiplexer passes to the GS1559's internal
reclocker stage. The function of this block is to lock to the input data stream, extract a
clean clock, and retime the serial digital data to remove high frequency jitter.
The Reclocker was designed with a 'hexabang' Phase and Frequency Detector. That is,
the PFD used can identify six 'degrees' of phase/frequency misalignment between the
input data stream and the clock signal provided by the VCO, and correspondingly signal
the Charge Pump to produce six different control voltages. This results in fast and
accurate locking of the PLL to the data stream.
In Master mode, the operating center frequency of the Reclocker is toggled between
270Mb/s and 1.485Gb/s by the Lock Detect block, (see Lock Detect on page 29). In Slave
mode, however, the center frequency is determined entirely by the SD/HD input control
signal set by the application layer.
If lock is achieved, the Reclocker provides an internal PLL_LOCK signal to the Lock
Detect block of the device.
4.3.1 External VCO
The GS1559 requires the external GO1555/GO1525* Voltage Controlled Oscillator as
part of the reclocker's phase-locked loop. This external VCO implementation was
chosen to ensure high quality reclocking.
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
26 of 71
Power for the external VCO is generated entirely by the GS1559 from an integrated
voltage regulator. The internal regulator uses +3.3V DC supplied via the
CP_VDD/CP_GND pins to provide +2.5V DC on the VCO_VCC/VCO_GND pins.
The control voltage to the VCO is output from the GS1559 on the LF pin and requires
4.7kΩ pull-up and pull-down resistors to ensure correct operation.
The GO1555/GO1525* produces a 1.485GHz reference signal for the Reclocker, input
on the VCO pin of the GS1559. Both LF and VCO signals should be referenced to the
supplied VCO_GND as shown in the recommended application circuit of Typical
Application Circuit (Part A) on page 65.
*For new designs use the GO1555.
4.3.2 Loop Bandwidth
The loop bandwidth of the integrated Reclocker is nominally 1.4MHz, but may be
increased or decreased via the LB_CONT pin. It is recommended that this pin be
connected to VCO_GND through 39.2kΩ to maximize the input jitter tolerance of the
device.
4.4 Serial Digital Loop-Through Output
The GS1559 contains an integrated current mode differential serial digital Cable Driver
with automatic slew rate control. When enabled, this serial digital output provides an
active loop-through of the input signal.
The integrated Cable Driver uses a separate power supply of +1.8V DC supplied via the
CD_VDD and CD_GND pins.
To enable the loop-through output, SDO_EN/DIS must be set HIGH by the application
layer. Setting the SDO_EN/DIS signal LOW will cause the SDO and SDO output pins to
become high-impedance, resulting in reduced device power consumption.
When not using the serial digital output from the GS1559, the SDO and SDO pins should
be left unconnected (floating). In addition, the SDO_EN pin should be set LOW and the
RSET pin may be AC terminated to analog ground through a 10nF capacitor.
Gennum recommends using the GS1528A SDI Dual Slew-Rate Cable Driver to meet
SMPTE specifications.
4.4.1 Output Swing
Nominally, the voltage swing of the serial digital loop-through output is 800mVp-p
single-ended into a 75Ω load. This is set externally by connecting the RSET pin to
CD_VDD through 281Ω.
The loop-through output swing may be decreased by increasing the value of the RSET
resistor. The relationship is approximated by the curve shown in Figure 4-1.
Alternatively, the serial digital output can drive 800mVp-p into a 50Ω load. Since the
output swing is reduced by a factor of approximately one third when the smaller load is
used, the RSET resistor must be 187Ω to obtain 800mVp-p.
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
27 of 71
1000
900
DVSDO(mVp-p)
800
700
600
500
400
300
250
300
350
400
450
500
550
600
650
700
750
RSET(W)
Figure 4-1: Serial Digital Loop-Through Output Swing
4.4.2 Reclocker Bypass Control
The serial digital loop-through output may be either a buffered version of the serial
digital input signal, or a reclocked version of that signal.
When operating in Slave mode, the application layer may choose the reclocked output
by setting RC_BYP to logic HIGH. If RC_BYP is set LOW, the data stream will bypass the
internal Reclocker and the serial digital output will be a buffered version of the input.
When operating in Master mode, the device will assert the RC_BYP pin HIGH only when
it has successfully locked to a SMPTE input data stream, (see Lock Detect on page 29). In
this case, the serial digital loop-through output will be a reclocked version of the input.
4.4.3 Serial Digital Output Mute
The GS1559 will automatically mute the serial digital loop-through output in both
Master and Slave modes when the internal CARRIER_DETECT signal indicates an
invalid serial input.
The loop-through output will also be muted in Slave mode when SDO/SDO is selected
as reclocked, (RC_BYP = HIGH), but the Lock Detect block has failed to lock to the data
stream, (LOCKED = LOW).
Table 4-1 summarizes the possible states of the serial digital loop-through output data
stream.
Table 4-1: Serial Digital Loop-Through Output Status
SLAVE MODE
SDO
CD
LOCKED
RC_BYP
(INPUT)
RECLOCKED
LOW
HIGH
HIGH
BUFFERED
LOW
X
LOW
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
28 of 71
Table 4-1: Serial Digital Loop-Through Output Status
MUTED
LOW
LOW
HIGH
MUTED
HIGH
LOW*
X
CD
LOCKED
RC_BYP
(OUTPUT)
RECLOCKED
LOW
HIGH
HIGH
BUFFERED
LOW
LOW
LOW
MUTED
HIGH
LOW*
LOW
MASTER MODE
SDO
*NOTE: LOCKED = HIGH if and only if CD = LOW
4.5 Serial-To-Parallel Conversion
The retimed data and phase-locked clock signals from the Reclocker are fed to the
serial-to-parallel converter. The function of this block is to extract 10-bit or 20-bit
parallel data words from the reclocked serial data stream and present them to the
SMPTE and DVB-ASI word alignment blocks simultaneously.
4.6 Modes Of Operation
The GS1559 has two basic modes of operation which determine how the Lock Detect
block controls the integrated Reclocker. Master mode is enabled when the application
layer sets the MASTER/SLAVE pin HIGH, and Slave mode is enabled when
MASTER/SLAVE is set LOW.
4.6.1 Lock Detect
The Lock Detect block controls the center frequency of the integrated Reclocker to
ensure lock to the received serial digital data stream is achieved, and indicates via the
LOCKED output pin that the device has detected the appropriate sync words. In
Data-Through mode, the detection for appropriate sync words is turned off. The
LOCKED pin is an indication of analog lock.
Lock Detection is a continuous process, which begins at device power-up or after a
system reset, and continues until the device is powered-down or held in reset.
The lock detection algorithm first determines if a valid serial digital input signal has
been presented to the device by sampling the internal CARRIER_DETECT signal. As
described in Carrier Detect Input on page 26, this signal will be LOW when a good serial
digital input signal has been detected.
If the CARRIER_DETECT signal is HIGH, the serial data into the device is considered
invalid, and the VCO frequency will be set to the center of the pull range. The LOCKED
pin will be LOW and all outputs of the device except for the PCLK output will be muted.
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
29 of 71
Instead, the PCLK output frequency will operate within +/-3% of the rates shown in
Table 4-16 of Parallel Output Clock (PCLK) on page 59.
NOTE: When the device is operating in DVB-ASI slave mode, the parallel outputs will not
mute when the CARRIER_DETECT signal is HIGH. The LOCKED signal will function
normally.
If a valid input signal has been detected, and the device is in Master mode, the lock
algorithm will enter a hunt phase where four attempts are made to detect the presence
of SMPTE TRS sync words. At each attempt, the center frequency of the reclocker will
be toggled between 270Mb/s and 1.485Gb/s.
Assuming that a valid SMPTE signal has been applied to the device, asynchronous lock
times will be as listed in Table 2-2.
In Slave mode, the application layer fixes the center frequency of the Reclocker such
that the lock algorithm will attempt to lock within the single data rate determined by the
setting of the SD/HD pin. Asynchronous lock times are also listed in Table 2-2.
NOTE: The PCLK output will continue to operate during the Lock Detection process. The
frequency may toggle between 148MHz and 27MHz when the 20bit/10bit pin is set
LOW, or between 74MHz and 13.5MHz when 20bit/10bit is set HIGH.
For SMPTE inputs, the Lock Detect block will only assert the LOCKED output signal
HIGH if (1) the Reclocker has locked to the input data stream as indicated by the internal
PLL_LOCK signal, and (2) TRS sync words have been correctly identified.
When Reclocker lock as indicated by the internal PLL_LOCK signal is achieved in this
mode, one of the following will occur:
1. In Slave mode, data will be passed directly to the parallel outputs without any
further processing taking place and the LOCKED signal will be asserted HIGH if and
only if the SMPTE_BYPASS and DVB_ASI input pins are set LOW; or
2. In Master mode, the LOCKED signal will be asserted LOW, the parallel outputs will
be latched to logic LOW, and the SMPTE_BYPASS output signal will also be set LOW.
4.6.2 Master Mode
Recall that the GS1559 is said to be in master mode when the MASTER/SLAVE input
signal is set HIGH. In this case, the following three device pins become output status
signals:
•
SMPTE_BYPASS
•
SD/HD
•
RC_BYP
The combined setting of these three pins will indicate whether the device has locked to
valid SMPTE data at SD or HD rates. DVB_ASI functionality is not supported in Master
mode. Table 4-2 shows the possible combinations.
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
30 of 71
4.6.3 Slave Mode
The GS1559 is said to be in Slave mode when the MASTER/SLAVE input signal is set
LOW. In this case, the device pins listed in Master Mode on page 30, in addition to the
DVB_ASI pin, become input control signals.
It is required that the application layer set the inputs to reflect the appropriate input data
format (SMPTE_BYPASS, DVB_ASI, and SD/HD). If just one of these three is configured
incorrectly, the device will not lock to the input data stream, and the DATA_ERROR pin
will be set LOW.
The input signal RC_BYP allows the application layer to determine whether the serial
digital loop-through output will be a reclocked or buffered version of the input, (see
Reclocker Bypass Control on page 28). Table 4-3 shows the required settings for various
input formats.
Table 4-2: Master Mode Output Status Signals
FORMAT
PIN SETTINGS
SMPTE_BYPASS
SD/HD
RC_BYP
HD SMPTE
HIGH
LOW
HIGH
SD SMPTE
HIGH
HIGH
HIGH
NOT SMPTE*
LOW
HIGH OR LOW
LOW
*NOTE: When the device locks to the data stream in PLL lock mode, the parallel outputs will
be latched LOW, and the serial loop-through output will be a buffered version of the input.
Table 4-3: Slave Mode Input Control Signals
FORMAT
PIN SETTINGS
SMPTE_BYPASS
DVB_ASI
SD/HD
HD SMPTE
HIGH
LOW
LOW
SD SMPTE
HIGH
LOW
HIGH
DVB-ASI
LOW
HIGH
HIGH
NOT SMPTE OR
DVB-ASI*
LOW
LOW
HIGH OR LOW
*NOTE: See Data Through Mode on page 39 for a complete description of Data Through
mode.
4.7 SMPTE Functionality
The GS1559 is said to be in SMPTE mode once the device has detected SMPTE TRS sync
words and locked to the input data stream as described in Lock Detect on page 29. The
device will remain in SMPTE mode until such time that SMPTE TRS sync words fail to be
detected.
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
31 of 71
The Lock Detect block may also drop out of SMPTE mode under the following
conditions:
•
RESET_TRST is asserted LOW
•
CDx is HIGH
•
SMPTE_BYPASS is asserted LOW in Slave mode
•
DVB_ASI is asserted HIGH in Slave mode
TRS word detection is a continuous process and both 8-bit and 10-bit TRS words will be
identified by the device in both SD and HD modes.
In Master mode, the GS1559 sets the SMPTE_BYPASS pin HIGH to indicate that it has
locked to a SMPTE input data stream. When operating in Slave mode, the application
layer must assert the DVB_ASI pin LOW and the SMPTE_BYPASS pin HIGH in order to
enable SMPTE operation.
4.7.1 SMPTE Descrambling and Word Alignment
After serial-to-parallel conversion, the internal 10-bit or 20-bit data bus is fed to the
SMPTE Descramble and Word Alignment block. The function of this block is to carry out
NRZI-to-NRZ decoding, descrambling according to SMPTE 259M or 292M, and word
alignment of the data to the TRS sync words.
Word alignment occurs when two consecutive valid TRS words (SAV and EAV inclusive)
with the same bit alignment have been detected.
In normal operation, re-synchronization of the word alignment process will only take
place when two consecutive identical TRS word positions have been detected. When
automatic or manual switch line lock handling is 'actioned', (see Switch Line Lock
Handling on page 33), word alignment re-synchronization will occur on the next
received TRS code word.
4.7.2 Internal Flywheel
The GS1559 has an internal Flywheel which is used in the generation of
internal/external timing signals, in the detection and correction of certain error
conditions and in automatic video standards detection. It is only operational in SMPTE
mode.
The Flywheel consists of a number of counters and comparators operating at video pixel
and video line rates. These counters maintain information about the total line length,
active line length, total number of lines per field/frame, and total active lines per
field/frame for the received video stream.
The Flywheel 'learns' the video standard by timing the horizontal and vertical reference
information contained in the TRS ID words of the received video stream. Full
synchronization of the Flywheel to the received video standard therefore requires one
complete video frame.
Once synchronization has been achieved, the Flywheel will continue to monitor the
received TRS timing information to maintain synchronization.
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
32 of 71
The FW_EN/DIS input pin controls the synchronization mechanism of the Flywheel.
When this input signal is LOW, the Flywheel will re-synchronize all pixel and line based
counters on every received TRS ID word.
When FW_EN/DIS is held HIGH, re-synchronization of the pixel and line based counters
will only take place when a consistent synchronization error has been detected. Two
consecutive video lines with identical TRS timing different to the current Flywheel
timing must occur to initiate re-synchronization of the counters. This provides a
measure of noise immunity to internal and external timing signal generation.
The Flywheel will be disabled should the LOCKED signal or the RESET_TRST signal be
LOW. A LOW to HIGH transition on either signal will cause the Flywheel to re-acquire
synchronization on the next received TRS word, regardless of the setting of the
FW_EN/DIS pin.
4.7.3 Switch Line Lock Handling
The principal of Switch Line Lock Handling is that the switching of synchronous video
sources will only disturb the horizontal timing and alignment of the stream, whereas the
vertical timing remains in synchronization.
To account for the horizontal disturbance caused by a synchronous switch, it is
necessary to re-synchronize the Flywheel immediately after the switch has taken place.
Rapid re-synchronization of the GS1559 to the new video standard can be achieved by
controlling the Flywheel using the FW_EN/DIS pin.
At every PCLK cycle the device samples the FW_EN/DIS pin. When a logic LOW to HIGH
transition at this pin is detected anywhere within the active line, the Flywheel will
re-synchronize immediately to the next TRS word. This is shown in Figure 4-2.
To ensure Switch Line Lock Handling, the FW_EN/DIS signal should be LOW for a
minimum of one PCLK cycle (maximum one video line) anywhere within the active
portion of the line on which the switch has taken place.
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
33 of 71
Switch point
Video source 1
EAV
ANC
EAV
Video source 2
SAV
ANC
SAV
ACTIVE PICTURE
EAV
ACTIVE PICTURE
ANC
EAV
ANC
SAV EAV
ACTIVE PICTURE
ANC
SAV EAV
EAV
ACTIVE PICTURE
ANC
ANC
EAV
SAV
ANC
ACTIVE PICTURE
EAV
ANC
SAV
SAV
ACTIVE PICTURE
EAV
ANC
SAV
switch video source 1 to 2
DATA IN
EAV
ANC
SAV
ACTIVE PICTURE
EAV
ANC
SAV
ACTIVE PICTURE
ANC
EAV
ANC
SAV
ACTIVE PICTURE
EAV
ANC
SAV
DATA OUT
EAV
ANC
SAV
ACTIVE PICTURE
EAV
ANC
SAV
ACTIVE PICTURE
ANC
EAV
ANC
SAV
ACTIVE PICTURE
EAV
ANC
SAV
Flywheel TRS
position
FW_EN/DIS
Flywheel re-synch
Switch point
Video source 1
EAV
ANC
SAV
ACTIVE PICTURE
EAV
ANC
SAV EAV
ACTIVE PICTURE
ANC
EAV
ACTIVE PICTURE
ANC
ANC
EAV
SAV
ANC
SAV
ACTIVE PICTURE
ACTIVE PICTURE
EAV
EAV
ANC
ANC
SAV
Video source 2
EAV
ANC
SAV
ACTIVE PICTURE
EAV
ANC
SAV EAV
SAV
DATA IN
EAV
ANC
SAV
ACTIVE PICTURE
EAV
ANC
SAV
ACTIVE PICTURE
EAV
ANC
SAV
ACTIVE PICTURE
EAV
ANC
SAV
DATA OUT
EAV
ANC
SAV
ACTIVE PICTURE
EAV
ANC
SAV
ACTIVE PICTURE
EAV
ANC
SAV
ACTIVE PICTURE
EAV
ANC
SAV
switch video source 2 to 1
Flywheel TRS
position
FW_EN/DIS
Flywheel re-synch
Figure 4-2: Switch Line Locking
The ability to manually re-synchronize the Flywheel is also important when switching
asynchronous sources or to implement other non-standardized video switching
functions.
The GS1559 also implements automatic Switch Line Lock handling. By utilizing the
synchronous switch points defined by SMPTE RP168 for all major video standards with
the automatic video standards detect function, the device automatically
re-synchronizes the Flywheel at the switch point.
This function will occur regardless of the setting of the FW_EN/DIS pin.
The Switch Line is defined as follows:
•
For 525 line interlaced systems: re-sync takes place at the end of lines 10 & 273.
•
For 525 line progressive systems: re-sync takes place at the end of line 10.
•
For 625 line interlaced systems: re-sync takes place at the end of lines 6 & 319.
•
For 625 line progressive systems: re-sync takes place at the end of line 6.
•
For 750 line progressive systems: re-sync takes place at the end of line 7.
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
34 of 71
•
For 1125 line interlaced systems: re-sync takes place at the end of lines 7 & 568.
•
For 1125 line progressive systems: re-sync takes place at the end of line 7.
A full list of all major video standards and switching lines is shown in Table 4-4.
NOTE 1: The Flywheel timing will define the line count such that the line numbers
shown in Table 4-4 may not correspond directly to the digital line counts.
NOTE 2: Unless indicated by SMPTE 352M Payload Identifier Packets, the GS1559 will
not distinguish between 50/60 frames PsF and 25/30 frames interlaced for the 1125 line
video systems; 24 PsF will be identified.
Table 4-4: Switch Line Position for Digital Systems
System
Video Format
Sampling
Signal
Standard
Parallel
Interface
Serial
Interface
Switch Line
No.
HD-SDTI
1920x1080 (PsF)
4:2:2
274M
274M + 348M
292M
7
1920x1080 (2:1)
4:2:2
274M
274M + 348M
292M
7, 569
1280x720 (1:1)
4:2:2
296M
296M + 348M
292M
7
720x576/50 (2:1)
4:2:2
BT.656
BT.656 + 305M
259M
6, 319
720x483/59.94 (2:1)
4:2:2
125M
125M + 305M
259M
10, 273
1280x720/60 (1:1)
4:2:2
296M
296M
296M
7
1280x720/50 (1:1)
4:2:2
296M
296M
296M
7
1280x720/30 (1:1)
4:2:2
296M
296M
296M
7
1280x720/25 (1:1)
4:2:2
296M
296M
296M
7
1280x720/24 (1:1)
4:2:2
296M
296M
296M
7
1920x1080/30 (PsF)
4:2:2
274M + RP211
274M + RP211
292M
7
1920x1080/25 (PsF)
4:2:2
274M + RP211
274M + RP211
292M
7
1920x1080/24 (PsF)
4:2:2
274M + RP211
274M + RP211
292M
7
1920x1080/60 (2:1)
4:2:2
274M + RP211
274M + RP211
292M
7, 569
1920x1080/50 (2:1)
4:2:2
274M + RP211
274M + RP211
292M
7, 569
960x483/59.94 (2:1)
4:2:2
267M
349M
292M
10, 273
960x483/59.94 (2:1)
4:2:2
267M
267M
259M
10, 273
720x483/59.94 (2:1)
4:4:4:4
267M
349M
292M
10, 273
720x483/59.94 (2:1)
4:4:4:4
267M
347M
344M
10, 273
720x483/59.94 (2:1)
4:4:4:4
267M
RP174
344M
10, 273
720x483/59.94 (2:1)
4:4:4:4
267M
RP175
RP175
10, 273
720x483/59.94 (2:1)
4:2:2
125M
349M
292M
10, 273
720x483/59.94 (2:1)
4:2:2
125M
125M
259M
10, 273
720x483/59.94 (1:1)
4:2:2
293M
349M
292M
10
SDTI
750
1125
525
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
35 of 71
Table 4-4: Switch Line Position for Digital Systems (Continued)
System
Video Format
Sampling
Signal
Standard
Parallel
Interface
Serial
Interface
Switch Line
No.
525
720x483/59.94 (1:1)
4:2:2
293M
347M
344M
10
720x483/59.94 (1:1)
4:2:2
293M
293M
294M
10
720x483/59.94 (1:1)
4:2:0
293M
349M
292M
10
720x483/59.94 (1:1)
4:2:0
293M
293M
294M
10
720x576/50 (1:1)
4:2:2
BT.1358
349M
292M
6
720x576/50 (1:1)
4:2:2
BT.1358
347M
344M
6
720x576/50 (1:1)
4:2:2
BT.1358
BT.1358
BT.1362
6
720x576/50 (1:1)
4:2:0
BT.1358
349M
292M
6
720x576/50 (1:1)
4:2:0
BT.1358
BT.1358
BT.1362
6
960x576/50 (2:1)
4:2:2
BT.601
349M
292M
6, 319
960x576/50 (2:1)
4:2:2
BT.601
BT.656
259M
6, 319
720x576/50 (2:1)
4:4:4:4
BT.799
349M
292M
6, 319
720x576/50 (2:1)
4:4:4:4
BT.799
347M
344M
6, 319
720x576/50 (2:1)
4:4:4:4
BT.799
BT.799
344M
6, 319
720x576/50 (2:1)
4:4:4:4
BT.799
BT.799
–
6, 319
720x576/50 (2:1)
4:2:2
BT.601
349M
292M
6, 319
720x576/50 (2:1)
4:2:2
BT.601
125M
259M
6, 319
625
4.7.4 HVF Timing Signal Generation
The GS1559 extracts critical timing parameters from either the received TRS signals
(FW_EN/DIS = LOW), or from the internal Flywheel-Timing Generator (FW_EN/DIS =
HIGH).
Horizontal blanking period (H), Vertical blanking period (V), and even/odd Field (F)
timing are all extracted and presented to the application layer via the H:V:F status
output pins.
The H signal timing is configurable via the H_CONFIG bit of the internal
IOPROC_DISABLE register as either active line based blanking, or TRS based blanking,
(see Error Correction and Insertion on page 53).
Active Line Based Blanking is enabled when the H_CONFIG bit is set LOW. In this mode,
the H output is HIGH for the entire horizontal blanking period, including the EAV and
SAV TRS words. This is the default H timing used by the device.
When H_CONFIG is set HIGH, TRS based blanking is enabled. In this case, the H output
will be HIGH for the entire horizontal blanking period as indicated by the H bit in the
received TRS ID words.
The timing of these signals is shown in Figure 4-3.
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
36 of 71
PCLK
LUMA DATA OUT
3FF
000
000
XYZ
(eav)
3FF
000
000
XYZ
(sav)
CHROMA DATA OUT
3FF
000
000
XYZ
(eav)
3FF
000
000
XYZ
(sav)
H
V
F
H:V:F TIMING - HD 20-BIT OUTPUT MODE
PCLK
MULTIPLEXED
Y/Cr/Cb DATA OUT
3FF
3FF
000
000
000
000
XYZ
(eav)
XYZ
(eav)
XYZ
(sav)
XYZ
(sav)
H
V
F
H:V:F TIMING AT EAV - HD 10-BIT OUTPUT MODE
PCLK
MULTIPLEXED
Y/Cr/Cb DATA OUT
3FF
3FF
000
000
000
000
H
V
F
H;V:F TIMING AT SAV - HD 10-BIT OUTPUT MODE
PCLK
CHROMA DATA OUT
3FF
000
3FF
000
LUMA DATA OUT
000
XYZ
(eav)
000
XYZ
(SAV)
H
V
H SIGNAL TIMING:
H_CONFIG = LOW
F
H_CONFIG = HIGH
H:V:F TIMING - SD 20-BIT OUTPUT MODE
PCLK
MULTIPLEXED
Y/Cr/Cb DATA OUT
3FF
000
000
XYZ
(eav)
3FF
000
000
XYZ
(sav)
H
V
F
H:V:F TIMING - SD 10-BIT OUTPUT MODE
Figure 4-3: H, V, F Timing
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
30572 - 8
July 2008
37 of 71
4.8 DVB-ASI Functionality
The Lock Detect block may drop out of DVB-ASI mode under the following conditions:
•
RESET_TRST is asserted LOW
•
CDx is HIGH
•
SMPTE_BYPASS is asserted HIGH in Slave mode
•
DVB_ASI is asserted LOW in Slave mode
DVB_ASI functionality is only supported in Slave mode. To operate in DVB_ASI mode,
the device must be in Slave mode and the application layer must set the SD/HD pin
HIGH, in addition to setting SMPTE_BYPASS LOW and DVB_ASI HIGH.
4.8.1 DVB-ASI 8b/10b Decoding and Word Alignment
After serial-to-parallel conversion, the internal 10-bit data bus is fed to the DVB-ASI
8b/10b Decode and Word Alignment block. The function of this block is to word align
the data to the K28.5 sync characters, and 8b/10b decode and bit-swap the data to
achieve bit alignment with the data outputs.
The extracted 8-bit data will be presented to DOUT[17:10], bypassing all internal SMPTE
mode data processing.
NOTE: When operating in DVB-ASI mode, DOUT[9:0] are forced LOW.
4.8.2 Status Signal Outputs
In DVB-ASI mode, the DOUT19 and DOUT18 pins will be configured as DVB-ASI status
signals SYNCOUT and WORDERR respectively.
SYNCOUT will be HIGH whenever a K28.5 sync character is present on the output. This
output may be used to drive the Write Enable signal of an external FIFO, thus providing
a means of removing the K28.5 sync characters from the data stream. Parallel DVB-ASI
data may then be clocked out of the FIFO at some rate less than 27MHz. See Figure 4-4.
WORDERR will be high whenever the device has detected a running disparity error or
illegal code word.
AOUT ~ HOUT
8
8
FIFO
DDI
DDI
GS1559
SYNCOUT
FE
FF
WORDERR
WORDERR
PCLK = 27MHz
TS
CLK_IN
WE
CLK_OUT
READ_CLK
工商网监
湘ICP备2023018690号
