GF9103-CPS

MultiGEN ™ GF9103 Over-Sampling Color Space Converter for Video Monitoring DATA SHEET FEATURES • 4:2:2 to over-sampled RGB or YCBCR conversion in a single device • single 10 bit 4:2:2 input • internal 4:2:2 de-multiplexer • 4:2:2 to 8:8:8 interpolation filters • internal YCBCR to RGB color space conversion • optional YCBCR (8:8:8) output mode • setup insertion in Luminance channel under user control • user selectable digital SIN X/X correction • rounding to 10/8 bit resolution per output channel • 40 MHz maximum clock rate • single +5 V power supply APPLICATIONS • Over-Sampling 4:2:2 to Analog RGB Conversions for video monitoring • Over-Sampling 4:2:2 to Analog YCBCR Conversions for video monitoring ORDERING INFORMATION PART NUMBER GF9103-CPS GF9103-CTS PACKAGE 68 pin PLCC 68 pin PLCC Tape TEMPERATURE RANGE 0° to 70° C 0° to 70° C DEVICE DESCRIPTION The GF9103 is specifically designed to simplify conversions from 4:2:2 component digital video to analog RGB or analog YCBCR component video. The GF9103 simplifies this process by performing 4:2:2 to 8:8:8 interpolation, digital color space conversion and digital SIN X/X correction in a single device. Immediately following the GF9103, three over-sampled channels of RGB or YCBCR data may be passed through Digital to Analog converters and simplified analog reconstruction filters. The GF9103 accepts a single 10 bit stream of 4:2:2 data and internally de-multiplexes it into three 10 bit channels of The YCBCR data is then passed through YCBCR data. three linear phase FIR filters that over-sample the Y data by a factor of 2 and the CB and CR data by a factor of 4. While operating in an over-sampled RGB output mode, the interpolated YCBCR data is passed through the internal color space converter to convert the YCBCR data to RGB data according to CCIR-601. Alternatively, the color space converter may be bypassed to obtain over-sampled YC BCR (8:8:8) output data. While operating in YCBCR output mode, setup may be dynamically inserted into the Luminance channel. Prior to output rounding, over-sampled YCBCR or RGB data may be corrected for SIN X/X characteristics of D/A conversion. Output data may be rounded to 10 or 8 bit resolution per channel. CB and CR may be presented as signed or unsigned data. The GF9103 is packaged in a 68 pin PLCC package, operates with a single +5 V power supply and typically consumes only 85 mA of current when operated at 27 MHz. SETUP SELECT_MATRIX BYPASS CONVERT OE Y X2 10 4:2:2 DEMUX Y SETUP Y Y/G SIN X/X Y/G CLIP & ROUND CB/B SIN X/X CLIP & ROUND CR/R SIN X/X CLIP & ROUND CR/R 2's COMP CB/B 2's COMP Y/G 10 Y/G MULTIPLEXED 4:2:2 DATA STREAM IN CB X4 CB CB YCBCR TO RGB MATRIX CB/B CB/B 10 CB/B 10 CR/R CR CLK X4 CR CR CR/R CR/R SYNC FUNCTIONAL BLOCK DIAGRAM Revision Date: August 1997 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com Document No. 521 - 33 - 04 PIN DESCRIPTION PIN NO. 10, 18, 27, 36, 44, 52, 61, 68 1, 6, 7, 9, 26, 30, 35, 40, 43, 60, 64 3 8, 11-17, 19, 20 SYMBOL VDD GND ±5 V ± 5% power supply. DESCRIPTION Ground. SCAN_EN SI9..0 Set Low. Input Data Port: Input data port with internal pull-downs. Input data is assumed to be a multiplexed stream of CBYCR [Y] CB..., where [Y] denotes an isolated Luminance sample. SI9 is the Most Significant Bit and SI0 is the Least Significant Bit. 4 OE Output Enable: Active low input with internal pull-up. When OE is high, the output data ports are in high impedance state. Output Data Port A: Depending on device configuration, SOA9..0 may output over-sampled Y or G video. SOA9 is the Most Significant Bit and SOA0 is the Least Significant Bit. Output Data Port B: Depending on device configuration, SOB9..0 may output over-sampled CB or B video. SOB9 is the Most Significant Bit and SOB0 is the Least Significant Bit. Output Data Port C: Depending on device configuration, SOC9..0 may output over-sampled CR or R video. SOC9 is the Most Significant Bit and SOC0 is the Least Significant Bit. 59-53, 51-49 SOA9..0 48-45, 42, 41, 39-37, 34 33-31, 29, 28, 25-21 SOB9..0 SOC9..0 2 5 CLK SYNC System Clock: All timing information relative to rising edge of clock. Synchronization: Control signal input with internal pull-up. This input is used to synchronize the incoming data by holding SYNC high on clock period N and low on clock period N+1 when the first CB sample is presented to the SI9..0 inputs. SYNC may be held low until resynchronization is desired or may be toggled at every occurrence of a CB sample. Select Color Space Conversion: Control signal input with internal pull-down. SELECT_MATRIX is used to enable and disable the internal YCBCR to RGB color space converter. Color space conversion is enabled while SELECT_MATRIX is high and is disabled while SELECT_MATRIX is low. Bypass SIN X/X Correction: Control signal input with internal pull-up. When BYPASS is high, SIN X/X correction for the three output channels is enabled. While BYPASS is low, SIN X/X correction is by-passed. Setup: Control signal input with internal pull-down. SETUP is used to enable and disable setup insertion in the Luminance channel. Two's Complement Conversion: Control signal input with internal pull-up. While CONVERT is high, SOB9..0 and SOC9..0 output signed (two’s complement) digital data. While CONVERT is low, SOB9..0 and SOC9..0 output unsigned (offset binary) data. When operating in RGB output mode, the CONVERT pin is over-ridden and both SOB9..0 and SOC9..0 output unsigned digital data. SOA9..0 outputs unsigned digital data in all operating modes. 65 SELECT_MATRIX 66 BYPASS 63 SETUP 62 CONVERT 67 RND10/8 Output Rounding: Control signal input with internal pull-up. RND10/8 selects rounding to 10 bit resolution per channel when high and rounding to 8 bit resolution per channel when low. 521 - 33 - 04 2 SELECT_MATRIX CONVERT SCAN_EN RND10/8 BYPASS SETUP SYNC GND GND GND GND GND VDD VDD SI8 SI7 SI6 SI5 SI4 SI3 SI2 VDD SI1 SI0 SOC0 SOC1 SOC2 SOC3 SOC4 GND 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 VDD CLK SI9 OE GND SOA9 SOA8 SOA7 SOA6 SOA5 SOA4 SOA3 VDD SOA2 SOA1 SOA0 SOB9 SOB8 SOB7 SOB6 VDD GF9103 TOP VIEW 52 51 50 49 48 47 46 45 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 SOC5 SOC6 GND SOC7 SOC8 SOC9 SOB0 GND SOB1 SOB2 SOB3 GND SOB4 SOB5 GND VDD VDD Fig. 1 GF9103 Pin Connections VDD VDD n SUBSTRATE n SUBSTRATE D1 p+ CONTROL INPUT n+ D2 n n p p D1 p+ n+ D2 p WELL GND GND p WELL Fig. 2a Equivalent Input Circuit Fig. 2b Equivalent Output Circuit 3 521 - 33 - 04 DEVICE DESCRIPTION The GF9103 is composed of five main sections: 1. 4:2:2 De-Multiplexer 2. FIR Filtering and Setup Insertion 3. Color Space Conversion 4. Digital SIN X/X Correction 5. Output Processing 4:2:2 DE-MULTIPLEXER The de-multiplexer accepts data multiplexed in a SMPTE 125M compliant format from the SI9..0 input data port. SI9 is the Most Significant Bit and SI0 is the Least Significant Bit. The input data stream is assumed to be a multiplexed stream of CB Y CR [Y] CB..., where the three words CB Y CR refer to cosited samples and where [Y] refers to an isolated Luminance sample. When operating the GF9103 with 8 bit input data, SI9..2 should be used to present data to the device and SI1..0 should be set low. At least once during a power cycle, the GF9103 must be synchronized to the incoming data stream. The GF9103 is synchronized by holding SYNC high on clock period N and low on clock period N+1 when the first CB sample is presented to the SI9..0 inputs. SYNC may be held low until re-synchronization is desired, or it may be toggled at every occurrence of a CB sample. Refer to the timing diagram in Figure 9 for required operation of the SYNC control signal. The internal de-multiplexer will de-multiplex all data in the input data stream including any ancillary, EDH,VITC, and EAV/SAV ... signals that may be present. Since this data is passed directly to the interpolation filters in the same way that active video would be, it is recommended that such data be replaced with appropriate blanking levels prior to entering the GF9103. The output of the 4:2:2 de-multiplexer consists of three 10 bit channels of YCBCR data. All three channels are then fed to their respective interpolation filter. INTERPOLATION FILTERS Within the interpolation stage, the Luminance data is oversampled by a factor of two and the CB and CR data is oversampled by a factor of four so that the 4:2:2 data is converted to 8:8:8 data. By over-sampling the 4:2:2 data to 8:8:8 data, the size, cost and complexity of the analog reconstruction filters following Digital to Analog converters are reduced. The Luminance data is over-sampled by a linear phase FIR filter providing 0.0 dB DC gain, +0.038/-0.025 pass- band ripple [0.0 ƒs to 0.21 ƒs], 6 dB attenuation at ƒs/4, and 47 dB stopband attenuation [0.30 ƒs to 0.50 ƒs]. Figure 3 and Figure 4 present the frequency response of the Luminance interpolation filter. The CB and CR data is over-sampled by a linear phase FIR filter providing 0.0 dB DC gain, passband ripple of +0.2 dB/0.2 dB [0.0 to 0.07 ƒs], 6 dB attenuation at ƒs/8 and a stopband attenuation of 28 dB [ 0.17ƒs to 0.50 ƒs]. Figure 5 and Figure 6 present the frequency response of the CB and CR interpolation filters. Following the interpolation process, a DC offset may be introduced into the Luminance channel. Setup insertion is enabled and disabled by the SETUP control signal. While SETUP is high, the Luminance data is scaled by a factor of +947/1024 and an offset of +71 (decimal) is added. While SETUP is low, no scaling or offset is applied and the data passes through the stage unmodified. The timing diagram in Figure 10 demonstrates the operation of the SETUP control signal. COLOR SPACE CONVERSION Two operating modes exist for the color space converter section. These two modes are controlled by the SELECT_MATRIX control signal. While SELECT_MATRIX is low, the de-matrixing 3 x 3 multiplier is bypassed so that over-sampled Y CB CR data is passed through the stage unmodified. While SELECT_MATRIX is high, the 3 x 3 multiplier implements the following color space conversion: G B= R 1 1 1 -689/2048 3548/2048 0 -1430/2048 0 2807/2048 Y CB CR SIN X/X CORRECTION While BYPASS is high, SIN X/X correction is enabled on each of the three output channels. SIN X/X correction is implemented by passing the data through a FIR filter with the frequency response shown in Figure 7. While BYPASS is low, the FIR filter is bypassed and each channel is passed directly to the output processing section. Total latency through the device is 22 clock cycles when BYPASS is low and 24 clock cycles when BYPASS is high. OUTPUT PROCESSING Output data may be rounded to 10 or 8 bit accuracy. RND10/8 should be set high for 10 bit output rounding and set low for 8 bit output rounding. Rounding to 8 bit accuracy is accomplished by adding a rounding bit to SO1 and then zeroing both SO0 and SO1. CB and CR data may be output as signed (two’s complement) or unsigned (offset binary) data depending on the state of the CONVERT control signal. When CONVERT is set high, the CB and CR channels are output as signed (two’s complement) data. When CONVERT is set low, CB and CR are output as unsigned (offset binary) data, obtained by inverting the sign bit of the two's complement number. When operating in RGB output mode, the CONVERT pin is over-ridden and RGB data is always output as unsigned (offset binary) data. 4 521 - 33 - 04 CONTROL SIGNAL/OPERATING MODE SUMMARY SYNC The SYNC control signal provides synchronization for the internal 4:2:2 de-multiplexer. SYNC should be held high on clock period N and low on clock period N+1 when the first CB sample is presented to the SI9..0 inputs. SYNC may be held low until re-synchronization is desired or may be toggled at every occurrence of a CB sample. SELECT_MATRIX AND SETUP SELECT_MATRIX and SETUP select the color space conversion and offset insertions which the GF9103 is to perform. The following chart presents the available color space conversions and the corresponding states of the SELECT_MATRIX and SETUP control pins. SETUP is a dynamic pin that may be modified every clock cycle. SELECT_MATRIX 0 0 SETUP 0 1 DESCRIPTION Selects output to be over-sampled YCBCR with no setup in Y channel. Selects output to be over-sampled YCBCR with a scaling factor of +947/1024 and an offset of +71 (decimal) applied to the Y channel. Selects output to be over-sampled RGB with no setup. 1 X SIN X/X CORRECTION BYPASS 1 0 DESCRIPTION SIN X/X correction enabled on all output data channels. Latency through the device is 24 clock cycles. SIN X/X correction disabled. Latency through the device is 22 clock cycles. OUTPUT ROUNDING RND10/8 1 0 Output data rounded to 10 bit resolution per channel. Output data rounded to 8 bit resolution per channel. DESCRIPTION TWO’S COMPLEMENT OUTPUT CONVERSION CONVERT 1 0 X SELECT_MATRIX 0 0 1 DESCRIPTION SOB9..0 and SOC9..0 output signed (two's complement) CB and CR data. SOB9..0 and SOC9..0 output unsigned (offset binary) CB and CR data. SOB9..0 and SOC9..0 output unsigned B and R data. OUTPUT ENABLE OE 0 1 All output data ports are enabled. All output data ports are in high impedance state. DESCRIPTION 5 521 - 33 - 04 0 -8 -16 0.10 0.08 0.06 MAGNITUDE (dB) -32 -40 -48 -56 -64 -72 -80 0.00 1.35 2.70 4.05 5.40 6.75 8.10 9.45 10.80 12.15 13.50 MAGNITUDE (dB) -24 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0.00 1.35 2.70 4.05 5.40 6.75 FREQUENCY (MHz) FREQUENCY (MHz) Fig. 3 Frequency Response of Luminance Interpolation Filter (Sampling at ƒs=27MHz) Fig. 4 Frequency Response of Luminance Interpolation Filter (Sampling at ƒs=27MHz) 0 -4 -8 1.0 0.8 0.6 0.4 MAGNITUDE (dB) -12 MAGNITUDE (dB) 0.00 1.35 2.70 4.05 5.40 6.75 8.10 9.45 10.80 12.15 13.50 -16 -20 -24 -28 -32 -36 -40 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0.00 0.54 1.08 1.62 2.16 2.70 3.24 FREQUENCY (MHz) FREQUENCY (MHz) Fig. 5 Frequency Response of Chrominance Interpolation Filter (Sampling at ƒs=27MHz) Fig. 6 Frequency Response of Chrominance Interpolation Filter (Sampling at ƒs=27MHz) 2.0 1.8 1.6 1.4 PARAMETER Filter Order Pass Band Ripple LUMINANCE FILTER 31 +0.038 / -0.025 dB (0.0 ƒs to 0.21 ƒs) CHROMINANCE FILTER 15 +0.2 / -0.2 dB (0.0 ƒs to 0.21 ƒs) 0.0 dB -6.00 dB (at ƒS/8) -28 dB (0.17 ƒs to 0.50 ƒs) MAGNITUDE (dB) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 0.00 1.35 2.70 4.05 5.40 6.75 8.10 9.45 10.80 12.15 13.50 DC Gain Attenuation Stop Band Attenuation 0.0 dB -6.00 dB (at ƒS/4) -47 dB (0.30 ƒs to 0.50 ƒs) FREQUENCY (MHz) Fig. 7 SIN X/X Compensation Filter Frequency Response (Sampling at ƒs=27MHz) fig. 8 luminance and chrominance filter characteristics 521 - 33 - 04 6 ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage Input Voltage Range (any input) Operating Temperature Range Storage Temperature Range Lead Temperature Range (soldering 10 seconds) VALUE -0.3 to +7.0 V +0.5 to (VDD +0.5) V 0°C ≤ TA ≤ 70°C -65°C ≤ TS ≤ 150°C 260°C ELECTRICAL CHARACTERISTICS VDD = 5V, TA = 0°C, RL = 150 Ω to GND and 144 Ω AC coupled unless otherwise shown. PARAMETER Supply Voltage Supply Current Quiescent Supply Current Unloaded Input Voltage, Logic Low Input Voltage, Logic High Switching Threshold Input Current: (CMOS Inputs) Inputs with Pulldown Resistors Inputs with Pullup Resistors Output Voltage, Logic Low Output Voltage, Logic High Hi-Z Output Leakage Current Short Circuit Output Current SYMBOL VDD IDDQ IDDU VIL VIH VT IIN CMOS CONDITIONS MIN 4.75 TYP 5 5 85 2.5 ±1 115 -115 0.2 4.5 ±1 - MAX 5.25 9 150 0.2VDD 10 222 -214 0.4 10 140 UNITS V mA mA V V V µA µA µA V V µA mA VDD = Max, VIN = 0V VDD = Max, OE = VDD, ƒ = 27MHz 0.7VDD -10 35 -35 2.4 -10 - VIN = VDD or GND VIN = VDD V IN = GND VOL VOH IOZ IOS VDD = Min, IOL = 4mA VDD = Min, IOH = -4mA VDD = Max, OE = 1 VDD = Max, output high one pin to ground, one second duration max TA = 25°C, ƒ = 1MHz TA = 25°C, ƒ = 1MHz Input Capacitance Output Capacitance CIN COUT - - 10 10 pF pF 0 1 2 3 4 5 6 7 CLOCK tPWH tPWL Y tCY CB Y CR SI9..0 CB tS tH Y CR SYNC Fig. 9 Operation of SYNC Control Signal 7 521 - 33 - 04 SWITCHING CHARACTERISTICS TA from 0°C to 70°C unless otherwise specified. NAME tD tOH tEN tDIS tCY tPWL tPWH tS tH PARAMETER Output delay Output hold time Output enable Output disable Cycle time Clock pulse width low Clock pulse width high Input setup time Input hold time TEST CONDITIONS VDD = Min, CL = 25pF VDD = Max, CL = 25pF VDD = Min, CL = 25pF VDD = Min, CL = 25pF MIN 8 1 25 10 10 8 1 TYP 9 - MAX 10 8 8 - UNITS ns ns ns ns ns ns ns ns ns 0 1 2 3 4 5 6 7 CLOCK tPWH Y tS tH CB Y tPWL CR Y tCY CB Y SI9..0 SETUP Fig. 10 Operation of SETUP Control Signal 0 1 2 3 4 5 6 7 CLOCK tPWH CB tS SYNC tH Y CR tPWL CB tCY Y Y CR SI9..0 25 26 27 28 29 30 31 32 CLOCK tD SOA9..0 SOB9..0 SOC9..0 1 2 3 tOH 4 5 6 7 8 Fig. 11 Input/Output Timing, BYPASS = 1 521 - 33 - 04 8 0 1 2 3 4 5 6 7 CLOCK tPWH CB tS tH SYNC Y CR tPWL CB tCY Y Y CR SI9..0 23 24 25 26 27 28 29 30 CLOCK SOA9..0 SOB9..0 SOC9..0 tD tOH 6 tDIS tEN 7 8 1 2 3 4 5 OE Fig. 12 Input/Output Timing, BYPASS = 0 CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION REVISION NOTES: DOCUMENT IDENTIFICATION DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. GENNUM CORPORATION MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 GENNUM JAPAN CORPORATION C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku Tokyo 168-0081, Japan Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839 GENNUM UK LIMITED Centaur House, Ancells Bus. Park, Ancells Rd, Fleet, Hants, England GU13 8UJ Tel. +44 (0)1252 761 039 Fax +44 (0)1252 761 114 Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. © Copyright March 1995 Gennum Corporation. All rights reserved. Printed in Canada. 9 521 - 33 - 04