GS1503B

GS1503B HD Embedded Audio CODEC Data Sheet Features • • • • • • • • • • • • complies with SMPTE 292M and SMPTE 299M single chip HD embedded audio solution operates as an embedded audio multiplexer or demultiplexer full support for 48kHz synchronous 24-bit audio support for 8 channels of audio per device cascadable architecture supports up to 16 audio channels integrated scrambler/descrambler and word alignment CRC error detection and insertion audio control packet insertion and extraction arbitrary data packet insertion and extraction 3.3V power supply with 5V tolerant I/O 144 pin TQFP package Description The GS1503B is a highly integrated, single chip solution for embedding/extracting digital audio streams into and out of high definition digital video signals. The GS1503B supports insertion/extraction of 24-bit synchronous audio data with a 48kHz sample rate. Audio signals with different sample rates may be converted to 48kHz by using audio sample rate converters before or after the GS1503B. Each GS1503B supports all processing required for embedding/extracting up to eight digital audio channels in the horizontal ancillary data space of the video chroma channel. Two GS1503B’s can be cascaded for insertion/extraction of up to 16 audio channels with no external glue logic. The GS1503B supports embedding/extracting of audio control and arbitrary data packets in the horizontal ancillary data space of the video luma channel. It also supports line CRC detection and insertion. The GS1503B supports HD video standards at 74.25MHz and 74.25/1.001MHz rates. It has an on chip SMPTE compliant scrambler/de-scrambler, and integrated word alignment. Use the GS1503B with Gennum’s GS1545 or GS1522 for two chip HD SDI receive or transmit solutions. The GS1503B operates from a single 3.3V power supply with 5V tolerant I/O and is packaged in a 144 pin TQFP package. Applications HD SDI Embedded Audio GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 www.gennum.com 1 of 90 DSCBYPASS EXTH EXTF SCRBYPASS VIN[19:0] 20 De-scrambler & Word Alignment 20 20 TRS Inserter 20 CRC Inserter & Scrambler 20 VOUT[19:0] VIDEO_DET OPERATE ERROR CRC_ERR VM[3:0] 4 Video Detection & Synchronization ANCI Timing Generation 4 CPUADR[8:0] CPUDAT[7:0] CPUCS, CPUWE, CPURE PKT[7:0] PKTEN AIN1/2 AIN3/4 AIN5/6 AIN7/8 WCINA/B 9 8 3 Host Interface Control Packet Mux HOST INTERFACE 8 Arbitrary Packet Mux PKTENO HOST INTERFACE 4 Audio Input Interface 2 AM[1:0] MUTE Audio Packet Mux 2 Multiplex Mode Block Diagram DSCBYPASS ANCI SCRBYPASS VIN[19:0] 20 De-scrambler & Word Alignment Video Detection & Synchronization ANCI Timing Generation 20 Delete ANCI 20 CRC Inserter & Scrambler 20 VOUT[19:0] VIDEO_DET OPERATE ERROR CRC_ERR PKT[7:0] PKTEN VM[3:0] 4 4 Arbitrary Packet Demux 8 HOST INTERFACE Control Packet Demux 9 8 3 Host Interface Audio Packet Demux HOST INTERFACE AOUT1/2 AOUT3/4 AOUT5/6 AOUT7/8 WCOUTA/B CPUADR[8:0] CPUDAT[7:0] CPUCS, CPUWE, CPURE 4 Audio Output Interface 2 AM[1:0] MUTE 2 Demultiplex Mode Block Diagram Contents Features.................................................................................................................................................................1 Applications.........................................................................................................................................................1 Description...........................................................................................................................................................1 1. Pin Connections .............................................................................................................................................5 1.1 Pin Descriptions ................................................................................................................................6 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 2 of 90 2. Electrical Characteristics ......................................................................................................................... 10 2.1 Absolute Maximum Ratings ....................................................................................................... 10 2.2 DC Electrical Characteristics ..................................................................................................... 10 2.3 AC Electrical Characteristics ..................................................................................................... 11 2.4 Solder Reflow Profiles .................................................................................................................. 13 3. Host Interface .............................................................................................................................................. 14 4. Detailed Description.................................................................................................................................. 17 4.1 Multiplex Mode .............................................................................................................................. 17 4.1.1 Functional Overview........................................................................................................ 17 4.2 Video Standard ............................................................................................................................... 18 4.3 Video Input Format ....................................................................................................................... 19 4.3.1 10-bit Y and Cb/Cr Input Video with TRS and Line Numbers ............................ 19 4.3.2 8-bit Y and Cb/Cr Input Video With TRS and Line Numbers.............................. 20 4.3.3 10-bit or 8-bit Y and Cb/Cr Input Without TRS and Line Numbers .................. 21 4.3.4 20-bit Scrambled Input .................................................................................................... 22 4.4 Video Output Format ................................................................................................................... 23 4.4.1 20-bit Scrambled Output................................................................................................. 23 4.4.2 10-bit Y and Cb/Cr Output ............................................................................................. 23 4.5 Video Data Processing ................................................................................................................. 24 4.5.1 Video Signal Input Detection......................................................................................... 24 4.5.2 Video Input CRC Error Detection................................................................................. 24 4.5.3 Video Output CRC Insertion .......................................................................................... 25 4.5.4 Illegal Code Re-mapping................................................................................................. 25 4.5.5 Input Blanking .................................................................................................................... 25 4.5.6 Line Number Insertion..................................................................................................... 26 4.5.7 TRS Word Insertion........................................................................................................... 26 4.6 Audio Data Processing ................................................................................................................. 27 4.6.1 Digital Audio Input Format ............................................................................................ 27 4.6.2 Digital Audio Input Timing............................................................................................. 28 4.6.3 Audio Clock Phase Locked Loop .................................................................................. 30 4.6.4 Audio Signal Input Detection ........................................................................................ 30 4.6.5 Audio Channel Status CRC Error Detection ............................................................. 31 4.6.6 Audio Input Parity Error Detection ............................................................................. 31 4.6.7 Audio Channel Status CRC Insert Function.............................................................. 32 4.7 Audio Data Packets ....................................................................................................................... 32 4.7.1 Audio Data Packet Structure ......................................................................................... 32 4.7.2 Audio Data Packet DID Setting ..................................................................................... 33 4.7.3 Audio Channel Multiplex Enable................................................................................. 34 4.8 Video Switching Line Setting ..................................................................................................... 35 4.9 Multiplex Cascade Mode ............................................................................................................ 36 4.10 Audio Control Packets ............................................................................................................... 38 4.10.1 Audio Control Packet Structure ................................................................................. 38 4.10.2 Audio Control Packet DID Setting ............................................................................. 39 4.11 Arbitrary Data Packets .............................................................................................................. 41 4.11.1 Arbitrary Data Multiplexing In External Pin Mode............................................. 42 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 3 of 90 4.11.2 Arbitrary Data Multiplexing in Host Interface Mode ......................................... 43 5. Demultiplex Mode ..................................................................................................................................... 52 5.1 Functional Overview .................................................................................................................... 52 5.2 Video Standard ............................................................................................................................... 53 5.3 Video Input Format ....................................................................................................................... 54 5.3.1 20-bit Scrambled Input .................................................................................................... 54 5.3.2 10-bit Y and Cb/Cr Input with TRS and Line Numbers ......................................... 55 5.4 Video Output Format ................................................................................................................... 56 5.4.1 10-bit Y and Cb/Cr Output ............................................................................................. 56 5.4.2 20-bit Scrambled Output................................................................................................. 56 5.5 Video Data Processing ................................................................................................................. 57 5.5.1 Video Signal Input Detection......................................................................................... 57 5.5.2 Video Input CRC Error Detection................................................................................. 57 5.5.3 Video Output CRC Insertion .......................................................................................... 58 5.5.4 Input Blanking .................................................................................................................... 58 5.5.5 Line Number Insertion..................................................................................................... 58 5.5.6 TRS Word Insertion........................................................................................................... 59 5.6 Audio Data Processing ................................................................................................................. 59 5.6.1 Digital Audio Output Format......................................................................................... 59 5.6.2 Digital Audio Output Timing ......................................................................................... 60 5.6.3 Audio Clock Phase Locked Loop .................................................................................. 63 5.6.4 Audio Data Packet Detection ........................................................................................ 64 5.6.5 ECC Error Detection & Correction ............................................................................... 64 5.6.6 Audio Data Packet Error Detection ............................................................................. 65 5.6.7 Audio Data Packet DID Setting ..................................................................................... 66 5.7 Demultiplex Cascade Mode ....................................................................................................... 67 5.8 Audio Control Packets ................................................................................................................. 68 5.8.1 Audio Control Packet Detection................................................................................... 68 5.8.2 Audio Control Packet DID Setting ............................................................................... 68 5.9 Arbitrary Data Packets ................................................................................................................. 70 5.9.1 Arbitrary Data Demultiplexing in External Pin Mode .......................................... 71 5.9.2 Arbitrary Data Demultiplexing in Host Interface Mode ...................................... 71 5.10 Ancillary Data Deletion ............................................................................................................ 72 5.10.1 Entire Ancillary Data Deletion ................................................................................... 72 5.10.2 Audio Group Designation Ancillary Data Deletion............................................. 72 5.11 Demultiplex Mode With Word Clock Input ....................................................................... 73 6. Using the GS1503B with the GS4911B or GS4910B ........................................................................ 86 7. References & Bibliography ...................................................................................................................... 87 8. Packaging & Ordering Information ...................................................................................................... 88 8.1 Package Dimensons ...................................................................................................................... 88 8.2 Packaging Data ............................................................................................................................... 88 8.3 Ordering Information ................................................................................................................... 89 9. Revision History.......................................................................................................................................... 90 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 4 of 90 1. Pin Connections GND CPUWE CPURE CPUCS VDD CPUDAT7 CPUDAT6 CPUDAT5 CPUDAT4 CPUDAT3 CPUDAT2 VDD CPUDAT1 CPUDAT0 CPUADR4 CPUADR3 CPUADR2 CPUADR1 CPUADR0 CPUADR5 GND VCLK GND DEC_MODE VDD CPUADR6 CPUADR7 CPUADR8 GND AOUT7/8 AOUT5/6 AOUT3/4 AOUT1/2 WCOUTB WCOUTA VDD VDD VIN19 VIN18 VIN17 GND VIN16 VIN15 VIN14 VDD VIN13 VIN12 VIN11 GND VIN10 VIN9 VIN8 VDD VIN7 VIN6 VIN5 GND VIN4 VIN3 VIN2 VDD VIN1 VIN0 CPU_SEL AM1 AM0 VM3 VM2 VM1 VM0 RESET GND 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 GS1503B TOP VIEW 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 GND VOUT19 VOUT18 VOUT17 VDD VOUT16 VOUT15 VOUT14 GND VOUT13 VOUT12 VOUT11 VDD VOUT10 VOUT9 VOUT8 GND VOUT7 VOUT6 VOUT5 VDD VOUT4 VOUT3 VOUT2 GND VOUT1 VOUT0 VIDEO_DET EXTF EXTH RSV RSV RSV RSV SCRBYPASS VDD GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 VDD AIN7/8 AIN5/6 AIN3/4 AIN1/2 WCINB WCINA DSCBYPASS PLLCNTB PLLCNTA CASCADE MUTE ANCI VDD MUX/DEMUX GND ACLKA GND ACLKB GND ERROR OPERATE CRC_ERROR PKTENO PKTEN PKT7 VDD PKT6 PKT5 PKT4 VDD PKT3 PKT2 PKT1 PKT0 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 5 of 90 1.1 Pin Descriptions Table 1-1: Pin Descriptions Number 1, 14, 27, 31, 37, 52, 60, 68, 73, 84, 97, 104, 109, 117, 125, 133 2 Symbol VDD Type – Description +3.3V power supply pins. AIN7/8 I Audio signal input for channels 7 and 8. AES/EBU digital audio data is bi-phase mark encoded. For all non-AES/EBU input modes, bi-phase mark encoding is not required. Audio signal input for channels 5 and 6. AES/EBU digital audio data is bi-phase mark encoded. For all non-AES/EBU input modes, bi-phase mark encoding is not required. Audio signal input for channels 3 and 4. AES/EBU digital audio data is bi-phase mark encoded. For all non-AES/EBU input modes, bi-phase mark encoding is not required. Audio signal input for channels 1 and 2. AES/EBU digital audio data is bi-phase mark encoded. For all non-AES/EBU input modes, bi-phase mark encoding is not required. 48kHz word clock for channels 5 to 8. Used only when operating in Multiplex Mode and when the audio source is not an AES/EBU data stream. This pin should be grounded when inputting AES/EBU digital audio data or when operating in Demultiplex Mode (DEC_MODE set LOW). 48kHz word clock for channels 1 to 4. Used only when operating in Multiplex Mode and when the audio source is not an AES/EBU data stream. This pin should be grounded when inputting AES/EBU digital audio data or when operating in Demultiplex Mode (DEC_MODE set LOW). Descrambler bypass. When set LOW, the internal SMPTE 292M descrambler is enabled. When set HIGH, the internal SMPTE 292M descrambler is bypassed. The video input to the device must be word aligned. Audio clock PLL control signal for channels 5 to 8. Audio clock PLL control signal for channels 1 to 4. Cascade mode select. When set HIGH, the GS1503B will default to audio groups 3 and 4. Two GS1503B devices can then be cascaded in series to allow up to 16 channels of audio to be multiplexed or demultiplexed (only one device requires CASCADE to be set HIGH). When set LOW, the GS1503B will default to audio groups 1 and 2. Audio mute. In Multiplex Mode, when set HIGH, the embedded audio packets are forced to '0'. In Demultiplex Mode, when set HIGH, the audio output data is forced to "0". Ancillary data delete select. Valid in Demultiplex Mode only. When set HIGH, all ancillary data packets are removed from both the Luma and Chroma channels of the input video signal. The data contained in the packets are output at the corresponding pins. When set LOW, all ancillary data packets remain in the video signal. See Demultiplex Mode With Word Clock Input on page 73. Mode of operation. When set LOW, the GS1503B operates in Multiplex Mode. When set HIGH, the GS1503B operates in Demultiplex Mode. 3 AIN5/6 I 4 AIN3/4 I 5 AIN1/2 I 6 WCINB I 7 WCINA I 8 DSCBYPASS I 9 10 11 PLLCNTB PLLCNTA CASCADE O O I 12 MUTE I 13 ANCI I 15 MUX/DEMUX I GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 6 of 90 Table 1-1: Pin Descriptions (Continued) Number 16, 18, 20, 36, 48, 56, 64, 72, 80, 86, 88, 108, 113, 121, 129, 144 17 19 21 Symbol GND Type – Description Device ground. ACLKA ACLKB ERROR I I O Input audio signal clock at 6.144 MHz (128 fs) for channels 1 to 4. Input audio signal clock at 6.144 MHz (128 fs) for channels 5 to 8. Format error indicator. When HIGH, the incoming video data stream contains TRS errors or there are errors within the incoming ancillary data packets. Audio processing indicator. When HIGH, audio data is being multiplexed or demultiplexed. CRC error indicator. Will be set HIGH when a CRC error is detected in the incoming video data stream. Arbitrary data packet timing signal. Valid in Multiplex Mode only. Will be HIGH when arbitrary data packets can be input to the device. This signal is only valid when multiplexing arbitrary data packets via the PKT[7:0] bus. See Figure 4-22 for timing. Arbitrary data packet enable. In Multiplex Mode, PKTEN is an input and must be set HIGH two VCLK cycles after the PKTENO signal goes HIGH. Arbitrary packet data is input to the device two VCLK cycles after PKTEN is set HIGH. In Demultiplex Mode, PKTEN is an output and is set HIGH two VCLK cycles before the device outputs arbitrary packet data. See Figure 4-22 and Figure 5-12. Arbitrary data I/O bus. PKT[7] is the MSB and PKT[0] is the LSB. In Multiplex Mode, the user must input the arbitrary data packet words starting from the data identification (DID) to the last user data word (UDW) according to SMPTE 291M. The GS1503B internally converts the data to 10 bits by generating the parity bit (bit 8) and inversion bit (bit 9). The checksum (CS) word is also generated internally. In Demultiplex Mode, the GS9023 outputs the arbitrary data packet words starting from the DID to the last UDW. See Figure 4-22 and Figure 5-12. Scrambler bypass. When set LOW, the output video stream is scrambled according to SMPTE 292M and NRZ(I) encoded. When set HIGH, the scrambler and NRZ(I) encoder are bypassed. Connect to ground. 22 OPERATE O 23 CRC_ERROR O 24 PKTENO O 25 PKTEN I/O 26, 28, 29, 30, 32, 33, 34, 35 PKT[7:0] I/O 38 SCRBYPASS I 39, 40, 41, 42 43 RSV – EXTH I/O Horizontal sync signal. The GS1503B outputs a horizontal sync signal derived from the incoming TRS. In Multiplex Mode, with EXT_SEL set HIGH in the Host Interface, a horizontal sync signal can be input to the device for TRS and line number insertion. Field sync signal. The GS1503B outputs a field sync signal derived from the incoming TRS. In Multiplex Mode, with EXT_SEL set HIGH in the Host Interface, a field sync signal can be input to the device for TRS and line number insertion. For progressive formats, a signal with a high to low transition at the position of line one must be provided. See Figure 4-6 and Figure 4-7. Video input signal detection. Indicates that the device has detected a valid video input stream. NOTE: When EXT_SEL is set HIGH in the Host Interface, VIDEO_DET will indicate when valid EXTH and EXTF signals have been detected. 44 EXTF I/O 45 VIDEO_DET O GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 7 of 90 Table 1-1: Pin Descriptions (Continued) Number 71, 70, 69, 67, 66, 65, 63, 62, 61, 59, 58, 57, 55, 54, 53, 51, 50, 49, 47, 46 74 75 76 Symbol VOUT[19:0] Type O Description Parallel digital video signal output. VOUT[19] is the MSB and VOUT[0] is the LSB. WCOUTA WCOUTB AOUT1/2 O O O 48kHz word clock for channels 1 to 4. Valid only when operating in Demultiplex Mode. 48kHz word clock for channels 5 to 8. Valid only when operating in Demultiplex Mode. Audio signal output for channels 1 and 2. The AES/EBU digital audio output is bi-phase mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded. Audio signal output for channels 3 and 4. The AES/EBU digital audio output is bi-phase mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded. Audio signal output for channels 5 and 6. The AES/EBU digital audio output is bi-phase mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded. Audio signal output for channels 7 and 8. The AES/EBU digital audio output is bi-phase mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded. Demultiplex Mode select. Valid in Demultiplex Mode only. When set HIGH, the GS1503B requires a 48kHz word clock input at WCINA and WCINB. This word clock must be synchronous to the word clock used to embed the audio data. The embedded audio clock phase information in the ancillary data packet will be ignored. See Demultiplex Mode With Word Clock Input on page 73. Video clock signal input. Host Interface address bus. CPUADR[8] is the MSB and CPUADR[0] is the LSB. In Host Interface Mode B (CPU_SEL set LOW), CPUADR[1:0] are used as the Host Interface control bus. See Table 3-4. Host Interface data bus. CPUDAT[7] is the MSB and CPUDAT[0] is the LSB. In Host Interface Mode B (CPU_SEL set LOW), CPUDAT[7:0] are used as the Host Interface address and data bus. 77 AOUT3/4 O 78 AOUT5/6 O 79 AOUT7/8 O 85 DEC_MODE I 87 81, 82, 83, 89, 94, 93, 92, 91, 90 103, 102, 101, 100, 99, 98, 96, 95 105 106 VCLK CPUADR[8:0] I I CPUDAT[7:0] I/O CPUCS CPURE I I Chip select for Host Interface. Active LOW. Read enable for Host Interface. Active LOW. In Host Interface Mode B (CPU_SEL set LOW), this input is not used. Write enable for Host Interface. Active LOW. In Host Interface Mode B (CPU_SEL set LOW), this input is used as the Host Interface control enable. Parallel digital video signal input. VIN[19] is the MSB and VIN[0] is the LSB. 107 CPUWE I 110, 111, 112, 114, 115, 116, 118, 119, 120, 122, 123, 124, 126, 127, 128, 130, 131, 132, 134, 135 VIN[19:0] I GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 8 of 90 Table 1-1: Pin Descriptions (Continued) Number 136 Symbol CPU_SEL Type I Description Host Interface mode select. When set HIGH, the GS1503B is configured for Host Interface Mode A. When set LOW, the GS1503B is configured for Host Interface Mode B. Audio format select. In Multiplex Mode, AM[1:0] indicates the input audio data format. In Demultiplex Mode, AM[1:0] indicates the output audio data format. AM[1] is the MSB and AM[0] is the LSB. See Table 4-16 and Table 5-13. Video standard select. VM[3] is the MSB and VM[0] is the LSB. See Table 4-1 or Table 5-1. Device reset. Active LOW. 137, 138 AM[1:0] I 139, 140, 141, 142 143 VM[3:0] I RESET I GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 9 of 90 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Table 2-1: Absolute Maximum Ratings Parameter Supply Voltage Input Voltage (any input) Operating Temperature Storage temperature Lead Temperature (soldering, 10 sec.) Value -0.3V to 4.0V -0.3 to 5.5V 0°C to 70°C -65°C to 150°C 260°C 2.2 DC Electrical Characteristics Table 2-2: DC Electrical Characteristics TA = 0°C to 70°C unless otherwise shown. Parameter Supply Voltage Supply Current Input Current Hi-Z Output Leakage Current Output Voltage, Logic High Output Voltage, Logic Low Input Voltage, Logic High Input Voltage, Logic Low Input Capacitance Output Capacitance I/O Capacitance Symbol VDD IDD IIN IOZ VOH VOL VIH VIL CI CO CIO Conditions 3.3V operating range VDD = 3.3V – – IOH = -12mA IOL = 12mA TTL Level TTL Level f = 1MHz, VDD = 0V f = 1MHz, VDD = 0V f = 1MHz, VDD = 0V Min 3.0 Typ 3.3 270 Max 3.6 Units V mA -1 -1 VDD-0.4 – 2.0 – – – – – – – – – – – – – 1 1 – 0.4 – 0.8 10 10 10 μA μA V V V V pF pF pF GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 10 of 90 2.3 AC Electrical Characteristics Table 2-3: AC Electrical Characteristics VDD = 3.3V ± 5%, TA = 0°C to 70°C unless otherwise shown. Parameter Video Clock Frequency Video Clock Pulse Width Low Video Clock Pulse Width High Video Input Data Setup Time Video Input Data Hold Time Video Output Data Delay Time Video Output Data Hold Time Audio Clock Frequency Audio Clock Pulse Width Low Audio Clock Pulse Width High Audio Input Data Setup Time Audio Input Data Hold Time Audio Output Data Delay Time Audio Output Data Hold Time Reset Pulse Width Device Latency Symbol Conditions – Min – 5.0 5.0 3.5 1.0 – 1.0 – 60 60 10.5 1.0 – 1.0 1 53 53 Typ 74.25 – – – – – – 6.144 – – – – – – – 53 53 Max 80 – – – – 8.5 – – – – – – 20.0 – – 53 53 Units MHz ns ns ns ns ns ns MHz ns ns ns ns ns ns ms PCLKs tVPWL tVPWH tVS tVH tVOD tVOH – – – – With 10pF loading With 10pF loading – tAPWL tAPWH tAS tAH tAOD tAOH tRESET – – – – – With 10pF loading With 10pF loading – Multiplexer Mode Demultiplexer Mode t VS VCLK t VH Data* * VIN[19:0], EXTF, EXTH, PKTEN, PKT[7:0] Figure 2-1: Video Data Input Setup & Hold Time GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 11 of 90 t VOH t VOD VCLK Data* * VOUT[19:0], EXTF, EXTH, PKTEN, PKT[7:0] Figure 2-2: Video Data Output Delay & Hold Time t AS ACLKA/B t AH Data* * WCINA, AIN1/2, AIN3/4, WCINB, AIN5/6, AIN7/8 Figure 2-3: Audio Data Input Setup & Hold Time t AOH t AOD ACLKA/B Data* * AOUT1/2, AOUT3/4, AOUT5/6, AOUT7/8 Figure 2-4: Audio Data Output Delay & Hold Time VDD(min) VDD t RESET RESET t RESET Figure 2-5: Reset Timing GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 12 of 90 2.4 Solder Reflow Profiles Temperature 60-150 sec. 10-20 sec. 230˚C 220˚C 3 ˚C/sec max 183˚C 6˚C/sec max 150˚C 100˚C 25˚C Time 120 sec. max 6 min. max Figure 2-6: Maximum Pb-Free Solder Reflow Profile (Preferred) Temperature 60-150 sec. 20-40 sec. 260˚C 250˚C 3 ˚C/sec max 217˚C 6˚C/sec max 200˚C 150˚C 25˚C Time 60-180 sec. max 8 min. max Figure 2-7: Standard Eutectic Solder Reflow Profile GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 13 of 90 3. Host Interface Table 3-1: Mode A (CPU_SEL set HIGH) Parameter Read Cycle Time Read Chip Select Setup Time Read Address Setup Time Read Data Output Delay Time Read Data Hold Time Write Cycle Time Write Chip Select Setup Time Write Address Setup Time Write Data Setup Time Write Data Hold Time Number 1 2 3 4 5 6 7 8 9 10 Min 50 0 15 – 0 50 10 10 10 0 Typ – – – – – – – – – – Max – – – 15 – – – – – – Units ns ns ns ns ns ns ns ns ns ns Read Cycle 1 CPUADR[8:0] 2 CPUCS Address 7 Write Cycle 6 Address CPURE 3 CPUWE 8 CPUDAT[7:0] 4 Valid Data 5 Valid Data 9 10 Figure 3-1: Host Interface Mode A Timing (CPU_SEL set HIGH) GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 14 of 90 Table 3-2: Mode B Read Cycle (CPU_SEL set LOW) Parameter Read Address Cycle Time Read Cycle Time Read Enable Setup Time Read Address Setup Time Read Chip Select Setup Time Read Chip Select Hold Time Read Data Output Delay Time Read Data Hold Time Number 1 2 3 4 5 6 7 8 Min 80 80 20 20 10 0 – 0 Typ – – – – – – – – Max – – – – – – 10 – Units ns ns ns ns ns ns ns ns 1 CPUADR[1:0] 01 1 00 2 11 8 CPUDAT[7:0] Upper Address Lower Address 7 Read Data CPUCS CPUWE 5 4 3 6 5 4 3 6 3 5 6 Figure 3-2: Host Interface Mode B Read Cycle Timing (CPU_SEL set LOW) Table 3-3: Mode B Write Cycle (CPU_SEL set LOW) Parameter Write Address Cycle Time Write Cycle Time Write Enable Setup Time Write Address Setup Time Write Chip Select Setup Time Write Chip Select Hold Time Write Data Setup Time Write Data Hold Time Number 1 2 3 4 5 6 7 8 Min 80 80 20 20 10 0 30 0 Typ – – – – – – – – Max – – – – – – – – Units ns ns ns ns ns ns ns ns GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 15 of 90 1 CPUADR[1:0] 01 1 00 2 10 8 CPUDAT[7:0] Upper Address Lower Address Write Data 7 CPUCS CPUWE 5 4 3 6 5 4 3 6 3 5 6 Figure 3-3: Host Interface Mode B Write Cycle Timing (CPU_SEL set LOW) Table 3-4: Host Interface Mode B Control Codes CPUADR[1:0] 01 00 11 10 Data Bus Operation Upper Address Lower Address Read Data Write Data GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 16 of 90 4. Detailed Description 4.1 Multiplex Mode 4.1.1 Functional Overview The GS1503B HD Embedded Audio CODEC fully supports the multiplexing of Audio Data Packets, Audio Control Packets and Arbitrary Data Packets as per SMPTE 291M and 299M. The device can be configured to operate with all video standards defined in SMPTE 292M, levels A through M. The GS1503B also supports the 1080/24PsF, 25PsF and 30PsF video formats as described in SMPTE RP211. The video input format can be one of the following configurations: • • 10-bit Y and Cb/Cr input with TRS and Line Numbers 8-bit Y and Cb/Cr input with TRS and Line Numbers 10-bit or 8-bit Y and Cb/Cr input without TRS and Line Numbers (GS1503B will insert TRS and Line Numbers based on EXTF and EXTH inputs) • • • 20-bit scrambled input 20-bit scrambled output 10-bit Y and Cb/Cr output The video output format can be one of the following configurations: Up to a maximum of 8 channels of 48kHz digital audio can be multiplexed per device. The audio input format can be selected as either AES/EBU, or one of two serial audio data input modes. A maximum of 16 channels of audio can be multiplexed by serially cascading two devices. Audio control packets, as defined in SMPTE 299M, can also be multiplexed to provide information to receivers about the nature of the embedded audio data. The contents of the audio control packet can be programmed via the Host Interface. The GS1503B will also multiplex arbitrary data packets as defined in SMPTE 291M. The arbitrary data packets can serve as an auxiliary data signal for proprietary applications. The GS1503B can be configured to multiplex arbitrary data packets, input via the Host Interface or using dedicated external pins. Up to a maximum of 255 8-bit words can be multiplexed (excluding Ancillary Data Flags and Checksum). To use the GS1503B in Multiplex Mode, set the MUX/DEMUX external pin LOW. GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 17 of 90 4.2 Video Standard The video standard is selected from the VM[3:0] external pins or VM[3:0] bits 3-0 in Host Interface register 000h. To configure the video standard via the Host Interface, VM_SEL bit 7 in Host Interface register 000h must be set HIGH. The GS1503B will default to the VM[3:0] external pin setting. The supported video standards are listed in Table 4-1. Table 4-1: Supported Video Standards VM [3:0] 1110b 1100b 1000b 1010b 1111b 0010b 0100b 0110b 0000b 0001b 0011b 0101b 0111b Input Format 1035i (30 & 30/1.001 Hz) 1080i (25 Hz) 1080i/1080sF (30 & 30/1.001 Hz) 1080i/1080sF (25 Hz) 1080sF (24 & 24/1.001 Hz) 1080p (30 & 30/1.001 Hz) 1080p (25 Hz) 1080p (24 & 24/1.001 Hz) 720p (60 & 60/1.001 Hz) 720p (30 & 30/1.001 Hz) 720p (50 Hz) 720p (25 Hz) 720p (24 & 24/1.001 Hz) Reference SMPTE Document 260M 295M 274M, RP211 274M, RP211 RP211 274M 274M 274M 296M 296M 296M 296M 296M SMPTE 292M Level A, B C D, E F G, H I J, K L, M All other settings are reserved Table 4-2: Register Settings Name VM_SEL Description 0: External pin select 1: Register select Address 000 Bit 7 Setting 1 Default 0 VM[3:0] Video formal selection (VM[3] is MSB) 000 3-0 See Table 4-1 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 18 of 90 4.3 Video Input Format 4.3.1 10-bit Y and Cb/Cr Input Video with TRS and Line Numbers GS1503B Y[9:0] VIN[19:10] Cb / Cr [9:0] VIN[9:0] EXTF +3.3V EXTH DSCBYPASS Figure 4-1: Configuration for 10-bit Y and Cb/Cr Input Video with TRS and Line Numbers 3 0 CRC0 CRC1 10-bit LN0 XYZ LN1 8 XYZ 000 000 3FF 3FF 000 000 V0 Y, C b/Cr Video EAV SAV Figure 4-2: Video Input Format 10-bit with TRS and Line Numbers Table 4-3: Register Settings Name EXT_SEL Description 0: EXTH/EXTF output select 1: EXTH/EXTF input select Address 001 Bit 3 Setting 0 Default 0 8BIT_SEL 0: 10-bit mode select 1: 8-bit mode select 001 1 0 DSCBYPASS 0: Descrambling enabled 1: Bypass descrambling 001 0 1 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 Vn 0 0 19 of 90 4.3.2 8-bit Y and Cb/Cr Input Video With TRS and Line Numbers GS1503B Y[9:0] VIN[19:12] VIN[11:10] C b/ C r[9:0] VIN[9:2] EXTF VIN[1:0] +3.3V EXTH DSCBYPASS Figure 4-3: Configuration for 8-bit Y and Cb/Cr Input Video with TRS and Line Numbers 8-bit 0 3 LN0 LN1 8 XY XY 00 00 00 00 V0 Y, C b/Cr Video EAV SAV Figure 4-4: Video Input Format 8-bit with TRS and Line Numbers Table 4-4: Register Settings Name EXT_SEL Description 0: EXTH/EXTF output select 1: EXTH/EXTF input select Address 001 Bit 3 Setting 0 Default 0 8BIT_SEL 0: 10-bit mode select 1: 8-bit mode select 001 1 1 DSCBYPASS 0: Descrambling enabled 1: Bypass descrambling 001 0 1 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 Vn FF FF 0 0 20 of 90 4.3.3 10-bit or 8-bit Y and Cb/Cr Input Without TRS and Line Numbers The GS1503B will insert TRS and Line Numbers based on EXTF and EXTH inputs. See Figure 4-6 for timing. In progressive format video standards, a high-to-low edge signal must be input at the EXTF external pin on every frame to indicate the position of line 1. See Figure 4-7. GS1503B Y[9:0] VIN[19:10] C b / Cr [9:0] EXTF EXTH +3.3V VIN[9:0] DSCBYPASS Figure 4-5: Configuration for 10-bit or 8-bit Y and Cb/Cr Input Video without TRS and Line Numbers 8/10-bit 0 3 8 V0 Y, Cb /C r Video 4 VCLK EXTH EXTF Figure 4-6: Video Input Format (8/10-bit without TRS and Line Numbers) 8/10-bit 0 3 8 V0 Y, C b/C r Video 4 VCLK EXTH EXTF Line 1 Figure 4-7: 15 Video Input Format (Progressive) GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 Vn Vn 21 of 90 Table 4-5: Register Settings Name EXT_SEL Description 0: EXTH/EXTF output select 1: EXTH/EXTF input select Address 001 Bit 3 Setting 1 Default 0 8BIT_SEL 0: 10-bit mode select 1: 8-bit mode select 001 1 0 or 1 0 DSCBYPASS 0: Descrambling enabled 1: Bypass descrambling 001 0 1 0 4.3.4 20-bit Scrambled Input GS1503B Y/C b / Cr [19:0] VIN[19:0] DSCBYPASS Figure 4-8: Configuration for 20-bit Scrambled Input Table 4-6: Register Settings (Default Mode) Name EXT_SEL Description 0: EXTH/EXTF output select 1: EXTH/EXTF input select Address 001 Bit 3 Setting 0 Default 0 8BIT_SEL 0: 10-bit mode select 1: 8-bit mode select 001 1 0 0 DSCBYPASS 0: Descrambling enabled 1: Bypass descrambling 001 0 0 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 22 of 90 4.4 Video Output Format 4.4.1 20-bit Scrambled Output GS1503B Y/Cb / C r [19:0] VOUT[19:0] SCRBYPASS Figure 4-9: Configuration for 20-bit Scrambled Output Table 4-7: Register Settings (Default Mode) Name SCRBYPASS Description 0: SMPTE 292M scrambling enabled 1: Bypass SMPTE 292M scrambling Address 001 Bit 2 Setting 0 Default 0 4.4.2 10-bit Y and Cb/Cr Output GS1503B Y[9:0] VOUT[19:10] VOUT[9:0] C b / Cr [9:0] +3.3V SCRBYPASS Figure 4-10: Configuration for 10-bit Y and Cb/Cr Output GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 23 of 90 Table 4-8: Register Settings Name SCRBYPASS Description 0: SMPTE 292M scrambling enabled 1: Bypass SMPTE 292M scrambling Address 001 Bit 2 Setting 1 Default 0 4.5 Video Data Processing 4.5.1 Video Signal Input Detection The GS1503B will set the VIDEO_DET external pin HIGH when three consecutive TRS are detected in the input video signal. Also, the VIDEO_DET bit of Host Interface register 000h is set HIGH. Table 4-9: Register Settings Name VIDEO_DET Description Video input signal detection (1: Detection) Address 000 Bit 6 Setting – Default 0 4.5.2 Video Input CRC Error Detection The GS1503B will set the CRC_ERR external pin HIGH when a CRC error is detected in the input video signal. Also, the CRC_ERR bit 5 of Host Interface register 000h is set HIGH. The number of CRC errors accumulated in one video frame can be read form CRC_CNT[11:0] in Host Interface registers 006h and 007h. Table 4-10: Register Settings Name CRC_ERR CRC_CNT[11:0] Description Video input signal CRC error detection (1: Detection) Video input signal CRC error accumulation in 1 video frame Address 000 006 007 Bit 5 3-0 7-0 Setting – – Default 0 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 24 of 90 4.5.3 Video Output CRC Insertion When the CRC_INS bit 4 of Host Interface register 000h is set HIGH, the GS1503B will re-calculate the video line CRC words. The re-calculated CRC words are inserted in the video output signal. When CRC_INS is set LOW, the line CRC words are not updated and existing CRC words at the input of the device will be output unchanged. Table 4-11: Register Settings Name CRC_INS Description Video line CRC insertion (1: Insertion) Address 000 Bit 4 Setting 1 Default 1 4.5.4 Illegal Code Re-mapping When LIMIT_ON bit 4 of Host Interface register 008h is set HIGH, input video words between 000-003 are re-mapped to 004, and values between 3FC-3FF are re-mapped to 3FB. Valid only when the EXT_SEL bit 3 of Host Interface register 000h is set HIGH. Table 4-12: Register Settings Name EXT_SEL Description 0: EXTH/EXTF output select 1: EXTH/EXTF input select Address 001 Bit 3 Setting 1 Default 0 LIMIT_ON Illegal code re-mapping (1: Enabled) 008 4 1 0 4.5.5 Input Blanking When VBLK_INS bit 3 of Host Interface register 008h is set HIGH, the input video vertical blanking will be set to 040h for the Luma channel and 200h for the Chroma channel. When HBLK_INS bit 2 of Host Interface register 008h is set HIGH, the input video horizontal blanking will be set to 040h for the Luma channel and 200h for the Chroma channel. The TRS, line number and CRC words will also be set to blanking values. The blanking function is performed at the output of the GS1503B video data stream. If the HBLK_INS bit is set HIGH, any multiplexed audio will be replaced with blanking codes. Table 4-13: Register Settings Name VBLK_INS HBLK_INS Description Input vertical blanking (1: Enabled) Input horizontal blanking (1: Enabled) Address 008 008 Bit 3 2 Setting 1 1 Default 0 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 25 of 90 4.5.6 Line Number Insertion When LN_INS bit 1 of Host Interface register 008h is set HIGH, the GS1503B will insert line numbers into the video data stream. When set LOW, existing line numbers will remain in the output video stream. When EXT_SEL bit 3 of Host Interface register 001h is set HIGH, line numbers will be inserted based on the timing of EXTH and EXTF input signals. Table 4-14: Register Settings Name LN_INS Description Line number insertion (1: Enabled) Address 008 Bit 1 Setting 1 Default 1 4.5.7 TRS Word Insertion When TRS_INS bit 0 of Host Interface register 008h is set HIGH, the GS1503B will insert TRS codes into the video data stream. When set LOW, existing TRS codes will remain in the output video stream. When EXT_SEL bit 3 of Host Interface register 001h is set HIGH, TRS codes will be inserted based on the timing of EXTH and EXTF input signals. Table 4-15: Register Settings Name TRS_INS Description TRS word insertion (1: Enabled) Address 008 Bit 0 Setting 1 Default 1 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 26 of 90 4.6 Audio Data Processing 4.6.1 Digital Audio Input Format The GS1503B will accept two audio input formats, AES/EBU digital audio input and serial input, as listed in Table 4-16. Serial input can be formatted in the following two modes. See Figure 4-11. • • 24-bit Left Justified; MSB first 24-bit Right Justified; MSB last The audio input format is configured using the AM[1:0] external pins or via AM[1:0] bits 1-0 in Host Interface register 010h. To configure the audio input format via the Host Interface, AM_SEL bit 7 in Host Interface register 010h must be set HIGH. The GS1503B will default to the AM[1:0] external pin setting. Table 4-16: Audio Input Formats AM[1:0] 0 1 2 Audio Input Format Serial audio input: 24-bit Left Justified; MSB first Serial audio input: 24-bit Right Justified; MSB last AES/EBU audio input Table 4-17: Register Settings Name AM_SEL Description 0: External pin setting 1: Register setting Address 010 Bit 7 Setting 1 Default 0 AM[1:0] Audio input format selection (AM[1] is MSB) 010 1-0 See Table 4-11 0 Channel 1 WCINA/WCINB MSB MODE0 23 LSB MODE1 0 MODE2 (AES/EBU) 34 24-bit Audio Sample Word Validity Bit User Data Bit Channel Status Bit Parity Bit 0 23 2728293031 0 34 0 MSB 23 LSB 0 Channel 2 0 23 2728293031 24-bit Audio Sample Word VUCP Sync Preamble Sync V U C P Preamble Figure 4-11: Audio Input Formats GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 27 of 90 4.6.2 Digital Audio Input Timing 4.6.2.1 AES/EBU Format Input A 6.144MHz (128fs) audio clock must be supplied to the ACLKA and ACLKB inputs. ACLKA is used to clock the AES/EBU digital audio signal for channels 1 to 4 (AIN1/2 and AIN3/4) into the device. ACLKB is used to clock the AES/EBU digital audio signal for channels 5 to 8 (AIN5/6 and AIN7/8) into the device. In AES/EBU input mode, the WCINB and WCINB external pins should be grounded. See Figure 4-12 for timing. GS1503B Y/C b / Cr [19:0] VIN[19:0] Audio Channels 1 & 2 Audio Channels 3 & 4 6.144MHz (128 fs) AIN1/2 AIN3/4 ACLKA WCINA Audio Channels 5 & 6 Audio Channels 7 & 8 6.144MHz (128 fs) AIN5/6 AIN7/8 ACLKB WCINB 6.144MHz ACLKA/B AIN1/2, AIN3/4 AIN5/6, AIN7/8 Figure 4-12: AES/EBU Input Configuration and Timing GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 28 of 90 4.6.2.2 Serial Audio Input Modes A 6.144MHz (128fs) audio clock must be supplied to the ACLKA and ACLKB inputs. The GS1503B divides this clock by 2 to clock the 3.072MHz audio data. An audio word clock at 48kHz (fs) must also be supplied to the WCINA and WCINB inputs, as shown in Figure 4-13. The AUDIO_CS[183:0] bits in Host Interface registers 058h to 06Eh can be used to enter the 23 8-bit bytes of the Audio Channel Status Block, as defined in AES3-1992. NOTE: The CRC byte is generated internally by the GS1503B. The GS1503B will default to Professional audio mode with 24-bit word length and emphasis off. See Table 4-34. GS1503B Y/C b / Cr [19:0] VIN[19:0] Audio Channels 1 & 2 Audio Channels 3 & 4 6.144MHz (128 fs) 48kHz (fs) AIN1/2 AIN3/4 ACLKA WCINA Audio Channels 5 & 6 Audio Channels 7 & 8 6.144MHz (128 fs) 48kHz (fs) AIN5/6 AIN7/8 ACLKB WCINB 64 CLKs ACLKA/B 64 CLKs WCINA/B AIN1/2, AIN3/4 AIN5/6, AIN7/8 Figure 4-13: Serial Audio Input Configuration and Timing GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 29 of 90 4.6.3 Audio Clock Phase Locked Loop Figure 4-14 shows the configuration for deriving the 6.144MHz audio clock in AES/EBU audio input mode. The GS1503B will internally synchronize the AES/EBU audio input to the corresponding ACLK, using the clock extracted from the AES/EBU bi-phase mark encoding. This configuration is not required for serial audio input modes. 6.144MHz (128 fs) GS1503B Y/C b / Cr [19:0] VIN[19:0] Audio Channels 1 & 2 Audio Channels 3 & 4 AIN1/2 AIN3/4 ACLKA PLLCNTA Low Pass Filter VCXO 24.576MHz 4 ÷ Audio Channels 5 & 6 Audio Channels 7 & 8 AIN5/6 AIN7/8 ACLKB PLLCNTB Low Pass Filter VCXO 24.576MHz 4 ÷ 6.144MHz (128 fs) Figure 4-14: Block Diagram of GS1503B Audio Clock PLL 4.6.4 Audio Signal Input Detection The audio input signal detect registers will be set HIGH in AES/EBU audio mode when the preamble of the audio input data is detected 3 times consecutively. In serial audio input mode, the GS1503B will set the audio input signal detect registers HIGH when a 48kHz word clock is detected at the corresponding inputs. Audio channels 1 to 4 will be set when WCINA is validated, and audio channels 5 to 8 when WCINB is validated. Host Interface register 010h, bits 6-3, report the individual audio channels pairs detected. Table 4-18: Register Settings Name AUD7/8_DET AUD5/6_DET Description Ch7/8 Audio input signal detection (1:Detection) Ch5/6 Audio input signal detection (1:Detection) Address 010 010 Bit 6 5 Setting – – Default 0 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 30 of 90 Table 4-18: Register Settings Name AUD3/4_DET AUD1/2_DET Description Ch3/4 Audio input signal detection (1:Detection) Ch1/2 Audio input signal detection (1:Detection) Address 010 010 Bit 4 3 Setting – – Default 0 0 4.6.5 Audio Channel Status CRC Error Detection In AES/EBU audio mode, the GS1503B will check the Channel Status CRC for errors. If any Channel Status CRC errors are detected in an AES/EBU audio input channel pair, the corresponding bit in Host Interface register 011h will be set HIGH. In serial audio input mode, the CRC error flags are always set LOW. Table 4-19: Register Settings Name ACRC7/8_ERR Description Ch7/8 Audio Channel Status CRC error detection (1: Detection) Address 011 Bit 3 Setting – Default 0 ACRC5/6_ERR Ch5/6 Audio Channel Status CRC error detection (1: Detection) 011 2 – 0 ACRC3/4_ERR Ch3/4 Audio Channel Status CRC error detection (1: Detection) 011 1 – 0 ACRC1/2_ERR Ch1/2 Audio Channel Status CRC error detection (1: Detection) 011 0 – 0 4.6.6 Audio Input Parity Error Detection In AES/EBU audio mode, the GS1503B will check for Audio Parity errors. If any Audio Parity errors are detected in an AES/EBU audio input channel pair, the corresponding bit in Host Interface register 012h will be set HIGH. In serial audio input mode, the Audio Parity error flags are always set LOW. Table 4-20: Register Settings Name AP7/8_ERR AP5/6_ERR AP3/4_ERR AP1/2_ERR Description Ch7/8 Audio parity error detection (1: Detection) Ch5/6 Audio parity error detection (1: Detection) Ch3/4 Audio parity error detection (1: Detection) Ch1/2 Audio parity error detection (1: Detection) Address 012 012 012 012 Bit 3 2 1 0 Setting – – – – Default 0 0 0 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 31 of 90 4.6.7 Audio Channel Status CRC Insert Function When bits 7-4 of Host Interface register 011h are set HIGH, the GS1503B will re-calculate the Channel Status CRC word for the corresponding audio input channel pair. The re-calculated Channel Status CRC word is multiplexed into the audio data packet as per SMPTE 299M. When bits 3-0 of Host Interface register 011h are set LOW, the Channel Status CRC word is not updated and the existing Channel Status CRC word will be multiplexed. In serial audio input mode, these registers should be set LOW. Table 4-21: Register Settings Name ACRC7/8_INS ACRC5/6_INS ACRC3/4_INS ACRC1/2_INS Description Ch7/8 Audio Channel Status CRC insertion (1: Insertion) Ch5/6 Audio Channel Status CRC insertion (1: Insertion) Ch3/4 Audio Channel Status CRC insertion (1: Insertion) Ch1/2 Audio Channel Status CRC insertion (1: Insertion) Address 011 011 011 011 Bit 7 6 5 4 Setting 1 1 1 1 Default 0 0 0 0 4.7 Audio Data Packets 4.7.1 Audio Data Packet Structure Figure 4-15 shows the structure of the audio data packets as defined in SMPTE 299M. The audio data packets are multiplexed into the Chroma channel of the video data stream. Table 4-22 lists the description of the individual audio data packet words. Note that the GS1503B will automatically generate certain audio data packet words. User Data Words 10-bit ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 DBN CH1 CH2 CH3 ADF CH4 CLK DID DC ECC Protected Figure 4-15: Audio Data Packet Structure GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 CS 32 of 90 Table 4-22: Audio Data Packet Word Descriptions Name ADF No of Words 3 Description Ancillary Data Flag Data 000h 3FFh 3FFh Auto-Generation Yes DID 1 Audio Group Data ID 2E7h 1E6h 1E5h 2E4h See Table 4-23 in Section 4.7.2 DBN DC CLK CH1 CH2 CH3 CH4 ECC0-5 1 1 2 4 4 4 4 6 Data Block Number Data Count Audio Clock Phase Data Channel 1 audio data Channel 2 audio data Channel 3 audio data Channel 4 audio data Error correction code for lower 8 bits of first 24 words Checksum. Calculates the sum of lower 9 bits of 22 words from DID Repeat 1-255 218h – – – – – – Yes Yes Yes Yes CS 1 – Yes 4.7.2 Audio Data Packet DID Setting The audio group DID for audio input channels 1 to 4 (AIN1/2 and AIN3/4) is set in DATAIDA[1:0] bits 1-0 of Host Interface register 014h. The audio group DID for audio input channels 5 to 8 (AIN5/6 and AIN7/8) is set in DATAIDB[1:0] bits 3-2 of Host Interface register 014h. Table 4-23 shows the 2-bit Host Interface setting for the corresponding audio group DID. When CASCADE is set LOW (external pin or register), the GS1503B will default to audio groups 1 and 2, where AIN1/2 and AIN3/4 will be multiplexed with audio group 1 DID, and AIN5/6 and AIN7/8 with audio group 2 DID. Table 4-23: Audio Data Packet Group DID Host Interface Setting Audio Group 1 2 3 4 10-bit Data 2E7h 1E6h 1E5h 2E4h Host Interface Register Setting (2-bit) 11b 10b 01b 00b GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 33 of 90 Table 4-24: Register Settings (CASCADE set LOW) Name DATAIDA [1-0] DATAIDB [1-0] Description Ch1-4 Audio data packet DID setting Ch5-8 Audio data packet DID setting Address 014 014 Bit 1-0 3-2 Setting See Table 4-23 Default 11b 10b When CASCADE is set HIGH (external pin or register), the GS1503B will default to audio groups 3 and 4, where AIN1/2 and AIN3/4 will be multiplexed with audio group 3 DID, and AIN5/6 and AIN7/8 with audio group 4 DID. Table 4-25: Register Settings (CASCADE set HIGH) Name DATAIDA [1-0] DATAIDB [1-0] Description Ch1-4 Audio data packet DID setting Ch5-8 Audio data packet DID setting Address 014 014 Bit 1-0 3-2 Setting See Table 4-23 Default 01b 00b 4.7.3 Audio Channel Multiplex Enable Multiplexing of individual audio channels is enabled using the CHACT[7:0] bits 7-0 of Host Interface register 013h. When set HIGH, the corresponding audio channel is multiplexed into the audio data packet in the Chroma video data stream. CHACT7 corresponds to audio input channel 8 and CHACT0 corresponds to audio input channel 1. When all bits are set LOW, no audio data packets will be multiplexed and the GS1503B will be in bypass mode. Table 4-26: Register Settings Name CHACT7 CHACT6 CHACT5 CHACT4 CHACT3 CHACT2 CHACT1 CHACT0 Description Ch8 multiplex enable (1: Enabled) Ch7 multiplex enable (1: Enabled) Ch6 multiplex enable (1: Enabled) Ch5 multiplex enable (1: Enabled) Ch4 multiplex enable (1: Enabled) Ch3 multiplex enable (1: Enabled) Ch2 multiplex enable (1: Enabled) Ch1 multiplex enable (1: Enabled) Address 013 013 013 013 013 013 013 013 Bit 7 6 5 4 3 2 1 0 Setting – – – – – – – – Default 1 1 1 1 1 1 1 1 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 34 of 90 4.8 Video Switching Line Setting The video switching point for field 1 and field 2 can be configured via the GS1503B Host Interface. The SW_LNA[12:0] register is used to configure the video switching line for field 1, and SW_LNB[12:0] to set video switching line for field 2. In progressive format video standards, only the SW_LNA[12:0] register is used. The default settings are line 7 for field 1 and line 569 for field 2 as defined in SMPTE 299M. The GS1503B will not multiplex any audio data packets in the line immediately after the video switching point. For example, with the default setting of line 7 field 1, there will be no audio data packets in line 8. The next packets will appear on line 9. Audio control packets will be multiplexed once per field, two lines after the video switching point (on line 9, using the previous example). Arbitrary data packets will not be multiplexed in the two lines following the video switching point . NOTE: The SMPTE 299M standard defines the video switching point as lines 7 and 569. If the SW_LNA[12:0] and SW_LNB[12:0] registers are programmed with values other than lines 7 and 569, the output of the GS1503B is not guaranteed to be compatible with all HD audio demultiplex systems. With non-SMPTE 299M compliant switch line settings, the user should avoid inputting a video data stream to the GS1503B, which already contains embedded audio data and control packets. For reliable operation, non-SMPTE 299M compliant video data streams with embedded audio should not be used in conjunction with the GS1503B in Multiplex Mode. Table 4-27: Register Settings Name SW_LNA[12:0] Description Video Field 1 switching point setting Address 004 005 Bit 4-0 7-0 4-0 7-0 Setting – Default 7d SW_LNB[12:0] Video Field 2 switching point setting 002 003 – 569d GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 35 of 90 4.9 Multiplex Cascade Mode Two GS1503B devices can be cascaded in series to allow up to 16 channels of audio to be multiplexed (only one device requires CASCADE to be set HIGH). Figure 4-16 shows the cascade architecture for a 16-channel system. To configure the GS1503B for cascade mode, the CASCADE external pin or CASCADE bit 7 of Host Interface register 014h is set HIGH. When set HIGH, the GS1503B will default to audio groups 3 and 4. When set LOW, the GS1503B will default to audio groups 1 and 2. GS1503B Y/Cb /Cr [19:0] VIN[19:0] VOUT[19:0] Y/C b /Cr [19:0] VIN[19:0] GS1503B VOUT[19:0] Y/C b /C r [19:0] Audio Group 1 Audio Channels 1 & 2 Audio Channels 3 & 4 AIN1/2 AIN3/4 Audio Group 3 Audio Channels 9 & 10 Audio Channels 11 & 12 AIN1/2 AIN3/4 Audio Group 2 Audio Channels 5 & 6 Audio Channels 7 & 8 AIN5/6 AIN7/8 Audio Group 4 Audio Channels 13 & 14 Audio Channels 15 & 16 +3.3V AIN5/6 AIN7/8 CASCADE CASCADE Figure 4-16: Multiplexing 16 Channels of Audio using Cascade Architecture Table 4-28: Register Settings Name CASCADE Description Cascade enable (1: Enabled) Address 014 Bit 7 Setting 1 Default 0 When CASCADE is set LOW, the GS1503B will multiplex audio data and control packets as shown in Figure 4-17 (NOTE: Only the Chroma channel of the video data stream is shown). Any existing audio data or control packets will be deleted and replaced with blanking data before the new packets are multiplexed. New packets are multiplexed immediately after the two video line CRC words. When CASCADE is set HIGH, the GS1503B will multiplex the audio data and control packets immediately after the existing packets, as shown in Figure 4-18. Avoid multiplexing new ancillary data packets with the same audio group DID as existing packets. GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 36 of 90 CRC EAV Blank (200 h ) Video Signal before GS1503B (no existing Audio Data Packets) Audio Group 1 Audio Group 2 CRC EAV Blank (200h) Video Signal before GS1503B (with existing Audio Data Packets) Audio Group 1 (New) Audio Group 2 (New) CRC EAV Blank (200h ) Video Signal after GS1503B Insertion of Audio Groups 1 & 2 (CASCADE = 0) Figure 4-17: Insertion of Audio Groups 1 & 2, without / with existing packets) Audio Group 1 Audio Group 2 CRC EAV Blank (200h) Video Signal before GS1503B (with existing Audio Data Packets) Audio Group 1 (Old) Audio Group 2 (Old) Audio Group 3 (New) Audio Group 4 (New) CRC EAV Blank (200 h) Video Signal after GS1503B Insertion of Audio Groups 3 & 4 (CASCADE = 1) Figure 4-18: Insertion of Audio Groups 3 & 4 in Cascade mode The GS1503B assumes that the ancillary data space from the first blanking location to the SAV contains no ancillary data packets. Existing ancillary data packets must be GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 37 of 90 SAV LN SAV LN SAV LN SAV LN SAV LN contiguous from the beginning of the HANC space or the GS1503B will overwrite existing packets with blanking before multiplexing new packets. See Figure 4-19. Audio Group 1 Blank (200h) Audio Group 2 CRC EAV Blank (200 h) Video Signal before GS1503B (with space between EAV and existing Audio Data Packets) Audio Group 3 (New) Audio Group 4 (New) CRC EAV Blank (200 h ) Video Signal after GS1503B Insertion of Audio Groups 3 & 4 (CASCADE = 1) Figure 4-19: Insertion of Audio Groups 3 & 4 with space between EAV and audio 4.10 Audio Control Packets 4.10.1 Audio Control Packet Structure Figure 4-20 shows the structure of the audio control packet as defined in SMPTE 299M. An audio control packet is multiplexed once per field in the Luma channel of the video data stream. Table 4-29 lists descriptions of the individual audio control packet words. The GS1503B will automatically generate certain audio control packet words. User Data Words DEL1-2 DEL3-4 10-bit RSRV DBN RATE ADF ACT DID DC Figure 4-20: Audio Control Packet Structure GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 CS AF SAV LN SAV LN 38 of 90 Table 4-29: Audio Control Packet Word Descriptions Name ADF No of Words 3 Description Ancillary Data Flag Data 000h 3FFh 3FFh Auto-Generation Yes DID 1 Audio Group Data ID 1E3h 2E2h 2E1h 1E0h See Table 4-30 in Section 5.8.2 DBN DC AF 1 1 1 Data Block Number Data Count Audio Frame Number 200h 10Bh – Yes Yes 9-bit Host Interface Setting 4-bit Host Interface Setting CHACT[7:0] setting 26-bit Host Interface setting 26-bit Host Interface setting 18-bit Host Interface setting Yes RATE 1 Sampling Frequency – ACT DEL1-2 1 3 Active Channel Ch1/2 Delay Data – – DEL3-4 3 Ch3/4 Delay Data – RSRV 2 Reserved Words 200h CS 1 Checksum. Calculates the sum of lower 9 bits of 15 words from DID – 4.10.2 Audio Control Packet DID Setting To multiplex audio control packets for audio channels 1 to 4 (inputs AIN1/2 and AIN3/4), the CTRONA bit 2 of Host Interface register 02Fh must be set HIGH. To multiplex audio control packets for audio channels 5 to 8 (inputs AIN5/6 and AIN7/8), the CTRONB bit 2 of Host Interface register 020h must be set HIGH. The audio control packet group DID for audio input channels 1 to 4 is set in CTRIDA[1:0] bits 1-0 of Host Interface register 02Fh. The audio control packet group DID for audio input channels 5 to 8 is set in CTRIDB[1:0] bits 3-2 of Host Interface register 020h. Table 4-30 shows the 2-bit Host Interface setting for the corresponding audio control packet group DID. When CASCADE is set LOW (external pin or register), the GS1503B will default to audio groups 1 and 2, where the audio control packet for AIN1/2 and AIN3/4 will be multiplexed with group 1 DID, and AIN5/6 and AIN7/8 with group 2 DID. Control packet data can be programmed via the corresponding registers in the Host Interface. GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 39 of 90 Table 4-30: Audio Control Packet Group DID Host Interface Settings Audio Group 1 2 3 4 10-bit Data 1E3h 2E2h 2E1h 1E0h Host Interface Register Setting (2-bit) 11b 10b 01b 00b Table 4-31: Register Settings Name CTRONA Description Ch1-4 Audio control packet multiplex enable (1: Enabled) Ch1-4 Audio control packet DID set Address 02F Bit 2 Setting 1 Default 1 CTRIDA[1:0] 02F 1-0 See Table 4-30 – 11b AF_NOA[8:0] Ch1-4 Audio frame number 030 031 0 7-0 3-1 0 0 RATEA[2:0] ASXA Ch1-4 Sampling frequency data Ch1-4 Synchronization (0:Synchronous; 1: Non-synchronous) 032 032 – – 0 0 DEL1-2A[25:0] Ch1/2 Delay data 033 034 035 036 1-0 7-0 7-0 7-0 1-0 7-0 7-0 7-0 1-0 7-0 7-0 2 – 0 DEL3-4A[25:0] Ch3/4 Delay data 037 038 039 03A – 0 RSRVA[17:0] Ch1-4 Reserved words 03B 03C 03D – 0 CTRONB Ch5-8 Audio control packet multiplex enable (1:Enabled) Ch5-8 Audio control packet DID set 020 1 1 CTRIDB[1:0] 020 1-0 See Table 4-30 – 10b AF_NOB[8:0] Ch5-8 Audio frame number 021 022 0 7-0 3-1 0 0 RATEB[2:0] ASXB Ch5-8 Sampling frequency data Ch5-8 Synchronization (0:Synchronous; 1: Non-synchronous) 023 023 – – 0 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 40 of 90 Table 4-31: Register Settings Name DEL1-2B[25:0] Description Ch5/6 Delay data Address 024 025 026 027 Bit 1-0 7-0 7-0 7-0 1-0 7-0 7-0 7-0 1-0 7-0 7-0 Setting – Default 0 DEL3-4B[25:0] Ch7/8 Delay data 028 029 02A 02B – 0 RSRVB[17:0] Ch5-8 Reserved words 02C 02D 02E – 0 4.11 Arbitrary Data Packets The GS1503B can multiplex arbitrary data packets according to SMPTE 291M. Typically, this consists of linear time code (LTC), vertical interval time code (VITC) or other user data, which is multiplexed once per video field. The GS1503B has two modes in which arbitrary data can be multiplexed into the Luma channel of the video data stream. A maximum of 255 user data words can be multiplexed in one packet. Figure 4-21 shows the structure of the arbitrary data packet. NOTE: Arbitrary data packets will not be multiplexed in the two lines following the video switching point (see Video Switching Line Setting on page 35). MSB UDW0[100] UDW1[101] UDW2[102] UDW3[103] ADF Not b8 Parity bit UDW252[1FC] UDW253[1FD] UDW251[1FB] UDW254[1FE] SDID CS DID LSB DC User Data Words Contents set in Host Interface registers Figure 4-21: Arbitrary Data Packet Structure GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 41 of 90 4.11.1 Arbitrary Data Multiplexing In External Pin Mode This is the default mode for multiplexing arbitrary data packets. The GS1503B will set the PKTENO external pin HIGH when arbitrary data can be input to the device. Two VCLK cycles after PKTENO goes HIGH, the user should set the PKTEN arbitrary packet enable pin HIGH. Two VCLK cycles after PKTEN is set HIGH, arbitrary data can be input at the PKT[7:0] bus. See Figure 4-22 for timing. The user is required to enter the following arbitrary data: Data ID (DID), Secondary Data ID (SDID), Data Count (DC) and User Data Words (UDW: maximum of 255), via the PKT[7-0] pins. This GS1503B automatically generates the Ancillary Data Flag (ADF), Checksum (CS) and bit 8 (Parity Bit) and bit 9 (Not bit 8). The PKTENO pin will be set HIGH on all video lines except the two lines following the video switching point. For example, with the default setting of line 7 field 1, PKTENO will not be set HIGH on lines 8 and 9. The switching point is set in the SW_LNA[12:0] and SW_LNB[12:0] Host Interface registers for field 1 and field 2 respectively. See Video Switching Line Setting on page 35. GS1503B Y/C / C [19:0] br VIN[19:0] Arbitrary Data Packet Timing PKTENO Arbitrary Data Input Enable PKTEN Arbitrary Data PKT[7:0] 2 CLKs VCLK 2 CLKs 2 CLKs 2 CLKs PKTENO PKTEN PKT[7:0] Arbitrary Data UDW252 UDW253 ADF ADF ADF DID DC Packet Automatically generated by the GS1503B Figure 4-22: Arbitrary Data Packet Input Timing Diagram GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 CS Arbitrary UDW250 UDW251 UDW254 UDW0 UDW1 UDW2 UDW3 SDID 42 of 90 4.11.2 Arbitrary Data Multiplexing in Host Interface Mode To select this mode, set ARBITMODE bit 0 in Host Interface register 050h HIGH. In this mode, the DID, SDID, DC and User Data Words must be programmed via the corresponding Host Interface registers. Set the video line number for field 1 and field 2 in which the arbitrary data packets are to be multiplexed using the ARBITLINEA[11:0] and ARBITLINEB[11:0] Host Interface registers respectively. The arbitrary data packet is multiplexed when ARBITON bit 1 in Host Interface register 050h is set HIGH. ARBITON should be set LOW during the programming of the arbitrary data packet in the Host Interface. ARBITLINEA[11:0] and ARBITLINEB[11:0] should not be set to the two line numbers following the line number set in the SW_LNA[12:0] and SW_LNB[12:0] Host Interface registers. For example, with the default setting of line 7 field 1, ARBITLINEA[11:0] should not be set to line 8 or 9. Table 4-32: Register Settings Name ARBITON Description Arbitrary packet multiplex enable (1: Enabled) Valid only when ARBITMODE is HIGH Address 050 Bit 1 Setting 1 Default 0 ARBITMODE Arbitrary packet mode selection (0: External pin mode; 1: Host mode) 050 0 1 0 ARBITDID[7-0] ARBITSDID[7-0] ARBITDC[7-0] ARBITLINEA[11:0] Arbitrary packet DID setting Arbitrary packet SDID setting Arbitrary packet DC setting Field 1 multiplexing line 051 052 053 054 055 7-0 7-0 7-0 3-0 7-0 3-0 7-0 7-0 – – – – 0 0 0 0 ARBITLINEB[11:0] Field 2 multiplexing line 056 057 – 0 ARBITUDW Arbitrary packet UDW setting 100-1FE – 0 Table 4-33: Multiplex Mode Host Interface Registers Control Item Video Name Description Address Bit R/W Default VM_SEL Video input format (external pin/internal register) configuration select. When set LOW, the video input format is configured via the VM[3:0] pins. When set HIGH, the video input format is configured via the "VM[3:0]" bits. Video signal detection flag. Set HIGH when 3 consecutive TRS are detected in the input video signal. 000 7 R/W 0 VIDEO_DET 000 6 R 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 43 of 90 Table 4-33: Multiplex Mode Host Interface Registers (Continued) Control Item Name Description Address Bit R/W Default CRC_ERR Video input signal CRC error detection. Set HIGH when a CRC error is detected in the input video signal. This register is refreshed on every video frame. Video CRC insertion. When set HIGH, the Luma and Chroma line CRC words are re-calculated and inserted into the output video signal. Video input format selection. See Table 4-1. Valid when "VM_SEL" is HIGH. External EXTH/EXTF input select. When set LOW, the EXTH and EXTF pins are configured as outputs. When set HIGH, the GS1503B will insert TRS and Line Numbers based on signals input at the EXTH and EXTF pins. Scramble processing bypass select. When set HIGH, the internal scrambler and NRZ(I) encoder is bypassed. NOTE: The status of the SCRBYPASS external pin is not updated in this register. The value programmed in this register is logical OR'd with the SCRBYPASS external pin setting. 000 5 R 0 CRC_INS 000 4 R/W 1 VM[3:0] 000 3-0 R/W 0 EXT_SEL 001 3 R/W 0 SCRBYPASS 001 2 R/W 0 8BIT_SEL 8-bit input selection. When set HIGH, the GS1503B will accept an 8-bit input video signal. Descramble process bypass select. When set HIGH, the internal SMPTE 292M descrambler is bypassed. NOTE: The status of the DSCBYPASS external pin is not updated in this register. The value programmed in this register is logical OR'd with the DSCBYPASS external pin setting. 001 1 R/W 0 DSCBYPASS 001 0 R/W 0 SW_LNB[12:0] Video Field 2 switching line setting. Designates the video switching point for field 2. The default line number is 569, as defined by SMPTE 299M. Video Field 1 switching line setting. Designates the video switching point for field 1. The default line number is 7, as defined by SMPTE 299M. CRC error accumulation. Reports the accumulated number of CRC errors in one video frame. Not used. Illegal code re-mapping select. When set HIGH, input video words between 000-003 are re-mapped to 004, and values between 3FC-3FF are re-mapped to 3FB. Valid only when "EXT_SEL" is set HIGH. 002 003 4-0 7-0 R/W 569d SW_LNA[12:0] 004 005 4-0 7-0 R/W 7d CRC_CNT[11:0] 006 007 008 008 3-0 7-0 7-5 4 – R 0 RSV LIMIT_ON 0 0 R/W GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 44 of 90 Table 4-33: Multiplex Mode Host Interface Registers (Continued) Control Item Name Description Address Bit R/W Default VBLK_INS Vertical blanking enable. When set HIGH, the output video vertical blanking will be set to 040h for the Luma channel and 200h for the Chroma channel. Horizontal blanking enable. When set HIGH, the output video horizontal blanking, including TRS, line numbers and line CRC words, will be set to 040h for the Luma channel and 200h for the Chroma channel. NOTE: If blanking of line numbers and TRS words is required, LN_INS and TRS_INS must be set LOW. 008 3 R/W 0 HBLK_INS 008 2 R/W 0 LN_INS Line insertion enable. When set HIGH, the GS1503B will insert line numbers into the video data stream. When set LOW, existing line numbers will remain in the output video stream. TRS insertion enable. When set HIGH, the GS1503B will insert TRS codes into the video data stream. When set LOW, existing TRS codes will remain in the output video stream. Audio input format (external pin/register) configuration select. When set LOW, the audio input format is configured via the AM[1:0] pins. When set HIGH, the audio input format is configured via the "AM[1:0]" bits. Ch7/8 audio input signal detection. When set HIGH, an audio signal has been detected at the AIN7/8 input pin. Ch5/6 audio input signal detection. When set HIGH, an audio signal has been detected at the AIN5/6 input pin. Ch3/4 audio input signal detection. When set HIGH, an audio signal has been detected at the AIN3/4 input pin. Ch1/2 audio input signal detection. When set HIGH, an audio signal has been detected at the AIN1/2 input pin. Not used. Audio input format select. See Table 4-16. Valid when "AM_SEL" is HIGH. Ch7/8 audio Channel Status CRC insertion. When set HIGH, the Ch7/8 audio input Channel Status CRC is re-calculated before being multiplexed into the Audio Data Packet. Valid only when AES/EBU audio input format is selected. 008 1 R/W 1 TRS_INS 008 0 R/W 1 Audio AM_SEL 010 7 R/W 0 AUD7/8_DET 010 6 R 0 AUD5/6_DET 010 5 R 0 AUD3/4_DET 010 4 R 0 AUD1/2_DET 010 3 R 0 RSV AM[1:0] 010 010 2 1-0 – R/W 0 0 ACRC7/8_INS 011 7 R/W 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 45 of 90 Table 4-33: Multiplex Mode Host Interface Registers (Continued) Control Item Name Description Address Bit R/W Default ACRC5/6_INS Ch5/6 audio Channel Status CRC addition. When set HIGH, the Ch5/6 audio input Channel Status CRC is re-calculated before being multiplexed into the Audio Data Packet. Valid only when AES/EBU audio input format is selected. Ch3/4 audio Channel Status CRC addition. When set HIGH, the Ch3/4 audio input Channel Status CRC is re-calculated before being multiplexed into the Audio Data Packet. Valid only when AES/EBU audio input format is selected. Ch1/2 audio Channel Status CRC addition. When set HIGH, the Ch1/2 audio input Channel Status CRC is re-calculated before being multiplexed into the Audio Data Packet. Valid only when AES/EBU audio input format is selected. Ch7/8 audio Channel Status error detection. When set HIGH, a Channel Status CRC error has been detected in the Ch7/8 audio input. Valid only when AES/EBU audio input format is selected. Ch5/6 audio Channel Status error detection. When set HIGH, a Channel Status CRC error has been detected in the Ch5/6 audio input. Valid only when AES/EBU audio input format is selected. Ch3/4 audio Channel Status error detection. When set HIGH, a Channel Status CRC error has been detected in the Ch3/4 audio input. Valid only when AES/EBU audio input format is selected. Ch1/2 audio Channel Status error detection. When set HIGH, a Channel Status CRC error has been detected in the Ch1/2 audio input. Valid only when AES/EBU audio input format is selected. Ch7/8 audio parity error detection. When set HIGH, an audio parity error has been detected in the Ch7/8 audio input. Valid only when AES/EBU audio input format is selected. Ch5/6 audio parity error detection. When set HIGH, an audio parity error has been detected in the Ch5/6 audio input. Valid only when AES/EBU audio input format is selected. Ch3/4 audio parity error detection. When set HIGH, an audio parity error has been detected in the Ch3/4 audio input. Valid only when AES/EBU audio input format is selected. 011 6 R/W 0 ACRC3/4_INS 011 5 R/W 0 ACRC1/2_INS 011 4 R/W 0 ACS7/8_ERR 011 3 R 0 ACS5/6_ERR 011 2 R 0 ACS3/4_ERR 011 1 R 0 ACS1/2_ERR 011 0 R 0 AP7/8_ERR 012 3 R 0 AP5/6_ERR 012 2 R 0 AP3/4_ERR 012 1 R 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 46 of 90 Table 4-33: Multiplex Mode Host Interface Registers (Continued) Control Item Name Description Address Bit R/W Default AP1/2_ERR Ch1/2 audio parity error detection. When set HIGH, an audio parity error has been detected in the Ch1/2 audio input. Valid only when AES/EBU audio input format is selected. Audio Channel Status set. Valid in Serial Audio Input modes. Used to enter the 23 8-bit bytes of the Audio Channel Status Block, as defined in AES3-1992. NOTE: The CRC byte is generated internally by the GS1503B. Audio channel multiplex enable. When set HIGH, the corresponding audio channel is multiplexed into the Chroma video data stream. "CHACT[7]" corresponds to audio input channel 8 and "CHACT[0]" corresponds to audio input channel 1. When all bits are set LOW, no audio data packets will be multiplexed and the GS1503B will be in bypass mode. Cascade select. When set HIGH, the GS1503B will default to audio groups 3 and 4. When set LOW, the GS1503B will default to audio groups 1 and 2. NOTE: The status of the CASCADE external pin is not updated in this register. The value programmed in this register is logical OR'd with the CASCADE external pin setting. 012 0 R 0 Audio Channel Status Block AUDIO_CS[7:0] : AUDIO_CS [183:176] 058 : 06E 7-0 : 7-0 R/W See Table 4-34 Audio Data Packet CHACT[7-0] 013 7-0 R/W FFh CASCADE 014 7 R/W 0 RSV AMUTEB Not used. Ch5-8 audio mute enable. When set HIGH, the multiplexed audio packets for audio channels 5 to 8 are forced to zero. NOTE: The status of the MUTE external pin is not updated in this register. The value programmed in this register is logical OR'd with the MUTE external pin setting. 014 014 6 5 – R/W – 0 AMUTEA Ch1-4 audio mute enable. When set HIGH, the multiplexed audio packets for audio channels 1 to 4 are forced to zero. NOTE: The status of the MUTE external pin is not updated in this register. The value programmed in this register is logical OR'd with the MUTE external pin setting. 014 4 R/W 0 DATAIDB[1:0] Ch5-8 audio group DID setting. Designates the audio group DID for audio channels 5 to 8. See Table 4-23. When CASCADE (external pin or register) is set LOW, the default setting is audio group 2. When CASCADE is set HIGH, the default setting is audio group 4. 014 3-2 R/W 10b GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 47 of 90 Table 4-33: Multiplex Mode Host Interface Registers (Continued) Control Item Name Description Address Bit R/W Default DATAIDA[1:0] Ch1-4 audio group DID setting. Designates the audio group DID for audio channels 1 to 4. See Table 4-23. When CASCADE (external pin or register) is set LOW, the default setting is audio group 1. When CASCADE is set HIGH, the default setting is audio group 3. Not used. 014 1-0 R/W 11b Audio Control Packet RSV 020 7-3 – 0 CTRONB Ch5-8 audio control packet multiplex enable. When set HIGH, the audio control packets for audio channels 5 to 8 will be multiplexed into the Luma channel of the video data stream. Ch5-8 audio control packet DID setting. Designates the audio control packet DID for audio channels 5 to 8. See Table 4-30. The default setting is audio group 2. Ch5-8 audio frame number. Designates the audio frame number for audio channels 5 to 8. Will be multiplexed into the audio control packet as per SMPTE 299M. Ch5-8 sampling frequency set. Designates the audio sampling frequency for audio channels 5 to 8. Will be multiplexed into the RATE word of the audio control packet as per SMPTE 299M. The default setting is 48kHz. Ch5-8 synchronization set. When set HIGH, the "asx" bit of the audio control packet RATE word designates audio channels 5 to 8 as asynchronous, as per SMPTE 299M. When set LOW, the "asx" bit of the audio control packet RATE word designates synchronous audio (default setting). Ch5/6 delay data. Designates the accumulated audio processing delay relative to video for audio channels 5 and 6. Will be multiplexed into the audio control packet as per SMPTE 299M. Ch7/8 delay data. Designates the accumulated audio processing delay relative to video for audio channels 7 and 8. Will be multiplexed into the audio control packet as per SMPTE 299M. Ch5-8 reserve words. Designates the value set in the RSRV words of the audio control packet for audio channels 5 to 8, as per SMPTE 299M. NOTE: As these words are reserved for future use, they should be set to zero. 020 2 R/W 1 CTRIDB[1:0] 020 1-0 R/W 10b AF_NOB[8:0] 021 022 0 7-0 R/W 0 RATEB[2:0] 023 3-1 R/W 0 ASXB 023 0 R/W 0 DEL1-2B[25:0] 024 025 026 027 028 029 02A 02B 02C 02D 02E 1-0 7-0 7-0 7-0 1-0 7-0 7-0 7-0 1-0 7-0 7-0 R/W 0 DEL3-4B[25:0] R/W 0 RSRVB[17:0] R/W 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 48 of 90 Table 4-33: Multiplex Mode Host Interface Registers (Continued) Control Item Name Description Address Bit R/W Default RSV CTRONA Not used. Ch1-4 audio control packet multiplex enable. When set HIGH, the audio control packets for audio channels 1 to 4 will be multiplexed into the Luma channel of the video data stream. Ch1-4 audio control packet DID setting. Designates the audio control packet DID for audio channels 1 to 4. See Table 4-30. The default setting is audio group 1. Ch1-4 audio frame number. Designates the audio frame number for audio channels 5 to 8. Will be multiplexed into the audio control packet as per SMPTE 299M. Ch1-4 sampling frequency set. Designates the audio sampling frequency for audio channels 1 to 4. Will be multiplexed into the RATE word of the audio control packet as per SMPTE 299M. The default setting is 48kHz. Ch1-4 synchronization set. When set HIGH, the "asx" bit of the audio control packet RATE word designates audio channels 1 to 4 as asynchronous, as per SMPTE 299M. When set LOW, the "asx" bit of the audio control packet RATE word designates synchronous audio (default setting). Ch1/2 delay data. Designates the accumulated audio processing delay relative to video for audio channels 1 and 2. Will be multiplexed into the audio control packet as per SMPTE 299M. Ch3/4 delay data. Designates the accumulated audio processing delay relative to video for audio channels 3 and 4. Will be multiplexed into the audio control packet as per SMPTE 299M. Ch1-4 reserve words. Designates the value set in the RSRV words of the audio control packet for audio channels 1 to 4, as per SMPTE 299M. NOTE: As these words are reserved for future use, they should be set to zero. 02F 02F 7-3 2 – R/W 0 1 CTRIDA[1:0] 02F 1-0 R/W 11b AF_NOA[8:0] 030 031 0 7-0 R/W 0 RATEA[2:0] 02F 3-1 R/W 0 ASXA 02F 0 R/W 0 DEL1-2A[25:0] 033 034 035 036 037 038 039 03A 03B 03C 03D 1-0 7-0 7-0 7-0 1-0 7-0 7-0 7-0 1-0 7-0 7-0 R/W 0 DEL3-4A[25:0] R/W 0 RSRVA[17:0] R/W 0 Arbitrary Data Packet ARBITON Arbitrary data packet multiplex. Valid only when "ARBITMODE" is HIGH. When set HIGH, arbitrary data packets will be multiplexed into the Luma video data stream using the Host Interface register settings. 050 1 R/W 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 49 of 90 Table 4-33: Multiplex Mode Host Interface Registers (Continued) Control Item Name Description Address Bit R/W Default ARBITMODE Arbitrary packet mode select. When set HIGH, arbitrary data packets are multiplexed using the Host Interface register settings. When set LOW, arbitrary data packets are multiplexed using the external pin inputs. Arbitrary packet Data ID setting. Designates the 8 LSBs of the arbitrary data packet DID word. The 2 MSBs are internally generated. "ARBITDID[7]" is the MSB and "ARBITDID[0]" is the LSB. Valid only when "ARBITMODE" is HIGH. Arbitrary packet Secondary Data ID setting. Designates the 8 LSBs of the arbitrary data packet secondary DID word. The 2 MSBs are internally generated. "ARBITSDID[7]" is the MSB and "ARBITSDID[0]" is the LSB. Valid only when "ARBITMODE" is HIGH. Arbitrary packet DC setting. Designates the 8 LSBs of the arbitrary data packet Data Count word. The 2 MSBs are internally generated. "ARBITDC[7]" is the MSB and "ARBITDC[0]" is the LSB. Valid only when "ARBITMODE" is HIGH. Field 2 arbitrary packet multiplex line number setting. Designates the field 2 video line in which the arbitrary data packets will be multiplexed. Valid only when "ARBITMODE" is HIGH. Field 1 arbitrary packet multiplex line number setting. Designates the field 1 video line in which the arbitrary data packets will be multiplexed. Valid only when "ARBITMODE" is HIGH. Arbitrary packet User Data Word set. Designates the 8 LSBs for each of the 255 arbitrary packet User Data Words. The 2 MSBs are internally generated. Valid only when "ARBITMODE" is HIGH. 050 0 R/W 0 ARBITDID[7:0] 051 7-0 R/W 0 ARBITSDID[7:0] 052 7-0 R/W 0 ARBITDC[7:0] 053 7-0 R/W 0 ARBITLINEB[11:0] 054 055 3-0 7-0 R/W 0 ARBITLINEA[11:0] 056 057 3-0 7-0 R/W 0 ARBITUDW0 : ARBITUDW254 100 : 1FE 7-0 : 7-0 R/W 0 Table 4-34: Audio Channel Status Default Values Address 058 Value 85 Channel Status Professional; Valid Audio; No Emphasis (manual override disabled); 48kHz Sampling Frequency (manual override disabled). Two-Channel Mode (manual override disabled). 059 08 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 50 of 90 Table 4-34: Audio Channel Status Default Values Address 05A Value 2C Channel Status Maximum Audio Sample Word Length is 24bits; Encoded Audio Word Length is 24-bit. – Others 00 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 51 of 90 5. Demultiplex Mode 5.1 Functional Overview The GS1503B HD Embedded Audio CODEC fully supports the demultiplexing of Audio Data Packets, Audio Control Packets and Arbitrary Data Packets as per SMPTE 291M and 299M. The device can be configured to operate with all video standards defined in SMPTE 292M, levels A through M. The GS1503B also supports the 1080/24PsF, 25PsF and 30PsF video formats as described in SMPTE RP211. The video input format can be one of the following configurations: • • • • 10-bit Y and Cb/Cr input with TRS and Line Numbers 20-bit scrambled input 20-bit scrambled output 10-bit Y and Cb/Cr output The video output format can be one of the following configurations: Up to a maximum of 8 channels of 48kHz digital audio can be demultiplexed per device. The audio output format can be selected as either AES/EBU, or one of two serial audio data output modes. A maximum of 16 channels of audio can be demultiplexed by cascading two devices in parallel. Audio control packets, as defined in SMPTE 299M, can also be demultiplexed to obtain information about the nature of the embedded audio data. The contents of the audio control packet are stored in registers of the Host Interface. The GS1503B will also demultiplex arbitrary data packets as defined in SMPTE 291M. The arbitrary data packets can serve as an auxiliary data signal for proprietary applications. The GS1503B can be configured to demultiplex arbitrary data packets and output them at dedicated external pins or via the Host Interface registers. Up to a maximum of 255 8-bit words can be demultiplexed (excluding Ancillary Data Flags and Checksum). To use the GS1503B in Demultiplex Mode, set the MUX/DEMUX external pin HIGH. GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 52 of 90 5.2 Video Standard The video standard is selected from the VM[3:0] external pins or VM[3:0] bits 3-0 in Host Interface register 000h. To configure the video standard via the Host Interface, VM_SEL bit 7 in Host Interface register 000h must be set HIGH. The GS1503B will default to the VM[3:0] external pin setting. The supported video standards are listed in Table 5-1. Table 5-1: Supported Video Standards VM [3:0] 1110b 1100b 1000b 1010b 1111b 0010b 0100b 0110b 0000b 0001b 0011b 0101b 0111b Input Format 1035i (30 & 30/1.001 Hz) 1080i (25 Hz) 1080i/1080sF (30 & 30/1.001 Hz) 1080i/1080sF (25 Hz) 1080sF (24 & 24/1.001 Hz) 1080p (30 & 30/1.001 Hz) 1080p (25 Hz) 1080p (24 & 24/1.001 Hz) 720p (60 & 60/1.001 Hz) 720p (30 & 30/1.001 Hz) 720p (50 Hz) 720p (25 Hz) 720p (24 & 24/1.001 Hz) Reference SMPTE Document 260M 295M 274M, RP211 274M, RP211 RP211 274M 274M 274M 296M 296M 296M 296M 296M SMPTE 292M Level A, B C D, E F G, H I J, K L, M All other settings are reserved Table 5-2: Register Settings Name VM_SEL Description 0: External pin select 1: Register select Address 000 Bit 7 Setting 1 Default 0 VM[3:0] Video formal selection (VM[3] is MSB) 000 3-0 See Table 5-1 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 53 of 90 5.3 Video Input Format 5.3.1 20-bit Scrambled Input GS1503B Y/C b / Cr [19:0] VIN[19:0] DSCBYPASS Figure 5-1: 20-bit Scrambled Input Configuration Table 5-3: Register Settings (Default Mode) Name EXT_SEL Description 0: EXTH/EXTF output select 1: EXTH/EXTF input select Address 001 Bit 3 Setting 0 Default 0 8BIT_SEL 0: 10-bit mode select 1: 8-bit mode select 001 1 0 0 DSCBYPASS 0: Descrambling enabled 1: Bypass descrambling 001 0 0 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 54 of 90 5.3.2 10-bit Y and Cb/Cr Input with TRS and Line Numbers GS1503B Y[9:0] VIN[19:10] C b/ C r[9:0] VIN[9:0] EXTF +3.3V EXTH DSCBYPASS Figure 5-2: 10-bit Y and Cb/Cr Input with TRS and Line Numbers Configuration 0 3 10-bit CRC0 CRC1 LN0 LN1 000 000 8 XYZ 000 000 XYZ 3FF 3FF V0 Y, C b / Cr Video 4 VCLK EXTH EXTF Figure 5-3: Video Input Format (10-bit with TRS and Line Numbers) Table 5-4: Register Settings Name EXT_SEL Description 0: EXTH/EXTF output select 1: EXTH/EXTF input select Address 001 Bit 3 Setting 0 Default 0 8BIT_SEL 0: 10-bit mode select 1: 8-bit mode select 001 1 0 0 DSCBYPASS 0: Descrambling enabled 1: Bypass descrambling 001 0 1 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 55 of 90 Vn 5.4 Video Output Format 5.4.1 10-bit Y and Cb/Cr Output GS1503B Y[9:0] VOUT[19:10] VOUT[9:0] C b / C r [9:0] +3.3V SCRBYPASS Figure 5-4: 10-bit Y and Cb/Cr Output Configuration Table 5-5: Register Settings Name SCRBYPASS Description 0: SMPTE 292M scrambling enabled 1: Bypass SMPTE 292M scrambling Address 001 Bit 2 Setting 1 Default 0 5.4.2 20-bit Scrambled Output GS1503B Y/C b / Cr [19:0] VOUT[19:0] SCRBYPASS Figure 5-5: 20-bit Scrambled Output Configuration GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 56 of 90 Table 5-6: Register Settings (Default Mode) Name SCRBYPASS Description 0: SMPTE 292M scrambling enabled 1: Bypass SMPTE 292M scrambling Address 001 Bit 2 Setting 0 Default 0 5.5 Video Data Processing 5.5.1 Video Signal Input Detection The GS1503B will set the VIDEO_DET external pin HIGH when three consecutive TRS are detected in the input video signal. Also, the VIDEO_DET bit of Host Interface register 000h is set HIGH. Table 5-7: Register Settings Name VIDEO_DET Description Video input signal detection (1: Detection) Address 000 Bit 6 Setting – Default 0 5.5.2 Video Input CRC Error Detection The GS1503B will set the CRC_ERR external pin HIGH when a CRC error is detected in the input video signal. Also, the CRC_ERR bit 5 of Host Interface register 000h is set HIGH. The number of CRC errors accumulated in one video frame can be read form CRC_CNT[11:0] in Host Interface registers 006h and 007h. Table 5-8: Register Settings Name CRC_ERR CRC_CNT[11:0] Description Video input signal CRC error detection (1: Detection) Video input signal CRC error accumulation in 1 video frame Address 000 006 007 Bit 5 3-0 7-0 Setting – – Default 0 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 57 of 90 5.5.3 Video Output CRC Insertion When the CRC_INS bit 4 of Host Interface register 000h is set HIGH, the GS1503B will re-calculate the video line CRC words. The re-calculated CRC words are inserted in the video output signal. When CRC_INS is set LOW, the line CRC words are not updated and existing CRC words at the input of the device will be output unchanged. Table 5-9: Register Settings Name CRC_INS Description Video line CRC insertion (1: Insertion) Address 000 Bit 4 Setting 1 Default 1 5.5.4 Input Blanking When VBLK_INS bit 3 of Host Interface register 008h is set HIGH, the input video vertical blanking will be set to 040h for the Luma channel and 200h for the Chroma channel. When HBLK_INS bit 2 of Host Interface register 008h is set HIGH, the input video horizontal blanking will be set to 040h for the Luma channel and 200h for the Chroma channel. The TRS, line number and CRC words will also be set to blanking values. The blanking function is performed at the output of the GS1503B video data stream. If the HBLK_INS bit is set HIGH, any embedded audio or control packets will be replaced with blanking codes. The GS1503B will demultiplex data contained in the packets, prior to the blanking function, and output at the corresponding pins. Table 5-10: Register Settings Name VBLK_INS HBLK_INS Description Input vertical blanking (1: Enabled) Input horizontal blanking (1: Enabled) Address 008 008 Bit 3 2 Setting 1 1 Default 0 0 5.5.5 Line Number Insertion When LN_INS bit 1 of Host Interface register 008h is set HIGH, the GS1503B will insert line numbers into the video data stream. When set LOW, existing line numbers will remain in the output video stream. Table 5-11: Register Settings Name LN_INS Description Line number insertion (1: Enabled) Address 008 Bit 1 Setting 1 Default 1 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 58 of 90 5.5.6 TRS Word Insertion When TRS_INS bit 0 of Host Interface register 008h is set HIGH, the GS1503B will insert TRS codes into the video data stream. When set LOW, existing TRS codes will remain in the output video stream. Table 5-12: Register Settings Name TRS_INS Description TRS word insertion (1: Enabled) Address 008 Bit 0 Setting 1 Default 1 5.6 Audio Data Processing 5.6.1 Digital Audio Output Format The GS1503B has two audio output formats, AES/EBU digital audio output and serial output, as listed in Table 5-13. The serial audio output can be formatted in the following two modes. See Figure 5-6: • • 24-bit Left Justified; MSB first 24-bit Right Justified; MSB last The audio output format is configured using the AM[1:0] external pins or via AM[1:0] bits 1-0 in Host Interface register 010h. To configure the audio output format via the Host Interface, AM_SEL bit 7 in Host Interface register 010h must be set HIGH. The GS1503B will default to the AM[1:0] external pin setting. NOTE: When configured in AES/EBU audio mode, the GS1503B will not output a 48kHz (fs) word clock at the WCOUTA and WCOUTB pins. Table 5-13: Audio Output Formats AM[1:0] 0 1 2 Audio Output Format Serial audio output: 24-bit Left Justified; MSB first Serial audio output: 24-bit Right Justified; MSB last AES/EBU audio output Table 5-14: Register Settings Name AM_SEL Description 0: External pin setting 1: Register setting Address 010 Bit 7 Setting 1 Default 0 AM[1:0] Audio output format selection (AM[1] is MSB) 010 1-0 See Table 5-13 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 59 of 90 WCOUTA/WCOUTB MSB MODE0 23 LSB MODE1 0 MODE2 (AES/EBU) 34 0 Channel 1 MSB 0 23 LSB 23 2728293031 0 24-bit Audio Sample Word Validity Bit User Data Bit Channel Status Bit Parity Bit 34 0 Channel 2 0 23 2728293031 24-bit Audio Sample Word VUCP Sync Preamble Sync V U C P Preamble Figure 5-6: Audio Output Formats 5.6.2 Digital Audio Output Timing 5.6.2.1 AES/EBU Format Output A 6.144MHz (128fs) audio clock must be supplied to the ACLKA and ACLKB inputs. ACLKA is used to clock AES/EBU digital audio signal for channels 1 to 4 (AOUT1/2 and AOUT3/4). ACLKB is used to clock AES/EBU digital audio signal for channels 5 to 8 (AOUT5/6 and AOUT7/8). In AES/EBU output mode, the audio word clock inputs WCINB and WCINB should be grounded. See Figure 5-7 for timing. The user can access the Audio Channel Status Block information via the AUDIO_CS[183:0] bits in Host Interface registers 058h to 06Eh. To read the Audio Channel Status information, the CS_MODE bit 3 of Host Interface register 06Fh should be set HIGH. The embedded audio channel from which the Channel Status information is to be extracted is set in the CH_SEL[2:0] bits 2-0 of Host Interface register 06Fh. The CH_SEL[2:0] setting for audio channel 1 is 000b, through to 111b for channel 8. The CS_RQST bit must be set HIGH to begin the process of extracting the Audio Channel Status information. Once extracted, the GS1503B will set CS_WEND bit HIGH and the user can access the data for Host Interface registers 058h to 06Eh. When CS_MODE is set LOW, the Audio Channel Status information in the AES/EBU audio outputs will be replaced with data programmed in the AUDIO_CS[183:0] bits of Host Interface registers 058h to 06Eh. Table 5-15: Register Settings Name CS_WEND Description Audio Channel Status write flag (1: Data ready) Address 06F Bit 5 Setting – Default 0 CS_RQST Audio Channel Status request (1: enable) 06F 4 1 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 60 of 90 Table 5-15: Register Settings Name CS_MODE Description 0: Audio Channel Status replace 1: Audio Channel Status demultiplex Address 06F Bit 3 Setting 1 Default 0 CH_SEL[2:0] Audio Channel Status select 06F 2-0 – 000b GS1503B Y/C b / Cr [19:0] VIN[19:0] AOUT1/2 AOUT3/4 6.144MHz (128 fs) ACLKA Audio Channels 1 & 2 Audio Channels 3 & 4 AOUT5/6 AOUT7/8 6.144MHz (128 fs) ACLKB Audio Channels 5 & 6 Audio Channels 7 & 8 6.144MHz ACLKA/B AOUT1/2, AOUT3/4 AOUT5/6, AOUT7/8 Figure 5-7: AES/EBU Audio Output Configuration and Timing GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 61 of 90 5.6.2.2 Serial Audio Output Modes A 6.144MHz (128fs) audio clock must be supplied to the ACLKA and ACLKB inputs. An audio word clock at 48kHz (fs) will be output at the WCOUTA and WCOUTB external pins, as shown in Figure 5-8. The user can access the Audio Channel Status Block information via the AUDIO_CS[183:0] bits in Host Interface registers 058h to 06Eh. To read the Audio Channel Status information, the CS_MODE bit 3 of Host Interface register 06Fh should be set HIGH. The embedded audio channel from which the Channel Status information is to be extracted is set in the CH_SEL[2:0] bits 2-0 of Host Interface register 06Fh. The CH_SEL[2:0] setting for audio channel 1 is 000b, through to 111b for channel 8. The CS_RQST bit must be set HIGH to begin the process of extracting the Audio Channel Status information. Once extracted, the GS1503B will set CS_WEND bit HIGH and the user can access the data for Host Interface registers 058h to 06Eh. When DEC_MODE (external pin or register setting) is set LOW, the audio word clock inputs WCINB and WCINB should be grounded. GS1503B Y/C b / Cr [19:0] VIN[19:0] AOUT1/2 AOUT3/4 6.144MHz (128 fs) ACLKA WCOUTA Audio Channels 1 & 2 Audio Channels 3 & 4 48kHz (fs) AOUT5/6 AOUT7/8 6.144MHz (128 fs) ACLKB WCOUTB Audio Channels 5 & 6 Audio Channels 7 & 8 48kHz (fs) 64 CLKs ACLKA/B 64 CLKs WCOUTA/B AOUT1/2, AOUT3/4 AOUT5/6, AOUT7/8 Figure 5-8: Serial Audio Output Configuration and Timing GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 62 of 90 5.6.3 Audio Clock Phase Locked Loop Figure 5-9 shows the configuration for deriving the 6.144MHz audio clock in AES/EBU and serial audio output modes. The GS1503B will internally synchronize the audio output to the corresponding ACLK. This configuration is not required when DEC_MODE is set HIGH. 6.144MHz (128 fs) GS1503B Y/C b / C r [19:0] VIN[19:0] AOUT1/2 AOUT3/4 Audio Channels 1 & 2 Audio Channels 3 & 4 Low ACLKA PLLCNTA Pass Filter Audio Channels 5 & 6 Audio Channels 7 & 8 VCXO 24.576MHz 4 ÷ AOUT5/6 AOUT7/8 Low ACLKB PLLCNTB Pass Filter VCXO 24.576MHz 4 ÷ 6.144MHz (128 fs) Figure 5-9: Block Diagram of GS1503B Audio Clock PLL GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 63 of 90 5.6.4 Audio Data Packet Detection The audio data packet detect registers will be set HIGH when a corresponding audio group DID has been detected in the Chroma channel of the input video stream. Host Interface register 013h, bits 7-4, report the individual audio groups detected. Table 5-16: Register Settings Name ADPG4_DET Description Audio group 4 data packet detection (1:Detection) Audio group 3 data packet detection (1:Detection) Audio group 2 data packet detection (1:Detection) Audio group 1 data packet detection (1:Detection) Address 013 Bit 7 Setting – Default 0 ADPG3_DET 013 6 – 0 ADPG2_DET 013 5 – 0 ADPG1_DET 013 4 – 0 5.6.5 ECC Error Detection & Correction The GS1503B performs BCH(31,25) forward error detection and correction as described in SMPTE 299M. The error correction for audio data packets with audio group DID set in DATAIDA[1:0] is activated when ECCA_ON bit 0 of Host Interface register 013h is set HIGH. Similarly, error correction for audio data packets with audio group DID set in DATAIDB[1:0] is activated when ECCB_ON bit 1 of Host Interface register 013h is set HIGH When a one-bit error is detected in a bit array of the ECC protected region of the audio data packet with audio group DID set in DATAIDA[1:0], ECCA_ERR bit 1 in Host Interface register 015h is set HIGH. When a one-bit error is detected in the ECC protected region of the audio data packet with audio group DID set in DATAIDB[1:0], the ECCB_ERR bit 5 in Host Interface register 015h is set HIGH. In both cases, the ERROR external pin will also be set HIGH. A bit array is defined as all 24 bits of bit 0. The next bit array is all 24 bits of bit 1, and so on through to bit 7. Up to 8 bits in error can be corrected, providing each bit error is in a different bit array. When there are two bits in error in the same 24-bit array, the errors will be detected, but not corrected. When there are more than two bits in error in a single bit array, the errors will not be detected or corrected. The number of audio data packets corrected in one video frame will be reported in the corresponding Host Interface registers CORRECTA[11:0] and CORRECTB[11:0]. The GS1503B will also report the number of audio data packets which could not be corrected in one video frame in the corresponding Host Interface registers NO_CORRECTA[11:0] and NO_CORRECTB[11:0]. GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 64 of 90 Table 5-17: Register Settings Name ECCB_ERR Description Ch5-8 Audio data packet ECC error detection (1: Detection) Address 015 Bit 5 Setting – Default 0 ECCA_ERR Ch1-4 Audio data packet ECC error detection (1: Detection) 015 1 – 0 CORRECTB[11:0] Ch5-8 correctable packets in one video frame 016 017 3-0 7-0 3-0 7-0 3-0 7-0 3-0 7-0 1 0 – 0 NO_CORRECTB[11:0] Ch5-8 un-correctable packets in one video frame 018 019 – 0 CORRECTA[11:0] Ch1-4 correctable packets in one video frame 01A 01B – 0 NO_CORRECTA[11:0] Ch5-8 un-correctable packets in one video frame 01C 01D – 0 ECCB_ON ECCA_ON Ch5-8 Audio data packet error correction (1: ON) Ch1-4 Audio data packet error correction (1: ON) 013 013 1 1 1 1 5.6.6 Audio Data Packet Error Detection When the 1-255 count sequence in the Data Block Number (DBN) word of audio data packets with audio group DID set in DATAIDA[1:0] is discontinuous, the DBNA_ERR bit 3 of Host Interface register 015h will be set HIGH. When the1-255 count sequence in the DBN word of audio data packets with audio group DID set in DATAIDB[1:0] is discontinuous, the DBNB_ERR bit 7 of Host Interface register 015h will be set HIGH. The GS1503B will check the parity (bit 8) for the CLK, CH1-4 and ECC0-5 words in the embedded audio data packets. When a parity bit error is detected in audio data packets with audio group DID set in DATAIDA[1:0], the ADPB8A_ERR bit 2 of Host Interface register 015h will be set HIGH. When a parity bit error is detected in audio data packets with audio group DID set in DATAIDB[1:0], the ADPB8B_ERR bit 6 of Host Interface register 015h will be set HIGH. The GS1503B will re-calculate the audio data packets Checksum and compare against the embedded Checksum word. When a Checksum error is detected in audio data packets with audio group DID set in DATAIDA[1:0], the ADPCSA_ERR bit 0 of Host Interface register 015h will be set HIGH. When a Checksum error is detected in audio data packets with audio group DID set in DATAIDB[1:0], the ADPCSB_ERR bit 4 of Host Interface register 015h will be set HIGH. When any of the above errors are detected, the ERROR external pin will also be set HIGH. GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 65 of 90 Table 5-18: Register Settings Name DBNB_ERR Description Ch5-8 Audio data packet DBN error detection (1:Detection) Ch5-8 Audio data packet bit8 error detection (1:Detection) Ch5-8 Audio data packet CS error detection (1:Detection) Ch1-4 Audio data packet DBN error detection (1:Detection) Ch1-4 Audio data packet bit8 error detection (1:Detection) Ch1-4 Audio data packet CS error detection (1:Detection) Address 015 Bit 7 Setting – Default 0 ADPB8B_ERR 015 6 – 0 ADPCSB_ERR 015 4 – 0 DBNA_ERR 015 3 – 0 ADPB8A_ERR 015 2 – 0 ADPCSA_ERR 015 0 – 0 5.6.7 Audio Data Packet DID Setting The audio group DID for audio output channels 1 to 4 (AOUT1/2 and AOUT3/4) is set in DATAIDA[1:0] bits 1-0 of Host Interface register 014h. The audio group DID for audio output channels 5 to 8 (AOUT5/6 and AOUT7/8) is set in DATAIDB[1:0] bits 3-2 of Host Interface register 014h. Table 5-19 shows the 2-bit Host Interface setting for the corresponding audio group DID. When CASCADE is set LOW (external pin or register), the GS1503B will default to audio groups 1 and 2, where AOUT1/2 and AOUT3/4 will be demultiplexed from audio data packets with group 1 DID, and AOUT5/6 and AOUT7/8 will be demultiplexed from audio data packets with group 2 DID. Table 5-19: Audio Group DID Host Interface Settings Audio Group 1 2 3 4 10-bit Data 2E7h 1E6h 1E5h 2E4h Host Interface Register Setting (2-bit) 11b 10b 01b 00b Table 5-20: Register Settings (CASCADE set LOW) Name DATAIDA[1-0] DATAIDB[1-0] Description Ch1-4 Audio data packet DID setting Ch5-8 Audio data packet DID setting Address 014 014 Bit 1-0 3-2 Setting See Table 5-19 Default 11b 10b GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 66 of 90 When CASCADE is set HIGH (external pin or register), the GS1503B will default to audio groups 3 and 4, where AOUT1/2 and AOUT3/4 will be demultiplexed from audio data packets with group 3 DID, and AOUT5/6 and AOUT7/8 will be demultiplexed from audio data packets with group 4 DID. Table 5-21: Register Settings (CASCADE set HIGH) Name DATAIDA[1-0] DATAIDB[1-0] Description Ch1-4 Audio data packet DID setting Ch5-8 Audio data packet DID setting Address 014 014 Bit 1-0 3-2 Setting See Table 5-19 Default 01b 00b 5.7 Demultiplex Cascade Mode Two GS1503B devices can be cascaded in parallel to allow up to 16 channels of audio to be demultiplexed (only one device requires CASCADE to be set HIGH). Figure 5-10 shows the cascade architecture for a 16-channel system. To configure the GS1503B for cascade mode, the CASCADE external pin or CASCADE bit 7 of Host Interface register 014h is set HIGH. When set HIGH, the GS1503B will default to audio groups 3 and 4. When set LOW, the GS1503B will default to audio groups 1 and 2. GS1503B Y/C b /Cr [19:0] VIN[19:0] VOUT[19:0] Y/C b /Cr [19:0] AOUT1/2 AOUT3/4 Audio Channels 1 & 2 Audio Channels 3 & 4 Audio Group 1 AOUT5/6 AOUT7/8 Audio Channels 5 & 6 Audio Channels 7 & 8 Audio Group 2 CASCADE GS1503B VIN[19:0] VOUT[19:0] Y/C b /Cr [19:0] AOUT1/2 AOUT3/4 Audio Channels 9 & 10 Audio Channels 11 & 12 Audio Group 3 AOUT5/6 AOUT7/8 +3.3V CASCADE Audio Channels 13 & 14 Audio Channels 15 & 16 Audio Group 4 Figure 5-10: Demultiplexing 16 Channels of Audio using Cascade Architecture GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 67 of 90 Table 5-22: Register Settings Name CASCADE Description Cascade enable (1: Enabled) Address 014 Bit 7 Setting 1 Default 0 5.8 Audio Control Packets 5.8.1 Audio Control Packet Detection The audio control packet detect registers will be set HIGH when a corresponding audio group DID has been detected in the Luma channel of the input video stream. Host Interface register 020h, bits 7-4, report the individual audio groups detected. Table 5-23: Register Settings Name ACPG4_DET Description Audio group 4 control packet detection (1: Detection) Audio group 3 control packet detection (1: Detection) Audio group 2 control packet detection (1: Detection) Audio group 1 control packet detection (1: Detection) Address 020 Bit 7 Setting – Default 0 ACPG3_DET 020 6 – 0 ACPG2_DET 020 5 – 0 ACPG1_DET 020 4 – 0 5.8.2 Audio Control Packet DID Setting To demultiplex audio control packets for audio channels 1 to 4 (AOUT1/2 and AOUT3/4), the CTRONA bit 2 of Host Interface register 02Fh is set HIGH. To demultiplex audio control packets for audio channels 5 to 8 (AOUT5/6 and AOUT7/8), the CTRONB bit 2 of Host Interface register 020h is set HIGH. The audio control packet group DID for audio output channels 1 to 4 is set in CTRIDA[1:0] bits 1-0 of Host Interface register 02Fh. The audio control packet group DID for audio output channels 5 to 8 is set in CTRIDB[1:0] bits 3-2 of Host Interface register 020h. Table 5-24 shows the 2-bit Host Interface setting for the corresponding audio control packet group DID. When CASCADE is set LOW (external pin or register), the GS1503B will default to audio groups 1 and 2, where audio control packet data for channels 1 to 4 will be demultiplexed from packets with group 1 DID, and audio control packet data for channels 5 to 8 will be demultiplexed from packets with group 2 DID. Control packet data is accessible via the corresponding registers in the Host Interface. GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 68 of 90 Table 5-24: Audio Control Packet Group DID Host Interface Settings Audio Group 1 2 3 4 10-bit Data 1E3h 2E2h 2E1h 1E0h Host Interface Register Setting (2-bit) 11b 10b 01b 00b Table 5-25: Register Settings Name CTRONA Description Ch1-4 Audio control packet demultiplex enable (1: Enabled) Address 02F Bit 2 Setting 1 Default 1 CTRIDA[1:0] Ch1-4 Audio control packet DID set 02F 1-0 See Table 5-24 – 11b AF_NOA[8:0] Ch1-4 Audio frame number 030 031 0 7-0 3-1 0 0 RATEA[2:0] ASXA Ch1-4 Sampling frequency data Ch1-4 Synchronization (0: Synchronous; 1: Non-synchronous) 032 032 – – 0 0 DEL1-2A[25:0] Ch1/2 Delay data 033 034 035 036 1-0 7-0 7-0 7-0 1-0 7-0 7-0 7-0 1-0 7-0 7-0 2 – 0 DEL3-4A[25:0] Ch3/4 Delay data 037 038 039 03A – 0 RSRVA[17:0] Ch1-4 Reserved words 03B 03C 03D – 0 CTRONB Ch5-8 Audio control packet demultiplex enable (1: Enabled) 020 1 1 CTRIDB[1:0] Ch5-8 Audio control packet DID set 020 1-0 See Table 5-24 – 10b AF_NOB[8:0] Ch5-8 Audio frame number 021 022 0 7-0 3-1 0 RATEB[2:0] Ch5-8 Sampling frequency data 023 – 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 69 of 90 Table 5-25: Register Settings Name ASXB Description Ch5-8 Synchronization (0: Synchronous; 1: Non-synchronous) Address 023 Bit 0 Setting – Default 0 DEL1-2B[25:0] Ch5/6 Delay data 024 025 026 027 1-0 7-0 7-0 7-0 1-0 7-0 7-0 7-0 1-0 7-0 7-0 – 0 DEL3-4B[25:0] Ch7/8 Delay data 028 029 02A 02B – 0 RSRVB[17:0] Ch5-8 Reserved words 02C 02D 02E – 0 5.9 Arbitrary Data Packets The GS1503B can demultiplex arbitrary data packets according to SMPTE 291M. Typically, arbitrary data packets consist of linear time code (LTC), vertical interval time code (VITC) or other user data, which is multiplexed once per video field. The GS1503B has two modes in which arbitrary data can be demultiplexed from the Luma channel of the video data stream. A maximum of 255 user data words can be demultiplexed. Figure 5-11 shows the structure of the arbitrary data packet. MSB Not b8 Parity bit UDW252[1FC] UDW253[1FD] UDW251[1FB] UDW254[1FE] UDW0[100] UDW1[101] UDW2[102] UDW3[103] ADF SDID DID LSB DC User Data Words Contents available in Host Interface registers Figure 5-11: Arbitrary Data Packet Structure GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 CS 70 of 90 5.9.1 Arbitrary Data Demultiplexing in External Pin Mode This is the default mode for demultiplexing arbitrary data packets. The GS1503B will set the PKTEN external pin HIGH before arbitrary data will be output. Two VCLK cycles after PKTEN goes HIGH, arbitrary data is output on the PKT[7:0] bus. See Figure 5-12 for timing. The following arbitrary data is output on the PKT[7:0] bus: Data ID (DID), Secondary Data ID (SDID), Data Count (DC) and User Data Words (UDW: up to a maximum of 255 words). GS1503B Y/C b / Cr [19:0] VIN[19:0] PKTEN PKT[7:0] Arbitrary Data Output Enable Arbitrary Data 2 CLKs VCLK 2 CLKs PKTEN PKT[7:0] Arbitrary Data ADF ADF ADF DID DC Packet Figure 5-12: Arbitrary Data Packet Output Timing Diagram 5.9.2 Arbitrary Data Demultiplexing in Host Interface Mode To select this mode, set ARBITMODE bit 0 in Host Interface register 050h HIGH. In this mode, the DID, SDID, DC and User Data Words must be programmed in the corresponding Host Interface registers. Set the video line number for field 1 and field 2 from which the arbitrary data packets are to be demultiplexed using the ARBITLINEA[11:0] and ARBITLINEB[11:0] Host Interface registers respectively. The arbitrary data packet is demultiplexed when the ARBITON bit 1 in Host Interface register 050h is set HIGH. ARBITON should be set LOW when reading the arbitrary data packet User Data Words from the ARBITUDW Host Interface registers. GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 71 of 90 CS Arbitrary UDW250 UDW251 UDW252 UDW253 UDW254 UDW0 UDW1 UDW2 UDW3 SDID Table 5-26: Register Settings Name ARBITON Description Arbitrary packet demultiplex enable (1: Enabled) Valid only when ARBITMODE is HIGH Address 050 Bit 1 Setting 1 Default 0 ARBITMODE Arbitrary packet mode selection (0: External pin mode; 1: Host mode) 050 0 1 0 ARBITDID[7-0] ARBITSDID[7-0] ARBITDC[7-0] ARBITLINEA[11:0] Arbitrary packet DID setting Arbitrary packet SDID setting Arbitrary packet DC setting Field 1 multiplexing line 051 052 053 054 055 7-0 7-0 7-0 3-0 7-0 3-0 7-0 7-0 –– – – 0 0 0 0 ARBITLINEB[11:0] Field 2 multiplexing line 056 057 – 0 ARBITUDW Arbitrary packet UDW 100-1FE – 0 5.10 Ancillary Data Deletion The GS1503B can be configured to delete the embedded ancillary data packets, after demultiplexing. There are two modes for ancillary data deletion. 5.10.1 Entire Ancillary Data Deletion When the ANCI external pin or ANCI bit 1 of Host Interface register 040h is set HIGH, all ancillary data packets in both the Luma and Chroma channel of the input video stream are deleted. The data is replaced with blanking values 040h in the Luma channel and 200h in the Chroma channel. The DEL_SEL bit 0 of Host Interface register 040h must be set LOW. 5.10.2 Audio Group Designation Ancillary Data Deletion When the ANCI bit 1 of Host Interface register 040h is set HIGH, and DEL_SEL bit 0 of Host Interface register 040h is HIGH, only audio data and control packets which are designated in Host Interface registers 041h will be deleted. To delete the arbitrary data packets, the corresponding DID must be set in the NDID[7:0] Host Interface register 042h. GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 72 of 90 Table 5-27: Register Settings Name ANCI DEL_SEL Description Ancillary data packet delete (1: Deletion enabled) Ancillary data packet delete mode select (0: Entire data delete; 1: Group designated data delete) Address 040 040 Bit 1 0 Setting 1 1 Default 0 0 ADPG4_DEL ADPG3_DEL ADPG2_DEL ADPG1_DEL ACPG4_DEL ACPG3_DEL ACPG2_DEL ACPG1_DEL NDID[7:0] Audio group 4 data packet delete (1: Delete) Audio group 3 data packet delete (1: Delete) Audio group 2 data packet delete (1: Delete) Audio group 1 data packet delete (1: Delete) Audio group 4 control packet delete (1: Delete) Audio group 3 control packet delete (1: Delete) Audio group 2 control packet delete (1: Delete) Audio group 1 control packet delete (1: Delete) Arbitrary packet DID delete setting 041 041 041 041 041 041 041 041 042 7 6 5 4 3 2 1 0 7-0 – – – – – – – – – 0 0 0 0 0 0 0 0 0 5.11 Demultiplex Mode With Word Clock Input Some commercially available HD audio embedding modules do not encode the audio word clock phase information correctly in the CLK words of the audio data packet. If this clock information is not correctly encoded, the GS1503B will not output the audio data correctly. Also, the GS1503B will be unable to reproduce the 48kHz audio word clock (fs) at the WCOUTA and WCOUTB pins in serial audio output modes. If the GS1503B is to be used in conjunction with a HD audio module, which encodes audio clock phase information incorrectly, the DEC_MODE external pin or DECMODE bit 2 of Host Interface register 01Eh must be set HIGH. When HIGH, an audio word clock synchronous to the original word clock used for embedding must be input at the WCINA and WCINB pins. Figure 5-13 shows a system example. When the embedded clock phase data for audio channel 1 to 4 is detected as being in error, the MUXERRA bit 0 of Host Interface register 01Eh will be set HIGH. Similarly, when the embedded clock phase data for audio channel 5 to 8 is detected as being in error, the MUXERRB bit 1 of Host Interface register 01Eh will be set HIGH. Table 5-28: Register Settings Name DECMODE Description Demultiplex Mode with word clock input enable (1: Enabled) Address 01E Bit 2 Setting 1 Default 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 73 of 90 Table 5-28: Register Settings Name MUXERRB Description Ch5-8 embedded clock phase information error detect (1: Detected) Ch1-4 embedded clock phase information error detect (1: Detected) Address 01E Bit 1 Setting – Default 0 MUXERRA 01E 0 – 0 HD Audio Embedding Module Y/C b / C r [19:0] VIN[19:0] GS1503B VOUT[19:0] Y/C b /Cr [19:0] Audio Channels 1 & 2 Audio Channels 3 & 4 48kHz (fs) AIN1/2 AIN3/4 WCINA WCINA AOUT1/2 AOUT3/4 Audio Channels 1 & 2 Audio Channels 3 & 4 Audio Channels 5 & 6 Audio Channels 7 & 8 48kHz (fs) AIN5/6 AIN7/8 WCINA +3.3V DEC_MODE MUX/DEMUX WCINA AOUT5/6 AOUT7/8 Audio Channels 5 & 6 Audio Channels 7 & 8 Figure 5-13: Demultiplex Mode with 48kHz Word Clock Input System Example Figure 5-14 shows the timing relationship between the audio word clock inputs and word clock outputs when the GS1503B is configured to serial audio output mode. 1 CLK ACLKA/B WCINA/B WCOUTA/B Figure 5-14: WCINA/B Input to WCOUTA/B Output Timing Diagram GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 74 of 90 Table 5-29: Demultiplex Mode Host Interface Registers Control Item Video Name Description Address Bit R/W Default VM_SEL Video input format (external pin/internal register) configuration select. When set LOW, the video input format is configured via the VM[3:0] pins. When set HIGH, the video input format is configured via the "VM[3:0]" bits. Video signal detection flag. Set HIGH when 3 consecutive TRS are detected in the input video signal. Video input signal CRC error detection. Set HIGH when a CRC error is detected in the input video signal. This register is refreshed on every video frame. Video CRC insertion. When set HIGH, the Luma and Chroma line CRC words are re-calculated and inserted into the output video signal. Video input format selection. See Table 5-1. Valid when "VM_SEL" is HIGH. External EXTH/EXTF input select. When set LOW, the EXTH and EXTF pins are configured as outputs. When set HIGH, the GS1503B will insert TRS and Line Numbers based on signals input at the EXTH and EXTF pins. Scramble processing bypass select. When set HIGH, the internal scrambler and NRZ(I) encoder is bypassed. NOTE: The status of the SCRBYPASS external pin is not updated in this register. The value programmed in this register is logical OR'd with the SCRBYPASS external pin setting. 000 7 R/W 0 VIDEO_DET 000 6 R 0 CRC_ERR 000 5 R 0 CRC_INS 000 4 R/W 1 VM[3:0] 000 3-0 R/W 0 EXT_SEL 001 3 R/W 0 SCRBYPASS 001 2 R/W 0 8BIT_SEL 8-bit input selection. When set HIGH, the GS1503B will accept an 8-bit input video signal. Descramble process bypass select. When set HIGH, the internal SMPTE 292M descrambler is bypassed. NOTE: The status of the DSCBYPASS external pin is not updated in this register. The value programmed in this register is logical OR'd with the DSCBYPASS external pin setting. 001 1 R/W 0 DSCBYPASS 001 0 R/W 0 CRC_CNT[11:0] CRC error accumulation. Reports the accumulated number of CRC errors in one video frame. Not used. Vertical blanking enable. When set HIGH, the output video vertical blanking will be set to 040h for the Luma channel and 200h for the Chroma channel. 006 007 008 008 3-0 7-0 7-4 3 R 0 RSV VBLK_INS R/W R/W 0 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 75 of 90 Table 5-29: Demultiplex Mode Host Interface Registers (Continued) Control Item Name Description Address Bit R/W Default HBLK_INS Horizontal blanking enable. When set HIGH, the output video horizontal blanking, including TRS, line numbers and line CRC words, will be set to 040h for the Luma channel and 200h for the Chroma channel. NOTE: If blanking of line numbers and TRS words is required, LN_INS and TRS_INS must be set LOW. 008 2 R/W 0 LN_INS Line insertion enable. When set HIGH, the GS1503B will insert line numbers into the video data stream. When set LOW, existing line numbers will remain in the output video stream. TRS insertion enable. When set HIGH, the GS1503B will insert TRS codes into the video data stream. When set LOW, existing TRS codes will remain in the output video stream. Audio input format (external pin/register) configuration select. When set LOW, the audio input format is configured via the AM[1:0] pins. When set HIGH, the audio input format is configured via the "AM[1:0]" bits. Not used. Audio input format select. See Table 5-13. Valid when "AM_SEL" is HIGH. Not used. Demultiplex Mode select. When set HIGH, the GS1503B requires a 48kHz word clock input at WCINA and WCINB. This word clock must be synchronous to the word clock used to embed the audio data. The embedded clock information in the audio data packet will be ignored. See Section 5.11. NOTE: The status of the DEC_MODE external pin is not updated in this register. The value programmed in this register is logical OR'd with the DEC_MODE external pin setting. 008 1 R/W 1 TRS_INS 008 0 R/W 1 Audio AM_SEL 010 7 R/W 0 RSV AM[1:0] 010 010 6-2 1-0 – R/W 0 0 RSV DECMODE 01E 01E 7-3 2 – R/W 0 0 MUXERRB Ch5-8 audio sample clock error. When set HIGH, the GS1503B is unable to recover the audio clock phase data in the embedded audio data packet for audio channels 5 to 8. See Section 5.11. Ch1-4 audio sample clock error. When set HIGH, the GS1503B is unable to recover the audio clock phase data in the embedded audio data packet for audio channels 1 to 4. See Section 5.11. 01E 1 R 0 MUXERRA 01E 0 R 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 76 of 90 Table 5-29: Demultiplex Mode Host Interface Registers (Continued) Control Item Audio Channel Status Block Name Description Address Bit R/W Default AUDIO_CS[7:0] : AUDIO_CS [183:176] Audio Channel Status. When "CS_MODE" is set HIGH, the 23 8-bit bytes of the Audio Channel Status Block, as defined in AES3-1992, are available in these registers. Valid in both AES/EBU and serial audio modes. When "CS_MODE" is set LOW, the Audio Channel Status information in the AES/EBU audio outputs will be replaced with data programmed in these registers. Valid only in AES/EBU audio mode. 058 : 06E 7-0 : 7-0 R 0 RSV CS_WEND Not used Audio Channel Status write flag. When set HIGH, indicates that the audio channel status information has been written into the Host Interface registers 058h to 06Eh and can be read by the user. Valid only when "CS_MODE" is set HIGH. Audio Channel Status request. When set HIGH, the GS1503B will read and store the Audio Channel Status information from the audio channel set in Host Interface register "CH_SEL[2:0]". Valid only when "CS_MODE" is set HIGH. Audio Channel Status mode. When set HIGH, the user can access the embedded Audio Channel Status information from the Host Interface registers 058h to 06Eh. Valid in both AES/EBU and serial audio modes. When set LOW, the Audio Channel Status information for all audio outputs will be replaced with data programmed in Host Interface registers 058h - 06Eh. Valid only in AES/EBU audio mode. 06F 06F 7-6 5 – R 0 0 CS_RQST 06F 4 R/W 0 CS_MODE 06F 3 R/W 0 CH_SEL[2:0] Audio Channel Status select. Designates the embedded audio channel from which the Audio Channel Status information will be demultiplexed. The setting 000b represent audio channel 1, through to 111b for channel 8. Valid only when "CS_MODE" is set HIGH. Audio group 4 data packet detect. When set HIGH, audio data packets with group 4 DID have been detected in the incoming Chroma video data stream. NOTE: Once this bit has been set, it will remain set until a device reset is performed. 06F 2-0 R/W 000b Audio Data Packet ADPG4_DET 013 7 R 0 ADPG3_DET Audio group 3 data packet detect. When set HIGH, audio data packets with group 3 DID have been detected in the incoming Chroma video data stream. NOTE: Once this bit has been set, it will remain set until a device reset is performed. 013 6 R 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 77 of 90 Table 5-29: Demultiplex Mode Host Interface Registers (Continued) Control Item Name Description Address Bit R/W Default ADPG2_DET Audio group 2 data packet detect. When set HIGH, audio data packets with group 2 DID have been detected in the incoming Chroma video data stream. NOTE: Once this bit has been set, it will remain set until a device reset is performed. 013 5 R 0 ADPG1_DET Audio group 1 data packet detect. When set HIGH, audio data packets with group 1 DID have been detected in the incoming Chroma video data stream. NOTE: Once this bit has been set, it will remain set until a device reset is performed. 013 4 R 0 RSV ECCB_ON Not used. Ch5-8 error correction enable. When set HIGH, the GS1503B will perform error correction on audio data packets for channels 5 to 8, based on the six ECC words. Ch1-4 error correction enable. When set HIGH, the GS1503B will perform error correction on audio data packets for channels 1 to 4, based on the six ECC words. Cascade select. When set HIGH, the GS1503B will default to audio groups 3 and 4. When set LOW, the GS1503B will default to audio groups 1 and 2. NOTE: The status of the CASCADE external pin is not updated in this register. The value programmed in this register is logical OR'd with the CASCADE external pin setting. 013 013 3-2 1 – R/W 0 1 ECCA_ON 013 0 R/W 1 CASCADE 014 7 R/W 0 RSV AMUTEB Not used. Ch5-8 audio mute enable. When set HIGH, the multiplexed audio packets for audio channels 5 to 8 are forced to zero. NOTE: The status of the MUTE external pin is not updated in this register. The value programmed in this register is logical OR'd with the MUTE external pin setting. 014 014 6 5 – R/W 0 0 AMUTEA Ch1-4 audio mute enable. When set HIGH, the multiplexed audio packets for audio channels 1 to 4 are forced to zero. NOTE: The status of the MUTE external pin is not updated in this register. The value programmed in this register is logical OR'd with the MUTE external pin setting. 014 4 R/W 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 78 of 90 Table 5-29: Demultiplex Mode Host Interface Registers (Continued) Control Item Name Description Address Bit R/W Default DATAIDB[1:0] Ch5-8 audio group DID setting. Designates the audio group DID for audio channels 5 to 8. See Table 5-19. When CASCADE (external pin or register) is set LOW, the default setting is audio group 2. When CASCADE is set HIGH, the default setting is audio group 4. Ch1-4 audio group DID setting. Designates the audio group DID for audio channels 1 to 4. See Table 5-19. When CASCADE (external pin or register) is set LOW, the default setting is audio group 1. When CASCADE is set HIGH, the default setting is audio group 3. Ch5-8 audio data packet DBN error. When set HIGH, a Data Block Number error has been detected in the audio data packet for audio channels 5 to 8. Ch5-8 audio data packet 'bit 8' error. When set HIGH, a 'bit 8' error has been detected in the audio data packet for audio channels 5 to 8. Ch5-8 audio data packet error. When set HIGH, an error has been detected in the audio data packet for audio channels 5 to 8, based on the six ECC words. Ch5-8 audio data packet CS error. When set HIGH, a Checksum error has been detected with the audio data packet for audio channels 5 to 8. Ch1-4 audio data packet DBN error. When set HIGH, a Data Block Number error has been detected in the audio data packet for audio channels 1 to 4. Ch1-4 audio data packet 'bit 8' error. When set HIGH, a 'bit 8' error has been detected in the audio data packet for audio channels 1 to 4. Ch1-4 audio data packet error. When set HIGH, an error has been detected in the audio data packet for audio channels 1 to 4, based on the six ECC words. Ch1-4 audio data packet CS error. When set HIGH, a Checksum error has been detected with the audio data packet for audio channels 1 to 4. Ch5-8 ECC correctable packets. Designates the number of audio data packets for channels 5 to 8 that have been corrected in one video frame using the BCH forward error correction system. 014 3-2 R/W 10b DATAIDA[1:0] 014 1-0 R/W 11b DBNB_ERR 015 7 R 0 ADPB8B_ERR 015 6 R 0 ECCB_ERR 015 5 R 0 ADPCSB_ERR 015 4 R 0 DBNA_ERR 015 3 R 0 ADPB8A_ERR 015 2 R 0 ECCA_ERR 015 1 R 0 ADPCSA_ERR 015 0 R 0 CORRECTB [11:0] 016 017 3-0 7-0 R 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 79 of 90 Table 5-29: Demultiplex Mode Host Interface Registers (Continued) Control Item Name Description Address Bit R/W Default NO_CORRECTB [11:0] Ch5-8 ECC un-correctable packets. Designates the number of audio data packets for channels 5 to 8 that could not be corrected in one video frame using the BCH forward error correction system. Ch1-4 ECC correctable packets. Designates the number of audio data packets for channels 1 to 4 that have been corrected in one video frame using the BCH forward error correction system. Ch1-4 ECC un-correctable packets. Designates the number of audio data packets for channels 1 to 4 that could not be corrected in one video frame using the BCH forward error correction system. Audio group 4 control packet detect. When set HIGH, audio control packets with group 4 DID have been detected in the incoming Luma video data stream. Audio group 3 control packet detect. When set HIGH, audio control packets with group 3 DID have been detected in the incoming Luma video data stream. Audio group 2 control packet detect. When set HIGH, audio control packets with group 2 DID have been detected in the incoming Luma video data stream. Audio group 1 control packet detect. When set HIGH, audio control packets with group 1 DID have been detected in the incoming Luma video data stream. Not used. Ch5-8 audio control packet demultiplex enable. When set HIGH, the audio control packets in the Luma channel of the video data stream for audio channels 5 to 8 will be demultiplexed. Ch5-8 audio control packet DID setting. Designates the audio control packet DID for audio channels 5 to 8. See Table 5-24. The default setting is audio group 2. Ch5-8 audio frame number. Designates the audio frame number for audio channels 5 to 8. Ch5-8 sampling frequency. Designates the audio sampling frequency for audio channels 5 to 8, taken from the RATE word of the audio control packet as defined in SMPTE 299M. 018 019 3-0 7-0 R 0 CORRECTA [11:0] 01A 01B 3-0 7-0 R 0 NO_CORRECTA [11:0] 01C 01D 3-0 7-0 R 0 Audio Control Packet ACPG4_DET 020 7 R 0 ACPG3_DET 020 6 R 0 ACPG2_DET 020 5 R 0 ACPG1_DET 020 4 R 0 RSV CTRONB 020 020 3 2 – R/W 0 1 CTRIDB[1:0] 020 1-0 R/W 10b AF_NOB[8:0] 021 022 023 0 7-0 3-1 R/W 0 RATEB[2:0] R/W 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 80 of 90 Table 5-29: Demultiplex Mode Host Interface Registers (Continued) Control Item Name Description Address Bit R/W Default ASXB Ch5-8 synchronization. When set HIGH, the "asx" bit of the audio control packet RATE word designates audio channels 5 to 8 as asynchronous, as per SMPTE 299M. When set LOW, the "asx" bit of the audio control packet RATE word designates synchronous audio. Ch5/6 delay data. Designates the accumulated audio processing delay relative to video for audio channels 5 and 6. 023 0 R/W 0 DEL1-2B[25:0] 024 025 026 027 1-0 7-0 7-0 7-0 1-0 7-0 7-0 7-0 1-0 7-0 7-0 7-3 2 R/W 0 DEL3-4B[25:0] Ch7/8 delay data. Designates the accumulated audio processing delay relative to video for audio channels 7 and 8. 028 029 02A 02B R/W 0 RSRVB[17:0] Ch5-8 reserve words. Designates the value set in the RSRV words of the audio control packet for audio channels 5 to 8, as per SMPTE 299M. Not used. Ch1-4 audio control packet demultiplex enable. When set HIGH, the audio control packets in the Luma channel of the video data stream for audio channels 1 to 4 will be demultiplexed. Ch1-4 audio control packet DID setting. Designates the audio control packet DID for audio channels 1 to 4. See Table 5-24. The default setting is audio group 1. Ch1-4 audio frame number. Designates the audio frame number for audio channels 1 to 4. Ch1-4 sampling frequency. Designates the audio sampling frequency for audio channels 1 to 4, taken from the RATE word of the audio control packet as defined in SMPTE 299M. Ch1-4 synchronization. When set HIGH, the "asx" bit of the audio control packet RATE word designates audio channels 1 to 4 as asynchronous, as per SMPTE 299M. When set LOW, the "asx" bit of the audio control packet RATE word designates synchronous audio. Ch1/2 delay data. Designates the accumulated audio processing delay relative to video for audio channels 1 and 2. 02C 02D 02E 02F 02F R/W 0 RSV CTRONA – R/W 0 1 CTRIDA[1:0] 02F 1-0 R/W 11b AF_NOA[8:0] 030 031 032 0 7-0 3-1 R/W 0 RATEA[2:0] R/W 0 ASXA 032 0 R/W 0 DEL1-2A[25:0] 033 034 035 036 1-0 7-0 7-0 7-0 R/W 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 81 of 90 Table 5-29: Demultiplex Mode Host Interface Registers (Continued) Control Item Name Description Address Bit R/W Default DEL3-4A[25:0] Ch3/4 delay data. Designates the accumulated audio processing delay relative to video for audio channels 3 and 4. 037 038 039 03A 1-0 7-0 7-0 7-0 1-0 7-0 7-0 R/W 0 RSRVA[17:0] Ch1-4 reserve words. Designates the value set in the RSRV words of the audio control packet for audio channels 1 to 4, as per SMPTE 299M. 03B 03C 03D R/W 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 82 of 90 Table 5-29: Demultiplex Mode Host Interface Registers (Continued) Control Item Packet Delete Name Description Address Bit R/W Default RSV Not used. 040 7-2 – 0 ANCI Ancillary data delete. When set HIGH, all ancillary data packets ("DEL_SEL" is LOW) or ancillary data packets with DIDs designated in Host Interface registers 041h and 042h ("DEL_SEL" is HIGH) are removed from the video signal. The ancillary data packets are replaced with blanking codes. The data contained in the packets are output at the corresponding pins. When set LOW, all ancillary data packets remain in the video signal. NOTE: The status of the ANCI external pin is not updated in this register. The value programmed in this register is logical OR'd with the ANCI external pin setting 040 1 R/W 0 DEL_SEL Ancillary data delete mode select. When set HIGH, individual audio groups can be deleted from the video signal by programming Host Interface register 041h. When set LOW, all ancillary data packets are deleted from the video signal. Audio group 4 data packet delete. When set HIGH, all audio data packets with group 4 DID will be deleted from the Chroma video data stream. Valid only when "DEL_SEL" is HIGH. Audio group 3 data packet delete. When set HIGH, all audio data packets with group 3 DID will be deleted from the Chroma video data stream. Valid only when "DEL_SEL" is HIGH. Audio group 2 data packet delete. When set HIGH, all audio data packets with group 2 DID will be deleted from the Chroma video data stream. Valid only when "DEL_SEL" is HIGH. Audio group 1 data packet delete. When set HIGH, all audio data packets with group 1 DID will be deleted from the Chroma video data stream. Valid only when "DEL_SEL" is HIGH. Audio group 4 control packet delete. When set HIGH, all audio control packets with group 4 DID will be deleted from the Luma video data stream. Valid only when "DEL_SEL" is set HIGH. To be fixed. Audio group 3 control packet delete. When set HIGH, all audio control packets with group 3 DID will be deleted from the Luma video data stream. Valid only when "DEL_SEL" is HIGH. To be fixed. 040 0 R/W 0 ADPG4_DEL 041 7 R/W 0 ADPG3_DEL 041 6 R/W 0 ADPG2_DEL 041 5 R/W 0 ADPG1_DEL 041 4 R/W 0 ACPG4_DEL 041 3 R/W 0 ACPG3_DEL 041 2 R/W 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 83 of 90 Table 5-29: Demultiplex Mode Host Interface Registers (Continued) Control Item Name Description Address Bit R/W Default ACPG2_DEL Audio group 2 control packet delete. When set HIGH, all audio control packets with group 2 DID will be deleted from the Luma video data stream. Valid only when "DEL_SEL" is HIGH. To be fixed. Audio group 1 control packet delete. When set HIGH, all audio control packets with group 1 DID will be deleted from the Luma video data stream. Valid only when "DEL_SEL" is HIGH. To be fixed. Arbitrary data packet delete. Designates the DID for the arbitrary data packets to be deleted from the Luma video data stream. Valid only when "DEL_SEL" is HIGH. Arbitrary data packet demultiplex. Valid only when "ARBITMODE" is HIGH. When set HIGH, arbitrary data packets will be demultiplexed from the Luma video data stream. Must be set LOW again to access valid data in the "ARBITUDW" registers. Arbitrary packet mode select. When set HIGH, arbitrary data packets are demultiplexed and the User Data Words are stored in Host Interface registers 100h to 1FEh. No data will be output on the PKT[7:0] external pins and PTKTEN will be LOW. When set LOW, arbitrary data packets are demultiplexed and output at the PKT[7:0] external pins. Arbitrary packet Data ID setting. Designates the 8 LSBs of the DID word of the arbitrary data packet to be demultiplexed. The 2 MSBs are internally generated. "ARBITDID[7]" is the MSB and "ARBITDID[0]" is the LSB. Valid only when "ARBITMODE" is HIGH. Arbitrary packet Secondary Data ID setting. Designates the 8 LSBs of the secondary DID word of the arbitrary data packet to be demultiplexed. The 2 MSBs are internally generated. "ARBITSDID[7]" is the MSB and "ARBITSDID[0]" is the LSB. Valid only when "ARBITMODE" is HIGH. Arbitrary packet DC setting. Designates the 8 LSBs of the Data Count word of the arbitrary data packet to be demultiplexed. The 2 MSBs are internally generated. "ARBITDC[7]" is the MSB and "ARBITDC[0]" is the LSB. Valid only when "ARBITMODE" is HIGH. Field 2 arbitrary packet demultiplex line number setting. Designates the field 2 video line from which the arbitrary data packets will be demultiplexed. Valid only when "ARBITMODE" is HIGH. 041 1 R/W 0 ACPG1_DEL 041 0 R/W 0 NDID[7:0] 042 7-0 R/W 0 Arbitrary Data Packet ARBITON 050 1 R/W 0 ARBITMODE 050 0 R/W 0 ARBITDID[7:0] 051 7-0 R/W 0 ARBITSDID[7:0] 052 7-0 R/W 0 ARBITDC[7:0] 053 7-0 R/W 0 ARBITLINEB [11:0] 054 055 3-0 7-0 R/W 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 84 of 90 Table 5-29: Demultiplex Mode Host Interface Registers (Continued) Control Item Name Description Address Bit R/W Default ARBITLINEA [11:0] Field 1 arbitrary packet demultiplex line number setting. Designates the field 1 video line from which the arbitrary data packets will be demultiplexed. Valid only when "ARBITMODE" is HIGH. Arbitrary packet User Data Word. Designates the 8 LSBs for up to 255 arbitrary packet User Data Words. Arbitrary data can be read from these registers once "ARBITON" has been set HIGH to LOW. Valid only when "ARBITMODE" is HIGH. 056 057 3-0 7-0 R/W 0 ARBITUDW0 : ARBITUDW254 100 : 1FE 7-0 : 7-0 R/W 0 GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 85 of 90 6. Using the GS1503B with the GS4911B or GS4910B In Serial Audio multiplex mode, the GS4911B or GS4901B can be used to provide clocks for the input audio. Figure 6-1 shows this arrangement. Video Data Video Chain PCLK (74.25MHz) VIN[19:0] PCLK ACLKA WCINA AIN1/2 AIN3/4 HVF ACLKA (128fs) WCLKA (48kHz) AIN1/2 AIN3/4 Audio Chain MCLK (256fs)* SCLK (128fs) WCLK (48kHz) GS1503B GS49X1B ACLK1 ACLK2 ACLK3 *Optional Figure 6-1: Using the GS1503B with the GS4911B or GS4910B in Serial Audio Mode GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 FSYNC VSYNC HSYNC ACLKB (128fs) WCLKB (48kHz) AIN5/6 AIN7/8 ACLKB WCINB AIN5/6 AIN7/8 86 of 90 7. References & Bibliography SMPTE 260M 1999 1125/60 High-Definition Production System - Digital Representation and Bit-Parallel Interface 1998 1920 x 1080 Scanning and Analog and Parallel Digital Interfaces for Multiple Picture Rates 1998 Ancillary Data Packet and Space Formatting 1998 Bit-Serial Digital Interface for High-Definition Television Systems 1997 1920 x 1080 50 Hz - Scanning and Interfaces 2001 1280 x 720 Scanning, Analog and Digital Representation and Analog Interface 1997 24-Bit Digital Audio Format for HDTV Bit-Serial Interface 2000 Implementation of 24P, 25P and 30P Segmented Frames for 1920 x 1080 Production Format SMPTE 274M SMPTE 291M SMPTE 292M SMPTE 295M SMPTE 296M SMPTE 299M SMPTE RP211 AES3-1992 (ANSI S4.40-1992) AES Recommended practice for digital audio engineering Serial transmission format for two-channel linearly represented digital audio data AES-3id-2001 AES information document for digital audio engineering - Transmission of AES3 formatted data by unbalanced coaxial cable EBU Tech. 3250-E Specification of the Digital Audio Interface (The AES/EBU Interface) (Second Edition 1992) Society of Motion Picture and Television Engineers: http://www.smpte.org Audio Engineering Society: http://www.aes.org European Broadcast Union: http://www.ebu.ch GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 87 of 90 8. Packaging & Ordering Information 8.1 Package Dimensons 18.0 ± 0.4 16.0 ± 0.1 108 73 109 72 View on A-A 18.0 ± 0.4 16.0 ± 0.1 A 0.09-0.20 0˚ MIN 8˚ MAX INDEX 144 37 1.0 REF 0.50 ±0.2 1 36 1.0 ± 0.1 1.20 MAX 144 pin TQFP Dimensions in millimetres 0.4 0.13-0.23 0.1 8.2 Packaging Data Parameter Package Type Moisture Sensitivity Level Junction to Case Thermal Resistance, θj-c Junction to Air Thermal Resistance, θj-a (at zero airflow) Pb-free and RoHS Compliant Value 144 pin TQFP 3 4°C/W 39°C/W Yes GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 88 of 90 8.3 Ordering Information Part Number GS1503BCVE2 Package 144 pin TQFP Temperature 0°C to 70°C Pb-Free Yes RoHS-Compliant Yes GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 89 of 90 9. Revision History Version 1 0 ECR 153293 139048 Date December 2009 August 2006 Changes / Modifications Updated document format. New document. DOCUMENT IDENTIFICATION CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DATA SHEET The product is in production. Gennum reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. 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Sinyi District, Taipei City 11502 Taiwan R.O.C. Phone: (886) 2-8732-8879 Fax: (886) 2-8732-8870 E-mail: gennum-taiwan@gennum.com Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. All other trademarks mentioned are the properties of their respective owners. GENNUM and the Gennum logo are registered trademarks of Gennum Corporation. © Copyright 2006 Gennum Corporation. All rights reserved. www.gennum.com GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 90 of 90 90