GS1504-CTD

HD-LINX ™ GS1504 HDTV Adaptive Equalizer DATA SHEET FEATURES • SMPTE 292M compliant • Automatic, adjustment free cable equalization for 1.485Gb/s HDTV signals • Differential serial outputs capable of driving 50Ω loads • Typically equalizes 100m of Belden 8281 or 150m of Belden 1694 high quality co-axial cable • Cable Length Indication • Output Mute • Maximum Cable Length Adjust • Low power • Minimal external components • Single +5V or -5V power supply operation • Pb-free and Green APPLICATIONS 1.485Gb/s HDTV Serial Digital Receiver Interfaces for Routers, Distribution Amplifiers, Switchers, and other receiving equipment. DESCRIPTION The GS1504 is a high performance cable equalizer designed to equalize HDTV component signal conforming to SMPTE 292M. The adaptive cable equalizer is capable of equalizing up to 100m of Belden 8281 co-axial cable. The GS1504 features DC restoration for immunity to the DC content in pathological test patterns. The device also incorporates a Cable Length Indicator signal that provides an indication of the amount of cable being equalized. A voltage programmable mute threshold (MCLADJ) is included to allow muting of the GS1504 output when a selected cable length is reached. This feature allows the GS1504 to distinguish between low amplitude HD SDI signals and noise at the input of the device. The CD/Mute pin provides an indication of the GS1504 mute status in addition to functioning as a mute control input. The output of the GS1504 may be forced to an active or a mute condition by applying a voltage to the CD/Mute pin. The GS1504 is a low power device that operates from a single 5V power supply. The GS1504 is packaged in a 16 pin narrow SOIC and does not need external pull-up resistors. GS1504 ORDERING INFORMATION PART NUMBER GS1504-CKD GS1504-CTD GS1504-CKDE3 GS1504-CTDE3 PACKAGE 16 pin narrow SOIC 16 pin Tape and Reel 16 pin narrow SOIC 16 pin Tape and Reel TEMPERATURE 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C Pb-FREE AND GREEN No No Yes Yes MCLADJ CABLE LENGTH INDICATOR/ADJUSTOR CARRIER DETECT MUTE CLI CD/MUTE SDI SDI EQUALIZER DC RESTORE SDO OUTPUT SDO AGC PATENT PENDING BLOCK DIAGRAM Revision Date: June 2004 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com Document No. 522 - 05 - 05 ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise indicated PARAMETER Supply Voltage Input Voltage Range (any input) VALUE 5.5V -0.3 to (VCC +0.3)V 0°C to 70°C -65°C to 150°C 300mW 260°C 2000V GS1504 Operating Temperature Range Storage Temperature Power Dissipation Lead Temperature (soldering, 10 sec) Input ESD Voltage DC ELECTRICAL CHARACTERISTICS VCC = 5V, VEE = 0V, TA = 0°C to 70°C, Data Rate = 1.485Gb/s PARAMETER Positive Supply Voltage Power Consumption Supply Current Output CM Voltage Input DC Voltage CLI DC Voltage (0m) CLI DC Voltage (no signal input) Cable Length Indicator Range MCLADJ DC Voltage CONDITIONS SYMBOL VCC MIN 4.75 3.75 TYP 5.00 250 50 4 2.7 3.3 1.3 2 3.1 MAX 5.25 65.0 4.25 1.7 3.4 UNITS V mW mA V V V V V V TEST LEVELS 1 1 1 1 1 4 1 2 1 Internal Bias. See Figure 2 CLI Output for 0m Cable 0.9 0 - Max m MCLADJ Input Voltage Required to Mute Output (max cable to 0m) Output Voltage of CD/Mute when Output is Active Min to Mute; VCD/Mute Max to Activate; VCD/Mute 2. Guaranteed by design. CLI 2.80 MCLADJ Range Mute DC Voltage 1 1.5 1.8 2.1 V V 2 1 Voltage Required to Force Outputs to Mute Voltage Required to Force Outputs Active TEST LEVELS: 1. 100% tested at 25°C. 4.2 3.8 3. Correlated Value. 4. Using EB1504 V V 2 2 GigaBERT 1400 EXT. CLOCK DATA CLOCK OUT OUT 50/75 2k EXT. CLOCK 1.485GHz 10k 15k DVM 8281 or 1694A CABLE IN CLI GS1504 EVAL. BOARD MCLADJ OUT OUT CH. 1 CH. 2 TDS 820 EXT. TRIGGER Fig. 1 Test Setup 2 of 13 522 - 05 - 05 AC ELECTRICAL CHARACTERISTICS VCC = 5V, VEE = 0V, TA = 0°C to 70°C, Data Rate = 1.485Gb/s PARAMETER Jitter Equalization CONDITIONS 100m (8281), PRN and pathological Belden 8281 Belden 1694 SYMBOL MIN 160 TYP 80 100 150 130 2.8 1 50 200 MAX 135 270 . 240 UNITS ps p-p m m ps kΩ pF Ω mVp-p TEST LEVEL 1 1 3 1 2 2 2 1 GS1504 Output Rise/Fall Time Input Resistance Input Capacitance Output Resistance Output Signal Swing SDO, SDO TEST LEVELS: 1. 100% tested at 25°C. 20% - 80% Single Ended Single Ended Single Ended Into 50Ω Loads; See Figure 21. 2. Guaranteed by design. 3. Correlated Value. 4. Using EB1504 PIN CONNECTIONS CLI VCC VEE SDI SDI VEE MCLADJ NC 1 2 3 4 5 6 7 8 GS1504 TOP VIEW 16 15 14 13 12 11 10 9 CD/MUTE VCC VEE SDO SDO VEE NC NC PIN DESCRIPTIONS NUMBER 1 SYMBOL CLI TYPE O DESCRIPTION Cable Length Indication. Provides a voltage output representing the amount of cable being equalized. See figures 19 and 20. The CLI voltage is an approximation of the cable length being equalized. It is intended as a guide for troubleshooting the initial design and not as an accurate indication of cable length. Most positive supply voltage. Most negative supply voltage. Differential Input Pins. AC coupled termination is recommended. Adjusts the maximum amount of cable to be equalized (from 0m to the maximum cable length). The output is muted (latched to the last state) when the maximum cable length is reached. To achieve maximum cable length, this pin should be left open. See figures 10 - 12. No Connect. Do not connect these pins to supply or ground. Differential Serial Data Output Pins, with 50Ω output resistance. Carrier Detect/Mute Indicator/Control. When the CD/Mute output is low, the carrier is present and the data output is active. When the CD/Mute output is high, the carrier is not present and the data output is muted (latched to the last state). This indicates that the maximum cable length as set by MCLADJ has been reached. The above default CD/Mute function can be overwritten as follows: if the CD/Mute pin is tied to ground the data output will not mute and the MCLADJ setting is overwritten. If the mute pin is tied high, the data output will always mute and the MCLADJ setting is overwritten. 2, 15 3, 6, 11, 14 4, 5 7 VCC VEE SDI, SDI MCLADJ I I I I 8, 9, 10 12, 13 16 NC SDO, SDO CD/Mute O I/O 3 of 13 522 - 05 - 05 INPUT/OUTPUT CIRCUITS All resistors in ohms, all capacitors in farads, unless otherwise shown. VCC 10k 6k SDI RC 7k 7k + CLI 6k SDI 10k GS1504 Fig. 2 Input Equivalent Circuit Fig. 5 CLI Output Circuit VCC VCC 40k + MCLADJ OUTPUT STAGE MUTE CONTROL 20k CD/MUTE 10k 42µ Fig. 3 MCLADJ Equivalent Circuit Fig. 6 CD/Mute Circuit 50 50 SDO SDO Fig. 4 Output Circuit 4 of 13 522 - 05 - 05 TYPICAL PERFORMANCE CURVES (unless otherwise shown, VCC = 5V, TA = 25°C) 350 POWER CONSUMPTION (mW) 300 250 200 GS1504 150 MCLADJ MCLADJ 100 50 0 0 20 40 60 80 Uncompensated MCLADJ Temperature Compensated MCLADJ TEMPERATURE (˚C) Fig. 7 Power Consumption Fig. 10 Temperature Compensation of MCLADJ 800 700 102 100 98 CABLE LENGTH (m) 600 96 94 92 90 88 86 84 Uncompensated Compensated JITTER (ps) 500 400 300 200 100 0 0 50 100 150 200 0 20 40 60 80 CABLE LENGTH (m) TEMPERATURE (˚C) Fig. 8 Typical Peak to Peak Jitter, PRN 2 -1, Belden 1694A 23 Fig. 11 Typical 1694A Cable Length vs. Temperature (%) CC 800 700 600 90 80 70 60 50 40 30 20 10 500 400 300 200 100 0 0 50 100 150 200 VOLTAGE NORMALIZED TO V JITTER (ps) 0 0 50 100 150 200 CABLE LENGTH (m) CABLE LENGTH (m) Fig. 9 Typical Peak to Peak Jitter, PRN 2 -1, Belden 8281 23 Fig. 12 MCLADJ Input Voltage vs 1694A Cable Length 5 of 13 522 - 05 - 05 TYPICAL PERFORMANCE CURVES (unless otherwise shown VCC = 5V, TA = 25°C) GS1504 Fig. 13 Input 100m (Belden 1694A) Fig. 16 Output 150m (Belden 1694A) 50 40 30 20 10 0 -10 -20 -30 -40 -50 0.05 GHz 1 GHz 2 GHz Fig. 14 Output 100m (Belden 1694A) Fig. 17 Input Return Loss 500 OUTPUT SIGNAL SWING (mV) 400 300 200 100 0 0 20 40 60 80 TEMPERATURE (˚C) Fig. 15 Input 150m (Belden 1694A) Fig. 18 Output Signal Swing, p-p, Differential 6 of 13 522 - 05 - 05 3.5 3 2.5 2 1.5 1 0.5 0 0 50 100 150 200 steady control voltage for the gain stage. As the frequency response of the gain stage is automatically varied by the application of negative feedback, the edge energy of the equalized signal is kept at a constant level which is representative of the original edge energy at the transmitter. The equalized signal is also DC restored, effectively restoring the logic threshold of the equalized signal to its correct level independent of shifts due to AC coupling. The digital output signals have a nominal voltage of 400mVpp differential, or 200mVpp single ended when terminated with 50Ω as shown in Figure 21. +100mV VCM = 4.0V typical SDO -100mV CLI VOLTAGE (V) GS1504 CABLE LENGTH (m) Fig. 19 CLI Voltage vs. Belden 1694A Cable Length 3.5 3 CLI VOLTAGE (V) SDO 2.5 2 1.5 1 0.5 0 0 50 100 150 +100mV 50 50 VCM = 4.0V typical -100mV Fig. 21 Typical Output Voltage Levels CABLE LENGTH INDICATION/CARRIER DETECT/MUTE CABLE LENGTH (m) Fig. 20 CLI Voltage vs. Belden 8281 Cable Length The GS1504 incorporates a versatile analog cable length indicator (CLI) output and a programmable threshold output mute (MCLADJ). In addition, a multi-function CD/MUTE pin allows control of the GS1504 MUTE functionality. The voltage output of CLI pin is an approximation of the amount of cable present at the GS1504 input. The CLI voltage versus cable length (signal strength) is shown in Figures 19 and 20. With 0m of cable (800mV input signal levels), the CLI output voltage is approximately 3.3V. As the cable length increases, the CLI voltage decreases providing an approximate correlation between the CLI voltage and cable length. In applications where there are multiple input channels using the GS1504, it is advantageous to have a programmable mute output. The output of the GS1504 can be muted when the input signal decreases below a preselected input level. The voltage applied to the MCLADJ pin vs input cable length is shown in Figure 12. The MCLADJ pin may be left unconnected for applications where output muting is not required. This feature has been designed for use in applications such as routers where signal crosstalk and circuit noise cause the equalizer to output erroneous data when no input signal is present. The use of a Carrier Detect function with a fixed internal reference does not solve this problem since the signal to noise ratio on the circuit board DETAILED DESCRIPTION The GS1504 is a high speed bipolar IC designed to equalize HD serial digital data at a rate of 1.485Gb/s. The device can typically equalize greater than 100 meters of Belden 8281 cable or 150 meters of Belden 1694 cable. Powered from a single +5V or -5V power supply, the device consumes approximately 250mW of power The HD serial data signal may be connected to the input pins (SDI/SDI) in either a differential or single ended configuration. AC coupling of the inputs is recommended, as the SDI and SDI inputs are internally biased at approximately 2.7 volts. The input signal passes through a variable gain equalizing stage whose frequency response closely matches the inverse cable loss characteristic. In addition, the variation of the frequency response with control voltage imitates the variation of the inverse cable loss characteristic with cable length. The edge energy of the equalized signal is monitored by a detector circuit which produces an error signal corresponding to the difference between the desired edge energy and the actual edge energy. This error signal is integrated by an internal AGC filter capacitor providing a 7 of 13 522 - 05 - 05 could be significantly less than the default signal detection level set by the on chip reference. The CD/Mute pin is a multi-function bidirectional pin that provides the following functions: • Applying a HIGH INPUT to the CD/Mute pin forces the GS1504 outputs to a muted condition. See the DC electrical characteristics table for voltage level. In this condition the outputs will be latched to the last logic level present at the output. • Applying a LOW INPUT to the CD/Mute pin will force the GS1504 outputs to remain active regardless of the length of input cable and the voltage applied to the MCLADJ pin. See the DC electrical characteristics table for voltage level. When used as an OUTPUT, the CD/Mute pin will provide an indication of the output mute status. The CD/Mute pin will be logic HIGH when the output is muted, and logic LOW when the outputs are not muted. • GS1504 TYPICAL APPLICATION CIRCUIT VCC 1 CLI 10n 10nH 47p 75 47p 37.5 10n 1 J3 2 VCC 2k 10k 1µ 15k All resistors in ohms, all capacitors in farads, unless otherwise shown. VCC 75 16 CD/MUTE VCC VEE 15 14 13 12 11 10 9 10n VCC + 4µ7 + 4µ7 10n VCC VEE SDI 2 3 4 5 SDI 6 7 8 NC VEE MCLADJ GS1504 SDO SDO VEE NC NC VCC 100n 1n 8 of 13 522 - 05 - 05 APPLICATION INFORMATION PCB LAYOUT Special attention must be paid to component layout when designing serial digital interfaces for HDTV. Figures 23 through 27 show the artwork for a four layer printed circuit evaluation board for the GS1504. The schematic is shown in Figure 22. An FR-4 dielectric can be used, however, controlled impedance transmission lines are required for PCB traces longer than approximately 1cm. Note the following PCB artwork features used to optimize performance: • PCB trace width for HD rate signals is closely matched to SMT component width to minimize reflections due to change in trace impedance. • The PCB ground plane is removed under the GS1504 input components to minimize parasitic capacitance. The PCB ground plane is removed under the GS1504 output components to minimize parasitic capacitance. • GS1504 • High speed traces are curved to minimize impedance changes. A picture of the GS1504 PCB assembly is shown in Figure 28. GS1504 EVALUATION BOARD J5 VCC R1 75 L4 J1 10nH R4 75 37 R2 47p C7 C8 47p 10n C5 TP1 VCC 1 10n C6 2 3 4 5 6 7 8 J4 2k R5 10k R3 CLI VCC VEE SDI SDI VEE CD/MUTE VCC VEE SDO SDO VEE NC NC 16 15 14 13 12 11 10 9 10n C4 VCC 4.7µ + C1 + C2 4.7µ C3 10n J2 J3 MCLADJ NC VCC C1, C2 must be tantalum capacitors. All resistors in ohms, all capacitors in farads, unless otherwise shown. C10 1µ 15k R6 C9 100n C11 1n Fig. 22 GS1504 Application Schematic 9 of 13 522 - 05 - 05 GS1504 Fig. 23 Silk Screen of EB1504 PCB Layout Fig. 26 Bottom Layer of EB1504 PCB Layout Fig. 24 Top Layer of EB1504 PCB Layout Fig. 27 Power Layer of EB1504 PCB Layout Fig. 25 Ground Layer of EB1504 PCB Layout Fig. 28 Photograph of GS1504 Evaluation Board 10 of 13 522 - 05 - 05 GS1504 / GS1508 INTERFACING Figures 30 through 34 show the artwork for a four layer printed circuit evaluation board for the GS1504. The schematic is shown in Fig 29. An FR-4 dielectric can be used, however, controlled impedance transmission lines are required for PCB traces longer than approximately 1cm. Note the following PCB artwork features used to optimize performance: • PCB trace width for HD rate signals is closely matched to SMT component width to minimize reflections due to change in trace impedance. • The PCB ground plane is removed under the GS1504/GS1508 input components to minimize parasitic capacitance. The PCB ground plane is removed under the GS1504/GS1508 output components to minimize parasitic capacitance. • GS1504 • High speed traces are curved to minimize impedance changes. A picture of the GS1504/08 PCB assembly is shown in Figure 34. VCC TP1 VCC C1 1µ C2 100n C3 1n TP2 GND R8 49.9 VCC C6 10n TP3 CLI J1 16 15 14 13 12 11 10 9 C4 10n VCC R11 53.6 VCC C20 10n 1 2 3 4 C16 1n VCC R7 49.9 R8 75 C10 100n R7 75 L2 12n R9 75 C17 1p C18 1p R10 75 L3 12n J4 4µ7 SDO EDGEMNT_BNC J5 C12 4µ7 SDO EDGEMNT_BNC C11 C11 AND C12 ARE TC3216 TANTALUM CAPACITORS. CLOSE TO MUTE J2 R16 75 L4 10n R1 75 R15 37.5 1 CLI 2V CD/MUTE VCC VEE SDO SDO VEE nc nc VIDEO IN C7 47p C8 47p C5 10n 2 J3 1 VCC R4 2k 3V EE 4 SDI 5 SDI 6V CC U2 SDI SDI VEE SDO 8 SDO 7 GND 6 5 V 7 MCLADJ 8 nc EE RSET CC C15 10n VCC GS1508 R5 10k R6 15k All resistors in ohms, all capacitors in farads, unless otherwise shown. Fig. 29 GS1504/08 Evaluation Board Assembly 11 of 13 522 - 05 - 05 GS1504 Fig. 30 Top Layer of EB1504/08 PCB Layout Fig. 32 Ground Layer of EB1504/08 PCB Layout Fig. 31 Power Layer of EB1504/08 PCB Layout Fig. 33 Bottom Layer of EB1504/08 PCB Layout = Fig. 34 Photograph of GS1504/GS1508 Evaluation Board 12 of 13 522 - 05 - 05 PACKAGE DIMENSIONS 16 9 E H 0 L 0.010" GS1504 Gauge Plane 1 b 8 Detail F D A2 A c e Seating Plane A1 Y L1 See Detail F CONTROLLING DIMENSION: MM SYMBOL MIN A A1 A2 b c D E e H L L1 Y 0 0° 5.80 0.40 1:35 0.10 1.30 0.33 0.19 9.80 3.80 9.91 3.90 1.27 6.00 0.64 1.07 0.10 8° 0° 6.20 1.27 0.228 0.016 MILLIMETER NOM 1:63 0.15 1.40 0.41 MAX. 1.75 0.25 1.50 0.51 0.25 10.01 4.00 MIN. 0.053 0.004 0.051 0.013 0.007 0.386 0.150 0.390 0.154 0.050 0.236 0.025 0.042 0.004 8° 0.244 0.050 INCH NOM. 0.064 0.006 0.055 0.016 MAX 0.069 0.010 0.059 0.020 0.010 0.394 0.157 CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DOCUMENT IDENTIFICATION DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. REVISION NOTES: Added Pb-free and green information. For the latest product information, visit www.gennum.com GENNUM CORPORATION MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F 6-14-1, Nishi Shinjuku Shinjuku-ku, Tokyo 160-0023 Japan Tel: +81 (03) 3349-5501 Fax: +81 (03) 3349-5505 GENNUM UK LIMITED Centaur House, Ancells Bus. Park, Ancells Rd, Fleet, Hants, England GU13 8UJ Tel. +44 (0)1252 761 039 Fax +44 (0)1252 761 114 Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. © Copyright August 1998 Gennum Corporation. All rights reserved. Printed in Canada. 13 of 13 522 - 05 - 05