GS1524A

GS1524A HD-LINX®II Adaptive Cable Equalizer GS1524A Data Sheet Features • • • • • • • • • • • • • • SMPTE 292M, SMPTE 344M and SMPTE 259M compliant Automatic cable equalization Multi-standard operation from 143Mb/s to 1.485Gb/s Supports DVB-ASI at 270Mb/s Pb-free and RoHS Compliant Pin compatible with the GS9064 Cable Equalizer Manual bypass (useful for low data rates with slow rise/fall times) Performance optimized for 270Mb/s and 1.485Gb/s Typical maximum equalized length of Belden 1694A cable: 140m at 1.485Gb/s, 350m at 270Mb/s 50Ω differential output (with internal 50Ω pull-ups) Manual output mute or programmable mute based on max cable length adjust Cable length indicator for SMPTE 259M inputs Single 3.3V power supply operation Operating temperature range: 0°C to +70°C Description The GS1524A is a second-generation high-speed bipolar integrated circuit designed to equalize and restore signals received over 75Ω co-axial cable. The GS1524A is designed to support SMPTE 292M, SMPTE 344M and SMPTE 259M, and is optimized for performance at 270Mb/s and 1.485Gb/s. The GS1524A features DC restoration to compensate for the DC content of SMPTE pathological test patterns. The device also incorporates a Cable Length Indicator (CLI) that provides an indication of the amount of cable being equalized for data rates up to 360Mb/s. A voltage programmable mute threshold (MCLADJ) is included to allow muting of the GS1524A output when an approximate selected cable length is reached for SMPTE 259M signals. This feature allows the GS1524A to distinguish between low amplitude SD-SDI signals and noise at the input of the device. The bidirectional CD/MUTE pin indicates the presence of a valid signal at the input of the GS1524A in addition to functioning as a mute control input. The outputs of the GS1524A will be forced to a mute state when an invalid input reference signal is applied to the input of the device or the application layer sets the CD/MUTE pin HIGH. If the application layer forces CD/MUTE LOW, the serial digital output of the device will always be active. Power consumption is typically 265mW using a 3.3V power supply. The GS1524A is Pb-free, and the encapsulation compound does not contain halogenated flame retardant (RoHS Compliant). Applications • SMPTE 292M, SMPTE 344M and SMPTE 259M Coaxial Cable Serial Digital Interfaces. 28852 - 1 May 2005 1 of 16 www.gennum.com GS1524A Data Sheet MCLADJ CABLE LENGTH INDICATOR/ADJUSTOR CARRIER DETECT MUTE CLI CD/MUTE BYPASS SDI SDI EQUALIZER DC RESTORE OUTPUT SDO SDO AGC GS1524A Functional Block Diagram Contents Features .......................................................................................................................1 Applications ..................................................................................................................1 Description ...................................................................................................................1 1. Pin Out ..................................................................................................................... 3 1.1 GS1524A Pin Assignment ..............................................................................3 1.2 GS1524A Pin Descriptions .............................................................................4 2. Electrical Characteristics .......................................................................................... 5 2.1 Absolute Maximum Ratings ............................................................................5 2.2 DC Electrical Characteristics ..........................................................................5 2.3 AC Electrical Characteristics ...........................................................................6 2.4 Solder Reflow Profiles .....................................................................................7 3. Input / Output Circuits .............................................................................................. 9 4. Detailed Description ............................................................................................... 11 4.1 Serial Digital Inputs .......................................................................................11 4.2 Cable Equalization ........................................................................................11 4.3 Programmable Mute Output and Cable Length Indicator .............................12 4.4 Mute and Carrier Detect ................................................................................13 5. Application Information........................................................................................... 14 5.1 PCB Layout ...................................................................................................14 5.2 Typical Application Circuits ...........................................................................14 6. Package & Ordering Information ............................................................................ 15 6.1 Package Dimensions ....................................................................................15 6.2 Packaging Data .............................................................................................15 6.3 Ordering Information .....................................................................................15 7. Revision History ..................................................................................................... 16 28852 - 1 May 2005 2 of 16 GS1524A Data Sheet 1. Pin Out 1.1 GS1524A Pin Assignment CLI VCC V EE 1 2 3 4 5 6 7 8 GS1524A (top view) 16 15 14 13 12 11 10 9 CD/MUTE VCC VEE SDO SDO V EE SDI SDI VEE AGC+ AGC- MCLADJ BYPASS Figure 1-1: 16-Pin SOIC 28852 - 1 May 2005 3 of 16 GS1524A Data Sheet 1.2 GS1524A Pin Descriptions Table 1-1: GS1524A Pin Descriptions Pin Number 1 Name CLI Timing Analog Type Output Description Cable Length Indicator. An analog voltage will be output proportional to the cable length connected to the serial digital input. NOTE: CLI is recommended for data rates up the 360Mb/s only. 2, 15 VCC Analog Power Most positive power supply connection. Connect to +3.3V DC. 3, 6, 11, 14 VEE Analog Power Most negative power supply connection. Connect to GND. 4, 5 7, 8 SDI, SDI AGC+, AGCBYPASS MCLADJ Analog Analog Input – Serial digital differential input. External AGC capacitor. Connect pin 7 and pin 8 together through a 1uF capacitor. 9 10 Not Synchronous Analog Input Input Forces the Equalizing and DC RESTORE stages into bypass mode when HIGH. No equalization occurs in this mode. Maximum cable length adjust. Adjusts the approximate maximum amount of cable to be equalized (from 0m to the maximum cable length). The output is muted (latched to the last state) when the maximum cable length is achieved. NOTE: MCLADJ is only recommended for data rates up to 360Mb/s. 12, 13 16 SDO, SDO CD/MUTE Analog Not Synchronous Output Bidirectional Equalized serial digital differential output. STATUS SIGNAL OUTPUT / CONTROL SIGNAL INPUT levels are LVCMOS/LVTTL compatible. OUTPUT (CD): Indicates the presence of a valid input signal. When the CD pin is LOW, a valid input signal has been detected. When this pin is HIGH, the input signal is invalid. If CD is set HIGH, the serial digital output of the device will be forced to a steady state (latched to the last state). NOTE: This pin will indicate loss of carrier for data rates > 19Mb/s. INPUT (MUTE): When the MUTE pin is set HIGH by the application interface, the serial digital output of the device will be forced to a steady state (latched to the last state). When the MUTE pin is set LOW, the serial digital output of the device will be active. NOTE: The CD/MUTE pin is not functional when BYPASS is set HIGH. 28852 - 1 May 2005 4 of 16 GS1524A Data Sheet 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Parameter Supply Voltage Input ESD Voltage Storage Temperature Range Input Voltage Range (any input) Operating Temperature Range Solder Reflow Temperature Value -0.5V to +3.6 VDC 2kV -50°C < Ts < 125°C -0.3 to (VCC +0.3)V 0°C to 70°C 260°C 2.2 DC Electrical Characteristics Table 2-1: DC Electrical Characteristics VDD = 3.3V, TA = 0°C to 70°C, unless otherwise shown Parameter Supply Voltage Power Consumption Supply Current Output Common Mode Voltage Input Common Mode Voltage CLI DC Voltage (0m) CLI DC Voltage (no signal) MCLADJ DC Voltage (to mute signal) MCLADJ Range CD/MUTE Output Voltage Symbol VCC PD Is VCMOUT VCMIN – – – – VCD/MUTE(OH) VCD/MUTE(OL) Conditions – TA = 25°C TA = 25°C TA = 25°C TA = 25°C TA = 25°C TA = 25°C 0m, TA = 25°C TA = 25°C Carrier not present Carrier present Min 3.135 – – – – – – – – 2.4 – Typ 3.3 265 80 VCC - ΔVSDO/2 1.75 2.5 1.9 1.3 0.69 – – Max 3.465 – – – – – – – – – 0.4 Units V mW mA V V V V V V V V Notes ±5% – – – – – – – – – – 28852 - 1 May 2005 5 of 16 GS1524A Data Sheet Table 2-1: DC Electrical Characteristics VDD = 3.3V, TA = 0°C to 70°C, unless otherwise shown Parameter CD/MUTE Input Voltage Required to Force Outputs to Mute CD/MUTE Input Voltage Required to Force Outputs Active Symbol VCD/MUTE Conditions Mute Min 2.0 Typ – Max – Units V Notes – VCD/MUTE Activate – – 0.8 V – 2.3 AC Electrical Characteristics VDD = 3.3V, TA = 0°C to 70°C, unless otherwise shown Parameter Serial input data rate Input Voltage Swing Output Voltage Swing Symbol DRSDO ΔVSDI ΔVSDO – – – Conditions GS1524A TA =25°C, at transmitter 50Ω load, TA =25°C, differential 270Mb/s, Belden 1694A, 350m equalized cable 270Mb/s, Belden 8281, 280m equalized cable 1.485Gb/s, Belden 1694A, 140m equalized cable 1.485Gb/s, Belden 8281, 100m equalized cable 20% - 80% – – – – single ended single ended single ended Min 143 720 – Typ – 800 750 Max 1485 950 – Units Mb/s mVp-p mVp-p UI UI UI Notes – – – Output Jitter – – – 0.2 0.2 0.25 – – – 1 1 1 – Output Rise/Fall time Mismatch in rise/fall time Duty cycle distortion Overshoot Input Return Loss Input Resistance Input Capacitance Output Resistance NOTES: – – – – – – – – – – – – – 15 – – – 0.25 80 – – – – 1.64 1 50 – 220 30 30 10 – – – – UI ps ps ps % dB kΩ pF Ω 1 – – – – 2 – – – 1. Equalizer Pathological. 2. Tested on CB1524 board from 5MHz to 2GHz. 28852 - 1 May 2005 6 of 16 GS1524A Data Sheet 2.4 Solder Reflow Profiles The device is manufactured with Matte-Sn terminations and is compatible with both standard eutectic and Pb-free solder reflow profiles. MSL qualification was performed using the maximum Pb-free reflow profile shown in Figure 2-1. The recommended standard Pb reflow profile is shown in Figure 2-2. Temperature 60-150 sec. 20-40 sec. 260˚C 250˚C 3 ˚C/sec max 217˚C 6˚C/sec max 200˚C 150˚C 25˚C Time 60-180 sec. max 8 min. max Figure 2-1: Maximum Pb-free Solder Reflow Profile (Preferred) Temperature 60-150 sec. 10-20 sec. 230˚C 220˚C 3 ˚C/sec max 183˚C 6˚C/sec max 150˚C 100˚C 25˚C Time 120 sec. max 6 min. max Figure 2-2: Standard Pb Solder Reflow Profile (Pb-free package) 28852 - 1 May 2005 7 of 16 GS1524A Data Sheet GigaBERT 1400 EXT. CLOCK DATA CLOCK OUT OUT 50/75 8281 or 1694A CABLE IN GS1524A TEST BOARD OUT OUT CH. 1 CH. 2 TDS 820 EXT. TRIGGER EXT. CLOCK 1.485GHz/270MHz Figure 2-3: Test Circuit 28852 - 1 May 2005 8 of 16 GS1524A Data Sheet 3. Input / Output Circuits 3k SDI RC 3.6k 3k SDI 3.6k Figure 3-1: Input Equivalent Circuit VCC 12k + MCLADJ - 150µ Figure 3-2: MCLADJ Equivalent Circuit 50 50 SDO SDO Figure 3-3: Output Circuit 28852 - 1 May 2005 9 of 16 GS1524A Data Sheet VCC 10k 10k CLI + Figure 3-4: CLI Output Circuit CD/MUTE Figure 3-5: CD/MUTE Circuit BYPASS Figure 3-6: Bypass Circuit 28852 - 1 May 2005 10 of 16 GS1524A Data Sheet 4. Detailed Description The GS1524A is a high speed bipolar IC designed to equalize serial digital signals. The GS1524A can equalize both HD and SD serial digital signals, and will typically equalize greater than 140m of Belden 1694A cable at 1.485Gb/s and 350m at 270Mb/s. The GS1524A/ is powered from a single +3.3V power supply and consumes approximately 265mW of power. 4.1 Serial Digital Inputs The serial data signal may be connected to the input pins (SDI/SDI) in either a differential or single ended configuration. AC coupling of the inputs is recommended, as the SDI and SDI inputs are internally biased at approximately 1.8V. 4.2 Cable Equalization The input signal passes through a variable gain equalizing stage whose frequency response closely matches the inverse of the cable loss characteristic. In addition, the variation of the frequency response with control voltage imitates the variation of the inverse cable loss characteristic with cable length. The edge energy of the equalized signal is monitored by a detector circuit which produces an error signal corresponding to the difference between the desired edge energy and the actual edge energy. This error signal is integrated by both an internal and an external AGC filter capacitor providing a steady control voltage for the gain stage. As the frequency response of the gain stage is automatically varied by the application of negative feedback, the edge energy of the equalized signal is kept at a constant level which is representative of the original edge energy at the transmitter. The equalized signal is also DC restored, effectively restoring the logic threshold of the equalized signal to its correct level independent of shifts due to AC coupling. The digital output signals have a nominal voltage of 750mVpp differential, or 375mVpp single ended when terminated with 50Ω as shown in Figure 4-1. 28852 - 1 May 2005 11 of 16 GS1524A Data Sheet +187.5mV VCM = 2.925V typical SDO -187.5mV SDO 50 50 +187.5mV VCM = 2.925V typical -187.5mV Figure 4-1: Typical Output Voltage Levels 4.3 Programmable Mute Output and Cable Length Indicator For SMPTE 259M inputs, the GS1524A incorporates a programmable threshold output mute (MCLADJ) and an analog cable length indicator (CLI). MCLADJ In applications where there are multiple input channels using the GS1524A, it is advantageous to have a programmable mute output to avoid signal crosstalk. The output of the GS1524A can be muted when the input signal decreases below a certain input level. This threshold is determined using the input voltage applied to the MCLADJ pin. The MCLADJ pin may be left unconnected for applications where output muting is not required. This feature has been designed for use in applications such as routers where signal crosstalk and circuit noise cause the equalizer to output erroneous data when no input signal is present. The use of a Carrier Detect function with a fixed internal reference does not solve this problem since the signal to noise ratio on the circuit board could be significantly less than the default signal detection level set by the on chip reference. NOTE: MCLADJ is only recommended for data rates up to 360Mb/s. CLI The output voltage of the CLI pin is an approximation of the amount of cable present at the GS1524A input. With 0m of cable, 800mV input signal levels, and a data rate of 270Mb/s, the CLI output voltage is approximately 2.5V. As the cable length increases, the CLI voltage decreases providing an approximate correlation between the CLI voltage and cable length. NOTE: CLI is only recommended for data rates up to 360Mb/s. 28852 - 1 May 2005 12 of 16 GS1524A Data Sheet 4.4 Mute and Carrier Detect In addition to the programmable mute output and cable length indicator, the GS1524A includes a multi-function CD/MUTE bidirectional pin that provides the following functions: INPUT (MUTE) Applying a HIGH INPUT to the CD/MUTE pin forces the GS1524A outputs to a muted condition. The minimum voltage required to force the outputs to a muted condition is listed in the DC electrical characteristics table. In this condition the outputs will be latched to the last logic level present at the output to avoid signal crosstalk. Applying a LOW INPUT to the CD/MUTE pin will force the GS1524A outputs to remain active regardless of the length of input cable and the voltage applied to the MCLADJ pin. See the DC electrical characteristics table for voltage levels. OUTPUT (CD) When used as an OUTPUT, the CD/MUTE pin will indicate the presence of a valid input signal. When CD/MUTE is LOW, a valid input signal has been detected at the input of the device. When CD/MUTE is HIGH, the input signal is invalid. This pin will indicate loss of carrier for data rates greater than 19Mb/s. NOTE: The CD/MUTE pin is not functional in BYPASS mode. 28852 - 1 May 2005 13 of 16 GS1524A Data Sheet 5. Application Information 5.1 PCB Layout Special attention must be paid to component layout when designing serial digital interfaces for HDTV. An FR-4 dielectric can be used, however, controlled impedance transmission lines are required for PCB traces longer than approximately 1cm. Note the following PCB artwork features used to optimize performance: • • • • PCB trace width for HD rate signals is closely matched to SMT component width to minimize reflections due to change in trace impedance. The PCB ground plane is removed under the GS1524A input components to minimize parasitic capacitance. The PCB ground plane is removed under the GS1524A output components to minimize parasitic capacitance. High speed traces are curved to minimize impedance changes. 5.2 Typical Application Circuits CLI CD/MUTE VCC VCC 10n BNC 6.4n 1u 75 1u 1 2 3 4 5 6 7 8 75 37.4 1u + CLI VCC VEE SDI SDI VEE AGC+ AGC- GS1524A CD/MUTE VCC VEE SDO SDO VEE MCLADJ BYPASS 16 15 14 13 12 11 10 9 10n + 4u7 SDO + SDO 4u7 MCLADJ BYPASS NOTE: All resistors in Ohms, capacitors in Farads, and inductors in Henrys, unless otherwise noted. Figure 5-1: GS1524A Typical Application Circuit 28852 - 1 May 2005 14 of 16 GS1524A Data Sheet 6. Package & Ordering Information 6.1 Package Dimensions * CONTROLLING DIMENSION: MM 16 9 MILLIMETER Symbol MIN. A E H A1 A2 0.010" 1 b 8 L GAUGE PLANE b c D E e Detail F H L L1 Y 0˚ 5.80 0.40 1.35 0.10 1.30 0.33 0.19 9.80 3.80 9.91 3.90 1.27 6.00 0.64 1.07 0.10 8˚ 0˚ 6.20 1.27 0.228 0.016 NOM. 1.63 0.15 1.40 0.41 MAX. 1.75 0.25 1.50 0.51 0.25 10.01 4.00 MIN. 0.053 0.004 0.051 0.013 0.007 0.386 0.150 0.390 0.154 0.50 0.236 0.025 0.042 0.004 8˚ 0.244 0.050 NOM. 0.064 0.006 0.055 0.016 MAX. 0.069 0.010 0.059 0.020 0.010 0.394 0.157 INCH D A2 c A1 e A L1 Y Seating Plane See Detail F 6.2 Packaging Data Parameter Package Type Package Drawing Reference Moisture Sensitivity Level Junction to Air Thermal Resistance, θj-a (at zero airflow) Pb-free and RoHS Compliant Value SOIC 16L JEDEC MS012 2 94.1°C/W Yes 6.3 Ordering Information Part Number GS1524A GS1524ACKDE3 Package Pb-free 16-Pin SOIC Temperature Range 0°C to 70°C 28852 - 1 May 2005 15 of 16 GS1524A Data Sheet 7. Revision History Version A 0 ECR 131284 135247 Date March 2004 December 2004 Changes and/or Modifications New document. Changed to Preliminary Data Sheet. Removed references to GS9064A. Updated AC, DC and Absolute Maximum Ratings tables. Added solder reflow profiles. Added Packaging Data information. Corrected minor typing errors. Updated document status to Data Sheet. Updated all ‘Green’ references to say ‘RoHS Compliant’. Clarified naming of solder reflow profiles and re-ordered profiles to show preference for Pb-free profile. Removed ‘Proprietary and Confidential’ footer. Corrected minor typing errors. 1 136832 May 2005 CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DOCUMENT IDENTIFICATION DATA SHEET The product is in production. Gennum reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. GENNUM CORPORATION Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. GENNUM and the G logo are registered trademarks of Gennum Corporation. © Copyright 2004 Gennum Corporation. All rights reserved. Printed in Canada. www.gennum.com 28852 - 1 May 2005 16 16 of 16