GS1531 HD-LINX® II
Multi-Rate Serializer with ClockCleaner™
GS1531 Data Sheet
Key Features
Description
•
SMPTE 292M and SMPTE 259M-C compliant
scrambling and NRZ → NRZI encoding (with
bypass)
•
DVB-ASI sync word insertion and 8b/10b encoding
•
Rejection of more than 300ps jitter on the input
PCLK
The GS1531 is a multi-standard serializer with an
integrated cable driver. When used in conjunction with
the GO1555/GO1525* Voltage Controlled Oscillator, a
transmit solution can be realized for HD-SDI, SD-SDI
and DVB-ASI applications.
•
User selectable additional processing features
including:
•
CRC, ANC data checksum, and line number
calculation and insertion
•
TRS and EDH packet generation and insertion
•
illegal code remapping
•
Internal flywheel for noise immune TRS generation
•
20-bit / 10-bit CMOS parallel input data bus
•
148.5MHz / 74.25MHz / 27MHz / 13.5MHz parallel
digital input
•
Automatic standards detection and indication
•
1.8V core power supply and 3.3V charge pump
power supply
•
3.3V digital I/O supply
•
JTAG test interface
•
Available in a Pb-free package
•
small footprint (11mm x 11mm)
Applications
•
SMPTE 292M Serial Digital Interfaces
•
SMPTE 259M-C Serial Digital Interfaces
•
DVB-ASI Serial Digital Interfaces
The device features an internal PLL, which can be
configured for loop bandwidth as narrow as 100kHz.
Thus the GS1531 can tolerate in excess of 300ps jitter
on the input PCLK and still provide output jitter well
within SMPTE specification. Connect the output clocks
from Gennum’s GS4911 clock generator directly to the
GS1531’s PCLK input and configure the GS1531’s loop
bandwidth accordingly.
In addition to serializing the input, the GS1531 performs
NRZ-to-NRZI encoding and scrambling as per SMPTE
292M/259M-C when operating in SMPTE mode. When
operating in DVB-ASI mode, the device will insert K28.5
sync characters and 8b/10b encode the data prior to
serialization.
Parallel data inputs are provided for 10-bit multiplexed
or 20-bit demultiplexed formats at both HD and SD
signal rates. An appropriate parallel clock input signal is
also required.
The integrated cable driver features an output mute on
loss of parallel clock, high impedance mode, adjustable
signal swing, and automatic dual slew rate selection
depending on HD/SD operational requirements.
The GS1531 also includes a range of data processing
functions including automatic standards detection and
EDH support. The device can also insert TRS signals,
calculate and insert line numbers and CRC’s, re-map
illegal code words and insert SMPTE 352M payload
identifier packets. All processing features are optional
and may be enabled/disabled via external control pin(s)
and/or host interface programming.
*For new designs use GO1555
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www.gennum.com
GS1531 Data Sheet
Functional Block Diagram
VCO_GND
LF
VCO_VCC
LB_CONT
VCO
VCO
CP_CAP
PCLK
LOCKED
F
V
H
DETECT_TRS
DVB_ASI
IOPROC_EN/DIS
SMPTE_BYPASS
BLANK
SD/HD
20bit/10bit
Phase detector, charge pump,
VCO control & power supply
HOST Interface /
JTAG test
sd/hd
bypass
DIN[19:0]
TRS insertion,
Line number
insertion,
CRC insertion,
data blank, codere-map and
flywheel
I/O
Buffer
&
demux
dvb-asi
ClockCleaner™
SDO_EN/DIS
DVB-ASI sync
word insert &
8b/10b encode
SMPTE
352M
generation
EDH
generation
& SMPTE
scramble
SDO
P -> S
SDO
RSET
Reset
RESET_TRST
SDOUT_TDO
SDIN_TDI
SCLK_TCK
CS_TMS
JTAG/HOST
GS1531 Functional Block Diagram
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GS1531 Data Sheet
Contents
Key Features .................................................................................................................1
Applications...................................................................................................................1
Description ....................................................................................................................1
Functional Block Diagram .............................................................................................2
1. Pin Out .....................................................................................................................5
1.1 Pin Assignment ...............................................................................................5
1.2 Pin Descriptions ..............................................................................................6
2. Electrical Characteristics ........................................................................................13
2.1 Absolute Maximum Ratings ..........................................................................13
2.2 DC Electrical Characteristics ........................................................................13
2.3 AC Electrical Characteristics.........................................................................14
2.4 Solder Reflow Profiles...................................................................................16
3. Input/Output Circuits ..............................................................................................17
3.1 Host Interface Maps ......................................................................................19
3.1.1 Host Interface Map (Read Only Registers) .........................................20
3.1.2 Host Interface Map (R/W Configurable Registers) .............................21
4. Detailed Description ...............................................................................................22
4.1 Functional Overview .....................................................................................22
4.2 Parallel Data Inputs.......................................................................................22
4.2.1 Parallel Input in SMPTE Mode............................................................23
4.2.2 Parallel Input in DVB-ASI Mode..........................................................23
4.2.3 Parallel Input in Data-Through Mode ..................................................23
4.2.4 Parallel Input Clock (PCLK) ................................................................24
4.3 SMPTE Mode................................................................................................25
4.3.1 Internal Flywheel.................................................................................25
4.3.2 HVF Timing Signal Extraction .............................................................25
4.4 DVB-ASI mode..............................................................................................26
4.4.1 Control Signal Inputs ..........................................................................27
4.5 Data-Through Mode ......................................................................................28
4.6 Additional Processing Functions...................................................................28
4.6.1 Input Data Blank .................................................................................28
4.6.2 Automatic Video Standard Detection..................................................28
4.6.3 Packet Generation and Insertion ........................................................30
4.7 Parallel-To-Serial Conversion .......................................................................37
4.8 Serial Digital Data PLL..................................................................................38
4.8.1 External VCO......................................................................................38
4.8.2 Lock Detect Output .............................................................................38
4.8.3 Loop Bandwidth Adjustment ...............................................................39
4.9 Serial Digital Output ......................................................................................39
4.9.1 Output Swing ......................................................................................39
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GS1531 Data Sheet
4.9.2 Serial Digital Output Mute...................................................................40
4.10 GSPI Host Interface ....................................................................................40
4.10.1 Command Word Description.............................................................41
4.10.2 Data Read and Write Timing ............................................................42
4.10.3 Configuration and Status Registers ..................................................43
4.11 JTAG...........................................................................................................43
4.12 Device Power Up ........................................................................................45
4.13 Device Reset...............................................................................................45
5. Application Reference Design ................................................................................46
5.1 Typical Application Circuit .............................................................................46
6. References & Relevant Standards.........................................................................47
7. Package & Ordering Information............................................................................48
7.1 Package Dimensions ....................................................................................48
7.2 Packaging Data.............................................................................................49
7.3 Ordering Information .....................................................................................49
8. Revision History .....................................................................................................50
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GS1531 Data Sheet
1. Pin Out
1.1 Pin Assignment
A
B
1
2
3
4
5
6
LF
VCO_
VCC
VCO_
GND
VCO
VCO
NC
LB_
CONT
NC
NC
NC
CP_CAP CP_VDD CP_GND
C
NC
D
NC
NC
NC
NC
E
NC
NC
NC
SD/HD
F
RSV
NC
NC
G
NC
NC
NC
H
NC
NC
NC
CS_
TMS
J
NC
NC
NC
K
RSET
CD_VDD
SDO
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PD_VDD PD_GND
8
9
10
PCLK
IO_VDD
DIN18
DIN19
NC
DETECT
_TRS
IO_GND
DIN16
DIN17
NC
NC
NC
DIN14
DIN15
NC
NC
DIN12
DIN13
DVB_ASI LOCKED
7
CORE
_GND
CORE
_VDD
NC
IO_VDD
DIN10
DIN11
CORE
_GND
CORE
_VDD
NC
IO_GND
DIN8
DIN9
10bit
IOPROC
_EN/DIS
SMPTE_
BYPASS
RESET
_TRST
NC
BLANK
DIN6
DIN7
SCLK
_TCK
SDOUT
_TDO
NC
H
DIN4
DIN5
NC
SDO_EN
/DIS
SDIN
_TDI
V
IO_GND
DIN2
DIN3
SD0
CD_GND
JTAG/
HOST
F
IO_VDD
DIN0
DIN1
20bit/
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GS1531 Data Sheet
1.2 Pin Descriptions
Table 1-1: Pin Descriptions
Pin
Number
Name
Timing
Type
Description
A1
LF
Analog
Output
Control voltage to external voltage controlled oscillator. Nominally +1.25V
DC.
A2
VCO_VCC
–
Output
Power
Power supply for the external voltage controlled oscillator. Connect to pin
7 of the GO1555/GO1525*. This pin is an output.
Should be isolated from all other power supplies.
*For new designs use GO1555
A3
VCO_GND
–
Output
Power
Ground reference for the external voltage controlled oscillator. Connect to
pins 2, 4, 6, and 8 of the GO1555/GO1525*. This pin is an output.
Should be isolated from all other grounds.
*For new designs use GO1555
A4, A5
VCO, VCO
Analog
Input
Differential inputs for the external VCO reference signal. For single ended
devices such as the GO1555/GO1525*, VCO should be AC coupled to
VCO_GND.
VCO is nominally 1.485GHz.
*For new designs use GO1555
A6, B5,
B6, C1,
C4, C5,
C6, C7,
C8, D1,
D2, D3,
D4, D7,
D8, E1,
E2, E3,
E7, F2,
F3, F7,
G1, G2,
G3, G7,
H1, H2,
H3, H7,
J1, J2,
J3, J4
NC
–
–
A7
PCLK
–
Input
A8, E8, K8
IO_VDD
–
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Power
No connect.
PARALLEL DATA BUS CLOCK
Signal levels are LVCMOS/LVTTL compatible.
HD 20-bit mode
PCLK = 74.25MHz or 74.25/1.001MHz
HD 10-bit mode
PCLK = 148.5MHz or 148.5/1.001MHz
SD 20-bit mode
PCLK = 13.5MHz
SD 10-bit mode
PCLK = 27MHz
Power supply connection for digital I/O buffers. Connect to +3.3V DC
digital.
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GS1531 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
A10, A9,
B10, B9,
C10, C9,
D10, D9,
E10, E9
DIN[19:10]
Synchronous
with PCLK
Input
PARALLEL DATA BUS
Signal levels are LVCMOS/LVTTL compatible.
DIN19 is the MSB and DIN10 is the LSB.
HD 20-bit mode
SD/HD = LOW
20bit/10bit = HIGH
Luma data input in SMPTE mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data input in Data-Through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
HD 10-bit mode
SD/HD = LOW
20bit/10bit = LOW
Multiplexed Luma and Chroma data input
in SMPTE mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data input in Data-Through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
SD 20-bit mode
SD/HD = HIGH
20bit/10bit = HIGH
Luma data input in SMPTE mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data input in Data-Through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
DVB-ASI data input in DVB-ASI mode
SMPTE_BYPASS = LOW
DVB_ASI = HIGH
SD 10-bit mode
SD/HD = HIGH
20bit/10bit = LOW
Multiplexed Luma and Chroma data input
in SMPTE mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data input in data through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
DVB-ASI data input in DVB-ASI mode
SMPTE_BYPASS = LOW
DVB_ASI = HIGH
B1
CP_CAP
Analog
Input
PLL lock time constant capacitor connection.
B2
CP_VDD
–
Power
Power supply connection for the charge pump. Connect to +3.3V DC
analog.
B3
CP_GND
–
Power
Ground connection for the charge pump. Connect to analog GND.
B4
LB_CONT
Analog
Input
Control voltage to set the loop bandwidth of the integrated reclocker.
B7
DETECT_TRS
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select the timing mode of the device.
When set HIGH, the device will lock the internal flywheel to the embedded
TRS timing signals in the parallel input data.
When set LOW, the device will lock the internal flywheel to the externally
supplied H, V, and F input signals.
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GS1531 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
B8, F8, J8
IO_GND
–
Power
Ground connection for digital I/O buffers. Connect to digital GND.
C2
PD_VDD
–
Power
Power supply connection for the phase detector. Connect to +1.8V DC
analog.
C3
PD_GND
–
Power
Ground connection for the phase detector. Connect to analog GND.
D5
DVB_ASI
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
When set HIGH in conjunction with SD/HD = HIGH and SMPTE_BYPASS
= LOW, the device will be configured to operate in DVB-ASI mode.
When set LOW, the device will not support the encoding of received
DVB-ASI data.
D6
LOCKED
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
The LOCKED signal will be HIGH whenever the device has correctly
received and locked to SMPTE compliant data in SMPTE mode or
DVB-ASI compliant data in DVB-ASI mode, or when the device has
achieved lock in Data-Through mode.
It will be LOW otherwise.
E4
SD/HD
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
When set LOW, the device will be configured to transmit signal rates of
1.485Gb/s or 1.485/1.001Gb/s only.
When set HIGH, the device will be configured to transmit signal rates of
270Mb/s only.
E5, F5
CORE_GND
–
Power
Ground connection for the digital core logic. Connect to digital GND.
E6, F6
CORE_VDD
–
Power
Power supply connection for the digital core logic. Connect to +1.8V DC
digital.
F1
RSV
–
–
F4
20bit/10bit
Non
Synchronous
Input
Connect to Analog GND.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select the input data bus width in SMPTE or Data-Through
modes.
When set HIGH, the parallel input will be 20-bit demultiplexed data.
When set LOW, the parallel input will be 10-bit multiplexed data.
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GS1531 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
F10, F9,
G10, G9,
H10, H9,
J10, J9,
K10, K9
DIN[9:0]
Synchronous
with PCLK
Input
PARALLEL DATA BUS
Signal levels are LVCMOS/LVTTL compatible.
DIN9 is the MSB and DIN0 is the LSB.
HD 20-bit mode
SD/HD = LOW
20bit/10bit = HIGH
Chroma data input in SMPTE mode
SMPTE_BYPASS =HIGH
DVB_ASI = LOW
Data input in Data-Through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
HD 10-bit mode
SD/HD = LOW
20bit/10bit = LOW
High impedance in all modes.
SD 20-bit mode
SD/HD = HIGH
20bit/10bit = HIGH
Chroma data input in SMPTE mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data input in Data-Through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
High impedance in DVB-ASI mode
SMPTE_BYPASS = LOW
DVB_ASI = HIGH
SD 10-bit mode
SD/HD = HIGH
20bit/10bit = LOW
G4
IOPROC_EN/DIS
Non
Synchronous
Input
High impedance in all modes.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable I/O processing features.
When set HIGH, the following I/O processing features of the device are
enabled:
• EDH Packet Generation and Insertion (SD-only)
• SMPTE 352M Packet Generation and Insertion
• ANC Data Checksum Calculation and Insertion
• Line-based CRC Generation and Insertion (HD-only)
• Line Number Generation and Insertion (HD-only)
• TRS Generation and Insertion
• Illegal Code Remapping
To enable a subset of these features, keep IOPROC_EN/DIS HIGH and
disable the individual feature(s) in the IOPROC_DISABLE register
accessible via the host interface.
When set LOW, the I/O processing features of the device are disabled,
regardless of whether the features are enabled in the IOPROC_DISABLE
register.
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GS1531 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
G5
SMPTE_BYPASS
Non
Synchronous
Input
Description
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
When set HIGH in conjunction with DVB_ASI = LOW, the device will be
configured to operate in SMPTE mode. All I/O processing features may be
enabled in this mode.
When set LOW, the device will not support the scrambling or encoding of
received SMPTE data. No I/O processing features will be available.
G6
RESET_TRST
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to reset the internal operating conditions to default settings and to
reset the JTAG test sequence.
Host Mode (JTAG/HOST = LOW)
When asserted LOW, all functional blocks will be set to default conditions
and all input and output signals become high impedance, including the
serial digital outputs SDO and SDO.
Must be set HIGH for normal device operation.
JTAG Test Mode (JTAG/HOST = HIGH)
When asserted LOW, all functional blocks will be set to default and the
JTAG test sequence will be held in reset.
When set HIGH, normal operation of the JTAG test sequence resumes.
G8
BLANK
Synchronous
with PCLK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable input data blanking.
When set LOW, the luma and chroma input data is set to the appropriate
blanking levels. Horizontal and vertical ancillary spaces will also be set to
blanking levels.
When set HIGH, the luma and chroma input data pass through the device
unaltered.
H4
CS_TMS
Synchronous
with
SCLK_TCK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Chip Select / Test Mode Select
Host Mode (JTAG/HOST = LOW)
CS_TMS operates as the host interface chip select, CS, and is active
LOW.
JTAG Test Mode (JTAG/HOST = HIGH)
CS_TMS operates as the JTAG test mode select, TMS, and is active
HIGH.
NOTE: If the host interface is not being used, tie this pin HIGH.
H5
SCLK_TCK
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Clock / Test Clock.
Host Mode (JTAG/HOST = LOW)
SCLK_TCK operates as the host interface burst clock, SCLK. Command
and data read/write words are clocked into the device synchronously with
this clock.
JTAG Test Mode (JTAG/HOST = HIGH)
SCLK_TCK operates as the JTAG test clock, TCK.
NOTE: If the host interface is not being used, tie this pin HIGH.
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GS1531 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
H6
SDOUT_TDO
Synchronous
with
SCLK_TCK
Output
CONTROL SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Output / Test Data Output
Host Mode (JTAG/HOST = LOW)
SDOUT_TDO operates as the host interface serial output, SDOUT, used
to read status and configuration information from the internal registers of
the device.
JTAG Test Mode (JTAG/HOST = HIGH)
SDOUT_TDO operates as the JTAG test data output, TDO.
H8
H
Synchronous
with PCLK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video line containing active video data
when DETECT_TRS is set LOW. The device will set the H bit in all
outgoing TRS signals for the entire period that the H input signal is HIGH
(IOPROC_EN/DIS must also be HIGH).
H signal timing is configurable via the H_CONFIG bit of the
IOPROC_DISABLE register, accessible via the host interface.
Active Line Blanking (H_CONFIG = 0h)
The H signal should be set HIGH for the entire horizontal blanking period,
including the EAV and SAV TRS words, and LOW otherwise. This is the
default setting.
TRS Based Blanking (H_CONFIG = 1h)
The H signal should be set HIGH for the entire horizontal blanking period
as indicated by the H bit in the received TRS ID words, and LOW
otherwise.
J5
SDO_EN/DIS
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable the serial digital output stage.
When set LOW, the serial digital output signals SDO and SDO are
disabled and become high impedance.
When set HIGH, the serial digital output signals SDO and SDO are
enabled.
J6
SDIN_TDI
Synchronous
with
SCLK_TCK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data In / Test Data Input
Host Mode (JTAG/HOST = LOW)
SDIN_TDI operates as the host interface serial input, SDIN, used to write
address and configuration information to the internal registers of the
device.
JTAG Test Mode (JTAG/HOST = HIGH)
SDIN_TDI operates as the JTAG test data input, TDI.
NOTE: If the host interface is not being used, tie this pin HIGH.
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GS1531 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
J7
V
Synchronous
with PCLK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video field / frame that is used for
vertical blanking when DETECT_TRS is set LOW. The device will set the
V bit in all outgoing TRS signals for the entire period that the V input signal
is HIGH (IOPROC_EN/DIS must also be HIGH).
The V signal should be set HIGH for the entire vertical blanking period and
should be set LOW for all lines outside of the vertical blanking interval.
The V signal is ignored when DETECT_TRS = HIGH.
K1
RSET
Analog
Input
Used to set the serial digital output signal amplitude. Connect to CD_VDD
through 281Ω +/- 1% for 800mVp-p single-ended output swing.
K2
CD_VDD
–
Power
Power supply connection for the serial digital cable driver. Connect to
+1.8V DC analog.
K3, K4
SDO, SDO
Analog
Output
Serial digital output signal operating at 1.485Gb/s, 1.485/1.001Gb/s, or
270Mb/s.
The slew rate of these outputs is automatically controlled to meet SMPTE
292M and 259M requirements according to the setting of the SD/HD pin.
K5
CD_GND
–
Power
Ground connection for the serial digital cable driver. Connect to analog
GND.
K6
JTAG/HOST
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select JTAG Test Mode or Host Interface Mode.
When set HIGH, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are
configured for JTAG boundary scan testing.
When set LOW, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are
configured as GSPI pins for normal host interface operation.
K7
F
Synchronous
with PCLK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the ODD / EVEN field of the video signal when
DETECT_TRS is set LOW. The device will set the F bit in all outgoing TRS
signals for the entire period that the F input signal is HIGH
(IOPROC_EN/DIS must also be HIGH).
The F signal should be set HIGH for the entire period of field 2 and should
be set LOW for all lines in field 1 and for all lines in progressive scan
systems.
The F signal is ignored when DETECT_TRS = HIGH.
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GS1531 Data Sheet
2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Parameter
Value/Units
Supply Voltage Core
-0.3V to +2.1V
Supply Voltage I/O
-0.3V to +4.6V
Input Voltage Range (any input)
-2.0V to + 5.25V
Ambient Operating Temperature
-20°C < TA < 85°C
Storage Temperature
-40°C < TSTG < 125°C
ESD Protection On All Pins (see Note 1)
1kV
NOTES:
1. HBM, per JESDA-114B.
2.2 DC Electrical Characteristics
Table 2-1: DC Electrical Characteristics
TA = 0°C to 70°C, unless otherwise specified.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Test
Level
Notes
Operation Temperature Range
TA
–
0
–
70
°C
3
1
Digital Core Supply Voltage
CORE_VDD
–
1.71
1.8
1.89
V
3
1
Digital I/O Supply Voltage
IO_VDD
–
3.13
3.3
3.47
V
3
1
Charge Pump Supply Voltage
CP_VDD
–
3.13
3.3
3.47
V
3
1
Phase Detector Supply Voltage
PD_VDD
–
1.71
1.8
1.89
V
3
1
Input Buffer Supply Voltage
BUFF_VDD
–
1.71
1.8
1.89
V
3
1
Cable Driver Supply Voltage
CD_VDD
–
1.71
1.8
1.89
V
3
1
External VCO Supply Voltage
Output
VCO_VCC
–
2.25
–
2.75
V
1
–
+1.8V Supply Current
I1V8
SDO Enabled
–
–
245
mA
3
3
+3.3V Supply Current
I3V3
–
–
–
45
mA
3
4
Total Device Power
PD
SDO Enabled
–
–
590
mW
3
–
System
30573 - 7
February 2008
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GS1531 Data Sheet
Table 2-1: DC Electrical Characteristics (Continued)
TA = 0°C to 70°C, unless otherwise specified.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Test
Level
Notes
Input Logic LOW
VIL
–
–
–
0.8
V
4
–
Input Logic HIGH
VIH
–
2.1
–
–
V
4
–
Output Logic LOW
VOL
+8mA
–
0.2
0.4
V
4
–
Output Logic HIGH
VOH
-8mA
IO_VDD - 0.4
–
–
V
4
–
VRSET
RSET=281Ω
0.54
0.6
0.66
V
1
2
VCMOUT
75Ω load,
RSET=281Ω,
SD and HD
0.8
1.0
1.2
V
1
–
Digital I/O
Input
RSET Voltage
Output
Output Common Mode Voltage
TEST LEVELS
NOTES
1. Production test at room temperature and nominal supply
voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply
voltage with guardbands for supply and temperature ranges
using correlated test.
3. Production test at room temperature and nominal supply
voltage.
4. QA sample test.
5. Calculated result based on Level 1, 2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of
similar product.
9. Indirect test.
1.
2.
3.
4.
All DC and AC electrical parameters within specification.
Set by the value of the RSET resistor.
Sum of all 1.8V supplies.
Sum of all 3.3V supplies.
2.3 AC Electrical Characteristics
Table 2-2: AC Electrical Characteristics
TA = 0°C to 70°C, unless otherwise shown
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Test
Level
Notes
–
10-bit SD
–
21
–
PCLK
8
–
–
–
20-bit HD
–
19
–
PCLK
8
–
DVB-ASI
–
11
–
PCLK
8
–
treset
–
1
–
–
ms
8
1
System
Device Latency
Reset Pulse Width
30573 - 7
February 2008
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GS1531 Data Sheet
Table 2-2: AC Electrical Characteristics (Continued)
TA = 0°C to 70°C, unless otherwise shown
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Test
Level
Notes
Parallel Clock Frequency
fPCLK
–
13.5
–
148.5
MHz
4
–
Parallel Clock Duty Cycle
DCPCLK
–
40
–
60
%
6
–
Input Data Setup Time
tsu
–
2.0
–
–
ns
5
–
Input Data Hold Time
tih
–
1.5
–
–
ns
5
–
DRSDO
–
–
1.485
–
Gb/s
1
–
–
–
1.485/1.001
–
Gb/s
9
–
Parallel Input
Serial Digital Output
Serial Output Data Rate
–
–
270
–
Mb/s
1
–
650
800
950
mVp-p
1
–
HD signal
–
–
260
ps
1
–
trSDO
SD signal
400
550
1500
ps
1
–
Serial Output Fall Time
20% ~ 80%
tfSDO
HD signal
–
–
260
ps
1
–
tfSDO
SD signal
400
550
1500
ps
1
–
Serial Output Intrinsic Jitter
tIJ
Pseudorandom and
pathological HD signal
–
90
125
ps
5
–
tIJ
Pseudorandom and
pathological SD signal
–
270
350
ps
5
–
–
6.6
MHz
8
–
Serial Output Swing
ΔVSDD
RSET = 281Ω
75Ω load
Serial Output Rise Time
20% ~ 80%
trSDO
GSPI
GSPI Input Clock Frequency
fSCLK
–
–
GSPI Input Clock Duty Cycle
DCSCLK
–
40
–
60
%
8
–
GSPI Input Data Setup Time
–
–
0
–
–
ns
8
–
GSPI Input Data Hold Time
–
–
1.43
–
–
ns
8
–
GSPI Output Data Hold Time
–
–
2.1
–
–
ns
8
–
GSPI Output Data Delay
Time
–
–
–
–
7.27
ns
8
–
TEST LEVELS
NOTES
1. Production test at room temperature and nominal supply voltage
with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage
with guardbands for supply and temperature ranges using
correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1, 2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of
similar product.
9. Indirect test.
1. See Device Power Up on page 45, Figure 4-12.
30573 - 7
February 2008
15 of 50
GS1531 Data Sheet
2.4 Solder Reflow Profiles
The GS1531 is available in a Pb or Pb-free package. It is recommended that the
Pb package be soldered with Pb paste using the Standard Eutectic profile shown
in Figure 2-1, and the Pb-free package be soldered with Pb-free paste using the
reflow profile shown in Figure 2-2.
NOTE: It is possible to solder a Pb-free package with Pb paste using a Standard
Eutectic profile with a reflow temperature maintained at 245oC – 250oC.
60-150 sec.
Temperature
10-20 sec.
230˚C
220˚C
3˚C/sec max
183˚C
6˚C/sec max
150˚C
100˚C
25˚C
Time
120 sec. max
6 min. max
Figure 2-1: Standard Eutectic Solder Reflow Profile (Pb package, Pb paste)
Temperature
60-150 sec.
20-40 sec.
260˚C
250˚C
3˚C/sec max
217˚C
6˚C/sec max
200˚C
150˚C
25˚C
Time
60-180 sec. max
8 min. max
Figure 2-2: Maximum Pb-free Solder Reflow Profile (Pb-free package, Pb-free
paste)
30573 - 7
February 2008
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GS1531 Data Sheet
3. Input/Output Circuits
All resistors in ohms, all capacitors in farads, unless otherwise shown.
SDO
SDO
Figure 3-1: Serial Digital Output
LF
CP_CAP
300
Figure 3-2: VCO Control Output & PLL Lock Time Capacitor
VDD
42K
63K
PCLK
Figure 3-3: PCLK Input
30573 - 7
February 2008
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GS1531 Data Sheet
VCO
VDD
25
1.5K
5K
25
VCO
Figure 3-4: VCO Input
LB_CONT
865mV
7.2K
Figure 3-5: PLL Loop Bandwidth Control
30573 - 7
February 2008
18 of 50
IOPROC_DISABLE
EDH_FLAG
VIDEO_STANDARD
VIDEO_FORMAT_B
VIDEO_FORMAT_A
FF_LINE_END_F1
FF_LINE_START_F1
FF_LINE_END_F0
FF_LINE_START_F0
AP_LINE_END_F1
AP_LINE_START_F1
AP_LINE_END_F0
AP_LINE_START_F0
RASTER_STRUCTURE4
RASTER_STRUCTURE3
RASTER_STRUCTURE2
RASTER_STRUCTURE1
REGISTER NAME
LINE_352M_f2
LINE_352M_f1
03h
02h
01h
00h
ADDRESS
1Ch
1Bh
1Ah
19h
18h
17h
16h
15h
14h
13h
12h
11h
10h
0Fh
0Eh
0Dh
0Ch
0Bh
0Ah
09h
08h
07h
06h
05h
04h
Not Used
Not Used
Not Used
VF4-b7
VF2-b7
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
15
Not Used
Not Used
Not Used
ANC-IDA
VDS-b3
VF4-b5
VF2-b5
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
13
Not Used
Not Used
30573 - 7
Not Used
ANC-UES
VDS-b4
VF4-b6
VF2-b6
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
14
Not Used
Not Used
3.1 Host Interface Maps
Not Used
ANC-EDA
VDS-b1
VF4-b3
VF2-b3
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
b11
b11
11
Not Used
Not Used
February 2008
Not Used
ANC-IDH
VDS-b2
VF4-b4
VF2-b4
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
12
Not Used
Not Used
Not Used
ANC-EDH
VDS-b0
VF4-b2
VF2-b2
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
b10
b10
b10
b10
10
b10
b10
Not Used
FF-UES
INT_PROG
VF4-b1
VF2-b1
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
9
b9
b9
H_CONFIG
FF-IDA
STD_
LOCK
VF4-b0
VF2-b0
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
8
b8
b8
Not Used
FF-IDH
NOT USED
VF3-b7
VF1-b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
7
b7
b7
352M_INS
FF-EDA
NOT USED
VF3-b6
VF1-b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
6
b6
b6
ILLEGAL_RE
MAP
FF-EDH
NOT USED
VF3-b5
VF1-b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
5
b5
b5
4
EDH_CRC_IN
S
AP-UES
NOT USED
VF3-b4
VF1-b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
3
ANC_
CSUM_INS
AP-IDA
NOT USED
VF3-b3
VF1-b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
CRC_INS
AP-IDH
NOT USED
VF3-b2
VF1-b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
2
b2
b2
TRS_INS
AP-EDH
NOT USED
VF3-b0
VF1-b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
0
b0
b0
19 of 50
LNUM_ INS
AP-EDA
NOT USED
VF3-b1
VF1-b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
1
b1
b1
GS1531 Data Sheet
VIDEO_STANDARD
RASTER_STRUCTURE4
RASTER_STRUCTURE3
RASTER_STRUCTURE2
RASTER_STRUCTURE1
REGISTER NAME
03h
02h
01h
00h
ADDRESS
1Ch
1Bh
1Ah
19h
18h
17h
16h
15h
14h
13h
12h
11h
10h
0Fh
0Eh
0Dh
0Ch
0Bh
0Ah
09h
08h
07h
06h
05h
04h
15
VDS-b3
13
30573 - 7
VDS-b4
14
VDS-b1
b11
b11
11
February 2008
VDS-b2
12
VDS-b0
b10
b10
b10
b10
10
3.1.1 Host Interface Map (Read Only Registers)
INT_PROG
b9
b9
b9
b9
9
STD_
LOCK
b8
b8
b8
b8
8
b7
b7
b7
b7
7
b6
b6
b6
b6
6
b5
b5
b5
b5
5
b4
b4
b4
b4
4
b3
b3
b3
b3
3
b2
b2
b2
b2
2
b1
b1
b1
b1
1
20 of 50
b0
b0
b0
b0
0
GS1531 Data Sheet
IOPROC_DISABLE
EDH_FLAG
VIDEO_FORMAT_B
VIDEO_FORMAT_A
FF_LINE_END_F1
FF_LINE_START_F1
FF_LINE_END_F0
FF_LINE_START_F0
AP_LINE_END_F1
AP_LINE_START_F1
AP_LINE_END_F0
AP_LINE_START_F0
REGISTER NAME
LINE_352M_f2
LINE_352M_f1
ADDRESS
1Ch
1Bh
1Ah
19h
18h
17h
16h
15h
14h
13h
12h
11h
10h
0Fh
0Eh
0Dh
0Ch
0Bh
0Ah
09h
08h
07h
06h
05h
04h
03h
02h
01h
00h
VF4-b7
VF2-b7
15
ANC-IDA
VF4-b5
VF2-b5
13
30573 - 7
ANC-UES
VF4-b6
VF2-b6
14
ANC-EDA
VF4-b3
VF2-b3
11
February 2008
ANC-IDH
VF4-b4
VF2-b4
12
ANC-EDH
VF4-b2
VF2-b2
10
b10
b10
FF-UES
VF4-b1
VF2-b1
b9
b9
b9
b9
b9
b9
b9
b9
9
b9
b9
3.1.2 Host Interface Map (R/W Configurable Registers)
H_CONFIG
FF-IDA
VF4-b0
VF2-b0
b8
b8
b8
b8
b8
b8
b8
b8
8
b8
b8
FF-IDH
VF3-b7
VF1-b7
b7
b7
b7
b7
b7
b7
b7
b7
7
b7
b7
352M_INS
FF-EDA
VF3-b6
VF1-b6
b6
b6
b6
b6
b6
b6
b6
b6
6
b6
b6
ILLEGAL_RE
MAP
FF-EDH
VF3-b5
VF1-b5
b5
b5
b5
b5
b5
b5
b5
b5
5
b5
b5
EDH_CRC_IN
S
AP-UES
VF3-b4
VF1-b4
b4
b4
b4
b4
b4
b4
b4
b4
4
b4
b4
ANC_
CSUM_INS
AP-IDA
VF3-b3
VF1-b3
b3
b3
b3
b3
b3
b3
b3
b3
3
b3
b3
CRC_INS
AP-IDH
VF3-b2
VF1-b2
b2
b2
b2
b2
b2
b2
b2
b2
2
b2
b2
TRS_INS
AP-EDH
VF3-b0
VF1-b0
b0
b0
b0
b0
b0
b0
b0
b0
0
b0
b0
21 of 50
LNUM_ INS
AP-EDA
VF3-b1
VF1-b1
b1
b1
b1
b1
b1
b1
b1
b1
1
b1
b1
GS1531 Data Sheet
GS1531 Data Sheet
4. Detailed Description
4.1 Functional Overview
The GS1531 is a multi-rate serializer with an integrated cable driver. When used in
conjunction with the external GO1555/GO1525* Voltage Controlled Oscillator, a
transmit solution at 1.485Gb/s, 1.485/1.001Gb/s or 270Mb/s is realized.
The device has three different modes of operation which must be set through
external device pins.
When SMPTE mode is enabled, the device will accept 10-bit multiplexed or 20-bit
demultiplexed SMPTE compliant data at both HD and SD signal rates. The
device’s additional processing features are also enabled in this mode.
In DVB-ASI mode, the GS1531 will accept an 8-bit parallel DVB-ASI compliant
transport stream on its upper input bus. The serial output data stream will be
8b/10b encoded and stuffed.
The GS1531’s third mode allows for the serializing of data not conforming to
SMPTE or DVB-ASI streams.
The provided serial digital outputs feature a high impedance mode, output mute on
loss of parallel clock and adjustable signal swing. The output slew rate is
automatically controlled by the SD/HD setting.
In the digital signal processing core, several data processing functions are
implemented including SMPTE 352M and EDH data packet generation and
insertion, and automatic video standards detection. These features are all enabled
by default, but may be individually disabled via internal registers accessible
through the GSPI host interface.
Finally, the GS1531 contains a JTAG interface for boundary scan test
implementations.
*For new designs use GO1555
4.2 Parallel Data Inputs
Data inputs enter the device on the rising edge of PCLK as shown in Figure 4-1.
The input data format is defined by the setting of the external SD/HD,
SMPTE_BYPASS and DVB_ASI pins and may be presented in 10-bit or 20-bit
format. The input data bus width is controlled independently from the internal data
bus width by the 20bit/10bit input pin.
30573 - 7
February 2008
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GS1531 Data Sheet
PCLK
DIN[19:0]
DATA
Control signal
input
tSU
tIH
Figure 4-1: PCLK to Data Timing
4.2.1 Parallel Input in SMPTE Mode
When the device is operating in SMPTE mode, see SMPTE Mode on page 25, both
SD and HD data may be presented to the input bus in either multiplexed or
demultiplexed form depending on the setting of the 20bit/10bit input pin.
In 20-bit mode, (20bit/10bit = HIGH), the input data format should be word aligned,
demultiplexed luma and chroma data. Luma words should be presented to
DIN[19:10] while chroma words should occupy DIN[9:0].
In 10-bit mode, (20bit/10bit = LOW), the input data format should be word aligned,
multiplexed luma and chroma data. The data should be presented to DIN[19:10].
DIN[9:0] will be high impedance in this mode.
4.2.2 Parallel Input in DVB-ASI Mode
When operating in DVB-ASI mode, see DVB-ASI mode on page 26, the GS1531
requires the input data bus to be configured for 10-bit operation (20bit/10bit =
LOW).
The device accepts 8-bit data words on DIN[17:10] such that DIN17 = HIN is the
most significant bit of the encoded transport stream data and DIN10 = AIN is the
least significant bit.
In addition, DIN19 and DIN18 are configured as the DVB-ASI control signals
INSSYNCIN and KIN respectively. See DVB-ASI mode on page 26 for a
description of these DVB-ASI specific input signals.
The pins DIN[9:0] are high impedance when the GS1531 is operating in DVB-ASI
mode.
4.2.3 Parallel Input in Data-Through Mode
When operating in Data-Through mode, see Data-Through Mode on page 28, the
GS1531 passes data presented to the parallel input bus to the serial output without
performing any encoding or scrambling.
The input data bus width accepted by the device in this mode is controlled by the
setting of the 20bit/10bit pin.
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February 2008
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GS1531 Data Sheet
4.2.4 Parallel Input Clock (PCLK)
The frequency of the PCLK input signal required by the GS1531 is determined by
the input data format. Table 4-1 below lists the possible input signal formats and
their corresponding parallel clock rates.
NOTE: DVB-ASI input requires a 10-bit wide input data bus (20bit/10bit = LOW).
Table 4-1: Parallel Data Input Format
Control Signals
Input Data Format
DIN
[19:10]
DIN [9:0]
PCLK
20bit/
10bit
SD/
HD
SMPTE_BYPASS
DVB_ASI
20bit DEMULTIPLEXED SD
LUMA
CHROMA
13.5MHz
HIGH
HIGH
HIGH
LOW
10bit MULTIPLEXED SD
LUMA /
CHROMA
HIGH
IMPEDANCE
27MHz
LOW
HIGH
HIGH
LOW
20bit DEMULTIPLEXED HD
LUMA
CHROMA
74.25 or
HIGH
LOW
HIGH
LOW
LOW
LOW
HIGH
LOW
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
SMPTE MODE
74.25/
1.001MHz
10bit MULTIPLEXED HD
LUMA /
CHROMA
HIGH
IMPEDANCE
148.5 or
DVB-ASI
HIGH
IMPEDANCE
27MHz
DATA
20bit DEMULTIPLEXED SD
DATA
DATA
13.5MHz
HIGH
HIGH
LOW
LOW
10bit MULTIPLEXED SD
DATA
HIGH
IMPEDANCE
27MHz
LOW
HIGH
LOW
LOW
20bit DEMULTIPLEXED HD
DATA
DATA
74.25 or
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
148.5/
1.001MHz
DVB-ASI MODE
10bit DVB-ASI
DATA-THROUGH MODE
74.25/
1.001MHz
10bit MULTIPLEXED HD
DATA
HIGH
IMPEDANCE
30573 - 7
148.5 or
148.5/
1.001MHz
February 2008
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GS1531 Data Sheet
4.3 SMPTE Mode
The GS1531 is said to be in SMPTE mode when the SMPTE_BYPASS pin is set
HIGH and the DVB_ASI pin is set LOW.
In this mode, the parallel data will be scrambled according to SMPTE 259M or
292M, and NRZ-to-NRZI encoded prior to serialization.
4.3.1 Internal Flywheel
The GS1531 has an internal flywheel which is used in the generation of internal /
external timing signals, and in automatic video standards detection. It is
operational in SMPTE mode only.
The flywheel consists of a number of counters and comparators operating at video
pixel and video line rates. These counters maintain information about the total line
length, active line length, total number of lines per field / frame and total active lines
per field / frame for the received video standard.
When DETECT_TRS is LOW, the flywheel will be locked to the externally supplied
H, V, and F timing signals.
When DETECT_TRS is HIGH, the flywheel will be locked to the embedded TRS
signals in the parallel input data. Both 8-bit and 10-bit TRS code words will be
identified by the device.
The flywheel 'learns' the video standard by timing the horizontal and vertical
reference information supplied a the H, V, and F input pins, or contained in the TRS
ID words of the received video data. Full synchronization of the flywheel to the
received video standard therefore requires one complete video frame.
Once synchronization has been achieved, the flywheel will continue to monitor the
received TRS timing or the supplied H, V, and F timing information to maintain
synchronization.
4.3.2 HVF Timing Signal Extraction
As discussed above, the GS1531's internal flywheel may be locked to externally
provided H, V, and F signals when DETECT_TRS is set LOW.
The H signal timing should also be configured via the H_CONFIG bit of the internal
IOPROC_DISABLE register as either active line based blanking or TRS based
blanking, see Packet Generation and Insertion on page 30.
Active line based blanking is enabled when the H_CONFIG bit is set LOW. In this
mode, the H input should be HIGH for the entire horizontal blanking period,
including the EAV and SAV TRS words. This is the default H timing assumed by
the device.
When H_CONFIG is set HIGH, TRS based blanking is enabled. In this case, the H
input should be set HIGH for the entire horizontal blanking period as indicated by
the H bit in the associated TRS words.
The timing of these signals is shown in Figure 4-2.
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GS1531 Data Sheet
PCLK
LUMA DATA OUT
3FF
000
000
XYZ
(eav)
3FF
000
000
XYZ
(sav)
CHROMA DATA OUT
3FF
000
000
XYZ
(eav)
3FF
000
000
XYZ
(sav)
H
V
F
H:V:F TIMING - HD 20-BIT INPUT MODE
PCLK
MULTIPLEXED
Y/Cr/Cb DATA OUT
3FF
3FF
000
000
000
XYZ
(eav)
XYZ
(eav)
000
XYZ
(sav)
XYZ
(sav)
000
H
V
F
H:V:F TIMING AT EAV - HD 10-BIT INPUT MODE
PCLK
MULTIPLEXED
Y/Cr/Cb DATA OUT
3FF
3FF
000
000
000
H
V
F
H;V:F TIMING AT SAV - HD 10-BIT INPUT MODE
PCLK
CHROMA DATA OUT
3FF
000
3FF
000
LUMA DATA OUT
000
XYZ
(eav)
000
XYZ
(SAV)
H
V
H SIGNAL TIMING:
H_CONFIG = LOW
F
H_CONFIG = HIGH
H:V:F TIMING - SD 20-BIT INPUT MODE
PCLK
MULTIPLEXED
Y/Cr/Cb DATA OUT
3FF
000
000
XYZ
(eav)
3FF
000
000
XYZ
(sav)
H
V
F
H:V:F TIMING - SD 10-BIT INPUT MODE
Figure 4-2: H, V, F Timing
4.4 DVB-ASI mode
To operate the GS1531 in DVB-ASI mode, set the SMPTE_BYPASS and
20bit/10bit pins LOW, and the DVB_ASI and SD/HD pins HIGH.
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GS1531 Data Sheet
4.4.1 Control Signal Inputs
In DVB-ASI mode, the DIN19 and DIN18 pins will be configured as DVB-ASI
control signals INSSYNCIN and KIN respectively.
When INSSYNCIN is set HIGH, the device will insert K28.5 sync characters into
the data stream. This function is used to assist system implementations where the
GS1531 may be preceded by an external data FIFO. Parallel DVB-ASI data may
be clocked into the FIFO at some rate less than 27MHz. The INSSYNCIN input
may then be connected to the FIFO empty signal, thus providing a means of
padding up the data transmission rate to 27MHz. See Figure 4-3.
NOTE: 8b/10b encoding will take place after K28.5 sync character insertion.
KIN should be set HIGH whenever the parallel data input is to be interpreted as any
special character defined by the DVB-ASI standard (including the K28.5 sync
character). This pin should be set LOW when the input is to be interpreted as data.
NOTE: When operating in DVB-ASI mode, DIN[9:0] become high impedance.
AIN ~ HIN
SDO
TS
8
8
FIFO
GS1531
KIN
KIN
WRITE_CLK
300ps pclk jitter in
Description section on page 1. Corrected IO_PROG pin setting typing error
in Section 4.6.2.1. Corrected VIDEO_FORMAT register labels in description
of bit 6 (352M_INS) in Table 4-5.
6
143759
42774
February 2007
Recommended GO1555 VCO for new designs. Updated Section 5.1
Typical Application Circuit. Added Section 4.8.3 Loop Bandwidth
Adjustment.
7
148907
–
February 2008
Changed register RASTER_STRUCTURE2 from 12 bits to 13 bits in Table
4-3: Host Interface Description for Raster Structure Registers. Changes
related to DVB-ASI mode in Pin Descriptions, Section 4.2.2, Section 4.2.4,
Table 4-1 & Section 4.4. Changed SMPTE 352 Lines from 13 to 10 in
Table 4-4.
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
DATA SHEET
The product is in production. Gennum reserves the right to make
changes at any time to improve reliability, function or design, in order to
provide the best product possible.
GENNUM CORPORATION
Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
GENNUM JAPAN CORPORATION
Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan
Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505
GENNUM UK LIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the
circuits or devices described herein. The sale of the circuit or device described herein does not imply any
patent license, and Gennum makes no representation that the circuit or device is free from patent infringement.
GENNUM and the G logo are registered trademarks of Gennum Corporation.
© Copyright 2004 Gennum Corporation. All rights reserved. Printed in Canada.
www.gennum.com
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