GS1574A HD-LINX® II Adaptive Cable Equalizer
Features
• • • • • • • • • • • • • SMPTE 292M and SMPTE 259M compliant Automatic cable equalization Multi-standard operation from 143Mb/s to 1.485Gb/s Supports DVB-ASI at 270Mb/s Small footprint (4mm x 4mm) Pb-free and RoHS compliant Manual bypass (useful for low data rates with slow rise/fall times) Performance optimized for 270Mb/s and 1.485Gb/s Typical equalized length of Belden 1694A cable: 200m at 1.485Gb/s, 350m at 270Mb/s 50Ω differential output (with internal 50Ω pull-ups) Manual output mute or programmable mute based on max cable length adjust Single 3.3V power supply operation Operating temperature range: 0°C to +70°C
Description
The GS1574A is a second-generation high-speed BiCMOS integrated circuit designed to equalize and restore signals received over 75Ω co-axial cable. The GS1574A is designed to support SMPTE 292M and SMPTE 259M, and is optimized for performance at 270Mb/s and 1.485Gb/s. The GS1574A features DC restoration to compensate for the DC content of SMPTE pathological test patterns. A voltage programmable mute threshold (MCLADJ) is included to allow muting of the GS1574A output when an approximate selected cable length is reached for SMPTE 259M signals. This feature allows the GS1574A to distinguish between low amplitude SD-SDI signals and noise at the input of the device. The serial digital outputs of the GS1574A may be forced to a mute state by applying a voltage to the MUTE pin. Power consumption is typically 215mW using a 3.3V power supply. The GS1574A is lead-free, and the encapsulation compound does not contain halogenated flame retardant. This component and all homogeneous subcomponents are RoHS compliant.
Application
• SMPTE 292M and SMPTE 259M Coaxial Cable Serial Digital Interfaces
MCLADJ
CABLE LENGTH ADJUSTOR CARRIER DETECT MUTE
CD MUTE BYPASS
SDI SDI
EQUALIZER
DC RESTORE
OUTPUT
SDO SDO
AGC
Figure A: GS1574A Functional Block Diagram
GS1574A HD-LINX® II Adaptive Cable Equalizer Data Sheet 33416 - 10 August 2011
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Revision History
Version
10
ECR
156775
PCN
–
Date
August 2011
Changes and/or Modifications
Added the tape and reel part number to Table 9-1: GS1574A Ordering Information Updated to latest Gennum template. Added maximum power consumption to DC Electrical Characteristics. Modified 200m cable length in front page Features section and Detailed Description. Added 200m output cable length jitter data at 1.485Gb/s in AC Electrical Characteristics. Corrected pad standoff height and tolerances for pad width & package dimension. Corrected pad shape. Convert to Data Sheet. Corrected typing errors. Corrected process to BiCMOS. Amended notes on use of MCLADJ above 360 Mb/s. Rephrased RoHS compliance statement. Corrected description of connection for AGC and AGC pins in the Pin Description table. Clarified solder reflow profile descriptions. Corrected minor typing errors.
9 8 7
153754 144435 141758
– – 40438
September 2009 March 2007 August 2006
6
141576
40438
August 2006
5
139634
38695
March 2006
4 3 2 1
137744 137321 137167 136885
– – – –
September 2005 June 2005 June 2005 May 2005
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Contents
Features.................................................................................................................................................................1 Application...........................................................................................................................................................1 Description...........................................................................................................................................................1 Revision History .................................................................................................................................................2 1. Pin Out...............................................................................................................................................................4 1.1 GS1574A Pin Assignment ..............................................................................................................4 1.2 GS1574A Pin Descriptions .............................................................................................................4 2. Electrical Characteristics ............................................................................................................................6 2.1 Absolute Maximum Ratings ..........................................................................................................6 2.2 DC Electrical Characteristics ........................................................................................................6 2.3 AC Electrical Characteristics ........................................................................................................7 3. Solder Reflow Profiles..................................................................................................................................9 4. Test Circuit.................................................................................................................................................... 10 5. Input / Output Circuits ............................................................................................................................. 11 6. Detailed Description.................................................................................................................................. 13 6.1 Serial Digital Inputs ...................................................................................................................... 13 6.2 Cable Equalization ........................................................................................................................ 13 6.3 Programmable Mute Output ...................................................................................................... 14 6.4 Mute and Carrier Detect .............................................................................................................. 14 7. Application Information .......................................................................................................................... 15 7.1 PCB Layout ....................................................................................................................................... 15 7.2 Typical Application Circuit ........................................................................................................ 15 8. Package and Ordering Information...................................................................................................... 16 8.1 Package Dimensions ..................................................................................................................... 16 8.2 Recommended PCB Footprint ................................................................................................... 17 8.3 Packaging Data ............................................................................................................................... 17 8.4 Ordering Information ................................................................................................................... 18
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1. Pin Out
1.1 GS1574A Pin Assignment
VCC_A MUTE VCC_D 13 12 VEE_D 11 CD 15
16 VEE_A 1
14
SDI
2
GS1574A (top view)
SDI 3 10
SDO
SDO
VEE_A
4 5 AGC 6 AGC 7 BYPASS 8 MCLADJ
9
VEE_D
Center Pad (bottom of package, internally bonded to VEE_A)
Figure 1-1: 16-Pin QFN
1.2 GS1574A Pin Descriptions
Table 1-1: GS1574A Pin Descriptions
Pin Number
1, 4
Name
VEE_A
Timing
Analog
Type
Power
Description
Most negative power supply for analog circuitry. Connect to GND.
2, 3 5, 6
SDI, SDI AGC, AGC
Analog Analog
Input –
Serial digital differential input. External AGC capacitor. Connect pin 5 and pin 6 together as shown in the Typical Application Circuit on page 13.
7
BYPASS
Not Synchronous Analog
Input
Forces the Equalizing and DC RESTORE stages into bypass mode when HIGH. No equalization occurs in this mode. Maximum cable length adjust. Adjusts the approximate maximum amount of cable to be equalized (from 0m to the maximum cable length). The output is muted (latched to the last state) when the maximum cable length is achieved. NOTE: MCLADJ is only recommended for data rates up to 360Mb/s. For data rates above this, MCLADJ should be left floating.
8
MCLADJ
Input
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Table 1-1: GS1574A Pin Descriptions (Continued)
Pin Number
9
Name
VEE_D
Timing
Analog
Type
Power
Description
Most negative power supply for the digital circuitry and output buffer. Connect to GND.
10, 11 12
SDO, SDO VEE_D
Analog Analog
Output Power
Equalized serial digital differential output. Most negative power supply for the digital circuitry and output buffer. Connect to GND.
13
VCC_D
Analog
Power
Most positive power supply for the digital I/O pins of the device. Connect to +3.3V DC.
14
MUTE
Not Synchronous
Input
CONTROL SIGNAL INPUT levels are LVCMOS/LVTTL compatible. (3.3V Tolerant) When the MUTE pin is set HIGH by the application interface, the serial digital output of the device will be forced to a steady state. When the MUTE pin is set LOW, the serial digital output of the device will be active. NOTE: This pin may be connected directly to the CD pin to allow mute on loss of carrier.
15
CD
Not Synchronous
Output
STATUS SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Indicates the presence of a good input signal. When the CD pin is LOW, a good input signal has been detected. When this pin is HIGH, the input signal is invalid. This pin will indicate loss of carrier for data rates > 19Mb/s.
16
VCC_A
Analog
Power
Most positive power supply for the analog circuitry of the device. Connect to +3.3V DC.
–
Center Pad
–
Power
Internally bonded to VEE_A.
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2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Table 2-1: Absolute Maximum Ratings
Parameter
Supply Voltage Input ESD Voltage Storage Temperature Range Input Voltage Range (any input) Operating Temperature Range Solder Reflow Temperature
Value
-0.5V to +3.6 VDC 2kV -50°C < Ts < 125°C -0.3 to (VCC +0.3)V 0°C to 70°C 260°C
2.2 DC Electrical Characteristics
Table 2-2: DC Electrical Characteristics
VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown
Parameter
Supply Voltage Power Consumption
Symbol
VCC PD
Conditions
– TA = 25°C –
Min
3.135 – – – –
Typ
3.3 215 – 65 VCC - ΔVSDO/2 1.75 1.3
Max
3.465 – 343 – –
Units
V mW mW mA V
Notes
±5% – – – –
Supply Current Output Common Mode Voltage Input Common Mode Voltage MCLADJ DC Voltage (to mute signal) MCLADJ Range CD Output Voltage
Is VCMOUT VCMIN –
TA = 25°C TA = 25°C TA = 25°C 0m, TA = 25°C TA = 25°C Carrier not present Carrier present
– –
– –
V V
– –
– VCD(OH) VCD(OL)
– 2.4
0.5 –
– –
V V
– –
–
–
0.4
V
–
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Table 2-2: DC Electrical Characteristics (Continued)
VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown
Parameter
Mute Input Voltage Required to Force Outputs to Mute Mute Input Voltage Required to Force Outputs Active
Symbol
VMute VMute
Conditions
Min to Mute
Min
2.0
Typ
–
Max
–
Units
V
Notes
–
Max to Activate
–
–
0.8
V
–
2.3 AC Electrical Characteristics
Table 2-3: AC Electrical Characteristics
VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown
Parameter
Serial input data rate Input Voltage Swing Output Voltage Swing
Symbol
DRSDO ΔVSDI ΔVSDO –
Conditions
– TA =25°C, differential 100Ω load, TA =25°C, differential 270Mb/s Belden 1694A: 0-350m Belden 8281: 0-280m 1.485Gb/s Belden 1694A: 0-140m Belden 8281: 0-100m 1.485Gb/s Belden 1694A: 140-200m 20% - 80% – – – – single ended single ended single ended
Min
143 720 –
Typ
– 800 750
Max
1485 950 –
Units
Mb/s mVp-p mVp-p UI
Notes
– 1 –
Output Jitter for Various Cable Lengths and Data Rates
–
0.2
–
2,5
–
–
0.25
–
UI
2,5
–
–
0.3
–
UI
4,5
Output Rise/Fall time Mismatch in rise/fall time Duty cycle distortion Overshoot Input Return Loss Input Resistance Input Capacitance Output Resistance NOTES:
– – – – – – – –
– – – – 15 – – –
80 – – – – 1.64 1 50
220 30 30 10 – – – –
ps ps ps % dB kΩ pF Ω
– – – – 3 – – –
1. 0m cable length. 2. All parts production tested. In order to guarantee jitter over the full range of specification (VCC = 3.3V ±5%, TA = 0°C to 70°C, and 720-880mV launch swing from the SDI cable driver) the recommended applications circuit must be used. 3. Tested on CB1574A board from 5MHz to 2GHz. 4. Based on characterization data using the recommended applications circuit, at VCC = 3.3V, TA = 25°C, and 800mV launch swing from the SDI cable driver. 5. Equalizer Pathological test signal is used.
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3. Solder Reflow Profiles
The device is manufactured with Matte-Sn terminations and is compatible with both standard eutectic and Pb-free solder reflow profiles. MSL qualification was performed using the maximum Pb-free reflow profile shown in Figure 3-1. The recommended standard Pb reflow profile is shown in Figure 3-2.
Temperature 60-150 sec. 20-40 sec. 260°C 250°C 3 °C/sec max 217°C 6°C/sec max
200°C
150°C
25°C Time 60-180 sec. max 8 min. max
Figure 3-1: Maximum Pb-free Solder Reflow Profile (Preferred)
Temperature
60-150 sec. 10-20 sec.
230°C 220°C 3 °C/sec max 183°C 6°C/sec max
150°C
100°C
25°C Time 120 sec. max 6 min. max
Figure 3-2: Standard Pb Solder Reflow Profile
GS1574A HD-LINX® II Adaptive Cable Equalizer Data Sheet 33416 - 10 August 2011
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4. Test Circuit
GigaBERT 1400 EXT. CLOCK DATA CLOCK OUT OUT 50/75
8281 or 1694A CABLE
IN GS1574A TEST BOARD
OUT OUT
CH. 1 CH. 2 TDS 820 EXT. TRIGGER
EXT. CLOCK 1.485GHz/270MHz
Figure 4-1: Test Circuit
5. Input / Output Circuits
3k SDI 3.6k RC
3k SDI 3.6k
Figure 5-1: Input Equivalent Circuit
VCC
12.2k + -
MCLADJ
150µ
Figure 5-2: MCLADJ Equivalent Circuit
GS1574A HD-LINX® II Adaptive Cable Equalizer Data Sheet 33416 - 10 August 2011 9 of 16
50
50
SDO
SDO
Figure 5-3: Output Circuit
MUTE, BYPASS
Figure 5-4: MUTE and BYPASS Circuits
CD
CD
Figure 5-5: CD Circuit
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6. Detailed Description
The GS1574A is a high speed BiCMOS IC designed to equalize serial digital signals. The GS1574A can equalize both HD and SD serial digital signals, and will typically equalize 200m of Belden 1694A cable at 1.485Gb/s and 350m at 270Mb/s. The GS1574A is powered from a single +3.3V power supply and consumes approximately 215mW of power.
6.1 Serial Digital Inputs
The serial data signal may be connected to the input pins (SDI/SDI) in either a differential or single ended configuration. AC coupling of the inputs is recommended, as the SDI and SDI inputs are internally biased at approximately 1.8V.
6.2 Cable Equalization
The input signal passes through a variable gain equalizing stage whose frequency response closely matches the inverse of the cable loss characteristic. In addition, the variation of the frequency response with control voltage imitates the variation of the inverse cable loss characteristic with cable length. The edge energy of the equalized signal is monitored by a detector circuit which produces an error signal corresponding to the difference between the desired edge energy and the actual edge energy. This error signal is integrated by both an internal and an external AGC filter capacitor providing a steady control voltage for the gain stage. As the frequency response of the gain stage is automatically varied by the application of negative feedback, the edge energy of the equalized signal is kept at a constant level which is representative of the original edge energy at the transmitter. The equalized signal is also DC restored, effectively restoring the logic threshold of the equalized signal to its correct level independent of shifts due to AC coupling. The digital output signals have a nominal voltage of 750mVpp differential, or 375mVpp single ended when terminated with 50Ω as shown in Figure 6-1.
+187.5mV VCM = 2.925V typical SDO -187.5mV
SDO 50 50
+187.5mV VCM = 2.925V typical -187.5mV
Figure 6-1: Typical Output Voltage Levels
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6.3 Programmable Mute Output
For SMPTE 259M inputs, the GS1574A incorporates a programmable threshold output mute (MCLADJ). In applications where there are multiple input channels using the GS1574A, it is advantageous to have a programmable mute output to avoid signal crosstalk. The output of the GS1574A can be muted when the input signal decreases below a certain input level. This threshold is determined using the input voltage applied to the MCLADJ pin. The MCLADJ pin may be left unconnected for applications where output muting is not required. This feature has been designed for use in applications such as routers where signal crosstalk and circuit noise cause the equalizer to output erroneous data when no input signal is present. The use of a Carrier Detect function with a fixed internal reference does not solve this problem since the signal to noise ratio on the circuit board could be significantly less than the default signal detection level set by the on chip reference. NOTE: MCLADJ is only recommended for data rates up to 360Mb/s. For data rates above this, MCLADJ should be left floating.
6.4 Mute and Carrier Detect
The GS1574A includes a MUTE input pin that allows the application interface to mute the serial digital output at any time. Set the MUTE pin HIGH to mute SDO and SDO. In this case, the outputs will mute regardless of the setting of the BYPASS pin. A Carrier Detect output pin (CD) indicates the presence of a valid signal at the input of the GS1574A. When CD is LOW, the device has detected a valid input on SDI and SDI. When CD is HIGH, the device has not detected a valid input. NOTE: CD will only detect loss of carrier for data rates greater than 19Mb/s. The CD output pin may be connected directly to the MUTE input pin to enable automatic muting of the GS1574A when no valid input signal has been detected. NOTE: If the maximum cable length is exceeded and the device is not in bypass mode the GS1574A will not assert the CD pin even if a carrier is present.
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7. Application Information
7.1 PCB Layout
Special attention must be paid to component layout when designing serial digital interfaces for HDTV. An FR-4 dielectric can be used, however, controlled impedance transmission lines are required for PCB traces longer than approximately 1cm. Note the following PCB artwork features used to optimize performance: • • • • PCB trace width for HD rate signals is closely matched to SMT component width to minimize reflections due to change in trace impedance. The PCB ground plane is removed under the GS1574A input components to minimize parasitic capacitance. The PCB ground plane is removed under the GS1574A output components to minimize parasitic capacitance. High speed traces are curved to minimize impedance changes.
7.2 Typical Application Circuit
CD MUTE VCC VCC
16
15
14
13
MUTE
VCC_A
VCC_D
CD
10n 6.2nH SDI 1μF 75Ω 1μF 75Ω 37.4Ω 3 1 VEE_A 2
10nF VEE_D 12 + 4.7μF SDO
SDI SDI
GS1574A
MCLADJ BYPASS
SDO
11
SDO
10
+ SDO
4
VEE_A
VEE_D
9
4.7μF
AGC
5
AGC
6
7
8 MCLADJ
470nF
470nF BYPASS
NOTE: All resistors in Ohms, capacitors in Farads, and inductors in Henrys, unless otherwise noted.
Figure 7-1: GS1574A Typical Application Circuit
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8. Package and Ordering Information
8.1 Package Dimensions
4.00+/-0.05
B
DATUM A
4.00+/-0.05
CENTER TAB
DETAIL B
2X 2X
0.15 C 0.15 C DATUM B 0.65 16X
0.20 REF
0.35+/-0.05 0.10 CAB 0.05 C
C
0.10 C 16X 0.08 C SEATING PLANE
0.85+/-0.05 0.00-0.05
DATUM A OR B
0.65/2 0.65 DETAIL B SCALE:NTS TERMINAL TIP
Figure 8-1: Package Dimensions
GS1574A HD-LINX® II Adaptive Cable Equalizer Data Sheet 33416 - 10 August 2011
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2.76+/-0.10
PIN 1 AREA
0.40+/-0.05
A
2.76+/-0.10
8.2 Recommended PCB Footprint
0.35 0.65 0.55
3.70
2.76
CENTER PAD
NOTE: All dimensions are in millimeters. 2.76 3.70
The Center Pad should be connected to the most negative power supply plane for analog circuitry in the device (VEE_A) by a minimum of 5 vias. Note: Suggested dimensions only. Final dimensions should conform to customer design rules and process optimizations.
8.3 Packaging Data
Table 8-1: Packaging Data
Parameter
Package Type Package Drawing Reference Moisture Sensitivity Level Junction to Case Thermal Resistance, θj-c Junction to Air Thermal Resistance, θj-a (at zero airflow) Psi Pb-free and RoHS compliant
Value
4mm x 4mm 16-pin QFN JEDEC M0220 3 31.0°C/W 43.8°C/W 11.0°C/W Yes
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9. Ordering Information
Table 9-1: GS1574A Ordering Information
Part Number
GS1574ACNE3 GS1574ACTE3
Package
16-pin QFN 16-pin QFN (250pc tape and reel)
Temperature Range
0°C to 70°C 0°C to 70°C
DOCUMENT IDENTIFICATION
CAUTION
ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
DATA SHEET
The product is in production. Gennum reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible.
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Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. All other trademarks mentioned are the properties of their respective owners. GENNUM and the Gennum logo are registered trademarks of Gennum Corporation. © Copyright 2004 Gennum Corporation. All rights reserved. www.gennum.com
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