GS1574ACNE3

GS1574A HD-LINX® II Adaptive Cable Equalizer GS1574A Data Sheet Features • • • • • • • • • • • • • SMPTE 292M and SMPTE 259M compliant Automatic cable equalization Multi-standard operation from 143Mb/s to 1.485Gb/s Supports DVB-ASI at 270Mb/s Small footprint (4mm x 4mm) Pb-free and RoHS compliant Manual bypass (useful for low data rates with slow rise/fall times) Performance optimized for 270Mb/s and 1.485Gb/s Typical maximum equalized length of Belden 1694A cable: 140m at 1.485Gb/s, 350m at 270Mb/s 50Ω differential output (with internal 50Ω pull-ups) Manual output mute or programmable mute based on max cable length adjust Single 3.3V power supply operation Operating temperature range: 0°C to +70°C Description The GS1574A is a second-generation high-speed BiCMOS integrated circuit designed to equalize and restore signals received over 75Ω co-axial cable. The GS1574A is designed to support SMPTE 292M and SMPTE 259M, and is optimized for performance at 270Mb/s and 1.485Gb/s. The GS1574A features DC restoration to compensate for the DC content of SMPTE pathological test patterns. A voltage programmable mute threshold (MCLADJ) is included to allow muting of the GS1574A output when an approximate selected cable length is reached for SMPTE 259M signals. This feature allows the GS1574A to distinguish between low amplitude SD-SDI signals and noise at the input of the device. The serial digital outputs of the GS1574A may be forced to a mute state by applying a voltage to the MUTE pin. Power consumption is typically 215mW using a 3.3V power supply. The GS1574A is lead-free, and the encapsulation compound does not contain halogenated flame retardant. This component and all homogeneous subcomponents are RoHS compliant. Applications • SMPTE 292M and SMPTE 259M Coaxial Cable Serial Digital Interfaces. MCLADJ CABLE LENGTH ADJUSTOR CARRIER DETECT MUTE CD MUTE BYPASS SDI SDI EQUALIZER DC RESTORE OUTPUT SDO SDO AGC GS1574A Functional Block Diagram 33416 - 5 March 2006 1 of 16 www.gennum.com GS1574A Data Sheet Contents Features ........................................................................................................................1 Applications...................................................................................................................1 Description ....................................................................................................................1 1. Pin Out ......................................................................................................................3 1.1 GS1574A Pin Assignment ..............................................................................3 1.2 GS1574A Pin Descriptions .............................................................................3 2. Electrical Characteristics ...........................................................................................5 2.1 Absolute Maximum Ratings ............................................................................5 2.2 DC Electrical Characteristics ..........................................................................5 2.3 AC Electrical Characteristics ...........................................................................6 2.4 Solder Reflow Profiles .....................................................................................7 3. Input / Output Circuits ...............................................................................................9 4. Detailed Description ................................................................................................11 4.1 Serial Digital Inputs .......................................................................................11 4.2 Cable Equalization ........................................................................................11 4.3 Programmable Mute Output ..........................................................................12 4.4 Mute and Carrier Detect ................................................................................12 5. Application Information............................................................................................13 5.1 PCB Layout ...................................................................................................13 5.2 Typical Application Circuit .............................................................................13 6. Package & Ordering Information .............................................................................14 6.1 Package Dimensions ....................................................................................14 6.2 Recommended PCB Footprint ......................................................................15 6.3 Packaging Data .............................................................................................15 6.4 Ordering Information .....................................................................................15 7. Revision History ......................................................................................................16 33416 - 5 March 2006 2 of 16 GS1574A Data Sheet 1. Pin Out 1.1 GS1574A Pin Assignment VCC_A MUTE VCC_D 13 12 VEE_D 11 GS1574A (top view) SDI 3 10 SDO CD 15 16 VEE_A 1 14 SDI 2 SDO VEE_A 4 5 AGC 6 AGC 7 BYPASS 8 MCLADJ 9 VEE_D Center Pad (bottom of package, internally bonded to VEE_A) Figure 1-1: 16-Pin QFN 1.2 GS1574A Pin Descriptions Table 1-1: GS1574A Pin Descriptions Pin Number 1, 4 Name VEE_A Timing Analog Type Power Description Most negative power supply for analog circuitry. Connect to GND. 2, 3 5, 6 SDI, SDI AGC, AGC Analog Analog Input – Serial digital differential input. External AGC capacitor. Connect pin 5 and pin 6 together as shown in the Typical Application Circuit on page 13. 7 8 BYPASS MCLADJ Not Synchronous Analog Input Input Forces the Equalizing and DC RESTORE stages into bypass mode when HIGH. No equalization occurs in this mode. Maximum cable length adjust. Adjusts the approximate maximum amount of cable to be equalized (from 0m to the maximum cable length). The output is muted (latched to the last state) when the maximum cable length is achieved. NOTE: MCLADJ is only recommended for data rates up to 360Mb/s. For data rates above this, MCLADJ should be left floating. 33416 - 5 March 2006 3 of 16 GS1574A Data Sheet Table 1-1: GS1574A Pin Descriptions (Continued) Pin Number 9 Name VEE_D Timing Analog Type Power Description Most negative power supply for the digital circuitry and output buffer. Connect to GND. 10, 11 12 SDO, SDO VEE_D Analog Analog Output Power Equalized serial digital differential output. Most negative power supply for the digital circuitry and output buffer. Connect to GND. 13 VCC_D Analog Power Most positive power supply for the digital I/O pins of the device. Connect to +3.3V DC. 14 MUTE Not Synchronous Input CONTROL SIGNAL INPUT levels are LVCMOS/LVTTL compatible. (3.3V Tolerant) When the MUTE pin is set HIGH by the application interface, the serial digital output of the device will be forced to a steady state. When the MUTE pin is set LOW, the serial digital output of the device will be active. NOTE: This pin may be connected directly to the CD pin to allow mute on loss of carrier. 15 CD Not Synchronous Output STATUS SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Indicates the presence of a good input signal. When the CD pin is LOW, a good input signal has been detected. When this pin is HIGH, the input signal is invalid. This pin will indicate loss of carrier for data rates > 19Mb/s. 16 VCC_A Analog Power Most positive power supply for the analog circuitry of the device. Connect to +3.3V DC. – Center Pad – Power Internally bonded to VEE_A. 33416 - 5 March 2006 4 of 16 GS1574A Data Sheet 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Parameter Supply Voltage Input ESD Voltage Storage Temperature Range Input Voltage Range (any input) Operating Temperature Range Solder Reflow Temperature Value -0.5V to +3.6 VDC 2kV -50°C < Ts < 125°C -0.3 to (VCC +0.3)V 0°C to 70°C 260°C 2.2 DC Electrical Characteristics Table 2-1: DC Electrical Characteristics VDD = 3.3V, TA = 0°C to 70°C, unless otherwise shown Parameter Supply Voltage Power Consumption Supply Current Output Common Mode Voltage Input Common Mode Voltage MCLADJ DC Voltage (to mute signal) MCLADJ Range CD Output Voltage Symbol VCC PD Is VCMOUT VCMIN – – VCD(OH) VCD(OL) Conditions – TA = 25°C TA = 25°C TA = 25°C TA = 25°C 0m, TA = 25°C TA = 25°C Carrier not present Carrier present Min to Mute Max to Activate Min 3.135 – – – – – – 2.4 – 2.0 – Typ 3.3 215 65 VCC - ΔVSDO/2 1.75 1.3 0.5 – – – – Max 3.465 – – – – – – – 0.4 – 0.8 Units V mW mA V V V V V V V V Notes ±5% – – – – – – – – – – Mute Input Voltage Required to Force Outputs to Mute Mute Input Voltage Required to Force Outputs Active VMute VMute 33416 - 5 March 2006 5 of 16 GS1574A Data Sheet 2.3 AC Electrical Characteristics Table 2-2: AC Electrical Characteristics VDD = 3.3V, TA = 0°C to 70°C, unless otherwise shown Parameter Serial input data rate Input Voltage Swing Output Voltage Swing Symbol DRSDO ΔVSDI ΔVSDO – – – – Conditions – TA =25°C, differential 100Ω load, TA =25°C, differential 270Mb/s, Belden 1694A, 350m 270Mb/s, Belden 8281, 280m 1.485Gb/s, Belden 1694A, 140m 1.485Gb/s, Belden 8281, 100m 20% - 80% – – – – single ended single ended single ended Min 143 720 – Typ – 800 750 Max 1485 950 – Units Mb/s mVp-p mVp-p UI UI UI UI ps ps ps % dB kΩ pF Ω Notes – 1 – Maximum Equalized Cable Length – – – – – – – – 15 – – – 0.2 0.2 0.25 0.25 80 – – – – 1.64 1 50 – – – – 220 30 30 10 – – – – 2 2 2 2 – – – – 3 – – – Output Rise/Fall time Mismatch in rise/fall time Duty cycle distortion Overshoot Input Return Loss Input Resistance Input Capacitance Output Resistance NOTES: – – – – – – – – 1. 0m cable length. 2. Equalizer Pathological. 3. Tested on CB1574A board from 5MHz to 2GHz. 33416 - 5 March 2006 6 of 16 GS1574A Data Sheet 2.4 Solder Reflow Profiles The device is manufactured with Matte-Sn terminations and is compatible with both standard eutectic and Pb-free solder reflow profiles. MSL qualification was performed using the maximum Pb-free reflow profile shown in Figure 2-1. The recommended standard Pb reflow profile is shown in Figure 2-2. Temperature 60-150 sec. 20-40 sec. 260˚C 250˚C 3 ˚C/sec max 217˚C 6˚C/sec max 200˚C 150˚C 25˚C Time 60-180 sec. max 8 min. max Figure 2-1: Maximum Pb-free Solder Reflow Profile (Preferred) Temperature 60-150 sec. 10-20 sec. 230˚C 220˚C 3 ˚C/sec max 183˚C 6˚C/sec max 150˚C 100˚C 25˚C Time 120 sec. max 6 min. max Figure 2-2: Standard Pb Solder Reflow Profile (Pb-free package) 33416 - 5 March 2006 7 of 16 GS1574A Data Sheet GigaBERT 1400 EXT. CLOCK DATA CLOCK OUT OUT 50/75 8281 or 1694A CABLE IN GS1574A TEST BOARD OUT OUT CH. 1 CH. 2 TDS 820 EXT. TRIGGER EXT. CLOCK 1.485GHz/270MHz Figure 2-3: Test Circuit 33416 - 5 March 2006 8 of 16 GS1574A Data Sheet 3. Input / Output Circuits 3k SDI RC 3.6k 3k SDI 3.6k Figure 3-1: Input Equivalent Circuit VCC 12.2k + MCLADJ - 150µ Figure 3-2: MCLADJ Equivalent Circuit 50 50 SDO SDO Figure 3-3: Output Circuit 33416 - 5 March 2006 9 of 16 GS1574A Data Sheet MUTE, BYPASS Figure 3-4: MUTE and BYPASS Circuits CD Figure 3-5: CD Circuit 33416 - 5 March 2006 10 of 16 GS1574A Data Sheet 4. Detailed Description The GS1574A is a high speed BiCMOS IC designed to equalize serial digital signals. The GS1574A can equalize both HD and SD serial digital signals, and will typically equalize greater than 140m of Belden 1694A cable at 1.485Gb/s and 350m at 270Mb/s. The GS1574A is powered from a single +3.3V power supply and consumes approximately 215mW of power. 4.1 Serial Digital Inputs The serial data signal may be connected to the input pins (SDI/SDI) in either a differential or single ended configuration. AC coupling of the inputs is recommended, as the SDI and SDI inputs are internally biased at approximately 1.8V. 4.2 Cable Equalization The input signal passes through a variable gain equalizing stage whose frequency response closely matches the inverse of the cable loss characteristic. In addition, the variation of the frequency response with control voltage imitates the variation of the inverse cable loss characteristic with cable length. The edge energy of the equalized signal is monitored by a detector circuit which produces an error signal corresponding to the difference between the desired edge energy and the actual edge energy. This error signal is integrated by both an internal and an external AGC filter capacitor providing a steady control voltage for the gain stage. As the frequency response of the gain stage is automatically varied by the application of negative feedback, the edge energy of the equalized signal is kept at a constant level which is representative of the original edge energy at the transmitter. The equalized signal is also DC restored, effectively restoring the logic threshold of the equalized signal to its correct level independent of shifts due to AC coupling. The digital output signals have a nominal voltage of 750mVpp differential, or 375mVpp single ended when terminated with 50Ω as shown in Figure 4-1. 33416 - 5 March 2006 11 of 16 GS1574A Data Sheet +187.5mV VCM = 2.925V typical SDO -187.5mV SDO 50 50 +187.5mV VCM = 2.925V typical -187.5mV Figure 4-1: Typical Output Voltage Levels 4.3 Programmable Mute Output For SMPTE 259M inputs, the GS1574A incorporates a programmable threshold output mute (MCLADJ). In applications where there are multiple input channels using the GS1574A, it is advantageous to have a programmable mute output to avoid signal crosstalk. The output of the GS1574A can be muted when the input signal decreases below a certain input level. This threshold is determined using the input voltage applied to the MCLADJ pin. The MCLADJ pin may be left unconnected for applications where output muting is not required. This feature has been designed for use in applications such as routers where signal crosstalk and circuit noise cause the equalizer to output erroneous data when no input signal is present. The use of a Carrier Detect function with a fixed internal reference does not solve this problem since the signal to noise ratio on the circuit board could be significantly less than the default signal detection level set by the on chip reference. NOTE: MCLADJ is only recommended for data rates up to 360Mb/s. For data rates above this, MCLADJ should be left floating. 4.4 Mute and Carrier Detect The GS1574A includes a MUTE input pin that allows the application interface to mute the serial digital output at any time. Set the MUTE pin HIGH to mute SDO and SDO. In this case, the outputs will mute regardless of the setting of the BYPASS pin. A Carrier Detect output pin (CD) indicates the presence of a valid signal at the input of the GS1574A. When CD is LOW, the device has detected a valid input on SDI and SDI. When CD is HIGH, the device has not detected a valid input. NOTE: CD will only detect loss of carrier for data rates greater than 19Mb/s. The CD output pin may be connected directly to the MUTE input pin to enable automatic muting of the GS1574A when no valid input signal has been detected. NOTE: If the maximum cable length is exceeded and the device is not in bypass mode the GS1574A will not assert the CD pin even if a carrier is present. 33416 - 5 March 2006 12 of 16 GS1574A Data Sheet 5. Application Information 5.1 PCB Layout Special attention must be paid to component layout when designing serial digital interfaces for HDTV. An FR-4 dielectric can be used, however, controlled impedance transmission lines are required for PCB traces longer than approximately 1cm. Note the following PCB artwork features used to optimize performance: • • • • PCB trace width for HD rate signals is closely matched to SMT component width to minimize reflections due to change in trace impedance. The PCB ground plane is removed under the GS1574A input components to minimize parasitic capacitance. The PCB ground plane is removed under the GS1574A output components to minimize parasitic capacitance. High speed traces are curved to minimize impedance changes. 5.2 Typical Application Circuit CD MUTE VCC VCC 16 VCC_A 10n SDI 6.2n 1 VEE_A 1u 75 1u 3 SDI 2 SDI 15 CD 14 MUTE 13 VCC_D 10n VEE_D 12 + 4u7 SDO SDO GS1574A SDO BYPASS MCLADJ 11 10 + SDO 4 75 37R4 VEE_A AGC AGC VEE_D 9 4u7 5 470n 6 7 8 MCLADJ 470n BYPASS NOTE: All resistors in Ohms, capacitors in Farads, and inductors in Henrys, unless otherwise noted. Figure 5-1: GS1574A Typical Application Circuit 33416 - 5 March 2006 13 of 16 GS1574A Data Sheet 6. Package & Ordering Information 6.1 Package Dimensions 0.40+/-0.05 4.00+/-0.05 A DATUM A 2.76+/-0.10 B PIN 1 AREA 4.00+/-0.05 CENTER TAB DETAIL B 2X 2X 0.15 C 0.15 C DATUM B 0.65 16X 0.20 REF 0.35+/-0.05 0.10 CAB 0.05 C C 0.10 C 16X 0.08 C SEATING PLANE 0.85+/-0.05 0.00-0.05 DATUM A OR B 0.65/2 TERMINAL TIP 0.65 DETAIL B SCALE:NTS 33416 - 5 March 2006 14 of 16 2.76+/-0.10 GS1574A Data Sheet 6.2 Recommended PCB Footprint 0.35 0.65 0.55 3.70 2.76 CENTER PAD NOTE: All dimensions are in millimeters. 2.76 3.70 The Center Pad should be connected to the most negative power supply plane for analog circuitry in the device (VEE_A) by a minimum of 5 vias. Note: Suggested dimensions only. Final dimensions should conform to customer design rules and process optimizations. 6.3 Packaging Data Parameter Package Type Package Drawing Reference Moisture Sensitivity Level Junction to Case Thermal Resistance, θj-c Junction to Air Thermal Resistance, θj-a (at zero airflow) Psi Pb-free and RoHS compliant Value 4mm x 4mm 16-pin QFN JEDEC M0220 3 31.0°C/W 43.8°C/W 11.0°C/W Yes 6.4 Ordering Information Part Number GS1574A GS1574ACNE3 Package 16-pin QFN Temperature Range 0°C to 70°C 33416 - 5 March 2006 15 of 16 GS1574A Data Sheet 7. Revision History Version 0 ECR 136149 PCN – Date March 2005 Changes and/or Modifications Converted to Preliminary Data Sheet. Updated typical application circuit. Updated Input/Output circuits. Updated AC and DC electrical characteristics. Updated description of MUTE and CD functionality. Correced minor typing errors. Updated center pad dimensions on PCB footprint. Corrected description of connection for AGC and AGC pins in the Pin Description table. Clarified solder reflow profile descriptions. Corrected minor typing errors. Rephrased RoHS compliance statement. Amended notes on use of MCLADJ above 360 Mb/s. Convert to Data Sheet. Corrected typing errors. Corrected process to BiCMOS. Corrected pad standoff height and tolerances for pad width & package dimension. Corrected pad shape. 1 136885 – May 2005 2 3 4 5 137167 137321 137744 139634 – – – 38695 June 2005 June 2005 September 2005 March 2006 CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DOCUMENT IDENTIFICATION DATA SHEET The product is in production. Gennum reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. GENNUM CORPORATION Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. GENNUM and the G logo are registered trademarks of Gennum Corporation. © Copyright 2004 Gennum Corporation. All rights reserved. Printed in Canada. www.gennum.com 33416 - 5 March 2006 16 16 of 16