GS1575B

GS1575B / GS9075B HD-LINX® II Multi-Rate SDI Automatic Reclocker Features GS1575B • • • • • • • • • • • • • • • SMPTE 292M, 259M and 344M compliant Supports data rates of 143, 177, 270, 360, 540, 1483.5, 1485 Mb/s Supports DVB-ASI at 270Mb/s Pb-free and RoHS Compliant Auto and Manual Modes for rate selection Standards indication in Auto Mode 4:1 input multiplexer Loss of Signal (LOS) Output Lock Detect Output On-chip Input and Output Termination Differential 50Ω inputs and outputs Mute, Bypass and Autobypass functions SD/HD indication output to control GS1528A Dual Slew-Rate Cable Driver Single 3.3V power supply Operating temperature range: 0°C to 70°C Description The GS1575B/9075B is a Multi-Rate Serial Digital Reclocker designed to automatically recover the embedded clock from a digital video signal and re-time the incoming video data. The GS1575B Serial Digital Reclocker will recover the embedded clock signal and re-time the data from a SMPTE 292M, SMPTE 259M or SMPTE 344M compliant digital video signal. The GS9075B Serial Digital Reclocker will recover the embedded clock signal and re-time the data from a SMPTE 259M or SMPTE 344M compliant digital video signal. The GS1575B/9075B removes the high frequency jitter components from the bit-serial stream. Input termination is on-chip for seamless matching to 50Ω transmission lines. An LVPECL compliant output interfaces seamlessly to the GS1578A/GS9078A Cable Driver. The GS1575B/9075B can operate in either auto or manual rate selection mode. In Auto mode the device will automatically detect and lock onto incoming SMPTE SDI data signals at any supported rate. For single rate data systems, the GS1575B/9075B can be configured to operate in Manual mode. In both modes, the device requires only one external crystal to set the VCO frequency when not locked and provides adjustment free operation. In systems which require passing of non-SMPTE data rates, the GS1575B/9075B can be configured to either automatically or manually enter a bypass mode in order to pass the signal without reclocking. The ASI/177 input pin allows for manual selection of support of either 177Mb/s or DVB-ASI inputs. The GS1575B/9075B is Pb-free, and the encapsulation compound does not contain halogenated flame retardant. This component and all homogeneous sub-components are RoHS compliant. GS9075B • • • • • • • • • • • • • • SMPTE 259M and 344M compliant Supports data rates of 143, 177, 270, 360, and 540Mb/s Supports DVB-ASI at 270Mb/s Pb-free and RoHS Compliant Auto and Manual Modes for rate selection Standards indication in Auto Mode 4:1 input multiplexer Loss of Signal (LOS) Output Lock Detect Output On-chip Input and Output Termination Differential 50Ω inputs and outputs Mute, Bypass and Autobypass functions Single 3.3V power supply Operating temperature range: 0°C to 70°C Applications GS1575B • SMPTE 292M, SMPTE 259M and SMPTE 344M Serial Digital Interfaces GS9075B • SMPTE 259M and SMPTE 344M Serial Digital Interfaces. GS1575B / GS9075B HD-LINX® II Multi-Rate SDI Automatic Reclocker Data Sheet 40063 - 1 June 2009 www.gennum.com 1 of 28 XTAL+ XTAL- XTAL XTAL OUT+ OUT- LF+ LF- KBB XTAL OSC BUFFER RE-TIMER M U X DATA BUFFER DDO/DDO DDO_MUTE SCO_ENABLE DDI 0 PHASE FREQUENCY DETECTOR D A T A M U X DIVIDE BY 152, 160, 208 M U X CHARGE PUMP CLOCK BUFFER SCO/SCO VCO DDI 1 PHASE DETECTOR DIVIDE BY 2,4,6,8,12,16 DDI 2 DDI 3 DDI_SEL[1:0] CONTROL LOGIC BYPASS LOGIC SS[2:0] ASI/177 AUTO/MAN SD/HD LD LOS AUTOBYPASS BYPASS GS1575B Functional Block Diagram XTAL+ XTAL- XTAL XTAL OUT+ OUT- LF+ LF- KBB XTAL OSC BUFFER RE-TIMER M U X DATA BUFFER DDO/DDO DDO_MUTE SCO_ENABLE DDI 0 PHASE FREQUENCY DETECTOR D A T A M U X DIVIDE BY 152, 160 M U X CHARGE PUMP CLOCK BUFFER SCO/SCO VCO DDI 1 PHASE DETECTOR DIVIDE BY 2,4,6,8,12 DDI 2 DDI 3 DDI_SEL[1:0] CONTROL LOGIC BYPASS LOGIC SS[2:0] ASI/177 AUTO/MAN SD/HD LD LOS AUTOBYPASS BYPASS GS9075B Functional Block Diagram GS1575B / GS9075B HD-LINX® II Multi-Rate SDI Automatic Reclocker Data Sheet 40063 - 1 June 2009 2 of 28 Revision History Version 1 0 ECR 152100 141777 PCN – – Date June 2009 August 2006 Changes and/or Modifications Updated document format. Converting to Preliminary Data Sheet. Removed ‘Proprietary and Confidential’ footer. New Document. A 141210 – July 2006 Contents Features.................................................................................................................................................................1 Applications.........................................................................................................................................................1 Description...........................................................................................................................................................1 Revision History .................................................................................................................................................3 1. Pin Out...............................................................................................................................................................5 1.1 GS1575B Pin Assignment ...............................................................................................................5 1.2 GS9075B Pin Assignment ...............................................................................................................6 1.3 Pin Descriptions ................................................................................................................................7 2. Electrical Characteristics ......................................................................................................................... 10 2.1 Absolute Maximum Ratings ....................................................................................................... 10 2.2 DC Electrical Characteristics ..................................................................................................... 10 2.3 AC Electrical Characteristics ..................................................................................................... 11 3. Input / Output Circuits ............................................................................................................................. 13 4. Detailed Description.................................................................................................................................. 16 4.1 Slew Rate Phase Lock Loop (S-PLL) ......................................................................................... 16 4.2 VCO .................................................................................................................................................... 17 4.3 Charge Pump ................................................................................................................................... 17 4.4 Frequency Acquisition Loop — The Phase-Frequency Detector .................................. 18 4.5 Phase Acquisition Loop — The Phase Detector ................................................................... 18 4.6 4:1 Input Mux .................................................................................................................................. 19 4.7 Automatic and Manual Data Rate Selection ......................................................................... 19 4.8 Bypass Mode ................................................................................................................................... 20 4.9 DVB-ASI Operation ....................................................................................................................... 21 4.10 Lock and LOS Indicators ........................................................................................................... 21 4.11 Output Drivers and Serial Clock Outputs ........................................................................... 22 4.12 Output Mute .................................................................................................................................. 22 5. Typical Application Circuits ................................................................................................................... 23 6. Package & Ordering Information .......................................................................................................... 25 6.1 Package Dimensions ..................................................................................................................... 25 6.2 Recommended PCB Footprint ................................................................................................... 26 GS1575B / GS9075B HD-LINX® II Multi-Rate SDI Automatic Reclocker Data Sheet 40063 - 1 June 2009 3 of 28 6.3 Packaging Data ............................................................................................................................... 26 6.4 Solder Reflow Profiles .................................................................................................................. 27 6.5 Ordering Information ................................................................................................................... 28 GS1575B / GS9075B HD-LINX® II Multi-Rate SDI Automatic Reclocker Data Sheet 40063 - 1 June 2009 4 of 28 1. Pin Out 1.1 GS1575B Pin Assignment VCC_CP XTAL_OUTXTAL_OUT+ VEE_CP XTAL+ XTAL- GND LF- DDI0 DDI0_VTT DDI0 GND DDI1 DDI1_VTT DDI1 GND DDI2 DDI2_VTT DDI2 GND DDI3 DDI3_VTT DDI3 GND 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 GND LF+ NC NC NC NC NC NC VEE_DDO VCC_DDO DDO NC DDO GND_DRV VEE_SCO VCC_SCO SCO NC SCO GND DDO_MUTE SCO_ENABLE KBB SD/HD 2 3 4 5 6 7 8 9 10 11 12 13 14 GS1575B 64-pin QFN (Top View) 42 41 40 39 38 37 36 35 34 15 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AUTO/MAN ASI/177 VEE_VCO AUTOBYPASS VCC_VCO DDI_SEL0 DDI_SEL1 BYPASS Ground Pad (bottom of package) Figure 1-1: 64-Pin QFN GS1575B / GS9075B HD-LINX® II Multi-Rate SDI Automatic Reclocker Data Sheet 40063 - 1 June 2009 LOCKED LOS VCC_DIG VEE_DIG GND SS0 SS1 SS2 5 of 28 1.2 GS9075B Pin Assignment VCC_CP XTAL_OUTXTAL_OUT+ VEE_CP XTAL+ XTAL- GND LF- DDI0 DDI0_VTT DDI0 GND DDI1 DDI1_VTT DDI1 GND DDI2 DDI2_VTT – DDI2 GND DDI3 DDI3_VTT DDI3 GND 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 GND LF+ NC NC NC NC NC NC VEE_DDO VCC_DDO DDO NC DDO GND_DRV VEE_SCO VCC_SCO SCO – 2 3 4 5 6 7 8 9 10 11 12 13 14 – GS9075B 64-pin QFN (Top View) 42 41 40 39 38 37 36 35 – SCO GND DDO_MUTE SCO_ENABLE KBB SD NC – 34 15 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AUTO/MAN VEE_VCO ASI/177 AUTOBYPASS VCC_VCO DDI_SEL0 DDI_SEL1 BYPASS Ground Pad (bottom of package) Figure 1-2: 64-Pin QFN GS1575B / GS9075B HD-LINX® II Multi-Rate SDI Automatic Reclocker Data Sheet 40063 - 1 June 2009 LOCKED LOS VCC_DIG VEE_DIG GND SS0 SS1 SS2 6 of 28 1.3 Pin Descriptions Table 1-1: Pin Descriptions Pin Number 1, 3 2 Name DDI0, DDI0 DDI0_VTT Type Input Passive Description Serial digital differential input 0. Center tap of two 50Ω on-chip termination resistors between DDI0 and DDI0. Recommended connect to GND. 4, 8, 12,16, 32, 37, 43, 49, 64 5, 7 6 GND Passive DDI1,DDI1 DDI1_VTT Input Passive Serial digital differential input 1. Center tap of two 50Ω on-chip termination resistors between DDI1 and DDI1. Serial digital differential input 2. Center tap of two 50Ω on-chip termination resistors between DDI2 and DDI2. Serial digital differential input 3. Center tap of two 50Ω on-chip termination resistors between DDI3 and DDI3. Serial digital input select. DDI_SEL1 0 0 1 1 DDI_SEL0 0 1 0 1 INPUT SELECTED DDI0 DDI1 DDI2 DDI3 9, 11 10 DDI2, DDI2 DDI2_VTT Input Passive 13, 15 14 DDI3, DDI3 DDI3_VTT Input Passive 17, 18 DDI_SEL[1:0] Logic Input 19 BYPASS Logic Input Bypass the reclocker stage. When BYPASS is HIGH, it overwrites the AUTOBYPASS setting. 20 AUTOBYPASS Logic Input Automatically bypasses the reclocker stage when the PLL is not locked This pin is ignored when BYPASS is HIGH. 21 AUTO/MAN Logic Input Auto/Manual select. When set HIGH, the standard is automatically detected from the input data rate. When set LOW, the user must program the input standard using the SS[2:0] pins. 22 VCC_VCO Power Most positive power supply connection for the internal VCO section. Connect to 3.3V. 23 VEE_VCO Power Most negative power supply connection for the internal VCO section. Connect to GND. GS1575B / GS9075B HD-LINX® II Multi-Rate SDI Automatic Reclocker Data Sheet 40063 - 1 June 2009 7 of 28 Table 1-1: Pin Descriptions (Continued) Pin Number 24, 25, 26 Name SS[2:0] Type Bi-directional Description When AUTO/MAN is HIGH, SS[0:2] are outputs, displaying the data rate to which the PLL has locked. When AUTO/MAN is LOW, SS[0:2] are inputs, forcing the PLL to lock only to a selected data rate . SS2 SS1 SS0 DATA RATE SELECTED/FORCED (Mb/s) 143 177 270 360 540 1483.5/1485 0 0 0 0 1 1 27 ASI/177 Logic Input 0 0 1 1 0 0 0 1 0 1 0 1 When set HIGH, the device disables the 177Mb/s data rate in the data rate detection circuit. This prevents a false lock to 177Mb/s when using DVB-ASI. When set LOW, 177Mb/s lock is possible, however, if a 270Mb/s ASI signal is applied, the device could false lock to the 177MHz signal. 28 LOCKED Output Lock Detect. This pin is set HIGH by the device when the PLL is locked. 29 LOS Output Loss of Signal. Set HIGH when there are no transitions on the active DDI[3:0] input. See Lock and LOS Indicators on page 21. 30 VCC_DIG Power Most positive power supply connection for the internal glue logic. Connect to 3.3V. 31 VEE_DIG Power Most negative power supply connection for the internal glue logic. Connect to GND. 33 SD/HD (GS1575B only) Output This signal will be set LOW by the device when the reclocker has locked to 1.485Gbps or 1.485/1.001Gbps, or when a non-SMPTE standard is applied (i.e. the device is not locked). It will be set HIGH when the reclocker has locked to 143Mbps, 177Mbps, 270Mbps, 360Mbps, or 540Mbps. 33 SD (GS9075B only) Output This signal will go HIGH when the reclocker has locked to the input SD signal. It will be LOW otherwise. Controls the loop bandwidth of the PLL. Leave this pin floating for serial reclocking applications. 34 KBB Analog Input 35 SCO_ENABLE Power Serial clock output enable. Connect to VCC to enable the serial clock output. Connect to GND to disable the serial clock output. NOTE: This is not a TTL signal input. 36 DDO_MUTE Logic Input Mutes the DDO/DDO outputs. This option is not available in bypass mode. GS1575B / GS9075B HD-LINX® II Multi-Rate SDI Automatic Reclocker Data Sheet 40063 - 1 June 2009 8 of 28 Table 1-1: Pin Descriptions (Continued) Pin Number 38, 40 Name SCO, SCO Type Output Description Serial clock output. When SCO_ENABLE is set HIGH, a serial digital differential clock will be presented to the application layer at the selected data rate. 39, 45, 54 - 59 41 NC VCC_SCO No Connect Power Not connected internally. Most positive power supply connection for the SCO/SCO output driver. Connect to 3.3V. 42 VEE_SCO Power Most negative power supply connection for the SCO/SCO output driver. Connect to GND. 43 44, 46 47 GND_DRV DDO, DDO VCC_DDO Passive Output Power Recommended connect to GND. Differential Serial Digital Outputs. Most positive power supply connection for the DDO/DDO output driver. Connect to 3.3V. 48 VEE_DDO Power Most negative power supply connection for the DDO/DDO output driver. Connect to GND. 50, 51 XTAL_OUT+, XTAL_OUTXTAL+, XTAL- Output Differential outputs of the reference oscillator used for monitoring or test purposes. Reference crystal input. Connect to the GO1535 as shown in the Typical Application Circuits on page 23. Most negative power supply connection for the internal charge pump. Connect to GND. 52, 53 Input 60 VEE_CP Power 61 VCC_CP Power Most positive power supply connection for the internal charge pump. Connect to 3.3V. 62, 63 LF+, LF- Passive Loop filter capacitor connection. Connect as shown in the Typical Application Circuits on page 23. Ground pad on bottom of package. Solder to main ground plane following recommendations under Recommended PCB Footprint on page 26. – Center Pad – GS1575B / GS9075B HD-LINX® II Multi-Rate SDI Automatic Reclocker Data Sheet 40063 - 1 June 2009 9 of 28 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Operating Temperature Range Storage Temperature Range Input ESD Voltage Solder Reflow Temperature Value +3.6 VDC Vcc + 0.5V 0°C to 70°C -50°C < Ts < 125°C 1kV 260°C 2.2 DC Electrical Characteristics Table 2-1: DC Electrical Characteristics VCC = 3.3V, TA = 0°C to 70°C, unless otherwise shown Parameter Supply Voltage Supply Current Symbol VCC ICC Conditions Operating Range SCO enabled, TA=25°C SCO disabled, TA=25°C SCO enabled, TA=25°C SCO disabled, TA=25°C High Low Min 3.135 – Typ 3.3 215 Max 3.465 260 Units V mA ICC – 195 230 mA Power Consumption – – 710 – mW – – 645 – mW Logic Inputs DDI_SEL[1:0], BYPASS, AUTOBYPASS, AUTO/MAN, ASI/177, DDO_MUTE Logic Outputs SD/HD, LOCKED, LOS Bi-Directional Pins (Manual Mode) SS[2:0], AUTO/MAN = 0 VIH VIL 2.0 – – – – 0.8 V V VOH VOL VIH VIL 250uA Load 250uA Load High Low 2.8 – 2.0 – – – – – – 0.5 – 0.8 V V V V GS1575B / GS9075B HD-LINX® II Multi-Rate SDI Automatic Reclocker Data Sheet 40063 - 1 June 2009 10 of 28 Table 2-1: DC Electrical Characteristics (Continued) VCC = 3.3V, TA = 0°C to 70°C, unless otherwise shown Parameter Bi-Directional Pins (Auto Mode) SS[2:0], AUTO/MAN = 1 XTAL_OUT+, XTAL_OUT- Symbol VOH VOL VOH VOL Conditions High, 250uA Load Low, 250uA Load High Low 1.5mA of current delivered Common Mode Min 2.8 – – – VCC - 0.165 1.65 + (VSID/2) – Typ – – VCC VCC - 0.285 – Max – 0.5 – – VCC + 0.165 VCC - (VSID/2) Units V V V V V SCO_ENABLE – Serial Input Voltage – – V Serial Output Voltage SDO/SDO, SCO/SCO – Common Mode VCC - (VOD/2) – V 2.3 AC Electrical Characteristics Table 2-2: AC Electrical Characteristics VCC = 3.3V, TA = 0°C to 70°C, unless otherwise shown Parameter Serial Input Data Rate Symbol – – Conditions GS1575B GS9075B Worst case modulation (e.g. square wave modulation) 143, 270, 360, 1485 Mb/s Min 143 143 0.8 Typ – – – Max 1485 540 – Units Mb/s Mb/s UI Serial Input Jitter Tolerance – PLL Lock Time - Asynchronous PLL Lock Time - Synchronous tALOCK t S LOCK t S LOCK – CLF=47nF, SD/HD=0 CLF=47nF, SD/HD=1 50Ω load (on chip) 50Ω load (on chip) Differential with internal 100Ω input termination See Figure 2-1 – – – – – 100 – – – 114 106 – 10 10 39 – – 800 ms us us ps ps mVp-p Serial Output Rise/Fall Time SDO/SDO and SCO/SCO (20% - 80%) Serial Digital Input Signal Swing trSDO,trSCO tfSDO,tfSCO VSID Serial Digital Output Signal Swing SDO/SDO and SCO/SCO VOD 100Ω load differential See Figure 2-2 1400 1600 2200 mVp-p GS1575B / GS9075B HD-LINX® II Multi-Rate SDI Automatic Reclocker Data Sheet 40063 - 1 June 2009 11 of 28 Table 2-2: AC Electrical Characteristics (Continued) VCC = 3.3V, TA = 0°C to 70°C, unless otherwise shown Parameter Serial Output Jitter SDO/SDO and SCO/SCO KBB = Float PRN, 223-1 Measurement is output jitter that includes input jitter from BERT. Symbol tOJ tOJ tOJ tOJ tOJ tOJ tOJ Conditions 143 Mb/s 177 Mb/s 270 Mb/s 360 Mb/s 540 Mb/s 1485 Mb/s (GS1575B only) Bypass 1.485 Gb/s, KBB = FLOAT (GS1575B only) 1.485 Gb/s, KBB = GND, 0.25UI), Q-clk will sample a different value than I-clk. In this condition, two extra phase correction signals will be generated which instructs the charge pump to create larger frequency corrections for the VCO. i-PHASE ALIGNMENT EDGE DATA RE-TIMING EDGE I-clk q-clk q-PHASE ALIGNMENT EDGE INPUT DATA WITH JITTER 0.25UI 0.8UI RE-TIMED OUTPUT DATA Figure 4-2: Phase Detector Characteristics When the PA loop is active, the crystal frequency and the incoming data rate are compared. If the resultant is more that 2%, the PLL is considered to be unlocked and the system jumps to the FA loop. GS1575B / GS9075B HD-LINX® II Multi-Rate SDI Automatic Reclocker Data Sheet 40063 - 1 June 2009 18 of 28 4.6 4:1 Input Mux The 4:1 input mux allows the connection of four independent streams of video/data. There are four differential inputs (DDI[3:0] and DDI[3:0]). The active channel can be selected via the DDI_SEL[1:0] pins. Table 4-1 shows the input selected for a given state at DDI_SEL[1:0]. Table 4-1: Bit Pattern for Input Select DDI_SEL[1:0] 00 01 10 11 Selected Input DDI0 DDI1 DDI2 DDI3 The DDI inputs are designed to be DC interfaced with the output of the GS1524A/9064A Cable Equalizer. There are on chip 50Ω termination resistors which come to a common point at the DDI_VT pins. Connect a 10nF capacitor to this pin and connect the other end of the capacitor to ground. This terminates the transmission line at the inputs for optimum performance. If only one input pair is used, connect the unused positive inputs to +3.3V and leave the unused negative inputs floating. This helps to eliminate crosstalk from potential noise that would couple to the unused input pair. 4.7 Automatic and Manual Data Rate Selection The GS1575B/9075B can be configured to manually lock to a specific data rate or automatically search for and lock to the incoming data rate. The AUTO/MAN pin selects automatic data rate detection mode (Auto mode) when HIGH and manual data rate selection mode (Manual mode) when LOW. In Auto mode, the SS[2:0] bi-directional pins become outputs and the bit pattern indicates the data rate that the PLL is locked to (or previously locked to). The "search algorithm" cycles through the data rates and starts over if that data rate is not found (see Figure 4-3). POWER-UP 143 Mb/s 177 Mb/s 270Mb/s 360 Mb/s 1.485Mb/s (GS1575B only) 540 Mb/s Figure 4-3: Data Rate Search Pattern GS1575B / GS9075B HD-LINX® II Multi-Rate SDI Automatic Reclocker Data Sheet 40063 - 1 June 2009 19 of 28 In Manual mode, the SS[2:0] pins become inputs and the data rate can be programmed by the application layer. In this mode, the search algorithm is disabled and the PLL will only lock to the data rate selected. Table 4-2 shows the SS[2:0] pin settings for either the data rate selected (in Manual mode) or the data rate that the PLL has locked to (in Auto mode). Table 4-2: Data Rate Indication/Selection Bit Pattern SS[2:0] 000 001 010 011 100 101* Data Rate (Mb/s) 143 177 270 360 540 1485/1483.5 * This setting only applies to the GS1575B. For the GS9075B, when AUTO/MAN is LOW, the pin settings SS[0:2] = 101 will be ignored by the device. 4.8 Bypass Mode In Bypass mode, the GS1575B/9075B passes the data at the inputs directly to the outputs. There are two pins that control the bypass function: BYPASS and AUTOBYPASS. When BYPASS is set HIGH by the application layer, the GS1575B/9075B will be in Bypass mode. When AUTOBYPASS is set HIGH by the application layer, the GS1575B/9075B will be configured to enter Bypass mode only when the PLL has not locked to a data rate. When BYPASS is set HIGH, AUTOBYPASS will be ignored. When the PLL is not locked, and both BYPASS and AUTOBYPASS are set LOW, the serial digital output DDO/DDO will produce invalid data. GS1575B / GS9075B HD-LINX® II Multi-Rate SDI Automatic Reclocker Data Sheet 40063 - 1 June 2009 20 of 28 4.9 DVB-ASI Operation The GS1575B/9075B will also re-clock DVB-ASI at 270 Mb/s. When reclocking DVB-ASI data set the ASI/177 pin HIGH to prevent a false lock to 177Mb/s. If ASI/177 is not set HIGH, a false lock may occur since there is a harmonic present in idle patterns (K28.5) which is very close the 177 Mb/s data rate (EIC 1179). Note that setting the ASI/177 pin HIGH will disable the 177 Mb/s search when the device is in Auto mode, consequently the GS1575B/9075B will not lock to that data rate. 4.10 Lock and LOS Indicators The LOCKED signal is an active high output which indicates when the PLL is locked. The internal lock logic of the GS1575B/9075B includes a system which monitors the Frequency Acquisition Loop and the Phase Acquisition Loop as well as a monitor to detect harmonic lock. The LOS (Loss of Signal) output is an active HIGH output which indicates the absence of data transitions at the DDIx input. In order for this output to be asserted, transitions must not be present for a period of typically 5.14 us. After this output has been asserted, LOS will deassert typically 5.14 us after the appearance of a transition at the DDIx input. This timing relationship is shown in Figure 4-4: 5.14 us 5.14 us DATA LOS Figure 4-4: LOS signal timing NOTE: LOS is sensitive to transitions appearing at the input, and does not distinguish between transitions caused by input data, and transitions due to noise. GS1575B / GS9075B HD-LINX® II Multi-Rate SDI Automatic Reclocker Data Sheet 40063 - 1 June 2009 21 of 28 4.11 Output Drivers and Serial Clock Outputs The device’s serial digital data outputs (DDO/DDO) have a nominal voltage of 800mv single ended or 1600mV differential when terminated into a 50Ω load. The GS1575B/9075B may also be configured to output a serial clock at the data output rate. The internal serial clock output block is powered via the SCO_ENABLE pin. When SCO_ENABLE is connected to VCC, a differential serial clock output will be present on SCO/SCO. Otherwise, when SCO_ENABLE is connected to GND, the clock output block will be powered down and the device will have reduced power consumption. NOTE: The SCO_ENABLE signal should have a 1.5mA drive strength to maintain a supply voltage of 3.3 +/- 0.165V. Clock and data alignment is shown in Figure 4-5. DATA SCLK For HD-SDI: t CD = 32ps (typ.), 36ps (max.) For SD-SDI: t CD = 30ps (typ.), 38ps (max.) tCD Figure 4-5: Clock and Data Alignment 4.12 Output Mute The DDO_MUTE pin is provided to allow muting of the re-timed output. When the PLL is locked and the device is reclocking, setting DDO_MUTE = LOW will force the serial digital outputs DDO/DDO to mute. However, if the GS1575B/9075B is in Bypass mode, (AUTOBYPASS = HIGH and/or BYPASS = HIGH), DDO_MUTE will have no effect on the output. GS1575B / GS9075B HD-LINX® II Multi-Rate SDI Automatic Reclocker Data Sheet 40063 - 1 June 2009 22 of 28 5. Typical Application Circuits GO1535 (14.140MHz) 47 n 3 . 3V 100 10n 55 64 63 62 61 60 59 58 57 56 54 53 52 51 50 XTAL_OUT + XTAL_OUT- GND XTAL+ XTAL- VC C _C P VE E _C P GND NC NC NC LF+ LF- NC NC NC 49 1 DDI0 D D I 0 _V T DDI0 GND DDI1 D D I 1 _V T DDI1 GND DDI2 D D I 2 _V T DDI2 GND DDI3 D D I 3 _V T DDI3 AUTO/MAN GND DDI_SEL0 DDI_SEL1 B Y PA S S A U T O B Y PA S S VEE_DDO VCC_DDO DDO NC DDO GND VEE_SCO 48 1 0n 47 46 45 44 43 42 1 0n 41 40 3.3V 3 .3 V DATA IN PU T 0 Z o = 50 10 n 2 3 4 5 Zo = 50 D ATA O U T P U T DATA IN PU T 1 Z o = 50 6 10 n 7 8 9 GS1 5 7 5 B VCC_SCO SCO NC SCO GND DDO_MUTE SCO_ENABLE KBB SD/HD 33 SD/HD 39 38 37 36 35 34 SDO_M UT E DATA IN PU T 2 Zo = 50 10 10 n 11 12 13 Z o = 5 0 C L O CK O U T P U T DATA IN PU T 3 Zo = 50 14 10 n 15 16 VCC_VCO VEE_VC0 V C C _ D IG V E E _ D IG 31 3.3V LOCKED ASI/177 17 18 19 20 21 22 23 24 25 26 27 28 29 30 10n D D I _SEL0 D D I _SEL1 A SI _1 7 7 3.3V 10n 32 GND LOS SS0 SS1 SS2 LOS LOCKED Note: All resistors in ohms and all capacitors in Farads. Figure 5-1: GS1575B Typical Application Circuit GS1575B / GS9075B HD-LINX® II Multi-Rate SDI Automatic Reclocker Data Sheet 40063 - 1 June 2009 23 of 28 GO 1 5 3 5 ( 1 4 . 1 4 0 M Hz ) 47n 3.3V 100 10n 55 64 63 62 61 60 59 58 57 56 54 53 52 51 50 X TA L _ OU T + X TA L _ OU T- GND X TA L + X TA L - V CC_ CP V E E _ CP GND NC NC NC LF+ LF- NC NC NC 49 1 DDI0 D D I 0 _VT DDI0 GND DDI1 D D I 1 _VT DDI1 GND DDI2 D D I 2 _VT DDI2 GND DDI3 D D I 3 _VT DDI3 AUT O / M AN GND DDI _ S E L 0 DDI _ S E L 1 B Y PAS S AUT O B Y PAS S V E E _ DDO V C C _ DDO DDO NC DDO GND VEE_SCO 48 1 0n 47 46 45 44 43 42 1 0n 41 40 3.3V 3.3V DATA IN P U T 0 Zo = 50 10n 2 3 4 5 Zo = 50 DATA OUTPUT DATA IN P U T 1 Zo = 50 6 10n 7 8 9 GS9075B VCC_SCO SCO NC SCO GND DDO _ M UT E S C O _ E NAB L E KBB SD 33 SD 39 38 37 36 35 34 SDO_MUTE DATA IN P U T 2 Zo = 50 10 10n 11 12 13 Z o = 5 0 CLOCK OUTPUT DATA IN P U T 3 Zo = 50 14 10n 15 16 VCC_VCO VEE_VC0 V C C _ DI G V E E _ DI G 31 3.3V LOCKED AS I / 1 7 7 17 18 19 20 21 22 23 24 25 26 27 28 29 30 10n D D I _SE L0 D D I _SE L1 A SI _1 7 7 3.3V 10n 32 GND LOS SS0 SS1 SS2 LOS LOCKED Note: All resistors in ohms and all capacitors in Farads. Figure 5-2: GS9075B Typical Application Circuit GS1575B / GS9075B HD-LINX® II Multi-Rate SDI Automatic Reclocker Data Sheet 40063 - 1 June 2009 24 of 28 6. Package & Ordering Information 6.1 Package Dimensions 0.40+/-0.05 9.00 4.50 A B 7.10+/-0.15 3.55 45° 45 ° 4.50 9.00 PIN 1 AREA CENTRE TAB 2X 0.15 C 0.20 REF 2X 0.10 C 0.15 C 0.25+/-0.05 0.50 64X C CAB 0.10 C 0.05 64X 0.08 C 0.90 +/- 0.10 +0.03 0.02-0.02 SEATING PLANE ALL DIMENSIONS IN MM GS1575B / GS9075B HD-LINX® II Multi-Rate SDI Automatic Reclocker Data Sheet 40063 - 1 June 2009 25 of 28 3.55 7.10+/-0.15 6.2 Recommended PCB Footprint 0.50 0.25 0.55 CENTER PAD 8.70 7.10 7.10 8.70 NOTE: All dimensions are in millimeters. The center pad of the PCB footprint should be connected to the ground plane by a minimum of 36 vias. NOTE: Suggested dimensions only. Final dimensions should conform to customer design rules and process optimizations. 6.3 Packaging Data Parameter Package Type Moisture Sensitivity Level Junction to Case Thermal Resistance, θj-c Junction to Air Thermal Resistance, θj-a (at zero airflow) Psi, Ψ Pb-free and RoHS Compliant Value 9mm x 9mm 64-pin QFN 3 9.1°C/W 21.5°C/W 0.2°C/W Yes GS1575B / GS9075B HD-LINX® II Multi-Rate SDI Automatic Reclocker Data Sheet 40063 - 1 June 2009 26 of 28 6.4 Solder Reflow Profiles The device is manufactured with Matte-Sn terminations and is compatible with both standard eutectic and Pb-free solder reflow profiles. MSL qualification was performed using the maximum Pb-free solder reflow profile shown in Figure 6-1. The recommended standard Pb solder reflow profile is shown in Figure 6-2. Temperature 60-150 se c . 20-40 se c . 260°C 250°C 3 °C/se c m ax 217°C 6°C/se c m ax 200°C 150°C 25°C Time 60-180 se c . max 8 min. max Figure 6-1: Maximum Pb-free Solder Reflow Profile (Preferred) Temperature 60-150 se c . 10-20 se c . 230°C 220°C 3 °C/se c m ax 183°C 6°C/se c m ax 150°C 100°C 25°C Time 120 se c . max 6 min. max Figure 6-2: Standard Pb Solder Reflow Profile GS1575B / GS9075B HD-LINX® II Multi-Rate SDI Automatic Reclocker Data Sheet 40063 - 1 June 2009 27 of 28 6.5 Ordering Information Part Number GS1575B GS9075B GS1575BCNE3 GS9075BCNE3 Package Pb-free 64-pin QFN Pb-free 64-pin QFN Temperature Range 0°C to 70°C 0°C to 70°C DOCUMENT IDENTIFICATION CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DATA SHEET The product is in production. Gennum reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. GENNUM CORPORATE HEADQUARTERS 4281 Harvester Road, Burlington, Ontario L7L 5M4 Canada Phone: +1 (905) 632-2996 E-mail: corporate@gennum.com Fax: +1 (905) 632-2055 www.gennum.com OTTAWA 232 Herzberg Road, Suite 101 Kanata, Ontario K2K 2A1 Canada Phone: +1 (613) 270-0458 Fax: +1 (613) 270-0429 SNOWBUSH IP - A DIVISION OF GENNUM 439 University Ave. Suite 1700 Toronto, Ontario M5G 1Y8 Canada Phone: +1 (416) 925-5643 Fax: +1 (416) 925-0581 E-mail: sales@snowbush.com Web Site: http://www.snowbush.com GERMANY Hainbuchenstraße 2 80935 Muenchen (Munich), Germany Phone: +49-89-35831696 Fax: +49-89-35804653 E-mail: gennum-germany@gennum.com CALGARY 3553 - 31st St. N.W., Suite 210 Calgary, Alberta T2L 2K7 Canada Phone: +1 (403) 284-2672 NORTH AMERICA WESTERN REGION Bayshore Plaza 2107 N 1st Street, Suite #300 San Jose, CA 95131 United States Phone: +1 (408) 392-9454 Fax: +1 (408) 392-9427 E-mail: naw_sales@gennum.com MEXICO 288-A Paseo de Maravillas Jesus Ma., Aguascalientes Mexico 20900 Phone: +1 (416) 848-0328 UNITED KINGDOM North Building, Walden Court Parsonage Lane, Bishop’s Stortford Hertfordshire, CM23 5DB United Kingdom Phone: +44 1279 714170 Fax: +44 1279 714171 JAPAN KK Shinjuku Green Tower Building 27F 6-14-1, Nishi Shinjuku Shinjuku-ku, Tokyo, 160-0023 Japan Phone: +81 (03) 3349-5501 Fax: +81 (03) 3349-5505 E-mail: gennum-japan@gennum.com Web Site: http://www.gennum.co.jp NORTH AMERICA EASTERN REGION 4281 Harvester Road Burlington, Ontario L7L 5M4 Canada Phone: +1 (905) 632-2996 Fax: +1 (905) 632-2055 E-mail: nae_sales@gennum.com INDIA #208(A), Nirmala Plaza, Airport Road, Forest Park Square Bhubaneswar 751009 India Phone: +91 (674) 653-4815 Fax: +91 (674) 259-5733 KOREA 8F Jinnex Lakeview Bldg. 65-2, Bangidong, Songpagu Seoul, Korea 138-828 Phone: +82-2-414-2991 Fax: +82-2-414-2998 E-mail: gennum-korea@gennum.com TAIWAN 6F-4, No.51, Sec.2, Keelung Rd. Sinyi District, Taipei City 11502 Taiwan R.O.C. Phone: (886) 2-8732-8879 Fax: (886) 2-8732-8870 E-mail: gennum-taiwan@gennum.com Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. All other trademarks mentioned are the properties of their respective owners. GENNUM and the Gennum logo are registered trademarks of Gennum Corporation. © Copyright 2006 Gennum Corporation. All rights reserved. www.gennum.com GS1575B / GS9075B HD-LINX® II Multi-Rate SDI Automatic Reclocker Data Sheet 40063 - 1 June 2009 28 of 28 28