GS1582-IBE3

GS1582 Multi-Rate Serializer with Cable Driver, Audio Multiplexer and ClockCleaner™ GS1582 Data Sheet Key Features • • • • HD-SDI, SD-SDI, DVB-ASI transmitter with audio embedding Integrated SMPTE 292M and 259M-C compliant cable driver Integrated ClockCleaner™ User selectable video processing features, including: • • • • • • • • • • Generic ancillary data insertion Support for HVF or EIA/CEA-861 timing input Automatic standard detection and indication Enhanced SMPTE 352M payload identifier generation and insertion TRS, CRC, ANC data checksum, and line number calculation and insertion EDH packet generation and insertion Illegal code remapping SMPTE 292M and SMPTE 259M-C compliant scrambling and NRZ → NRZI encoding Blanking of input HANC and VANC space Description The GS1582 is the next generation multi-standard serializer with an integrated cable driver. The device provides robust parallel to serial conversion, generating a SMPTE 292M/259M-C compliant serial digital output signal. The integrated cable driver features an output disable (high impedance) mode and an adjustable signal swing. Data input is accepted in 20-bit parallel format or 10-bit parallel format. An associated parallel clock input must be provided at the appropriate operating frequency; 74.25/74.1758/13.5MHz (20-bit mode) or 148.5/148.352/27MHz (10-bit mode). The GS1582 features an internal PLL which, if desired, can be configured for a loop bandwidth below 100kHz. When used in conjunction with the GO1555 Voltage Controlled Oscillator, the GS1582 can tolerate well in excess of 300ps jitter on the input PCLK and still provide output jitter within SMPTE specifications. In addition to serializing the input, the GS1582 performs NRZ-to-NRZI encoding and scrambling as per SMPTE 292M/259M-C when operating in SMPTE mode. When operating in DVB-ASI mode, the device will insert K28.5 sync characters and 8b/10b encode the data prior to serialization. The device also provides a range of other data processing functions. All processing features are optional and may be enabled/disabled via external control pin(s) and/or host interface programming. The GS1582 can embed up to 8 channels of audio into the video data stream in accordance with SMPTE 299M and SMPTE 272M. The audio input signal formats supported by the device include AES/EBU and I2S serial digital formats with a 16, 20 or 24 bit sample size and a 48 kHz sample rate. Additional audio processing features include individual channel enable, channel swap, group swap, ECC generation and audio channel status insertion. Typical power consumption, including the GO1555 VCO, is 500mW. The standby feature allows the power to be reduced to 125mW. Power may be reduced to less than 10mW by also removing the power to the cable driver and eliminating transitions at the parallel data and clock inputs. The GS1582 is Pb-free and RoHS compliant. User selectable audio processing features, including: • • • SMPTE 299M and SMPTE 272M-A/C compliant audio embedding Support for up to 8 channels Support for audio group replacement • • • • • • JTAG test interface 1.8V core and 3.3V charge pump power supply 1.8V and 3.3V digital I/O support Low power standby mode Operating temperature range: -20oC to +85oC Pb-free, RoHS compliant, 11mm x 11mm 100-ball BGA package Applications • • SMPTE 292M and SMPTE 259M-C Serial Digital Interfaces DVB-ASI Serial Digital Interfaces 40117 - 1 November 2007 1 of 114 www.gennum.com GS1582 Data Sheet Functional Block Diagram SDOUT_TDO SDIN_TDI SCLK_TCLK CS_TMS DVB_ASI Host Interface AUDIO_INT GRP1_EN/DIS GRP2_EN/DIS Ain_1/2 Ain_3/4 Ain_5/6 Ain_7/8 ACLK1 ACLK2 WCLK1 WCLK2 F/DE V/VSYNC H/HSYNC TIM_861 DIN[19:0] PCLK GSPI SD/HD Audio Embedding Input Mux/ Demux HANC/ VANC Blanking RSET SMPTE 352M Generation and Insertion ANC Data Insertion TRS, Line Number and CRC Insertion EDH Packet Insertion NRZ/NRZI SMPTE SCRAMBLER Mux Parallel to Serial Converter SMPTE Cable Driver SDO SDO SDO_EN/DIS DVB ASI ENDEC PhaseDetector/ Chargepump 2.5V Regulator LOCKED ClockCleaner™ VCO_GND VCO_VCC VCO LF CP_RES GS1582 Functional Block Diagram 40117 - 1 November 2007 2 of 114 GS1582 Data Sheet Contents Key Features .................................................................................................................1 Applications...................................................................................................................1 Description ....................................................................................................................1 Functional Block Diagram .............................................................................................2 1. Pin Out ......................................................................................................................7 1.1 Pin Assignment ...............................................................................................7 1.2 Pin Descriptions ..............................................................................................8 2. Electrical Characteristics .........................................................................................17 2.1 Absolute Maximum Ratings ..........................................................................17 2.2 Recommended Operating Conditions ...........................................................17 2.3 DC Electrical Characteristics ........................................................................18 2.4 AC Electrical Characteristics .........................................................................19 2.5 Solder Reflow Profiles ...................................................................................21 3. Input/Output Circuits ...............................................................................................22 4. Detailed Description ................................................................................................25 4.1 Functional Overview .....................................................................................25 4.2 Parallel Data Inputs .......................................................................................26 4.2.1 Parallel Input in SMPTE Mode.............................................................26 4.2.2 Parallel Input in DVB-ASI Mode...........................................................26 4.2.3 Parallel Input in Data-Through Mode...................................................27 4.2.4 Parallel Input Clock (PCLK) .................................................................27 4.3 SMPTE Mode ................................................................................................28 4.3.1 HVF Timing..........................................................................................28 4.3.2 CEA 861 Timing...................................................................................29 4.4 DVB-ASI mode ..............................................................................................34 4.4.1 Control Signal Inputs ...........................................................................34 4.5 Data-Through Mode ......................................................................................35 4.6 Standby Mode ...............................................................................................35 4.7 Audio Multiplexer ..........................................................................................36 4.7.1 Audio Core Configurations...................................................................36 4.7.2 Audio Detection ...................................................................................37 4.7.3 Audio Modes of Operation ...................................................................38 4.7.4 Audio Packet Delete ............................................................................39 4.7.5 Arbitrary, SMPTE 352M & EDH Packet Detect ...................................40 4.7.6 Audio Packet Multiplexing....................................................................41 4.7.7 Audio Insertion After Video Switching Point ........................................41 4.7.8 Audio Data Packets .............................................................................42 4.7.9 Audio Control Packets .........................................................................45 4.7.10 Setting Packet DID ............................................................................47 4.7.11 Audio Group Replacement ................................................................48 40117 - 1 November 2007 3 of 114 GS1582 Data Sheet 4.7.12 Channel and Group Activation...........................................................50 4.7.13 ECC Error Detection & Correction (HD Mode Only) ..........................50 4.7.14 Interrupt Control.................................................................................50 4.7.15 Audio Clocks ......................................................................................50 4.7.16 5-frame Sequence Detection .............................................................51 4.7.17 Audio Input Format ............................................................................52 4.7.18 Audio Channel Status Input ...............................................................55 4.7.19 Audio Crosspoint ...............................................................................56 4.7.20 Audio Word Clock ..............................................................................57 4.7.21 GS1582 SD Audio FIFO Block ..........................................................58 4.7.22 Audio Sample Distributions................................................................59 4.7.23 Audio Mute.........................................................................................62 4.8 Ancillary Data Insertion .................................................................................62 4.8.1 Ancillary Data Insertion Operating Mode .............................................63 4.8.2 HANC Insertion....................................................................................64 4.8.3 VANC Insertion ....................................................................................65 4.9 Additional Processing Functions ...................................................................65 4.9.1 ANC Data Blanking..............................................................................65 4.9.2 Automatic Video Standard Detection...................................................65 4.9.3 Video Standard Indication....................................................................66 4.9.4 Packet Generation and Insertion .........................................................68 4.10 Parallel to Serial Conversion .......................................................................73 4.11 Internal ClockCleanerTM PLL ......................................................................74 4.11.1 External VCO .....................................................................................74 4.11.2 Loop Filter..........................................................................................74 4.11.3 Lock Detect Output ............................................................................75 4.12 Serial Digital Output ....................................................................................76 4.12.1 Output Swing .....................................................................................76 4.13 GSPI Host Interface ....................................................................................76 4.13.1 Command Word Description..............................................................78 4.13.2 Data Read and Write Timing .............................................................78 4.13.3 Configuration and Status Registers ...................................................80 4.14 JTAG Test Operation ................................................................................105 4.15 Device Reset .............................................................................................107 5. Application Reference Design ...............................................................................108 5.1 Typical Application Circuit (Part A) .............................................................108 5.2 Typical Application Circuit (Part B) .............................................................109 6. References & Relevant Standards ........................................................................110 7. Package & Ordering Information ...........................................................................111 7.1 Package Dimensions ..................................................................................111 7.2 Marking Diagram .........................................................................................112 7.3 Packaging Data ...........................................................................................112 7.4 Ordering Information ...................................................................................112 8. Revision History ....................................................................................................113 40117 - 1 November 2007 4 of 114 GS1582 Data Sheet List of Figures Figure 2-1: Maximum Pb-free Solder Reflow Profile ..................................................21 Figure 3-1: Differential Output Stage (SDO/SDO) .....................................................22 Figure 3-2: Charge Pump Current Setting Resistor (CP_RES) ..................................22 Figure 3-3: PLL Loop Filter ........................................................................................23 Figure 3-4: VCO Input ................................................................................................23 Figure 3-5: Digital Input Pin with Weak Pull Up(>33kW) (ACLK[2:1], WCLK[2:1], AIN[4:1], PCLK, DIN[19:0]) .................................................24 Figure 3-6: 5V Tolerant Input Pin (All Other Input Pins) .............................................24 Figure 3-7: Digital Output Pin with High Impedance Mode (LOCKED, AUDIO_INT, SDOUT_TDO) .....................................................................24 Figure 4-1: PCLK to Data Timing ...............................................................................26 Figure 4-2: H_Blanking, V_Blanking, F_Digital Timing ..............................................29 Figure 4-3: HSYNC:VSYNC:DE Input Timing 1280 x 720p @ 59.94/60 ....................31 Figure 4-4: HSYNC:VSYNC:DE Input Timing 1920 x 1080i @ 59.94/60 ...................31 Figure 4-5: HSYNC:VSYNC:DE Input Timing 720 (1440) x 480i @ 59.94/60 ...........32 Figure 4-6: HSYNC:VSYNC:DE Input Timing 1280 x 720p @ 50 ..............................33 Figure 4-7: HSYNC:VSYNC:DE Input Timing 1920 x 1080i @ 50 .............................33 Figure 4-8: HSYNC:VSYNC:DE Input Timing 720 (1440) x 576 @ 50 ......................34 Figure 4-9: DVB-ASI FIFO Implementation using the GS1582 ..................................35 Figure 4-10: Audio Multiplexer Top Level ..................................................................37 Figure 4-11: Ancillary Data Packet Placement Example ............................................39 Figure 4-12: SD Audio Data Packet Structure ...........................................................42 Figure 4-13: SD Extended Audio Data Packet Structure ...........................................43 Figure 4-14: HD Audio Data Packet Structure ...........................................................43 Figure 4-15: SD Audio Control Packet Structure .......................................................45 Figure 4-16: HD Audio Control Packet Structure .......................................................46 Figure 4-17: Audio Group Replacement Example (HD Formats) ...............................49 Figure 4-18: ACLK to Data & Control Signal Input Timing .........................................51 Figure 4-19: AES/EBU Sub-frame Formatting ...........................................................54 Figure 4-20: AES/EBU Audio Input Format ................................................................54 Figure 4-21: Serial Audio Input: Left Justified; MSB First ..........................................54 Figure 4-22: Serial Audio Input: Left Justified; LSB First ...........................................55 Figure 4-23: Serial Audio Input: Right Justified; MSB First ........................................55 Figure 4-24: Serial Audio Input: Right Justified; LSB First .........................................55 Figure 4-25: I2S Audio Input .......................................................................................55 Figure 4-26: Gennum Serial Peripheral Interface (GSPI) ..........................................77 Figure 4-27: Command Word .....................................................................................78 Figure 4-28: Data Word ..............................................................................................78 Figure 4-29: GSPI Read Mode Timing .......................................................................79 Figure 4-30: GSPI Write Mode Timing .......................................................................79 Figure 4-31: In-Circuit JTAG ....................................................................................106 Figure 4-32: System JTAG .......................................................................................106 Figure 4-33: Reset Pulse .........................................................................................107 40117 - 1 November 2007 5 of 114 GS1582 Data Sheet List of Tables Table 1-1: Pin Descriptions .......................................................................................... 8 Table 2-1: Recommended Operating Conditions ....................................................... 17 Table 2-2: DC Electrical Characteristics .................................................................... 18 Table 2-3: AC Electrical Characteristics..................................................................... 19 Table 4-1: Parallel Data Input Format ........................................................................ 27 Table 4-2: Standby Power Consumption ................................................................... 36 Table 4-3: Audio Multiplexer Modes of Operation ...................................................... 39 Table 4-4: Non-audio Ancillary Data Packet DIDs ..................................................... 40 Table 4-5: Audio Data Packet Word Descriptions ...................................................... 42 Table 4-6: Extended Audio Data Packet Word Descriptions...................................... 43 Table 4-7: Audio Data Packet Word Descriptions ...................................................... 44 Table 4-8: Audio Control Packet Word Descriptions .................................................. 45 Table 4-9: Audio Control Packet Word Descriptions .................................................. 46 Table 4-10: Audio Group DID Host Interface Settings ............................................... 48 Table 4-11: Audio Data and Control Packet DID Setting Register ............................. 48 Table 4-12: GS1582 Serial Audio Data Inputs ........................................................... 51 Table 4-13: Frame Rates with AFN = 0...................................................................... 52 Table 4-14: Frame Rates with varying samples per frame ........................................ 52 Table 4-15: Audio Input Formats................................................................................ 53 Table 4-16: Audio Channel Status Block Default Settings ......................................... 56 Table 4-17: Audio Channel Status Information Register Settings .............................. 56 Table 4-18: Audio Channel Mapping Codes .............................................................. 57 Table 4-19: Source Input Address Registers ............................................................. 57 Table 4-20: Audio Clock Selection Host Interface Settings........................................ 58 Table 4-21: Audio Buffer Pointer Offset Settings ....................................................... 59 Table 4-22: 5-frame Sequence Sample Distribution .................................................. 59 Table 4-23: Group 1 Audio Sample Distribution......................................................... 60 Table 4-24: Group 2 Audio Sample Distribution......................................................... 60 Table 4-25: Group 3 Audio Sample Distribution......................................................... 60 Table 4-26: Group 4 Audio Sample Distribution......................................................... 60 Table 4-27: Group 1 Audio Sample Distribution......................................................... 61 Table 4-28: Group 2 Audio Sample Distribution......................................................... 61 Table 4-29: Group 3 Audio Sample Distribution......................................................... 61 Table 4-30: Group 4 Audio Sample Distribution......................................................... 61 Table 4-31: Synchronous Audio Sample Distributions ............................................... 62 Table 4-32: Host Interface Description for Video Standard Register ......................... 66 Table 4-33: Host Interface Description for Raster Structure Registers ..................... 66 Table 4-34: Supported Video Standards.................................................................... 67 Table 4-35: Host Interface Description for Internal Processing Disable Register ...... 69 Table 4-36: Host Interface Description for SMPTE 352M Packet Line Number Insertion Registers ..................................................................................................... 70 Table 4-37: Host Interface Description for SMPTE 352M Payload Identifier Registers .................................................................................................................... 70 Table 4-38: Host Interface Description for EDH Flag Register (SD Mode Only)........ 72 Table 4-39: Serial Digital Output Rates...................................................................... 74 Table 4-40: Loop Filter Component Values ............................................................... 75 Table 4-41: GSPI Timing Parameters ........................................................................ 79 Table 4-42: GS1582 Internal Registers...................................................................... 80 Table 4-43: Video Configuration and Status Registers .............................................. 81 Table 4-44: SD Audio Configuration and Status Registers ........................................ 88 Table 4-45: HD Audio Configuration and Status Registers ........................................ 98 40117 - 1 November 2007 6 of 114 GS1582 Data Sheet 1. Pin Out 1.1 Pin Assignment 1 A B C D E F G H J K DIN17 2 DIN18 3 F/DE 4 H/HSYNC 5 CORE _VDD 6 PD_VDD 7 LF 8 VCO_ VCC 9 VCO 10 CP_VDD DIN15 DIN16 DIN19 PCLK CORE _GND PD_VDD CP_RES VCO_ GND VCO_ GND CP_GND DIN13 DIN14 DIN12 V/VSYNC CORE _GND PD_GND PD_GND PD_GND CD_GND SDO DIN11 DIN10 STANDBY SDO_EN/ DIS CORE _GND NC NC NC CD_GND SDO CORE _VDD CORE _GND SD/HD NC CORE _GND CORE _GND CORE _GND NC CD_GND CD_VDD DIN9 DIN8 DETECT _TRS RSV CORE _GND CORE _GND CORE _GND NC CD_GND RSET IO_VDD IO_GND TIM 861 20bit/ 10bit DVB_ASI SMPTE_ IOPROC BYPASS _EN/DIS GRP2_ EN/DIS GRP1_ EN/DIS AUDIO _INT RESET CORE _GND CORE _VDD DIN7 DIN6 ANC_ BLANK LOCKED JTAG/ HOST CORE _GND IO_GND IO_VDD DIN5 DIN4 DIN1 Ain_5/6 WCLK_2 Ain_1/2 WCLK_1 SDOUT _TDO SCLK _TCLK SDIN _TDI DIN3 DIN2 DIN0 Ain_7/8 ACLK_2 Ain_3/4 ACLK_1 CORE _VDD CS_ TMS 40117 - 1 November 2007 7 of 114 GS1582 Data Sheet 1.2 Pin Descriptions Table 1-1: Pin Descriptions Pin Number A1, A2, B1, B2, B3, C1, C2, C3, D1, D2 Name DIN[19:10] Timing Synchronous with PCLK Type Input Description PARALLEL DATA BUS Signal levels are LVCMOS/LVTTL compatible. DIN19 is the MSB and DIN10 is the LSB. HD 20-bit mode SD/HD = LOW 20bit/10bit = HIGH Luma data input in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data input in Data-Through mode SMPTE_BYPASS = LOW DVB_ASI = LOW HD 10-bit mode SD/HD = LOW 20bit/10bit = LOW Multiplexed Luma and Chroma data input in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data input in Data-Through mode SMPTE_BYPASS = LOW DVB_ASI = LOW SD 20-bit mode SD/HD = HIGH 20bit/10bit = HIGH Luma data input in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data input in Data-Through mode SMPTE_BYPASS = LOW DVB_ASI = LOW DVB-ASI data input in DVB-ASI mode SMPTE_BYPASS = LOW DVB_ASI = HIGH SD 10-bit mode SD/HD = HIGH 20bit/10bit = LOW Multiplexed Luma and Chroma data input in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data input in data through mode SMPTE_BYPASS = LOW DVB_ASI = LOW DVB-ASI data input in DVB-ASI mode SMPTE_BYPASS = LOW DVB_ASI = HIGH 40117 - 1 November 2007 8 of 114 GS1582 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number A3 Name F/DE Timing Synchronous with PCLK Type Input Description PARALLEL DATA TIMING Signal levels are LVCMOS/LVTTL compatible. TIM_861 = LOW: Used to indicate the ODD / EVEN field of the video signal when DETECT_TRS is set LOW. The device will set the F bit in all outgoing TRS signals for the entire period that the F input signal is HIGH (IOPROC_EN/DIS must also be HIGH). The F signal should be set HIGH for the entire period of field 2 and should be set LOW for all lines in field 1 and for all lines in progressive scan systems. The F signal is ignored when DETECT_TRS = HIGH. TIM_861 = HIGH: The DE signal is used to indicate the active video period. DE is HIGH for active data and LOW for blanking. See Section 4.3.1 and Section 4.3.2 for timing details. The DE signal is ignored when DETECT_TRS = HIGH. A4 H/HSYNC Synchronous with PCLK Input PARALLEL DATA TIMING Signal levels are LVCMOS/LVTTL compatible. TIM_861 = LOW: The H signal is used to indicate the portion of the video line containing active video data, when DETECT_TRS is set low. Active Line Blanking The H signal should be set HIGH for the entire horizontal blanking period, including the EAV and SAV TRS words, and LOW otherwise. This is the default setting. TRS Based Blanking (H_CONFIG = 1h) The H signal should be set HIGH for the entire horizontal blanking period as indicated by the H bit in the received TRS ID words, and LOW otherwise. The H signal is ignored when DETECT_TRS = HIGH. TIM_861 = HIGH: The HSYNC signal indicates horizontal timing. See Section 4.3.1 for timing details. The HSYNC signal is ignored when DETECT_TRS = HIGH. A5, E1, G10, K8 A6, B6 A7 A8 A9 A10 CORE_VDD PD_VDD LF VCO_VCC VCO CP_VDD Non Synchronous Analog Analog Analog Analog Analog Input Power Input Power Input Output Power Input Input Power Power supply connection for the digital core logic. Connect to +1.8V DC digital. Power supply connection for the phase detector. Connect to +1.8V DC analog. PLL loop filter connection. Power supply for the external voltage controlled oscillator. 2.5V DC supplied by the device to the external VCO. Input from external VCO. Power supply connection for the charge pump and on chip VCO regulator. Connect to +3.3V DC analog. 40117 - 1 November 2007 9 of 114 GS1582 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number B4 Name PCLK Timing – Type Input Description PARALLEL DATA BUS CLOCK Signal levels are LVCMOS/LVTTL compatible. HD 20-bit mode HD 10-bit mode SD 20-bit mode SD 10-bit mode PCLK = 74.25MHz or 74.25/1.001MHz PCLK = 148.5MHz or 148.5/1.001MHz PCLK = 13.5MHz PCLK = 27MHz B5, C5, D5, E2, E5, E6, E7, F5, F6, F7, G9, J8 C6, C7, C8 B7 B8, B9 B10 C4 CORE_GND Non Synchronous Input Power Ground connection for the digital core logic. Connect to digital GND. PD_GND CP_RES VCO_GND CP_GND V/VSYNC Analog – Analog Analog Synchronous with PCLK Input Power Input Output Power Input Power Input Ground connection for the phase detector. Connect to analog GND. Charge pump current setting resistor. Ground pins for the VCO. Ground pin for the charge pump and PLL. PARALLEL DATA TIMING Signal levels are LVCMOS/LVTTL compatible. TIM_861 = LOW: The V signal is used to indicate the portion of the video field/frame that is used for vertical blanking, when DETECT_TRS is set LOW. The V signal should be set HIGH for the entire vertical blanking period and should be set LOW for all lines outside of the vertical blanking interval. The V signal is ignored when DETECT_TRS = HIGH. TIM_861 = HIGH: The VSYNC signal indicates vertical timing. See Section 4.3.1 for timing details. The VSYNC signal is ignored when DETECT_TRS = HIGH. C9, D9, E9, F9 C10, D10 CD_GND SDO, SDO Analog Analog Input Power Output Ground connection for the serial digital cable driver. Connect to analog GND. Serial digital output signal operating at 1.485Gb/s, 1.485/1.001Gb/s, or 270Mb/s. The slew rate of these outputs is automatically controlled to meet SMPTE 292M and 259M requirements according to the setting of the SD/HD pin. Serial digital output signal from the internal cable driver. NOTE: The SDO/SDO output signals will be set to high impedance when RESET = LOW. 40117 - 1 November 2007 10 of 114 GS1582 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number D3 Name STANDBY Timing Non Synchronous Type Input Description CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Power down input. When set HIGH, the device will be in standby mode. D4 SDO_EN/DIS Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to enable or disable the serial digital output stage. When set LOW, the serial digital output signals SDO and SDO are disabled and become high impedance. When set HIGH, the serial digital output signals SDO and SDO are enabled. The SDO and SDO outputs will also be high impedance when the RESET pin is LOW. D6, D7, D8, E4, E8, F8 E3 NC SD/HD – Non Synchronous – Input No connect. Not connected internally. CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. When set LOW, the device will be configured to transmit signals of 1.485Gb/s - 1.485/1.001Gb/s rates only. When set HIGH, the device will be configured to transmit signals of a 270Mb/s rate only. E10 F1, F2, H1, H2, J1, J2, J3, K1, K2, K3 CD_VDD DIN[9:0] Analog Synchronous with PCLK Input Power Input Power supply connection for the serial digital cable driver. Connect to +3.3V DC analog. PARALLEL DATA BUS Signal levels are LVCMOS/LVTTL compatible. DIN9 is the MSB and DIN0 is the LSB. HD 20-bit mode SD/HD = LOW 20bit/10bit = HIGH Chroma data input in SMPTE mode SMPTE_BYPASS =HIGH DVB_ASI = LOW Data input in Data-Through mode SMPTE_BYPASS = LOW DVB_ASI = LOW HD 10-bit mode SD/HD = LOW 20bit/10bit = LOW SD 20-bit mode SD/HD = HIGH 20bit/10bit = HIGH High impedance in all modes. Chroma data input in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data input in Data-Through mode SMPTE_BYPASS = LOW DVB_ASI = LOW Forced low in DVB-ASI mode SMPTE_BYPASS = LOW DVB_ASI = HIGH SD 10-bit mode SD/HD = HIGH 20bit/10bit = LOW High impedance in all modes. 40117 - 1 November 2007 11 of 114 GS1582 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number F3 Name DETECT_TRS Timing Non Synchronous Type Input Description CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to select external HVF timing mode or TRS Extraction timing mode. When DETECT_TRS = LOW, the device will use timing from the externally supplied H:V:F or CEA-861 timing signals, dependent on the state of the TIM_861 pin. When DETECT_TRS = HIGH, the device will extract timing from TRS signals embedded in the supplied video stream. F4 F10 G1, H10 G2, H9 G3 RSV RSET IO_VDD IO_GND TIM_861 – Analog Non Synchronous Non Synchronous Non Synchronous – Input Input Power Input Power Input Reserved. Do not connect. An external 1% resistor connected to this input is used to set the SDO/SDO output amplitude. Power supply connection for digital I/O buffers. Connect to +3.3V or +1.8V DC digital. Ground connection for digital I/O buffers. Connect to digital GND. CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to select external CEA-861 timing mode. When DETECT_TRS = LOW and TIM_861 = LOW, the device will use externally supplied H:V:F timing signals. When DETECT_TRS = LOW and TIM_861 = HIGH, the device will use externally supplied HSYNC, VSYNC, DE timing signals. When DETECT_TRS = HIGH, the device will extract timing from TRS signals embedded in the supplied video stream. G4 20bit/10bit Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to select the input data bus width. G5 DVB_ASI Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. When set HIGH, the device is configured for the transmission of DVB-ASI data in SD mode (SD/HD = HIGH). When set LOW, the device will not support the encoding of DVB-ASI data. NOTE: When operating in DVB-ASI mode the SD/HD pin must be set HIGH and SMPTE_BYPASS must be set LOW. 40117 - 1 November 2007 12 of 114 GS1582 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number G6 Name SMPTE_BYPASS Timing Non Synchronous Type Input Description CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to enable/disable all forms of encoding/decoding, scrambling and EDH insertion. When set LOW, the device will operate in data through mode (DVB_ASI = LOW), or in DVB-ASI mode (DVB_ASI = HIGH). No SMPTE scrambling will take place and none of the I/O processing features of the device will be available when SMPTE_BYPASS is set LOW. When set HIGH, the device will perform SMPTE scrambling and I/O processing. G7 IOPROC_EN/DIS Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to enable or disable I/O processing features. When set HIGH, the following I/O processing features of the device are enabled: • Audio Embedding • EDH Packet Generation and Insertion (SD-only) • SMPTE 352M Packet Generation and Insertion • ANC Data Checksum Calculation • ANC Data Insertion • Line-based CRC Generation and Insertion (HD-only) • Line Number Generation and Insertion (HD-only) • TRS Generation and Insertion • Illegal Code Remapping To enable a subset of these features, set IOPROC_EN/DIS = HIGH and disable the individual feature(s) in the IOPROC_DISABLE register accessible via the host interface. When set LOW, the I/O processing features of the device are disabled, and can not be enabled by changing the settings in the IOPROC_DISABLE register. G8 RESET Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to reset the internal operating conditions to default settings and to reset the JTAG test sequence. Normal Mode (JTAG/HOST = LOW) When set LOW, all functional blocks will be set to default conditions and all input and output signals become high impedance including the serial digital outputs SDO and SDO. When set HIGH, normal operation of the device resumes 10usec after the low to high transition of the RESET signal. JTAG Test Mode (JTAG/HOST = HIGH) When set LOW, all functional blocks will be set to default and the JTAG test sequence will be held in reset. When set HIGH, normal operation of the JTAG test sequence resumes. 40117 - 1 November 2007 13 of 114 GS1582 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number H3 Name ANC_BLANK Timing Non Synchronous Type Input Description CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to enable or disable ANC data blanking. When set LOW, the HANC and VANC data is mapped to the appropriate blanking levels. H4 LOCKED Synchronous with PCLK Output STATUS SIGNAL OUTPUT Signal levels are LVCMOS / LVTTL compatible. This signal is set HIGH by the device when the internal PLL has achieved lock to the supplied PCLK signal. This pin is set LOW by the device under all other conditions. IO_VDD = 3.3V Drive Strength = 8mA IO_VDD = 1.8V Drive Strength = 4mA H5 H6 H7 GRP2_EN/DIS GRP1_EN/DIS AUDIO_INT Non Synchronous Non Synchronous Non Synchronous Input Input Output Enable Input for Audio Group 2. Enable Input for Audio Group 1. STATUS SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Summary Interrupt from Audio Processing. This signal is set HIGH by the device to indicate a problem with the audio processing which requires the Host processor to interrogate the interrupt status registers. IO_VDD = 3.3V Drive Strength = 8mA IO_VDD = 1.8V Drive Strength = 4mA H8 JTAG/HOST Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to select JTAG Test Mode or Host Interface Mode. When set HIGH, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are configured for JTAG boundary scan testing. When set LOW, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are configured as Gennum Serial Peripheral Interface (GSPI) pins for normal host interface operation. 40117 - 1 November 2007 14 of 114 GS1582 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number J4 J5 J6 J7 J9 Name AIN_5/6 WCLK_2 AIN_1/2 WCLK_1 SDOUT_TDO Timing Synchronous with ACLK_2 Clock Synchronous with ACLK_1 Clock Synchronous with SCLK_TCK Type Input Input Input Input Output Description Serial Audio Input; Channels 5 and 6. 48kHz word clock for Audio Group 2. Serial Audio Input; Channels 1 and 2. 48kHz word clock for Audio Group 1. COMMUNICATION SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Serial Data Output / Test Data Output Host Mode (JTAG/HOST = LOW) This pin operates as the host interface serial output, used to read status and configuration information from the internal registers of the device. JTAG Test Mode (JTAG/HOST = HIGH) This pin is used to shift test results and operates as the JTAG test data output, TDO. NOTE: If the host interface is not being used leave this pin unconnected. IO_VDD = 3.3V Drive Strength = 12mA IO_VDD = 1.8V Drive Strength = 4mA J10 SCLK_TCK Non Synchronous Input COMMUNICATION SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Serial Data Clock / Test Clock. Host Mode (JTAG/HOST = LOW) SCLK_TCK operates as the host interface burst clock, SCLK. Command and data read/write words are clocked into the device synchronously with this clock. JTAG Test Mode (JTAG/HOST = HIGH) This pin is the TEST MODE START pin, used to control the operation of the JTAG test clock, TCK. NOTE: If the host interface is not being used, tie this pin HIGH. 40117 - 1 November 2007 15 of 114 GS1582 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number K4 K5 K6 K7 K9 Name AIN_7/8 ACLK_2 AIN_3/4 ACLK_1 CS_TMS Timing Synchronous with ACLK_2 Clock Synchronous with ACLK_1 Clock Synchronous with SCLK_TCK Type Input Input Input Input Input Description Serial Audio Input; Channels 7 and 8. 3.072MHz audio clock for Audio Group 2 (channels 5-8). Serial Audio Input; Channels 3 and 4. 3.072MHz audio clock for Audio Group 1(channels 1-4). COMMUNICATION SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Chip Select / Test Mode Start. Host Mode (JTAG/HOST = LOW) CS_TMS operates as the host interface chip select, CS, and is active LOW. JTAG Test Mode (JTAG/HOST = HIGH) CS_TMS operates as the JTAG test mode start, TMS, used to control the operation of the JTAG test, and is active HIGH. NOTE: If the host interface is not being used, tie this pin HIGH. K10 SDIN_TDI Synchronous with SCLK_TCK Input COMMUNICATION SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Serial Data In / Test Data Input Host Mode (JTAG/HOST = LOW) This pin operates as the host interface serial input, SDIN, used to write address and configuration information to the internal registers of the device. JTAG Test Mode (JTAG/HOST = HIGH) This pin is used to shift and operates as the JTAG test data input, TDI. NOTE: If the host interface is not being used, tie this pin HIGH. 40117 - 1 November 2007 16 of 114 GS1582 Data Sheet 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Parameter Supply Voltage, Core (CORE_VDD) Supply Voltage, Analog 1.8V (PD_VDD) Supply Voltage, I/O (IO_VDD) Supply Voltage, Analog 3.3V (CP_VDD, CD_VDD) Input Voltage Range (ACLK, WCLK, AIN, PCLK, DIN) Input Voltage Range (VCO, CP_RES, LF, RSET) Input Voltage Range (All other pins) Ambient Operating Temperature Storage Temperature Peak Reflow Temperature (JEDEC J-STD-020C) ESD Sensitivity, HBM (JESD22-A114) ESD Sensitivity, MM (JESD22-A115) NOTES: 1. Absolute Maximum Ratings are those values beyond which damage may occur. Functional operation under these conditions or at any other condition beyond those indicated in the AC/DC Electrical Characteristics sections is not implied. Value/Units -0.3V to +2.1V -0.3V to +2.1V -0.3V to +3.6V -0.3V to +3.6V -0.5V to IO_VDD+0.25V -0.5V to +3.6V -0.5V to +5.25V -40°C < TA < 95°C -40°C < TSTG < 125°C 260°C 4000V 200V 2.2 Recommended Operating Conditions Table 2-1: Recommended Operating Conditions Parameter Operating Temperature Range, Ambient Supply Voltage, Digital Core Supply Voltage, Phase Detector Supply Voltage, Charge Pump Supply Voltage, Cable Driver Supply Voltage, Digital I/O Supply Voltage, Digital I/O Symbol TA CORE_VDD PD_VDD CP_VDD CD_VDD IO_VDD IO_VDD Conditions – – – – – 1.8V mode 3.3V mode Min -20 1.71 1.71 3.13 3.13 1.71 3.13 Typ 25 1.8 1.8 3.3 3.3 1.8 3.3 Max 85 1.89 1.89 3.47 3.47 1.89 3.47 Units °C V V V V V V Note s 40117 - 1 November 2007 17 of 114 GS1582 Data Sheet 2.3 DC Electrical Characteristics Table 2-2: DC Electrical Characteristics Guaranteed over recommended operating conditions unless otherwise noted. Parameter System External VCO Power Supply Voltage (VCO_VDD) +1.8V Supply Current Symbol Conditions Min Typ Max Units Notes 2.375 2.5 2.625 V 1 I1V8 10/20bit HD, Audio Enabled 10/20bit HD, Audio Disabled 10/20bit SD, Audio Enabled 10/20bit SD, Audio Disabled DVB_ASI – – – – – – – – – – – – – – – – 10 138 109 112 104 100 74 74 74 74 74 491 440 445 430 424 310 125 165 130 130 120 120 86 86 86 86 86 600 540 545 530 510 – – mA mA mA mA mA mA mA mA mA mA mW mW mW mW mW mW mW 2,4 2,4 2,4 2,4 2,4 3,4 3,4 3,4 3,4 3,4 4 4 4 4 4 – 5 +3.3V Supply Current I3V3 10/20bit HD, Audio Enabled 10/20bit HD, Audio Disabled 10/20bit SD, Audio Enabled 10/20bit SD, Audio Disabled DVB_ASI Total Device Power PD 10/20bit HD, Audio Enabled 10/20bit HD, Audio Disabled 10/20bit SD, Audio Enabled 10/20bit SD, Audio Disabled DVB_ASI Reset Standby Digital I/O Input Logic LOW Input Logic HIGH Output Logic LOW VIL VIH VOL 3.3V or 1.8V operation 3.3V or 1.8V operation 1.8V mode 3.3V mode Output Logic HIGH VOH 1.8V mode 3.3V mode – 0.7 x IO_VDD – – 1.4 2.4 – – – – – – 0.3 x IO_VDD – 0.3 0.4 – – V V V V V V – – – – – – 40117 - 1 November 2007 18 of 114 GS1582 Data Sheet Table 2-2: DC Electrical Characteristics (Continued) Guaranteed over recommended operating conditions unless otherwise noted. Parameter Output Output Common Mode Voltage NOTES 1. 2. 3. 4. 5. Symbol Conditions Min Typ Max Units Notes VCMOUT 75Ω load, RSET=750Ω SD and HD mode – CD_VDD - ΔVSDD – V – VCO_VDD guaranteed only when GO1555 is connected. Sum of all 1.8V supplies. Sum of all 3.3V supplies. IO_VDD = 3.3V. When IO_VDD = 1.8V, the current/power consumption is lower by up to 5mA/10mW. See Standby Section for details. 2.4 AC Electrical Characteristics Table 2-3: AC Electrical Characteristics Guaranteed over recommended operating conditions unless otherwise noted. Parameter System Device Latency Symbol Conditions Min Typ Max Units Notes – – – – 10-bit SD 20-bit HD DVB-ASI 10-bit SD or 20-bit HD; All Audio Disabled – – – – – – – – – 550 1065 15 27 PCLK PCLK PCLK PCLK – – – – Reset Pulse Width treset 10 – – ms 1 Parallel Input Parallel Clock Frequency Parallel Clock Duty Cycle Input Data Setup Time Input Data Hold Time fPCLK DCPCLK tsu tih – – 50% levels; 3.3V or 1.8V operation 13.5 40 2 2 – – – – 148.5 60 – – MHz % ns ns – – 4 4 Serial Audio Data Input Input Data Set-up Time Input Data Hold Time tsu tih 50% levels; 3.3V or 1.8V operation 74 74 – – – – ns ns – – Serial Digital Output Serial Output Data Rate DRSDO – – – Serial Output Swing Serial Output Rise/Fall Time 20% ~ 80% VSDD trfSDO trfSDO RSET = 750Ω 75Ω load HD mode SD mode – – – 750 – 400 1.485 1.485/1.001 270 800 120 660 – – – 850 270 800 Gb/s Gb/s Mb/s mVp-p ps ps – – – – – – 40117 - 1 November 2007 19 of 114 GS1582 Data Sheet Table 2-3: AC Electrical Characteristics (Continued) Guaranteed over recommended operating conditions unless otherwise noted. Parameter Mismatch in rise/fall time Duty Cycle Distortion Overshoot Output Return Loss Serial Output Intrinsic Jitter Symbol Δtr,Δtf – – – ORL tOJ Conditions – – SD/HD=0 SD/HD=1 5 MHz - 1.485 GHz Pseudorandom and SMPTE Colour Bars HD signal Pseudorandom and SMPTE Colour Bars SD signal Min – – – – – – Typ – 1 5 3 18 35 Max 35 5 10 8 – 80 Units ps % % % dB ps Notes – 5 5 5 6 2 tOJ – 100 200 ps 3 GSPI GSPI Input Clock Frequency GSPI Input Clock Duty Cycle GSPI Input Data Setup Time GSPI Input Data Hold Time GSPI Output Data Hold Time CS low before SCLK rising edge Time between end of command word (or data in Auto-Increment mode) and the first SCLK of the following data word - write cycle Time between end of command word (or data in Auto-Increment mode) and the first SCLK of the following data word - read cycle CS high after SCLK rising edge NOTES: See ’Device Reset’ on page 107, Figure 4-33. Alignment Jitter = measured from 100kHz to 148.5MHz Alignment Jitter = measured from 1kHz to 27MHz Input setup and hold time is dependent on the rise and fall time on the parallel input. Parallel clock and data with rise time or fall time greater than 500ps require larger setup and hold times. 5. Single Ended into 75Ω external load. 6. ORL depends on board design. The GS1582 achieves this specification on Gennum’s evaluation boards. 1. 2. 3. 4. fSCLK DCSCLK – – – – – 15pF load 50% levels 3.3V or 1.8V operation 50% levels 3.3V or 1.8V operation 50% levels 3.3V or 1.8V operation – 40 1.5 1.5 1.5 1.5 37.1 – 50 – – – – – 10 60 – – – – – MHz % ns ns ns ns ns – – – – – – – – 50% levels 3.3V or 1.8V operation 148.4 – – ns – – 50% levels 3.3V or 1.8V operation 37.1 – – ns – 40117 - 1 November 2007 20 of 114 GS1582 Data Sheet 2.5 Solder Reflow Profiles The GS1582 is available in a Pb-free package. It is recommended that the Pb-free package be soldered with Pb-free paste using the reflow profile shown in Figure 2-1. Temperature 60-150 sec. 20-40 sec. 260˚C 250˚C 3 ˚C/sec max 217˚C 6˚C/sec max 200˚C 150˚C 25˚C Time 60-180 sec. max 8 min. max Figure 2-1: Maximum Pb-free Solder Reflow Profile 40117 - 1 November 2007 21 of 114 GS1582 Data Sheet 3. Input/Output Circuits All resistors in ohms, all capacitors in farads, unless otherwise shown. CD_VDD SDO SDO IREF Figure 3-1: Differential Output Stage (SDO/SDO) CP_RES 200 800mV Figure 3-2: Charge Pump Current Setting Resistor (CP_RES) 40117 - 1 November 2007 22 of 114 GS1582 Data Sheet VDD VDD 800 5.6K LF 5.6K 800 Figure 3-3: PLL Loop Filter VCO VDD 50 40K 50 160K 50pF Figure 3-4: VCO Input 40117 - 1 November 2007 23 of 114 GS1582 Data Sheet IO_VDD Input Pin Figure 3-5: Digital Input Pin with Weak Pull Up(>33kΩ) (ACLK[2:1], WCLK[2:1], AIN[4:1], PCLK, DIN[19:0]) IO_VDD Input Pin Figure 3-6: 5V Tolerant Input Pin (All Other Input Pins) EN Output Pin Figure 3-7: Digital Output Pin with High Impedance Mode (LOCKED, AUDIO_INT, SDOUT_TDO) 40117 - 1 November 2007 24 of 114 GS1582 Data Sheet 4. Detailed Description 4.1 Functional Overview The GS1582 is a multi-rate serializer with an integrated cable driver and embedded audio multiplexer. When used in conjunction with the external GO1555 Voltage Controlled Oscillator, a transmit solution at 1.485Gb/s, 1.485/1.001Gb/s or 270Mb/s is realized. The device has three basic modes of operation that must be set through external device pins; SMPTE mode, DVB-ASI mode, and Data-Through mode. In SMPTE mode, the device will accept 10-bit multiplexed or 20-bit demultiplexed SMPTE compliant data at both HD and SD signal rates. By default, the device’s additional processing features, including audio embedding, will be enabled in this mode. In DVB-ASI mode, the GS1582 will accept an 8-bit parallel DVB-ASI compliant transport stream on DIN[17:10]. The serial output data stream will be 8b/10b encoded with stuffing characters added as per the standard. Data-Through mode allows for the serializing of data not conforming to SMPTE or DVB-ASI streams. No additional processing will be done in this mode. In Standby mode, the device power consumption will be reduced. The serial digital output features a high impedance mode and adjustable signal swing. The output slew rate is automatically set by the SD/HD pin setting. GS1582 provides several data processing functions including generic ANC insertion, SMPTE 352M and EDH data packet generation and insertion, automatic video standards detection, and TRS, CRC, ANC data checksum, and line number calculation and insertion. These features are all enabled/disabled collectively using the external IO processing pin, but may be individually disabled via internal registers accessible through the GSPI host interface. Finally, the GS1582 contains a JTAG interface for boundary scan test implementations. 40117 - 1 November 2007 25 of 114 GS1582 Data Sheet 4.2 Parallel Data Inputs Data is clocked into the device on the rising edge of PCLK as shown in Figure 4-1. The input data format is defined by the setting of the external SD/HD, SMPTE_BYPASS, and DVB_ASI pins and may be presented in 10-bit or 20-bit format. The input data bus width is controlled by the 20bit/10bit input pin. PCLK DIN[19:0] DATA Control signal input tSU tIH Figure 4-1: PCLK to Data Timing 4.2.1 Parallel Input in SMPTE Mode When the device is operating in SMPTE mode, see SMPTE Mode on page 28, both SD and HD data may be presented to the input bus in either multiplexed or demultiplexed form depending on the setting of the 20bit/10bit input pin. In 20-bit mode, (20bit/10bit = HIGH), the input data format should be word aligned, demultiplexed luma and chroma data. Luma words should be presented on DIN[19:10] while chroma words should be presented on DIN[9:0]. In 10-bit mode, (20bit/10bit = LOW), the input data format should be word aligned, multiplexed luma and chroma data. The data should be presented on DIN[19:10]. DIN[9:0] will be high impedance in this mode. 4.2.2 Parallel Input in DVB-ASI Mode When operating in DVB-ASI mode, see DVB-ASI mode on page 34, the GS1582 must be set to 10-bit operation mode by setting the 20bit/10bit pin LOW. The device will accept 8-bit data words on DIN[17:10]. DIN17 = HIN is the most significant bit of the encoded transport stream data and DIN10 = AIN is the least significant bit. In addition, DIN19 and DIN18 will be configured as the DVB-ASI control signals INSSYNCIN and KIN respectively. See DVB-ASI mode on page 34 for a description of these DVB-ASI specific input signals. DIN[9:0] will have a Logic Level HIGH in DVB-ASI mode. 40117 - 1 November 2007 26 of 114 GS1582 Data Sheet 4.2.3 Parallel Input in Data-Through Mode When operating in Data-Through mode, see Data-Through Mode on page 35, the GS1582 passes data from the parallel input bus to the serial output without performing any encoding or scrambling. The input data bus width is controlled by the setting of the 20bit/10bit pin. 4.2.4 Parallel Input Clock (PCLK) The frequency of the PCLK input signal required by the GS1582 is determined by the input data format. Table 4-1 below lists the possible input signal formats and their corresponding parallel clock rates. Note that the DVB-ASI input will only be in 10-bit format, when setting the 20bit/10bit pin LOW. Table 4-1: Parallel Data Input Format Control Signals Input Data Format DIN [19:10] DIN [9:0] PCLK 20bit/ 10bit SD/ HD SMPTE_BYPASS DVB_ASI SMPTE MODE 20-bit DEMULTIPLEXED SD 10-bit MULTIPLEXED SD 20-bit DEMULTIPLEXED HD LUMA LUMA / CHROMA LUMA CHROMA HIGH IMPEDANCE CHROMA 13.5MHz 27MHz 74.25 or 74.25/ 1.001MHz LUMA / CHROMA HIGH IMPEDANCE 148.5 or 148.5/ 1.001MHz LOW LOW HIGH LOW HIGH LOW HIGH HIGH HIGH LOW HIGH HIGH HIGH LOW LOW LOW 10-bit MULTIPLEXED HD DVB-ASI MODE 10-bit DVB-ASI DVB-ASI DATA HIGH IMPEDANCE 27MHz LOW LOW HIGH HIGH LOW LOW HIGH HIGH DATA-THROUGH MODE 20-bit SD 10-bit SD 20-bit HD DATA DATA DATA DATA HIGH IMPEDANCE DATA 13.5MHz 27MHz 74.25 or 74.25/ 1.001MHz 10-bit HD DATA HIGH IMPEDANCE 148.5 or 148.5/ 1.001MHz LOW LOW LOW LOW HIGH LOW HIGH HIGH HIGH LOW LOW LOW LOW LOW LOW LOW 40117 - 1 November 2007 27 of 114 GS1582 Data Sheet 4.3 SMPTE Mode The GS1582 operates in SMPTE mode when the SMPTE_BYPASS pin is set HIGH and the DVB_ASI pin is set LOW. In this mode, the parallel data will be scrambled according to SMPTE 259M or 292M, and NRZ-to-NRZI encoded prior to serialization. 4.3.1 HVF Timing In SMPTE mode, the GS1582 can automatically detect the video standard and generate all internal timing signals. The total line length, active line length, total number of lines per field/frame and total active lines per field/frame are calculated for the received parallel video. When DETECT_TRS is LOW, the video standard and timing signals are based on the externally supplied H_Blanking, V_Blanking, and F_Digital signals. These signals go to the H/HSYNC, V/VSYNC and F/DE pins respectively. When DETECT_TRS is HIGH, the video standard timing signals will be extracted from the embedded TRS ID words in the parallel input data. Both 8-bit and 10-bit TRS code words will be identified by the device. NOTE: IO processing must be enabled for the device to remap 8-bit TRS words to the corresponding 10-bit value for transmission. See Section 4.9.4.2 for more information. The GS1582 determines the video standard by timing the horizontal and vertical reference information supplied at the H/HSYNC, V/VSYNC, and F/DE input pins, or contained in the TRS ID words of the received video data. Therefore, full synchronization to the received video standard requires one complete video frame. Once synchronization has been achieved, the GS1582 will continue to monitor the received TRS timing or the supplied H, V, and F timing information to maintain synchronization. GS1582 will lose all timing information immediately following loss of H, V and F. The H signal timing should also be configured via the H_CONFIG bit of the internal IOPROC_DISABLE register as either active line based blanking or TRS based blanking. See Packet Generation and Insertion on page 68. Active line based blanking is enabled when the H_CONFIG bit is set LOW. In this mode, the H input should be HIGH for the entire horizontal blanking period, including the EAV and SAV TRS words. This is the default H timing used by the device. The timing of these signals is shown in Figure 4-2. 40117 - 1 November 2007 28 of 114 GS1582 Data Sheet PCLK LUMA DATA OUT 3FF 000 000 XYZ (eav) XYZ (eav) 3FF 000 000 XYZ (sav) XYZ (sav) CHROMA DATA OUT 3FF 000 000 3FF 000 000 H V F H_Blanking: V_Blanking: F_Digital TIMING - HD 20-BIT INPUT MODE PCLK MULTIPLEXED Y/Cr/Cb DATA OUT H V F 3FF 3FF 000 000 000 000 XYZ (eav) XYZ (eav) H_Blanking: V_Blanking: F_Digital TIMING AT EAV - HD 10-BIT INPUT MODE PCLK MULTIPLEXED Y/Cr/Cb DATA OUT H V F 3FF 3FF 000 000 000 000 XYZ (sav) XYZ (sav) H_Blanking: V_Blanking: F_Digital TIMING AT SAV - HD 10-BIT INPUT MODE PCLK CHROMA DATA OUT 3FF 000 3FF 000 LUMA DATA OUT H V F H_CONFIG = HIGH 000 XYZ (eav) 000 XYZ (SAV) H SIGNAL TIMING: H_CONFIG = LOW H_Blanking: V_Blanking: F_Digital TIMING - SD 20-BIT INPUT MODE PCLK MULTIPLEXED Y/Cr/Cb DATA OUT H V F 3FF 000 000 XYZ (eav) 3FF 000 000 XYZ (sav) H_Blanking: V_Blanking: F_Digital TIMING - SD 10-BIT INPUT MODE Figure 4-2: H_Blanking, V_Blanking, F_Digital Timing 4.3.2 CEA 861 Timing The GS1582 extracts timing information from externally provided HSYNC, VSYNC, and DE signals when CEA 861 timing mode is selected by setting DETECT_TRS = LOW and the TIM_861 = HIGH. 40117 - 1 November 2007 29 of 114 GS1582 Data Sheet Horizontal sync (H), Vertical sync (V), and Data Enable (DE) timing must be provided via the H/HSYNC, V/VSYNC and F/DE input pins. The host interface register bit H_CONFIG will be ignored in the CEA 861 input timing mode. The GS1582 will determine the EIA/CEA-861 standard and embed EAV and SAV TRS words in the output serial video stream. Video standard detection is not dependent on the HSYNC pulse width or the VSYNC pulse width and therefore the GS1582 will tolerate non-standard pulse widths. In addition, the device can compensate for up to ±1 PCLK cycle of jitter on VSYNC with respect to HSYNC and sample VSYNC correctly. NOTE 1: The period between the leading edge of the HSYNC pulse and the leading edge of Data Enable (DE) must follow the timing requirements described in the EIA/CEA-861 specification. The GS1582 embeds TRS words according to this timing relationship to maintain compatibility with the corresponding SMPTE standard. NOTE 2: When CEA 861 standards 6 & 7 [720(1440)x480i] are presented to the GS1582, the device will embed TRS words corresponding to the timing defined in SMPTE 125M to maintain SMPTE compatibility. CEA 861 standards 6 & 7 [720(1440)x480i] define the active area on lines 22 to 261 and 285 to 524 inclusive (240 active lines per field). SMPTE 125M defines the active area on lines 20 to 263 and 283 to 525 inclusive (244 lines on field 1; 243 lines on field 2). Therefore, in the first field, the GS1582 adds two active lines above and two active lines below the original active image. In the second field it adds two lines above and one line below the original active image. 40117 - 1 November 2007 30 of 114 GS1582 Data Sheet 1650 Total Horizontal Clocks per line Data Enable 370 1280 Clocks for Active Video 40 110 220 clocks HSYNC Progressive Frame: 30 Vertical Blanking Lines Data Enable 720 Active Vertical Lines ~ ~ ~ ~ ~ 745 746 110 1650 clocks HSYNC ~ ~ 745 746 747 748 749 750 1 2 3 4 5 6 7 25 26 ~ ~ ~ 750 562 VSYNC Figure 4-3: HSYNC:VSYNC:DE Input Timing 1280 x 720p @ 59.94/60 2200 Total Horizontal Clocks per line Data Enable 280 1920 Clocks for Active Video 44 148 clocks 88 HSYNC Field 1: 22 Vertical Blanking Lines Data Enable 2200 clocks 88 540 Active Vertical Lines per field ~ ~ 1123 1124 1125 1 2 3 4 5 6 7 8 ~ ~ 19 20 21 ~ HSYNC ~ ~ ~ 560 561 VSYNC Field 2: 23 Vertical Blanking Lines Data Enable 88 2200 clocks 1100 540 Active Vertical Lines per field ~ HSYNC ~ ~ ~ ~ ~ 560 561 562 563 564 565 566 567 568 569 570 582 583 584 VSYNC Figure 4-4: HSYNC:VSYNC:DE Input Timing 1920 x 1080i @ 59.94/60 40117 - 1 November 2007 ~ ~ 1123 1124 1125 ~ ~ 31 of 114 GS1582 Data Sheet 1716 Total Horizontal Clocks per line Data Enable 276 38 HSYNC 124 1440 Clocks for Active Video 114 clocks Field 1: 22 Vertical Blanking Lines Data Enable 38 1716 clocks 240 Active Vertical Lines per field ~ ~ ~ 238 ~ HSYNC 524 525 1 2 3 4 5 6 7 8 9 21 22 261 262 263 VSYNC Field 2: 23 Vertical Blanking Lines Data Enable 1716 clocks 858 240 Active Vertical Lines per field ~ ~ ~ 238 ~ HSYNC 261 262 263 264 265 266 267 268 269 270 271 284 285 524 525 1 VSYNC Figure 4-5: HSYNC:VSYNC:DE Input Timing 720 (1440) x 480i @ 59.94/60 40117 - 1 November 2007 ~ ~ ~ ~ ~ ~ ~ ~ 32 of 114 GS1582 Data Sheet 1980 Total Horizontal Clocks per line Data Enable 700 1280 Clocks for Active Video 40 220 clocks 440 HSYNC Progressive Frame: 30 Vertical Blanking Lines Data Enable ~ ~ 440 1980 clocks 720 Active Vertical Lines ~ ~ HSYNC ~ ~ ~ 745 746 747 748 749 750 1 2 3 4 5 6 7 25 26 ~ 745 746 ~ ~ 750 VSYNC Figure 4-6: HSYNC:VSYNC:DE Input Timing 1280 x 720p @ 50 2640 Total Horizontal Clocks per line Data Enable 720 1920 Clocks for Active Video 44 148 clocks 528 HSYNC Field 1: 22 Vertical Blanking Lines Data Enable 2640 clocks 528 540 Active Vertical Lines per field ~ ~ 1123 1124 1125 1 2 3 4 5 6 7 8 ~ ~ 19 20 21 ~ HSYNC ~ ~ ~ 560 561 VSYNC Field 2: 23 Vertical Blanking Lines Data Enable 528 2640 clocks 1320 540 Active Vertical Lines per field ~ HSYNC ~ ~ ~ ~ ~ 560 561 562 563 564 565 566 567 568 569 570 582 583 584 VSYNC Figure 4-7: HSYNC:VSYNC:DE Input Timing 1920 x 1080i @ 50 40117 - 1 November 2007 ~ ~ 1123 1124 1125 ~ ~ 562 33 of 114 GS1582 Data Sheet 1728 Total Horizontal Clocks per line Data Enable 288 24 HSYNC 126 1440 Clocks for Active Video 138 clocks Field 1: 24 Vertical Blanking Lines Data Enable 24 1728 clocks 288 Active Vertical Lines per field ~ ~ ~ 264 ~ 22 23 HSYNC 623 624 625 1 2 3 4 5 6 7 310 311 312 VSYNC Field 2: 25 Vertical Blanking Lines Data Enable 1728 clocks 864 288 Active Vertical Lines per field ~ ~ ~ 264 ~ 335 336 HSYNC 310 311 312 313 314 315 316 317 318 319 320 623 624 625 VSYNC Figure 4-8: HSYNC:VSYNC:DE Input Timing 720 (1440) x 576 @ 50 4.4 DVB-ASI mode The GS1582 operates in DVB-ASI mode when the SMPTE_BYPASS pin is set LOW and the DVB_ASI and SD/HD pins are set HIGH. In this mode, all SMPTE processing functions are disabled, and the 8-bit transport stream data will be 8b/10b encoded prior to serialization. 4.4.1 Control Signal Inputs In DVB-ASI mode, the DIN19 and DIN18 pins are configured as DVB-ASI control signals INSSYNCIN and KIN respectively. When INSSYNCIN is set HIGH, the device will insert K28.5 sync characters into the data stream. This function is used in system implementations where the GS1582 is preceded by an external data FIFO. Parallel DVB-ASI data may be clocked into the FIFO at some rate less than 27MHz. The INSSYNCIN input may then be connected to the FIFO empty signal, providing a means of padding the data transmission rate to 27MHz. See Figure 4-9. 40117 - 1 November 2007 ~ ~ ~ ~ ~ ~ ~ ~ 34 of 114 GS1582 Data Sheet NOTE: 8b/10b encoding will take place after K28.5 sync character insertion. KIN should be set HIGH whenever the parallel data input is to be interpreted as any special character defined by the DVB-ASI standard (including the K28.5 sync character). This pin should be set LOW when the input is to be interpreted as data. NOTE: When operating in DVB-ASI mode, DIN[9:0] are set to high impedance. AIN ~ HIN TS 8 FIFO 8 SDO KIN WRITE_CLK