GS1881-IDA

GS1881, GS4881, GS4981 Monolithic Video Sync Separators DATA SHEET FEATURES • noise tolerant odd/even flag, back porch and horizontal sync pulse • fast recovery from impulse noise • excellent temperature stability • 0.5 V to 4 Vpp input signal amplitude with 5 V supply • well-controlled clamp discharge current and slicing level • programmable horizontal scan rate (up to 130 kHz) • composite, vertical, back porch, odd/even (GS1881, GS4881), horizontal (GS4981) outputs • predictable vertical output pulse width with default trigger for non-standard video signals • 5 V to 12 V supply voltage range • pin compatible with LM1881 sync separator SELECTION CHART DESCRIPTION The GS1881, GS4881 and GS4981 are general purpose sync separators for use in a wide variety of video applications. The devices extract the timing information from composite video signals with scan rates from 15 to 130 kHz. The GS1881 is a drop-in replacement for the industry standard LM1881 with much improved performance. The device generates composite sync, vertical sync, back porch and odd/even field signals. The GS4881 is identical to the GS1881 but features a noise immune back porch pulse which maintains a constant H rate during the vertical interval. The GS4981 is identical to the GS4881, except that it provides horizontal sync in place of the odd/even output. All three devices feature a self-adjusting windowing circuit for noise immunity, which synchronizes to H rate. This windowing c i r c u i t d e t e r m i n e s t h e o d d o r e v e n f i e l d in the GS1881 and GS4881, gates the back porch pulse in the GS4881 and GS4981, and generates the horizontal sync output in the GS4981. The devices feature an improved input stage which ensures that the input signal is sliced at a predictable point due to well-controlled input clamp discharge current and sync slicing level. A missing pulse detector enables the devices to recover quickly from impulse noise disturbances by temporarily increasing the clamp discharge current by roughly ten times. The input stage will operate with signals from 0.5 to 4 volts peak to peak with a 5 volt supply. The GS1881, GS4881 and GS4981 also feature a predictable vertical output pulse width with a default trigger for non-standard video signals. All three are available in commercial and industrial temperature ranges and are packaged in both DIP and SOIC. APPLICATION Direct LM1881 Replacement with Improved Performance New Applications Substitution for LM1881 New Applications Requiring Horizontal Sync Output CHOOSE DEVICE: GS1881 GS4881 GS4981 PIN CONNECTIONS GS1881, GS4881 COMPOSITE SYNC OUT COMPOSITE VIDEO IN VERTICAL SYNC OUT GROUND 1 2 3 4 8 7 6 5 V COMPOSITE SYNC OUT COMPOSITE VIDEO IN VERTICAL SYNC OUT GROUND 1 2 3 4 GS4981 8 7 6 5 V cc cc ODD/EVEN RSET BACK PORCH HORIZONTAL R SET BACK PORCH 8 PIN DIP 8 PIN SOIC Patent No. 5,432,559 Revision Date: October 1995 8 PIN DIP 8 PIN SOIC Document No. 520 - 23 - 03 GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-2055 Japan Branch: A-302 Miyamae Village, 2-10-42 Miyamae, Suginami-ku, Tokyo 168, Japan tel. (03) 3247-8838 fax (03) 3247-8839 GS1881 ELECTRICAL CHARACTERISTICS PARAMETER Supply Voltage Supply Current (VCC= 5 V, R SET = 680 kΩ, TA = 25 ° C, unless otherwise specified) CONDITIONS MIN 4.5 TYP 5 4.6 5.0 MAX 13.2 6.5 7.0 UNITS V mA mA Outputs at Logic 1 VCC = 5 V V CC = 12 V - Video Input (Pin 2) (a) Signal Level (b) Clamp Current VCC = 5 V Charge Discharge - normal - Nosync flag raised (c) Delay to raising of Nosync flag Video input held high (d) Sync Tip Clamp Voltage Sync Slice Level RSET Pin Reference Voltage (Pin 6) Composite Sync Out (Pin 1) Delay from Video Back Porch Pulse Out (Pin 5) (a) Delay from Rising Edge of Sync (b) Pulse Width Vertical Sync Out (Pin 3) (a) Pulse Width (b) Default Starting Time Horizontal Scan Rate Logic Outputs (a) V OH I OH = 40 µA I OH = 1.6 mA (b) V OL I OL = -1.6 mA V CC = 5 V V CC = 12 V VCC = 5 V VCC = 12 V 4.2 11.2 2.4 9.4 4.6 11.6 3.4 10.4 0.3 0.6 V V V V V Serrations during vertical interval No serrations during the vertical interval Modified R SET 197.7 48 15 197.7 65 197.7 82 130 µs µs kHz 400 2.0 500 2.5 650 3.2 ns µs Relative to sync tip clamp voltage See Note 1 See Note 2 CL = 15p CL = 15p 0.5 500 9 65 64 70 1.14 40 650 11 95 95 1.55 77 1.24 60 4 850 13 115 130 84 1.34 80 Vp-p µA µA µA µs V mV V ns Note 1: When placing the RSET resistor and the 0.1µF decoupling capacitor careful attention should be made to ensure that they are as close as possible to pin 6. Care should also be taken to avoid parasitic capacitive coupling from any output pin (pins 1, 3, 5 and 7) to pin 6. Note 2: Measured from slicing point of input falling edge to 50% point of composite sync falling edge. ORDERING INFORMATION Part Number GS1881 - CDA GS1881 - CKA GS1881 - CTA GS1881 - IDA GS1881 - IKA GS1881 - ITA Package Type 8 PDIP 8 SOIC 8 TAPE 8 PDIP 8 SOIC 8 TAPE Temperature Range 0° to 70° C 0° to 70° C 0° to 70° C -25° to 85° C -25° to 85° C -25° to 85° C CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION 520 - 23 - 03 2 GS4881 ELECTRICAL CHARACTERISTICS PARAMETER Supply Voltage Supply Current (VCC= 5 V, RSET = 680 k Ω, TA = 25° C, unless otherwise specified) CONDITIONS MIN 4.5 TYP 5 4.6 5.0 MAX 13.2 6.5 7.0 UNITS V mA mA Outputs at Logic 1 VCC = 5 V VCC = 12 V - Video Input (Pin 2) (a) Signal Level (b) Clamp Current VCC = 5 V Charge Discharge - normal - Nosync flag raised (c) Delay to raising of Nosync flag Video input held high (d) Sync Tip Clamp Voltage Sync Slice Level RSET Pin Reference Voltage (Pin 6) Composite Sync Out (Pin 1) Delay from Video Back Porch Pulse Out (Pin 5) (a) Delay from Rising Edge of Sync (b) Pulse Width (c) Occurence Rate Vertical Sync Out (Pin 3) (a) Pulse Width (b) Default Starting Time Horizontal Scan Rate Logic Outputs (a) VOH I OH = 40 µA I OH = 1.6 mA (b) VOL I OL = -1.6 mA V CC = 5 V VCC = 12 V VCC = 5 V V CC = 12 V 4.2 11.2 2.4 9.4 4.6 11.6 3.4 10.4 0.3 0.6 V V V V V Serrations during vertical interval No serrations during the vertical interval Modified R SET 197.7 48 15 197.7 65 197.7 82 130 µs µs kHz 400 2.0 H 500 2.5 H 650 3.2 H ns µs Relative to sync tip clamp voltage See Note 1 See Note 2 CL = 15p CL = 15p 0.5 500 9 65 64 70 1.14 40 650 11 95 95 1.55 77 1.24 60 4 850 13 115 130 84 1.34 80 Vp-p µA µA µA µs V mV V ns Note 1: When placing the RSET resistor and the 0.1µF decoupling capacitor careful attention should be made to ensure that they are as close as possible to pin 6. Care should also be taken to avoid parasitic capacitive coupling from any output pin (pins 1, 3, 5 and 7) to pin 6. Note 2: Measured from slicing point of input falling edge to 50% point of composite sync falling edge. ORDERING INFORMATION Part Number GS4881 - CDA GS4881 - CKA GS4881 - CTA GS4881 - IDA GS4881 - IKA GS4881 - ITA Package Type 8 PDIP 8 SOIC 8 TAPE 8 PDIP 8 SOIC 8 TAPE Temperature Range 0° to 70° C 0° to 70° C 0° to 70° C -25° to 85° C -25° to 85° C -25° to 85° C 3 520 - 23 - 03 GS4981 ELECTRICAL CHARACTERISTICS PARAMETER Supply Voltage Supply Current (VCC= 5 V, RSET = 680 k Ω, TA = 25° C, unless otherwise specified) CONDITIONS MIN 4.5 TYP 5 4.6 5.0 MAX 13.2 6.5 7.0 UNITS V mA mA Outputs at Logic 1 VCC = 5 V VCC = 12 V - Video Input (Pin 2) (a) Signal Level (b) Clamp Current VCC = 5 V Charge Discharge - normal - Nosync flag raised (c) Delay to raising of Nosync flag Video input held high (d) Sync Tip Clamp Voltage Sync Slice Level RSET Pin Reference Voltage (Pin 6) Composite Sync Out (Pin 1) Delay from Video Back Porch Pulse Out (Pin 5) (a) Delay from Rising Edge of Sync (b) Pulse Width (c) Occurence Rate Vertical Sync Out (Pin 3) (a) Pulse Width (b) Default Starting Time Horizontal Sync Out (Pin 7) (a) Delay from Video (b) Pulse Width Horizontal Scan Rate Logic Outputs (a) V OH I OH = 40 µA I OH = 1.6 mA Note 3 (b) V OL I OL = -1.6 mA V CC = 5 V VCC = 12 V VCC = 5 V VCC = 12 V 4.2 11.2 2.4 9.4 4.6 11.6 3.4 10.4 0.3 0.6 V V V V V Modified RSET Serrations during vertical interval No serrations during the vertical interval CL = 15p 90 5.0 15 190 7.0 290 9.0 130 ns µs kHz 197.7 48 197.7 65 197.7 82 µs µs 400 2.0 H 500 2.5 H 650 3.2 H ns µs Relative to sync tip clamp voltage See Note 1 See Note 2 CL = 15p CL = 15p 0.5 500 9 65 64 70 1.14 40 650 11 95 95 1.55 77 1.24 60 4 850 13 115 130 84 1.34 80 Vp-p µA µA µA µs V mV V ns Note 1: When placing the RSET resistor and the 0.1 µF decoupling capacitor careful attention should be made to ensure that they are as close as possible to pin 6. Care should also be taken to avoid parasitic capacitive coupling from any output pin (pins 1, 3, 5 and 7) to pin 6. Note 2: Measured from slicing point of input falling edge to 50% point of composite sync falling edge. Note 3: Applies only to composite sync, vertical sync, and back porch outputs. Horizontal sync has a passive 10 kΩ pull-up to V CC . ORDERING INFORMATION Part Number GS4981 - CDA GS4981 - CKA GS4981 - CTA GS4981 - IDA GS4981 - IKA GS4981 - ITA 520 - 23 - 03 Package Type 8 PDIP 8 SOIC 8 TAPE 8 PDIP 8 SOIC 8 TAPE Temperature Range 0° to 70° C 0° to 70° C 0° to 70° C -25° to 85° C -25° to 85° C -25° to 85° C 4 TYPICAL PERFORMANCE CHARACTERISTICS (VS = 5V, TA = 25° C unless otherwise shown) 700 600 500 70 VERTICAL DEFAULT TIME (µs) 15 35 55 75 95 115 135 60 50 40 30 20 10 0 0 100 200 300 400 500 600 700 RSET (kΩ) 400 300 200 100 0 SCAN RATE (kHz) RSET (k Ω) Fig. 1 RSET vs Scan Rate Fig. 2 Vertical Sync Default Starting Time vs RSET 700 600 3000 BACK PORCH DELAY (ns) 2500 500 400 300 200 100 0 BACK PORCH WIDTH (ns) 2000 1500 1000 500 0 100 200 300 400 500 600 700 0 0 100 200 300 400 500 600 700 RSET (kΩ) RSET (kΩ) Fig. 3 Back Porch Delay vs RSET Fig. 4 Back Porch Width vs RSET 8000 7000 110 100 HORIZONTAL WIDTH (µs) 6000 5000 4000 3000 2000 1000 0 0 100 200 300 400 500 600 700 NOSYNC DELAY TIME ( µs) 90 80 70 60 50 40 30 20 10 0 0 100 200 300 400 500 600 700 RSET (k Ω) RSET (k Ω) Fig. 5 Horizontal Width vs RSET Fig. 6 Nosync Delay Time vs RSET 5 520 - 23 - 03 TEMPERATURE CHARACTERISTICS (VS = 5V, RSET = 680 kΩ unless otherwise shown) Commercial Temperature Range (0 - 70 °C) 10 850 COMPOSITE SYNC DELAY VARIATION (ns) 8 CLAMPING CURRENT (µ A) 740 6 4 2 0 -2 -4 -6 -25 -15 -5 5 15 25 35 45 55 65 75 85 650 550 450 350 -25 -15 -5 5 15 25 35 45 55 65 75 85 TEMPERATURE (°C) TEMPERATURE ( °C) Fig. 7 Composite Sync Delay Variation vs Temperature Fig. 8 Clamping Current vs Temperature 30 125 BACK PORCH DELAY VARIATION (ns) BACK PORCH WIDTH VARIATION (ns) 100 75 50 25 0 -25 -50 -75 100 -125 20 10 0 -10 -20 -25 -15 -5 5 15 25 35 45 55 65 75 85 -25 -15 -5 5 15 25 35 45 55 65 75 85 TEMPERATURE (°C) TEMPERATURE (°C) Fig. 9 Back Porch Delay Variation vs Temperature Fig. 10 Back Porch Width Variation vs Temperature 25 600 HORIZONTAL DELAY VARIATION (ns) HORIZONTAL WIDTH VARIATION (ns) 500 400 300 200 100 0 -100 -200 -300 -25 -15 -5 5 15 25 35 45 55 65 75 85 20 15 10 5 0 -5 -25 -15 -5 5 15 25 35 45 55 65 75 85 TEMPERATURE ( °C) TEMPERATURE (°C) Fig. 11 Horizontal Delay Variation vs Temperature 520 - 23 - 03 Fig. 12 Horizontal Width Variation vs Temperature 6 CIRCUIT DESPCRIPTION The block diagrams for the GS1881, GS4881 and GS4981, are shown in Figures 17 through 19, with timing diagrams for the devices shown in Figure 20. When stimulated by a composite input signal, the GS1881 and GS4881 sync separators output composite sync, vertical sync, back porch, and odd/even field information. The GS4981 substitutes the odd/even output of the GS4881 with a horizontal output. An external resistor on pin 6 is used to define internal currents allowing the devices to accommodate horizontal scan rates from 15 kHz to 130 kHz. COMPOSITE VIDEO INPUT (pin 2) and COMPOSITE SYNC OUTPUT (pin 1) Composite video is AC coupled via an external coupling capacitor to pin 2. The device clamps the sync tip of the input video to 1.5 V ( Vclamp ) and then slices at 77 mV above the clamp voltage ( V slice ) . The resultant signal, provided at pin 1, is a reproduction of the input signal with the active video portion removed. As Vclamp and Vslice are supply and input signal independent, for 0.5 V p-p signals (sync height of 143 mV) slicing will occur at just above the 50% point and for 2 V p-p signals (sync height of 572 mV) slicing will occur at approximately 13% of sync height. The video signal path and composite sync slicing circuitry have been optimized and compensated to achieve a low propagation delay that is stable over temperature. The typical delay is 60 ns with less than 3 ns drift over the commercial temperature range. The typical input clamp discharge current is 11 µA. This current is optimal under normal operating circumstances but needs to be increased when the clamp is trying to recover from negative going impulse noise. The device improves the recovery time by raising a NOSYNC flag when there has not been a sync pulse for approximately 11/2 horizontal lines. When this flag is raised the discharge current is increased by 85 µA so that the recovery time is sped up by nearly 10 times. Figure 13 shows a comparison between the recovery times with and without the increased discharge current. VIDEO INPUT BACK PORCH OUTPUT (pin 5) In an NTSC composite video signal, horizontal sync pulses are followed by the back porch interval. The device generates a negative going pulse on pin 5 during this time. It is delayed typically 500 ns from the rising edge of sync and has a typical width of 2.5 µs. Both of these times are set by the external RSET resistor. During the pre-equalizing, vertical sync, and post-equalizing periods, composite sync doubles in frequency. The GS4881 and GS4981 maintain the back porch output at the horizontal rate due to Back Porch Enable (BPEN), generated by the internal windowing circuit, which forces back porch to be asserted at the horizontal rate. This gating circuit is also the reason for the excellent impulse noise immunity of the back porch output as shown in Figure 14. Video Input Impulse Noise Back Porch Output GS4881 GS4981 Fig. 14 Back Porch Noise Immunity The GS1881 does not gate the Back Porch which allows for total pin compatibility with the LM1881. VERTICAL SYNC OUTPUT (pin 3) The vertical sync interval is detected by integrating the composite sync pulses. The first broad vertical sync pulse causes an internal capacitor to charge past a fixed threshold and raises an internal vertical flag. Once the vertical flag is raised, the positive edge of the next serration clocks out the vertical output. When the vertical sync interval ends, the first post equalizing pulse is unable to charge the capacitor sufficiently, causing the internal vertical flag to go high. The rising edge of the second post-equalizing pulse then clocks out the high flag to end the vertical sync pulse. The vertical output is clocked in and out and therefore is a fixed width of 197.7 µs (3H + 4.7 µs + 2.3 µs). In the case of a non-standard vertical interval that has no serrations, a second internal capacitor is charged and clocks the vertical pulse out after typically 65 µs. In this case the end of the vertical pulse will still be the rising edge of the second post-equalizing pulse. As the vertical detector is designed as a true integrator, it provides improved noise immunity. IMPULSE NOISE COMPOSITE SYNC RECOVERY TIME without INCREASED DISCHARGE CURRENT (LM1881) RECOVERY TIME T1 COMPOSITE SYNC RECOVERY TIME with INCREASED DISCHARGE CURRENT (GS1881, GS4881, GS4981) RECOVERY TIME T1 / 10 Fig. 13 Impulse Noise: Recovery Time Comparison 7 520 - 23 - 03 ODD/EVEN FIELD OUTPUT (pin 7 GS1881, GS4881) NTSC PAL and SECAM composite video standards are interlaced video schemes and therefore have odd and even fields. For odd fields the first broad vertical sync pulse is coincident with the start of horizontal, while for even fields the first broad vertical sync pulse starts in the middle of a horizontal line. Therefore by comparing the vertical sync with an internally generated horizontal sync the odd/even field information is determined. This output is clocked out by the falling edge of vertical sync. The odd/even output is low during even fields and high during odd fields. This method of detecting odd and even fields is very noise tolerant. Noise during the pre-equalizing pulses does not affect the output since the field decision is made at the beginning of the vertical interval. This noise immunity is displayed in Figure 15 in which an extra pre-equalizing pulse has been added to the video input with no negative effect on the odd/even field information. HORIZONTAL OUTPUT (pin 7 GS4981) As mentioned above, the odd/even field output of the GS1881 and GS4881 is generated by comparing vertical sync with an internal horizontal sync signal. This horizontal sync signal is a true horizontal signal (i.e. maintained during the vertical interval) and is outputted on pin 7 for the GS4981. A delay of 190 ns from the video input and a width of 6.5 µs are typically characteristics for this signal. The windowing circuit which generates horizontal provides excellent impulse noise immunity as shown in Figure 16. This output buffer is an open collector stage with an internal 10 kΩ pull up resistor. Video Input Impulse Noise Video Input Horizontal Output Impulse Noise Even Odd Fig. 16 Horizontal Output Odd/Even Output Fig. 15 Odd/Even Output 520 - 23 - 03 8 C SYNC VIDEO INPUT (Pin 2) V SLICE COMPOSITE SYNC OUTPUT (Pin 1) + HORIZONTAL + V CLAMP + WINDOWING CIRCUIT D Q D Q ODD / EVEN OUTPUT (Pin 7) G Q CLK Q 11µ 85µ NOSYNC VCC (Pin 8) D VOLTAGE REGULATOR 1.2V Q VERTICAL DETECTOR VERTICAL SYNC OUTPUT (PIN 3) CLK Q R_SET (Pin 6) BACK PORCH OUTPUT (Pin 5) BACK PORCH DETECTOR TIMING CURRENTS Fig. 17 GS1881 Block Diagram C SYNC VIDEO INPUT (Pin 2) V SLICE COMPOSITE SYNC OUTPUT (Pin 1) + HORIZONTAL + V CLAMP + WINDOWING CIRCUIT D Q D Q ODD / EVEN OUTPUT (Pin 7) G Q CLK Q 11µ 85µ NOSYNC B PEN VCC (Pin 8) VOLTAGE REGULATOR D VERTICAL DETECTOR Q VERTICAL SYNC OUTPUT (PIN 3) CLK Q 1.2V R_SET (Pin 6) BACK PORCH OUTPUT (Pin 5) BACK PORCH DETECTOR TIMING CURRENTS Fig. 18 GS4881 Block Diagram 9 520 - 23 - 03 C SYNC VIDEO INPUT (Pin 2) V1 COMPOSITE SYNC OUTPUT (Pin 1) + 10k + V2 + WINDOWING CIRCUIT HORIZONTAL OUTPUT (Pin 7) 11µ 85µ NOSYNC B PEN VCC (Pin 8) VOLTAGE REGULATOR 1.2V D Q VERTICAL DETECTOR VERTICAL SYNC OUTPUT (PIN 3) CLK Q BACK PORCH OUTPUT (Pin 5) BACK PORCH DETECTOR R_SET (Pin 6) TIMING CURRENTS Fig. 19 GS4981 Block Diagram 525 1 2 3 4 5 6 7 8 COMPOSITE VIDEO INPUT COMPOSITE SYNC OUTPUT GS1881, GS4881, GS4981 BACK PORCH OUTPUT GS4881, GS4981 BACK PORCH OUTPUT GS1881 HORIZONTAL OUTPUT GS4981 VERTICAL SYNC OUTPUT GS1881, GS4881, GS4981 ODD/EVEN OUTPUT GS1881, GS4881 600ns 2.5µs COMPOSITE VIDEO INPUT BACK PORCH OUTPUT 500ns 2.5µs Fig. 20 GS1881, GS4881, GS4981 Video Sync Separator Timing Diagram 520 - 23 - 03 10 APPLICATION NOTES (1) Choosing the Appropriate Input Coupling Capacitor to Optimize Slicing Level and Hum Rejection The video designer can adjust the slicing level by choosing the value of the input coupling capacitor. The relationship between slicing level and input coupling capacitor is described by the following equation. ∆VSLICE = where: IDIS CC ∆T = VDROOP SLICING LEVEL (mV) 137 127 117 107 97 87 77 0.01 0.02 IDIS = clamp discharge current = 11 µA ∆T = TLINE - TSYNC = (63.5 µs - 4.7 µs) CC = input coupling capacitor 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 INPUT COUPLING CAPACITOR (µF) Fig. 21 Slicing Level vs Input Coupling Capacitor Figure 21 is a graphical representation of this equation and photographs 1 and 2 show the input video waveforms for 0.1 µF and 0.01 µF input capacitors respectively. The advantage in choosing a smaller input coupling capacitor, is increased hum rejection as the following analyses illustrates. CH1 CH1 CH2 VIDEO 2 0.1µF 75Ω 8 CH2 6 4 680k 0.1µ Test Circuit 1 Photograph 1 CH1 CH1 CH2 VIDEO 2 0.01µF 75Ω 8 CH2 6 4 680k 0.1µ Test Circuit 2 Photograph 2 11 520 - 23 - 03 The interfering hum component is defined by: vHUM(t) = V P cos(2π ƒ HUMt) where: VP = Peak voltage of AC hum ƒHUM = Frequency of hum (50 Hz or 60 Hz) The maximum rate of change of this hum signal occurs at the zero crossing points and is: verifying that there is enough clamping current ∆Vt = 29.4 mV + 29.4 mV = 58.8 mV ... i = 0.022 µ ( 58.8 mV ) = 275 µA 4.7 µ which is less than 650 µA. (2) FIltering dvHUM dt π 3π t=2, 2 = ± V P2 π ƒHUM Since the horizontal scan period is much faster than the period of the interference ( 63.5 µs ∆ VHUM. VDROOP is increased by decreasing the input coupling capacitor value. Therefore the video designer can increase hum rejection by decreasing the value of this capacitor. The following is a numerical example: choosing C ... VDROOP = c ) (TSYNC) = (IDIS) (TLINE - TSYNC) (4.7 µs) = (11 µA) (63. 5 µs - 4.7 µs) AVG AVG ... ICLAMP = 137.6 µA This clamp current flows in the source resistance causing a voltage drop equal to : VCLIP = ( ICLAMP AVG ) (RS) = (137.6 µ) (RS) = 0.022 µF 11 (63.5 µ - 4.7 µ) = 29.4 mV 0.022 VIDEO INPUT 75Ω ICLAMP RS VCLIP + CC Cƒ 4 2 6 680k 0.1µ 8 the maximum amount of 60 Hz hum that could be rejected would be when: ∆VDROOP = ∆VHUM = VP 2πƒHUM TLINE ... VP = ∆VDROOP 29.4mV = =1.23vPEAK HUM Fig. 22 Simple Chrominance Filtering 2 π ƒHUM TLINE 2 π(60) (63.5 µ ) 520 - 23 - 03 12 Photograph 3 shows the amount of sync clipping for a 560 Ω source resistor. A graph of V CLIP v ersus R S i s shown in Figure 23, and Figure 24 shows the corresponding capacitor value for a particular series resistor to provide a corner frequency of 500 kHz. In applications where signal levels are small the amount of attenuation should be minimized. It follows from Figure 23 and Figure 24 that in order to minimize attenuation a small series resistor and a larger capacitor to ground should be chosen. This however, increases the capacitive loading of the signal source. CH1 VIDEO 2 560Ω 75Ω 0.1µF CH2 8 Another way to minimize the amount of attenuation is to control the source resistance seen by the sync separator by using a PNP emitter follower (Figure 25). A PNP emitter follower works well to drive the sync separator, and does not require much DC current because the transistor provides the current when it is needed during sync. Figure 26 is a typical application circuit that minimizes sync tip clipping. CH1 6 4 CH2 680k 0.1µ Test Circuit 3 Photograph 3 100 90 80 70 10 9 8 7 VCLIP (mV) 50 40 30 20 10 0 0 100 200 300 400 500 600 700 Cƒ (nF) 60 6 5 4 3 2 1 0 0 100 200 300 400 500 600 700 SERIES RESISTOR (Ω) SERIES RESISTOR (Ω) Fig. 23 V CLIP vs Series Resistor Fig. 24 Cƒ vs Series Resistor VCC 5.6k VIDEO INPUT FILTER 75Ω -5V CC 4 6 680k 0.1µ 8 2 VCC 5.6k VIDEO INPUT 8 5.6k 2 CC 4 75Ω 56p -5V 6 680k 0.1µ Fig. 25 PNP Emitter Follower Buffer Fig. 26 Typical NTSC Application Circuit 13 520 - 23 - 03 (3) Deriving Odd/Even Using the GS4981 Odd/even field information can be derived using the vertical and horizontal outputs from the GS4981 along with an external positive edge D flip/flop. The horizontal output is used as the D input and the vertical output as the clock, as shown in Figure 27. At the start of an odd field the vertical output ends in the middle of the horizontal line and a high will be latched. At the start of an even field, the vertical output ends near the beginning of the horizontal line and since the horizontal output is low, a low will be latched. This timing sequence is shown in Figure 28. COMPOSITE SYNC OUTPUT 0.1µF COMPOSITE VIDEO INPUT VERTICAL SYNC OUTPUT GS4981 1 2 3 4 8 7 6 0.1µF 5 VCC 5 - 12V HORIZONTAL 680kΩ R SET BACK PORCH OUTPUT D FLIP/FLOP D Q Q ODD/EVEN OUTPUT Fig. 27 Derivation of Odd/Even with GS4981 START OF ODD FIELD 525 1 2 3 4 5 6 7 8 COMPOSITE VIDEO INPUT HORIZONTAL OUTPUT GS4981 VERTICAL SYNC OUTPUT GS4981 ODD/EVEN OUTPUT START OF EVEN FIELD 263 264 265 266 267 268 269 270 COMPOSITE VIDEO INPUT HORIZONTAL GS4981 VERTICAL SYNC OUTPUT GS4981 ODD/EVEN OUTPUT Fig. 28 Timing Diagram DOCUMENT IDENTIFICATION PRODUCT PROPOSAL This data has been compiled for market investigation purposes only, and does not constitute an offer for sale. ADVANCE INFORMATION NOTE This product is in development phase and specifications are subject to change without notice. Gennum reserves the right to remove the product at any time. Listing the product does not constitute an offer for sale. PRELIMINARY The product is in a preproduction phase and specifications are subject to change without notice. REVISION NOTES The only change from 520-23-02 to 520-23-03 is that the document has been upgraded to a full DATA SHEET. It is no longer Preliminary. DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. © Copyright March 1991 Gennum Corporation. All rights reserved. V CLK Printed in Canada. 520 - 23 - 03 14