GS2962 3G/HD/SD-SDI Serializer with Complete SMPTE Video Support
Key Features
•
•
•
Operation at 2.970Gb/s, 2.970/1.001Gb/s, 1.485Gb/s,
1.485/1.001Gb/s and 270Mb/s
Application: Dual Link (HD-SDI)
to Single Link (3G-SDI) Converter
HD-SDI
Link A
Supports SMPTE 425M (Level A and Level B), SMPTE
424M, SMPTE 292, SMPTE 259M-C and DVB-ASI
EQ
GS2974B
EQ
GS2974B
•
Integrated, low noise VCO
•
Integrated Narrow-Bandwidth PLL
•
Ancillary data insertion
•
Optional conversion from SMPTE 425M Level A to
Level B for 1080p 50/60 4:2:2 10-bit
•
Parallel data bus selectable as either 20-bit or 10-bit
•
SMPTE video processing including TRS calculation and
insertion, line number calculation and insertion, line
based CRC calculation and insertion, illegal code
re-mapping, SMPTE 352M payload identifier
generation and insertion
10-bit
10-bit
FIFO
HV F/PCLK
W
3G-SDI
R
HV F/PCLK
HD-SDI
Link B
Integrated Cable Driver
HD-SDI
Deserializer
(GS1559 or
GS2970)
HD-SDI
Deserializer
(GS1559 or
GS2970)
GS2962
10-bit
10-bit
FIFO
HV F/PCLK
W
HV F
R
GS4910
X TAL
Description
The GS2962 is a complete SDI Transmitter, generating a
SMPTE 424M, SMPTE 292, SMPTE 259M-C or DVB-ASI
compliant serial digital output signal.
The integrated narrow-BW PLL allows the device to accept
parallel clocks with high input jitter, and still provide a
SMPTE compliant serial digital output.
•
GSPI host interface
•
1.2V digital core power supply, 1.2V and 3.3V analog
power supplies, and selectable 1.8V or 3.3V I/O power
supply
The device can operate in four basic user selectable modes:
SMPTE mode, DVB-ASI mode, Data-Through mode, or
Standby mode.
•
-20ºC to +85ºC operating temperature range
•
Low power operation (typically at 400mW, including
Cable Driver)
•
Small 11mm x 11mm 100-ball BGA package
In SMPTE mode, the GS2962 performs all SMPTE
processing features. Both SMPTE 425M Level A and Level B
formats are supported with optional conversion from Level
A to Level B for 1080p 50/60 4:2:2 10-bit.
•
Pb-free and RoHS compliant
In DVB-ASI mode, the device will perform 8b/10b encoding
prior to transmission.
Applications
In Data-Through mode, all SMPTE and DVB-ASI processing
is disabled. The device can be used as a simple parallel to
serial converter.
Application: Single Link (3G-SDI)
to Dual Link (HD-SDI) Converter
10-bit
HD-SDI
GS2962
Link A
HV F/PCLK
3G-SDI
EQ
GS2974
The device can also operate in a lower power Standby
mode. In this mode, no signal is generated at the output.
GS2960
HV F/PCLK
10-bit
HD-SDI
GS2962
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Data Sheet
48005 - 7
October 2010
Link B
The GS2962 integrates a fully SMPTE-compliant Cable
Driver for SMPTE 259M-C, SMPTE 292 and SMPTE 424M
interfaces. It features automatic dual slew-rate selection,
depending on 3Gb/s or HD or SD operational requirements.
www.gennum.com
1 of 82
DVB_ASI
SMPTE_BYPASS
IOPROC_EN/DIS
STANDBY
RESET
IO_GND
IO_VDD
CORE_GND
CORE_VDD
SDIN_TDI
SCLK_TCLK
CS_TMS
SDOUT_TDO
JTAG/HOST
TDO
TDI
TMS
TCK
Dedicated JTAG pins
Shared JTAG and GSPI pins
(for Drop-in Compatibility
with GS1572/82)
Functional Block Diagram
AVDD
JTAG
CONTROLLER
GSPI
Host
Interface
AGND
PLL_VDD
PLL_VDD
VCO_GND
VCO_GND
CD_VDD
CD_GND
ANC_BLANK
F/DE
V/VSYNC
H/HSYNC
TIM_861
20BIT/10BIT
DIN[19:0]
PCLK
RSET
SMPTE 425M
Input
Mux/
Demux
Level A
Level B
1080p 50/60 4:2:2 10-bit
HANC/
VANC
Blanking
SMPTE 352M
Generation
and Insertion
ANC Data
Insertion
TRS , Line
Number
and CRC
Insertion
EDH
Packet
Insertion
NRZ/NRZI
SMPTE
Scrambler
Mux
Parallel to Serial
Converter
SMPTE
Cable
Driver
SDO
SDO
SDO_EN/DIS
DVB-ASI
8b/10b
Encoder
PLL with Low Noise
VCO
LOCKED
ClockCleaner™
LF
RATE_SEL[1:0]
VBG
Figure A: GS2962 Functional Block Diagram
Revision History
Version
ECR
PCN
7
155080
56059
6
153717
5
Date
Changes and/or Modifications
October 2010
Revised power rating in standby mode. Documented
CSUM behaviour in Section 4.7, Section 4.8.4 and
Configuration and Status Registers.
−
March 2010
Updates throughout entire document. Added
Figure 4-2, Figure 4-3 and Figure 4-4. Correction to
registers 040h to 13Fh in Table 4-16: Configuration and
Status Registers.
152224
−
July 2009
Updated Device Latency numbers in 2.4 AC Electrical
Characteristics. Updates to 4.7 ANC Data Insertion.
Replaced 7.3 Marking Diagram.
4
151319
−
January 2009
Correction to timing values in Table 4-1: GS2962 Digital
Input AC Electrical Characteristics.
3
150802
−
December 2008
Conversion to Data Sheet.
2
150720
−
October 2008
Conversion to Preliminary Data Sheet.
1
148587
−
September 2008
New Document.
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Data Sheet
48005 - 7
October 2010
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Contents
Key Features........................................................................................................................................................1
Applications.........................................................................................................................................................1
Description...........................................................................................................................................................1
Functional Block Diagram ..............................................................................................................................2
Revision History .................................................................................................................................................2
1. Pin Out...............................................................................................................................................................7
1.1 Pin Assignment ..................................................................................................................................7
1.2 Pin Descriptions ................................................................................................................................8
2. Electrical Characteristics ......................................................................................................................... 15
2.1 Absolute Maximum Ratings ....................................................................................................... 15
2.2 Recommended Operating Conditions .................................................................................... 15
2.3 DC Electrical Characteristics ..................................................................................................... 16
2.4 AC Electrical Characteristics ..................................................................................................... 18
3. Input/Output Circuits ............................................................................................................................... 21
4. Detailed Description.................................................................................................................................. 26
4.1 Functional Overview .................................................................................................................... 26
4.2 Parallel Data Inputs ....................................................................................................................... 27
4.2.1 Parallel Input in SMPTE Mode....................................................................................... 28
4.2.2 Parallel Input in DVB-ASI Mode................................................................................... 29
4.2.3 Parallel Input in Data-Through Mode......................................................................... 29
4.2.4 Parallel Input Clock (PCLK) ............................................................................................ 30
4.3 SMPTE Mode ................................................................................................................................... 31
4.3.1 H:V:F Timing ....................................................................................................................... 31
4.3.2 CEA 861 Timing.................................................................................................................. 33
4.4 DVB-ASI Mode ............................................................................................................................... 40
4.5 Data-Through Mode ..................................................................................................................... 41
4.6 Standby Mode ................................................................................................................................. 41
4.7 ANC Data Insertion ....................................................................................................................... 41
4.7.1 ANC Insertion Operating Modes .................................................................................. 42
4.7.2 3G ANC Insertion............................................................................................................... 43
4.7.3 HD ANC Insertion.............................................................................................................. 45
4.7.4 SD ANC Insertion............................................................................................................... 46
4.8 Additional Processing Functions .............................................................................................. 47
4.8.1 Video Format Detection .................................................................................................. 47
4.8.2 3G Format Detection ........................................................................................................ 50
4.8.3 ANC Data Blanking ........................................................................................................... 52
4.8.4 ANC Data Checksum Calculation and Insertion..................................................... 53
4.8.5 TRS Generation and Insertion ....................................................................................... 53
4.8.6 HD and 3G Line Number Calculation and Insertion.............................................. 54
4.8.7 Illegal Code Re-Mapping................................................................................................. 54
4.8.8 SMPTE 352M Payload Identifier Packet Insertion.................................................. 54
4.8.9 Line Based CRC Generation and Insertion (HD/3G) .............................................. 55
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Data Sheet
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October 2010
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4.8.10 EDH Generation and Insertion ................................................................................... 55
4.8.11 SMPTE 372M Conversion ............................................................................................. 56
4.8.12 Processing Feature Disable.......................................................................................... 56
4.9 Serial Digital Output ..................................................................................................................... 57
4.9.1 Output Signal Interface Levels...................................................................................... 58
4.9.2 Overshoot/Undershoot.................................................................................................... 58
4.9.3 Slew Rate Selection........................................................................................................... 59
4.9.4 Serial Digital Output Mute.............................................................................................. 59
4.10 Serial Clock PLL ........................................................................................................................... 59
4.10.1 PLL Bandwidth................................................................................................................. 60
4.10.2 Lock Detect........................................................................................................................ 61
4.11 GSPI Host Interface ..................................................................................................................... 61
4.11.1 Command Word Description ...................................................................................... 62
4.11.2 Data Read or Write Access........................................................................................... 63
4.11.3 GSPI Timing....................................................................................................................... 64
4.12 Host Interface Register Maps .................................................................................................. 66
4.13 JTAG ID Codeword ..................................................................................................................... 76
4.14 JTAG Test Operation .................................................................................................................. 76
4.15 Device Power-Up ........................................................................................................................ 76
4.16 Device Reset .................................................................................................................................. 76
5. Application Reference Design ............................................................................................................... 77
5.1 Typical Application Circuit ........................................................................................................ 77
6. References & Relevant Standards ......................................................................................................... 78
7. Package & Ordering Information .......................................................................................................... 79
7.1 Package Dimensions ..................................................................................................................... 79
7.2 Packaging Data ............................................................................................................................... 80
7.3 Marking Diagram ........................................................................................................................... 80
7.4 Solder Reflow Profiles .................................................................................................................. 81
7.5 Ordering Information ................................................................................................................... 81
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Data Sheet
48005 - 7
October 2010
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List of Figures
Figure 3-1: Differential Output Stage....................................................................................................... 21
Figure 3-2: Digital Input Pin ........................................................................................................................ 21
Figure 3-3: Digital Input Pin with Schmitt Trigger............................................................................... 22
Figure 3-4: Digital Input Pin with weak pull-down............................................................................. 22
Figure 3-5: Digital Input Pin with weak pull-up................................................................................... 23
Figure 3-6: Bidirectional Digital Input/Output Pin with programmable drive strength......... 23
Figure 3-7: Bidirectional Digital Input/Output Pin with programmable drive strength ........ 24
Figure 3-8: VBG .............................................................................................................................................. 24
Figure 3-9: Loop Filter .................................................................................................................................. 25
Figure 4-1: GS2962 Video Host Interface Timing Diagrams ............................................................ 27
Figure 4-2: H:V:F Output Timing - 3G Level A and HDTV 20-bit Mode ...................................... 32
Figure 4-3: H:V:F Output Timing - 3G Level A and HDTV 10-bit Mode
3G Level B 20-bit Mode, each 10-bit stream ......................................................................................... 32
Figure 4-4: H:V:F Output Timing - 3G Level B 10-bit Mode ............................................................. 32
Figure 4-5: H:V:F Input Timing - HD 20-bit Input Mode ................................................................... 32
Figure 4-6: H:V:F Input Timing - HD 10-bit Input Mode ................................................................... 33
Figure 4-7: H:V:F Input Timing - SD 20-bit Mode ............................................................................... 33
Figure 4-8: H:V:F Input Timing - SD 10-bit Mode ............................................................................... 33
Figure 4-9: H:V:DE Input Timing 1280 x 720p @ 59.94/60 (Format 4) ........................................ 35
Figure 4-10: H:V:DE Input Timing 1920 x 1080i @ 59.94/60 (Format 5) ..................................... 35
Figure 4-11: H:V:DE Input Timing 720 (1440) x 480i @ 59.94/60 (Format 6&7) ....................... 36
Figure 4-12: H:V:DE Input Timing 1280 x 720p @ 50 (Format 19) ................................................ 36
Figure 4-13: H:V:DE Input Timing 1920 x 1080i @ 50 (Format 20) ............................................... 37
Figure 4-14: H:V:DE Input Timing 720 (1440) x 576 @ 50 (Format 21&22) ................................ 38
Figure 4-15: H:V:DE Input Timing 1920 x 1080p @ 59.94/60 (Format 16) ................................. 38
Figure 4-16: H:V:DE Input Timing 1920 x 1080p @ 50 (Format 31) .............................................. 39
Figure 4-17: H:V:DE Input Timing 1920 x 1080p @ 23.94/24 (Format 32) ................................. 39
Figure 4-18: H:V:DE Input Timing 1920 x 1080p @ 25 (Format 33) .............................................. 40
Figure 4-19: H:V:DE Input Timing 1920 x 1080p @ 29.97/30 (Format 34) ................................. 40
Figure 4-20: ORL Matching Network, BNC and Coaxial Cable Connection ............................... 58
Figure 4-21: GSPI Application Interface Connection ........................................................................ 62
Figure 4-22: Command Word Format ..................................................................................................... 62
Figure 4-23: Data Word Format ................................................................................................................ 63
Figure 4-24: Write Mode .............................................................................................................................. 64
Figure 4-25: Read Mode ............................................................................................................................... 64
Figure 4-26: GSPI Time Delay .................................................................................................................... 64
Figure 4-27: Reset Pulse ............................................................................................................................... 76
Figure 7-1: Pb-free Solder Reflow Profile .............................................................................................. 81
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Data Sheet
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October 2010
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List of Tables
Table 1-1: Pin Descriptions ............................................................................................................................ 8
Table 2-1: Absolute Maximum Ratings................................................................................................... 15
Table 2-2: Recommended Operating Conditions................................................................................ 15
Table 2-3: DC Electrical Characteristics ................................................................................................. 16
Table 2-4: AC Electrical Characteristics ................................................................................................. 18
Table 4-1: GS2962 Digital Input AC Electrical Characteristics ....................................................... 27
Table 4-2: GS2962 Input Video Data Format Selections................................................................... 27
Table 4-3: GS2962 PCLK Input Rates....................................................................................................... 30
Table 4-4: CEA861 Timing Formats ......................................................................................................... 34
Table 4-5: Supported Video Standards................................................................................................... 48
Table 4-6: SMPTE 352M Packet Data....................................................................................................... 52
Table 4-7: IOPROC Register Bits................................................................................................................ 57
Table 4-7: Serial Digital Output - Serial Output Data Rate............................................................... 57
Table 4-8: RSET Resistor Value vs. Output Swing................................................................................. 58
Table 4-9: Serial Digital Output - Overshoot/Undershoot ............................................................... 59
Table 4-10: Serial Digital Output - Rise/Fall Time............................................................................... 59
Table 4-11: PCLK and Serial Digital Clock Rates ................................................................................. 60
Table 4-12: GS2962 PLL Bandwidth......................................................................................................... 60
Table 4-13: GS2962 Lock Detect Indication .......................................................................................... 61
Table 4-14: GSPI Time Delay...................................................................................................................... 64
Table 4-15: GSPI AC Characteristics........................................................................................................ 65
Table 4-16: Configuration and Status Registers................................................................................... 66
Table 7-1: Packaging Data........................................................................................................................... 80
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Data Sheet
48005 - 7
October 2010
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1. Pin Out
1.1 Pin Assignment
1
2
A
DIN17
DIN18
B
DIN15
C
3
4
5
6
7
8
9
10
F/DE
H/HSYNC
CORE
_VDD
PLL_
VDD
LF
VBG
RSV
A_VDD
DIN16
DIN19
PCLK
CORE
_GND
PLL_
VDD
VCO_
VDD
VCO_
GND
A_GND A_GND
DIN13
DIN14
DIN12
V/VSYNC
CORE
_GND
PLL_
GND
PLL_
GND
PLL_
GND
CD_GND
SDO
D
DIN11
DIN10
STANDBY
SDO_
EN/DIS
CORE
_GND
RSV
RSV
RSV
CD_GND
SDO
E
CORE
_VDD
CORE
_GND
RATE_
SEL0
RATE_
SEL1
CORE
_GND
CORE
_GND
TDI
TMS
CD_GND CD_VDD
F
DIN9
DIN8
DETECT
_TRS
CORE
_GND
CORE
_GND
CORE
_GND
CORE
_GND
TDO
CD_GND
RSET
CORE
_GND
CORE
_VDD
G
IO_VDD IO_GND TIM_861
SMPTE_ IOPROC
20bit/
DVB_ASI
RESET
BYPASS _EN/DIS
10bit
CORE
_GND
CORE
_GND
RSV
JTAG/
HOST
IO_GND IO_VDD
RSV
RSV
RSV
RSV
TCK
SDOUT_ SCLK_
TDO
TCK
RSV
RSV
RSV
RSV
CORE
_VDD
ANC_
LOCKED
BLANK
H
DIN7
DIN6
J
DIN5
DIN4
DIN1
K
DIN3
DIN2
DIN0
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Data Sheet
48005 - 7
October 2010
CS_
TMS
SDIN_
TDI
7 of 82
1.2 Pin Descriptions
Table 1-1: Pin Descriptions
Pin
Number
Name
A1, A2, B1,
B2, B3, C1,
C2, C3, D1,
D2
DIN[19:10]
Timing
Type
Input
Description
PARALLEL DATA BUS
Signal levels are LVCMOS / LVTTL compatible.
20-bit mode
20BIT/10BIT = HIGH
Data Stream 1/Luma data input in
SMPTE mode (SMPTE_BYPASS = HIGH)
Data input in data through mode
(SMPTE_BYPASS = LOW)
10-bit mode
20BIT/10BIT = LOW
Multiplexed Data Stream 1/Luma and
Data Stream 2/Chroma data input in
SMPTE mode
(SMPTE_BYPASS = HIGH)
Data input in data through mode
(SMPTE_BYPASS = LOW)
DVB-ASI data input in DVB-ASI mode
(SMPTE_BYPASS = LOW)
(DVB_ASI = HIGH)
A3
F/DE
Synchronous
with
PCLK
Input
PARALLEL DATA TIMING.
Signal levels are LVCMOS / LVTTL compatible.
TIM_861 = LOW:
Used to indicate the ODD / EVEN field of the video signal when
DETECT_TRS is set LOW. The device will set the F bit in all outgoing
TRS signals for the entire period that the F input signal is HIGH
(IOPROC_EN/DIS must also be HIGH).
The F signal should be set HIGH for the entire period of field 2 and
should be set LOW for all lines in field 1 and for all lines in
progressive scan systems.
The F signal is ignored when DETECT_TRS = HIGH.
TIM_861 = HIGH:
The DE signal is used to indicate the active video period when
DETECT_TRS is set LOW. DE is HIGH for active data and LOW for
blanking. See Section 4.3 and Section 4.3.2 for timing details.
The DE signal is ignored when DETECT_TRS = HIGH.
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Data Sheet
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October 2010
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Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
A4
H/HSYNC
Synchronous
with
PCLK
Input
PARALLEL DATA TIMING.
Signal levels are LVCMOS / LVTTL compatible.
TIM_861 is LOW:
The H signal is used to indicate the portion of the video line
containing active video data, when DETECT_TRS is set LOW.
Active Line Blanking
The H signal should be LOW for the active portion of the video line.
The signal goes LOW at the first active pixel of the line, and then
goes HIGH after the last active pixel of the line.
The H signal should be set HIGH for the entire horizontal blanking
period, including both EAV and SAV TRS words, and LOW otherwise.
TRS Based Blanking (H_CONFIG = 1h)
The H signal should be set HIGH for the entire horizontal blanking
period as indicated by the H bit in the received TRS ID words, and
LOW otherwise.
TIM_861 = HIGH:
The HSYNC signal indicates horizontal timing. See Section 4.3.
When DETECT_TRS is HIGH, this pin is ignored at all times.
If DETECT_TRS is set HIGH and TIM_861 is set HIGH, the DETECT_TRS
feature will take priority.
A5, E1, G10,
K8
CORE_VDD
Input Power
Power supply connection for digital core logic. Connect to 1.2V DC
digital.
A6, B6
PLL_VDD
Input Power
Power supply pin for PLL. Connect to 1.2V DC analog.
A7
LF
Analog
Output
Loop Filter component connection.
A8
VBG
Output
Bandgap voltage filter connection.
A9, D6, D7,
D8, H7, J4,
J5, J6, J7,
K4, K5, K6,
K7
RSV
−
A10
A_VDD
Input Power
B4
PCLK
Input
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Data Sheet
48005 - 7
October 2010
These pins are reserved and should be left unconnected.
VDD for sensitive analog circuitry. Connect to 3.3VDC analog.
PARALLEL DATA BUS CLOCK.
Signal levels are LVCMOS / LVTTL compatible.
3G 20-bit mode
PCLK @ 148.5MHz
3G 10-bit mode DDR
PCLK @ 148.5MHz
HD 20-bit mode
PCLK @ 74.25MHz
HD 10-bit mode
PCLK @ 148.5MHz
SD 20-bit mode
PCLK @ 13.5MHz
SD 10-bit mode
PCLK @ 27MHz
DVB-ASI mode
PCLK @ 27MHz
9 of 82
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
B5, C5, D5,
E2, E5, E6,
F4, F5, F6,
F7, G9, H5,
H6
CORE_GND
Input Power
Reserved. Connect to CORE_GND.
B7
VCO_VDD
Input Power
Power pin for VCO. Connect to 1.2V DC analog followed by an RC
filter (see Typical Application Circuit on page 77). VCO_VDD is
nominally 0.7V.
B8
VCO_GND
Input Power
Ground connection for VCO. Connect to analog GND.
B9, B10
A_GND
Input Power
GND pins for sensitive analog circuitry. Connect to analog GND.
C4
V/VSYNC
Synchronous
with
PCLK
Type
Input
Description
PARALLEL DATA TIMING.
Signal levels are LVCMOS / LVTTL compatible.
TIM_861 = LOW:
The V signal is used to indicate the portion of the video field/frame
that is used for vertical blanking, when DETECT_TRS is set LOW.
The V signal should be set HIGH for the entire vertical blanking
period and should be set LOW for all lines outside of the vertical
blanking interval.
The V signal is ignored when DETECT_TRS = HIGH.
TIM_861 = HIGH:
The VSYNC signal indicates vertical timing. See Section 4.3 for
timing details.
The VSYNC signal is ignored when DETECT_TRS = HIGH.
C6, C7, C8
PLL_GND
Input Power
Ground connection for PLL. Connect to analog GND.
C9, D9, E9,
F9
CD_GND
Input Power
Ground connection for the serial digital cable driver. Connect to
analog GND.
C10, D10
SDO, SDO
Output
Serial Data Output Signal.
Serial digital output signal operating at 2.97Gb/s, 2.97/1.001Gbs,
1.485Gb/s, 1.485 /1.001Gb/s or 270Mb/s.
The slew rate of the output is automatically controlled to meet
SMPTE 424M, SMPTE 292 and 259M specifications according to the
setting of the RATE_SEL0 and RATE_SEL1 pins.
D3
STANDBY
Input
Standby input.
HIGH to place the device in Standby mode.
D4
SDO_EN/DIS
Input
CONTROL SIGNAL INPUT.
Signal levels are LVCMOS / LVTTL compatible.
Used to enable or disable the serial digital output stage.
When SDO_EN/DIS is LOW, the serial digital output signals SDO and
SDO are disabled and become high impedance.
When SDO_EN/DIS is HIGH, the serial digital output signals SDO and
SDO are enabled.
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Data Sheet
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October 2010
10 of 82
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
E3, E4
RATE_SEL0,
RATE_SEL1
Timing
Type
Description
Input
CONTROL SIGNAL INPUT.
Signal levels are LVCMOS/LVTTL compatible.
Used to configure the operating data rate.
RATE_SEL0
E7
TDI
Input
Data Rate
RATE_SEL1
0
0
1.485 or 1.485/1.001Gb/s
0
1
2.97 or 2.97/1.001Gb/s
1
X
270Mb/s
COMMUNICATION SIGNAL INPUT.
Signal levels are LVCMOS/LVTTL compatible.
Dedicated JTAG pin.
Test data in.
This pin is used to shift JTAG test data into the device when the
JTAG/HOST pin is LOW.
E8
TMS
Input
COMMUNICATION SIGNAL INPUT.
Signal levels are LVCMOS/LVTTL compatible.
Dedicated JTAG pin.
Test mode start.
This pin is JTAG Test Mode Start, used to control the operation of
the JTAG test when the JTAG/HOST pin is LOW.
E10
CD_VDD
Input Power
F1, F2, H1,
H2, J1, J2,
J3, K1, K2,
K3
DIN[9:0]
Input
Power for the serial digital cable driver. Connect to 3.3V DC analog.
PARALLEL DATA BUS.
Signal levels are LVCMOS / LVTTL compatible.
In 10-bit mode, these pins are not used.
20-bit mode
20BIT/10BIT = HIGH
Data Stream 2/Chroma data input in
SMPTE mode SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data input in data through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
Not Used in DVB-ASI mode
SMPTE_BYPASS = LOW
DVB_ASI = HIGH
10-bit mode
20BIT/10BIT = LOW
F3
DETECT_TRS
Input
Not used.
CONTROL SIGNAL INPUT.
Signal levels are LVCMOS / LVTTL compatible.
Used to select external HVF timing mode or TRS extraction timing
mode.
When DETECT_TRS is LOW, the device extracts all internal timing
from the supplied H:V:F or CEA-861 timing signals, dependent on
the status of the TIM861 pin.
When DETECT_TRS is HIGH, the device extracts all internal timing
from TRS signals embedded in the supplied video stream.
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SMPTE Video Support
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Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
F8
TDO
Timing
Type
Output
Description
COMMUNICATION SIGNAL OUTPUT.
Signal levels are LVCMOS/LVTTL compatible.
Dedicated JTAG pin.
JTAG Test Data Output.
This pin is used to shift results from the device when the JTAG/HOST
pin is LOW.
F10
RSET
Input
An external 1% resistor connected to this input is used to set the
SDO/SDO output signal amplitude.
G1, H10
IO_VDD
Input Power
Power connection for digital I/O. Connect to 3.3V or 1.8V DC digital.
G2, H9
IO_GND
Input Power
Ground connection for digital I/O. Connect to digital GND.
G3
TIM_861
Input
CONTROL SIGNAL INPUT.
Signal levels are LVCMOS / LVTTL compatible.
Used to select external CEA-861 timing mode.
When DETECT_TRS is LOW and TIM-861 is LOW, the device extracts
all internal timing from the supplied H:V:F timing signals.
When DETECT_TRS is LOW and TIM-861 is HIGH, the device extracts
all internal timing from the supplied HSYNC, VSYNC, DE timing
signals.
When DETECT_TRS is HIGH, the device extracts all internal timing
from TRS signals embedded in the supplied video stream.
G4
20bit/10bit
Input
CONTROL SIGNAL INPUT.
Signal levels are LVCMOS/LVTTL compatible.
Used to select the input bus width.
G5
DVB_ASI
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable/disable the DVB-ASI data transmission.
When DVB_ASI is set HIGH and SMPTE_BYPASS is set LOW, then the
device will carry out DVB-ASI word alignment, I/O processing and
transmission.
When SMPTE_BYPASS and DVB_ASI are both set LOW, the device
operates in data-through mode.
G6
SMPTE_BYPASS
Input
CONTROL SIGNAL INPUT.
Signal levels are LVCMOS/LVTTL compatible.
Used to enable / disable all forms of encoding / decoding,
scrambling and EDH insertion.
When set LOW, the device operates in data through mode
(DVB_ASI= LOW), or in DVB-ASI mode (DVB_ASI = HIGH).
No SMPTE scrambling takes place and none of the I/O processing
features of the device are available when SMPTE_BYPASS is set
LOW.
When set HIGH, the device carries out SMPTE scrambling and I/O
processing.
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SMPTE Video Support
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Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
G7
IOPROC_EN/DIS
Timing
Type
Description
Input
CONTROL SIGNAL INPUT.
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable the I/O processing features.
When IOPROC_EN/DIS is HIGH, the I/O processing features of the
device are enabled. When IOPROC_EN/DIS is LOW, the I/O processing
features of the device are disabled.
Only applicable in SMPTE mode.
G8
RESET
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to reset the internal operating conditions to default settings
and to reset the JTAG sequence.
Normal mode (JTAG/HOST = LOW).
When LOW, all functional blocks will be set to default conditions
and all input and output signals become high impedance.
When HIGH, normal operation of the device resumes.
JTAG test mode (JTAG/HOST = HIGH).
When LOW, all functional blocks will be set to default and the JTAG
test sequence will be reset.
When HIGH, normal operation of the JTAG test sequence resumes.
H3
ANC_BLANK
Input
CONTROL SIGNAL INPUT.
Signal levels are LVCMOS / LVTTL compatible.
When ANC_BLANK is LOW, the Luma and Chroma input data is set
to the appropriate blanking levels during the H and V blanking
intervals.
When ANC_BLANK is HIGH, the blanking function is disabled.
Only applicable in SMPTE mode.
H4
LOCKED
Output
STATUS SIGNAL OUTPUT.
Signal levels are LVCMOS / LVTTL compatible.
PLL lock indication.
HIGH indicates PLL is locked.
LOW indicates PLL is not locked.
H8
JTAG/HOST
Input
CONTROL SIGNAL INPUT.
Signal levels are LVCMOS / LVTTL compatible.
Used to select JTAG test mode or host interface mode.
When JTAG/HOST is HIGH, the host interface port is configured for
JTAG test.
When JTAG/HOST is LOW, normal operation of the host interface
port resumes and the separate JTAG pins become the JTAG port.
J8
TCK
Input
COMMUNICATION SIGNAL INPUT.
Signal levels are LVCMOS/LVTTL compatible.
JTAG Serial Data Clock Signal.
This pin is the JTAG clock when the JTAG/HOST pin is LOW.
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SMPTE Video Support
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Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
J9
SDOUT_TDO
Timing
Type
Output
Description
COMMUNICATION SIGNAL OUTPUT.
Signal levels are LVCMOS / LVTTL compatible.
Shared JTAG/HOST pin. Provided for compatibility with the GS1582.
Serial Data Output/Test Data Output.
Host Mode (JTAG/HOST = LOW)
This pin operates as the host interface serial output, used to read
status and configuration information from the internal registers of
the device.
JTAG Test Mode (JTAG/HOST = HIGH)
This pin is used to shift test results and operates as the JTAG test
data output, TDO (for new designs, use the dedicated JTAG port).
NOTE: If the host interface is not being used leave this pin
unconnected.
IO_VDD = 3.3V
Drive Strength = 12mA
IO_VDD = 1.8V
Drive Strength = 4mA
J10
SCLK_TCK
Input
COMMUNICATION SIGNAL INPUT.
Signal levels are LVCMOS / LVTTL compatible.
Shared JTAG/HOST pin. Provided for pin compatibility with GS1582.
Serial data clock signal.
Host Mode (JTAG/HOST = LOW)
SCLK_TCK operates as the host interface burst clock, SCLK.
Command and data read/write words are clocked into the device
synchronously with this clock.
JTAG Test Mode (JTAG/HOST = HIGH)
This pin is the TEST MODE START pin, used to control the operation
of the JTAG test clock, TCK (for new designs, use the dedicated JTAG
port).
NOTE: If the host interface is not being used, tie this pin HIGH.
K9
CS_TMS
Input
COMMUNICATION SIGNAL INPUT.
Signal levels are LVCMOS / LVTTL compatible.
Chip select / test mode start.
JTAG Test mode (JTAG/HOST = HIGH)
CS_TMS operates as the JTAG test mode start, TMS, used to control
the operation of the JTAG test, and is active HIGH (for new designs,
use the dedicated JTAG port).
Host mode (JTAG/HOST = LOW), CS_TMS operates as the host
interface Chip Select, CS, and is active LOW.
K10
SDIN_TDI
Input
COMMUNICATION SIGNAL INPUT.
Signal levels are LVCMOS / LVTTL compatible.
Shared JTAG/HOST pin. Provided for pin compatibility with GS1582.
Serial data in/test data in.
In JTAG mode, this pin is used to shift test data into the device (for
new designs, use the dedicated JTAG port).
In host interface mode, this pin is used to write address and
configuration data words into the device.
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Data Sheet
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2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Table 2-1: Absolute Maximum Ratings
Parameter
Value/Units
Supply Voltage, Digital Core (CORE_VDD)
-0.3V to +1.5V
Supply Voltage, Digital I/O (IO_VDD)
-0.3V to +3.6V
Supply Voltage, Analog 1.2V (PLL_VDD, VCO_VDD)
-0.3V to +1.5V
Supply Voltage, Analog 3.3V (CD_VDD, A_VDD)
-0.3V to +3.6V
Input Voltage Range (RSET)
-0.3V to (CD_VDD + 0.3)V
Input Voltage Range (VBG)
-0.3V to (A_VDD + 0.3)V
Input Voltage Range (LF)
-0.3V to (PLL_VDD + 0.3)V
Input Voltage Range (digital inputs)
-2.0V to +5.25V
Operating Temperature Range
-20°C to +85°C
Functional Temperature Range
-40°C to +85°C
Storage Temperature Range
-40°C to +125°C
Peak Reflow Temperature (JEDEC J-STD-020C)
260°C
ESD Sensitivity, HBM (JESD22-A114)
2kV
NOTES:
Absolute Maximum Ratings are those values beyond which damage may occur. Functional
operation under these conditions or at any other condition beyond those indicated in the
AC/DC Electrical Characteristics sections is not implied.
2.2 Recommended Operating Conditions
Table 2-2: Recommended Operating Conditions
Parameter
Operating Temperature Range,
Ambient
Supply Voltage, Digital Core
Supply Voltage, Digital I/O
Symbol
Conditions
Min
Typ
Max
Units
Notes
TA
–
-20
−
85
°C
−
CORE_VDD
–
1.14
1.2
1.26
V
−
1.8V mode
1.71
1.8
1.89
V
−
3.3V mode
3.13
3.3
3.47
V
−
IO_VDD
Supply Voltage, PLL
PLL_VDD
–
1.14
1.2
1.26
V
–
Supply Voltage, VCO
VCO_VDD
–
−
0.7
−
V
1
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Data Sheet
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Table 2-2: Recommended Operating Conditions
Parameter
Supply Voltage, Analog
Supply Voltage, CD
Symbol
Conditions
Min
Typ
Max
Units
Notes
A_VDD
–
3.13
3.3
3.47
V
–
CD_VDD
–
3.13
3.3
3.47
V
–
NOTES:
1. This is 0.7V rather than 1.2V because there is a voltage drop across an external 105Ω resistor. See Typical Application Circuit on page 77.
2.3 DC Electrical Characteristics
Table 2-3: DC Electrical Characteristics
VCC = 3.3V ±5%, TA = -20°C to +85°C, unless otherwise shown
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Notes
I1V2
10bit 3G
−
110
170
mA
−
20bit 3G
−
110
170
mA
−
10/20bit HD
−
90
150
mA
−
10/20bit SD
−
75
120
mA
−
DVB_ASI
−
75
120
mA
−
10bit 3G
−
10
15
mA
−
20bit 3G
−
10
15
mA
−
10/20bit HD
−
10
25
mA
−
10/20bit SD
−
3
10
mA
−
DVB_ASI
−
3
10
mA
−
10bit 3G
−
80
100
mA
−
20bit 3G
−
80
100
mA
−
10/20bit HD
−
80
100
mA
−
10/20bit SD
−
70
90
mA
−
DVB_ASI
−
70
90
mA
−
10bit 3G
−
350
510
mW
−
20bit 3G
−
350
510
mW
−
10/20bit HD
−
330
490
mW
−
10/20bit SD
−
300
450
mW
−
DVB_ASI
−
300
410
mW
−
Reset
−
200
−
mW
−
Standby
−
100
180
mW
1
System
+1.2V Supply Current
+1.8V Supply Current
+3.3V Supply Current
Total Device Power
(IO_VDD = 1.8V)
I1V8
I3V3
P1D8
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Table 2-3: DC Electrical Characteristics (Continued)
VCC = 3.3V ±5%, TA = -20°C to +85°C, unless otherwise shown
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Notes
Total Device Power
(IO_VDD = 3.3V)
P3D3
10bit 3G
−
370
510
mW
−
20bit 3G
−
380
520
mW
−
10/20bit HD
−
370
500
mW
−
10/20bit SD
−
320
450
mW
−
DVB_ASI
−
320
450
mW
−
Reset
−
230
−
mW
−
Standby
−
110
180
mW
1
Digital I/O
Input Logic LOW
VIL
3.3V or 1.8V operation
IO_VSS-0.3
−
0.3 x IO_VDD
V
−
Input Logic HIGH
VIH
3.3V or 1.8V operation
0.7 x
IO_VDD
−
IO_VDD+0.3
V
−
VOL
IOL=5mA, 1.8V operation
−
−
0.2
V
−
Output Logic LOW
IOL=8mA, 3.3V operation
−
−
0.4
V
−
IOH=-5mA, 1.8V operation
1.4
−
–
V
−
IOH=-8mA, 3.3V operation
2.4
−
–
V
−
75Ω load, RSET = 750Ω
SD and HD mode
2.5
SDI_VDD (0.75/2)
SDI_VDD (0.55/2)
V
−
Output Logic HIGH
VOH
Serial Output
Serial Output
Common Mode
Voltage
VCMOUT
NOTES:
1. Devices manufactured prior to April 1, 2011 consume 150mW of power in Standby mode.
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2.4 AC Electrical Characteristics
Table 2-4: AC Electrical Characteristics
VCC = 3.3V ±5%, TA = -20°C to +85°C, unless otherwise shown
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Notes
–
3G bypass (PCLK
= 148.5MHz)
–
54
–
PCLK
–
–
3G SMPTE (PCLK
= 148.5MHz)
–
95
–
PCLK
–
–
3G IOPROC
disabled 20-bit
mode (PCLK =
148.5MHz)
–
94
–
PCLK
–
–
HD bypass (PCLK
= 74.25MHz)
–
54
–
PCLK
–
–
HD SMPTE (PCLK
= 74.25MHz)
–
95
–
PCLK
–
–
HD IOPROC
disabled 10-bit
mode (PCLK =
74.25MHz)
–
SD bypass (PCLK =
27MHz)
–
54
–
PCLK
–
–
SD SMPTE (PCLK
= 27MHz)
–
112
–
PCLK
–
–
SD IOPROC
disabled 10-bit
mode (PCLK =
27MHz)
–
94
–
PCLK
–
–
DVB-ASI
–
52
–
PCLK
–
treset
–
1
–
–
ms
–
Parallel Clock Frequency
fPCLK
–
13.5
–
148.5
MHz
–
Parallel Clock Duty Cycle
DCPCLK
–
40
–
60
%
–
Input Data Setup Time
tsu
1.2
–
–
ns
1
Input Data Hold Time
tih
50% levels; 3.3V
or 1.8V operation
0.8
–
–
ns
1
System
Device Latency
Reset Pulse Width
98
Parallel Input
Serial Digital Output
Serial Output Data Rate
DRSDO
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Data Sheet
48005 - 7
October 2010
–
–
2.97
–
Gb/s
–
–
–
2.97/1.001
–
Gb/s
–
–
–
1.485
–
Gb/s
–
–
–
1.485/1.001
–
Gb/s
–
–
–
270
–
Mb/s
–
18 of 82
Table 2-4: AC Electrical Characteristics (Continued)
VCC = 3.3V ±5%, TA = -20°C to +85°C, unless otherwise shown
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Notes
Serial Output Swing
VSDD
RSET = 750Ω
75Ω load
750
800
850
mVp-p
–
Serial Output Rise/Fall Time
20% ~ 80%
trfSDO
3G/HD mode
–
120
135
ps
–
trfSDO
SD mode
400
660
800
ps
–
Δtr,Δtf
–
–
–
35
ps
–
–
–
–
–
5
%
2
Mismatch in rise/fall time
Duty Cycle Distortion
–
3G/HD mode
–
5
10
%
2
–
SD mode
–
3
8
%
2
ORL
1.485GHz 2.97GHz
–
-12
–
dB
3
5 MHz - 1.485
GHz
–
-18
–
dB
3
tOJ
Pseudorandom
and SMPTE
Colour Bars 3G
signal
–
40
68
ps
4, 6
tOJ
Pseudorandom
and SMPTE
Colour Bars HD
signal
–
50
95
ps
4, 6
tOJ
Pseudorandom
and SMPTE
Colour Bars SD
signal
–
200
400
ps
5
GSPI Input Clock Frequency
fSCLK
–
–
80
MHz
–
GSPI Input Clock Duty Cycle
DCSCLK
50% levels
3.3V or 1.8V
operation
40
50
60
%
–
GSPI Input Data Setup Time
–
1.5
–
–
ns
–
Overshoot
Output Return Loss
Serial Output Intrinsic Jitter
GSPI
GSPI Input Data Hold Time
–
1.5
–
–
ns
–
GSPI Output Data Hold Time
–
15pF load
1.5
–
–
ns
–
CS low before SCLK rising
edge
t0
50% levels
3.3V or 1.8V
operation
1.5
–
–
ns
–
Time between end of
command word (or data in
Auto-Increment mode) and
the first SCLK of the
following data word - write
cycle
t4
50% levels
3.3V or 1.8V
operation
–
–
ns
–
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Data Sheet
48005 - 7
October 2010
PCLK
(MHz)
ns
unlocked
445
13.5
74.2
27.0
37.1
74.25
13.5
148.5
6.7
19 of 82
Table 2-4: AC Electrical Characteristics (Continued)
VCC = 3.3V ±5%, TA = -20°C to +85°C, unless otherwise shown
Parameter
Time between end of
command word (or data in
Auto-Increment mode) and
the first SCLK of the
following data word - read
cycle
CS high after SCLK falling
edge
Symbol
Conditions
t5
50% levels
3.3V or 1.8V
operation
t7
50% levels
3.3V or 1.8V
operation
Min
PCLK
(MHz)
ns
unlocked
1187
13.5
297
27.0
148.4
74.25
53.9
148.5
27
PCLK
(MHz)
ns
unlocked
445
13.5
74.2
27.0
37.1
74.25
13.5
148.5
6.7
Typ
Max
Units
Notes
–
–
ns
–
–
–
ns
–
NOTES:
1. Input setup and hold time is dependent on the rise and fall time on the parallel input. Parallel clock and data with rise time or fall time greater
than 500ps require larger setup and hold times.
2. Single Ended into 75Ω external load.
3. ORL depends on board design.
4. Alignment Jitter = measured from 100kHz to serial data rate/10.
5. Alignment Jitter = measured from 1kHz to 27MHz.
6. This is the maximum jitter for a BER of 10-12. The equivalent jitter value as per RP184 is 40ps max.
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SMPTE Video Support
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3. Input/Output Circuits
SDO
SDO
CD_VDD
I REF
Figure 3-1: Differential Output Stage (SDO/SDO)
IO_VDD
200Ω
Input Pin
Figure 3-2: Digital Input Pin (20bit/10bit, ANC_BLANK, DETECT_TRS, DVB_ASI,
RATE_SEL0, SMPTE_BYPASS, RATE_SEL1, TIM_861, F/DE, H/HSYNC, PCLK,
V/VSYNC)
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SMPTE Video Support
Data Sheet
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IO_VDD
200Ω
Input Pin
Figure 3-3: Digital Input Pin with Schmitt Trigger (RESET)
IO_VDD
200Ω
Input Pin
Figure 3-4: Digital Input Pin with weak pull-down - maximum pull-down
current
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