GS2972-IBE3

GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Key Features • • Applications Operation at 2.970Gb/s, 2.970/1.001Gb/s, 1.485Gb/s, 1.485/1.001Gb/s and 270Mb/s Application: 1080p 50/60 Camera/Camcorder AES - IN MIC Supports SMPTE ST 425 (Level A and Level B), SMPTE ST 424, SMPTE ST 292, SMPTE ST 259-C and DVB-ASI • Integrated Cable Driver • Integrated, low-noise VCO • Integrated Narrow-Bandwidth PLL • Integrated Audio Embedder for up to 8 channels of 48kHz audio • Ancillary data insertion • Optional conversion from SMPTE ST 425 Level A to Level B for 1080p 50/60 4:2:2 10-bit AUDIO 1/ 2 ADC Audio Processor CCD Video Processor Audio Clocks AUDIO 3/4 20-bit 3G-SDI GS2972 HV F/PCLK OPTICS CTRL/TIME CODE Storage: Tape/Disc /Solid State • Parallel data bus selectable as either 20-bit or 10-bit • SMPTE video processing including TRS calculation and insertion, line number calculation and insertion, line based CRC calculation and insertion, illegal code re-mapping, SMPTE ST 352 payload identifier generation and insertion Application: Dual Link (HD-SDI) to Single Link (3G-SDI) Converter HD-SDI Link A EQ GS2974B HD-SDI Deserializer (GS1559 or GS2970) 10-bit 10-bit FIFO HV F/PCLK W 3G-SDI R HV F/PCLK HD-SDI Link B EQ GS2974B HD-SDI Deserializer (GS1559 or GS2970) GS2972 10-bit 10-bit FIFO HV F/PCLK W R GS4910 HV F X TAL • GSPI host interface • +1.2V digital core power supply, +1.2V and +3.3V analog power supplies, and selectable +1.8V or +3.3V I/O power supply • -20ºC to +85ºC operating temperature range • Low power operation (typically at 400mW, including Cable Driver) • Small 11mm x 11mm 100-ball BGA package • Pb-free and RoHS compliant GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 Application: Multi-format Audio Embedder Module 10-bit EQ SD/HD/3G-SDI GS2974B GS2970 P CLK Audio Clocks GS4911 X TAL HV F GS2972 SD/HD/3G-SDI AUDIO 1/ 2 AES Audio Inputs Analog Audio Inputs www.semtech.com AUDIO 3/ 4 SRC AUDIO 5/ 6 ADC Switch Logic & Buffers AUDIO 7/ 8 1 of 125 Application: Multi-format Digital VTR/Video Server V ideo Inputs 20-bit Video Processor Storage: Tape/HDD/Solid State HV F /P CLK 3G-SDI GS2972 AUDIO 1/ 2 AUDIO 3/ 4 Audio Processor AUDIO 5/ 6 AUDIO 7/ 8 Audio Clocks Audio Inputs Analog Sync Sync Seperator GS4911 X TAL Application: Multi-format Presentation Switcher (Output Stage) P rogram AE S Out P rogram AE S In Audio Mixer P reset AE S In V oice-Over P review AE S Out SD/HD/3G-SDI Auxiliary I2S Audio + Clocks AE S from Input Dem ux 10-bit + Clk GS2972 SD/HD/3G-SDI Preview 20-bit + Clk DVE Mixers Logo Inserter Key & Fill Keyer Keyer GS2972 SD/HD/3G-SDI Program 20-bit + Clk GS2972 Key/Fill Inputs Image Store GS4911 Clock & Sync Distribution Application: 3Gb/s SDI Test Signal Generator Memory X TAL 20-bit Sync Seperator GS4911 HV F/PCLK Video Signal Generator HV F/PCLK AE S 1/ 2 Audio Clocks Audio Generator AE S 3/ 4 AE S 5/ 6 AE S 7/ 8 GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 3G-SDI GS2972 The integrated Narrow BW PLL allows the device to accept parallel clocks with high input jitter, and still provide a SMPTE compliant serial digital output. The device can operate in four basic user selectable modes: SMPTE mode, DVB-ASI mode, Data-Through mode, or Standby mode. In SMPTE mode, the GS2972 performs all SMPTE processing features. Both SMPTE ST 425 Level A and Level B formats are supported with optional conversion from Level A to Level B for 1080p 50/60 4:2:2 10-bit. In DVB-ASI mode, the device will perform 8b/10b encoding prior to transmission. In Data-Through mode, all SMPTE and DVB-ASI processing is disabled. The device can be used as a simple parallel to serial converter. The GS2972 integrates a fully SMPTE-compliant Cable Driver for SMPTE ST 259-C, SMPTE ST 292 and SMPTE ST 424 interfaces. It features automatic dual slew-rate selection, depending on 3Gb/s or HD or SD operational requirements. X TAL Analog Sync The GS2972 is a complete SDI Transmitter, generating a SMPTE ST 424, SMPTE ST 292, SMPTE ST 259-C or DVB-ASI compliant serial digital output signal. The device can also operate in a lower power Standby mode. In this mode, no signal is generated at the output. Analog Sync Sync Seperator Description In accordance with SMPTE ST 272 and SMPTE ST 299, up to eight channels (two audio groups) of serial digital audio may be embedded into the video data stream.The input audio signal formats supported by the device include AES/EBU, I2S and serial audio. 16, 20 and 24-bit audio formats are supported at 48kHz synchronous for SD modes and 48kHz synchronous or asynchronous in HD, 3Gb/s modes. www.semtech.com 2 of 125 AUDIO_INT GRP1_EN/DIS GRP2_EN/DIS SMPTE_BYPASS IOPROC_EN/DIS STANDBY RESET IO_GND IO_VDD CORE_GND CORE_VDD DVB_ASI Shared JTAG and GSPI pins (for drop-in compatibility with GS1572/82) SDIN_TDI SCLK_TCK CS_TMS SDOUT_TDO JTAG/HOST Dedicated JTAG pins TDO TDI TMS TCK Functional Block Diagram AVDD JTAG Controller GSPI Host Interface AGND PLL_VDD Ain_1/2 Ain_3/4 Ain_5/6 Ain_7/8 PLL_GND VCO_VDD VCO_GND ACLK1 ACLK2 WCLK1 WCLK2 CD_VDD CD_GND ANC_BLANK F/DE V/VSYNC H/HSYNC TIM_861 20BIT/10BIT DIN[19:0] PCLK Input Mux/ Demux SMPTE ST 425 Level A to Level B 1080p 50/60 4:2:2 10-bit HANC/ VANC Blanking SMPTE ST 352 Generation and Insertion RSET 3G/HD/SD Audio Embedding ANC Data Insertion TRS , Line Number and CRC Insertion EDH Packet Insertion NRZ/NRZI SMPTE Scrambler Mux Parallel to Serial Converter SMPTE Cable Driver SDO SDO SDO_EN/DIS DVB-ASI 8b/10b Encoder PLL with Low Noise VCO LOCKED Narrow BW PLL RATE_SEL[1:0] VBG LF Figure A: GS2972 Functional Block Diagram GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 3 of 125 Revision History Version ECO PCN Date 9 014806 – September 2013 Updates throughout the document. 8 011355 – February 2013 Updated to the Semtech Template. 7 155820 56554 February 2011 Added section 4.7.22.2 Blanking Values Following Audio Data Packet Insertion. 6 155608 – January 2011 Clarified the function of the ACS_REGEN bit in Section 4.7.11 Audio Channel Status. 5 155080 56059 October 2010 Revised power rating in standby mode. Documented CSUM behaviour in Section 4.8, Section 4.9.4 and Video Core Configuration and Status Registers. 4 153717 – March 2010 Updates throughout entire document. Added Figure 4-2, Figure 4-3 and Figure 4-4. Correction to registers 040h to 13Fh in Table 4-34: Video Core Configuration and Status Registers. 3 152220 – July 2009 2 151320 − January 2009 1 150803 − December 2008 0 150717 – October 2008 Converted to Preliminary Data Sheet. D 149428 – August 2008 Updated Typical Application Circuit. Applied new format to the document. Updates to all sections. C 148810 – February 2008 B 148770 – December 2007 Updates and revised 5.1 Typical Application Circuit. A 147987 – December 2007 New Document. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 Changes and/or Modifications Updated Device Latency numbers in 2.4 AC Electrical Characteristics. Updates to 4.8 ANC Data Insertion. Replaced 7.3 Marking Diagram. Correction to timing values in Table 4-1: GS2972 Digital Input AC Electrical Characteristics. Converted to Data Sheet. Updates to all sections. Updates to all sections. www.semtech.com 4 of 125 Contents Key Features ........................................................................................................................................................1 Applications.........................................................................................................................................................1 Description...........................................................................................................................................................2 Functional Block Diagram ..............................................................................................................................3 Revision History .................................................................................................................................................4 1. Pin Out............................................................................................................................................................ 10 1.1 Pin Assignment ............................................................................................................................... 10 1.2 Pin Descriptions ............................................................................................................................. 11 2. Electrical Characteristics ......................................................................................................................... 20 2.1 Absolute Maximum Ratings ....................................................................................................... 20 2.2 Recommended Operating Conditions .................................................................................... 20 2.3 DC Electrical Characteristics ..................................................................................................... 21 2.4 AC Electrical Characteristics ..................................................................................................... 23 3. Input/Output Circuits ............................................................................................................................... 26 4. Detailed Description.................................................................................................................................. 30 4.1 Functional Overview .................................................................................................................... 30 4.2 Parallel Data Inputs ....................................................................................................................... 31 4.2.1 Parallel Input in SMPTE Mode....................................................................................... 33 4.2.2 Parallel Input in DVB-ASI Mode................................................................................... 33 4.2.3 Parallel Input in Data-Through Mode......................................................................... 34 4.2.4 Parallel Input Clock (PCLK) ............................................................................................ 34 4.3 SMPTE Mode ................................................................................................................................... 35 4.3.1 H:V:F Timing ....................................................................................................................... 35 4.3.2 CEA 861 Timing.................................................................................................................. 38 4.4 DVB-ASI Mode ............................................................................................................................... 44 4.5 Data-Through Mode ..................................................................................................................... 44 4.6 Standby Mode ................................................................................................................................. 44 4.7 Audio Embedding .......................................................................................................................... 45 4.7.1 Serial Audio Data Inputs ................................................................................................. 45 4.7.2 Serial Audio Data Format Support............................................................................... 47 4.7.3 3G Mode................................................................................................................................ 49 4.7.4 HD Mode............................................................................................................................... 49 4.7.5 SD Mode................................................................................................................................ 50 4.7.6 Audio Embedding Operating Modes .......................................................................... 50 4.7.7 Audio Packet Detection................................................................................................... 51 4.7.8 Audio Packet Deletion ..................................................................................................... 51 4.7.9 Audio Packet Detection and Deletion ........................................................................ 51 4.7.10 Audio Mute (Default Off).............................................................................................. 52 4.7.11 Audio Channel Status .................................................................................................... 53 4.7.12 Audio Crosspoint............................................................................................................. 54 4.7.13 Audio Word Clock .......................................................................................................... 55 4.7.14 Channel & Group Activation ....................................................................................... 55 4.7.15 Audio FIFO - SD............................................................................................................... 56 4.7.16 Audio FIFO - HD and 3G............................................................................................... 57 GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 5 of 125 4.7.17 Five-frame Sequence Detection - SD........................................................................ 57 4.7.18 Frame Sequence Detection - HD/3G ........................................................................ 60 4.7.19 ECC Error Detection and Correction ........................................................................ 61 4.7.20 Audio Control Packet Insertion - SD......................................................................... 61 4.7.21 Audio Control Packet Insertion - HD and 3G......................................................... 62 4.7.22 Audio Data Packet Insertion........................................................................................ 63 4.7.23 Audio Interrupt Control ................................................................................................ 64 4.8 ANC Data Insertion ....................................................................................................................... 65 4.8.1 ANC Insertion Operating Modes .................................................................................. 65 4.8.2 3G ANC Insertion............................................................................................................... 67 4.8.3 HD ANC Insertion.............................................................................................................. 69 4.8.4 SD ANC Insertion............................................................................................................... 70 4.9 Additional Processing Functions .............................................................................................. 71 4.9.1 Video Format Detection .................................................................................................. 71 4.9.2 3G Format Detection ........................................................................................................ 74 4.9.3 ANC Data Blanking ........................................................................................................... 75 4.9.4 ANC Data Checksum Calculation and Insertion..................................................... 75 4.9.5 TRS Generation and Insertion ....................................................................................... 75 4.9.6 HD and 3G Line Number Calculation and Insertion.............................................. 76 4.9.7 Illegal Code Re-Mapping................................................................................................. 76 4.9.8 SMPTE ST 352 Payload Identifier Packet Insertion ................................................ 77 4.9.9 Line Based CRC Generation and Insertion (HD/3G) .............................................. 78 4.9.10 EDH Generation and Insertion ................................................................................... 78 4.9.11 GS2972 3G/HD HANC Space Considerations when Embedding Audio ...... 79 4.9.12 SMPTE ST 372 Conversion ........................................................................................... 79 4.9.13 Processing Feature Disable.......................................................................................... 80 4.10 SMPTE ST 352 Data Extraction ............................................................................................... 81 4.11 Serial Clock PLL ........................................................................................................................... 82 4.11.1 PLL Bandwidth................................................................................................................. 82 4.11.2 Lock Detect........................................................................................................................ 83 4.12 Serial Digital Output .................................................................................................................. 84 4.12.1 Output Signal Interface Levels ................................................................................... 85 4.12.2 Overshoot/Undershoot ................................................................................................. 85 4.12.3 Slew Rate Selection......................................................................................................... 86 4.12.4 Serial Digital Output Mute ........................................................................................... 86 4.13 GSPI Host Interface ..................................................................................................................... 87 4.13.1 Command Word Description ...................................................................................... 88 4.13.2 Data Read or Write Access........................................................................................... 88 4.13.3 GSPI Timing....................................................................................................................... 89 4.14 Host Interface Register Maps .................................................................................................. 91 4.14.1 Video Core Registers...................................................................................................... 91 4.14.2 SD Audio Core................................................................................................................ 100 4.14.3 HD and 3G Audio Core Registers............................................................................. 111 4.15 JTAG ID Codeword ................................................................................................................... 119 4.16 JTAG Test Operation ................................................................................................................ 119 4.17 Device Power-Up ...................................................................................................................... 119 4.18 Device Reset ................................................................................................................................ 119 GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 6 of 125 5. Application Reference Design ............................................................................................................. 120 5.1 Typical Application Circuit ......................................................................................................120 6. References & Relevant Standards ....................................................................................................... 121 7. Package & Ordering Information ........................................................................................................ 122 7.1 Package Dimensions ................................................................................................................... 122 7.2 Packaging Data ............................................................................................................................. 123 7.3 Marking Diagram ......................................................................................................................... 123 7.4 Solder Reflow Profiles ................................................................................................................ 124 7.5 Ordering Information ................................................................................................................. 124 List of Figures Figure 1-1: Pin Assignment ......................................................................................................................... 10 Figure 3-1: Differential Output Stage (SDO/SDO) .............................................................................. 26 Figure 3-2: Digital Input Pin ........................................................................................................................ 26 Figure 3-3: Digital Input Pin with Schmitt Trigger (RESET) .............................................................. 26 Figure 3-4: Digital Input Pin with weak pull-down - maximum pull-down current ............... 27 Figure 3-5: Digital Input Pin with weak pull-up - maximum pull-up current ........................... 27 Figure 3-6: Bidirectional Digital Input/Output Pin with programmable drive strength......... 27 Figure 3-7: Bidirectional Digital Input/Output Pin with programmable drive strength......... 28 Figure 3-8: VBG .............................................................................................................................................. 28 Figure 3-9: Loop Filter .................................................................................................................................. 29 Figure 4-1: GS2972 Video Host Interface Timing Diagrams ............................................................ 31 Figure 4-2: H:V:F Output Timing - 3G Level A and HDTV 20-bit Mode ...................................... 36 Figure 4-3: H:V:F Output Timing - 3G Level A and HDTV 10-bit Mode 3G Level B 20-bit Mode, each 10-bit stream ......................................................................................... 36 Figure 4-4: H:V:F Output Timing - 3G Level B 10-bit Mode ............................................................. 36 Figure 4-5: H:V:F Input Timing - HD 20-bit Input Mode ................................................................... 36 Figure 4-6: H:V:F Input Timing - HD 10-bit Input Mode ................................................................... 37 Figure 4-7: H:V:F Input Timing - SD 20-bit Mode ............................................................................... 37 Figure 4-8: H:V:F Input Timing - SD 10-bit Mode ............................................................................... 37 Figure 4-9: H:V:DE Input Timing 1280 x 720p @ 59.94/60 (Format 4) ........................................ 39 Figure 4-10: H:V:DE Input Timing 1920 x 1080i @ 59.94/60 (Format 5) ..................................... 39 Figure 4-11: H:V:DE Input Timing 720 (1440) x 480i @ 59.94/60 (Format 6&7) ....................... 40 Figure 4-12: H:V:DE Input Timing 1280 x 720p @ 50 (Format 19) ................................................ 40 Figure 4-13: H:V:DE Input Timing 1920 x 1080i @ 50 (Format 20) ............................................... 41 Figure 4-14: H:V:DE Input Timing 720 (1440) x 576 @ 50 (Format 21&22) ................................ 41 Figure 4-15: H:V:DE Input Timing 1920 x 1080p @ 59.94/60 (Format 16) ................................. 42 Figure 4-16: H:V:DE Input Timing 1920 x 1080p @ 50 (Format 31) .............................................. 42 Figure 4-17: H:V:DE Input Timing 1920 x 1080p @ 23.94/24 (Format 32) ................................. 42 Figure 4-18: H:V:DE Input Timing 1920 x 1080p @ 25 (Format 33) .............................................. 43 Figure 4-19: H:V:DE Input Timing 1920 x 1080p @ 29.97/30 (Format 34) ................................. 43 Figure 4-20: ACLK to Data and Control Signal Input Timing .......................................................... 46 Figure 4-21: I2S Audio Input Format ....................................................................................................... 47 Figure 4-22: AES/EBU Audio Input Format .......................................................................................... 48 Figure 4-23: Serial Audio, Left Justified, MSB First ............................................................................. 48 Figure 4-24: Serial Audio, Left Justified, LSB First .............................................................................. 48 Figure 4-25: Serial Audio, Right Justified, MSB First .......................................................................... 48 Figure 4-26: Serial Audio, Right Justified, LSB First ........................................................................... 48 Figure 4-27: Ancillary Data Packet Placement Example for SD Mode ........................................ 52 Figure 4-28: ORL Matching Network, BNC and Coaxial Cable Connection ............................... 84 GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 7 of 125 Figure 4-29: GSPI Application Interface Connection ........................................................................ 87 Figure 4-30: Command Word Format ..................................................................................................... 88 Figure 4-31: Data Word Format ................................................................................................................ 88 Figure 4-32: Write Mode .............................................................................................................................. 89 Figure 4-33: Read Mode ............................................................................................................................... 89 Figure 4-34: GSPI Time Delay .................................................................................................................... 89 Figure 4-35: Reset Pulse ............................................................................................................................. 119 Figure 5-1: Typical Application Circuit ................................................................................................ 120 Figure 7-1: Package Dimensions ............................................................................................................. 122 Figure 7-2: Marking Diagram ................................................................................................................... 123 Figure 7-3: Pb-free Solder Reflow Profile ............................................................................................ 124 List of Tables Table 1-1: Pin Descriptions ......................................................................................................................... 11 Table 2-1: Absolute Maximum Ratings................................................................................................... 20 Table 2-2: Recommended Operating Conditions................................................................................ 20 Table 2-3: DC Electrical Characteristics ................................................................................................. 21 Table 2-4: AC Electrical Characteristics ................................................................................................. 23 Table 4-1: GS2972 Digital Input AC Electrical Characteristics....................................................... 31 Table 4-2: GS2972 Input Video Data Format Selections................................................................... 31 Table 4-3: GS2972 PCLK Input Rates....................................................................................................... 34 Table 4-4: CEA861 Timing Formats ......................................................................................................... 38 Table 4-5: Serial Audio Input Pin Description...................................................................................... 45 Table 4-6: GS2972 Serial Audio Data Inputs - AC Electrical Characteristics............................. 46 Table 4-7: Audio Input Formats ................................................................................................................ 47 Table 4-8: GS2972 Audio Operating Mode Selection ........................................................................ 50 Table 4-9: GS2972 SD Audio Crosspoint Channel Selection ........................................................... 54 Table 4-10: Audio Source Host Interface Fields .................................................................................. 54 Table 4-11: GS2972 SD Audio Buffer Size Selection .......................................................................... 56 Table 4-12: GS2972 SD Audio Five Frame Sequence Sample Count............................................ 58 Table 4-13: GS2972 SD Audio Group 1 Audio Sample Distribution - 525 line.......................... 58 Table 4-14: GS2972 SD Audio Group 2 Audio Sample Distribution - 525 line.......................... 59 Table 4-15: GS2972 SD Audio Group 3 Audio Sample Distribution - 525 line.......................... 59 Table 4-16: GS2972 SD Audio Group 4 Audio Sample Distribution - 525 line.......................... 59 Table 4-17: GS2972 SD Audio Group 1 Audio Sample Distribution - 625 line.......................... 59 Table 4-18: GS2972 SD Audio Group 2 Audio Sample Distribution - 625 line.......................... 60 Table 4-19: GS2972 SD Audio Group 3 Audio Sample Distribution - 625 line.......................... 60 Table 4-20: GS2972 SD Audio Group 4 Audio Sample Distribution - 625 line.......................... 60 Table 4-21: Audio Interrupt Control – Host Interface Bit Description ......................................... 64 Table 4-22: Supported Video Standards................................................................................................. 72 Table 4-23: IOPROC Register Bits ............................................................................................................. 80 Table 4-24: SMPTE ST 352 Packet Data................................................................................................... 81 Table 4-25: PCLK and Serial Digital Clock Rates ................................................................................. 82 Table 4-26: GS2972 PLL Bandwidth......................................................................................................... 83 Table 4-27: GS2972 Lock Detect Indication .......................................................................................... 83 Table 4-28: Serial Digital Output - Serial Output Data Rate ............................................................ 84 Table 4-29: RSET Resistor Value vs. Output Swing .............................................................................. 85 Table 4-30: Serial Digital Output - Overshoot/Undershoot ............................................................. 85 Table 4-31: Serial Digital Output - Rise/Fall Time............................................................................... 86 Table 4-32: GSPI Time Delay...................................................................................................................... 89 Table 4-33: GSPI AC Characteristics........................................................................................................ 90 Table 4-34: Video Core Configuration and Status Registers............................................................ 91 Table 4-35: SD Audio Core Configuration and Status Registers................................................... 100 GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 8 of 125 Table 4-36: HD and 3G Audio Core Configuration and Status Registers .................................. 111 Table 7-1: Packaging Data......................................................................................................................... 123 Table 7-2: Ordering Information............................................................................................................. 124 GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 9 of 125 1. Pin Out 1.1 Pin Assignment 1 2 A DIN17 DIN18 F/DE B DIN15 DIN16 DIN19 C DIN13 DIN14 DIN12 D DIN11 E CORE _VDD F DIN9 G 3 4 5 6 7 8 9 10 H/HSYNC CORE _VDD PLL_ VDD LF VBG RSV A_VDD PCLK CORE _GND PLL_ VDD VCO_ VDD VCO_ GND A_GND A_GND V/VSYNC CORE _GND PLL_ GND PLL_ GND PLL_ GND CD_GND SDO DIN10 STANDBY SDO_ EN/DIS RSV RSV RSV RSV CD_GND SDO CORE _GND RATE_ SEL0 RATE_ SEL1 CORE _GND CORE _GND TDI TMS CD_GND CD_VDD DIN8 DETECT _TRS RSV CORE _GND CORE _GND RSV TDO CD_GND RSET CORE _GND CORE _VDD SMPTE_ IOPROC_ 20bit/ DVB_ASI RESET BYPASS EN/DIS 10bit IO_VDD IO_GND TIM_861 ANC_ GRP2_EN GRP1_EN AUDIO_ LOCKED /DIS /DIS BLANK INT H DIN7 DIN6 J DIN5 DIN4 DIN1 K DIN3 DIN2 DIN0 JTAG/ HOST IO_GND IO_VDD AIN_5/6 WCLK2 AIN_1/2 WCLK1 TCK SDOUT_ SCLK_ TDO TCK AIN_7/8 ACLK2 AIN_3/4 ACLK1 CORE _VDD CS_ TMS SDIN_ TDI Figure 1-1: Pin Assignment GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 10 of 125 1.2 Pin Descriptions Table 1-1: Pin Descriptions Pin Number Name Timing Type Description PARALLEL DATA BUS. Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. 20-bit mode 20BIT/10BIT = HIGH B3, A2, A1, B2, B1, C2, C1, C3, D1, D2 DIN[19:10] Input 10-bit mode 20BIT/10BIT = LOW Data Stream 1/Luma data input in SMPTE mode (SMPTE_BYPASS = HIGH) Data input in data through mode (SMPTE_BYPASS = LOW) Multiplexed Data Stream 1/Luma and Data Stream 2/Chroma data input in SMPTE mode (SMPTE_BYPASS = HIGH) Data input in data through mode (SMPTE_BYPASS = LOW) DVB-ASI data input in DVB-ASI mode (SMPTE_BYPASS = LOW) (DVB_ASI = HIGH) PARALLEL DATA TIMING. Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. A3 F/DE Synchronous with PCLK Input TIM_861 = LOW: Used to indicate the ODD / EVEN field of the video signal when DETECT_TRS is set LOW. The device will set the F bit in all outgoing TRS signals for the entire period that the F input signal is HIGH (IOPROC_EN/DIS must also be HIGH). The F signal should be set HIGH for the entire period of field 2 and should be set LOW for all lines in field 1 and for all lines in progressive scan systems. The F signal is ignored when DETECT_TRS = HIGH. TIM_861 = HIGH: The DE signal is used to indicate the active video period when DETECT_TRS is LOW. DE is HIGH for active data and LOW for blanking. See Section 4.3 and Section 4.3.2 for timing details. The DE signal is ignored when DETECT_TRS = HIGH. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 11 of 125 Table 1-1: Pin Descriptions (Continued) Pin Number Name Timing Type Description PARALLEL DATA TIMING. Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. TIM_861 is LOW: The H signal is used to indicate the portion of the video line containing active video data, when DETECT_TRS is set LOW. A4 H/HSYNC Synchronous with PCLK Input Active Line Blanking The H signal should be LOW for the active portion of the video line. The signal goes LOW at the first active pixel of the line, and then goes HIGH after the last active pixel of the line. The H signal should be set HIGH for the entire horizontal blanking period, including both EAV and SAV TRS words, and LOW otherwise. TRS Based Blanking (H_CONFIG = 1h) The H signal should be set HIGH for the entire horizontal blanking period as indicated by the H bit in the received TRS ID words, and LOW otherwise. TIM_861 = HIGH: The HSYNC signal indicates horizontal timing. See Section 4.3. When DETECT_TRS is HIGH, this pin is ignored at all times. If DETECT_TRS is set HIGH and TIM_861 is set HIGH, the DETECT_TRS feature will take priority. A5, E1, G10, K8 CORE_VDD Input Power Power supply connection for digital core logic. Connect to +1.2V DC digital. A6, B6 PLL_VDD Input Power Power supply pin for PLL. Connect to +1.2V DC analog. A7 LF Analog Output Loop Filter component connection. A8 VBG Output Bandgap voltage filter connection. A9, D6, D7, D8, F4 RSV − A10 A_VDD Input Power These pins are reserved and should be left unconnected. VDD for sensitive analog circuitry. Connect to +3.3VDC analog. PARALLEL DATA BUS CLOCK. Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. B4 B5, C5, E2, E5, E6, F5, F6, G9 PCLK CORE_GND GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 Input Input Power 3G 20-bit mode PCLK @ 148.5MHz 3G 10-bit mode DDR PCLK @ 148.5MHz HD 20-bit mode PCLK @ 74.25MHz HD 10-bit mode PCLK @ 148.5MHz SD 20-bit mode PCLK @ 13.5MHz SD 10-bit mode PCLK @ 27MHz DVB-ASI mode PCLK @ 27MHz GND connection for digital logic. Connect to digital GND. www.semtech.com 12 of 125 Table 1-1: Pin Descriptions (Continued) Pin Number Name B7 VCO_VDD Input Power Power pin for VCO. Connect to +1.2V DC analog followed by an RC filter (see Typical Application Circuit on page 120). VCO_VDD is nominally 0.7V. B8 VCO_GND Input Power Ground connection for VCO. Connect to analog GND. B9, B10 A_GND Input Power GND pins for sensitive analog circuitry. Connect to analog GND. Timing Type Description PARALLEL DATA TIMING. Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. TIM_861 = LOW: C4 V/VSYNC Synchronous with PCLK The V signal is used to indicate the portion of the video field/frame that is used for vertical blanking, when DETECT_TRS is set LOW. Input The V signal should be set HIGH for the entire vertical blanking period and should be set LOW for all lines outside of the vertical blanking interval. The V signal is ignored when DETECT_TRS = HIGH. TIM_861 = HIGH: The VSYNC signal indicates vertical timing. See Section 4.3 for timing details. The VSYNC signal is ignored when DETECT_TRS = HIGH. C6, C7, C8 PLL_GND Input Power Ground connection for PLL. Connect to analog GND. C9, D9, E9, F9 CD_GND Input Power Ground connection for the serial digital cable driver. Connect to analog GND. Serial Data Output Signal. C10, D10 SDO, SDO Output D3 STANDBY Input Serial digital output signal operating at 2.97Gb/s, 2.97/1.001Gbs, 1.485Gb/s, 1.485 /1.001Gb/s or 270Mb/s. The slew rate of the output is automatically controlled to meet SMPTE ST 424, SMPTE ST 292 and ST 259-C specifications according to the setting of the RATE_SEL0 and RATE_SEL1 pins. Power Down input. HIGH to power down device. CONTROL SIGNAL INPUT. Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. D4 SDO_EN/DIS Input Used to enable or disable the serial digital output stage. When SDO_EN/DIS is LOW, the serial digital output signals SDO and SDO are disabled and become high impedance. When SDO_EN/DIS is HIGH, the serial digital output signals SDO and SDO are enabled. D5, F7 RSV GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 − These pins are reserved and should be connected to CORE_GND. www.semtech.com 13 of 125 Table 1-1: Pin Descriptions (Continued) Pin Number Name Timing Type Description CONTROL SIGNAL INPUT. Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Used to configure the operating data rate. E3, E4 RATE_SEL0, RATE_SEL1 Input RATE_SEL0 Data Rate RATE_SEL1 0 0 1.485 or 1.485/1.001Gb/s 0 1 2.97 or 2.97/1.001Gb/s 1 X 270Mb/s COMMUNICATION SIGNAL INPUT. Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. E7 TDI Input Dedicated JTAG pin. Test data in. This pin is used to shift JTAG test data into the device when the JTAG/HOST pin is LOW. COMMUNICATION SIGNAL INPUT. Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. E8 TMS Input Dedicated JTAG pin. Test mode start. This pin is JTAG Test Mode Start, used to control the operation of the JTAG test when the JTAG/HOST pin is LOW. E10 CD_VDD Input Power Power for the serial digital cable driver. Connect to +3.3V DC analog. PARALLEL DATA BUS. Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. In 10-bit mode, these pins are not used. F1, F2, H1, H2, J1, J2, K1, K2, J3, K3 Data Stream 2/Chroma data input in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW DIN[9:0] Input 20-bit mode 20BIT/10BIT = HIGH Data input in data through mode SMPTE_BYPASS = LOW DVB_ASI = LOW Not Used in DVB-ASI mode SMPTE_BYPASS = LOW DVB_ASI = HIGH 10-bit mode 20BIT/10BIT = LOW GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com High impedance. 14 of 125 Table 1-1: Pin Descriptions (Continued) Pin Number Name Timing Type Description CONTROL SIGNAL INPUT. Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. F3 DETECT_TRS Input Used to select external HVF timing mode or TRS extraction timing mode. When DETECT_TRS is LOW, the device extracts all internal timing from the supplied H:V:F or CEA-861 timing signals, dependent on the status of the TIM861 pin. When DETECT_TRS is HIGH, the device extracts all internal timing from TRS signals embedded in the supplied video stream. COMMUNICATION SIGNAL OUTPUT. Please refer to the Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. F8 TDO Output Dedicated JTAG pin. JTAG Test Data Output. This pin is used to shift results from the device when the JTAG/HOST pin is LOW. An external 1% resistor connected to this input is used to set the SDO/SDO output signal amplitude. F10 RSET Input G1, H10 IO_VDD Input Power Power connection for digital I/O. Connect to +3.3V or +1.8V DC digital. G2, H9 IO_GND Input Power Ground connection for digital I/O. Connect to digital GND. CONTROL SIGNAL INPUT. Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Used to select external CEA-861 timing mode. G3 TIM_861 Input When DETECT_TRS is LOW and TIM-861 is LOW, the device extracts all internal timing from the supplied H:V:F timing signals. When DETECT_TRS is LOW and TIM-861 is HIGH, the device extracts all internal timing from the supplied HSYNC, VSYNC, DE timing signals. When DETECT_TRS is HIGH, the device extracts all internal timing from TRS signals embedded in the supplied video stream. CONTROL SIGNAL INPUT. G4 20BIT/10BIT Input Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Used to select the input bus width. CONTROL SIGNAL INPUT. Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Used to enable/disable the DVB-ASI data transmission. G5 DVB_ASI Input When DVB_ASI is set HIGH and SMPTE_BYPASS is set LOW, then the device will carry out DVB-ASI word alignment, I/O processing and transmission. When SMPTE_BYPASS and DVB_ASI are both set LOW, the device operates in data-through mode. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 15 of 125 Table 1-1: Pin Descriptions (Continued) Pin Number Name Timing Type Description CONTROL SIGNAL INPUT. Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Used to enable / disable all forms of encoding / decoding, scrambling and EDH insertion. G6 SMPTE_BYPASS Input When set LOW, the device operates in data through mode (DVB_ASI= LOW), or in DVB-ASI mode (DVB_ASI = HIGH). No SMPTE scrambling takes place and none of the I/O processing features of the device are available when SMPTE_BYPASS is set LOW. When set HIGH, the device carries out SMPTE scrambling and I/O processing. CONTROL SIGNAL INPUT. Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. G7 IOPROC_EN/DIS Input Used to enable or disable the I/O processing features. When IOPROC_EN/DIS is HIGH, the I/O processing features of the device are enabled. When IOPROC_EN/DIS is LOW, the I/O processing features of the device are disabled. Only applicable in SMPTE mode. CONTROL SIGNAL INPUT. Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Used to reset the internal operating conditions to default settings and to reset the JTAG sequence. Normal mode (JTAG/HOST = LOW). G8 RESET Input When LOW, all functional blocks will be set to default conditions and all input and output signals become high impedance. When HIGH, normal operation of the device resumes. JTAG test mode (JTAG/HOST = HIGH). When LOW, all functional blocks will be set to default and the JTAG test sequence will be reset. When HIGH, normal operation of the JTAG test sequence resumes. CONTROL SIGNAL INPUT. Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. H3 ANC_BLANK Input When ANC_BLANK is LOW, the Luma and Chroma input data is set to the appropriate blanking levels during the H and V blanking intervals. When ANC_BLANK is HIGH, the Luma and Chroma data pass through the device unaltered. Only applicable in SMPTE mode. STATUS SIGNAL OUTPUT. H4 LOCKED Output Please refer to the Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. PLL lock indication. HIGH indicates PLL is locked. LOW indicates PLL is not locked. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 16 of 125 Table 1-1: Pin Descriptions (Continued) Pin Number Name H5 GRP2_EN/DIS Input Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. H6 GRP1_EN/DIS Input Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Timing Type Description Enables Audio Group 2 embedding. Set HIGH to enable. Enables Audio Group 1 embedding. Set HIGH to enable. STATUS SIGNAL OUTPUT. Please refer to the Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Summary Interrupt from Audio Processing. This signal is set HIGH by the device to indicate a problem with the audio processing which requires the Host processor to interrogate the interrupt status registers. H7 AUDIO_INT Output IO_VDD = +3.3V Drive Strength = 8mA IO_VDD = +1.8V Drive Strength = 4mA Note: By default, out of reset, the AUDIO_INT pin will output the HD_AUDIO_CLOCK, rather than the audio interrupt signal. In order to output the interrupt flags from the audio core as intended, the user must write 0001h to register 0232h. CONTROL SIGNAL INPUT. Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. H8 JTAG/HOST Input Used to select JTAG test mode or host interface mode. When JTAG/HOST is HIGH, the host interface port is configured for JTAG test. When JTAG/HOST is LOW, normal operation of the host interface port resumes and the separate JTAG pins become the JTAG port. Serial Audio Input; Channels 5 and 6. J4 AIN_5/6 Input J5 WCLK2 Input J6 AIN_1/2 Input Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. 48kHz Word Clock associated with AIN_5/6 and AIN_7/8 (channels 5, 6, 7 and 8). Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Serial Audio Input; Channels 1 and 2. J7 WCLK1 GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 Input Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. 48kHz Word Clock associated with AIN_1/2 and AIN_3/4 (channels 1, 2, 3 and 4). Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. www.semtech.com 17 of 125 Table 1-1: Pin Descriptions (Continued) Pin Number Name Timing Type Description COMMUNICATION SIGNAL INPUT. J8 TCK Input Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. JTAG Serial Data Clock Signal. This pin is the JTAG clock when the JTAG/HOST pin is LOW. COMMUNICATION SIGNAL OUTPUT. Please refer to the Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Shared JTAG/HOST pin. Provided for compatibility with the GS1582. Serial Data Output/Test Data Output. J9 SDOUT_TDO Output Host Mode (JTAG/HOST = LOW) This pin operates as the host interface serial output, used to read status and configuration information from the internal registers of the device. JTAG Test Mode (JTAG/HOST = HIGH) This pin is used to shift test results and operates as the JTAG test data output, TDO (for new designs, use the dedicated JTAG port). Note: If the host interface is not being used leave this pin unconnected. IO_VDD = +3.3V Drive Strength = 12mA IO_VDD = +1.8V Drive Strength = 4mA COMMUNICATION SIGNAL INPUT. Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Shared JTAG/HOST pin. Provided for pin compatibility with GS1582. Serial data clock signal. J10 SCLK_TCK Input Host Mode (JTAG/HOST = LOW) SCLK_TCK operates as the host interface burst clock, SCLK. Command and data read/write words are clocked into the device synchronously with this clock. JTAG Test Mode (JTAG/HOST = HIGH) This pin is the TEST MODE START pin, used to control the operation of the JTAG test clock, TCK (for new designs, use the dedicated JTAG port). Note: If the host interface is not being used, tie this pin HIGH. K4 AIN_7/8 Input Serial Audio Input; Channels 7 and 8. K5 ACLK2 Input 64 x WCLK associated with AIN_5/6 and AIN_7/8 (channels 5, 6, 7 and 8). K6 AIN_3/4 Input Serial Audio Input; Channels 3 and 4. K7 ACLK1 Input 64 x WCLK associated with AIN_1/2 and AIN_3/4 (channels 1, 2, 3and 4). GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 18 of 125 Table 1-1: Pin Descriptions (Continued) Pin Number Name Timing Type Description COMMUNICATION SIGNAL INPUT. Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Chip select / test mode start. K9 CS_TMS Input JTAG Test mode (JTAG/HOST = HIGH) CS_TMS operates as the JTAG test mode start, TMS, used to control the operation of the JTAG test, and is active HIGH (for new designs, use the dedicated JTAG port). Host mode (JTAG/HOST = LOW), CS_TMS operates as the host interface Chip Select, CS, and is active LOW. COMMUNICATION SIGNAL INPUT. Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Shared JTAG/HOST pin. Provided for pin compatibility with GS1582. K10 SDIN_TDI Input Serial data in/test data in. In JTAG mode, this pin is used to shift test data into the device (for new designs, use the dedicated JTAG port). In host interface mode, this pin is used to write address and configuration data words into the device. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 19 of 125 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Table 2-1: Absolute Maximum Ratings Parameter Value/Units Supply Voltage, Digital Core (CORE_VDD) -0.3V to +1.5V Supply Voltage, Digital I/O (IO_VDD) -0.3V to +3.6V Supply Voltage, Analog +1.2V (PLL_VDD, VCO_VDD) -0.3V to +1.5V Supply Voltage, Analog +3.3V (CD_VDD, A_VDD) -0.3V to +3.6V Input Voltage Range (RSET) -0.3V to (CD_VDD + 0.3)V Input Voltage Range (VBG) -0.3V to (A_VDD + 0.3)V Input Voltage Range (LF) -0.3V to (PLL_VDD + 0.3)V Input Voltage Range (digital inputs) -2.0V to +5.25V Temperature Range -40°C to +85°C Storage Temperature Range -40°C to +125°C Peak Reflow Temperature (JEDEC J-STD-020C) 260°C ESD Sensitivity, HBM (JESD22-A114) 2kV Note: Absolute Maximum Ratings are those values beyond which damage may occur. Functional operation outside of the ranges shown in Table 2-1 is not implied. 2.2 Recommended Operating Conditions Table 2-2: Recommended Operating Conditions Parameter Operating Temperature Range, Ambient Supply Voltage, Digital Core Supply Voltage, Digital I/O Symbol Conditions Min Typ Max Units Note TA – -20 − 85 °C – CORE_VDD – 1.14 1.2 1.26 V – +1.8V mode 1.71 1.8 1.89 V – +3.3V mode 3.13 3.3 3.47 V – IO_VDD Supply Voltage, PLL PLL_VDD – 1.14 1.2 1.26 V – Supply Voltage, VCO VCO_VDD – − 0.7 − V 1 A_VDD – 3.13 3.3 3.47 V – CD_VDD – 3.13 3.3 3.47 V – Supply Voltage, Analog Supply Voltage, CD GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 20 of 125 Table 2-2: Recommended Operating Conditions (Continued) Parameter Symbol Conditions Min Typ Max Units Note Operating Temperature Range – – -20 – 85 °C 2 Functional Temperature Range – – -40 – 85 °C 2 Notes: 1. This is 0.7V rather than 1.2V because there is a voltage drop across an external 105Ω resistor. See Typical Application Circuit. 2. Operating Temperature Range guarantees the parameters given in the DC Electrical Characteristics and AC Electrical Characteristics. Functional Temperature Range guarantees a device start-up. 2.3 DC Electrical Characteristics Table 2-3: DC Electrical Characteristics VCC = +3.3V ±5%, TA = -20°C to +85°C, unless otherwise shown Parameter Symbol Conditions Min Typ Max Units Note 10bit 3G − 135 200 mA − 20bit 3G − 135 200 mA − 10/20bit HD − 100 160 mA − 10/20bit SD − 75 120 mA − DVB_ASI − 75 120 mA − 10bit 3G − 15 30 mA − 20bit 3G − 15 32 mA − 10/20bit HD − 15 32 mA − 10/20bit SD − 3 10 mA − DVB_ASI − 3 10 mA − 10bit 3G − 90 110 mA − 20bit 3G − 90 110 mA − 10/20bit HD − 90 110 mA − 10/20bit SD − 70 90 mA − DVB_ASI − 70 90 mA − 10bit 3G − 400 560 mW − 20bit 3G − 400 560 mW − 10/20bit HD − 350 510 mW − 10/20bit SD − 300 450 mW − DVB_ASI − 300 450 mW − Reset − 200 − mW − Standby − 110 180 mW 1 System +1.2V Supply Current +1.8V Supply Current +3.3V Supply Current Total Device Power (IO_VDD = +1.8V) I1V2 I1V8 I3V3 P1D8 GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 21 of 125 Table 2-3: DC Electrical Characteristics (Continued) VCC = +3.3V ±5%, TA = -20°C to +85°C, unless otherwise shown Parameter Total Device Power (IO_VDD = +3.3V) Symbol P3D3 Conditions Min Typ Max Units Note 10bit 3G − 430 600 mW − 20bit 3G − 450 610 mW − 10/20bit HD − 420 550 mW − 10/20bit SD − 320 450 mW − DVB_ASI − 320 450 mW − Reset − 230 − mW − Standby − 110 180 mW 1 Digital I/O Input Logic LOW VIL +3.3V or +1.8V operation IO_VSS-0.3 − 0.3 x IO_VDD V − Input Logic HIGH VIH +3.3V or +1.8V operation 0.7 x IO_VDD − IO_VDD+0.3 V − Output Logic LOW VOL IOL=5mA, +1.8V operation − − 0.2 V − IOL=8mA, +3.3V operation − − 0.4 V − Output Logic HIGH VOH IOH=-5mA, +1.8V operation 1.4 − – V − IOH=-8mA, +3.3V operation 2.4 − – V − − CD_VDD VSDD/2 − V − Serial Output Serial Output Common Mode Voltage VCMOUT 75Ω load, RSET = 750Ω SD and HD mode Note: 1. Devices manufactured prior 1to April 1, 2011 consume 150mW of power in Standby mode. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 22 of 125 2.4 AC Electrical Characteristics Table 2-4: AC Electrical Characteristics VCC = +3.3V ±5%, TA = -20°C to +85°C, unless otherwise shown Parameter Symbol Conditions Min Typ Max Units Note – 3G bypass (PCLK = 148.5 MHz) – 54 – PCLK – – 3G SMPTE without audio (PCLK = 148.5 MHz) – 95 – PCLK – – 3G SMPTE with audio (PCLK = 148.5 MHz) – 1106 – PCLK – – 3G IOPROC disabled 20-bit mode (PCLK = 148.5MHz) – 94 – PCLK – – HD bypass (PCLK = 74.25 MHz) – 54 – PCLK – – HD SMPTE without audio (PCLK = 74.25 MHz) – 95 – PCLK – – HD SMPTE with audio (PCLK = 74.25 MHz) – 1106 – PCLK – – HD IOPROC disabled 10-bit mode (PCLK = 74.25MHz) – SD bypass (PCLK = 27 MHz) – 54 – PCLK – – SD SMPTE without audio – 112 – PCLK – – SD SMPTE with audio – 638 – PCLK – – SD IOPROC disabled 10-bit mode (PCLK = 27MHz) – 94 – PCLK – – DVB-ASI – 52 – PCLK – treset – 1 – – ms – Parallel Clock Frequency fPCLK – 13.5 – 148.5 MHz – Parallel Clock Duty Cycle DCPCLK – 40 – 60 % – Input Data Setup Time tsu 1.2 – – ns 1 Input Data Hold Time tih 50% levels; +3.3V or +1.8V operation 0.8 – – ns 1 System Device Latency Reset Pulse Width 98 Parallel Input Serial Digital Output GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 23 of 125 Table 2-4: AC Electrical Characteristics (Continued) VCC = +3.3V ±5%, TA = -20°C to +85°C, unless otherwise shown Parameter Serial Output Data Rate Symbol DRSDO Conditions Min Typ Max Units Note – – 2.97 – Gb/s – – – 2.97/1.001 – Gb/s – – – 1.485 – Gb/s – – – 1.485/1.001 – Gb/s – – – 270 – Mb/s – 750 800 850 mVpp 2 Serial Output Swing VSDD RSET = 750Ω 75Ω load Serial Output Rise/Fall Time 20% ~ 80% trfSDO 3G/HD mode – 120 135 ps – trfSDO SD mode 400 660 800 ps – Mismatch in rise/fall time Δtr ,Δtf – – – 35 ps – Duty Cycle Distortion Overshoot Output Return Loss – – – – 5 % 2 – 3G/HD mode – 5 10 % 2 – SD mode – 3 8 % 2 ORL 1.485GHz 2.97GHz – -12 – dB 3 5 MHz - 1.485 GHz – -18 – dB 3 tOJ Pseudorandom and SMPTE Colour Bars 3G signal – 40 68 ps 4, 6 tOJ Pseudorandom and SMPTE Colour Bars HD signal – 50 95 ps 4, 6 tOJ Pseudorandom and SMPTE Colour Bars SD signal – 200 400 ps 5 – – 80 MHz – 40 50 60 % – 1.5 – – ns – 1.5 – – ns – Serial Output Intrinsic Jitter Serial Output Intrinsic Jitter GSPI GSPI Input Clock Frequency fSCLK 50% levels +3.3V or +1.8V operation GSPI Input Clock Duty Cycle DCSCLK GSPI Input Data Setup Time – GSPI Input Data Hold Time – GSPI Output Data Hold Time – 15pF load 1.5 – – ns – t0 50% levels +3.3V or +1.8V operation 1.5 – – ns – – – ns – CS low before SCLK rising edge Time between end of command word (or data in Auto-Increment mode) and the first SCLK of the following data word - write cycle PCLK (MHz) t4 GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 50% levels +3.3V or +1.8V operation ns unlocked 445 13.5 74.2 27.0 37.1 74.25 13.5 148.5 6.7 www.semtech.com 24 of 125 Table 2-4: AC Electrical Characteristics (Continued) VCC = +3.3V ±5%, TA = -20°C to +85°C, unless otherwise shown Parameter Time between end of command word (or data in Auto-Increment mode) and the first SCLK of the following data word - read cycle CS high after SCLK falling edge Symbol t5 t7 Conditions 50% levels +3.3V or +1.8V operation 50% levels +3.3V or +1.8V operation Min PCLK (MHz) ns unlocked 1187 13.5 297 27.0 148.4 74.25 53.9 148.5 27 PCLK (MHz) ns unlocked 445 13.5 74.2 27.0 37.1 74.25 13.5 148.5 6.7 Typ Max Units Note – – ns – – – ns – Notes: 1. Input setup and hold time is dependent on the rise and fall time on the parallel input. Parallel clock and data with rise time or fall time greater than 500ps require larger setup and hold times. 2. Single Ended into 75Ω external load. 3. ORL depends on board design. 4. Alignment Jitter = measured from 100kHz to serial data rate/10. 5. Alignment Jitter = measured from 1kHz to 27MHz. 6. This is the maximum jitter for a BER of 10-12. The equivalent jitter value as per RP184 is 40ps max. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 25 of 125 3. Input/Output Circuits SDO SDO CD_VDD I REF Figure 3-1: Differential Output Stage (SDO/SDO) IO_VDD 200Ω Input Pin Figure 3-2: Digital Input Pin (20bit/10bit, ANC_BLANK, DETECT_TRS, DVB_ASI, RATE_SEL0, SMPTE_BYPASS, RATE_SEL1, TIM_861, F/DE, H/HSYNC, PCLK, V/VSYNC) IO_VDD 200Ω Input Pin Figure 3-3: Digital Input Pin with Schmitt Trigger (RESET) GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 26 of 125 IO_VDD 200Ω Input Pin Figure 3-4: Digital Input Pin with weak pull-down - maximum pull-down current Channel Status is based on user-defined data stored in the ACSR. With ACS_REGEN = 1, the GS2972 will serialize user-defined information to the output data. The user-defined data is applied to the output when the following steps are followed, and the time that the new status boundary occurs for the audio channel. Audio channel status replacement follows the same procedure when replacing audio channel status for either AES or I2S audio formats. To replace audio channel status, the following procedure should be used: 1. Write the desired ACS data to the ACSR [183:0] (SD Core registers 420h-42Ch, HD/3G Core registers 820h-82Ch). 2. Set ACS_REGEN bit = 1. 3. The Audio Channel Status on the serialized output will now contain the user defined ACS data. To replace audio channel status on the fly, the following procedure should be used: 1. Write the desired ACS data to the ACSR [183:0] (SD Core registers 420h-42Ch, HD/3G Core registers 820h-82Ch) 2. Set ACS_REGEN bit = 1, if ACS_REGEN is already set, re-write ACS_REGEN = 1 again. 3. The Audio Channel Status on the serialized output will now contain the user-defined ACS data. The GS2972 automatically calculates the CRC required for the Audio Channel Status block. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 53 of 125 4.7.12 Audio Crosspoint The GS2972 is capable of mapping any input channel to any Primary or Secondary group channel. Each group channel specifies the audio source using a 3-bit selector defined below in Table 4-9: Table 4-9: GS2972 SD Audio Crosspoint Channel Selection Audio Source SD Selector HD/3G Selector Input channel 1 000 000 Input channel 2 001 001 Input channel 3 010 010 Input channel 4 011 011 Input channel 5 100 100 Input channel 6 101 101 Input channel 7 110 110 Input channel 8 111 111 Each Primary and Secondary group channel specifies the audio source using the following host interface fields: Table 4-10: Audio Source Host Interface Fields Host Interface Field Description Default GPA_CH1_SRC[2:0] Primary Group Channel 1 Source Selector 000 GPA_CH2_SRC[2:0] Primary Group Channel 2 Source Selector 001 GPA_CH3_SRC[2:0] Primary Group Channel 3 Source Selector 010 GPA_CH4_SRC[2:0] Primary Group Channel 4 Source Selector 011 GPB_CH1_SRC[2:0] Secondary Group Channel 1 Source Selector 100 GPB_CH2_SRC[2:0] Secondary Group Channel 2 Source Selector 101 GPB_CH3_SRC[2:0] Secondary Group Channel 3 Source Selector 110 GPB_CH4_SRC[2:0] Secondary Group Channel 4 Source Selector 111 Audio channels can be paired only when both channels are derived from the same Word Clock and are synchronous. The same audio channel cannot be used in both Primary and Secondary groups at the same time. The GS2972 asserts the XPOINT_ERROR host interface bit if any audio channel is programmed to be included in both the Primary and Secondary groups. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 54 of 125 4.7.13 Audio Word Clock When the GS2972 combines two stereo pair inputs into one audio group, the format allows for only one Word Clock, or sampling clock. For the Primary group, the GS2972 uses the Word Clock associated with the source selected by the GPA_WCLK_SRC[2:0] host interface field. If in SD mode, address 40Ch. If in HD/3G mode, address 80Bh. For the Secondary group, the GS2972 uses the Word Clock associated with the source selected by the GPB_WCLK_SRC[2:0] host interface field. If in SD mode, address 40Dh. If in HD/3G mode, address 80Ch. For proper operation, the combined Stereo Pair inputs must have identical Word Clocks. WCLK is not required for AES/EBU audio. 4.7.14 Channel & Group Activation The GS2972 embeds Primary group packets when any of the following host interface bits are set and the associated audio group enable pin is HIGH: ACT1 Embed Primary group audio channel 1 ACT2 Embed Primary group audio channel 2 ACT3 Embed Primary group audio channel 3 ACT4 Embed Primary group audio channel 4 If none of the bits are set, then no audio will be embedded. The GS2972 will embed Secondary group packets when any of the following host interface bits are set and the associated audio group enable pin is HIGH: ACT5 Embed Secondary group audio channel 1 ACT6 Embed Secondary group audio channel 2 ACT7 Embed Secondary group audio channel 3 ACT8 Embed Secondary group audio channel 4 When an embedded packet contains one or more channels with the ACTx bit set to zero, the GS2972 replaces the data for those channels with null samples (all bits set to zero). In the default state, the GS2972 embeds all audio channels in accordance with the setting of the respective audio group enable pins of the device. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 55 of 125 4.7.15 Audio FIFO - SD Each input channel has a First In First Out (FIFO) buffer that can hold up to 52 samples. Samples are added (written) to the FIFO as they are received from the audio inputs. Samples are removed (read) from the FIFO as they are embedded in audio data packets and audio extended packets. After power up, reset or clear, the FIFO is in the start-up state where it will output zeroes until it has accumulated the start-up count of 26 samples. When the start-up state ends, the buffer operates as a normal FIFO, and expects to receive an equal number of read and write operations over the period of five frames. At the end of five frames, the FIFO still has 26 samples in the buffer. When the FIFO does not receive an equal number of read and write operations, the FIFO checks for the overflow and underflow conditions. When a sample is required for embedding into a packet and the FIFO is holding less than 6 samples, the GS2972 prevents the underflow condition by repeating the last sample without removing a sample from the FIFO. Therefore, a sample will be duplicated. When an input sample is received and the FIFO has room for less than six more samples, the GS2972 prevents the overflow condition by discarding the sample. Therefore, a sample will be dropped. If 28 consecutive samples are duplicated or dropped, the audio FIFO is cleared and placed into the start-up state. If the CLEAR_AUDIO host interface bit is set, the audio FIFO is cleared and put into the start-up state. When the detected video standard changes, the audio FIFO is cleared and put into the start-up state. The buffer size and start-up count can be reduced using the OS_SEL host interface field, as seen in Table 4-11 below: Table 4-11: GS2972 SD Audio Buffer Size Selection Address OS_SEL[1:0] Buffer Size Start-Up Count 00 52 samples (default) 26 samples 01 24 samples 12 samples 10 12 samples 6 samples 11 Reserved Reserved GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 56 of 125 4.7.16 Audio FIFO - HD and 3G For HD and 3G formats, the audio FIFO block is a maximum of seven samples deep. According to SMPTE ST 299, audio samples are multiplexed immediately in the next HANC region after the audio sample occurs. A buffer size of seven samples takes into account that there are no samples after the switching line (for one line) and the worst-case video standard of 720p/24, plus a one-sample safety margin. Due to the sample distribution used in HD video standards and the size of the buffer in HD mode, no checking is made for buffer underflow/overflow conditions. The pointers should maintain a variable offset between 0 and 6. 4.7.17 Five-frame Sequence Detection - SD The GS2972 detects the frame sequence that describes the sample distribution for synchronous audio. The frame sequence is used in the generation of audio control packets; where the Audio Frame Number (AFN) field describes the position of the current frame within the frame sequence. The frame sequence is also used in the generation of Audio Sample Distribution for formats with 525 lines. Each frame has 1602 samples or 1601 samples, depending upon the frame sequence. The GS2972 sets the AFN of the Primary group control packets to zero, unless the AFNA_AUTO host interface bit (400h bit 7) is set to produce automatic AFN generation. The Multiplexer sets the AFN of the Secondary group control packets to zero unless the AFNB_AUTO host interface bit (800h bit 10) is set to produce automatic AFN generation. When the frame rate is 25Hz, every frame has 1920 samples and the AFN is always set to one. When the frame rate is 29.97Hz, an even number of samples (8008) are distributed over five frames in the following sequence: 1602 1601 1602 1601 1602 The GS2972 sets the AFN field to a number between one and five, depending on where the current frame lies within the sequence. The GS2972 adds the offset specified in the AFN_OFS host interface field (400h bits 6-4) to the generated AFN. The result of the addition wraps around such that the AFN will always be in the range of one to five. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 57 of 125 4.7.17.1 525-Line Audio Sample Distribution As per the SMPTE ST 272 standard, the following sample distribution allows the embedding of 16 channels (4 audio groups) of 24-bit sampled audio into the HANC of 525-line based video formats. The sample distribution is established for Group One and then offset by one line for each subsequent group. The sample distribution is as follows (start line is 12): {[3](10+G),([4],[3]15)15,[4],[3](11-G),[0],[3](3+G),([4],[3]15)15,[4/3],[3]12,[4],[3](4-G),[0]}5 [#] = Number of samples / line [4/3] = One line with either 3 or 4 samples depending on five-frame sequence (#) = Number of times to repeat the sequence. When this # is 0, no samples are inserted G = Audio group number from 1 to 4 {…}5 = 5-frame sequence as shown in Table 4-12: Table 4-12: GS2972 SD Audio Five Frame Sequence Sample Count Frame Number of Samples 1 1602 2 1601 3 1602 4 1601 5 1602 The following tables show the audio sample distribution for each of the four audio groups. Each distribution has 525 lines. Each distribution has 1602 samples or 1601 samples, based on the frame number in the five-frame sequence. When 1602 samples are required in a frame, the [4/3] term represents a line with four samples. When 1601 samples are required in a frame, the [4/3] term represents a line with three samples. Table 4-13: GS2972 SD Audio Group 1 Audio Sample Distribution - 525 line [3](6),[4],[3](3) [0],[3](11) ([4],[3]15)15 [4],[3](10) [0],[3](4) ([4],[3]15)15 [4/3],[3](6) Samples 31 33 735 34 12 735 22/21 Lines 10 12 240 11 5 240 7 GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 58 of 125 Table 4-14: GS2972 SD Audio Group 2 Audio Sample Distribution - 525 line [3](7),[4],[3](2) [0],[3](12) ([4],[3]15)15 [4],[3](9) [0],[3](5) ([4],[3]15)15 [4/3],[3](5) Samples 31 36 735 31 15 735 19/18 Lines 10 13 240 10 6 240 6 Table 4-15: GS2972 SD Audio Group 3 Audio Sample Distribution - 525 line [3](8),[4],[3](1) [0],[3](13) ([4],[3]15)15 [4],[3](8) [0],[3](6) ([4],[3]15)15 [4/3],[3](4) Samples 31 39 735 28 21 735 16/15 Lines 10 14 240 9 7 240 5 Table 4-16: GS2972 SD Audio Group 4 Audio Sample Distribution - 525 line [3](9),[4],[3](0) [0],[3](14) ([4],[3]15)15 [4],[3](7) [0],[3](7) ([4],[3]15)15 [4/3],[3](3) Samples 31 42 735 25 21 735 13/12 Lines 10 15 240 8 8 240 4 4.7.17.2 625-Line Audio Sample Distribution The GS2972 uses the following sample distribution to maximize the available space in the Ancillary Data region. Note: the following formula starts from line 1: [3]6,[0],[3](G-1),([4],[3]11)25,[4],[3](12-G),[0],[3](G-1),([4],[3]11)24,[4],[3](17-G) • [#] represents one line with # samples • (#) represents the number of times to repeat the line sequence • [3](0) represents no lines and no samples • G is the audio group number from one to four The following tables show the audio sample distribution for each of the four audio groups: Each distribution has 625 lines. Each distribution has 1920 samples. Table 4-17: GS2972 SD Audio Group 1 Audio Sample Distribution - 625 line [3]6 [0],[3](0) ([4],[3]11)25 [4],[3](11) [0],[3](0) ([4],[3]11)24 [4],[3](16) Samples 18 0 925 37 0 888 52 Lines 6 1 300 12 1 288 17 GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 59 of 125 Table 4-18: GS2972 SD Audio Group 2 Audio Sample Distribution - 625 line [3]6 [0],[3](1) ([4],[3]11)25 [4],[3](10) [0],[3](1) ([4],[3]11)24 [4],[3](15) Samples 18 3 925 34 3 888 49 Lines 6 2 300 11 2 288 16 Table 4-19: GS2972 SD Audio Group 3 Audio Sample Distribution - 625 line [3]6 [0],[3](2) ([4],[3]11)25 [4],[3](9) [0],[3](2) ([4],[3]11)24 [4],[3](14) Samples 18 6 925 31 6 888 46 Lines 6 3 300 10 3 288 15 Table 4-20: GS2972 SD Audio Group 4 Audio Sample Distribution - 625 line [3]6 [0],[3](3) ([4],[3]11)25 [4],[3](8) [0],[3](3) ([4],[3]11)24 [4],[3](13) Samples 18 9 925 28 9 888 43 Lines 6 4 300 9 4 288 14 4.7.18 Frame Sequence Detection - HD/3G The GS2972 detects the frame sequence that describes the sample distribution for synchronous audio. The frame sequence is only used in the generation of audio control packets; where the Audio Frame Number (AFN) field describes the position of the current frame within the frame sequence. The GS2972 sets the AFN of the Primary group control packets to zero when the ASXA host interface bit is set for asynchronous audio. The GS2972 sets the AFN of the Primary group control packets to zero, unless the AFNA_AUTO host interface bit is set to produce automatic AFN generation. The GS2972 sets the AFN of the Secondary group control packets to zero, when the ASXB host interface bit is set for asynchronous audio. The GS2972 sets the AFN of the Secondary group control packets to zero, unless the AFNB_AUTO host interface bit is set to produce automatic AFN generation. The GS2972 sets the AFN to one when every frame has the same number of samples: Frame Rate 23.976Hz - Each frame has exactly 2002 samples Frame Rate 24.000Hz - Each frame has exactly 2000 samples Frame Rate 25.000Hz - Each frame has exactly 1920 samples Frame Rate 30.000Hz - Each frame has exactly 1600 samples Frame Rate 50.000Hz - Each frame has exactly 960 samples Frame Rate 60.000Hz - Each frame has exactly 800 samples GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 60 of 125 When the frame rate is 29.97Hz, an even number of samples (8008) are distributed over five frames in the following sequence: 1602 1601 1602 1601 1602 When the frame rate is 59.94Hz, an even number of samples (4004) are distributed over five frames in the following sequence: 801 800 801 801 801 The GS2972 sets the AFN field to a number between one and five, depending on where the current frame lies within the sequence. The GS2972 adds the offset specified in the AFN_OFS host interface field to the generated AFN. The result of the addition wraps around such that the AFN will always be in the range of one to five. 4.7.19 ECC Error Detection and Correction The GS2972 generates the error detection and correction fields in the audio data packets. The error detection and correction complies with SMPTE ST 299. 4.7.20 Audio Control Packet Insertion - SD The GS2972 embeds audio control packets associated with the Primary Group audio and the Secondary Group audio. The Primary Group audio to be embedded is specified using the IDA[1:0] host interface field (Address 400h). The Secondary Group audio to be embedded is specified using the IDB[1:0] host interface field. The Primary Group audio control packets is embedded as commanded by the CTRA_ON host interface bit. (Default is ON) The Secondary Group audio control packets is embedded as commanded by the CTRB_ON host interface bit. (Default is ON) The Primary Group audio control packets is replaced as commanded by the CTR_AGR host interface bit. (Default is OFF) The Secondary Group audio control packets is replaced as commanded by the CTR_AGR and ONE_AGR host interface bits. (Default is OFF) The contents of the Primary Group audio control packet is specified using the following host interface fields: AFNA_AUTO Primary Group audio frame number generation. EBIT1A Primary Group delay valid flag for channel 1. DEL1A[25:0] Primary Group delay for channel 1. EBIT2A Primary Group delay valid flag for channel 2. DEL2A[25:0] Primary Group delay for channel 2. EBIT3A Primary Group delay valid flag for channel 3. DEL3A[25:0] Primary Group delay for channel 3. EBIT4A Primary Group delay valid flag for channel 4. DEL4A[25:0] Primary Group delay for channel 4. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 61 of 125 The contents of the Secondary Group audio control packet is specified using the following host interface fields: AFNB_AUTO Secondary Group audio frame number generation. EBIT1B Secondary Group delay valid flag for channel 1. DEL1B[25:0] Secondary Group delay for channel 1. EBIT2B Secondary Group delay valid flag for channel 2. DEL2B[25:0] Secondary Group delay for channel 2. EBIT3B Secondary Group delay valid flag for channel 3. DEL3B[25:0] Secondary Group delay for channel 3. EBIT4B Secondary Group delay valid flag for channel 4. DEL4B[25:0] Secondary Group delay for channel 4. 4.7.21 Audio Control Packet Insertion - HD and 3G The GS2972 embeds audio control packets associated with the Primary Group audio and the Secondary Group audio. The Primary Group audio to be embedded is specified using the IDA[1:0] host interface field. (Default is 00 in NORMAL mode). The Secondary Group audio to be embedded is specified using the IDB[1:0] host interface field. (Default is 01 in NORMAL mode). The Primary Group audio control packets are embedded as commanded by the CTRA_ON host interface bit. (Default is 1). The Secondary Group audio control packets are embedded as commanded by the CTRB_ON host interface bit. (Default is 1). The Primary Group audio control packets are replaced as commanded by the CTR_AGR host interface bit. (Default is 0). The Secondary Group audio control packets are replaced as commanded by the CTR_AGR and ONE_AGR host interface bits. (Default is 0). The Primary Group audio control packets are not embedded or replaced unless one or more of the ACT1, ACT2, ACT3 or ACT4 host interface bits are set. The Secondary Group audio control packets are not embedded or replaced unless one or more of the ACT5, ACT6, ACT7 or ACT8 host interface bits are set. The contents of the Primary Group audio control packet is specified using the following host interface fields: AFNA_AUTO - Primary Group audio frame number auto-generation. ASXA - Primary Group asynchronous mode. DEL1_2A[25:0] - Primary Group audio delay for channels 1 and 2. DEL3_4A[25:0] - Primary Group audio delay for channels 3 and 4. The contents of the Secondary Group audio control packet is specified using the following host interface fields: AFNB_AUTO - Secondary Group audio frame number auto-generation. ASXB - Secondary Group asynchronous mode. DEL1_2B[25:0] - Secondary Group audio delay for channels 1 and 2. DEL3_4B[25:0] - Secondary Group audio delay for channels 3 and 4. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 62 of 125 4.7.22 Audio Data Packet Insertion In Normal Mode, the GS2972 embeds audio data packets into a space where all pre-existing embedded audio data packets have been removed. In Cascade Mode, the GS2972 embeds audio data packets contiguously after all of the pre-existing audio data packets. The GS2972 does not replace any pre-existing audio data packets with new audio packets, even if the new audio packets have the same group number. In this situation, the new audio data packets are appended to the last packet, and there is an illegal mix of different groups using the same group number. This condition will be indicated by the following host interface bits: Š MUX_ERRA: Set in Cascade Mode when Primary Group audio data packets are added to video that already contains audio data packets with the same group number Š MUX_ERRB: Set in Cascade Mode when Secondary Group audio data packets are added to video that already contains audio data packets with the same group number In Group Replacement Mode the GS2972 embeds audio data packets and sorts all of the embedded audio data packets in order of group number. If there are any pre-existing audio data packets with the same group number as the new audio packets, then the pre-existing packets will be replaced. In Group Replacement Mode the GS2972 replaces only the Primary Group audio if the ONE_AGR host interface bit is set. The GS2972 deletes arbitrary data packets if there is not enough room in the horizontal ancillary data space to embed the selected audio data packets. The GS2972 does not embed audio data packets when there is insufficient room in the horizontal ancillary data space after deleting arbitrary data packets. 4.7.22.1 Audio Data Packet Insertion - SD only The GS2972 embeds the audio channels specified by the ACT[8:1] host interface fields. The GS2972 detects and preserves embedded EDH packets. The GS2972 generates extended packets for 24-bit audio when the AUDIO_24BIT host interface bit is set. 4.7.22.2 Blanking Values Following Audio Data Packet Insertion For 3G Level A, Level B dual-stream, and Level B dual-link Y’C’BC’R 4:2:2 10-bit formats, the audio insertion block will insert blanking data in accordance with the original video format. For all other video formats (for example: RGB 4:4:4 10-bit or 12-bit, Y’C’BC’R 12-bit), the audio block will insert blanking values of 200h and 040h, which may not match the blanking data of the original format. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 63 of 125 4.7.23 Audio Interrupt Control The GS2972 will assert the interrupt signal when an internal interrupt condition becomes true and the type of interrupt is enabled. The following host interface bits enable the various interrupt sources: i Table 4-21: Audio Interrupt Control – Host Interface Bit Description Bit Name Description Bit Address (SD) Bit Address (HD&3G) EN_NO_VIDEO Asserts interrupt when video format is unknown 40Eh-14 80Dh-14 EN_ACPG1_DET Asserts interrupt when ACPG1_DET flag is set 40Eh-4 80Dh-4 EN_ACPG2_DET Asserts interrupt when ACPG2_DET flag is set 40Eh-5 80Dh-5 EN_ACPG3_DET Asserts interrupt when ACPG3_DET flag is set 40Eh-6 80Dh-6 EN_ACPG4_DET Asserts interrupt when ACPG4_DET flag is set 40Eh-7 80Dh-7 EN_ADPG1_DET Asserts interrupt when ADPG1_DET flag is set 40Eh-0 80Dh-0 EN_ADPG2_DET Asserts interrupt when ADPG2_DET flag is set 40Eh-1 80Dh-1 EN_ADPG3_DET Asserts interrupt when ADPG3_DET flag is set 40Eh-2 80Dh-2 EN_ADPG4_DET Asserts interrupt when ADPG4_DET flag is set 40Eh-3 80Dh-3 EN_AES_ERRA Asserts interrupt when AES_ERRA flag is set 40Eh-8 80Dh-8 EN_AES_ERRB Asserts interrupt when AES_ERRB flag is set 40Eh-9 80Dh-9 EN_AES_ERRC Asserts interrupt when AES_ERRC flag is set 40Eh-10 80Dh-10 EN_AES_ERRD Asserts interrupt when AES_ERRD flag is set 40Eh-11 80Dh-11 EN_MUX_ERRA Asserts interrupt when MUX_ERRA flag is set 40Eh-12 80Dh-12 EN_MUX_ERRB Asserts interrupt when MUX_ERRB flag is set 40Eh-13 80Dh-13 By default, the interrupts are all disabled. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 64 of 125 4.8 ANC Data Insertion Horizontal or vertical ancillary data words may be inserted on up to four different lines per video frame. Up to 512 data words may be inserted per frame with all Data Words - including the ANC packet ADF, DBN, DCNT, DID, SDID and CSUM words - being provided by the user via host interface configuration. The CSUM word is re-calculated and inserted by the ANC Data Checksum Calculation and Insertion function. Note that any value may be used for the CSUM word, provided that it is outside the protected ranges from 000h to 003h and from 3FCh to 3FFh. If a CSUM value in either of these ranges is used, it will not be corrected by the device. The GS2972 does not provide error checking or correction to the ANC data provided by user via the host interface. It is the responsibility of the user to ensure that all data provided for insertion is fully standard compliant. In 3G Level A mode, ancillary data packets are inserted into Data Stream One or Data Stream Two as selected by the host interface. The default insertion will be in Data Stream One. See address 02Dh, STREAM_TYPE1_LINE_X. In 3G Level B mode, ancillary data packets are inserted into the Y or C video stream of Link A or Link B as selected by the user in the host interface. The default insertion will be in the Y video stream of Link A. For Link A or Link B, see Register 02Dh. For Y or C, see Registers 026h, 028h, 02Ah and 02Ch. In HD mode, ANC data packets are inserted into the Y or C video stream, as selected via the host interface. The default insertion will be in the Y stream. For Y or C, see Registers 026h, 028h, 02Ah and 02Ch. In SD mode, the ANC data packets are inserted into the multiplexed CbYCr data stream. ANC data insertion only takes place if the IOPROC_EN/DIS pin is HIGH and SMPTE_BYPASS is HIGH. In addition to this, the GS2972 requires the ANC_INS bit to be set LOW in the IOPROC register. The ANC_PACKET_BANK register (040h - 13Fh) is used to program the ANC data words for ANC data insertion. 4.8.1 ANC Insertion Operating Modes User selection of one of the two operating modes is provided through host interface configuration, using the ANC_INS_MODE register bit (see Table 4-34: Video Core Configuration and Status Registers). The supported operating modes are Concatenated mode and Separate Line operating mode. By default (at power up or after system reset), the Separate Line operating mode is enabled. Ancillary data packets are programmed into the ANC_PACKET_BANK host register at addresses 040h to 13Fh. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 65 of 125 4.8.1.1 Separate Line Operating Mode In Separate Line mode, it is possible to insert horizontal or vertical ancillary data on up to four lines per video frame. In Separate Line mode, the ANC_PACKET_BANK bits are separated in four sections. Each section consists of 64 x 16-bit registers. ANC_PACKET_BANK_1 uses registers 040h to 07Fh. ANC_PACKET_BANK_2 uses registers 080h to 0BFh. ANC_PACKET_BANK_3 uses registers 0C0h to 0FFh. ANC_PACKET_BANK_4 uses registers 100h to 13Fh. HANC or VANC can be specified, independently of each other, on a per-line basis. 025h FIRST_LINE_NUMBER, 027h SECOND_LINE_NUMBER, 029h THIRD_LINE_NUMBER and 02Bh FOURTH_LINE_NUMBER. For each of the four video lines, up to 128 x 8-bit HANC or VANC data words can be inserted. Separate Line mode is selected by setting the ANC_INS_MODE bit in the host interface LOW. By default, at power up, Separate Line mode is selected. The lines on which ancillary data is to be inserted is programmed in the host register addresses 025h to 02Ch. For HD formats, the stream into which the ancillary data is to be inserted (Luma or Chroma) is also programmed in these register addresses. The non-zero video line numbers on which to insert the ancillary data, the ancillary data type (HANC or VANC), and the total number of words to insert per line must be provided via the host interface (see Section 4.14). At power up, or after system reset, all ancillary data insertion line numbers and total number of words default to zero. If the total number of Data Words specified per line exceeds 128 only the first 128 Data Words will be inserted, the rest will be ignored. The data words are programmed as two 8-bit values per address, starting at host interface address 040h in the ANC_PACKET_BANK register (see Table 4-34). The device automatically converts the provided 8-bit Data Words into the 10-bit data, formatted according to SMPTE ST 291 prior to insertion. 4.8.1.2 Concatenated Operating Mode In Concatenated mode, it is possible to insert up to 512 8-bit horizontal or vertical ancillary Data Words on one line per video frame. Concatenated Line mode can be selected by setting the ANC_INS_MODE bit in the host interface HIGH. By default, at power up, Separate Line mode is selected. In Concatenated mode, only the FIRST_LINE registers of the host interface need to be programmed (addresses 025h and 026h). See Table 4-34. The non-zero video line number on which to insert the ancillary data, the ancillary data type (HANC or VANC), and the total number of words to insert must be provided via the host interface. At power up, or after system reset, the ancillary data insertion line number and total number of words default to zero. If the total number of data words specified exceeds 512 only the first 512 Data Words will be inserted, the rest will be ignored. The data words are programmed as two 8-bit values per address, starting at host interface address 040h in the ANC_PACKET_BANK register. See Table 4-34. The device automatically converts the provided 8-bit data words into the 10-bit data formatted according to SMPTE ST 291 prior to insertion. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 66 of 125 4.8.2 3G ANC Insertion 4.8.2.1 Level A Mode When operating in 3G (RATE _SEL0 = LOW, RATE_SEL1 = HIGH) Level A mode, the GS2972 inserts VANC or HANC data packets into Data Stream One (default) or Data Stream Two. The data stream for insertion is selectable for each of the ANC insertion lines selected via the host interface. Data Stream One is selected when the STREAM_TYPE_1 bit in the register associated with the insertion line is set LOW (default). Data Stream Two is selected when the STREAM_TYPE_1 bit associated with the insertion line is set HIGH. ANC data should be placed in DS1 first in Level A mode, and only in DS2 as an overflow if DS1 is full. Data insertion starts at the first available location in the HANC space following any audio and pre-existing arbitrary data packets. All Data Words identified by the user are inserted in a contiguous fashion starting at the first available data space. HANC data insertion terminates when all Data Words identified by the user have been inserted; or by the start of the four word TRS SAV code, regardless of the number of Data Words actually inserted. The rest of the packet will be ignored. Vertical Ancillary data (VANC), is inserted into the data stream on the video line(s) defined by the user. Data insertion starts at the first active pixel immediately following the last word of the TRS SAV code. All Data Words identified by the user are inserted in a contiguous fashion, starting at the first active pixel. VANC data insertion terminates when all data words identified by the user have been inserted; or by the start of the four word TRS EAV code, regardless of the number of Data Words actually inserted. The total number of Data Words to be inserted and the line number on which the ANC data insertion takes place is provided by the user via the host interface as part of the configuration of the ANC data insertion function. The user data for insertion is provided via the host interface register STREAM_TYPE_1 (02Dh). GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 67 of 125 4.8.2.2 Level B Mode When operating in 3G (RATE_SEL0 = LOW, RATE_SEL1 = HIGH) Level B mode, the GS2972 inserts VANC or HANC data packets into either the Y or C data stream of Data Stream One (default) or Data Stream Two, as selected by the STREAM_TYPE_1 bit in the host interface on a per line basis. By default (at power up or after system reset), all ANC data insertion takes place in the Y data stream of Data Stream One. The user can select between the Y or C data stream for insertion on a per line basis in Separate Line mode. The Y data stream is selected when the STREAM_TYPE_0 bit is LOW (default). The C data stream is selected when the STREAM_TYPE_0 bit is HIGH. The user can select between the Y or C data stream for insertion on a single line basis in Concatenated mode. The Y data stream is selected when the STREAM_TYPE_0 bit is LOW (default). The C data stream is selected when the STREAM_TYPE_0 bit is HIGH. Horizontal Ancillary data (HANC), is inserted into the Y or C data stream on the video line(s) defined by the user. Data insertion starts at the first available location in the HANC space following any audio and pre-existing arbitrary data packets. All Data Words identified by the user are inserted in a contiguous fashion, starting at the first available data space. HANC data insertion terminates when all Data Words identified by the user have been inserted; or by the start of the four word TRS SAV code, regardless of the number of data words actually inserted. Vertical Ancillary data (VANC), is inserted into the Y or C data stream on the video line(s) defined by the user. Data insertion starts at the first active pixel immediately following the last word of the TRS SAV code. All Data Words identified by the user are inserted in a contiguous fashion starting at the first active pixel. VANC data insertion terminates when all Data Words identified by the user have been inserted; or by the start of the four word TRS EAV code, regardless of the number of Data Words actually inserted. The total number of data words to be inserted and line number on which ANC data insertion takes place is provided by the user via the host interface as part of the configuration of the ANC data insertion function. The user data for insertion is provided via the host interface. STREAM_TYPE_1 = address 02Dh, STREAM_TYPE_0 for the four lines of insertion is at addresses 026h (bit 14), 028h (bit 14), 02Ah (bit 14) and 02Ch (bit 14). GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 68 of 125 4.8.3 HD ANC Insertion When operating in HD mode (RATE_SEL0 = LOW, RATE_SEL1 = LOW), the GS2972 inserts VANC or HANC data packets into either the Y data stream or C data stream. By default (at power up or after system reset), all ANC data insertion takes place in the Y data stream. The user can select between Y or C data stream for insertion on a per line basis in Separate Line mode. The Y data stream is selected when the STREAM_TYPE_0 bit is LOW (default). The C data stream is selected when the STREAM_TYPE_0 bit is HIGH. The user can select between Y or C data stream for insertion on a single line basis in Concatenated mode. The Y data stream is selected when the STREAM_TYPE_0 bit is LOW (default). The C data stream is selected when the STREAM_TYPE_0 bit is HIGH. Horizontal Ancillary data (HANC), is inserted into the Y or C data stream on the video line(s) defined by the user. Data insertion starts at the first available location in the HANC space, following any audio and pre-existing arbitrary data packets. All Data Words identified by the user are inserted in a contiguous fashion starting at the first available data space. HANC data insertion terminates when all Data Words identified by the user have been inserted; or by the start of the four word TRS SAV code, regardless of the number of Data Words actually inserted. Vertical Ancillary data (VANC), is inserted into the Y or C data stream on the video line(s) defined by the user. Data insertion starts at the first active pixel immediately following the last word of the TRS SAV code. All Data Words identified by the user are inserted in a contiguous fashion, starting at the first active pixel. VANC data insertion terminates when all Data Words identified by the user have been inserted; or by the start of the four word TRS EAV code, regardless of the number of Data Words actually inserted. The total number of Data Words to be inserted and the line number on which ANC data insertion takes place is provided by the user via the host interface as part of the configuration of the ANC data insertion function. The user data for insertion is provided via host interface configuration. STREAM_TYPE_1 = address 02Dh, STREAM_TYPE_0 for the four lines of insertion is at addresses 026h (bit 14), 028h (bit 14), 02Ah (bit 14) and 02Ch (bit 14). GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 69 of 125 4.8.4 SD ANC Insertion When operating in SD mode (RATE_SEL0 = HIGH), the GS2972 inserts VANC or HANC data packets into the multiplexed CbYCr data stream. Horizontal Ancillary data (HANC), is inserted on the video line(s) defined by the user. Data insertion starts at the first available location in the HANC space following any audio and pre-existing arbitrary data packets. All Data Words identified by the user are inserted in a contiguous fashion, starting at the first available data space. HANC data insertion terminates when all Data Words identified by the user have been inserted; or by the start of the four word TRS SAV code, regardless of the number of Data Words actually inserted. For the case where HANC data insertion is required on the same line as the EDH packet, data insertion is terminated by the start of the EDH packet, regardless of the number of Data Words actually inserted. Vertical Ancillary data (VANC), is inserted into the data stream on the video line(s) defined by the user. Data insertion starts at the first active Cb pixel immediately following the last word of the TRS SAV code. All data words identified by the user are inserted in a contiguous fashion, starting at the first active pixel. VANC data insertion terminates when all Data Words identified by the user have been inserted; or by the start of the four word TRS EAV code, regardless of the number of Data Words actually inserted. The total number of data words to be inserted and the line number on which ANC data insertion takes place is provided by the user via the host interface as part of the configuration of the ANC data insertion function. The user data for insertion is provided via host interface configuration. STREAM_TYPE_1 = address 02Dh, STREAM_TYPE_0 for the four lines of insertion is at addresses 026h (bit 14), 028h (bit 14), 02Ah (bit 14) and 02Ch (bit 14). GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 70 of 125 4.9 Additional Processing Functions The GS2972 contains a number of signal processing features. These features are only enabled in SMPTE mode of operation (SMPTE_BYPASS = HIGH), and when I/O processing is enabled (IOPROC_EN/DIS = HIGH). Signal processing features include: • TRS generation and insertion • Line number calculation and insertion • Line based CRC calculation and insertion • Illegal code re-mapping • SMPTE ST 352 payload identifier packet insertion • ANC checksum calculation and correction • EDH generation and insertion • Audio Embedding • SMPTE ST 372 conversion To enable these features in the GS2972, the SMPTE_BYPASS pin must be HIGH, the IOPROC_EN/DIS pin must be HIGH and the individual feature must be enabled via bits set in the IOPROC register of the host interface. By default, all of the processing features are enabled, except for SMPTE ST 372 conversion. 4.9.1 Video Format Detection By using the timing parameters extracted from the received TRS signals, or the supplied external timing signals, the GS2972 calculates the video format. The total samples per line, active samples per line, total lines per field/frame, and active lines per field/frame are measured and reported to the user via the four RASTER_STRUC_X registers in the host interface. These line and sample count registers are updated once per frame at the end of line 12. The RASTER_STRUC_X registers also contain two status bits: STD_LOCK and INT/PROG. The STD_LOCK bit is set HIGH whenever the automatic video format detection circuit has achieved full synchronization. The INT/PROG bit is set LOW if the detected video standard is Progressive, and is set HIGH if the detected video standard is Interlaced. The Gennum video standard code (VD_STD), as used in the GS2972, GS1582 and GS1572, is included in Table 4-22 for reference purposes. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 71 of 125 Table 4-22: Supported Video Standards SMPTE STANDARD ACTIVE VIDEO AREA LENGTH OF HANC LENGTH OF ACTIVE VIDEO TOTAL SAMPLES SMPTE ST 352 LINES Gennum VD_STD [4:0] RATE_ SEL1 ST 428.1 2048x1080/24 (1:1) 690 2048 2750 10 1Ch 1 ST 428.1 2048x1080/25 (1:1) 580 2048 2640 10 1Ch 1 1920x1080/60 (1:1) 268 1920 2200 10 (18)1 0Bh 1 1920x1080/50 (1:1) 708 1920 2640 10 (18)1 0Dh 1 2682 19202 2200 10, 572 0Ah 1 7082 19202 2640 10, 572 0Ch 1 1280x720/60 (1:1) 3582 12802 1650 10 (13)1 00h 1 1280x720/50 (1:1) 6882 12802 1980 10 (13)1 04h 1 1920x1080/30 (1:1) 2682 19202 2200 10 (18)1 0Bh 1 1920x1080/25 (1:1) 7082 19202 2640 10 (18)1 0Dh 1 1280x720/25 (1:1) 26682 12802 3960 10 (13)1 06h 1 1920x1080/24 (1:1) 8182 19202 2750 10 (18)1 10h 1 1280x720/24 (1:1) 28332 12802 4125 10 (13)1 08h 1 ST 260 (HD) 1920x1035/60 (2:1) 268 1920 2200 10, 572 15h 0 ST 295 (HD) 1920x1080/50 (2:1) 444 1920 2376 10, 572 14h 0 268 1920 2200 10, 572 0Ah 0 708 1920 2640 10, 572 0Ch 0 1920x1080/30 (1:1) 268 1920 2200 10 (18)1 0Bh 0 1920x1080/25 (1:1) 708 1920 2640 10 (18)1 0Dh 0 1920x1080/24 (1:1) 818 1920 2750 10 (18)1 10h 0 1920x1080/24 (PsF) 818 1920 2750 10, 572 11h 0 1920x1080/25 (1:1) – EM 324 2304 2640 10 (18)1 0Eh 0 1920x1080/25 (PsF) – EM 324 2304 2640 10, 572 0Fh 0 1920x1080/24 (1:1) – EM 338 2400 2750 10 (18)1 12h 0 1920x1080/24 (PsF) – EM 338 2400 2750 10, 572 13h 0 ST 425 (3G) 4:2:2 1920x1080/60 (2:1) or 1920x1080/30 (PsF) 1920x1080/50 (2:1) or 1920x1080/25 (PsF) ST 425 (3G) 4:4:4 1920x1080/60 (2:1) or 1920x1080/30 (PsF) 1920x1080/50 (2:1) or 1920x1080/25 (PsF) ST 274 (HD) GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 72 of 125 Table 4-22: Supported Video Standards (Continued) LENGTH OF HANC LENGTH OF ACTIVE VIDEO TOTAL SAMPLES SMPTE ST 352 LINES Gennum VD_STD [4:0] RATE_ SEL1 1280x720/30 (1:1) 2008 1280 3300 10 (13)1 02h 0 1280x720/30 (1:1) – EM 408 2880 3300 10 (13)1 03h 0 1280x720/50 (1:1) 688 1280 1980 10 (13)1 04h 0 1280x720/50 (1:1) – EM 240 1728 1980 10 (13)1 05h 0 1280x720/25 (1:1) 2668 1280 3960 10 (13)1 06h 0 1280x720/25 (1:1) – EM 492 3456 3960 10 (13)1 07h 0 1280x720/24 (1:1) 2833 1280 4125 10 (13)1 08h 0 1280x720/24 (1:1) – EM 513 3600 4125 10 (13)1 09h 0 1280x720/60 (1:1) 358 1280 1650 10 (13)1 00h 0 1280x720/60 (1:1) – EM 198 1440 1650 10 (13)1 01h 0 268 1440 1716 13, 276 16h X 268 1440 1716 13, 276 17h X 525-line 487 generic − − 1716 13, 276 19h X 525-line 507 generic − − 1716 13, 276 1Bh X 280 1440 1728 9, 322 18h X 625-line generic (EM) − − 1728 9, 322 1Ah X Unknown HD RATE_SEL0 = 0 − − − − 1Dh Unknown SD RATE_SEL0 = 1 − − − − 1Eh X Unknown 3G RATE_SEL0 = 0 − − − − 1Fh 1 SMPTE STANDARD ACTIVE VIDEO AREA ST 296 (HD) 1440x487/60 (2:1) (Or dual link progressive) ST 125 (SD) 1440x507/60 (2:1) 1440x576/50 (2:1) ITU-R BT.656 (SD) (Or dual link progressive) Notes: 1. The Line Numbers in brackets refer to version zero SMPTE ST 352 packet locations, if they are different from version 1. 2. The part may provide full or limited functionality with standards that are not included in this table. Please consult a Semtech technical representative. By default (at power up or after system reset), the four RASTER_STRUC_X, STD_LOCK and INT/PROG registers are set to zero. These registers are also cleared when the SMPTE_BYPASS pin is LOW, or the LOCKED pin is LOW. Note 1: The Line Numbers in brackets refer to Version zero SMPTE ST 352 packet locations, if they are different from the Version one locations. Note 2: 3G formats cannot be fully determined from these measurements. Their detailed information will be derived from SMPTE ST 352 packets, which must be in the video stream as a mandatory requirement of the SMPTE ST 424 specification, as described below. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 73 of 125 4.9.2 3G Format Detection Format detection is more difficult for 3G signals, as there are two levels of signal (Level A and Level B) and multiple mappings within each level. Timing information is not sufficient to fully decode the video format. For this reason SMPTE ST 352 video payload identifier packets are mandatory for all SMPTE ST 424 serial signals. Note: The only exception is when the SMPTE ST 425 mapping is Level B twin SMPTE ST 292 streams, and one or both of the SMPTE ST 292 streams carries HD-SDTI data. In this case the HD-SDTI header packets are used for payload identification. 4.9.2.1 Level A and Level B Signals: The GS2972 uses SMPTE ST 352 packets to determine the video format. The SMPTE ST 352 packets used for format detection will either be: • When the 352_INS (address 000h bit 6) bit is LOW, then if either bit 6 or 7 of address 20Ah are HIGH, the format is 3G Level B. If both are LOW, then it will look at the information programmed at address 00Ah VIDEO_FORMAT_OUT_DS1_X. See SMPTE ST 425 Standard for details. • When the bit is HIGH, the format is 3G Level A. Extraction of SMPTE ST 352 packets cannot be done in 3G Level B. The GS2972 uses the programmed SMPTE ST 352 packets if the 352_INS register bit in the IOPROC register is HIGH. If there are no SMPTE ST 352 packets embedded in the input signal, and the user does not embed SMPTE ST 352 packets from the host interface, the GS2972 assumes an input signal of 1080p/50 or 1080p/59.94. The GS2972 uses information from the RASTER_STRUC_X registers to select between these two frame rates. For Level B inputs, the GS2972 does not extract the SMPTE ST 352 packets from the parallel input. The only source of SMPTE ST 352 packets in Level B mode, to be used for format detection and for embedding in the output data streams, is from the user programmed registers in the host interface. Note: If proper SMPTE video is applied and then removed from the input, the device does not flag that the H_LOCK, V_LOCK, VD_SDT etc. has changed (been lost). This is the case for either TRS detect or HVF modes. This problem occurs only when the video data is removed, but not the PCLK. Usually, when a video signal is removed, it includes the clock, the video data, as well as the H, V, F as a whole. So the scenario is not likely to occur. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 74 of 125 4.9.3 ANC Data Blanking The GS2972 can blank the video input data during the H and V blanking periods. This function will be enabled by setting the ANC_BLANK pin LOW. This function is only available when the device is operating in SMPTE mode (SMPTE_BYPASS = HIGH). In this mode, input video data in the horizontal and vertical blanking periods will be replaced by SMPTE compliant blanking values. The blanking function will operate only on the video input signal and will remove all ancillary data already embedded in the input video stream. In SD mode, SAV and EAV code words already embedded in the input video stream will be protected and will not be blanked. In HD and 3G modes, SAV and EAV code words, line numbers and line based CRC's already embedded in the input video stream will be protected and will not be blanked. The above two statements are really implementation specific, and are provided only to ensure that the “Detect TRS” function for timing generation is supported by the device, even when the blanking function is enabled. From a system perspective, use of the input blanking function is not recommended unless TRS, line number and CRC generation and insertion functions are enabled. The active image area will not be blanked. The input blanking function will not blank any of the ancillary data, TRS words, line numbers, CRC's, EDH, SMPTE ST 352 payload identifiers or audio control and data packets inserted by the device itself. 4.9.4 ANC Data Checksum Calculation and Insertion The GS2972 calculates checksums for all detected ancillary data packets and audio data presented to the device. ANC data checksum insertion only takes place if the IOPROC_EN/DIS pin is HIGH, the SMPTE_BYPASS is HIGH and the ANC_CSUM_INS bit is set LOW in the IOPROC register. Note: The device will correct any CSUM value outside the protected ranges from 000h to 003h and from 3FCh to 3FFh. If a CSUM value in either of these ranges is presented to the device, it will not be corrected. 4.9.5 TRS Generation and Insertion The GS2972 is capable of generating and inserting TRS codes. TRS word generation and insertion are performed in accordance with the timing parameters generated by the timing circuits, which is locked to the externally provided H:V:F or CEA-861 signals, or the TRS signals embedded in the input data stream. The GS2972 will overwrite the TRS signals if they're already embedded. When a 3G Level A signal is applied to the GS2972, and when the CONV_372 (bit 9 address 000h) is set LOW (Level A to Level B conversion), TRS will be inserted according to 3G Level B format. 10-bit TRS code words are inserted at all times. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 75 of 125 The insertion of TRS ID words only take place if the IOPROC_EN/DIS pin is HIGH and the SMPTE_BYPASS pin is HIGH. In addition to this, the GS2972 requires the TRS_INS bit to be set LOW in the IOPROC register. If the TIM_861 pin is HIGH, then the timing circuits are locked to CEA-861 timing. 4.9.6 HD and 3G Line Number Calculation and Insertion The GS2972 is capable of line number generation and insertion, in accordance with the relevant HD video standard, as determined by the automatic video standard detector. Line numbers are inserted into both the Y and C channels. Note: Line number generation and insertion only occurs in HD and 3G modes (RATE_SEL0 = LOW). The insertion of line numbers only take place if the IOPROC_EN/DIS pin is HIGH and SMPTE_BYPASS pin is HIGH. In addition to this, the GS2972 requires the LNUM_INS bit to be set LOW in the IOPROC register. 4.9.7 Illegal Code Re-Mapping The GS2972 detects and corrects illegal code words within the active picture area. All codes within the active picture (outside the horizontal and vertical blanking periods), between the values of 3FCh and 3FFh are re-mapped to 3FBh. All codes within the active picture area between the values of 000h and 003h are remapped to 004h. 8-bit TRS code words are re-mapped to 10-bit values. The illegal code re-mapping will only take place if the IOPROC_EN/DIS pin is HIGH and SMPTE_BYPASS is HIGH. In addition to this, the GS2972 requires the ILLEGAL_WORD_REMAP bit to be set LOW in the IOPROC register. Note: Due to the architecture of the GS2972 serializer, illegal code words appearing in the middle of a line that look like TRS sequences will be treated as such by the device. For example, any sequence in the middle of a line that produces 3FFh 000h 000h followed by another 10-bit word will be treated as a TRS, even if that following word does not match the XYZh code words allowed by SMPTE. To avoid this issue, any groupings of words that look like TRS sequence must be kept out of the active picture portion of the video line or it will not be remapped. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 76 of 125 4.9.8 SMPTE ST 352 Payload Identifier Packet Insertion When enabled by the SMPTE_352M_INS bit in the IOPROC register, new SMPTE ST 352 payload identifier packets are inserted into the data stream. These packets are supplied by the user via the host interface. Setting the SMPTE_352M_INS bit LOW enables this insertion. The device will automatically calculate the checksum and generate Version One compliant ST 352 ancillary data preambles: DID, SDID, DBN, DC. The SMPTE ST 352 packet is inserted into the data stream according to the line number and sample position rules defined in the 2002 standard. For HDTV video systems the SMPTE ST 352 packet is placed in the Y channel only. By default (at power up or after system reset), the four VIDEO_FORMAT_IN_DS1 registers and the four VIDEO_FORMAT_OUT_DS1 registers are set to zero. 4.9.8.1 3G SMPTE ST 352 Payload Identifier Packet Insertion When enabled by the SMPTE_352M_INS bit in the IOPROC register (000h), new SMPTE ST 352 payload identifier packets are inserted into the data streams. Setting this bit LOW enables insertion. Insertion of SMPTE ST 352 packets into each data stream is controlled by the status format describing bit, SDTI_TDM_DS1 and SDTI_TDM_DS2 for Data Stream One and Data Stream Two. If SDTI_TDM_DS1 (default LOW) is set HIGH by the user, the GS2972 does not insert SMPTE ST 352 packets into Data Stream One. Similarly, SMPTE ST 352 packets are inserted in Data Stream Two only if SDTI_TDM_DS2 is set LOW. This allows the user to individually disable SMPTE ST 352 packets where the data stream is carrying an HD-SDTI or TDM signal, which must not have SMPTE ST 352 packets embedded. Note: The user must ensure that there is sufficient space in the horizontal blanking interval for the insertion of the SMPTE ST 352 packets. If the FIRST_AVAIL_POSITION bit in the host interface registers is set HIGH (by default), the SMPTE ST 352 packets are inserted in the first available position following any existing ancillary data. If the FIRST_AVAIL_POSITION CSR bit is set LOW, then the packets are inserted immediately after the EAV/CRC1. If the first available position is HIGH and there is insufficient space, ST 352 packets will not be inserted. If there are pre-existing ST 352 packets, they will be overwritten, independent of the setting of the FIRST_AVAIL_POSITION CSR bit. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 77 of 125 4.9.9 Line Based CRC Generation and Insertion (HD/3G) When operating in HD mode (RATE_SEL0 pin = LOW, RATE_SEL1 pin = LOW), the GS2972 generates and inserts line based CRC words into both the Y and C channels of the data stream. When operating in 3G (RATE_SEL0 pin = LOW, RATE_SEL1 pin = HIGH) Level A mode, the GS2972 generates and inserts line based CRC words into both Data Stream One and Data Stream Two. When operating in 3G (RATE_SEL0 pin = LOW, RATE_SEL1 pin = HIGH) Level B mode, the GS2972 generates and inserts line based CRC words into both Y and C channels of both Link A and Link B. The line based CRC insertion only takes place if the IOPROC_EN/DIS pin is HIGH and SMPTE_BYPASS is HIGH. In addition to this, the GS2972 requires the EDH_CRC_INS bit to be set LOW in the IOPROC register. 4.9.10 EDH Generation and Insertion When operating in SD mode, the GS2972 generates and inserts EDH packets into the data stream. The EDH packet generation and insertion only takes place if the IOPROC_EN/DIS pin is HIGH, SMPTE_BYPASS pin is HIGH, the RATE_SEL0 pin is HIGH and the EDH_CRC_INS bit is set LOW in the IOPROC register. Calculation of both Full Field (FF) and Active Picture (AP) CRCs is carried out by the device. EDH error flags EDH, EDA, IDH, IDA and UES for ancillary data, full field and active picture are also inserted. • When the EDH_CRC_UPDATE bit of the host interface is set LOW, these flags are sourced from the ANC_EDH_FLAG, FF_EDH_FLAG and AP_EDH_FLAG registers of the device, where they are programmed by the application layer • When the EDH_CRC_UPDATE bit of the host interface is set HIGH, incoming EDH flags are preserved and inserted in the outgoing EDH packets. In this mode the ANC_EDH_FLAG, FF_EDH_FLAG and AP_EDH_FLAG registers contain the incoming EDH flags, and will be read only The GS2972 generates all of the required EDH packet data including all ancillary data preambles: DID, DBN, DC, reserved code words and checksum. The prepared EDH packet is inserted at the appropriate line of the video stream (in accordance with RP165). The start pixel position of the inserted packet is based on the SAV position of that line, such that the last byte of the EDH packet (the checksum) is placed in the sample immediately preceding the start of the SAV TRS word. Note 1: When the EDH_CRC_UPDATE bit of the host interface is set LOW, it is the responsibility of the application interface to ensure that the EDH flag registers are updated regularly (once per field). Note 2: It is also the responsibility of the application interface to ensure that there is sufficient space in the horizontal blanking interval for the EDH packet to be inserted. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 78 of 125 4.9.11 GS2972 3G/HD HANC Space Considerations when Embedding Audio Standards having more than 1024 HANC words in the blanking can potentially re-transmit pre-embedded packets twice in CASCADE or AGR modes. Here is the list of standards at risk: (1920x1080/24/1:1, 444) = 1648 words in HANC (2048x1080/25/1:1, 444) = 1172 words in HANC (2048x1080/24/1:1, 444) = 1392 words in HANC (1280x720/24/1:1, 444) = 5678 words in HANC (1280x720/23.98/1:1, 444) = 5678 words in HANC (1280x720/25/1:1, 444) = 5348 words in HANC (1280x720/50/1:1, 444) = 1388 words in HANC (1920x1080/23.98/1:1, 444) = 1648 words in HANC (1920x1080/50/2:1, 444) = 1428 words in HANC (1920x1080/25/1:1, 444) = 1428 words in HANC (1920x1080/25/PsF, 444) = 1428 words in HANC (1280x720/30/1:1, 422) = 2008 words in HANC (1280x720/29.97/1:1, 422) = 2008 words in HANC (1280x720/25/1:1, 422) = 2668 words in HANC (1280x720/24/1:1, 422) = 2833 words in HANC (1280x720/23.98/1:1, 422) = 2833 words in HANC Note: For all of the standards listed above, Semtech recommends using the GS2972 as the source of any ancillary data packets. If packets already exist in the video coming in to the GS2972, Semtech recommends deleting all ANC packets if this problem is to be avoided. 4.9.12 SMPTE ST 372 Conversion When the IOPROC_EN/DIS pin is HIGH and the CONV_372 bit in the IOPROC register is LOW, the GS2972 converts SMPTE ST 425 Level A mapping 1 (1080P 4:2:2) to Level B SMPTE ST 372 dual link prior to serialization. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 79 of 125 4.9.13 Processing Feature Disable The GS2972 contains an IOPROC register. This register contains one bit for each processing feature, allowing the user to enable/disable each process individually. By default (at power up or after system reset), all of the IOPROC register bits are LOW, except for the SMPTE ST 372 conversion. To disable an individual processing feature, the application interface must set the corresponding bit HIGH in the IOPROC register. To enable these features, the IOPROC_EN/DIS pin must be HIGH, and the individual feature must be enabled by setting bits LOW in the IOPROC register of the host interface. The I/O processing functions supported by the GS2972 are shown in Table 4-25 below. Table 4-23: IOPROC Register Bits I/O Processing Feature IOPROC Register Bit TRS insertion TRS_INS (000h Bit 0) Y and C line number insertion LNUM_INS (000h Bit 1) Y and C line based CRC insertion CRC_INS (000h Bit 2) Ancillary data checksum correction ANC_CSUM_INS (000h Bit 3) EDH CRC error calculation and insertion EDH_ CRC_INS (000h Bit 4) Illegal word re-mapping ILLEGAL_WORD_REMAP (000h Bit 5) SMPTE ST 352 packet insertion SMPTE_352M_INS (000h Bit 6) SMPTE ST 372 conversion CONV_372 (000h Bit 9) Audio embedding AUDIO_EMBED (000h Bit 10) GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 80 of 125 4.10 SMPTE ST 352 Data Extraction If there are no SMPTE ST 352 packets embedded in the input signal, the GS2972 will raise an error flag in the “NO_352_ERR” bit. If there are ST 352 packets present in the stream, the GS2972 reports the extracted SMPTE ST 352 packets in the VIDEO_FORMAT_352_IN registers in the host interface. The user can use this information, along with the RASTER_STRUC_X registers, to determine the video format. If there is a conflict between the numbers in the RASTER_STRUC_X registers and the format defined in the SMPTE ST 352 packets, the GS2972 will raise a TIMING_ERR flag via the host interface. Note: SMPTE ST 352 packets will not be present in an HD-SDTI input stream, and will not be embedded in an output HD-SDTI serial stream. This is controlled by the user as described in Section 4.9.8.1. By default (at power up or after system reset), the VIDEO_FORMAT_352_IN registers are set to zero (undefined video format). These registers are also cleared when the SMPTE_BYPASS pin is set LOW, or the LOCKED pin is LOW. The SMPTE ST 352 packet should be received once per field for interlaced systems and once per frame for progressive video systems. If the packet is not received for two complete video frames, the VIDEO_FORMAT_352_IN registers are cleared to zero. Table 4-24: SMPTE ST 352 Packet Data Register Name Bit Bit Name 15-8 VIDEO_FORMAT_IN_ DS1_4 (Byte 4) 7-0 Description R/W Default Data will be available in this register when Video Payload Identification Packets are detected in the data stream. R 0 VIDEO_FORMAT_IN_ DS1_3 (Byte 3) Data will be available in this register when Video Payload Identification Packets are detected in the data stream. R 0 15-8 VIDEO_FORMAT_IN_ DS1_2 (Byte 2) Data will be available in this register when Video Payload Identification Packets are detected in the data stream. R 0 7-0 VIDEO_FORMAT_IN_ DS1_1 (Byte 1) Data will be available in this register when Video Payload Identification Packets are detected in the data stream. R 0 15-8 VIDEO_FORMAT_IN_ DS2_4 (Byte 4) Data will be available in this register when Video Payload Identification Packets are detected in the data stream. R 0 7-0 VIDEO_FORMAT_IN_ DS2_3 (Byte 3) Data will be available in this register when Video Payload Identification Packets are detected in the data stream. R 0 15-8 VIDEO_FORMAT_IN_ DS2_2 (Byte 2) Data will be available in this register when Video Payload Identification Packets are detected in the data stream. R 0 7-0 VIDEO_FORMAT_IN_ DS2_1 (Byte 1) Data will be available in this register when Video Payload Identification Packets are detected in the data stream. R 0 VIDEO_FORMAT_352_IN_WORD_2 VIDEO_FORMAT_352_IN_WORD_1 VIDEO_FORMAT_352_IN_WORD_4 VIDEO_FORMAT_352_IN_WORD_3 GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 81 of 125 4.11 Serial Clock PLL An internal VCO provides the transmission clock rates for the GS2972. The power supply to the VCO is provided to the VCO_VDD/VCO_GND pins of the device. This VCO is locked to the input PCLK via an on-chip PLL and Charge Pump. Internal division ratios for the PCLK are determined by the setting of the RATE_SEL0 pin, the RATE_SEL1 pin and the 20BIT/10BIT pin as shown in Table 4-25: Table 4-25: PCLK and Serial Digital Clock Rates External Pin Setting Supplied PCLK Rate Serial Digital Output Rate RATE_SEL0 RATE_SEL1 20BIT/10BIT LOW HIGH HIGH 148.5 or 148.5/1.001MHz 2.97 or 2.97/1.001 Gb/s LOW HIGH LOW 148.5 or 148.5/1.001MHz (DDR) 2.97 or 2.97/1.001 Gb/s LOW LOW HIGH 74.25 or 74.25/1.001MHz 1.485 or 1.485/1.001Gb/s LOW LOW LOW 148.5 or 148.5/1.001MHz 1.485 or 1.485/1.001Gb/s HIGH X HIGH 13.5MHz 270Mb/s HIGH LOW LOW 27MHz 270Mb/s As well as generating the serial digital output clock signals, the PLL is also responsible for generating all internal clock signals required by the device. 4.11.1 PLL Bandwidth Table 4-26 shows the GS2972 PLL loop bandwidth variations. PLL bandwidth is a function of the external loop filter resistor and the charge pump current. We recommend using a 200Ω loop filter resistor, however, this value can be varied from 100Ω to 380Ω, depending on application. Values other than 200Ω are not guaranteed. As the resistor is changed, the bandwidth will scale proportionately (for example, a change from a 200Ω to 300Ω resistor will cause a 50% increase in bandwidth). The charge pump current is preset to 100μA and should not be changed. The external loop filter capacitor does not affect the PLL loop bandwidth. The external loop filter capacitor affects PLL loop settling time, phase margin and noise. It is selectable from 1μF to 33μF. However, it should be kept at 10μF for optimal performance. A smaller capacitor results in shorter lock time but less stability. A larger capacitor results in longer lock time but more stability. Narrower loop bandwidths require a larger capacitor to be stable. In other words, a small loop filter resistor requires a larger loop capacitor. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 82 of 125 Table 4-26: GS2972 PLL Bandwidth Mode PCLK Frequency (MHz) Filter Resistor (Ω) Charge Pump Current (μA) Bandwidth (kHz) SD 13.50 200 100 4.78 SD 27.00 200 100 9.57 HD 74.25 200 100 26.32 HD 148.50 200 100 52.63 3G 148.50 200 100 52.63 4.11.2 Lock Detect The Lock Detect block controls the serial digital output signal and indicates to the application layer the lock status of the device. The LOCKED output pin is provided to indicate the device operating status. The LOCKED output signal is set HIGH by the lock detect block under the following conditions (see Table 4-27): Table 4-27: GS2972 Lock Detect Indication RESET PLL Lock SMPTE_BYPASS DVB_ASI RATE_SEL0 HIGH HIGH HIGH LOW X HIGH HIGH LOW HIGH HIGH HIGH HIGH LOW LOW X Any other combination of signal states not included in the above table results in the LOCKED pin being LOW. Note: When the LOCKED pin is LOW, the serial digital output is in the muted state. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 83 of 125 4.12 Serial Digital Output The GS2972 has a single, low-impedance current mode differential output driver, capable of driving at least 800mV into a 75Ω single-ended load. The output signal amplitude, or swing, will be user-configurable using an external resistor on the RSET pin. The serial digital output data rate supports SMPTE ST 424, SMPTE ST 292, SMPTE ST 259-C and DVB-ASI operation. This is summarized in Table 4-28: Table 4-28: Serial Digital Output - Serial Output Data Rate Parameter Symbol Serial Output Data Rate Conditions Min Typ Max Units SMPTE ST 424 signal − 2.97, 2.97/1.001 − Gb/s SMPTE ST 292 signal − 1.485, 1.485/1.001 − Gb/s SMPTE ST 259-C signal − 270 − Mb/s DVB-ASI signal − 270 − Mb/s BRSDO The SDO and SDO pins of the device provide the serial digital output. Compliance with all requirements defined in Section 4.12.1 through Section 4.12.4 is guaranteed when measured across a 75Ω terminated load at the output of 1m of Belden 1694A cable, including the effects of the Semtech recommended ORL matching network, BNC and coaxial cable connection, except where otherwise stated. Figure 4-28 illustrates this requirement, which is in accordance with the measurement methodology defined in SMPTE ST 424, SMPTE ST 292 and SMPTE ST 259-C. Measuring Device DUT GS2972 ORL Matching Network 1m Belden 1694A 75Ω Coaxial Cable BNC BNC 75Ω Resistive Load Figure 4-28: ORL Matching Network, BNC and Coaxial Cable Connection GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 84 of 125 4.12.1 Output Signal Interface Levels The Serial Digital Output signals (SDO and SDO pins), of the device meet the amplitude requirements as defined in SMPTE ST 424 for an unbalanced generator (single-ended). The signal amplitude is controlled to better than +/-7% of the nominal level defined in SMPTE ST 424, when an external 750Ω 1% resistor is connected between the RSET pin of the device and VCC. The output signal amplitude can be reduced to less than 1/10th of the nominal amplitude, defined above, by increasing the value of the resistor connected between the RSET pin of the device and VCC. These requirements are met across all ambient temperature and power supply operating conditions described in Section 2. The output amplitude of the GS2972 can be adjusted by changing the value of the RSET resistor as shown in Table 4-29. For a 800mVpp output a value of 750Ω is required. A ±1% SMT resistor should be used. The RSET resistor is part of the high speed output circuit of the GS2972. The resistor should be placed as close as possible to the RSET pin. In addition, an anti-pad should be used underneath the resistor. Table 4-29: RSET Resistor Value vs. Output Swing RSET Resistor Values (Ω) Output Swing (mVpp) 995 608 824 734 750 800 680 884 4.12.2 Overshoot/Undershoot The serial digital output signal overshoot and undershoot is controlled to be less that 7% of the output signal amplitude, when operating as an unbalanced generator (single-ended). This requirement is met for nominal signal amplitudes as defined by SMPTE ST 292. This requirement is met regardless of the output slew rate setting of the device. This requirement is met across all ambient temperature and power supply operating conditions described in Section 2. This requirement is summarized in Table 4-30: Table 4-30: Serial Digital Output - Overshoot/Undershoot Parameter Symbol Conditions Min Typ Max Units − − − 0 7 % Serial output overshoot /undershoot GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 85 of 125 4.12.3 Slew Rate Selection The GS2972 supports two user-selectable output slew rates. Control of the slew rate is determined by the setting of the RATE_SEL0 input pin. When this pin is set HIGH, the output slew rate matches the requirements as defined by the SMPTE ST 259-C standard. When this pin is set LOW, the output slew rate is better than the requirements as defined by the SMPTE ST 424 standard. These requirements is met across all ambient temperature and power supply operating conditions described in Section 2. This requirement is summarized in Table 4-31: Table 4-31: Serial Digital Output - Rise/Fall Time Parameter Serial Output Rise/Fall Time 20% ~ 80% Symbol SDOTR Conditions Min Typ Max Units SMPTE ST 292/ST 424 signal − − 135 ps SMPTE ST 259-C signal 400 − 800 ps 4.12.4 Serial Digital Output Mute When the SDO_EN/DIS pin is LOW, the serial digital output signals of the device become high-impedance, reducing system power. The serial digital output is also placed in the high-impedance state when the LOCKED pin is LOW, or when the STANDBY pin is HIGH. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 86 of 125 4.13 GSPI Host Interface Note: When using more than one Semtech serializer or deserializer (SerDes) in the same design, carefully read this section to see how the GSPI ports of multiple ICs should be connected to each other. Unlike some previous devices, the SDOUT pin of these SerDes ICs is a non-clocked, loop-through of SDIN (allowing for multiple devices to be connected to the GSPI chain). The SDOUT pins of multiple SerDes ICs should not be bussed together, as was the case with some older generations of SerDes ICs. The GSPI, or Gennum Serial Peripheral Interface, is a 4-wire interface provided to allow the application layer to access additional status information through configuration registers in the GS2972. The GSPI comprises a Serial Data Input signal (SDIN), Serial Data Output signal (SDOUT), an active-low Chip Select (CS) and a Burst Clock (SCLK). Because these pins can be shared with the JTAG interface port for compatibility with the GS1582, an additional control signal pin JTAG/HOST is provided. When JTAG/HOST is LOW, the GSPI interface is enabled. When JTAG/HOST is HIGH, the JTAG interface is enabled. When operating in GSPI mode, the SCLK, SDIN, and CS signals are provided by the application interface. The SDOUT pin is a non-clocked loop-through of SDIN, and may be connected to the SDIN of another device, allowing multiple devices to be connected to the GSPI chain. The interface is illustrated in Figure 4-29 below. Application Host GS2972 SCLK CS1 SDOUT SCLK CS SDIN SDOUT GS2972 SCLK CS2 CS SDIN SDIN SDOUT Figure 4-29: GSPI Application Interface Connection All read or write access to the GS2972 is initiated and terminated by the application host processor. Each access always begins with a Command/Address Word followed by a data read to or written from the GS2972. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 87 of 125 4.13.1 Command Word Description The Command Word consists of a 16-bit word transmitted MSB first and contains a read/write bit, an Auto-Increment bit and a 12-bit address. Figure 4-30 shows the command word format and bit configurations. Command Words are clocked into the GS2972 on the rising edge of the Serial Clock SCLK, which operates in a burst fashion. When the Auto-Increment bit is set LOW, each Command Word must be followed by only one Data Word to ensure proper operation. If the Auto-Increment bit is set HIGH, the following Data Word will be written into the address specified in the Command Word, and subsequent data words will be written into incremental addresses from the previous Data Word. This facilitates multiple address writes without sending a Command Word for each Data Word. MSB R/W LSB RSV RSV AutoInc A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Figure 4-30: Command Word Format 4.13.2 Data Read or Write Access Serial data is transmitted or received MSB first synchronous with the rising edge of the Serial Clock, SCLK. The Chip Select (CS) signal must be active LOW a minimum of 1.5ns (t0 in Figure 4-32) before the first clock edge to ensure proper operation. During a Read sequence (Command Word R/W bit set HIGH), a wait state of 148ns (4 x 1/fPCLK, t5 in Figure 4-32) is required between writing the Command Word and reading the following Data Word. The read bits are clocked out on the negative edges of SCLK. Note 1: Where several devices are connected to the GSPI chain, only one CS_TMS may be asserted during a read sequence. During a Write sequence (Command Word R/W bit set LOW), a wait state of 37ns (1 x 1/fPCLK, t4 in Figure 4-32) is required between the Command Word and the following Data Word. This wait state must also be maintained between successive Command Word/Data Word write sequences. When Auto-increment mode is selected (AutoInc = 1), the wait state must be maintained between successive Data Words after the initial Command Word/Data Word sequence. During the write sequence, all command and following Data Words input at the SDIN pin are output at the SDOUT pin as is. When several devices are connected to the GSPI chain, data can be written simultaneously to all the devices which have CS set LOW. Note 2: If the application interface performs a Read or Write access after power-up, prior to the application of a valid serial video input signal, the SCLK frequency must not exceed 10MHz. MSB D15 LSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 4-31: Data Word Format GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 88 of 125 4.13.3 GSPI Timing Write and Read Mode timing for the GSPI interface is as shown in the following diagrams: t t 0 1 t t 4 7 SCLK_TCK t t 3 t 2 8 CS_TMS SDIN_TDI R/W RSV RSV Auto _Inc A11 A10 SDOUT_TDO R/W RSV RSV Auto _Inc A11 A10 A9 A9 A8 A7 A8 A7 A6 A5 A6 A4 A3 A2 A1 A3 A2 A1 A4 A5 A0 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D5 D4 D3 D2 D1 D0 D4 D3 D2 D1 D0 Figure 4-32: Write Mode t 5 SCLK_TCK t CS_TMS SDIN_TDI R/W RSV RSV Auto _Inc A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 SDOUT_TDO R/W RSV RSV Auto _Inc A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 6 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 4-33: Read Mode SDIN_TDI to SDOUT_TDO combinational path for daisy chain connection of multiple GS2972 devices. TDELAY SDIN_TDI data_0 SDOUT_TDO data_0 Figure 4-34: GSPI Time Delay Table 4-32: GSPI Time Delay Parameter Symbol Conditions Min Typ Max Units Delay time tDELAY 50% levels; +1.8V operation − − 10.5 ns Delay time tDELAY 50% levels; +3.3V operation − − 8.7 ns GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 89 of 125 Table 4-33: GSPI AC Characteristics Parameter Symbol Conditions Min Typ Max Units CS low before SCLK rising edge t0 1.5 − − ns SCLK period t1 12.5 − − ns SCLK duty cycle t2 40 50 60 % Input data setup time t3 1.5 − − ns − − − − ns − − ns − − ns − − ns Time between end of Command Word (or data in Auto-Increment mode) and the first SCLK of the following Data Word – write cycle. Time between end of Command Word (or data in Auto-Increment mode) and the first SCLK of the following Data Word – read cycle. Output hold time (15pF load) CS HIGH after last SCLK rising edge Input data hold time PCLK (MHz) ns unlocked 445 13.5 74.2 27.0 37.1 74.25 13.5 148.5 6.7 PCLK (MHz) ns unlocked 1187 13.5 297 27.0 148.5 74.25 53.9 148.5 27 t4 50% levels; +3.3V or +1.8V operation t5 t6 1.5 PCLK (MHz) ns unlocked 445 74.2 74.2 37.10 37.1 74.25 13.5 148.5 6.7 t7 t8 1.5 ns Note: If the application interface performs a Read or Write access after power-up, prior to the application of a valid serial video input signal, the SCLK frequency must not exceed 10MHz. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 90 of 125 4.14 Host Interface Register Maps 4.14.1 Video Core Registers Table 4-34: Video Core Configuration and Status Registers Address Register Name Bit Name Bit Description R/W Default RSVD 15 Reserved. R 0 DELAY_LINE_ENABLE 14 HIGH - enables the delay line. LOW - disables the delay line. R/W 0 13 HIGH - embeds audio on the DS2 of a 3G Level B signal. LOW - embeds audio on the DS1 of a 3G Level B signal. R/W 0 12 HIGH - preserve incoming EDH flags and insert into outgoing EDH packets. LOW - embed flags from 003 in EDH packet. R/W 0 ANC_INS 11 HIGH - disable ancillary data insertion. LOW - embeds ANC packet stored at 040h to 13Fh according to parameters at 005h to 02Dh. R/W 0 AUDIO_EMBED 10 HIGH - disable audio embedding. LOW - enables audio embedding. R/W 0 9 HIGH - disable Level A-B conversion. LOW - enable Level A-B conversion. R/W 1 R/W 0 AUDIO_LEVELB_STREAM_2_1B EDH_CRC_UPDATE 000h IOPROC CONV_372 Chooses H configuration; H_CONFIG 8 LOW - Active-line based blanking is enabled. HIGH - SMPTE H timing. RSVD 7 Reserved. R/W 0 SMPTE_352M_INS 6 HIGH - disables insertion of SMPTE ST 352 packets. LOW - enables insertion of SMPTE ST 352 packets R/W 0 ILLEGAL_WORD_REMAP 5 HIGH - disables illegal word remapping. R/W 0 EDH_CRC_INS 4 HIGH - disables EDH CRC error correction and insertion. R/W 0 ANC_CSUM_INS 3 HIGH - disables insertion of ancillary data checksums. R/W 0 CRC_INS 2 HIGH - disables insertion of HD/3G CRC words. R/W 0 GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 91 of 125 Table 4-34: Video Core Configuration and Status Registers (Continued) Address 000h Register Name Bit Name Bit Description R/W Default LNUM_INS 1 HIGH = disables insertion of HD/3G line numbers. R/W 0 TRS_INS 0 HIGH = disables insertion of TRS words. R/W 0 R 0 R 0 R 0 R 0 IOPROC RSVD 15-7 Reserved. TRS protection error. 001h TRS_PERR 6 Y1_EDH_CS_ERR 5 LOW - No errors in TRS. HIGH - Errors in TRS. Same as CS_ERR but only updates its state when packet being inspected is an EDH packet. HIGH indicates that a checksum error is detected. It is updated every time a CS word is present on the output. Y1_CS_ERR 4 FORMAT_ERR 3 HIGH indicates standard is not recognized for 861D conversion. R 0 TIMING_ERR 2 HIGH indicates that the RASTER measurements do not line up with the extracted ST 352 packet information. R 0 NO_352M_ERR 1 HIGH indicates no ST 352 packet embedded in incoming video. R 0 LOCK_ERR 0 HIGH indicates PLL lock error indication. R 0 ERROR_STAT GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 Note: This bit will not be set for CSUM values in the protected ranges (from 000h to 003h and from 3FCh to 3FFh). www.semtech.com 92 of 125 Table 4-34: Video Core Configuration and Status Registers (Continued) Address 002h Register Name Bit Name Bit Description R/W Default RSVD 15 Reserved. R 0 ANC_UES_EXT 14 Ancillary data - unknown error status flag. R 0 ANC_IDA_EXT 13 Ancillary data - internal error detected already flag. R 0 ANC_IDH_EXT 12 Ancillary data - internal error detected here flag. R 0 ANC_EDA_EXT 11 Ancillary data - error detected already flag. R 0 ANC_EDH_EXT 10 Ancillary data - error detected here flag. R 0 FF_UES_EXT 9 EDH Full Field - unknown error status flag. R 0 FF_IDA_EXT 8 EDH Full Field - internal error detected already flag. R 0 FF_IDH_EXT 7 EDH Full Field - internal error detected here flag. R 0 FF_EDA_EXT 6 EDH Full Field - error detected already flag. R 0 FF_EDH_EXT 5 EDH Full Field - error detected here flag. R 0 AP_UES_EXT 4 EDH Active Picture - unknown error status flag. R 0 AP_IDA_EXT 3 EDH Active Picture - internal error detected already flag. R 0 AP_IDH_EXT 2 EDH Active Picture - internal error detected here flag. R 0 AP_EDA_EXT 1 EDH Active Picture - error detected already flag. R 0 AP_EDH_EXT 0 EDH Active Picture - error detected here flag. R 0 EDH_FLAG_EXT GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 93 of 125 Table 4-34: Video Core Configuration and Status Registers (Continued) Address 003h Register Name Bit Name Bit Description R/W Default RSVD 15 Reserved. R 0 ANC_UES_PGM 14 Ancillary data - unknown error status flag. R 0 ANC_IDA_PGM 13 Ancillary data - internal error detected already flag. R/W 0 ANC_IDH_PGM 12 Ancillary data - internal error detected here flag. R/W 0 ANC_EDA_PGM 11 Ancillary data - error detected already flag. R/W 0 ANC_EDH_PGM 10 Ancillary data - error detected here flag. R/W 0 FF_UES_PGM 9 EDH Full Field - unknown error status flag. R/W 0 FF_IDA_PGM 8 EDH Full Field - internal error detected already flag. R/W 0 FF_IDH_PGM 7 EDH Full Field - internal error detected here flag. R/W 0 FF_EDA_PGM 6 EDH Full Field - error detected already flag. R/W 0 FF_EDH_PGM 5 EDH Full Field - error detected here flag. R/W 0 AP_UES_PGM 4 EDH Active Picture - unknown error status flag. R/W 0 AP_IDA_PGM 3 EDH Active Picture - internal error detected already flag. R/W 0 AP_IDH_PGM 2 EDH Active Picture - internal error detected here flag. R/W 0 AP_EDA_PGM 1 EDH Active Picture - error detected already flag. R/W 0 AP_EDH_PGM 0 EDH Active Picture - error detected here flag. R/W 0 Reserved. R 0 9-5 Detected video standard. R 0 INT/PROGB 4 HIGH = interlaced signal LOW = progressive signal R 0 CONV_372_LOCKED 3 Convert 372 lock indication. Active HIGH. R 0 STD_LOCK 2 Standard lock indication. Active HIGH. R 0 V_LOCK 1 Vertical lock indication. Active HIGH. R 0 H_LOCK 0 Horizontal lock indication. Active HIGH. R 0 EDH_FLAG_PGM RSVD VD_STD 004h 15-10 DATA_FORMAT GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 94 of 125 Table 4-34: Video Core Configuration and Status Registers (Continued) Address Register Name 005h RSVD 006h 007h VSD_FORCE EDH_STATUS Bit Name Bit Description RSVD 15-0 RSVD 15-6 VSD_FORCE 5 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh FIRST_AVAIL_ POSITION RESERVED Default Reserved. R 0 Reserved. R 0 Use the CSR register STD value rather than the flywheels STD value. Active HIGH. R/W 0 R/W 0 VID_STD_FORCE 4-0 Force VID STD CSR. RSVD 15-2 Reserved. R 0 FF_CRC_V 1 Full Field extracted V bit. R 0 AP_CRC_V 0 Active Picture extracted V bit. R 0 Reserved. R 0 R/W 1 R 0 RSVD 008h R/W 15-1 FIRST_AVAIL_POSITION 0 HIGH - ST 352 insertion occurs on first available ANC space. LOW - insert ST 352 packets right after EAV/CRC1. RESERVED_7 15-0 Reserved. VIDEO_FORMAT_OUT_DS1_2 15-8 SMPTE ST 352 DS1 embedded packet - byte 2. R/W 0 VIDEO_FORMAT_OUT_DS1_1 7-0 SMPTE ST 352 DS1 embedded packet - byte 1. R/W 0 VIDEO_FORMAT_OUT_DS1_4 15-8 SMPTE ST 352 DS1 embedded packet - byte 4. R/W 0 VIDEO_FORMAT_OUT_DS1_3 7-0 SMPTE ST 352 DS1 embedded packet - byte 3. R/W 0 VIDEO_FORMAT_OUT_DS2_2 15-8 SMPTE ST 352 DS2 embedded packet - byte 2. R/W 0 VIDEO_FORMAT_OUT_DS2_1 7-0 SMPTE ST 352 DS2 embedded packet - byte 1. R/W 0 VIDEO_FORMAT_OUT_DS2_4 15-8 SMPTE ST 352 DS2 embedded packet - byte 4. R/W 0 VIDEO_FORMAT_OUT_DS2_3 7-0 SMPTE ST 352 DS2 embedded packet - byte 3. R/W 0 VIDEO_FORMAT_IN_DS1_2 15-8 SMPTE ST 352 DS1 extracted packet - byte 2. R 0 VIDEO_FORMAT_IN_DS1_1 7-0 SMPTE ST 352 DS1 extracted packet - byte 1. R 0 VIDEO_FORMAT_IN_DS1_4 15-8 SMPTE ST 352 DS1 extracted packet - byte 4. R 0 VIDEO_FORMAT_IN_DS1_3 7-0 SMPTE ST 352 DS1 extracted packet - byte 3. R 0 VIDEO_FORMAT_3 52_OUT_WORD_1 VIDEO_FORMAT_3 52_OUT_WORD_2 VIDEO_FORMAT_3 52_OUT_WORD_3 VIDEO_FORMAT_3 52_OUT_WORD_4 VIDEO_FORMAT_3 52_IN_WORD_1 VIDEO_FORMAT_3 52_IN_WORD_2 GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 95 of 125 Table 4-34: Video Core Configuration and Status Registers (Continued) Address Register Name 010h VIDEO_FORMAT_3 52_IN_WORD_3 011h 012h 013h 014h 015h 016h to 023h Bit Name Bit Description R/W Default VIDEO_FORMAT_IN_DS2_2 15-8 SMPTE ST 352 DS2 extracted packet - byte 2. R 0 VIDEO_FORMAT_IN_DS2_1 7-0 SMPTE ST 352 DS2 extracted packet - byte 1. R 0 VIDEO_FORMAT_IN_DS2_4 15-8 SMPTE ST 352 DS2 extracted packet - byte 4. R 0 VIDEO_FORMAT_IN_DS2_3 7-0 SMPTE ST 352 DS2 extracted packet - byte 3. R 0 VIDEO_FORMAT_3 52_IN_WORD_4 RSVD 15-11 Reserved. R 0 LINES_PER_FRAME 10-0 Total lines per frame. R 0 RSVD 15-14 Reserved. R 0 WORDS_PER_LINE 13-0 Total words per line. R 0 RSVD 15-13 Reserved. R 0 ACTIVE_WORDS_PER_LINE 12-0 Words per active line. R 0 RSVD 15-11 Reserved. R 0 ACTIVE_LINES_PER_FIELD 10-0 Active lines per frame. R 0 RSVD 15-0 Reserved. R 0 RSVD 15-2 Reserved. R 0 R 0 HIGH - one of the addresses from 040h to 13Fh was read and written to at the same time. R 0 Reserved. R 0 R/W 0 R/W 0 RASTER_STRUC_1 RASTER_STRUC_2 RASTER_STRUC_3 RASTER_STRUC_4 RSVD PACKET_MISSED 024h 1 FIRST_LINE _NUMBER_ STATUS ANC data packet could not be inserted in its entirety. HIGH - ANC packet cannot be inserted in it’s entirety. Same RAM address was read and written to at the same time. RW_CONFLICT RSVD 0 15-12 ANC data insertion mode. 025h FIRST_LINE_ NUMBER ANC_INS_MODE FIRST_LINE_NUMBER GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 11 10-0 HIGH - Concatenate LOW - Separate First line number to insert ANC packet on. www.semtech.com 96 of 125 Table 4-34: Video Core Configuration and Status Registers (Continued) Address 026h Register Name FIRST_LINE_ NUMBER_OF_ WORDS Bit Name Bit Description R/W Default FIRST_LINE_NUMBER_ANC_ TYPE 15 ANC region to insert packet in HIGH - VANC, LOW - HANC. R/W 0 FIRST_LINE_NUMBER_ STREAM_TYPE 14 R/W 0 R 0 R/W 0 R 0 Stream to insert packet in RSVD 13-10 FIRST_LINE_NUMBER_OF_ WORDS 027h 028h SECOND_LINE_ NUMBER SECOND_LINE_ NUMBER_OF_ WORDS 02Ah THIRD_LINE_ NUMBER_OF_ WORDS Reserved. SECOND_LINE_NUMBER 10-0 Second line number to insert ANC packet on in Separate Line mode. R/W 0 SECOND_LINE_NUMBER_ ANC_TYPE 15 ANC region to insert packet in. HIGH - VANC, LOW - HANC. R/W 0 SECOND_LINE_NUMBER_ STREAM_TYPE 14 R/W 0 R 0 R/W 0 R 0 9-0 HIGH - C stream, LOW - Y stream. Reserved. Total number of words in ANC packet to be inserted in second line. RSVD 15-11 Reserved. THIRD_LINE_NUMBER 10-0 Third line number to insert ANC packet on in Separate Line mode. R/W 0 ANC region to insert packet in. HIGH - VANC, LOW - HANC. R/W 0 R/W 0 R 0 R/W 0 R 0 R/W 0 THIRD_LINE_NUMBER_ANC_ TYPE 15 THIRD_LINE_NUMBER_ STREAM_TYPE 14 Stream to insert packet in. 13-10 THIRD_LINE_NUMBER_OF_ WORDS FOURTH_LINE_ NUMBER Stream to insert packet in. 13-10 RSVD 02Bh Total number of words in ANC packet to be inserted in first line. 15-11 SECOND_LINE_NUMBER_ OF_WORDS 029h Reserved. RSVD RSVD THIRD_LINE_ NUMBER 9-0 HIGH - C stream, LOW - Y stream. 9-0 HIGH - C stream, LOW - Y stream. Reserved. Total number of words in ANC packet to be inserted in third line. RSVD 15-11 Reserved. FOURTH_LINE_NUMBER 10-0 Fourth line number to insert ANC packet on in Seperate Line mode. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 97 of 125 Table 4-34: Video Core Configuration and Status Registers (Continued) Address 02Ch Register Name FOURTH_LINE_ NUMBER_OF_ WORDS Bit Name Bit Description R/W Default FOURTH_LINE_NUMBER_ ANC_TYPE 15 ANC region to insert packet in HIGH - VANC, LOW - HANC. R/W 0 FOURTH_LINE_NUMBER_ STREAM_TYPE 14 R/W 0 R 0 R/W 0 R 0 4 HIGH - ANC block will not insert data into the EDH region of the HANC space. LOW - ANC block will insert data into the EDH region. R/W 1 3 HIGH - data for the fourth line in separate mode is inserted into Data Stream Two. LOW - Data Stream One. Parameter only applicable for 3G. R/W 0 2 HIGH - data for the third line in separate mode is inserted into Data Stream Two. LOW - Data Stream One. Parameter only applicable for 3G. R/W 0 1 HIGH - data for the second line in separate mode is inserted into Data Stream Two. LOW - Data Stream One. Parameter only applicable for 3G. R/W 0 0 HIGH - data for the first line in separate mode is inserted into Data Stream Two. LOW - Data Stream One. Parameter only applicable for 3G. R/W 0 R 0 − − − − RSVD 13-10 9-0 Total number of words in ANC packet to be inserted in fourth line. RSVD 15-5 Reserved. STREAM_TYPE1_LINE_4 STREAM_TYPE_1 STREAM_TYPE1_LINE_3 STREAM_TYPE1_LINE_2 STREAM_TYPE1_LINE_1 02Eh to 03Fh 040h to 07Fh RSVD ANC_PACKET_ BANK_1 Reserved. FOURTH_LINE_NUMBER_OF_ WORDS EDH_LINE_CHECK_EN 02Dh Stream to insert packet in. HIGH - C stream, LOW - Y stream. RSVD 15-0 Reserved. First bank of user-defined 8-bit ancillary data. ANC_PACKET_BANK 15-0 Bit 15 - 8: 2nd byte (MSB to LSB) Bit 7 - 0: 1st byte (MSB to LSB) See 4.8 ANC Data Insertion. 080h to 0BFh ANC_PACKET_ BANK_2 Second bank of user-defined 8-bit ancillary data. ANC_PACKET_BANK 15-0 Bit 15 - 8: 2nd byte (MSB to LSB) Bit 7 - 0: 1st byte (MSB to LSB) See 4.8 ANC Data Insertion. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 98 of 125 Table 4-34: Video Core Configuration and Status Registers (Continued) Address 0C0h to 0FFh Register Name ANC_PACKET_ BANK_3 Bit Name Bit Description R/W Default − − − − Third bank of user-defined 8-bit ancillary data. ANC_PACKET_BANK 15-0 Bit 15 - 8: 2nd byte (MSB to LSB) Bit 7 - 0: 1st byte (MSB to LSB) See 4.8 ANC Data Insertion. 100h to 13Fh ANC_PACKET_ BANK_4 Fourth bank of user-defined 8-bit ancillary data. ANC_PACKET_BANK 15-0 Bit 15 - 8: 2nd byte (MSB to LSB) Bit 7 - 0: 1st byte (MSB to LSB) See 4.8 ANC Data Insertion. 140h to 209h 20Ah 20Bh to 20Ch 20Dh RSVD RSVD − Reserved. R 0 RSVD 15-8 Reserved. R 0 SDTI_TDM_DS2 7 HIGH indicates an SDTI type signal on input for Data Stream Two. R/W 0 SDTI_TDM_DS1 6 HIGH indicates an SDTI type signal on input for Data Stream One. R/W 0 SDTI_TDM RSVD LEVELB_INDICATION RSVD 5-0 Reserved. R 0 RSVD − Reserved. R 0 RSVD 15-9 Reserved. R 0 HIGH indicates level B detected. Only relevant for 3G input streams. R 0 LEVEL_B 8 RSVD 7-0 Reserved. R 0 RSVD 15-6 Reserved. R/W 0 R/W 0 R/W 0 Drive strength value for AUDIO_INT pin. AUDIO_INT_DS 20Eh 5-4 00: 4mA; 01: 6mA; 10: 8mA(+1.8V), 10mA(+3.3V); 11: 10mA(+1.8V), 12mA(+3.3V) Drive strength value for LOCKED pin. DRIVE_STRENGTH LOCKED_DS 3-2 00: 4mA; 01: 6mA; 10: 8mA(+1.8V), 10mA(+3.3V); 11: 10mA(+1.8V), 12mA(+3.3V) Drive strength value for SDOUT_TDO pin. 20Fh RSVD SDOUT_TDO_DS 1-0 00: 4mA; 01: 6mA; 10: 8mA(+1.8V), 10mA(+3.3V); 11: 10mA(+1.8V), 12mA(+3.3V) R/W 2 RSVD 15-0 Reserved. R/W 0 GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 99 of 125 Table 4-34: Video Core Configuration and Status Registers (Continued) Address Register Name Bit Name Bit Description R/W Default R/W 0 Drive strength value for TDO pin. 210h 211h to 232h 15-14 RSVD 13-0 Reserved. R/W 0 RSVD 15-0 Reserved. R 0 R/W Default R/W 0 R/W 0 R/W 0 DRIVE_STRENGTH2 RSVD 00: 4mA; 01: 6mA; 10: 8mA(+1.8V), 10mA(+3.3V); 11: 10mA(+1.8V), 12mA(+3.3V) TDO_DS 4.14.2 SD Audio Core Table 4-35: SD Audio Core Configuration and Status Registers Address Register Name Bit Name Bit Description Selects replacement of audio control packets. CTR_AGR 15 AGR 14 LOW - Do not replace audio control packets HIGH - Replace all audio control packets Selects Audio Group Replacement operating mode. Active HIGH. Specifies the replacement of just the primary group. 400h CFG_AUD ONE_AGR 13 CTRB_ON 12 Specifies the embedding of the secondary group audio control packets. Active HIGH. R/W 1 CLEAR_AUDIO 11 Clears all audio FIFO buffers and puts them in the start-up state. Active HIGH. R/W 0 AFNB_AUTO 10 Enables Secondary group audio frame number generation. Active HIGH. R/W 1 CTRA_ON 9 Specifies the embedding of primary group audio control packets. Active HIGH. R/W 1 R/W 0 AUDIO_24BIT GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 8 LOW - Replace both the primary and secondary groups HIGH Replace only the primary group Specifies the sample size for embedded audio. HIGH - 24-bit LOW - 20-bit/16-bit www.semtech.com 100 of 125 Table 4-35: SD Audio Core Configuration and Status Registers (Continued) Address Register Name Bit Name Description R/W Default 7 Enables Primary group audio frame number generation. Active HIGH. R/W 1 6-4 Offset to add to generated Audio Frame Number. Must be in the range of 0 to 4. R/W 0 3-2 Specifies the secondary audio group to embed. Note: Should IDA and IDB be set to the same value, they automatically revert to their default values. R/W 1 IDA 1-0 Specifies the primary audio group to embed. Note: Should IDA and IDB be set to the same value, they automatically revert to their default values. R/W 0 RSVD 15-3 Reserved. R 0 R/W 0 R/W 0 Reserved. R 0 3 Stereo Pair D (7&8) audio input parity error when using AES format. Automatically cleared when read. R 0 2 Stereo Pair C (5&6) audio input parity error when using AES format. Automatically cleared when read. R 0 1 Stereo Pair B (3&4) audio input parity error when using AES format. Automatically cleared when read. R 0 0 Stereo Pair A (1&2) audio input parity error when using AES format. Automatically cleared when read. R 0 AFNA_AUTO AFN_OFS 400h CFG_AUD IDB OFFSET_DISABLE 401h 2 Set to disable staggering of secondary group audio sample distribution by one line. Active HIGH. Specifies the audio FIFO buffer size. FIFO_BUF_SIDE OS_SEL 1-0 RSVD 15-4 AES_ERRD AES_ERRC 402h Bit AES_EBU_ERR_ STATUS AES_ERRB AES_ERRA GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 00-52 samples deep, 26 sample start-up count 01-24 samples deep, 12 sample start-up count 10-12 samples deep, 6 sample start-up count 11-Reserved www.semtech.com 101 of 125 Table 4-35: SD Audio Core Configuration and Status Registers (Continued) Address 403h Register Name CHANNEL_STAT_ REGEN Bit Name Bit Description RSVD 15-1 Reserved. PACKET_DET_ STATUS Default R 0 R/W 0 Reserved. R 0 Specifies that Audio Channel Status of all channels should be replaced with ACSR[183:0] field. ACS_REGEN RSVD 404h R/W 0 15-14 LOW: Do not replace Channel Status HIGH: Replace Channel Status of all channels AXPG4_DET 13 Set while Group 4 audio extended packets are detected. R 0 AXPG3_DET 12 Set while Group 3 audio extended packets are detected. R 0 AXPG2_DET 11 Set while Group 2 audio extended packets are detected. R 0 AXPG1_DET 10 Set while Group 1 audio extended packets are detected. R 0 ACPG4_DET 9 Set while Group 4 audio control packets are detected. R 0 ACPG3_DET 8 Set while Group 3 audio control packets are detected. R 0 ACPG2_DET 7 Set while Group 2 audio control packets are detected. R 0 ACPG1_DET 6 Set while Group 1 audio control packets are detected. R 0 ADPG4_DET 5 Set while Group 4 audio data packets are detected. R 0 ADPG3_DET 4 Set while Group 3 audio data packets are detected. R 0 ADPG2_DET 3 Set while Group 2 audio data packets are detected. R 0 ADPG1_DET 2 Set while Group 1 audio data packets are detected. R 0 1 Set while the GS2972 is waiting for a status boundary in the Secondary group before applying the ACSR[183:0] data to that group. R 0 0 ACS_APPLY_WAITA: Set while the GS2972 is waiting for a status boundary in Primary group before applying the ACSR[183:0] data. R 0 ACS_APPLY_WAITB ACS_APPLY_WAITA GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 102 of 125 Table 4-35: SD Audio Core Configuration and Status Registers (Continued) Address 405h 406h Register Name AES_EBU_ERR_ STATUS1 Bit Name Bit Description RSVD 15-6 Reserved. R 0 5 Final audio sample distribution error. R 0 HELD_ASD_ERR 4 Audio sample distribution error. R 0 HELD_AES_ERR 3-0 AES received errors for the 4 audio lines. R 0 RSVD 15-1 Reserved. R 0 R/W 0 R 0 R/W 3 CASCADE RSVD Default FINAL_HELD_ASD_ERR EN_CASCADE 407h to 40Ah R/W RSVD AMD 0 15-0 15-14 If HIGH, puts the GS2972 into cascade mode. This bit is only effective if the AGR bit = LOW. Reserved. Audio input format selector for Stereo Pair D input channels 7 and 8. 00: AES/EBU 01: Serial Left Justified 10: Serial Right Justified 11: I2S 40Bh SERIAL_AUDIO_ FORMAT AMC 13-12 Audio input format selector for Stereo Pair C input channels 5 and 6. (See above for decoding). R/W 3 AMB 11-10 Audio input format selector for Stereo Pair B input channels 3 and 4. (See above for decoding). R/W 3 AMA 9-8 Audio input format selector for Stereo Pair A input channels 1 and 2. (See above for decoding). R/W 3 MUTE8 7 Audio input channel 8 mute enable. Active HIGH. R/W 0 MUTE7 6 Audio input channel 7 mute enable. Active HIGH. R/W 0 MUTE6 5 Audio input channel 6 mute enable. Active HIGH. R/W 0 MUTE5 4 Audio input channel 5 mute enable. Active HIGH. R/W 0 MUTE4 3 Audio input channel 4 mute enable. Active HIGH. R/W 0 MUTE3 2 Audio input channel 3 mute enable. Active HIGH. R/W 0 MUTE2 1 Audio input channel 2 mute enable. Active HIGH. R/W 0 MUTE1 0 Audio input channel 1 mute enable. Active HIGH. R/W 0 GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 103 of 125 Table 4-35: SD Audio Core Configuration and Status Registers (Continued) Address Register Name Bit Name Bit Description RSVD 15 Reserved. R/W Default R 0 R/W 0 Primary Audio group word clock source selector. 40Ch 40Dh GPA_WCLK_SRC 14-12 GPA_CH4_SRC 11-9 Primary Audio group channel 4 source selector. 011. R/W 3 GPA_CH3_SRC 8-6 Primary Audio group channel 3 source selector. 010. R/W 2 GPA_CH2_SRC 5-3 Primary Audio group channel 2 source selector. 001. R/W 1 GPA_CH1_SRC 2-0 Primary Audio group channel 1 source selector. 000 - Input channel R/W 0 RSVD 15 Reserved. R 0 CHANNEL_XP_ GRPA CHANNEL_XP_ GRPB Input channel 1 000 Input channel 2 001 Input channel 3 010 Input channel 4 011 Input channel 5 100 Input channel 6 101 Input channel 7 110 Input channel 8 111 GPB_WCLK_SRC 14-12 Secondary Audio group word clock source selector. R/W 4 GPB_CH4_SRC 11-9 Secondary Audio group channel 4 source selector. R/W 7 GPB_CH3_SRC 8-6 Secondary Audio group channel 3 source selector. R/W 6 GPB_CH2_SRC 5-3 Secondary Audio group channel 2 source selector. R/W 5 GPB_CH1_SRC 2-0 Secondary Audio group channel 1 source selector. R/W 4 GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 104 of 125 Table 4-35: SD Audio Core Configuration and Status Registers (Continued) Address 40Eh Register Name Bit Name Bit Description R/W Default EN_ASD_ERR 15 Asserts ASD error flag. R/W 0 EN_NO_VIDEO 14 Mask bit when the video format is unknown. R/W 0 EN_MUX_ERRB 13 Asserts AUDIO_INT when the MUX_ERRB flag is set. R/W 0 EN_MUX_ERRA 12 Asserts AUDIO_INT when the MUX_ERRA flag is set. R/W 0 EN_AES_ERRD 11 Asserts AUDIO_INT when the AES_ERRD flag is set. R/W 0 EN_AES_ERRC 10 Asserts AUDIO_INT when the AES_ERRC flag is set. R/W 0 EN_AES_ERRB 9 Asserts AUDIO_INT when the AES_ERRB flag is set. R/W 0 EN_AES_ERRA 8 Asserts AUDIO_INT when the AES_ERRA flag is set. R/W 0 EN_ACPG4_DET 7 Asserts AUDIO_INT when the ACPG4_DET flag is set. R/W 0 EN_ACPG3_DET 6 Asserts AUDIO_INT when the ACPG3_DET flag is set. R/W 0 EN_ACPG2_DET 5 Asserts AUDIO_INT when the ACPG2_DET flag is set. R/W 0 EN_ACPG1_DET 4 Asserts AUDIO_INT when the ACPG1_DET flag is set. R/W 0 EN_ADPG4_DET 3 Asserts AUDIO_INT when the ADPG4_DET flag is set. R/W 0 EN_ADPG3_DET 2 Asserts AUDIO_INT when the ADPG3_DET flag is set. R/W 0 EN_ADPG2_DET 1 Asserts AUDIO_INT when the ADPG2_DET flag is set. R/W 0 EN_ADPG1_DET 0 Asserts AUDIO_INT when the ADPG1_DET flag is set. R/W 0 INTERRUPT_MASK GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 105 of 125 Table 4-35: SD Audio Core Configuration and Status Registers (Continued) Address Register Name Bit Name RSVD MUTE_ALL Reserved. R/W Default R 0 Mutes all input audio channels. R/W 0 11 Causes the fourth stereo pair serial input formats to use LSB first. Used in conjunction with AMD, and only relevant when AMD is 01 or 10 Figure 4-16 to 4-19. R/W 0 10 Causes the third stereo pair serial input formats to use LSB first. Used in conjunction with AMCand only relevant when AMC is 01 or 10 Figure 4-16 to 4-19. R/W 0 9 Causes the second stereo pair serial input formats to use LSB first. Used in conjunction with AMB and only relevant when AMD is 01 or 10 Figure 4-16 to 4-19. R/W 0 LSB_FIRSTA 8 Causes the first stereo pair serial input formats to use LSB first. Used in conjunction with AMA and only relevant when AMA is 01 or 10 Figure 4-16 to 4-19. R/W 0 ACT8 7 Specifies embedding of secondary audio group channel 8. Active HIGH. R/W 1 ACT7 6 Specifies embedding of secondary audio group channel 7. Active HIGH. R/W 1 ACT6 5 Specifies embedding of secondary audio group channel 6. Active HIGH. R/W 1 ACT5 4 Specifies embedding of secondary audio group channel 5. Active HIGH. R/W 1 ACT4 3 Specifies embedding of primary audio group channel 4. Active HIGH. R/W 1 ACT3 2 Specifies embedding of primary audio group channel 3. Active HIGH. R/W 1 ACT2 1 Specifies embedding of primary audio group channel 2. Active HIGH. R/W 1 ACT1 0 Specifies embedding of primary audio group channel 1. Active HIGH. R/W 1 LSB_FIRSTC LSB_FIRSTB ACTIVE_CHANNEL 15-13 Description 12 LSB_FIRSTD 40Fh Bit GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 106 of 125 Table 4-35: SD Audio Core Configuration and Status Registers (Continued) Address Register Name Bit Name Bit Description R/W Default RSVD 15-3 Reserved. R 0 2 Set in Cascade mode when the incoming video contains packets with the same group number as the Secondary Group. R 0 1 Set in Cascade mode when the incoming video contains packets with the same group number as the Primary Group. R 0 XPOINT_ERROR 0 Set when the crosspoint switch is configured to put the same audio channel in both Primary and Secondary Groups. R 0 RSVD − Reserved. R 0 RSVD 15-8 Reserved. R 0 ACSR_BYTE_1 7-0 Audio channel status block byte 1. R/W 133 RSVD 15-8 Reserved. R 0 ACSR_BYTE_2 7-0 Audio channel status block byte 2. R/W 8 ACSR_BYTE_4 15-8 Audio channel status block byte 4. R/W 0 ACSR_BYTE_3 7-0 Audio channel status block byte 3. R/W 44 ACSR_BYTE_6 15-8 Audio channel status block byte 6. R/W 0 ACSR_BYTE_5 7-0 Audio channel status block byte 5. R/W 0 ACSR_BYTE_8 15-8 Audio channel status block byte 8. R/W 0 ACSR_BYTE_7 7-0 Audio channel status block byte 7. R/W 0 ACSR_BYTE_10 15-8 Audio channel status block byte 10. R/W 0 ACSR_BYTE_9 7-0 Audio channel status block byte 9. R/W 0 ACSR_BYTE_12 15-8 Audio channel status block byte 12. R/W 0 ACSR_BYTE_11 7-0 Audio channel status block byte 11. R/W 0 ACSR_BYTE_14 15-8 Audio channel status block byte 14. R/W 0 ACSR_BYTE_13 7-0 Audio channel status block byte 13. R/W 0 ACSR_BYTE_16 15-8 Audio channel status block byte 16. R/W 0 ACSR_BYTE_15 7-0 Audio channel status block byte 15. R/W 0 MUX_ERRB 410h XPOINT_ERROR MUX_ERRA 411h to 41Fh RSVD 420h CHANNEL_STATUS_ REG_1 421h 422h 423h 424h 425h 426h 427h 428h CHANNEL_STATUS_ REG_2 CHANNEL_STATUS_ REG_3 CHANNEL_STATUS_ REG_4 CHANNEL_STATUS_ REG_5 CHANNEL_STATUS_ REG_6 CHANNEL_STATUS_ REG_7 CHANNEL_STATUS_ REG_8 CHANNEL_STATUS_ REG_9 GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 107 of 125 Table 4-35: SD Audio Core Configuration and Status Registers (Continued) Address Register Name 429h CHANNEL_STATUS_ REG_10 42Ah 42Bh 42Ch 42Dh to 43Fh 440h Bit Name Bit Description R/W Default ACSR_BYTE_18 15-8 Audio channel status block byte 18. R/W 0 ACSR_BYTE_17 7-0 Audio channel status block byte 17. R/W 0 ACSR_BYTE_20 15-8 Audio channel status block byte 20. R/W 0 ACSR_BYTE_19 7-0 Audio channel status block byte 19. R/W 0 ACSR_BYTE_22 15-8 Audio channel status block byte 22. R/W 0 ACSR_BYTE_21 7-0 Audio channel status block byte 21. R/W 0 RSVD 15-8 Reserved. R/W 0 ACSR_BYTE_23 7-0 Audio channel status block byte 23. R/W 0 CHANNEL_STATUS_ REG_11 CHANNEL_STATUS_ REG_12 CHANNEL_STATUS_ REG_13 RSVD RSVD − Reserved. R 0 RSVD 15-9 Reserved. R 0 DEL1A_BYTE_1 8-1 Primary Audio group delay data for channel 1 byte 1. R/W 0 Primary Audio group delay data for channel 1. HIGH - indicates delay specified at DEL1A_BYTE_1 is valid. See SMPTE ST 272 for additional information. R/W 0 R 0 R/W 0 R 0 R/W 0 R 0 AUDIO_CTRL_ GRPA_REG_1 EBIT1A 441h 442h 443h AUDIO_CTRL_ GRPA_REG_2 AUDIO_CTRL_ GRPA_REG_3 AUDIO_CTRL_ GRPA_REG_4 RSVD 15-9 Reserved. DEL1A_BYTE_2 8-0 Primary Audio group delay data for channel 1 byte 2. RSVD 15-9 Reserved. DEL1A_BYTE_3 8-0 Primary Audio group delay data for channel 1 byte 3. RSVD 15-9 Reserved. DEL2A_BYTE_1 8-1 Primary Audio group delay data for channel 2 byte 1. R/W 0 0 Primary Audio group delay data valid flag for channel 2. R/W 0 R 0 R/W 0 R 0 R/W 0 EBIT2A 444h 445h AUDIO_CTRL_ GRPA_REG_5 AUDIO_CTRL_ GRPA_REG_6 0 RSVD 15-9 Reserved. DEL2A_BYTE_2 8-0 Primary Audio group delay data for channel 2 byte 2. RSVD 15-9 Reserved. DEL2A_BYTE_3 8-0 Primary Audio group delay data for channel 2 byte 3. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 108 of 125 Table 4-35: SD Audio Core Configuration and Status Registers (Continued) Address 446h Register Name AUDIO_CTRL_ GRPA_REG_7 Bit Name Bit Description RSVD 15-9 Reserved. DEL3A_BYTE_1 8-1 0 EBIT3A 447h 448h 449h AUDIO_CTRL_ GRPA_REG_8 AUDIO_CTRL_ GRPA_REG_9 AUDIO_CTRL_ GRPA_REG_10 44Bh 44Ch AUDIO_CTRL_ GRPA_REG_11 AUDIO_CTRL_ GRPA_REG_12 AUDIO_CTRL_ GRPB_REG_1 44Dh 44Eh 44Fh AUDIO_CTRL_ GRPB_REG_3 AUDIO_CTRL_ GRPB_REG_4 R 0 Primary Audio group delay data for channel 3 byte 1. R/W 0 Primary Audio group delay data valid flag for channel 3. R/W 0 R 0 R/W 0 R 0 R/W 0 R 0 15-9 Reserved. DEL3A_BYTE_2 8-0 Primary Audio group delay data for channel 3 byte 2. RSVD 15-9 Reserved. DEL3A_BYTE_3 8-0 Primary Audio group delay data for channel 3 byte 3. RSVD 15-9 Reserved. DEL4A_BYTE_1 8-1 Primary Audio group delay data for channel 4 byte 1. R/W 0 0 Primary Audio group delay data valid flag for channel 4. R/W 0 R 0 R/W 0 R 0 R/W 0 R 0 RSVD 15-9 Reserved. DEL4A_BYTE_2 8-0 Primary Audio group delay data for channel 4 byte 2. RSVD 15-9 Reserved. DEL4A_BYTE_3 8-0 Primary Audio group delay data for channel 4 byte 3. RSVD 15-9 Reserved. DEL1B_BYTE_1 8-1 Secondary Audio group delay data for channel 1 byte 1. R/W 0 0 Secondary Audio group delay data valid flag for channel 1. R/W 0 R 0 R/W 0 R 0 R/W 0 R 0 EBIT1B AUDIO_CTRL_ GRPB_REG_2 Default RSVD EBIT4A 44Ah R/W RSVD 15-9 Reserved. DEL1B_BYTE_2 8-0 Secondary Audio group delay data for channel 1 byte 2. RSVD 15-9 Reserved. DEL1B_BYTE_3 8-0 Secondary Audio group delay data for channel 1 byte 3. RSVD 15-9 Reserved. DEL2B_BYTE_1 8-1 Secondary Audio group delay data for channel 2 byte 1. R/W 0 0 Secondary Audio group delay data valid flag for channel 2. R/W 0 EBIT2B GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 109 of 125 Table 4-35: SD Audio Core Configuration and Status Registers (Continued) Address 450h 451h 452h Register Name AUDIO_CTRL_ GRPB_REG_5 AUDIO_CTRL_ GRPB_REG_6 AUDIO_CTRL_GR PB_REG_7 Bit Name Bit Description RSVD 15-9 Reserved. DEL2B_BYTE_2 8-0 Secondary Audio group delay data for channel 2 byte 2. RSVD 15-9 Reserved. DEL2B_BYTE_3 8-0 Secondary Audio group delay data for channel 2 byte 3. RSVD 15-9 Reserved. DEL3B_BYTE_1 8-1 0 EBIT3B 453h 454h 455h AUDIO_CTRL_GR PB_REG_8 AUDIO_CTRL_GR PB_REG_9 AUDIO_CTRL_GR PB_REG_10 457h AUDIO_CTRL_GR PB_REG_11 AUDIO_CTRL_GR PB_REG_12 Default R 0 R/W 0 R 0 R/W 0 R 0 Secondary Audio group delay data for channel 3 byte 1. R/W 0 Secondary Audio group delay data valid flag for channel 3. R/W 0 R 0 R/W 0 R 0 R/W 0 R 0 RSVD 15-9 Reserved. DEL3B_BYTE_2 8-0 Secondary Audio group delay data for channel 3 byte 2. RSVD 15-9 Reserved. DEL3B_BYTE_3 8-0 Secondary Audio group delay data for channel 3 byte 3. RSVD 15-9 Reserved. DEL4B_BYTE_1 8-1 Secondary Audio group delay data for channel 4 byte 1. R/W 0 0 Secondary Audio group delay data valid flag for channel 4. R/W 0 R 0 R/W 0 R 0 R/W 0 EBIT4B 456h R/W RSVD 15-9 Reserved. DEL4B_BYTE_2 8-0 Secondary Audio group delay data for channel 4 byte 2. RSVD 15-9 Reserved. DEL4B_BYTE_3 8-0 Secondary Audio group delay data for channel 4 byte 3. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 110 of 125 4.14.3 HD and 3G Audio Core Registers Table 4-36: HD and 3G Audio Core Configuration and Status Registers Address Register Name Bit Name Bit Description R/W Default R/W 0 R/W 0 R/W 0 Selects replacement of audio control packets. CTR_AGR 15 AGR 14 LOW - Do not replace audio control packets HIGH - Replace all audio control packets Selects Audio Group Replacement operating mode. Active HIGH. Specifies the replacement of just the primary group. 800h LOW - Replace both the primary and secondary groups. HIGH - Replace only the primary group. ONE_AGR 13 CTRB_ON 12 Specifies the embedding of the secondary group audio control packets. Active HIGH. R/W 1 ASXB 11 Secondary Group asynchronous mode. Active HIGH. R/W 0 AFNB_AUTO 10 Enables Secondary group audio frame number generation. Active HIGH. R/W 1 CTRA_ON 9 Specifies the embedding of primary group audio control packets. Active HIGH. R/W 1 ASXA 8 Primary Group asynchronous mode. R/W 0 AFNA_AUTO 7 Enables Primary group audio frame number generation. R/W 1 Offset to add to generated Audio Frame Number. Must be in the range of 0 to 4. R/W 0 R/W 1 R/W 0 R 0 CFG_AUD ANF_OFS 6-4 Specifies the Secondary audio group to embed. IDB 3-2 00: Audio group #1 01: Audio group #2 10: Audio group #3 11: Audio group #4 Specifies the Primary audio group to embed. 801h RSVD IDA 1-0 00: Audio group #1 01: Audio group #2 10: Audio group #3 11: Audio group #4 RSVD 15-0 Reserved. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 111 of 125 Table 4-36: HD and 3G Audio Core Configuration and Status Registers (Continued) Address 802h Register Name CHANNEL_STAT_ REGREN Bit Name Bit Description RSVD 15-1 Reserved. PACKET_DET_ STATUS ACS_REGEN 803h R 0 0 R/W 0 15-14 Reserved. R 0 LOW: Do not replace Channel Status HIGH: Replace Channel Status of all channels AES_ERRD 13 Stereo Pair D audio input parity error when using AES format. Automatically cleared when read. R 0 AES_ERRC 12 Stereo Pair C audio input parity error when using AES format. Automatically cleared when read. R 0 AES_ERRB 11 Stereo Pair B audio input parity error when using AES format. Automatically cleared when read. R 0 AES_ERRA 10 Stereo Pair A audio input parity error when using AES format. Automatically cleared when read. R 0 ACPG4_DET 9 Set while Group 4 audio control packets are detected. R 0 ACPG3_DET 8 Set while Group 3 audio control packets are detected. R 0 ACPG2_DET 7 Set while Group 2 audio control packets are detected. R 0 ACPG1_DET 6 Set while Group 1 audio control packets are detected. R 0 ADPG4_DET 5 Set while Group 4 audio data packets are detected. R 0 ADPG3_DET 4 Set while Group 3 audio data packets are detected. R 0 ADPG2_DET 3 Set while Group 2 audio data packets are detected. R 0 ADPG1_DET 2 Set while Group 1 audio data packets are detected. R 0 1 Set while the GS2972 is waiting for a status boundary in the Secondary group before applying the ACSR[183:0] data to that group. R 0 0 ACS_APPLY_WAITA: Set while the multiplexer is waiting for a status boundary in Primary group before applying the ACSR[183:0] data. R 0 ACS_APPLY_WAITB PACKET_DET_ STATUS Default Specifies that Audio Channel Status of all channels should be replaced with ACSR[183:0] field. RSVD 803h R/W ACS_APPLY_WAITA GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 112 of 125 Table 4-36: HD and 3G Audio Core Configuration and Status Registers (Continued) Address Register Name 804h AES_EBU_ERR_ STATUS 805h Bit Name Bit Description RSVD 15-4 HELD_AES_ERR RSVD Default Reserved. R 0 3-0 AES received errors for the 4 audio lines. R 0 15-1 Reserved. R 0 R/W 0 R 0 R/W 3 CASCADE EN_CASCADE 806h to 809h R/W RSVD RSVD AMD 0 15-0 15-14 If HIGH, puts the GS2972 into cascade mode. This bit is only effective if the AGR bit is LOW. Reserved. Audio input format selector for Stereo Pair D input channels 7 and 8. 00: AES/EBU 01: Serial Left Justified 10: Serial Right Justified 11: I2S 80Ah 80Ah SERIAL_AUDIO_ FORMAT AMC 13-12 Audio input format selector for Stereo Pair C input channels 5 and 6. (See above for decoding). R/W 3 AMB 11-10 Audio input format selector for Stereo Pair B input channels 3 and 4. (See above for decoding). R/W 3 AMA 9-8 Audio input format selector for Stereo Pair A input channels 1 and 2. (See above for decoding). R/W 3 MUTE8 7 Audio input channel 8 mute enable. R/W 0 MUTE7 6 Audio input channel 7 mute enable. R/W 0 MUTE6 5 Audio input channel 6 mute enable. R/W 0 MUTE5 4 Audio input channel 5 mute enable. R/W 0 MUTE4 3 Audio input channel 4 mute enable. R/W 0 MUTE3 2 Audio input channel 3 mute enable. R/W 0 MUTE2 1 Audio input channel 2 mute enable. R/W 0 MUTE1 0 Audio input channel 1 mute enable. R/W 0 GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 113 of 125 Table 4-36: HD and 3G Audio Core Configuration and Status Registers (Continued) Address 80Bh 80Ch Register Name CHANNEL_XP_ GRPA CHANNEL_XP_ GRPB Bit Name Bit Description RSVD 15 Reserved. R/W Default R 0 GPA_WCLK_SRC 14-12 Primary Audio group word clock source selector. R/W 0 GPA_CH4_SRC 11-9 Primary Audio group channel 4 source selector. R/W 3 GPA_CH3_SRC 8-6 Primary Audio group channel 3 source selector. R/W 2 GPA_CH2_SRC 5-3 Primary Audio group channel 2 source selector. R/W 1 GPA_CH1_SRC 2-0 Primary Audio group channel 1 source selector. R/W 0 RSVD 15 Reserved. R 0 GPB_WCLK_SRC 14-12 Secondary Audio group word clock source selector. R/W 4 GPB_CH4_SRC 11-9 Secondary Audio group channel 4 source selector. R/W 7 GPB_CH3_SRC 8-6 Secondary Audio group channel 3 source selector. R/W 6 GPB_CH2_SRC 5-3 Secondary Audio group channel 2 source selector. R/W 5 GPB_CH1_SRC 2-0 Secondary Audio group channel 1 source selector. R/W 4 GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 114 of 125 Table 4-36: HD and 3G Audio Core Configuration and Status Registers (Continued) Address 80Dh Register Name INTERRUPT_ MASK Bit Name Bit Description R/W Default RSVD 15 Reserved. R 0 EN_NO_VIDEO 14 Asserts AUDIO_INT mask bit when the video format is unknown i.e. when NO_VIDEO register bit is set. R/W 0 EN_MUX_ERRB 13 Asserts AUDIO_INT when the MUX_ERRB flag is set. R/W 0 EN_MUX_ERRA 12 Asserts AUDIO_INT when the MUX_ERRA flag is set. R/W 0 EN_AES_ERRD 11 Asserts AUDIO_INT when the AES_ERRD flag is set. R/W 0 EN_AES_ERRC 10 Asserts AUDIO_INT when the AES_ERRC flag is set. R/W 0 EN_AES_ERRB 9 Asserts AUDIO_INT when the AES_ERRB flag is set. R/W 0 EN_AES_ERRA 8 Asserts AUDIO_INT when the AES_ERRA flag is set. R/W 0 EN_ACPG4_DET 7 Asserts AUDIO_INT when the ACPG4_DET flag is set. R/W 0 EN_ACPG3_DET 6 Asserts AUDIO_INT when the ACPG3_DET flag is set. R/W 0 EN_ACPG2_DET 5 Asserts AUDIO_INT when the ACPG2_DET flag is set. R/W 0 EN_ACPG2_DET 5 Asserts AUDIO_INT when the ACPG2_DET flag is set. R/W 0 EN_ACPG1_DET 4 Asserts AUDIO_INT when the ACPG1_DET flag is set. R/W 0 EN_ADPG4_DET 3 Asserts AUDIO_INT when the ADPG4_DET flag is set. R/W 0 EN_ADPG3_DET 2 Asserts AUDIO_INT when the ADPG3_DET flag is set. R/W 0 EN_ADPG2_DET 1 Asserts AUDIO_INT when the ADPG2_DET flag is set. R/W 0 EN_ADPG1_DET 0 Asserts AUDIO_INT when the ADPG1_DET flag is set. R/W 0 GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 115 of 125 Table 4-36: HD and 3G Audio Core Configuration and Status Registers (Continued) Address Register Name Bit Name RSVD 80Eh 15-13 Description Reserved. R/W Default R 0 MUTE_ALL 12 Mutes all input audio channels. R/W 0 LSB_FIRSTD 11 Causes the fourth stereo pair serial input formats to use LSB first. R/W 0 LSB_FIRSTC 10 Causes the third stereo pair serial input formats to use LSB first. R/W 0 LSB_FIRSTB 9 Causes the second stereo pair serial input formats to use LSB first. R/W 0 LSB_FIRSTA 8 Causes the first stereo pair serial input formats to use LSB first. R/W 0 ACT8 7 Specifies embedding of secondary audio group channel 8. Active HIGH. R/W 1 ACT7 6 Specifies embedding of secondary audio group channel 7. Active HIGH. R/W 1 ACT6 5 Specifies embedding of secondary audio group channel 6. Active HIGH. R/W 1 ACT5 4 Specifies embedding of secondary audio group channel 5. Active HIGH. R/W 1 ACT4 3 Specifies embedding of secondary audio group channel 4. Active HIGH. R/W 1 ACT3 2 Specifies embedding of secondary audio group channel 3. Active HIGH. R/W 1 ACT2 1 Specifies embedding of secondary audio group channel 2. Active HIGH. R/W 1 ACT1 0 Specifies embedding of secondary audio group channel 1. Active HIGH. R/W 1 RSVD 15-3 Reserved. R 0 2 Set in Cascade mode when the incoming video contains packets with the same group number as the Secondary Group. R 0 1 Set in Cascade mode when the incoming video contains packets with the same group number as the Primary Group. R 0 0 Set when the crosspoint switch is configured to put the same audio channel in both Primary and Secondary Groups. R 0 ACTIVE_ CHANNEL MUX_ERRB 80Fh Bit XPOINT_ERROR MUX_ERRA XPOINT_ERROR GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 116 of 125 Table 4-36: HD and 3G Audio Core Configuration and Status Registers (Continued) Address Register Name 810h to 81Fh RSVD 820h CHANNEL_ STATUS_REG_1 821h 822h 823h 824h 825h 826h 827h 828h 829h 82Ah 82Bh 82Ch 82Dh to 83Fh 840h CHANNEL_ STATUS_REG_2 CHANNEL_ STATUS_REG_3 CHANNEL_ STATUS_REG_4 CHANNEL_ STATUS_REG_5 CHANNEL_ STATUS_REG_6 CHANNEL_ STATUS_REG_7 CHANNEL_ STATUS_REG_8 CHANNEL_ STATUS_REG_9 CHANNEL_ STATUS_REG_10 CHANNEL_ STATUS_REG_11 CHANNEL_ STATUS_REG_12 CHANNEL_ STATUS_REG_13 RSVD AUDIO_CTRL_ GRPA_REG_1 Bit Name Bit Description R/W Default RSVD − Reserved. R 0 RSVD 15-8 Reserved. R 0 ACSR_BYTE_1 7-0 Audio channel status block byte 1. R/W 133 RSVD 15-8 Reserved. R 0 ACSR_BYTE_2 7-0 Audio channel status block byte 2. R/W 8 ACSR_BYTE_4 15-8 Audio channel status block byte 4. R/W 0 ACSR_BYTE_3 7-0 Audio channel status block byte 3. R/W 44 ACSR_BYTE_6 15-8 Audio channel status block byte 6. R/W 0 ACSR_BYTE_5 7-0 Audio channel status block byte 5. R/W 0 ACSR_BYTE_8 15-8 Audio channel status block byte 8. R/W 0 ACSR_BYTE_7 7-0 Audio channel status block byte 7. R/W 0 ACSR_BYTE_10 15-8 Audio channel status block byte 10. R/W 0 ACSR_BYTE_9 7-0 Audio channel status block byte 9. R/W 0 ACSR_BYTE_12 15-8 Audio channel status block byte 12. R/W 0 ACSR_BYTE_11 7-0 Audio channel status block byte 11. R/W 0 ACSR_BYTE_14 15-8 Audio channel status block byte 14. R/W 0 ACSR_BYTE_13 7-0 Audio channel status block byte 13. R/W 0 ACSR_BYTE_16 15-8 Audio channel status block byte 16. R/W 0 ACSR_BYTE_15 7-0 Audio channel status block byte 15. R/W 0 ACSR_BYTE_18 15-8 Audio channel status block byte 18. R/W 0 ACSR_BYTE_17 7-0 Audio channel status block byte 17. R/W 0 ACSR_BYTE_20 15-8 Audio channel status block byte 20. R/W 0 ACSR_BYTE_19 7-0 Audio channel status block byte 19. R/W 0 ACSR_BYTE_22 15-8 Audio channel status block byte 22. R/W 0 ACSR_BYTE_21 7-0 Audio channel status block byte 21. R/W 0 RSVD 15-8 Reserved. R 0 ACSR_BYTE_23 7-0 Audio channel status block byte 23. R/W 0 RSVD − Reserved. R 0 RSVD 15-9 Reserved. R 0 DEL1_2A_BYTE_1 8-1 Primary Audio group delay data for channel 1 & 2. R/W 0 Primary Audio group delay data valid flag for channel 1 & 2. R/W 0 EBIT1_2A GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 0 www.semtech.com 117 of 125 Table 4-36: HD and 3G Audio Core Configuration and Status Registers (Continued) Address Register Name 841h AUDIO_CTRL_ GRPA_REG_2 842h 843h AUDIO_CTRL_ GRPA_REG_3 AUDIO_CTRL_ GRPA_REG_4 Bit Name Bit Description RSVD 15-9 Reserved. DEL1_2A_BYTE_2 8-0 Primary Audio group delay data for channel 1 & 2. RSVD 15-9 Reserved. DEL1_2A_BYTE_3 8-0 Primary Audio group delay data for channel 1 & 2. RSVD 15-9 Reserved. DEL3_4A_BYTE_1 8-1 EBIT3_4A 844h 845h 846h AUDIO_CTRL_ GRPA_REG_5 AUDIO_CTRL_ GRPA_REG_6 AUDIO_CTRL_ GRPB_REG_1 848h 849h AUDIO_CTRL_ GRPB_REG_2 AUDIO_CTRL_ GRPB_REG_3 AUDIO_CTRL_ GRPB_REG_4 84Ah 84Bh AUDIO_CTRL_ GRPB_REG_6 R 0 R/W 0 R 0 R/W 0 R 0 Primary Audio group delay data for channel 3 & 4. R/W 0 Primary Audio group delay data valid flag for channel 3 & 4. R/W 0 R 0 R/W 0 R 0 R/W 0 R 0 15-9 Reserved. DEL3_4A_BYTE_2 8-0 Primary Audio group delay data for channel 3 & 4. RSVD 15-9 Reserved. DEL3_4A_BYTE_3 8-0 Primary Audio group delay data for channel 3 & 4. RSVD 15-9 Reserved. DEL1_2B_BYTE_1 8-1 Secondary Audio group delay data for channel 1 & 2. R/W 0 0 Secondary Audio group delay data valid flag for channel 1 & 2. R/W 0 R 0 R/W 0 R 0 R/W 0 R 0 RSVD 15-9 Reserved. DEL1_2B_BYTE_2 8-0 Secondary Audio group delay data for channel 1 & 2. RSVD 15-9 Reserved. DEL1_2B_BYTE_3 8-0 Secondary Audio group delay data for channel 1 & 2. RSVD 15-9 Reserved. DEL3_4B_BYTE_1 8-1 Secondary Audio group delay data for channel 3 & 4. R/W 0 0 Secondary Audio group delay data for channel 3 & 4. R/W 0 R 0 R/W 0 R 0 R/W 0 EBIT3_4B AUDIO_CTRL_ GRPB_REG_5 Default RSVD EBIT1_2B 847h 0 R/W RSVD 15-9 Reserved. DEL3_4B_BYTE_2 8-0 Secondary Audio group delay data for channel 3 & 4. RSVD 15-9 Reserved. DEL3_4B_BYTE_3 8-0 Secondary Audio group delay data for channel 3 & 4. GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 118 of 125 4.15 JTAG ID Codeword The Platform ID for the 297X family is 0Fh. The part number field of the JTAG ID codeword for the GS2972 is set to 0F01h. 4.16 JTAG Test Operation When the JTAG/HOST pin is HIGH, the GSPI host interface port is configured for JTAG test operation. In this mode the SCLK, SDIN, SDOUT and CS become TCK, TDI, TDO and TMS. In addition, the TRST pin becomes active. Boundary scan testing using the JTAG interface is enabled in this mode. When the JTAG/HOST pin is LOW, the dedicated JTAG interface is used. In this mode the TCK, TDI, TDO and TMS pins are active. This is the recommended mode for new designs. 4.17 Device Power-Up Because the GS2972 is designed to operate in a multi-voltage environment, any power-up sequence is allowed. The Charge Pump, Phase Detector, Core Logic, Serial Digital Output and I/O Buffers can all be powered up in any order. 4.18 Device Reset Note: At power-up, the device must be reset to operate correctly. In order to initialize all internal operating conditions to their default states, hold the RESET signal LOW for a minimum of treset = 1ms after all power supplies are stable. There are no requirements for power supply sequencing. When held in reset, all device outputs will be driven to a high-impedance state. Nominal Level 95% of Nominal Level Supply Voltage treset treset Reset Reset RESET Figure 4-35: Reset Pulse GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 119 of 125 5. Application Reference Design 5.1 Typical Application Circuit Power Filtering Power Decoupling CD_VDD +3.3V +1.2V +1.2V_A 0Ω 10nF +1.2V 0Ω 10nF 1µF 1µF 10nF 1µF 1µF 10nF 10nF 10nF 10nF 10nF 0Ω GND_A GND_A +3.3V_A IO_VDD IO_VDD 0Ω 10nF 1µF 1µF 1µF 10nF 10nF 10nF GND_A Place close to GS2972 +3.3V_A CD_VDD +1.2V_A +1.2V_A 105Ω 10nF 10nF GND_A GND_A A3 C4 A4 F/DE V/VSYNC H/HSYNC PCLK PCLK DNP B4 A5 E1 K8 G10 F/DE V/VSYNC H/HSYNC STANDBY TIM_861 SMPTE_BYPASS DVB_ASI RATE_SEL0 RATE_SEL1 IOPROC_EN/DIS 20bit/10bit SDO_EN/DIS DETECT_TRS ANC_BLANK PCLK DNP DIN[19:0] B3 A2 A1 B2 B1 C2 C1 C3 D1 D2 F1 F2 H1 H2 J1 J2 K1 K2 J3 K3 A_VDD CD_VDD CORE_VDD CORE_VDD CORE_VDD CORE_VDD A6 B6 PLL_VDD PLL_VDD LF VBG DIN 19 DIN 18 DIN 17 DIN 16 DIN 15 DIN 14 DIN 13 DIN 12 DIN 11 DIN 10 DIN 9 DIN 8 DIN 7 DIN 6 DIN 5 DIN 4 DIN 3 DIN 2 DIN 1 DIN 0 RSV RSV RSV RSV RSV RSV RSV TCK TDO TMS GS2972-IBE3 TDI SDO SDO AUDIO_INT STANDBY TIM_861 SMPTE_BYPASS DVB_ASI RATE_SEL0 RATE_SEL1 IOPROC_EN/DIS 20BIT/10BIT SDO_EN/DIS DETECT_TRS ANC_BLANK D5 F7 F4 D6 D7 D8 A9 J8 F8 E8 TCK TDO TMS E7 TDI Return Loss Compensation Network RSET H7 D3 G3 G6 G5 E3 E4 G7 G4 D4 F3 H3 F10 750Ω 5.6nH C10 SDO D10 SDO 75Ω 75Ω 75Ω CD_VDD SDO 10nF GND_A GND_A 4.7µF 1 SDO AUDIO_INT (SUBJECT TO CHANGE) CS_TMS SCLK_TCK SDIN_TDI SDOUT_TDO JTAG/HOST RESET LOCKED IO_GND IO_GND K9 J10 K10 J9 H8 G8 H4 G2 H9 CORE_GND CORE_GND CORE_GND CORE_GND CORE_GND CORE_GND CORE_GND CORE_GND B5 C5 E2 E5 E6 F5 F6 G9 CD_GND CD_GND CD_GND CD_GND A_GND A_GND VCO_GND GND_A CS_TMS SCLK_TCK SDIN_TDI SDOUT_TDO JTAG/HOST RESET LOCKED C9 D9 E9 F9 C6 C7 C8 PLL_GND PLL_GND PLL_GND GRP1_EN/DIS ACLK1 WCLK1 Ain_1/2 Ain_3/4 GRP2_EN/DIS ACLK2 WCLK2 Ain_5/6 Ain_7/8 B9 B10 B8 Audio Data and Clock Input H6 K7 J7 J6 K6 H5 K5 J5 J4 K4 1 75Ω 5.6nH GRP1_EN/DIS ACLK1 WCLK1 AIN_1/2 AIN_3/4 GRP2_EN/DIS ACLK2 WCLK2 AIN_5/6 AIN_7/8 4.7µF CD_VDD SDI Output Video Data, Clock & Timing Input 1µF 2 3 A7 A8 GND_A 2 3 200Ω E10 B7 VCO_VDD 100pF 10µF A10 IO_VDD +1.2V Close to GS2972. Close to GS2972. GND_A G1 H10 GND_A 10nF IO_VDD IO_VDD 10µF GND_A Notes: 1. DNP (Do Not Populate). 2. The value of the series resistors on video data, clock, and timing connections should be determined by board signal integrity test (See Section 4.1.1). 3. For analog power and ground isolation refer to PCB layout guide. 4. For critital 3G signal layout refer to PCB layout guide. 5. For impedance controlled signals refer to PCB layout guide. Figure 5-1: Typical Application Circuit GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 120 of 125 6. References & Relevant Standards SMPTE ST 125 Component video signal 4:2:2 – bit parallel interface SMPTE ST 259-C 10-bit 4:2:2 Component and 4fsc Composite Digital Signals - Serial Digital Interface SMPTE ST 260 1125 / 60 high definition production system – digital representation and bit parallel interface SMPTE ST 267 Bit parallel digital interface – component video signal 4:2:2 16 x 9 aspect ratio SMPTE ST 272 Formatting AES/EBU Audio and Auxiliary Data into Digital Video Ancillary Data Space SMPTE ST 274 1920 x 1080 scanning analog and parallel digital interfaces for multiple picture rates SMPTE ST 291 Ancillary Data Packet and Space Formatting SMPTE ST 292 Bit-Serial Digital Interface for High-Definition Television Systems SMPTE ST 293 720 x 483 active line at 59.94Hz progressive scan production – digital representation SMPTE ST 296 1280 x 720 scanning, analog and digital representation and analog interface SMPTE ST 299 24-Bit Digital Audio Format for HDTV Bit-Serial Interface SMPTE ST 305 Serial Data Transport Interface SMPTE ST 348 High Data-Rate Serial Data Transport Interface (HD-SDTI) SMPTE ST 352 Video Payload Identification for Digital Television Interfaces SMPTE ST 372 Dual Link ST 292 Interface for 1920 x 1080 Picture Raster SMPTE ST 424 3Gb/s Signal/Data Serial Interface SMPTE ST 425 3Gb/s Signal/Data Serial Interface - Source Image Format Mapping SMPTE RP165 Error Detection Checkwords and Status Flags for use in Bit-Serial Digital Interfaces for Television SMPTE RP168 Definition of Vertical Interval Switching Point for Synchronous Video Switching CEA 861 Video Timing Requirements GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 121 of 125 7. Package & Ordering Information 7.1 Package Dimensions Figure 7-1: Package Dimensions GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 122 of 125 7.2 Packaging Data Table 7-1: Packaging Data Parameter Value Package Type 11mm x 11mm 100-ball LBGA Package Drawing Reference JEDEC M0192 (with exceptions noted in Package Dimensions on page 122). Moisture Sensitivity Level 3 Junction to Case Thermal Resistance, θj-c 10.4°C/W Junction to Air Thermal Resistance, θj-a (at zero airflow) 37.1°C/W Junction to Board Thermal Resistance, θj-b 26.4°C/W Psi, ψ 0.4°C/W Pb-free and RoHS Compliant Yes 7.3 Marking Diagram Pin 1 ID GS2972 XXXXXXE3 YYWW XXXXXX - Last 6 digits (excluding decimal) of SAP Batch Assembly (FIN) as listed on Packing Slip. E3 - Pb-free & Green indicator YYWW - Date Code Figure 7-2: Marking Diagram GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 123 of 125 7.4 Solder Reflow Profiles The GS2972 is available in a Pb-free package. It is recommended that the Pb-free package be soldered with Pb-free paste using the reflow profile shown in Figure 7-3. Temperature 60-150 sec. 20-40 sec. 260°C 250°C 3°C/sec max 217°C 6°C/sec max 200°C 150°C 25°C Time 60-180 sec. max 8 min. max Figure 7-3: Pb-free Solder Reflow Profile 7.5 Ordering Information Table 7-2: Ordering Information Part Number Package Pb-free Temperature Range GS2972-IBE3 100-ball BGA Yes -20°C to 85°C GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 124 of 125 DOCUMENT IDENTIFICATION CAUTION FINAL DATA SHEET ELECTROSTATIC SENSITIVE DEVICES Information relating to this product and the application or design described herein is believed to be reliable, however such information is provided as a guide only and Semtech assumes no liability for any errors in this document, or for the application or design described herein. Semtech reserves the right to make changes to the product or this document at any time without notice. DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION © Semtech 2012 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Contact Information Semtech Corporation Gennum Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111, Fax: (805) 498-3804 www.semtech.com GS2972 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support Final Data Sheet Rev. 9 GENDOC-047479 September 2013 www.semtech.com 125 of 125 125