GS2974A HD-LINX™ III Adaptive Cable Equalizer
Features
• • • • • • • • • • • • • • SMPTE 424M, SMPTE 292M and SMPTE 259M compliant Automatic cable equalization 0.3UI Maximum Output Jitter at 2.97Gb/s Multi-standard operation from 143Mb/s to 2.97Gb/s Supports DVB-ASI at 270Mb/s Small footprint (4mm x 4mm) Pb-free and RoHS compliant Manual bypass (useful for low data rates with slow rise/fall times) Performance optimized for 1.485Gb/s and 2.97Gb/s Typical equalized length of Belden 1694A cable: 120m at 2.97Gb/s, 200m at 1.485Gb/s, and 350m at 270Mb/s 50Ω differential output (internal 50Ω pull-ups) Programmable mute based on max cable length adjust Single 3.3V power supply operation Operating temperature range: 0°C to +70°C
Description
The GS2974A is a high-speed BiCMOS integrated circuit designed to equalize and restore signals received over 75Ω co-axial cable. The GS2974A is designed to support SMPTE 424M, SMPTE 292M and SMPTE 259M, and is optimized for performance at 1.485Gb/s and 2.97Gb/s. The GS2974A features DC restoration to compensate for the DC content of SMPTE pathological test patterns. A voltage programmable mute threshold (MCLADJ), applicable for SD mode (refer to Section 4.3), is included to allow muting of the GS2974A output when an approximate selected cable length is reached for SMPTE 259M signals. This feature allows the GS2974A to distinguish between low amplitude SD-SDI signals and noise at the input of the device. The serial digital outputs of the GS2974A may be forced to a mute state by applying a voltage to the MUTE pin. Power consumption is typically 215mW using a 3.3V power supply. The GS2974A is lead-free, and the encapsulation compound does not contain halogenated flame retardant. This component and all homogeneous subcomponents are RoHS compliant.
Applications
• SMPTE 424M, SMPTE 292M and SMPTE 259M Coaxial Cable Serial Digital Interfaces.
MCLADJ
CABLE LENGTH ADJUSTOR CARRIER DETECT MUTE
CD MUTE BYPASS
SDI SDI
EQUALIZER
DC RESTORE
OUTPUT
SDO SDO
AGC
GS2974A Functional Block Diagram
GS2974A HD-LINX™ III Adaptive Cable Equalizer Data Sheet 42216 - 3 January 2009
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Revision History
Version
3
ECR
151331
PCN
–
Date
January 2009
Changes and/or Modifications
Added 2500pc reel size to 6.6 Ordering Information. Changed the Output Voltage Swing from 550mVp-p to 600mVp-p in Table 2-2: AC Electrical Characteristics. Added “0.3UI Maximum Output Jitter at 2.97Gb/s” to Features Section and Table 2-2: AC Electrical Characteristics. Changed cables lengths from 100 to 120 and 400 to 350 in Section 4. Detailed Description. Re-wrote Section 4.3 Programmable Maximum Cable Length Adjust (MCLADJ). Added Tape & Reel to 6.6 Ordering Information. Converted to Data Sheet. Converted to Preliminary Data Sheet. Removed ‘Proprietary and Confidential’ footer. Modified DC Electrical Characteristics and AC Electrical Characteristics table. Added section 6.4 Marking Diagram. New Document.
2
149719
–
April 2008
1 0
145131 144247
– –
May 2007 February 2007
A
143102
–
December 2006
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Contents
Features.................................................................................................................................................................1 Applications.........................................................................................................................................................1 Description...........................................................................................................................................................1 Revision History .................................................................................................................................................2 1. Pin Out...............................................................................................................................................................4 1.1 GS2974A Pin Assignment ..............................................................................................................4 1.2 GS2974A Pin Descriptions .............................................................................................................4 2. Electrical Characteristics ............................................................................................................................6 2.1 Absolute Maximum Ratings ..........................................................................................................6 2.2 DC Electrical Characteristics ........................................................................................................6 2.3 AC Electrical Characteristics ........................................................................................................7 Test Circuit ...........................................................................................................................................................8 3. Input/Output Circuits ..................................................................................................................................8 4. Detailed Description.....................................................................................................................................9 4.1 Serial Digital Inputs .........................................................................................................................9 4.2 Cable Equalization ........................................................................................................................ 10 4.3 Programmable Maximum Cable Length Adjust (MCLADJ) ............................................. 10 4.4 Mute and Carrier Detect .............................................................................................................. 11 5. Application Information .......................................................................................................................... 12 5.1 PCB Layout ....................................................................................................................................... 12 5.2 Typical Application Circuit ........................................................................................................ 12 6. Package & Ordering Information .......................................................................................................... 13 6.1 Package Dimensions ..................................................................................................................... 13 6.2 Packaging Data ............................................................................................................................... 13 6.3 Recommended PCB Footprint ................................................................................................... 14 6.4 Marking Diagram ........................................................................................................................... 14 6.5 Solder Reflow Profiles .................................................................................................................. 15 6.6 Ordering Information ................................................................................................................... 15
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1. Pin Out
1.1 GS2974A Pin Assignment
VCC_A MUTE VCC_D 13 12 VEE_D 11 GS2974A (top view) SDI 3 10 SDO CD 15
16 VEE_A 1
14
SDI
2
SDO
VEE_A
4 5 AGC 6 AGC 7 BYPASS 8 MCLADJ
9
VEE_D
Center Pad (bottom of package, internally bonded to VEE_A)
Figure 1-1: 16-Pin QFN
1.2 GS2974A Pin Descriptions
Table 1-1: GS2974A Pin Descriptions
Pin Number
1, 4
Name
VEE_A
Timing
Analog
Type
Power
Description
Most negative power supply for analog circuitry. Connect to GND.
2, 3 5, 6
SDI, SDI AGC, AGC
Analog Analog
Input –
Serial digital differential input. External AGC capacitor. Connect pin 5 and pin 6 together as shown in the Typical Application Circuit on page 12.
7
BYPASS
Not Synchronous Analog
Input
Forces the Equalizing and DC RESTORE stages into bypass mode when HIGH. No equalization occurs in this mode. Maximum cable length adjust. Adjusts the approximate maximum amount of cable to be equalized. See Section 4.3. and Section 4.4
8
MCLADJ
Input
9
VEE_D
Analog
Power
Most negative power supply for the digital circuitry and output buffer. Connect to GND.
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Table 1-1: GS2974A Pin Descriptions (Continued)
Pin Number
10, 11 12
Name
SDO, SDO VEE_D
Timing
Analog Analog
Type
Output Power
Description
Equalized serial digital differential output. Most negative power supply for the digital circuitry and output buffer. Connect to GND.
13
VCC_D
Analog
Power
Most positive power supply for the digital I/O pins of the device. Connect to +3.3V DC.
14
MUTE
Not Synchronous
Input
CONTROL SIGNAL INPUT levels are LVCMOS/LVTTL compatible. (3.3V Tolerant) Controls output behaviour on SDO and SDO See Section 4.4.
15
CD
Not Synchronous
Output
STATUS SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Indicates the presence of a good input signal. See Section 4.4.
16
VCC_A
Analog
Power
Most positive power supply for the analog circuitry of the device. Connect to +3.3V DC.
–
Center Pad
–
Power
Internally bonded to VEE_A.
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2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Parameter
Supply Voltage Input ESD Voltage Storage Temperature Range Input Voltage Range (any input) Operating Temperature Range Solder Reflow Temperature
Value
-0.3V to +3.6 VDC 2kV -50°C < Ts < 125°C -0.3 to (VCC +0.3)V 0°C to 70°C 260°C
2.2 DC Electrical Characteristics
Table 2-1: DC Electrical Characteristics
VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown
Parameter
Supply Voltage Power Consumption Supply Current Output Common Mode Voltage Input Common Mode Voltage MCLADJ DC Voltage (to mute signal) MCLADJ Range CD Output Voltage
Symbol
VCC PD Is VCMOUT VCMIN –
Conditions
– TA = 25°C TA = 25°C TA = 25°C TA = 25°C 0m, TA = 25°C TA = 25°C Carrier not present Carrier present Min to Mute
Min
3.135 – – –
Typ
3.3 215 65 VCC - ΔVSDO/2 1.75 3.2
Max
3.465 343 98 –
Units
V mW mA V
Notes
±5% – – –
– –
– –
V V
– –
– VCD(OH) VCD(OL)
– 2.4
0.5 –
– –
V V
– –
– 2.0
– –
0.4 –
V V
– –
Mute Input Voltage Required to Force Outputs to Mute Mute Input Voltage Required to Force Outputs Active
VMute VMute
Max to Activate
–
–
0.8
V
–
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2.3 AC Electrical Characteristics
Table 2-2: AC Electrical Characteristics
VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown
Parameter
Serial input data rate Input Voltage Swing
Symbol
DRSDO ΔVSDI
Conditions
– TA =25°C, differential, 270Mb/s and 1.485Gb/s TA =25°C, differential, 2.97Gb/s
Min
143 720
Typ
– 800
Max
2970 950
Units
Mb/s mVp-p mVp-p mVp-p UI
Notes
– 1
720
800
880
1
Output Voltage Swing
ΔVSDO –
100Ω load, TA =25°C, differential 270Mb/s Belden 1694A: 0-300m 270Mb/s Belden 1694A: 300-350m 1.485Gb/s Belden 1694A: 0-140m 1.485Gb/s Belden 1694A: 140-200m 2.97Gb/s Belden 1694A: 0-70m 2.97Gb/s Belden 1694A: 70-120m 20% - 80% – – – – single ended single ended single ended
600
750
1050
–
Output Jitter of Various Cable Lengths and Data Rates
–
–
0.2
2,5
–
–
0.2
–
UI
4,5
–
–
0.25
UI
2,5
–
–
0.3
–
UI
4,5
–
–
–
0.3
UI
2,5
–
–
0.3
–
UI
4,5
Output Rise/Fall time Mismatch in rise/fall time Duty cycle distortion Overshoot Input Return Loss Input Resistance Input Capacitance Output Resistance NOTES:
– – – – – – – –
40 – – – 15 – – –
80 – – – 21 1.52 1 50
220 30 30 10 – – – –
ps ps ps % dB kΩ pF Ω
– – – – 3 – – –
1. 0m cable length. 2. All parts were production tested. In order to guarantee jitter over the full range of specification (VCC = 3.3V ±5%, TA = 0°C to 70°C, and 720-880mV launch swing from the SDI cable driver) the recommended applications circuit must be used. 3. Tested on CB2974A board from 5MHz to 3GHz. 4. Based on characterization data using the recommended applications circuit, at VCC = 3.3V, TA = 25°C and 800mV launch swing from the SDI cable driver 5. Equalizer Pathological test signal was used.
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Test Circuit
BERT Pattern Generator EXT. CLOCK CLOCK OUT DATA OUT 50/75
1694A CABLE
IN GS2974A TEST BOARD
OUT OUT
CH. 1 CH. 2 TDS 820 EXT. TRIGGER
EXT. CLOCK 2.97GHz/1.485GHz/ 270MHz
Figure 2-1: Test Circuit
3. Input/Output Circuits
VCC 3k SDI RC 3.6k 3.6k MCLADJ + 3k SDI 12.2k
150µ
Figure 3-1: Input Equivalent Circuit Figure 3-2: MCLADJ Equivalent Circuit
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50
50
SDO
SDO
Figure 3-3: Output Circuit
MUTE, BYPASS
CD
Figure 3-4: MUTE and BYPASS Circuits
Figure 3-5: CD Circuit
4. Detailed Description
The GS2974A is a high speed BiCMOS IC designed to equalize serial digital signals. The GS2974A can equalize both HD and SD serial digital signals, and will typically equalize 120m of Belden 1694A cable at 2.97Gb/s, 200m at 1.485Gb/s and 350m at 270Mb/s.The GS2974A is powered from a single +3.3V power supply and consumes approximately 215mW of power.
4.1 Serial Digital Inputs
The serial data signal may be connected to the input pins (SDI/SDI) in either a differential or single-ended configuration. AC-coupling of the inputs is recommended, as the SDI and SDI inputs are internally biased at approximately 1.8V.
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4.2 Cable Equalization
The input signal passes through a variable gain equalizing stage whose frequency response closely matches the inverse of the cable loss characteristic. In addition, the variation of the frequency response with control voltage imitates the variation of the inverse cable loss characteristic with cable length. The edge energy of the equalized signal is monitored by a detector circuit which produces an error signal corresponding to the difference between the desired edge energy and the actual edge energy. This error signal is integrated by both an internal and an external AGC filter capacitor providing a steady control voltage for the gain stage. As the frequency response of the gain stage is automatically varied by the application of negative feedback, the edge energy of the equalized signal is kept at a constant level which is representative of the original edge energy at the transmitter. The equalized signal is also DC restored, effectively restoring the logic threshold of the equalized signal to its correct level independent of shifts due to AC coupling. The digital output signals have a nominal voltage of 750mVpp differential, or 375mVpp single ended when terminated with 50Ω as shown in Figure 4-1.
+187.5mV VCM = 2.925V typical SDO -187.5mV
SDO 50 50
+187.5mV VCM = 2.925V typical -187.5mV
Figure 4-1: Typical Output Voltage Levels
4.3 Programmable Maximum Cable Length Adjust (MCLADJ)
For SMPTE 259M inputs, the GS2974A incorporates a programmable Maximum Cable Length Adjust (MCLADJ) threshold. This feature can be useful in applications where there are multiple input channels using the GS2974A and the maximum gain can be limited to avoid crosstalk. The MCLADJ pin acts to change the threshold of the Carrier Detect (CD) pin. When the input signal drops below a certain threshold, the CD pin will be driven high, indicating that there is not a valid input signal. In order to enable automatic muting of the output of the GS2974A, the CD pin should be connected directly to the MUTE pin. In applications where programmable maximum cable length adjust is not required, the MCLADJ pin may be left unconnected. This feature has been designed for use in applications such as routers, where signal crosstalk and circuit noise cause the Equalizer to output erroneous data when no input signal is present. The use of a Carrier Detect function with a fixed internal reference
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does not solve this problem, since the signal to noise ratio on the circuit board could be significantly less than the default signal detection level set by the on chip reference. NOTE: MCLADJ is only recommended for data rates up to 360Mb/s. For data rates above this, MCLADJ should be left floating.
4.4 Mute and Carrier Detect
The GS2974A includes a MUTE input pin that allows the application interface to mute the serial digital output at any time. Set the MUTE pin HIGH to mute SDO and SDO. In this case, the outputs will mute regardless of the setting of the BYPASS pin. A Carrier Detect output pin (CD) indicates the presence of a valid signal at the input of the GS2974A. When CD is LOW, the device has detected a valid input on SDI and SDI. When CD is HIGH, the device has not detected a valid input. NOTE: This pin may be connected directly to the CD pin to allow mute on loss of carrier. NOTE: CD will only detect loss of carrier for data rates greater than 19Mb/s. The CD output pin may be connected directly to the MUTE input pin to enable automatic muting of the GS2974A when no valid input signal has been detected. NOTE: If the maximum cable length is exceeded and the device is not in bypass mode the GS2974A will not assert the CD pin even if a carrier is present. Table 4-1: Mute Input Table
Mute
0 1
Function
SDO and SDO operate normally SDO and SDO are forced to a steady state
Table 4-2: CD Output Table
CD
0 1
Input Status
Valid Input on SDI, SDI pins Input is not valid
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5. Application Information
5.1 PCB Layout
Special attention must be paid to component layout when designing serial digital interfaces for HDTV. An FR-4 dielectric can be used, however, controlled impedance transmission lines are required for PCB traces longer than approximately 1cm. Note the following PCB artwork features used to optimize performance: • • • • PCB trace width for HD rate signals is closely matched to SMT component width to minimize reflections due to change in trace impedance. The PCB ground plane is removed under the GS2974A input components to minimize parasitic capacitance. The PCB ground plane is removed under the GS2974A output components to minimize parasitic capacitance. High speed traces are curved to minimize impedance changes.
5.2 Typical Application Circuit
CD MUTE VCC VCC
16 SDI 10n 6.2n* 1 VEE_A 1u 75 1u 3 SDI 2 SDI
15
14
13
MUTE
VCC_D
VCC_A
CD
10n VEE_D 12 + 4u7
SDO
SDO GS2974A SDO
11
10
+
SDO 4u7
MCLADJ
AGC
AGC
75
37R4
BYPASS
4
VEE_A
VEE_D
9
5 470n
6
7
8 MCLADJ
470n
BYPASS
NOTE: All resistors in Ohms, capacitors in Farads, and inductors in Henrys, unless otherwise noted. * Value dependent on layout
Figure 5-1: GS2974A Typical Application Circuit
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6. Package & Ordering Information
6.1 Package Dimensions
0.40+/-0.05
4.00+/-0.05
A
DATUM A
2.76+/-0.10
B
PIN 1 AREA
4.00+/-0.05
CENTER TAB
DETAIL B
2X 2X
0.15 C 0.15 C DATUM B 0.65 16X
0.20 REF
0.35+/-0.05 0.10 CAB 0.05 C
C
0.10 C 16X 0.08 C SEATING PLANE
0.85+/-0.05 0.00-0.05
DATUM A OR B
0.65/2 TERMINAL TIP 0.65 DETAIL B SCALE:NTS
6.2 Packaging Data
Parameter
Package Type Package Drawing Reference Moisture Sensitivity Level Junction to Case Thermal Resistance, θj-c Junction to Air Thermal Resistance, θj-a (at zero airflow) Psi, ψ Pb-free and RoHS compliant
Value
4mm x 4mm 16-pin QFN JEDEC M0220 3 31.0°C/W 43.8°C/W 11.0°C/W Yes
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2.76+/-0.10
6.3 Recommended PCB Footprint
0.35 0.65
0.55
3.70
2.76
CENTER PAD
NOTE: All dimensions are in millimeters. 2.76 3.70
The Center Pad should be connected to the most negative power supply plane for analog circuitry in the device (VEE_A) by a minimum of five vias. NOTE: Suggested dimensions only. Final dimensions should conform to customer design rules and process optimizations.
6.4 Marking Diagram
Pin 1 ID
GS2974A XXXXE3 YYWW
XXXX - Lot/Work Order ID YYWW - Date Code
YY - 2-digit year WW - 2-digit week number
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6.5 Solder Reflow Profiles
The device is manufactured with Matte-Sn terminations and is compatible with both standard eutectic and Pb-free solder reflow profiles. MSL qualification was performed using the maximum Pb-free reflow profile shown in Figure 6-1. The recommended standard Pb reflow profile is shown in Figure 6-2.
Temperature 6 0-150 se c . 20-40 se c . 2 6 0°C 250°C 3 °C/se c m ax 217°C 6 °C/se c m ax
200°C
150°C
25°C
Time 6 0-180 se c . max 8 min. max
Figure 6-1: Maximum Pb-free Solder Reflow Profile (Preferred)
Temperature
6 0-150 se c . 10-20 se c .
230°C 220°C 3 °C/se c m ax 183°C 6 °C/se c m ax 150°C
100°C
25°C Time 120 se c . max 6 m in. max
Figure 6-2: Standard Pb Solder Reflow Profile
6.6 Ordering Information
Part Number
GS2974A GS2974A GS2974ACNE3 GS2974ACTE3
Package
16-pin QFN 16-pin QFN Tape & Reel (250pcs) 16-pin QFN Tape & Reel (2,500pcs)
Temperature Range
0°C to 70°C 0°C to 70°C
GS2974A
GS2974ACNTE3Z
0°C to 70°C
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DOCUMENT IDENTIFICATION
CAUTION
ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
DATA SHEET
The product is in production. Gennum reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible.
GENNUM CORPORATION
Mailing Address: P.O. Box 489, Station A, Burlington, Ontario L7R 3Y3 Canada Street Addresses: 4281 Harvester Road, Burlington, Ontario L7L 5M4 Canada Phone: +1 (905) 632-2996 Email: corporate@gennum.com Fax: +1 (905) 632-2055 www.gennum.com
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Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. All other trademarks mentioned are the properties of their respective owners. GENNUM and the Gennum logo are registered trademarks of Gennum Corporation. © Copyright 2006 Gennum Corporation. All rights reserved. Printed in Canada. www.gennum.com
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