GS2985 Multi-Rate SDI Reclocker with Equalization & De-emphasis
Features
Description
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•
•
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The GS2985 is a multi-rate serial digital reclocker designed to
automatically recover the embedded clock from a digital video
signal and retime the incoming video data. It will recover the
embedded clock signal and retime the data from a SMPTE 424M,
SMPTE 292M, or SMPTE 259M-C compliant digital video signal.
•
•
•
•
•
•
•
SMPTE 424M, SMPTE 292M and SMPTE 259M-C compliant
Supports DVB-ASI at 270Mb/s
Single supply operation at 3.3V or 2.5V
180mW typical power consumption (210mW with RCO
enabled) at 2.5V
Input signal equalization and output-signal de-emphasis
settings to compensate for board-trace dielectric losses
4:1 input multiplexer patented technology
Choice of dual reclocked data outputs or one reclocked data
output and one clock output
Uses standard 27MHz crystal
Cascadable crystal buffer supports multiple reclockers using
a single crystal
Differential inputs and outputs
support DC coupling to industry-standard differential
logic
on-chip 100Ω differential data input/output termination
selectable 400mVppd or 800mVppd output swing on
each output
seamless interface to other Gennum products
4 wire SPI host interface for device configuration and
monitoring
•
Standard logic control and status signal levels
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•
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•
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Auto and Manual modes for rate selection
Standards indication in Auto mode
Lock Detect Output
Mute, Bypass and Autobypass functions
SD/HD indication output to control GS2978 or GS2988 dual
slew-rate cable drivers
Operating temperature range: -40°C to +85°C
Small footprint QFN package (9mm x 9mm)
Package-compatible with GS2975A
Pb-free and RoHS compliant
•
•
•
A serial host interface provides the ability to configure and
monitor multiple GS2985 devices in a daisy-chain configuration.
Adjustable input trace equalization (EQ) for up to 40” of FR4 trace
losses, and adjustable output de-emphasis (DE) for up to 20” of
FR4 trace losses, can be configured via the host interface.
The GS2985 can operate in either auto or manual rate selection
mode. In Auto mode, the device will automatically detect and lock
onto incoming SMPTE SDI data signals at any supported rate. For
single rate data systems, the GS2985 can be configured to operate
in Manual mode. In both modes, the device requires only one
external crystal to set the VCO frequency when not locked and
provides adjustment free operation.
The GS2985 accepts industry-standard differential input levels
including LVPECL and CML. The differential data and clock
outputs feature selectable output swing via the host interface,
ensuring compatibility with most industry-standard, terminated
differential receivers.
The GS2985 features dual differential outputs. The second output
can be configured to emit either the recovered clock signal or the
re-timed video data. This output can also be disabled to save
power.
In systems which require passing of non-SMPTE data rates, the
GS2985 can be configured to either automatically or manually
enter a bypass mode in order to pass the signal without reclocking.
The GS2985 is Pb-free, and the encapsulation compound does not
contain halogenated flame retardant. This component and all
homogeneous sub-components are RoHS compliant.
Applications
•
SMPTE 424M, SMPTE 292M and SMPTE 259M-C coaxial
cable serial digital interfaces
GS2985 Multi-Rate SDI Reclocker with Equalization &
De-emphasis
Data Sheet
36663 - 2
March 2010
www.gennum.com
1 of 44
XTAL-
CP_CAP
XTAL_BUF_OUT
XTAL+
XTAL
OSC
LF+ KBB
Buffer
LDO
DDO0
Data
Buffer
Retimer
DDO0
Phase
Frequency
Detector
DDI0
DDI0
Charge
Pump
Equalizer/
Data Mux
DDO1/RCO
Clock/
Data
Buffer
VCO
DDI1
DDI1
DE0_EN
DE1_EN
DDO1/RCO
Phase
Detector
DDI2
DDI2
Selectable
Divide
DDI3
DDI3
Selectable
Divide
LOS
Detect
LDO
Control
SDO/EQ1_EN
SCK/EQ2_EN
CS/EQ3_EN
HIF
LOS
SDI/EQ0_EN
DDI_SEL[1:0]
1.8V
SPI
SS[1:0]
AUTO/MAN
LOCKED
BYPASS
SD/HD
DATA/CLOCK
AUTOBYPASS
DDO1_DISABLE
DATA_MUTE
VDD_1p8
GS2985 Functional Block Diagram
Revision History
Version
ECR
PCN
Date
Changes and/or Modifications
2
153705
–
March 2010
Converted to Data Sheet. Updated
Power numbers in Table 2-1: DC
Electrical Characteristics. Added Table
4-5: Suggested LOS Threshold Settings.
1
152592
–
September
2009
Updates to Section 4.15 Host Interface.
0
152329
–
July 2009
Converted document to Preliminary
Data Sheet.
D
152240
–
July 2009
Added Figure 4-2: De-emphasis
Waveform.
C
152042
–
June 2009
Removed ‘Proprietary & Confidential”
from document.
B
151967
–
May 2009
Added Section 4.15 Host Interface.
A
151318
–
April 2009
New document.
GS2985 Multi-Rate SDI Reclocker with Equalization &
De-emphasis
Data Sheet
36663 - 2
March 2010
2 of 44
Contents
Features.................................................................................................................................................................1
Applications.........................................................................................................................................................1
Description...........................................................................................................................................................1
Revision History .................................................................................................................................................2
1. Pin Out...............................................................................................................................................................5
1.1 Pin Assignment ..................................................................................................................................5
1.2 Pin Descriptions ................................................................................................................................6
2. Electrical Characteristics ............................................................................................................................9
2.1 Absolute Maximum Ratings ..........................................................................................................9
2.2 DC Electrical Characteristics ........................................................................................................9
2.3 AC Electrical Characteristics ..................................................................................................... 10
3. Input/Output Circuits ............................................................................................................................... 13
4. Detailed Description.................................................................................................................................. 18
4.1 Serial Data Input ............................................................................................................................ 18
4.2 Modes of Operation ...................................................................................................................... 18
4.3 Input Trace Equalization ............................................................................................................. 18
4.4 4:1 Input Mux .................................................................................................................................. 19
4.5 Crystal Buffer .................................................................................................................................. 20
4.6 LOS (Loss Of Signal) Detection .................................................................................................. 20
4.7 Serial Digital Reclocker ............................................................................................................... 21
4.8 Lock Detection ................................................................................................................................ 21
4.8.1 Lock Detect and Asynchronous Lock ......................................................................... 22
4.9 Serial Data Output ......................................................................................................................... 22
4.9.1 Output Signal Interface Levels...................................................................................... 22
4.9.2 Adjustable Output Swing................................................................................................ 22
4.9.3 Output De-emphasis ........................................................................................................ 22
4.10 Automatic and Manual Data Rate Selection ...................................................................... 23
4.11 SD/HD Indication ........................................................................................................................ 24
4.12 Bypass Mode ................................................................................................................................. 25
4.13 DVB-ASI ......................................................................................................................................... 25
4.14 Output Mute and Data/Clock Output Selection ............................................................... 25
4.15 Host Interface ............................................................................................................................... 26
4.15.1 Introduction ...................................................................................................................... 26
4.15.2 Legacy Mode & Start-up................................................................................................ 26
4.15.3 Host Interface Mode & Start-up.................................................................................. 26
4.15.4 Clock & Data Timing....................................................................................................... 27
4.15.5 Single Device Operation............................................................................................... 27
4.15.6 Write Operation - Single Device ................................................................................ 28
4.15.7 Read Operation - Single Device ................................................................................. 28
4.15.8 Daisy Chain Operation.................................................................................................. 31
4.15.9 Read & Write Operation - Daisy Chained Devices .............................................. 32
4.15.10 Writing to all Devices .................................................................................................. 32
GS2985 Multi-Rate SDI Reclocker with Equalization &
De-emphasis
Data Sheet
36663 - 2
March 2010
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4.15.11 Writing to a Single Device in the Chain ................................................................ 33
4.15.12 Reading from all Devices ........................................................................................... 33
4.15.13 Reading from a Single Device in the Chain.......................................................... 34
4.15.14 Host Register Map......................................................................................................... 35
4.16 Device Power-up ......................................................................................................................... 39
4.17 Standby ........................................................................................................................................... 39
5. Typical Application Circuit ..................................................................................................................... 40
6. Package and Ordering Information...................................................................................................... 41
6.1 Package Dimensions ..................................................................................................................... 41
6.2 Recommended PCB Footprint ................................................................................................... 42
6.3 Packaging Data ............................................................................................................................... 42
6.4 Marking Diagram ........................................................................................................................... 43
6.5 Solder Reflow Profile .................................................................................................................... 43
6.6 Ordering Information ................................................................................................................... 44
GS2985 Multi-Rate SDI Reclocker with Equalization &
De-emphasis
Data Sheet
36663 - 2
March 2010
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1. Pin Out
53
52
51
GND
54
N/C
55
XTAL_BUF_OUT
56
XTAL+
57
CS/EQ3_EN
SDI/EQ0_EN
58
N/C
59
XTAL-
60
SCK/EQ2_EN
61
SDO/EQ1_EN
62
N/C
63
VEE_CP
LF+
64
VCC_CP
N/C
CP_CAP
1.1 Pin Assignment
50
49
DDI0
1
48
VEE_DDO0
HIF
2
47
VCC_DDO0
DDI0
3
46
DDO0
DE0_EN
GND
4
45
DDI1
5
44
DDO0
N/C
6
43
GND_DRV
DDI1
7
GND
8
GS2985
64-pin QFN
(top view)
42
VEE_DDO1
41
VCC_DDO1
DDI2
9
40
DDO1/RCO
N/C
10
39
DE1_EN
DDI2
11
38
DDO1/RCO
GND
12
37
DATA/CLOCK
23
24
25
26
27
28
29
30
31
32
GND
22
VSS_DIG
21
LOS
20
VDD_DIG
19
LOCKED
Ground Pad
(bottom of package)
18
VDD_1P8
SD/HD
17
SS1
33
SS0
16
N/C
KBB
GND
VEE_VCO
34
VCC_VCO
15
AUTO/MAN
DDO1_DISABLE
DDI3
BYPASS
DATA_MUTE
35
AUTOBYPASS
36
14
DDI_SEL1
13
DDI_SEL0
DDI3
RSVD
Figure 1-1: GS2985 Pin Out
GS2985 Multi-Rate SDI Reclocker with Equalization &
De-emphasis
Data Sheet
36663 - 2
March 2010
5 of 44
1.2 Pin Descriptions
Table 1-1: GS2985 Pin Descriptions
Pin Number
Name
Type
Description
1, 3
DDI0, DDI0
Input
2
HIF
Logic Input
4, 8, 12, 16, 32,
49
GND
Power
Connect to GND.
5, 7
DDI1, DDI1
Input
Serial Digital Differential Input 1.
6, 10, 24, 50, 54,
59, 64
N/C
No Connect
9, 11
DDI2, DDI2
Input
Serial Digital Differential Input 2.
13, 15
DDI3, DDI3
Input
Serial Digital Differential Input 3.
14
RSVD
Reserved
17, 18
DDI_SEL[0:1]
Logic Input
Selects one of four serial digital input signals for processing. See
Section 4.4.
19
BYPASS
Logic Input
Bypasses the reclocker stage. See Section 4.12.
20
AUTOBYPASS
Logic Input
When HIGH, this pin automatically bypasses the reclocker stage when the
PLL is not locked to a supported rate. See Section 4.12.
21
AUTO/MAN
Logic Input
When set HIGH, the standard is automatically detected from the input
data rate.
22
VCC_VCO
Power
Most positive power supply connection for the internal
VCO section. Connect to a 3.3V supply with a 422Ω resistor, or to a 2.5V
supply with a 267Ω resistor.
23
VEE_VCO
Power
Most negative power supply connection for the internal
VCO section. Connect to GND.
25, 26
SS0, SS1
Bi-directional
Serial Digital Differential Input 0.
Host interface selection pin. Active-low input. See Section 4.15.14.
Do not connect.
Reserved pin. Do not connect to this pin.
When AUTO/MAN is HIGH, SS[1:0] are outputs displaying the data rate to
which the PLL has locked to.
When AUTO/MAN is LOW, SS[1:0] are inputs forcing the PLL to lock only to
the selected data rate.
See Table 4-8 from Section 4.10.
27
VDD_1P8
Power
External capacitor for internal 1.8V digital supply.
28
LOCKED
Output
Lock Detect status signal. HIGH when the PLL is locked.
29
LOS
Output
Loss Of Signal status. HIGH when the input signal is invalid.
30
VDD_DIG
Power
Most positive power supply connection for the digital core.
Connect to 3.3V or 2.5V.
31
VSS_DIG
Power
Most negative power supply for the digital core.
Connect to GND.
GS2985 Multi-Rate SDI Reclocker with Equalization &
De-emphasis
Data Sheet
36663 - 2
March 2010
6 of 44
Table 1-1: GS2985 Pin Descriptions
Pin Number
Name
Type
Description
33
SD/HD
Output
34
KBB
Analog Input
35
DDO1_DISABLE
Logic Input
Disables the DDO1/RCO and DDO1/RCO outputs
when LOW.
See Section 4.14.
36
DATA_MUTE
Logic Input
Mutes the DDO0/DDO0 and DDO1/DDO1 (if data is selected) outputs when
LOW.
Set HIGH for normal operation.
37
DATA/CLOCK
Logic Input
DATA/CLOCK select.
See Section 4.14.
38, 40
DDO1/RCO,
DDO1/RCO
Output
39
DE1_EN
Logic Input
This signal will be LOW for all rates other than 270Mb/s.
This signal is HIGH for 270Mb/s.
Controls the loop bandwidth of the PLL. Leave this pin
floating for serial reclocking applications.
Differential serial clock or data outputs.
De-emphasis on/off pin for serial digital output 1.
HIGH = de-emphasis on
LOW = de-emphasis off
41
VCC_DDO1
Power
Most positive power supply connection for the DDO1/DDO1 output driver.
Connect to 3.3V or 2.5V.
42
VEE_DDO1
Power
Most negative power supply connection for the DDO1/DDO1 output
driver. Connect to GND.
43
GND_DRV
Power
Connect to GND.
44, 46
DDO0, DDO0
Output
Differential Serial Digital Outputs.
45
DE0_EN
Logic Input
De-emphasis on/off pin for serial digital output 0.
HIGH = de-emphasis on
LOW = de-emphasis off
47
VCC_DDO0
Power
Most positive power supply connection for the DDO0/DDO0 output driver.
Connect to 3.3V or 2.5V.
48
VEE_DDO0
Power
Most negative power supply connection for the DDO0/DDO0 output
driver.
Connect to GND.
51
XTAL_BUF_OUT
Output
Buffered output of the reference oscillator.
52
XTAL+
Output
Reference crystal output.
53
XTAL-
Input
55
CS/EQ3_EN
Input/Logic
Input
Reference crystal input.
In host mode (HIF set LOW):
Chip select input for SPI serial host interface. Active-low input.
In non-host mode (HIF set HIGH):
Trace equalization on/off pin for Serial Digital Differential Input 3.
Active-high input.
GS2985 Multi-Rate SDI Reclocker with Equalization &
De-emphasis
Data Sheet
36663 - 2
March 2010
7 of 44
Table 1-1: GS2985 Pin Descriptions
Pin Number
Name
Type
56
SCK/EQ2_EN
Input/Logic
Input
Description
In host mode (HIF set LOW):
Burst-mode clock input for SPI serial host interface.
In non-host mode (HIF set HIGH):
Trace equalization on/off pin for Serial Digital Differential Input 2.
Active-high input.
57
SDO/EQ1_EN
Input/Logic
Input
In host mode (HIF set LOW):
Serial digital data output for SPI serial host interface. Active-high output.
In non-host mode (HIF set HIGH):
Trace equalization on/off pin for Serial Digital Differential Input 1.
Active-high input.
58
SDI/EQ0_EN
Input/Logic
Input
In host mode (HIF set LOW):
Serial digital data input for SPI serial host interface. Active-high input.
In non-host mode (HIF set HIGH):
Trace equalization on/off pin for Serial Digital Differential Input 0.
Active-high input.
60
VEE_CP
Power
Most negative power supply connection for the internal
charge pump. Connect to GND.
61
VCC_CP
Power
Most positive power supply connection for the internal charge pump.
Connect to 3.3V or 2.5V
62
LF+
Passive
Loop Filter capacitor connection. (CLF = 47nF). Connect as shown in Typical
Application Circuit on page 40.
63
CP_CAP
Power
External capacitor for internal LDO regulator supplying the charge pump
circuit.
−
Center Pad
−
GS2985 Multi-Rate SDI Reclocker with Equalization &
De-emphasis
Data Sheet
36663 - 2
March 2010
Ground pad on bottom of package. Connect to GND.
8 of 44
2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Parameter
Value
Supply Voltage
-0.5 to +3.6VDC
Input ESD Voltage
4kV
Storage Temperature Range
-50ºC < TA < 125ºC
Operating Temperature Range
-40ºC to 85ºC
Input Voltage Range
-0.3 to (VCC + 0.3) VDC
Solder Reflow Temperature
260ºC
2.2 DC Electrical Characteristics
Table 2-1: DC Electrical Characteristics
Parameter
Min
Typ
Max
Units
3.3V
3.135
3.3
3.465
V
2.5V
2.375
2.5
2.625
V
VDD = 3.3V
−
250
325
mW
VDD = 2.5V
−
180
235
mW
Power (DDO1/RCO enabled, minimum
output swing)
VDD = 3.3V
−
290
390
mW
VDD = 2.5V
−
210
275
mW
Power in Power-down mode
VDD = 3.3V
−
48
60
mW
VDD = 2.5V
−
30
40
mW
Supply Voltage
Power (DDO1/RCO disabled, minimum
output swing)
Symbol
VDD
P
Conditions
Serial Input Termination
−
Differential
80
100
120
Ω
Serial Output Termination
−
Differential
80
100
120
Ω
Serial Input Common Mode Voltage
−
−
1.6
−
VDD
V
Serial Output Common Mode Voltage
−
−
−
VCC(ΔVOD
/2)
−
V
VIL (2.5V operation)
−
VOUT≤VOL, max
-0.3
−
0.7
V
VOUT≤VOL, max
-0.3
−
0.8
V
VIL (3.3V operation)
GS2985 Multi-Rate SDI Reclocker with Equalization &
De-emphasis
Data Sheet
36663 - 2
March 2010
9 of 44
Table 2-1: DC Electrical Characteristics (Continued)
Parameter
Symbol
Conditions
−
VIH (2.5V operation)
VIH (3.3V operation)
Min
Typ
Max
Units
VOUT≥VOH, min
1.7
−
VDD
+0.3
V
VOUT≥VOH, min
2
−
VDD
+0.3
V
IIN
−
VIN = 0V or VIN = VDD
−
+/-10
+/-20
μA
VOL (2.5V operation)
−
VDD = min, IOL = 100μA
−
−
0.4
V
VDD = min, IOL = 100μA
−
−
0.4
V
VDD = min, IOH = -100μA
2.1
−
−
V
VDD = min, IOH = -100μA
VDD
-0.4
−
−
V
2.5V operation
−
350
−
mV
3.3V operation
−
420
−
mV
VOL (3.3V operation)
−
VOH (2.5V operation)
VOH (3.3V operation)
−
Hysteresis Voltage (SPI inputs)
2.3 AC Electrical Characteristics
Table 2-2: AC Electrical Characteristics
Parameter
Serial Input Data Rate
(for reclocking)
Symbol
DRSDO
Serial Input Data Rate
(bypass)
Conditions
Min
Typ
Max
Units
Notes
−
0.27
−
2.97
Gb/s
−
−
DC
−
2.97
Gb/s
−
−
−
−
10
MHz
−
2000
mVp-pd
−
SPI Operating Speed
−
Input Voltage Swing
ΔVSDI
set ATTEN_EN = 1 for
ΔVSDI>1Vpp
100
Output Voltage Swing
ΔVOD
default
300
400
500
mVp-pd
−
see DRIVER_1 register
(0x01) addresses 8 & 9 in
4.15.14 Host Register
Map.
600
800
1000
mVp-pd
−
LOW
Recommended setting for 0 to 10
inches of FR4
−
MED
Recommended setting for 10 to 20
inches of FR4
−
HIGH
Recommended setting for >20 inches
of FR4
−
Input Trace Equalization
−
GS2985 Multi-Rate SDI Reclocker with Equalization &
De-emphasis
Data Sheet
36663 - 2
March 2010
10 of 44
Table 2-2: AC Electrical Characteristics (Continued)
Parameter
Output De-Emphasis
Symbol
−
Input Jitter Tolerance
Loop Bandwidth
Conditions
Min
Typ
Max
Units
Notes
OFF - 0
−
0
−
dB
−
ON - 0
−
0
−
dB
−
ON - 1
−
0.7
−
dB
−
ON - 2
−
1.3
−
dB
−
ON - 3
−
2
−
dB
−
ON - 4
−
2.6
−
dB
−
ON - 5
−
3.3
−
dB
−
ON - 6
−
4
−
dB
−
ON - 7
−
4.7
−
dB
−
0.8
−
−
UI
−
KBB = VCC
−
170
−
kHz
−
KBB = FLOAT
−
340
−
kHz
−
KBB = GND
−
680
−
kHz
−
KBB = VCC
−
0.875
−
MHz
−
KBB = FLOAT
−
1.75
−
MHz
−
KBB = GND
−
3.5
−
MHz
−
KBB = VCC
−
1.75
−
MHz
−
KBB = FLOAT
−
3.5
−
MHz
−
KBB = GND
−
7.0
−
MHz
−
square-wave modulated
jitter
BWLOOP
(270Mb/s)
BWLOOP
(1485Mb/s)
BWLOOP
(2970Mb/s)
PLL Lock Time (asynchronous)
talock
−
−
0.5
1
ms
−
PLL Lock Time (synchronous)
tslock
CLF = 47nF, SD/HD = 0
−
0.5
4
μs
−
CLF = 47nF, SD/HD = 1
−
5
10
μs
−
KBB = FLOAT
−
0.01
0.02
UI
1
−
0.03
0.04
UI
1
−
0.05
0.08
UI
1
20% to 80% (400mV
swing)
−
65
90
ps
−
20% to 80% (800mV
swing)
−
80
110
ps
−
−
−
−
15
ps
−
Serial Data Output Jitter Intrinsic
(DDO0)
tOJ(270Mb/s)
PRN 2^23-1 test pattern
tOJ(1485Mb/s)
KBB = FLOAT
PRN 2^23-1 test pattern
tOJ(2970Mb/s)
KBB = FLOAT
PRN 2^23-1 test pattern
Output Rise/Fall Time
Output Rise/Fall Time Mismatch
tr/f
−
GS2985 Multi-Rate SDI Reclocker with Equalization &
De-emphasis
Data Sheet
36663 - 2
March 2010
11 of 44
Table 2-2: AC Electrical Characteristics (Continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Notes
Eye Cross Shift
−
percentage of signal
amplitude
−
−
5
%
−
Power Supply Noise Rejection
−
50 - 100Hz
−
100
−
mVp-p
−
100Hz - 10MHz
−
40
−
mVp-p
−
10MHz - 1.485GHz
−
10
−
mVp-p
−
Notes:
1. Accumulated jitter measured peak to peak differential over 1000 hits.
GS2985 Multi-Rate SDI Reclocker with Equalization &
De-emphasis
Data Sheet
36663 - 2
March 2010
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3. Input/Output Circuits
VCC
5.55kΩ
12.96kΩ
25Ω
VCC
25Ω
DDI
VCC
25Ω
25Ω
DDI
Figure 3-1: High-speed Inputs (DDI0, DDI0, DDI1, DDI1, DDI2, DDI2, DDI3, DDI3)
VCC
2.5µA
VCC
1.4kΩ
IN
VREF
Figure 3-2: Low-speed Input with weak internal pull-up (HIF, RSVD, AUTO/MAN,
DDO1_DISABLE, DATA_MUTE)
GS2985 Multi-Rate SDI Reclocker with Equalization &
De-emphasis
Data Sheet
36663 - 2
March 2010
13 of 44
VCC
VCC
1.4kΩ
IN
VREF
2.5µA
Figure 3-3: Low-speed Input with weak internal pull-down (DDI_SEL0,
DDI_SEL1, BYPASS, AUTOBYPASS, DE1_EN, DE0_EN)
VCC
VCC
1.4kΩ
VREF
VCC
SS0/SS1
VCC
Tgate
SS0/SS1
Auto/Man
Figure 3-4: Data Rate Control/Indicators (SS0, SS1)
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VCC
VCC
972Ω
OUT
Figure 3-5: Low-speed Outputs (LOCKED, LOS, HD/SD)
VCC
VCC
VCC
50Ω
50Ω
DDO
DDO
Figure 3-6: High-speed Outputs (DDO1/RCO, DDO1/RCO, DDO0, DDO0)
VCC
VREF 1
VCC
VCC
1.4kΩ
KBB
VCC
VREF 2
Figure 3-7: Loop Bandwidth Control (KBB)
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VCC
VCC
XTAL_BUFF_OUT
Figure 3-8: Crystal Buffered Output (XTAL_BUF_OUT)
VCC
VCC
EN
VCC
VCC
XTAL+
246Ω
XTALEN
Figure 3-9: High-speed Crystal Oscillator I/O (XTAL-, XTAL+)
VCC
IN
VCC
1kΩ
2.5µA
Figure 3-10: SPI Inputs/EQ Ctrl (CS/EQ3_EN, SCK/EQ2_EN, SDI/EQ0_EN)
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VCC
VCC
1.4kΩ
VREF
2.5µA
VCC
Tgate
SDO
SPI SDO
tri-state
Logic
Figure 3-11: SPI Output/EQ Control (SDO/EQ1_EN)
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4. Detailed Description
The GS2985 is a multi-standard reclocker for serial digital SDTV signals operating at 270Mb/s,
and HDTV signals operating at 1.485Gb/s, 1.485/1.001Gb/s, 2.97Gb/s and 2.97/1.001Gb/s.
4.1 Serial Data Input
The GS2985 features four differential input buffers.
The serial data input signal is connected to the DDI0/DDI0, DDI1/DDI1, DDI2/DDI2 and
DDI3/DDI3 input pins of the device.
Input signals can be single-ended or differential, DC or AC-coupled.
The input circuit is self-biasing, to allow for simple AC or DC-coupling of input signals to the
device.
The serial digital data inputs are also compatible when DC-coupled with LVPECL or CML
differential outputs from crosspoint switches which operate from 3.3V or 2.5V supplies. This
includes but is not limited to: GS2974A, GS2974B, and GS2984 equalizers.
4.2 Modes of Operation
The GS2985 has two modes of operation: Legacy Mode (HIF = HIGH) and SPI Mode (HIF = LOW).
In Legacy Mode, chip functions are controlled via pins only, and offers limited control of input
equalization and output de-emphasis.
In SPI mode, access is gained to additional EQ and DE settings as well as access to additional
features such as LOS adjustment, polarity invert, auto-mute, etc.
4.3 Input Trace Equalization
The GS2985 features adjustable trace equalization to compensate for PCB trace dielectric losses
at 1.5GHz.
The trace equalization has three peak-gain settings. The maximum peak gain value is optimized
for compensating the high-frequency losses associated with 25 inches of 5-mil stripline in FR4
material. For boards with different striplines or materials, users can experiment to find the EQ
setting which optimizes their system performance.
These settings are accessible via the serial host interface.
Each serial digital input; DDI, DDI includes a pin EQn_EN to turn its trace equalizer on or off.
When a pin EQn_EN is tied LOW or left unconnected, the trace equalization for input n is set to
the Low Range.
When an EQn_EN pin is tied HIGH, and input n is selected, the trace equalization for input n is
set to the Medium Range.
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Table 4-1: Input Trace Equalization Operation
EQn_EN Setting
Trace Equalization Range
LOW
Low
HIGH
Medium
The default peak-gain setting upon power-up is optimized for compensating the
high-frequency losses associated with approximately 10 inches of 5-mil stripline in FR4
material.
The EQn_EN pins are multiplexed with the serial host interface pins. The EQn_EN functionality
is enabled when pin HIF is tied HIGH, as shown in Table 4-2:
Table 4-2: EQn_EN Pins Multiplexed
Pin
Function
SDI/EQ0_EN
Active-high logic input to enable trace-equalization for high-speed input channel 0.
SDO/EQ1_EN
Active-high logic input to enable trace-equalization for high-speed input channel 1.
SCK/EQ2_EN
Active-high logic input to enable trace-equalization for high-speed input channel 2.
CS/EQ3_EN
Active-high logic input to enable trace-equalization for high-speed input channel 3.
4.4 4:1 Input Mux
The GS2985 incorporates a 4:1 input mux, which allows the connection of four independent
streams of video/data. There are four differential inputs (DDI[3:0] / DDI[3:0]). The active channel
can be selected via the DDI_SEL[1:0] pins as shown in Table 4-3.
Table 4-3: Input Selection Table
DDI_SEL[1:0]
Selected Input
00
DDI0
01
DDI1
10
DDI2
11
DDI3
The DDI_SEL pins include internal pull-downs, which pull the input voltage LOW if either pin
is unconnected. Active circuitry associated with the input buffers and trace EQ can only be
turned on for the selected input. Inputs which are not selected have their input buffers and trace
EQs turned OFF to save power. Unused inputs can be either left floating, or tied to VCC.
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4.5 Crystal Buffer
The GS2985 features a crystal buffer supporting a Gennum recommended external 27MHz
crystal. The GS2985 requires an external 27MHz reference clock for correct operation. This
reference clock is generated by connecting a crystal to the XTAL- and XTAL+ pins of the device.
Alternately, a 27MHz external clock source can be connected to the XTAL- pin of the device,
while the XTAL+ pin should be left floating.
4.6 LOS (Loss Of Signal) Detection
The LOS (Loss Of Signal) status pin is an active-high output that indicates when the serial digital
input signal selected at the 4:1 input mux is invalid. In order for this output to be asserted,
transitions must not be present for a period of tLA = 5 - 10μs. After this output has been asserted,
LOS will de-assert within tLD = 0 - 5μs after the appearance of a transition at the DDIx input. See
Figure 4-1.
This signal is HIGH (signal lost), when the number of data edges within a window is below a
defined threshold. The output is automatically muted when LOS is detected.
This signal is LOW (signal valid), when the number of data edges within a window is above a
defined threshold. See Table 4-4.
Table 4-4: LOS Operation
LOS
Signal
HIGH
Invalid
LOW
Valid
The LOS function is operational for all operating modes of the device.
t LA
t LD
DATA
LOS
Figure 4-1: LOS Signal Timing
The LOS detector has two major modes. In legacy mode, a simple edge-based detector is used to
monitor the received signal at the output of the data slicer. Since the incoming signal has
undergone considerable gain by this point, the legacy detector can be more susceptible to false
de-assertion of LOS for unused channels which experience significant cross-talk from adjacent
active channels.
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The new LOS detector uses a measure of both signal amplitude and duration to minimize false
detection of the impulse like signals that are characteristic of cross-talk. In this mode, the signal
is tapped off at the output of the equalizer stage, prior to the high gain buffers.
The threshold setting within the detector can be adjusted to increase or decrease its sensitivity.
Gennum recommends using the least sensitive threshold level. This provides the most margin
against false de-assertion of LOS.
Table 4-5: Suggested LOS Threshold Settings
Input Signal
Amplitude
LOS Detection
Method Select
LOS Threshold
Adjust
>250mV
0x1
0x0
200mV to 250mV
0x1
0x1
150mV to 200mV
0x1
0x2
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